ADVANCED ENGINEERING MATHEMATICS[As per Choice Based Credit System (CBCS) scheme] SEMESTER – I Subject Code 16ELD11 IA Marks 20 Number of 04 Exam Marks 80 Lecture Hours/Week Total Number of 50 Exam Hours 03 Lecture Hours CREDITS – 04 Course objectives: This course will enable students to: • Acquaint with principles of linear algebra, calculus of variations, probability theory and random process. • Apply the knowledge of linear algebra, calculus of variations, probability theory and random process in the applications of electronics and communication engineering sciences. Revised Modules Teaching Bloom’s Hours Taxonomy (RBT) Level Module -1 Linear Algebra-I Introduction to vector spaces and sub-spaces, definitions, illustrative examples and simple problems. Linearly independent and dependent vectors-definition and problems. 10 Hours L1,L2 Basis vectors, dimension of a vector space. Linear (Text 1 & transformations- definition, properties and problems. Rank- Ref. 1) Nullity theorem(without proof). Matrix form of linear transformations-Illustrative examples. Module -2 Linear Algebra-II Computation of Eigen values and Eigen vectors of real symmetric matrices-Given’s method. Orthogonal vectors and 10 Hours L1,L2 orthogonal bases. Gram-Schmidt orthogonalization process. QR (Text 1 & decomposition, singular value decomposition, least square Ref. 1) approximations. Module -3 1 Calculus of Variations Concept of functional-Eulers equation. functional dependent on first and higher order derivatives, functional on several 10 Hours L1,L2 dependent variables. Isoperimetric problems-variation (Text 2 & problems with moving boundaries. Ref. 2) Module -4 Probability Theory Review of basic probability theory. Definitions of random variables and probability distributions, probability mass and 10 Hours L1,L2 density functions, expectation, moments, central moments, (Text 3 & characteristic functions, probability generating and moment Ref. 3) generating functions-illustrations. Binomial, Poisson, Exponential, Gaussian and Rayleigh distributions-examples. Module -5 Joint probability distributions Definition and properties of CDF, PDF, PMF, conditional 10 Hours L1,L2 distributions. Expectation, covariance and correlation. (Text 3 & Independent random variables. Statement of central limit Ref. 3) theorem-Illustrative examples. Random process- Classification, stationary and ergodic random process. Auto correlation function-properties, Gaussian random process. Course Outcomes: After studying this course, students will be able to: 1. Understand vector spaces, basis, linear transformations and the process of obtaining matrix of linear transformations arising in magnification and rotation of images. 2. Apply the techniques of QR and singular value decomposition for data compression, least square approximation in solving inconsistent linear systems. 3. Utilize the concepts of functionals and their variations in the applications of communication systems, decision theory, synthesis and optimization of digital circuits. 4. Learn the idea of random variables (discrete/continuous) and probability distributions in analyzing the probability models arising in control systems and system communications. 5. Apply the idea of joint probability distributions and the role of parameter- dependent random variables in random process. 2 Statistics and Random Process“. Lay and J.. selecting one full question from each module.ac. 5th Edition. 3rd Edition. Richard Bronson: “Schaum’s Outlines of Theory and Problems of Matrix Operations”. 3.in/courses. Pearson Education Ltd.:”Differential Equations and Calculus of Variations”. • There will be 2 full questions from each module covering all the topics of the module • The students will have to answer 5 full questions.com 3 .. 2015.php?disciplineId=111 2. 2015. Kreyszig.Question paper pattern: • The question paper will have 10 full questions carrying equal marks. Elsevier Academic Press.mit. “Advanced Engineering Mathematics”. 1988. 2. Text Books: 1. McGraw-Hill. 3.McDonald: Linear Algebra and its Applications.2008. 1977.J. Childers: “Probability and Random Process with application to Signal Processing”. MIR Publications.Miller. Steven R. http://nptel.class-central.edu/courses/mathematics/ 4. 3rd Edition. Reference books: 1. http://ocw. Elsgolts. David C. Scott L.Veerarajan: “Probability. L. http://www. Wiley.2013. www. • Each full question consists of 16 marks with a maximum of four sub questions.wolfram. 2. Web links: 1. T. 2nd Edition. DonaldG. E. Tata McGraw Hill Co. 10th edition.com/subject/math(MOOCs) 3.Lay. Infer state of the art Semiconductors Memory circuits. MOSFET Scaling and Small-Geometry Effects. L2 Structure. MOS Inverters-Static Characteristics: Introduction. Revised Modules Teachin Bloom’s g Hours Taxono my (RBT) Level Module -1 MOS Transistor: The Metal Oxide Semiconductor (MOS) 10 Hours L1. Outline the comprehensive coverage of Methodologies and Design practice that are used to reduce the Power Dissipation of large scale digital circuits. Structure and Operation of MOS Transistor. Resistive-Load Inverter. Illustrate VLSI and ASIC design. Explain VLSI Design Methodologies 2. Inverters with n_Type MOSFET Load. 4. MOSFET Current-Voltage Characteristics. Learn Static and Dynamic operation principles. Module -2 4 . analysis and design of inverter circuit. 5. 3. The MOS System under External Bias. DIGITAL VLSI DESIGN [As per Choice Based Credit System (CBCS) scheme] SEMESTER –I Subject Code 16EVE12 IA Marks 20 Number 04 Exam Marks 80 Total 50 Exam Hours 03 Number of CREDITS – 04 Course objectives: This course will enable students to: 1. Design for Manufacturability: Introduction. Dynamic 10 Hours L1. 10 Hours L2. Voltage Bootstrapping. BiCMOS Logic Circuits: Introduction. Flash Memory. Latch-Up and Its Prevention. Pass Transistor Circuits. Output Circuits and L(di/dt) Noise. On-Chip Clock Generation and Distribution. Input Circuits.L2. L2. Nonvolatile Memory. Module -3 Semiconductor Memories: Introduction. L3. Switching Power Dissipation of CMOS Inverters. L4 Synchronous Dynamic Circuit Techniques. Calculation of Delay Times. 10 Hours L2. Static Random Access Memory (SRAM).MOS Inverters-Static Characteristics: CMOS Inverter. Basic Concepts and Definitions. Basic BiCMOS Circuits: Static Behavior. 5 . Design of Experiments and Performance Modeling. L3 MOS Inverters: Switching Characteristics and Interconnect Effects: Introduction. Esimation of Interconnect Parasitics. BiCMOS Applications. Basic Principles of 10 Hours L1. L3 ESD Protection. Module -5 Chip Input and Output (I/O) Circuits: Introduction. Ferroelectric Random Access Memory (FRAM). Delay-Time Definition. Process Variations. Inverter Design with Delay Constraints. Dynamic Behavior of BJTs. L3 Random Access Memory (DRAM). Calculation of Interconnect Delay. Bipolar Junction Transistor (BJT): Structure and Operation. Switching Delay in BiCMOS Logic Circuits. Module -4 Dynamic Logic Circuits: Introduction. High Performance Dynamic CMOS Circuits. Dynamic CMOS Circuit Techniques. Analyse issues of On-chip interconnect Modelling and Interconnect delay calculation. 2. 6 . Question Paper Pattern • The question paper will have 10 full questions carrying equal marks. Graduate Attributes (as per NBA): o Engineering Knowledge. o Design / development of solutions (partly). Second Edition. 1998. “Principles of CMOS VLSI Design: A System Perspective”. Second Edition. Use the Dynamic Logic circuits in state of the art VLSI chips. Clock distribution. selecting one full question from each module. Analyse the Switching Characteristics in Digital Integrated Circuits. Wayne. Pearson Education (Asia) Pvt. 2000. Third Edition. Reference Books: 1. Use Bipolar and Bi-CMOS circuits in very high speed design. students will be able to: 1. “CMOS Digital Integrated Circuits: Analysis and Design”. Neil Weste and K. and Latch phenomenon 5. • Each full question consists of 16 marks with a maximum of four sub questions. Douglas A Pucknell & Kamran Eshragian . Text Books: Sung Mo Kang & Yosuf Leblebici. 3. Ltd. Study critical issues such as ESD protection. Tata McGraw-Hill. “Basic VLSI Design” PHI 3rd Edition (original Edition – 1994). Eshragian. Wolf. o Problem Analysis. “Modern VLSI Design: System on Silicon” Prentice Hall PTR/Pearson Education. 3. Clock buffering. 2.Course outcomes: After studying this course. 4. o Interpretation of data. • There will be 2 full questions from each module covering all the topics of the module • The students will have to answer 5 full questions. Characteristics and Quality Attributes of Embedded Systems (Selected Topics from Ch -1. emulators and debugging (Selected Topics From Ch-7. 12. for different applications Revised Modules Teaching Bloom’s Hours Taxonomy (RBT) Level Module -1 Embedded System: Embedded vs General computing system. 10 Hours L1. Components in embedded system 10 Hours L1. development environment (IDE). Memory. embedded firmware development languages. L4 compilation. L2. 3 of Text 1). interrupts and exceptions. Files generated during L3. LED. Communication Interface. Module -2 Hardware Software Co-Design. a 32 bit microcontroller including memory map. application and purpose of ES. • Program ARM CORTEX M3 using the various instructions. simulators. computational models. Core of an Embedded System. RTC. Reset circuits. • Describe the hardware software co-design and firmware design approaches • Explain the architectural features of ARM CORTEX M3. Actuators. L3 WDT. ADVANCED EMBEDDED SYSTEM [As per Choice Based Credit System (CBCS) scheme] SEMESTER – I Subject Code 16EVE13 IA Marks 20 Number of 04 Exam Marks 80 Lecture Hours/Week Total Number of 50 Exam Hours 03 Lecture Hours CREDITS – 04 Course objectives: This course will enable students to: • Understand the basic hardware components and their selection method based on the characteristics and attributes of an embedded system. embedded firmware design approaches. 2. Sensors. 7 . classification. Integration and testing of Embedded Hardware and firmware. Optocoupler. L2. 13 of Text 1). Various Units in the architecture. stack operation. L2. TMH education Pvt. V. Memory Systems. Memory maps. Cortex-M3 Programming using assembly and C L1.Module -3 ARM-32 bit Microcontroller: Thumb-2 technology and applications of ARM. interface (Ch-4. interrupts and exceptions. useful instructions. "Embedded systems. L3 language. • Problem Analysis. Ltd. Peckol. students will be able to: • Understand the basic hardware components and their selection method based on the characteristics and attributes of an embedded system. • There will be 2 full questions from each module covering all the topics of the module • The students will have to answer 5 full questions. 3 of Text 2). Special 10 Hours L1.A contemporary design tool". interrupts. 2009 2. pipeline and bus 10 Hours L1. K. James K. • Design/Development of solutions Question paper pattern: • The question paper will have 10 full questions carrying equal marks. L2. • Each full question consists of 16 marks with a maximum of four sub questions. Instruction list and description. 2008 8 . 2. 2. 6 of Text 2). Systick Timer. L2. a 32 bit microcontroller including memory map. exceptions. CMSIS (Ch-7. L3 Registers. selecting one full question from each module. Module -4 Instruction Sets: Assembly basics. General Purpose Registers. Text Books: 1. reset sequence (Ch 1. • Explain the hardware software co-design and firmware design approaches. 8. • Acquire the knowledge of the architectural features of ARM CORTEX M3. "Introduction to embedded systems". Architecture of ARM Cortex M3. L3. Graduate Attributes (as per NBA) • Engineering Knowledge. Cortex M3 implementation overview. 5. John Wiley. Shibu. • Apply the knowledge gained for Programming ARM CORTEX M3 for different applications. 10 Hours Course Outcomes: After studying this course. L4 Module -5 Exceptions. 10 of Text 2). Nested Vector interrupt controller design. data correlation analysis in DSP systems. basic principles of low power design. • Explain power dissipation at all layers of design hierarchy from technology. Simulation power analysis: SPICE circuit simulation. architecture and system • Apply State-of-the art approaches to power estimation and reduction. logic. charging and 10 Hours L1. • Practice the low power techniques using current generation design style and process technology Revised Teaching Bloom’s Modules Hours Taxonomy (RBT) Level Module -1 Introduction: Need for low power VLSI chips. Module -2 9 . • Describe the various power reduction and the power estimation methods. low power figure of merits. circuit. Monte Carlo simulation. gate level logic simulation. short circuit current in CMOS leakage (Text1) current. discrete transistor modeling and analysis. Low Power VLSI Design [As per Choice Based Credit System (CBCS) scheme] SEMESTER –I Subject Code 16EVE14 IA Marks 20 Number of 04 Exam Marks 80 Lecture Hours/Week Total Number of 50 Exam Hours 03 Lecture Hours CREDITS – 04 Course objectives: This course will enable students to: • Know the basics and advanced techniques in low power design which is a hot topic in today’s market where the power plays a major role. L2 discharging capacitance. static current. architecture level analysis. (Text 1) Circuit: Transistor and gate sizing. multipliers. circuit design style. sources of power dissipation in DRAM and SRAM (Text 2). special latches and flip flops. switching activity reduction. L2. Low power arithmetic components: Introduction. L3 frequency. signal entropy. 1 . sources and reductions 10 Hours L1-L4 of power dissipation in memory subsystem. chip & package co design of clock network (Text 2). adjustable device threshold voltage Module -3 Logic: Gate reorganization.L4 Low power Architecture & Systems: Power & performance management. logic encoding. Advanced Techniques: Adiabatic computation. Module -5 Low power memory design: Introduction. adders. low power digital cell library. Architectural level estimation & synthesis (Text 2). L3 machine encoding. Zero skew Vs tolerable skew. equivalent pin ordering. Asynchronous circuits (Text 1). single driver Vs distributed buffers. signal gating. Module -4 10 Hours L1. Algorithm & Architectural Level Methodologies: Introduction. pass transistor. network restructuring and reorganization. pre-computation logic (Text 1). Algorithmic level analysis & optimization. probabilistic power analysis techniques. probability & 10 Hours L1. L2. division (Text 2). design flow. state 10 Hours L1. Low power Clock Distribution: Power dissipation in clock distribution.Probabilistic power analysis: Random logic signals. parallel architecture with voltage reduction. flow graph transformation (Text 1). 2. Jan M. “Practical Low Power Digital VLSI Design”. Kluwer Academic. “Low power digital CMOS design”. “Low-Power CMOS VLSI Circuit Design” Wiley. 2010. o Design / development of solutions (partly). Kaushik Roy.1995.Broadersen. Gary K. • There will be 2 full questions from each module covering all the topics of the module • The students will have to answer 5 full questions.P. 2000 2. Question paper pattern: • The question paper will have 10 full questions carrying equal marks. A Bellamour and M I Elmasri. “Low Power Design Methodologies” Kluwer Academic. • Perform power analysis using simulation based approaches and probabilistic analysis.Rabaey. • Make the power design a reality by making power dimension an integral part of the design process • Use practical low power design techniques and their analysis at various levels of design abstraction and analyse how these are being captured in the latest design automation environments.1995. Text Books: 1. 1998. Sharat Prasad. selecting one full question from each module. Graduate Attributes (as per NBA): o Engineering Knowledge. Massoud Pedram.W. Kluwer Academic. “ Low power VLSI CMOS circuit design”. 3. Kluwer Academic.Course outcomes: After studying this course. 1 . A. Yeap. students will be able to: • Identify the sources of power dissipation in CMOS circuits. o Problem Analysis. • Each full question consists of 16 marks with a maximum of four sub questions.Chandrasekaran and R. • Use optimization and trade-off techniques that involve power dissipation of digital circuits. o Interpretation of data. Reference Books: 1. Models. Fixed and Floating. Implementation Fabrics: ICs. Module -2 Number Basics: Unsigned and Signed Integers. Module -4 1 . Clocked Synchronous Timing Methodology Module -3 Memories: Concepts. Interconnection and Signal Integrity. 8 Hours L1. Design Methodology. Error Detection and 8 Hours L1. L2 Correction. • Inspect how effectively IC’s are embedded in package and assembled in PCB’s for different application • Design and diagnosis of processors and I/O controllers they can be used in embedded systems Revised Modules Teachi Bloom’s ng Taxonom Hours y (RBT) Level Module -1 Introduction and Methodology: Digital Systems and Embedded 8 Hours L1. Memory Types. Sequential Basics: Storage elements. DIGITAL SYSTEM DESIGN USING VERILOG [As per Choice Based Credit System (CBCS) scheme] SEMESTER – I Subject Code 16EVE151 IA Marks 20 Number of Lecture 03 Exam Marks 80 Hours/Week Total Number of Lecture 40 Exam Hours 03 Hours CREDITS – 03 Course objectives: This course will enable students to: • Understand the concepts of Verilog Language • Design the digital systems as an activity in a larger systems design context. Packaging and Circuit Boards. Real-World Circuits. • Study the design and operation of semiconductor memories frequently used in application specific digital system. L2 Systems. Counters. PLDs. L2 point Numbers. Binary representation and Circuit Elements. Sequential Data paths and Control. Second Edition by Samir Palnitkar. Verification of accelerators. selecting one full question from each module. Explore the different types of semiconductor memories and their usage for specific chip design 5. 8 Hours L2. Design & Construct the combinational circuits using discrete gates and programmable logic devices. 3. L3 and Data. 1 . Design optimization. L3 Design Methodology: Design flow. 2010. or hard or soft processor cores. Module -5 Accelerators: Concepts. • There will be 2 full questions from each module covering all the topics of the module • The students will have to answer 5 full questions. Design and synthesis of different types of processor and I/O controllers that are used in embedded system design Graduate Attributes (as per NBA): o Engineering Knowledge. using small microcontrollers. Instruction 8 Hours L2. o Design / development of solutions (partly). case study. I/O interfacing: I/O devices. I/O controllers. Design embedded systems. larger CPUs/DSPs. • Each full question consists of 16 marks with a maximum of four sub questions. Serial Transmission. 2. Question paper pattern: • The question paper will have 10 full questions carrying equal marks. Parallel Buses. I/O software. o Problem Analysis. Describe Verilog model for sequential circuits and test pattern generation 4. Course outcomes: After studying this course. “Digital Design: An Embedded Systems Approach Using VERILOG”. Ashenden.Processor Basics: Embedded Computer Organization. Interfacing with memory. Elesvier. o Interpretation of data. Reference Book: Verilog HDL: A Guide to Digital Design and Synthesis. Design for test. students will be able to: 1. Text Book: Peter J. Development milestones in 8 Hours L1. L2 microfabrication and electronic industry. 1 .L3 techniques. • Describe technologies involved in modern day electronic devices. effects of nanometerlength scale. Revised Modules Teaching Bloom’s hours Taxono my (RBT) Module -1 Introduction: Overview of nanoscience and engineering. Microscopic techniques. ordering of nanosystems (Text 1). Field ion microscopy. diffraction techniques: bulk and surface diffraction techniques (Text 1). Moores law and continued miniaturization. devices and systems. Bottom up processes methods for templating the growth of nanomaterials. Bonding between atoms. Giant molecular solids. • Explain basics of top-down and bottom-up fabrication process. Electronic conduction. Electronic properties of atoms and solids: Isolated atom. scanning probe 8 Hours L2. Periodicity of crystal lattices. • Appreciate the complexities in scaling down the electronic devices in the future. Module -2 Characterization: Classification. crystalline solids. Classification of Nanostructures. Free electron models and energy bands. NANOELECTRONICS [As per Choice Based Credit System (CBCS) scheme] SEMESTER – I Subject Code 16EVE152 IA Marks 20 Number of Lecture Hours/Week 03 Exam Marks 80 Total Number of Lecture Hours 40 Exam Hours 03 CREDITS – 03 Course objectives: This course will enable students to: • Enhance basic engineering science and technological knowledge of nanoelectronics. Fabrication methods: Top down processes. thermally annealed quantum wells. Light emission processes. 1 . quantum cascade lasers. optical memories. Inorganic semiconductor nanostructures: overview of semiconductor physics.Module -3 Characterization: spectroscopy techniques: photon. radiofrequency. quantum wires. biological tagging. characterization of semiconductor nanostructures: optical electrical and structural (Text 1). collidal quantum dots. Ion beam. electronic density of states (Text 1). ballistic carrier transport. 8 Hours L1-L3 lithography and etching. super-lattices. mass. QWIP’s. charging effects. Inter band absorption. nonlinear effects. epitaxial growth of quantum wells. Physical processes: modulation doping. surface analysis and dept 8 Hours L1-L3 profiling: electron. quantum hall effect. Quantum well width fluctuations. phonon bottleneck. intraband absorption. quantum dots. crystollography. microscopy. thermal properties. Reflectrometry. photonic structures. strain induced dots and wires. self-assembly techniques. spectroscopy (Text 2). NEMS. semiconductor nanocrystals. Module -5 Methods of measuring properties: atomic. coherence and dephasing. Techniques for property measurement: mechanical. electron. resonant tunneling. quantum confined stark effect. growth of vicinal substrates. band offsets. MEMS (Text 1). electrostatically induced dots and wires. electron. Module -4 Fabrication techniques: requirements of ideal semiconductor. magnetic. single-photon sources. cleaved-edge over growth. 8 Hours L1-L4 Applications: Injection lasers. Quantum confinement in semiconductor nanostructures: quantum wells. coulomb blockade devices. 2007. 1 . optical and electrical properties of nanomaterials. CRC press.Course outcomes: After studying this course. Ian Hamley. “Introduction to Nanotechnology”. • Design the process flow required to fabricate state of the art transistor tech nology. Text Books: 1. John Wiley. Reprint 2011. John Wiley. “Nanoscale Science and Technology”. Frank J Owens. Donald W Brenner. Graduate Attributes (as per NBA): o Engineering Knowledge. Copyright 2006. • Analyze the requirements for new materials and device structure in the futu re technologies. 2003. students will be able to: • Know the principles behind Nanoscience engineering and Nanoelectronics. Jr. • There will be 2 full questions from each module covering all the topics of the module • The students will have to answer 5 full questions. Lyshevski. “Hand Book of Nanoscience Engineering and Technology”. Reference Book: Ed William A Goddard III. selecting one full question from each module. Charles P Poole. thermal. • Know the effect of particles size on mechanical. Ed Robert Kelsall. Sergey E. Mark Geoghegan. o Problem Analysis. • Each full question consists of 16 marks with a maximum of four sub questions. Gerald J Iafrate. o Interpretation of data. • Apply the knowledge to prepare and characterize nanomaterials. o Design / development of solutions (partly). Question paper pattern: • The question paper will have 10 full questions carrying equal marks. 2. I/O cells. Logical 08 Hours L1-L3 area and logical efficiency. Xilinx LCA: XC3000 CLB. ASIC Design flow. Semi-custom and 08 Hours L1-L2 Programmable ASICs. Carry save. Data path Operators. Optimum delay and number of stages. Conditional sum. ACT 2 and ACT 3 Logic Modules. CMOS Logic: Datapath Logic Cells: Data Path Elements. ASIC cell libraries. and routing. placement. floor-planning. Revised Modules Teaching Bloom’s Hours Taxonomy (RBT)Level Module -1 Introduction to ASICs. Altera FLEX and MAX. Logical paths. Module -2 ASIC Library Design: Logical effort: Predicting Delay. • Analyse back-end physical design flow. Carry bypass. including partitioning. Adders: Carry skip. Module -3 1 . Carry select. Multiplier (Booth encoding). Actel ACT: ACT 1. Full custom. • Gain sufficient theoretical knowledge for carrying out FPGA and ASIC designs. ASIC DESIGN [As per Choice Based Credit System (CBCS) scheme] SEMESTER – I Subject Code 16EVE153 IA Marks 20 Number of Lecture Hours/Week 03 Exam Marks 80 Total Number of Lecture Hours 40 Exam Hours 03 CREDITS – 03 Course objectives: This course will enable students to: • Explain ASIC methodologies and programmable logic cells to implement a function on IC. Multi stage cells. Programmable ASIC Logic Cells: MUX as Boolean function generators. • Design CAD algorithms and explain how these concepts interact in ASIC design. Left-Edge and Area-Routing Algorithms. • There will be 2 full questions from each module covering all the topics of the module • The students will have to answer 5 full questions. Graduate Attributes (as per NBA): o Engineering Knowledge. 08 Hours L1-L4 Low-level design entry: Schematic entry: Hierarchical design. 1 . 4. data path elements. Floor 08 Hours L1-L4 planning tools. Module -4 Floor planning and placement: Goals and objectives. Placement: Goals and Objectives. Course outcomes: After studying this course. Module -5 Routing: Global Routing: Goals and objectives. Detailed Routing: Goals and objectives. Min-cut Placement algorithm. perform design entry and explain the physical design flow. I/O and Power planning and Clock planning. Design data path elements for ASIC cell libraries and compute optimum path delay. Partitioning: Goals and objectives. Global 08 Hours L1-L4 Routing Methods. CAD Tools. students will be able to: 1. Netlist screener. Iterative Partitioning Improvement. o Interpretation of data.Programmable ASIC I/O Cells: Xilinx and Altera I/O Block. Constructive Partitioning. Create floorplan including partition and routing with the use of CAD algorithms. Question paper pattern: • The question paper will have 10 full questions carrying equal marks. o Design / development of solutions (partly). Measurement of Channel Density. Describe the concepts of ASIC design methodology. KL. • Each full question consists of 16 marks with a maximum of four sub questions. 2. Iterative Placement Improvement. FM and Look Ahead algorithms. Back-annotation. logical effort and FPGA architectures. Special Routing. Analyze the design of FPGAs and ASICs suitable for specific tasks. Physical Design Flow. 3. o Problem Analysis. ASIC Construction: Physical Design. Circuit extraction and DRC. selecting one full question from each module. Channel definition. Springer. Rakesh Chadha.. 3rd edition. Addison Wesley/ Pearson education. “CMOS VLSI Design: A Circuits and Systems Perspective”. 2011. 2011. Springer. 2005. Neil H. ISBN: 978-1- 4614-4270-7.Specific Integrated Circuits” Addison- Wesley Professional. Bhasker J. Reference Books: 1. “An ASIC Low Power Primer”. 2. “VLSI Design: A Practical Guide for FPGA and ASIC Implementations”. David Harris. ISBN: 978-1-4614-1119-2.E. 1 . 3. Vikram Arkalgud Chandrasetty. and Ayan Banerjee. Weste.Text Book: Michael John Sebastian Smith. “Application . VLIW (Text 1) Architectures. Instruction pipeline design. Control flow versus 8 Hours L2. Hardware and software parallelism. Program and Network 8 Hours L2. 8 Hours L1. Performance Metrics and Measures. Data and resource (Text 1) Dependences. Program flow mechanisms. Module -3 Advanced Processors: Advanced processor technology. Instruction-set Architectures. Module -4 2 . Pipelining. Comparisons of flow mechanisms. L3. Grain Size and latency. CISC Scalar Processors. Multiprocessors and multicomputers. L2. L4 data flow. Parallel Processing Applications. L3. Demand driven (Text 1) mechanisms. Scalability Analysis and Approaches. Speedup Performance Laws. ADVANCED COMPUTER ARCHITECTURE [As per Choice Based Credit System (CBCS) scheme] SEMESTER – I Subject Code 16ELD154 IA Marks 20 Number of Lecture 03 Exam Marks 80 Hours/Week Total Number of 40 Exam Hours 03 Lecture Hours CREDITS – 03 Course objectives: This course will enable students to: • Understand the basic concepts for parallel processing • Analyze program partitioning and flow mechanisms • Apply pipelining concept for the performance evaluation • Learn the advanced processor architectures for suitable applications Revised Teaching Bloom’s Modules Hours Taxonomy (RBT) Level Module -1 Parallel Computer Models: Classification of parallel computers. L4 Properties. Multivector and SIMD computers. Module -2 Program partitioning and scheduling. Linear pipeline processor. nonlinear pipeline processor. Superscalar Processors. Principles of Scalable Performance. Data flow Architecture. Conditions of parallelism. L3 RISC Scalar Processors. 2002. (Text 1 & 2) Data flow Architecture. Reference Books: 1. Dynamic 8 Hours L2. Text Books: 1. “Computer Architecture: A quantitative approach”. L4 instruction scheduling. 2002. “Advanced computer architecture”. “Scalable Parallel Computers Architecture”. L2. 2. 2. • There will be 2 full questions from each module covering all the topics of the module • The students will have to answer 5 full questions. Pipelined and Parallel Processor Design”. Symmetric shared memory architecture.J. Narosa Publishing. 2008. Arithmetic Pipeline Design.Mechanisms for instruction pipelining.L. Course outcomes: At the end of this course. Module -5 Multithread and Dataflow Architecture: Principles of 8 Hours L1.Hennessy.A. Morgan Kauffmann feb. L3 Multithreading. distributed shared memory architecture. Kai Hwang and Zu. 2 . Branch Handling techniques. TMH.Patterson. L3. Flynn. M. 2007. Static Arithmetic pipeline. J. MGH. D. Multifunctional arithmetic pipelines. • Each full question consists of 16 marks with a maximum of four sub questions. (Text 1) branch prediction. Computer arithmetic principles. selecting one full question from each module. Kai Hwang. the students will be able to: • Understand the basic concepts for parallel processing • Analyze program partitioning and flow mechanisms • Apply pipelining concept for the performance evaluation • Learn the advanced processor architectures for suitable applications Graduating Attributes (as per NBA) • Engineering Knowledge • Problem Analysis • Design / development of solutions Question paper pattern: • The question paper will have 10 full questions carrying equal marks. Scalable and Multithreaded Architecture. “Computer Architecture. The ports are dedicated for read and write and will take one clock cycle for read or write operation 2 .1 [As per Choice Based Credit System (CBCS) scheme] SEMESTER – I Laboratory Code 16EVEL16 IA Marks 20 Number of Lecture 01Hr Tutorial (Instructions) Exam 80 Hours/Week + 02 Hours Laboratory Marks Exam 03 Hours CREDITS – 02 Course objectives: This course will enable students to: • Learn Verilog Code Programming for the design of digital circuits • Use FPGA/CPLD board and Logic Analyzer or Chipscope to verify the results • Learn Assembly language programming for different applications using ARM- Cortex M3 Kit and Keil uvision. VLSI and ES LAB .Cortex M3 Kit and Keil uvision-4 tool.4 tool.L3. • Learn C language programming for different applications using ARM. f) Design and verify a Linear feedback shift register based on a given polynomial expression g) Design and verify the following 8 bit multipliers. e) Design and verify 8 bit Ripple carry adder and Carry skip adder. Laboratory Experiments: Revised Bloom’s Taxonomy 1) Digital Design Experiments Using Verilog code and any L2.L5 Compiler. Download code to FPGA/CPLD board and verify the output using Logic Analyzer or Chipscope a) Design and verify an 8 to 3 programmable priority encoder b) Design and verify 3-bit Arbitrary Counter and repeat the given sequence c) Design and Verify BCD adder and subtractor d) Design and verify a sequential block to generate a sequence (say 11101) using appropriate FSM.L4. Also report on area delay trade-off i) Serial Multiplier ii) Parallel Multiplier h) Design and verify a parameterized FIFO i) Design and verify register file which has 32-entry 3-ports having explicit address decoder. +1 b) Write a Assembly language program to link multiple object files and link them together c) Write an Assembly language program to store data in RAM d) Write a C program to Output the “Hello World” message using UART e) Write a C program to Design a Stopwatch using interrupts Course outcomes: On the completion of this laboratory course. 2 . SUM = 10+9+8+... 3) Students are allowed to pick one experiment from the lot. • Problem Analysis.. Conduct of Practical Examination: 1) All laboratory experiments are to be included for practical examination. 4) Strictly follow the instructions as printed on the cover page of answer script for breakup of marks.. the students will be able to: • Develop Verilog Code for the design of digital circuits • Use FPGA/CPLD board and Logic Analyzer or Chipscope to verify the results • Develop Assembly language programs for different applications using ARM- Cortex M3 Kit and Keiluvision-4 tool. two questions using different tool to be set... 5) Change of experiment is allowed only once and Marks allotted to the procedure part to be made zero.. • Develop C language programs for different applications using ARM-Cortex M3 Kit and Keil uvision-4 tool Graduate Attributes (as per NBA) • Engineering Knowledge.L3..2) ARM Cortex M3 Programs: ( Programming to be done using L2.L4 Keil uvision 4 and download the program on to a M3 evaluation board such as NXP LPC1768 or ATMEL ATSAM3U) a) Write an Assembly language program to calculate the sum and display the result for the addition of first ten numbers. 2) For examination. • Design/Development of solutions.