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VISVESVARAYA TECHNOLOGICAL UNIVERSITY, BELGAUMSCHEME OF TEACHING AND EXAMINATION FOR M.Tech. VLSI Design and Embedded Systems CREDIT BASED I Semester Subject Code Name of the Subject 14ELD11 14EVE12 Advanced Mathematics Digital VLSI Design 14EVE13 14EVE14 14EVE15X 14EVE16 14EVE17 Teaching hours/week Practical / Field Work / Lecture Assignment/ Tutorials 4 2 Marks for Exam Total Marks CREDITS 50 100 150 4 Duration of Exam in Hours I.A. 3 4 2 3 50 100 150 4 Advanced Embedded Systems 4 2 3 50 100 150 4 VLSI Process Technology 4 2 3 50 100 150 4 Elective - 1 4 2 3 50 100 150 4 VLSI Design and Embedded System Lab -1 Seminar on Advanced topics from refereed journals -- 3 3 25 50 75 2 -- 3 -- 25 -- 25 1 20 16 18 300 550 850 23 Total Elective-1: 14 ELD151 14 EVE 152 14 ELD 153 Digital System Design using Verilog VLSI Design Automation Nanoelectronics 14 EVE 154 14 EVE 155 ASIC Design System Verilog VISVESVARAYA TECHNOLOGICAL UNIVERSITY, BELGAUM SCHEME OF TEACHING AND EXAMINATION FOR M.Tech. VLSI Design and Embedded Systems CREDIT BASED II Semester Subject Code Teaching hours/week Practical / Field Work / Lecture Assignment/ Tutorials Name of the Subject Marks for Duration of Exam in Hours I.A. Exam Total Marks CREDITS 4 2 3 50 100 150 4 14EVE22 Design of Analog and Mixed mode VLSI Circuits Low Power VLSI Design 4 2 3 50 100 150 4 14EVE23 VLSI Testing and Verification 4 2 3 50 100 150 4 14ELD 24 Real Time Operating Systems 4 2 3 50 100 150 4 14EVE25X Elective-2 4 2 3 50 100 150 4 3 3 25 50 75 2 14EVE21 14EVE26 VLSI Design and Embedded System Lab -2 Seminar on Advanced topics from refereed 14EVE27 journals **Project Phase-I(6 week Duration) -- 3 -- 25 -- 25 1 Total 20 16 18 300 550 850 23 14 EVE 254 14 EVE 255 CMOS RF Circuit Design SOC Design Elective-2: 14 EVE 251 14 EVE 252 14 ELD 253 VLSI for signal processing High Speed VLSI Design MEMS ** Between the II Semester and III Semester, after availing a vocation of 2 weeks. VISVESVARAYA TECHNOLOGICAL UNIVERSITY, BELGAUM SCHEME OF TEACHING AND EXAMINATION FOR M.Tech. VLSI Design and Embedded Systems CREDIT BASED III Semester: INTERNSHIP # No. of Hrs./Week Practical / Lecture Field Work I.A. Exam Total Marks CREDITS - - 25 - 25 4 - - - 75 75 12 - - 3 – 50 50 4 - - - 100 50 150 20 Subject 14EVE31 Midterm Presentation on Internship (After 8 weeks from the date of commencement) * - 14EVE32 Report on Internship (After 16 weeks from the date of commencement) 14EVE33 Evaluation and Viva-voce Total Marks for Duration of the Exam in Hours Course Code * The student shall make a midterm presentation of the activities undertaken during the first 8 weeks of internship to a panel comprising Internship Guide, a senior faculty from the department and Head of the Department. # The College shall facilitate and monitor the student internship program. The internship report of each student shall be submitted to the University. VISVESVARAYA TECHNOLOGICAL UNIVERSITY, BELGAUM SCHEME OF TEACHING AND EXAMINATION FOR M.TECH. VLSI Design and Embedded Systems CREDIT BASED IV Semester Subject Code 14EVE41 14EVE42X 14EVE43 14EVE44 14EVE45 No. of Hrs./Week Practical / Field Work / Lecture Assignment/ Tutorials Subject Marks for Duration of Exam in Hours I.A. Exam Total Marks CREDITS Synthesis and Optimization of Digital Circuits 4 2 Elective-3 4 2 Evaluation of Project Phase-I - - - 25 - 25 1 - - - 25 - 25 1 – - 3 - 100+100 200 18 8 04 09 150 400 550 28 Phase-II : Midterm evaluation of Project # Evaluation of Project Work and Viva-voce Total Grand Total (I to IV Sem.) : 2400 Marks; 94 Credits Elective-3: 14 EVE 421 14 ELD 422 14 ESP 423 Advances in VLSI Design Image and Video Processing Modern DSP 14 EVE 424 14 EVE 425 Advanced Computer Architecture Reconfigurable Computing Note: 1) Project Phase – I: 6 weeks duration shall be carried out between II and III Semesters. Candidates in consultation with the guides shall carryout literature survey / visit to Industries to finalize the topic of dissertation. 2) Project Phase – II: 16 weeks duration during III Semester. Evaluation shall be taken during the Second week of the IV Semester. Total Marks shall be 25. 3) Project Evaluation: 24 weeks duration in IV Semester. Project Work Evaluation shall be taken up at the end of the IV Semester. Project Work Evaluation and Viva-Voce Examinations shall be conducted. Total Marks shall be 250 (Phase I Evaluation: 25 Marks, Phase –II Evaluation: 25 Marks, Project Evaluation marks by Internal Examiner (guide): 50, Project Evaluation marks by External Examiner: 50, marks for external and 100 for viva-voce). Marks of Evaluation of Project: • The I.A. Marks of Project Phase – I & II shall be sent to the University along with Project Work report at the end of the Semester. 4) During the final viva, students have to submit all the reports. 5) The Project Valuation and Viva-Voce will be conducted by a committee consisting of the following: a) Head of the Department (Chairman) b) Guide c) Two Examiners appointed by the university. (Out of two external examiners at least one should be present). Richard Bronson. McGraw-Hill. Marks : 50 : 03 : 100 Matrix Theory QR EL Decomposition – Eigen values using shifted QR algorithm. .Tucker conditions and solutions Reference Books: 1.Two Phase and Big M techniques – Duality theory.Singular Value EL Decomposition .Variational problems with moving boundaries Transform Methods Laplace transform methods for one dimensional wave equation – Displacements in a string – Longitudinal vibration of a elastic bar – Fourier transform methods for one dimensional heat conduction problems in infinite and semi infinite rod.Euler’s equation – functional dependent on first and higher order derivatives – Functionals on several dependent variables – Isoperimetric problems. 1988. Non Linear Programming –Constrained extremal problems. Elliptic Equation Laplace equation – Properties of harmonic functions – Fourier transform methods for laplace equations.Pseudo inverse. of Lecture Hours / Week Total No.Least square approximations Calculus of Variations Concept of Functionals. Solution for Poisson equation by Fourier transforms method Linear and Non Linear Programming Simplex Algorithm.Advanced Mathematics Subject Code No.Dual Simplex method.Lagranges multiplier method.Kuhn. Hours Exam. "Schaum’s Outlines of Theory and Problems of Matrix Operations". of Lecture Hours : 14ELD11 : 04 : 50 IA Marks Exam. 2006. 1982. Mir.N. “Operations research . 4. 1995 6. "Introduction to partial differential equations". Prentice – Hall of India.An introduction".. 1992. "Higher Engineering Mathematics". Sneddon. 1977. 5. Venkataraman M K. K. Co. "Elements of Partial differential equations".I. Dover Publications. L. 3. Sankara Rao. Elsgolts. "Differential Equations and Calculus of Variations". Taha H A.. .2. National Pub. McMilan Publishing co.. High Performance Dynamic CMOS Circuits. Worst-Case Analysis. Output Circuits and L(di/dt) Noise. MOS Inverters: Switching Characteristics and Interconnect Effects: Introduction. MOSFET Current-Voltage Characteristics. Dynamic Random Access Memory (DRAM). Resistive-Load Inverter. Inverter Design with Delay Constraints. Bipolar Junction Transistor (BJT): Structure and Operation. Estimation and Optimization of Switching Acivity. Low-Power Design Through Voltage Scaling. Performance Variability Minimization. of Lecture Hours /week : 04 Total no. Dynamic CMOS Circuit Techniques.Digital VLSI Design Subject Code : 14EVE12 No. Parametric Yield Maximization. Semiconductor Memories: Introduction. Inverters with n_Type MOSFET Load. On-Chip Clock Generation and Distribution. BiCMOS Logic Circuits: Introduction. Input Circuits. Design for Manufacturability : Introduction. Overview of Power Consumption. Reduction of Switched Capacitance. Switching Delay in BiCMOS Logic Circuits. BiCMOS Applications. . Dynamic Behavior of BJTs. MOS Inverters: Static Characteristics: Introduction. Latch-Up and Its Prevention. Basic Concepts and Definitions. Design of Experiments and Performance Modelling. Basic BiCMOS Circuits: Static Behavior. Esimation of Interconnect Parasitics. Calculation of Delay Times. Process Variations. Ferroelectric Random Access Memory (FRAM). Parametric Yield Esimation. of Lecture Hours : 50 IA Marks : 50 Exam Hours : 03 Exam Marks : 100 MOS Transistor: The Metal Oxide Semiconductor (MOS) Structure. Voltage Bootstrapping. Structure and Operation of MOS Transistor. Dynamic Logic Circuits : Introduction. Flash Memory. MOSFET Scaling and Small-Geometry Effects. Switching Power Dissipation of CMOS Inverters. Chip Input and Output ( I/O ) Circuits: Introduction. Static Random Access Memory (SRAM). ESD Protection. Adiabatic Logic Circuits. CMOS Inverter. Nonvolatile Memory. Low-Power CMOS Logic Circuits: Introduction. Basic Principles of Pass Transistor Circuits. Calculation of Interconnect Delay. Synchronous Dynamic Circuit Techniques. The MOS System under External Bias. Delay-Time Definition. Pearson Education (Asia) Pvt. . Neil Weste and K. “CMOS Digital Integrated Circuits: Analysis and Design”. Tata McGraw-Hill. Second Edition.Reference Books: 1. Third Edition. Ltd. Eshragian. 2. “Principles of CMOS VLSI Design: A System Perspective”. 2000. Sung Mo Kang & Yosuf Leblebici. . Design Rules check.. of Lecture Hours : 14EVE13 : 04 : 50 IA Marks : 50 Exam Hours : 03 Exam Marks : 100 Typical Embedded System : Core of the Embedded System. Other System Components. Sensors and Actuators. Debug Architecture. Types of Files Generated on Cross compilation. Multiprocessing and Multitasking. Interrupt behavior of ARM Cortex M3. Bill of materials. Program Counter. Disassembler/ELDompiler. Tasks. Target Hardware Debugging. Exceptions Programming. ARM -32 bit Microcontroller family. Nested Vector Interrupt Controller. How to Use EDA Tool.Advanced Embedded Systems Subject Code No. port. Link Register. Emulators and Debugging. Communication Interface. Simulators. Process and Threads. PCB Layout Design – Building blocks. Special Register. Introduction to Unified Modeling Language. Device Drivers. Embedded Hardware Design and Development :EDA Tools. Component placement. creating part numbers. Characteristics and Quality Attributes of Embedded Systems: Hardware Software Co-Design and Program Modeling: Fundamental Issues in Hardware Software Co-Design. Netlist creation . junction. Processes and Scheduling: Putting them altogether. Hardware Software Trade-offs. Types of OS. Computational Models in Embedded Design. Threads. Task Scheduling. Task Communication. Schematic Design – Place wire. Memory Protection. Bus . Embedded Firmware Development Languages Real-Time Operating System (RTOS) based Embedded System Design: Operating System Basics. How to Choose an RTOS The Embedded System Development Environment: The Integrated Development Environment (IDE). Memory. PCB track routing. Advanced Programming Features. Task Synchronization. Embedded Firmware. Architecture of ARM Cortex M3 –General Purpose Registers. Stack Pointer. Embedded Firmware Design and Development: Embedded Firmware Design Approaches. of Lecture Hours /week Total no. Boundary Scan. 3. 2009 2. John Weily. (Elsevier). Tata McGraw Hill Education Private Limited. “The Definitive Guide to the ARM Cortex-M3”. Shibu K V. James K Peckol. 2008.Reference Books: 1. Newnes. . “Introduction to Embedded Systems”. Joseph Yiu. “Embedded Systems – A contemporary Design Tool”. 2008. Feature-Size Control and Anisotropic Etch Mechanisms. Fundamental Considerations for IC Processing. Metallization Applications. Silicon Nitride. Second Edition. Second Edition. Deposition Processes. Epitaxy: Introduction. of Lecture Hours : 14EVE14 : 04 : 50 IA Marks : 50 Exam Hours : 03 Exam Marks : 100 Crystal Growth and Wafer Preparation: Introduction. X-ray Lithography. Epitaxial Evaluation. Plasma Properties. John Wiley Inc. Ghandhi. Patterning. McGraw-Hill. Process Considerations. Silicon on Insulators. Implantation Equipment. New Role of Metallization. Physical Vapor Deposition. Metallization Choices. Specific Etch Processes. Optical Lithography. Silicon Shaping. "VLSI Fabrication Principles". VLSI Process Integration: Introduction. Sze. IC Fabrication. Reactive Plasma-Etching Techniques and Equipment. PlasmaAssisted Depositions. “VLSI Technology”. Metallization: Introduction. MOS Memory IC Technology. 2. Reference Books: 1. Packaging Design Considerations.. Molecular Beam Epitaxy. S. Lithography: Introduction. S. Electron Lithography. 1994. . NMOS IC technology.VLSI Process Technology Subject Code No. Range Theory. Ion Lithography. Package Types. Electronic-Grade Silicon. Czochralski Crystal Growing. High-Energy Implantation. Shallow Junctions. Other Materials. Annealing. Silicon Dioxide. CMOS IC Technology. Dielectric and Polysilicon Film Deposition: Introduction. Reactive Plasma Etching: Introduction. M. Packaging of VLSI Devices: Introduction. Other Properties of Etch Processes. Vapour-Phase Epitaxy. Metallization Problems. of Lecture Hours /week Total no. New York. Ion Implantation: Introduction. Bipolar IC Technology. Polysilicon.K. Combinational Components and Circuits. Design Methodology: Design flow. Binary Coding. Elesvier. Verification of accelerators. Real-World Circuits. Fixed and Floating-point Numbers.Digital System Design Using Verilog Subject Code : 14 ELD151 No. Parallel Buses. of Lecture Hours /week : 04 Total no. Sequential Basics: Storage elements. Instruction and Data. Ashenden. Memory Types. Verification of Combinational Circuits. Packaging and Circuit Boards. Models. Implementation Fabrics: ICs. Clocked Synchronous Timing Methodology. Serial Transmission. Design Methodology. “Digital Design: An Embedded Ssytems Approach Using VERILOG”. Memories: Concepts. Processor Basics: Embedded Computer Organization. PLDs. I/O software. Interfacing with memory. Error Detection and Correction. Peter J. Design for test. Counters. Interconnection and Signal Integrity. 2010. Combinational Basics: Boolean Functions and Boolean Algebra. . REFERENCE BOOKS: 1. case study. Binary representation and Circuit Elements. Design optimization. I/O controllers. I/O interfacing: I/O devices. Accelerators: Concepts. of Lecture Hours : 50 IA Marks : 50 Exam Hours : 03 Exam Marks : 100 Introduction and Methodology: Digital Systems and Embedded Systems. Sequential Datapaths and Control. Number Basics: Unsigned and Signed Integers. Maze routing algorithm. VB Script. and switchbox routing algorithms. of Lecture Hours : 50 IA Marks : 50 Exam Hours : 03 Exam Marks : 100 Logic Synthesis & Verification: Introduction to combinational logic synthesis. Tied Variables. KAP. 2002. classification of global routing algorithms. General & channel pin assignment Global Routing: Problem formulation. Christophn Meinel & Thorsten Theobold. Rolf Drechsheler : “Evolutionary Algorithm for VLSI”. VLSI Automation Algorithms: Partitioning: problem formulation. Naveed Shervani. Second edition 4. 3rd Edn. simulated annealing & evolution. Schwartz Tom Phoenix. two layer channel routing algorithms. simulation base placement algorithms. “Algorithm and Data Structures for VLSI Design”. Oreilly Publications. classification of routing algorithms. other placement algorithms. 2. Floor Planning & Pin Assignment: problem formulation. constrained & unconstrained via minimization Scripting Languages : Overview of Scripting Languages – PERL. Objects. Trimburger. classification of partitioning algorithms. PERL: Operators. Randal L. Group migration algorithms. constraint based floor planning. line probe algorithm. Hardware models for High-level synthesis. Kluwer Academic publisher.VLSI Design Automation Subject Code : 14EVE152 No. Inter process Communication Threads. Second edition. 2000 . Placement. Binary Decision Diagram.. Java Script. of Lecture Hours /week : 04 Total no. “Learning PERL”. floor planning algorithms for mixed block & cell design. Modules. other partitioning algorithms. ILP based approaches Detailed Routing: problem formulation. Over The Cell Routing & Via Minimization: two layers over the cell routers. CGI. 3. Kluwer Academic Publisher. three layer channel routing algorithms. Steiner Tree based algorithms. 2002 5. Compilation & Line Interfacing REFERENCE BOOKS: 1. Data Structures. single layer routing algorithms. “Introduction to CAD for VLSI”. “Algorithms for VLSI physical design Automation”. Statements Pattern Matching etc. “PERL Cookbook”. Nathan Torkington. 3rd Edn. Edn.2000 .. Oreilly Publications. John Orwant. 3rd 7. Oreilly Publications. Tom Christiansen. Larry Wall.6. 2000. 8. “Programming PERL”. Tom Christiansen. NanoElectronics Subject Code : 14ELD153 No. surface. Light emission processes. Electronic properties of atoms and solids: Isolated atom. electrostatically induced dots and wires. strain induced dots and wires. semiconducting nanoparticles. Bottom up processes methods for templating the growth of nanomaterials. fuelcells. growth of vicinal substrates. radiofrequency. phonon bottleneck. thermolysis. Techniques for property measurement: mechanical.spectroscopy. Classification of Nanostructures. charging effects.. Microscopic techniques. nonlinear effects.Self assembling nanostructured . Development milestones in microfabrication and electronic industry. sensors. lithography and etching. quantum wires.microscopy. effects of nanometerlength scale. rare gas and molecularclusters. Physical processes: modulation doping. intraband absorption. Fabrication methods: Top down processes. Electronic conduction. Inorganic semiconductor nanostructures: overview of semiconductor physics. magnetic. ballistic carrier transport. Properties of nanoparticles: metalnano clusters. self-assembly techniques. Characterization: Classification. electron. electron. coherence and dephasing. characterization of semiconductor nanostructures: optical electrical and structural. cleaved edgeover growth. pulsed laser methods) Carbon nanostructures and its applications(field emission and shielding. thermal properties. Quantum well width fluctuations. diffraction techniques: bulk. quantum hall effect. Methods of measuring properties:structure:atomic. Inter band absorption. ordering of nanosystems. super-lattices. thermally annealed quantum wells. mass. crystalline solids.crystallography. resonanttunneling. Giantmolecular solids. epitaxial growth of quantum wells. Field ion microscopy. band offsets. Fabrication techniques: requirements of ideal semiconductor. collidal quantum dots. Moores law and continued miniaturization. Reflectrometry. quantum dots. semiconductor nanocrystals. electronicdensity of states. chemical. catalysis). computers. Quantum confinement in semiconductor nanostructures: quantumwells. Ion beam. methods of synthesis(RF. spectroscopy techniques: photon. Bonding between atoms. of Lecture Hours : 50 IA Marks : 50 Exam Hours : 03 Exam Marks : 100 Introduction: Overview of nanoscience and engineering. surface analysis and dept profiling: electron. quantumconfined stark effect. scanning probe techniques. of Lecture Hours /week : 04 Total no. Free electron models and energy bands. Periodicity of crystal lattices. nanomagnetism intechnology. Ed William A Goddard III. NEMS. liquid crystal mesophases. template dnanostructures. quantumcascadelasers. coulomb blockade devices. opticalmemories.Gerald J Lafrate.2007. principles of self assembly. Applications: Injectionlasers. “Introduction to Nanotechnology” . photonic structures. “ Hand Book of Nanoscience Engineering and Technology” .Donald W Brenner. Reference Books: 1. QWIP’s. singlephotonsources. 3. biologicaltagging. Charles P Poole. Nanomagnetic materials and devices: magnetism.CRC press. “ Nanoscale science and technology” . magnetoresistance.MarkGeoghegan. methods to prepare and pattern nanoparticles. materials.2003 .Frank J owens. MEMS.copyright 2006.molecular materials and devices: building blocks.Reprint 2011. 2.John wiley.Sergey EdwardLyshevski. challenges facing nanomagnetism.Jr.John wiley and sons.IanHamley. Ed Robert Kelsall. CAD Tools. optimum delay. ASIC I/O cell. SIC cell libraries. Estimating ASIC size. iterative placement improvement. Data Logic Cells: Data Path Elements. 1994. vectored instances and buses. FPGA design flow. an introduction to CFI designs representation. Low-Level Design Entry: Schematic Entry: Hierarchical design. Prentice Hall. Back annotation. Nets. Cell Compilers ASIC Library Design: Logical effort: practicing delay.“Application . Schematic. clock planning. The cell library. Names.Specific Integrated Circuits” – Pearson Education.S . Icons & Symbols. I/O and power planning. multi stage cells. of Lecture Hours /week : 04 Total no. Netlist.Smith. PLA Tools. . Reference Books: 1. .J. Physical Design flow global Routing. placement algorithms. Programmable ASIC: programmable ASIC logic cell. YannisTsividis. 2. Half gate ASIC. Introduction to Synthesis and Simulation. Semi custom ASICS. structured get array. Detail Routing. System Partitioning. of stages. ASIC Construction Floor Planning and Placement And Routing: Physical Design. Multiplier. Floor planning tools. I/O cell.France. screener. Arithmetic Operator. Special Routing. M. Time driven placement methods. Channel less gate array. schematic entry for ASIC’S. Local Routing. optimum no. 2003. Channelled gate array. “Design of Analog-Digital VLSICircuits for Telecommunication and signal processing”. Edit in place attributes. Circuit Extraction and DRC.ASIC Design Subject Code : 14EVE154 No. partitioning methods. Standard Cell based ASIC. Adders. Gate array based ASIC. Programmable logic device. logical area and logical efficiency logical paths. of Lecture Hours : 50 IA Marks : 50 Exam Hours : 03 Exam Marks : 100 Note: All Designs Will Be Based On VHDL Introduction: Full Custom with ASIC. library cell design. connections. A Brief Introduction to Low Level Design Language: an introduction to EDIF. Jose E. “Analog VLSI Design . 1998. Lan. “Analog VLSI Signal andInformation Processing”.3.NMOSand CMOS”. McGraw Hill. Mohammed Ismail and Terri Fiez. C. MalcolmR.Haskard. 4. May. Prentice Hall. 1994 . systemverilog enhancements to tasks and functions. directed vs random testing. random sequence and examples. generic interfaces. (Reference 1) System Verilog operators. random case. Packed and Unpacked Arrays. program blocks. enum. local and protected keywords. how interfaces work. Testbench . randomize-randomizing class variables. $unit and $root. program block interaction with modules. mailboxes and methods. of Lecture Hours : 50 Exam Marks Basics of Verification: Difference between ASIC verification and ASIC testing. queue methods. static and dynamic type casting.System Verilog Subject Code : 14 EVE155 IA Marks No. Packages. interface mode ports. Importance of hardware verification languages and methodologies. struct data type. foreach loop. (Reference 1) Program block: Fundamental testbench construction. jumps. ‘time scale. requirements of good interface. systemverilog timeunit and time precision (Reference 1) Structs. rand and randc class data types. overriding class methods. functions: loops and jumps in system verilog. strings. extending class methods. built-in-randomization methods. introduction to different always blocks. : 50 : 03 : 100 Layered Organization of Testbenches. Unions and packed unions. associative arrays and methods. Random number generation. bounded and unbounded mailboxes. loops. Testbenches. Verification basics. enhanced literal numbers syntax. queues and concatenation operations. interfaces vs records. class extension and inheritance. semaphores and methods. object handles. interface constructs. class declaration. class object construction. Unions. typedefs. of Lecture Hours /week : 04 Exam Hours Total no. (Reference1) Interfaces: Interface overview. array indexing. Type parameters. constrained random variables. final blocks. class members and methods. class handles. (Reference website/Verilog Books / SystemVerilog Methodologies ) System Verilog data types and typedefs: System Verilog data types. chaining new() constructors. systemverilog priority and unique modifiers for case and if statements. super and this keywords. user defined constructors. Semaphores and Mailboxes: Structs and its assignments. 4-state and 2-state types. (Reference 1) Class and Randomization: Systemverilog class basics. packed and unpacked arrays. dynamic arrays and methods. structs and packed structs. why to use virtual class. Assertion severity tasks. pure virtual methods. assert and cover properties and labels. 3 rd edition. Vacuous success. passing type parameters. Virtual class. constraint distribution and set membership. system Verilog assertion types. 2. coverage capabilities. immediate assertions. external constraints. sequences. VijayaRaghavan. assertion and coverage example of an FSM design. assertion benefits.stimulus/Verification vector timing strategies. virtual class methods and restrictions. pure constraints. Springer publications. “ Systemverilog for Design”. covergroups. “ SystemVerilog for Verification: A guide to learning the Testbench language features”. Methods and interfaces: Randomization constraints. (Reference 1) Constrained Random variables. clocking skews. clocking block scheduling. virtual interfaces. Sutherland. coverpoints. polymorphism using virtual methods. (Reference 1) System Verilog assertions: Assertion definition. “SystemVerilog Assertions”. property styles. (Reference 3) References: 1. constraint distribution operators. Springer publications . fork-join processes. covergroup options. Christian B Spear. Springer publications. simple and multi-statement constraints. coverpoint bins and labels. (Reference 1) Clocking: Clocking blocks. System Verilog assertion system functions. overlapping and non-overlapping implications. concurrent assertions. cross coverage. edge testing functions. Coverage. 2005 3. Flip flop -RS. of Lecture Hours : 42 IA Marks : 50 Exam Hours : 03 Exam Marks : 50 VLSI Digital Design ASIC-Digital Design Flow 1. T 4. JK. observe the waveform and synthesize the code with technological library(constraints to be given). 1.Aninverter. Write Verilog code for the design of 8-bit i.VLSI Design and Embedded System Lab -1 Subject Code : 14EVE16 No.Basic/universal gates 3.Carry Skip Adder iv. of Lecture Hours /week : 03 Total no. Do the initial timing verification with gate level simulation. Write Verilog Code for the following circuits and their Test Bench for verification.Buffer and Transmission gate 2.BCD Adder & Subtracter . D. Down load the programs on FPGA/CPLD boards and performance testing may be done using pattern generator (32 channels and logic analyzer )/Chipscope pro apart from verification by simulation with any of the front end tools 1. MS. Carry Ripple Adder ii.4-bit counter [Synchronous & Asynchronous counter] FPGA DIGITAL DESIGN VLSI Front End Design programs: Programming can be done using any complier. Carry LookAhead adder iii.Serial & Parallel adder 5. iii. 7. The system is ready to accept new call request when the receiver is placed on the hook. Note: Implementing the above designs on Xilinx/Altera/Cypress/equivalent based FPGA/CPLD kits Embedded Systems: 1.2. 5. vii. .3. Write Verilog code for 4/8-bit i. to continue the call.Universal Shift Register 4. Design a coin operated public Telephone unit using Mealy FSM model with following operations i.Familiarize the different entities for the circuit diagram design. Design a Mealy and Moore Sequence Detector using Verilog to detect Sequence.5.6. If line is busy. Array Multiplication (Signed and Unsigned) ii. Write Verilog Code for 3-bit Arbitary Counter to generate 0. Eg 11101 (with and without overlap) any sequence can be specified 6. If user doesn't insert the coin within 60 seconds the call should be terminated. Write Verilog Code for 8-bit i. If line is through. 2. ii.Use any EDA (Electronic Design Automation) tool to learn the Embedded Hardware Design and for PCB design. the call is allowed for 60 seconds at the 45th second prompt another 1 Rupee coin to be inserted. Magnitude Comparator ii.Parity Generator iv. v.1. The calling process is initiated by lifting the receiver. Design a FIFO and LIFO buffers in Verilog and Verify its Operation. Insert 1 Rupee Coin to make a call. vi. Booth Multiplication (Radix-4) 3. LFSR iii.2.7 and repeats. placing the receiver on hook should return a coin iv. The FSM goes 'out of order' state when there is a Line Fault. Write a Assembly language program to link Multiple object files and link them together.. .. Write a SVC handler in C. Write an Assembly Language Program for locking a Mutex.. component placement. 1.+1 2. 8. Write a Assembly language program to store data in RAM. building blocks.. The C handler can then use this to extract the stacked PC location and the stacked register values.. Write a C program to Output the "Hello World" message using UART. 4. ARM-CORTEX M3 [Programming to be done using Keiluvision 4 and download the program on to a M3 evaluation board such as NXP LPC1768 or ATMEL ATSAM3U]. Write a C program to Design a Stopwatch using interrupts. 6. Write an Assembly language program to calculate 10+9+8+.Familiarize with the layout design tool. 3. routings.. 5.Write an Exception vector table in C 7.. design rule checking etc.3. Use the wrapper code to extract the correct stack frame starting location.. Charge pump PLL. Cascade stage and Difference pair. “Design of Analog CMOS Integrated Circuits”. VCO. Noise in Op Amps. Slew rate. Differential pair with MOS loads. Bandgap Refernces and Switched capacitor Circuits: General Considerations. Current Steering DAC. current source load. divide connected load. . CS stage with source degeneration. Common gate stage. Cyclic DAC. Frequency response of CS stage: source follower. Non-ideal effects in PLL. Supply Independent biasing. source follower. Behzad Razavi. 2007. common-gate stage.G stage. Two Stage OP-Amp. Pipeline ADC. triode load. Gain boosting. source follower. Successive Approximation ADC. Oscillators and Phase Locked Loops: Ring Oscillators. Constant Gm Biasing. Data Converter Architecturres: DAC & ADC Specifications. Delay locked loops and applications. Reference Book: 1. Common Mode Feedback. Charge Scaling DAC. choice of device models. TMH. Pipeline DAC. R-2R Ladder Network. Integrating ADC. Basic current mirrors. Switched Capacitor Amplifiers. Single stage Amplifier: CS stage with resistance load. differential pair. Cascade mirrors. PTAT Current Generation. of Lecture Hours /week : 04 Total no. MOS device models. MOS I/V Characteristics. active current mirrors. second order effects. Mathematical Model of VCO. C. Flash ADC. Operational Amplifiers: One Stage OP-Amp. of Lecture Hours : 50 IA Marks : 50 Exam Hours : 03 Exam Marks : 100 Basic MOS Device Physics: General considerations. cascade stage. LC Oscillators. cascade stage. Differential Amplifiers & Current Mirrors: Basic difference pair. common mode response. Sampling Switches. Power Supply Rejection. Simple PLL. Resistor String DAC.Design of Analog and Mixed Mode VLSI Circuits Subject Code : 14 EVE21 No. Noise in CS stage. Gilbert cell. low power digital cells library. probabilistic power analysis techniques. pre-computation logic. parallel architecture with voltage reduction. Physics of power dissipation in CMOS devices. state machine encoding. Impact of technology Scaling. KAP. Power estimation. “Practical Low Power Digital VLSI Design”. Probabilistic power analysis: Random logic signals. design flow. high capacitance nodes. low power arithmetic components. capacitive power estimation. 2002 . Algorithmic level analysis & optimization. Gary K. Sources of power dissipation on Digital Integrated circuits. probability & frequency. single driver Vs distributed buffers. of Lecture Hours : 50 IA Marks : 50 Exam Hours : 03 Exam Marks : 100 Introduction: Need for low power VLSI chips. 2000 2. Emerging Low power approaches. Reference Books: 1. gate level logic simulation. “Low-Power CMOS VLSI Circuit Design” Wiley. low power memory design. architecture level analysis. Low Power Design Circuit level: Power consumption in circuits. chip & package co design of clock network. Architectural level estimation & synthesis. Kaushik Roy. logic encoding. signal gating. flow graph transformation. Zero skew Vs tolerable skew. Low power Clock Distribution: Power dissipation in clock distribution. static state power. Sharat Prasad. switching activity reduction. Simulation Power analysis: SPICE circuit simulators.Low Power VLSI Design Subject Code : 14 EVE22 No. data correlation analysis in DSP systems. Technology & Device innovation. Logic level: Gate reorganization. Device & Technology Impact on Low Power: Dynamic dissipation in CMOS. Low power Architecture & Systems: Power & performance management. Transistor sizing & gate oxide thickness. of Lecture Hours /week : 04 Total no. Algorithm & Architectural Level Methodologies: Introduction. signal entropy. Flip Flops & Latches design. Yeap. Monte Carlo simulation. gate level capacitance estimation. 3. Pedram. “Low Power Design Methodologies” Kluwer Academic. 1997 . Rabaey. Temporary Faults. verifying responses. Modeling of Faults. Design of Dignosable Sequential Circuits. Functional verification. BIST Techniques for Ram Chips. of Lecture Hours /week Total no. Boundry Scan. Role of Testing. of Lecture Hours : 14 EVE23 : 04 : 50 IA Marks : 50 Exam Hours : 03 Exam Marks : 100 Introduction to Testing: Testing Philosophy. Test Generation and BIST for Embedded RAMs. verifying strategies. system level verification. Simulators: Stimulus and response. linting verilog source code. Output Response Analysis.[Ref4-Chapter2] The verification plan: The role of verification plan: specifying the verification plan. ASIC and FPGA verification. Importance of Design Verification: What is verification? What is attest bench? The importance of verification. BIST Architectures. The Scan-Path Technique for Testable Sequential Circuit Design. reusable components verification. cycle based simulation. Ad Hoc Design Rules for Improving Testability. Levels of verification: unit level verification. CrossCheck. board level verification. Circular BIST. linting OpenVera and esource code. Detection of Pattern Sensitive Faults. Level-Sensitive Scan Design. Co-simulators. Equivalence checking. Test Algorithms for RAMs. Test Generation Techniques for Combinational Circuits. Event based simulation.Chapter1] Verification Tools: Linting tools: Limitations of linting tools. defining the first success. Detection of Multiple Fauls in Combinational Logic Circuits. [Ref4-Chapter3] . Random Access Scan Technique. Built-In Self Test: Test Pattern Generation for BIST.VLSI Testing and Verification Subject Code No. Partial Scan. Faults in Digital Circuits: Failures and Faults. waveform viewers. Reconvergence model. Testable Memory Design: RAM Fault Models.[Ref4. Formal verification. code reviews. verification intellectual property: hardware modelers. linting VHDL source code. Design of Testable Sequential Circuits: Controllability and Observability. Testable Sequential Circuit Design Using Nonscan Techniques. Model checking. Digital and Analog VLSI Testing. VLSI Technology Trends Affecting Testing. Test Generation for Combinational Logic Circuits: Fault Diagnosis of Digital Circuits. Academic Press 2. Abramovici. Limitations of STA. Cross talk and noise. K.RakeshChadha . 2. crosstalk delayanalysis. http://www. 7. critical path analysis.2003 5. Breuer and A.Static Timing Verification: Concept of static timing analysis. clock domains. [Ref5 Chapter 1. 2nd edition .“Static Timing Analysis for Nanometer Designs” A practical approach. slew of a wave form. Antenna. Kulwer Publications.D. timing verification [Ref6 Chapter 8] Reference Books: 1. PeterPaterson. “Writing testbenches: functional verification of HDL models”. "Digital Systems and Testable Design". Agrawal. M. Lala.L. 3. Friedman. PrakashRashinkar.psu.html . Min and Max timing paths. Springer publications 6.Leena Singh “System on a Chip Verification”. 3. 4. Parasitic extraction. M. Memory and Mixed-Signal VLSI Circuits”. Timing models.cse. Bushnell and V. falsepaths. JanickBergeron. Kluwar Academic Publishers.D. Crosstalk and Noise: Cross talk glitch analysis. Skew between the signals.Kluwer Academic Publishers. 8] Physical Design Verification: Layout rule checks and electrical rule checks. Jaico Publishing House. M.edu/~vijay/verify/instructors. operating conditions. P. “Essentials of Electronic Testing for Digital.A. 2002. Timing arcs and unateness. JayaramBhasker. “Digital Circuit Testing and Testability”. of Lecture Hours /week : 04 Total no.Real Time Operating Systems Subject Code : 14 ELD24 No. I/O Resources: Worst-case Execution time. Software application components. Efficiency. A brief history of Embedded Systems. Checking return codes. Dynamic priority policies. Application-level debugging. Cengage Learning India Edition. Performance Tuning: Basic concepts of drill-down tuning. of Lecture Hours : 50 IA Marks : 50 Exam Hours : 03 Exam Marks : 100 Introduction to Real-Time Embedded Systems: Brief history of Real Time Systems. ECC Memory. “Real-Time Embedded Systems and Components”. QoS. Embedded System Components: Firmware components. Similarities and differences. Memory: Physical hierarchy. Single-step debugging. Test access ports. Building performance monitoring into software. Feasibility. Debugging Components: Execptions assert. Rate Monotonic least upper bound. Design tradeoffs. Critical sections to protect shared resources. Preemptive Fixed Priority Scheduling Policies. Hierarchical applications for Fail-safe design. kernel scheduler traces. Available software. Real-Time Service Utility. Execution efficiency. Alternatives to rate monotonic policy. Design of RTOS – PIC microcontroller. Shared Memory. Thread Safe Reentrant Functions. Real-Time OS. Deadlock and livestock. Trace ports. Multi-resource Services: Blocking. . (Chap 13 of book Myke Predko) Reference Books: 1. Reliability. System Resources: Resource Analysis. and Call frequency. priority inversion Soft Real-Time Services: Missed Deadlines. Scheduling Classes. Sam Siewert. Path length. Scheduler Concepts. Intermediate I/O. Mixed hard and soft real-time services. Necessary and Sufficient feasibility. RTOS system software mechanisms. Capacity and allocation. hardware – supported profiling and tracing. Power-On self test and diagnostics. 2007. The Cyclic Executive. Deadline – Monotonic Policy. High availability and Reliability Design: Reliability and Availability. Flash file systems. Reliable software. External test equipment. I/O Architecture. Processing: Preemptive Fixed-Priority Policy. Fundamental optimizations. 3rd Ed. 2008. Jhon Wiley. Dreamtech Software Team. 3. India Pvt. “Programming and Customizing the PIC microcontroller”. 2008. TMH. “Programming for Embedded Systems”. . Ltd.2. Myke Predko.. cyclic Convolution Design of fast convolution Algorithm by Inspection Pipelined and Parallel recursive and adaptive filter: Pipeline Interleaving in Digital Filter. Critical path. Unfolding And Retiming. Iteration Bounds: Data flow graph Representations. Design and implementation ". " VLSI and Modern Signal Processing ". Combined pipelining and parallel processing for IIR Filter. France.Y. Reference Books: 1. Representations Of DSP Algorithms.Digital VLSI Circuits for Telecommunication and Signal Processing ". KeshabK. Prentice Hall. T. Inter Science. " Analog VLSI Signal and Information Processing ". of Lecture Hours : 14 EVE251 : 04 : 50 IA Marks : 50 Exam Hours : 03 Exam Marks : 100 Introduction to DSP systems: Typical DSP Algorithms. Prentice Hall. Systolic Design for space representation containing Delays. White House. Higher order IIR digital Filter. " VLSI Digital Signal Processing systems. Iteration Bound of multi rate data flow graphs. 1999. Properties Of Unfolding. 3. parallel processing. of Lecture Hours /week Total no. Mohammed Isamail and Terri Fiez.J. Kung. Retiming Techniques. Unfolding An Algorithm for Unfolding. Retiming: Definition and Properties. loop bound and Iteration bound.Parthi. Mc Graw-Hill. Kailath. Selection of Scheduling Vector. 1985. parallel processing for IIR filter. Application of Unfolding Systolic architecture design: systolic array design Methodology. Jose E. S. pipelined Adaptive digital filter. " Design of Analog . DSP Application Demands And Scaled CMOS Technologies. 2.VLSI for Signal Processing Subject Code No. first order IIR digital Filter. Wiley. Fast convolution–Cook-Toom Algorithm. 1994 . 4. Pipelining and parallel processing. FIR systolic array. H. Iterated convolution. Low power IIR Filter Design Using Pipe lining and parallel processing.1994. Matrix-Matrix Multiplication and 2D systolic Array Design. YannisTsividis. Solving Systems of Inequalities. Winograd Algorithm. Algorithms for Computing Iteration Bound. Pipelining and parallel processing for low power. pipelining of FIR Digital Filters. 1998. simultaneous bi-directional signaling terminations. Timing convention and synchronisation: Timing fundamentals. crosstalk and inter symbol interference. IR drops. clock distribution. clock distribution. DCVS Logic. Non-Clocked Pass Gate Families. local power regulation. clock oscillators and clock jitter . controlling crosstalk in clock lines. transmitter and receiver circuits. pipeline timing. “Digital Systems Engineering”. driving lossy LC lines. Dally & John W. speed and power. power supply noise. Latched Domino Structures. open loop timing. signaling over RC interconnect. level sensitive clocking. timing properties of clocked storage elements. Cambridge University Press. transmission lines. lossy RLC transmission lines and special transmission lines. On-chip bypass capacitors and symbiotic bypass capacitors. Race Free Latches for Pre-charged Logic Asynchronous Latch Techniques Reference Books: 1. area bonding. Latching Strategies: Basic Latch Design. Clocked & non clocked Logics: Single-Rail Domino Logic. of Lecture Hours : 50 IA Marks : 50 Exam Hours : 03 Exam Marks : 100 Introduction to high speed digital design: Frequency. Poulton. Noise sources in digital systems. Electrical models of wires.PLL and DLL based clock aligners. delay adjustments. geometry and electrical properties of wires. Power supply isolation. high speed properties of logic gates. clock skew and methods to reduce clock skew. Dual-Rail Domino Structures. of Lecture Hours /week : 04 Total no. Signaling convention and circuits: Signaling modes for transmission lines. closed loop timing. time and distance issues in digital VLSI design. signals and events. signaling over lumped transmission media. Static CMOS. Clocked Pass GateLogic.High Speed VLSI Design Subject Code : 14 EVE252 No. Power distribution and Noise: Power supply network. . Modeling of wires. synchronization failure and meta-stability. Capacitance and inductance effects. William S. lossless LC transmission lines. and Latching single-ended logic and Differential Logic. “High Speed Digital Circuits”. Kerry Bernstein & et. “Digital Integrated Circuits”. 1996. et al. 1999. Prentice Hall PTR. 3. 2003. Pearson. Howard Johnson & Martin Graham. Addison Wesley Publishing Company. “High Speed Digital Design” A Handbook of Black Magic. 4. 1993. 5. Masakazu Shoji. . Rabaey.2.. Kluwer. “High Speed CMOS Design Styles”. A Design Perspective. Al. Jan M. MEMS Subject Code No. bulk micromachining. consumer products and telecommunications. Tai — Ran Hsu. diffusion. scaling in geometry. electricity. Features and Design considerations of RF MEMS. LIGA process. Some MEMS fabrication processes: surface micro-machining. aerospace industry. scaling in rigid body dynamics. 2002 . Interfaces in micro system packaging. MEMS with micro actuators. magnetic and bio — sensors. Typical MEMS and Micro system products — features of MEMS. Tata McGraw Hill. Micro system packaging: Over view of mechanical packaging of micro electronics micro system packaging. electromagnetic forces. “MEMS and Micro Systems : Design and Manufacture”. Design considerations of Optical MEMS (MOEMS).i) Cantilever beam ii) Micro switches iii) MEMS based SMART antenna in mobile applications for maximum reception of signal in changing communication conditions and iv) MEMS based micro mirror array for control and switching in optical communications. Micro System Design and Modeling: Introduction. Photolithography. Micro sensors — thermal. Microsystems Fabrication Process: Introduction. Reference Books 1. The multidisciplinary nature of Microsystems design and manufacture. FAB-less fabrication. industrial products. radiation. Packaging technologies. health care industry. Design considerations: Process design. Applications of Microsystems in automotive industry. Scaling Laws in Miniaturization: Introduction to scaling. PVD. Ion-implantation. Mechanical design. scaling in fluid mechanics & heat transfer. MUMPS. oxidation. etching and materials used for MEMS. Transduction Principles in MEMS & Microsystems: Introduction. mechanical. CVD. Micro actuation. Modeling using CAD tools: ANSYS / Multiphysics or Intellisuite or MEMS CAD. scaling electrostatic forces. LASER micro machining. of Lecture Hours /week Total no. of Lecture Hours : 14ELD253 : 04 : 50 IA Marks : 50 Exam Hours : 03 Exam Marks : 100 Overview of MEMS & Microsystems: MEMS & Microsystems. Design and Modeling: case studies . N. Norwood. Devices and Structures”. Artech House”. “Micro Sensors MEMS and SMART Devices”. MA.2. 2000. J. W. 2002 3. 2002 4. . CRC Press. Maluf “Introduction to Micro Mechanical Systems Engineering. Gardner and V. John Wiley. Boca Raton. “MEMS and NEMS: Systems. Vardan. K. Basic topologies VCO and definition of phase noise. Various mixers. PHI 1998. Y. “RF Microelectronics” PHI 1998 R.E. Liberalization techniques. Noise performance and limitations of devices. Razavi. layout and Simulation”. Resonator VCO designs. Quadrature and single sideband generators. Noise power and trade off. Thomas H. Basic concepts in RF design: Nonlinearly and Time Variance. Receiver and Transmitter architectures. Boyce “CMOS Circuit Design. Oscillators. “Mixed Analog and Digital Devices and Technology”. Complexity and Choice of Technology. Reference Books: B. Coherent and noncoherent detection. Direct IF and sub sampled receivers. Design issues in integrated RF filters. of Lecture Hours : 50 IA Marks : 50 Exam Hours : 03 Exam Marks : 100 Introduction to RF Design and Wireless Technology: Design and Applications. integrated parasitic elements at high frequencies and their monolithic implementation RF Circuits Design: Overview of RF Filter design.working and implementation. Design of Mixers at GHz frequency range. Low noise Amplifier design in various technologies. Homodyne. Basic blocks in RF systems and their VLSI implementation.W. modeling of the transistors and SPICE model. Image reject. D. Comparison of various techniques for power efficiency.CMOS RF Circuit Design Subject Code : 14 EVE254 No. Sensitivity and dynamic range. Radio frequency Synthesizers. Tsividis. BJT and MOSFET Behavior at RF Frequencies: BJT and MOSFET behavior at RF frequencies. Jacob Baker. random processes and noise.PLLS. Various RF synthesizer architectures and frequency dividers. H. TMH 1996 . Lee “Design of CMOS RF Integrated Circuits” Cambridge University press 1998.P. of Lecture Hours /week : 04 Total no. Power Amplifier design. Intersymbol interference. Li. Direct conversion and two-step transmitters RF Testing: RF testing for heterodyne. Active RF components & modeling. Matching and Biasing Networks. Mobile RF communication and basics of Multiple Access techniques. conversion of gains and distortion RF Modulation: Analog and digital modulation of RF circuits. Bus architecture and its limitations. Hardware-Software codesign. Topics related to cache memories. Logic design issues. System-on-Chip. which include processors. top down vs bottom up. of Lecture Hours : 50 IA Marks : 50 Exam Hours : 03 Exam Marks : 100 Goal of the course – Today. power. Techniques for designing MPSoCs. The course aims to provide an appreciation for the motivation behind SoC design. Hardware Accelerators in Soc. performance maximization. benefits of system-on-chip integration in terms of cost. Typical goals in SoC design – cost reduction. Mesh-based NoC. MPSoCs: What. Network on Chip (NOC) topologies. IP verification and Integration. Embedded Memories –cache memories. Packet switching and wormhole routing. Comparison on System-on-Board. embedded DRAM. Performance and flexibility for MPSoCs design Case Study: A Low Power Open Multimedia Application Platform for 3G Wireless. Types of Specification. How MPSoCs. Cache coherence. and System-in-Package. of Lecture Hours /week : 04 Total no. Motivation for SoC Design . System On Chip Design Process: A canonical SoC Design. Low Power. Interconnect architectures for SoC. MESI protocol and Directory-based coherence. and the overall SoC design flow. Soft IP vs Hard IP. and performance.Review of Moore‟s law and CMOS scaling. On chip buses and interfaces. Verification strategy. waterfall vs spiral. Why.SoC Design Subject Code : 14EVE255 No. Specification requirement. . peripheral controllers. Productivity gap issues and the ways to improve the gap – IP based design and design reuse. design effort reduction. SoC Designflow. memories. power reduction. and connectivity sub-systems. VLSI chips are entire “system-on-chip” designs. Design for timing closure. flash memories. the challenges of SoC design. System level design issues. System Design Process. Routing in an NoC. Morgan Kaufmann Publishers © 2008. McGraw-Hill. Peckol. Sudeep Pasricha and Nikil Dutt. Madhavan Swaminathan. 2008. 2008. 3. James K. Rao R. Pierre Bricaud.Miniaturization of the Entire Syste”. Michael Keating. Tata Mcgraw-Hill.Reference Books: 1. Sung-Mo Kang. Tummala. 2. 3rd Edition. 4. 2nd edition."On-Chip Communication Architectures: System on Chip Interconnect”. “Embedded Systems: A Contemporary Design Tool”. Kluwer Accademic Publishers. Wiley Student Edition. “Reuse Methodology Manual for System on Chip designs”. “Introduction to system on package sop. “CMOS Digital Integrated Circuits”. Yusuf Leblebici. . 5. Draw the Layout and verify the DRC. Check for XX d.VLSI Design and Embedded System Lab -2 Subject Code : 14EVE26 No. completing thedesign flow mentioned below: a. Draw the schematic and verify the following i) DC Analysis ii) Transient Analysis b. Design an Inverter with given specifications*. completing the design flowmentioned below: a. ERC c. Verify & Optimize for Time. Extract RC and back annotate the same and verify the Design e. Draw the Layout and verify the DRC. ERC c. Check for XX d. of Lecture Hours : 42 IA Marks : 25 Exam Hours : 03 Exam Marks : 50 ANALOG DESIGN Analog Design Flow 1. of Lecture Hours /week : 03 Total no. i) A Single Stage differential amplifier . Power and Area to the givenconstraint*** 2. Design the following circuits with given specifications*. Extract RC and back annotate the same and verify the Design. Draw the schematic and verify the following i) DC Analysis ii) AC Analysis iii) Transient Analysis b. Design a 4 bit R-2R based DAC for the given specification and completing the design flow mentioned using given op-amp in the library**. Draw the Layout and verify the DRC. Check for XX d. For the SAR based ADC mentioned in the figure below draw the mixed signal schematic and verify the functionality by completing ASIC Design FLOW. 3. Draw the schematic and verify the following i) DC Analysis ii). Check for XX d. Draw the Layout and verify the DRC. ERC c.ii) Common source and Common Drain amplifier. Extract RC and back annotate the same and verify the Design.[Specifications to GDS-II] . Design an op-amp with given specification* using given differentialamplifier Common source and Common Drain amplifier in library** andcompleting the design flow mentioned below: a. ERC c. 5. 4. AC Analysis iii) Transient Analysis b. Draw the schematic and verify the following i) DC Analysis ii) AC Analysis iii) Transient Analysis b. Extract RC and back annotate the same and verify the Design. a. 2.Two child threads are crated with normal priority. 4.Test the program below using multithread application .Implement the multithread application satisfying the following : i.Thread 2 prints the priority of the thread 1 and rises its priority toabove normal and retrieves the new priority of thread 1. *** An appropriate constraint should be given 6 Design a simple 8-bit ADC converter using any one of the tools given above. iv.Thread 1 receives and prints its priority and sleeps for 50ms and thenquits. The main threadwaits for complete execution of all the child threads and then quits. prints it andthen quits. Design a simple NAND/NOR gate using any one of the tools given above.Implement the usage of anonymous pipe with 512 bytes for data sharingbetween parent and child processes using handle inheritance mechanism. 3.(Any other experiments may be added in supportive of the course) EMBEDDED SYSTEMS Embedded Programming Concepts (RTOS) 1. ** Applicable Library should be added & information should be given to the Designer. Compileand execute in Linux. ii.Create ‘n’ number of child threads.* Appropriate specification should be given. iii. 7.The main thread waits for the child thread to complete its job andquits. Each thread prints the message “ I’m inthread number …” and sleeps for 50 ms and then quits. The main thread continues sending the random messages to thechild thread till the ‘WM_QUIT’ message is sent to child thread. .Use a named message queue with name ‘MyQueue’.The main thread checks the termination of the child thread andquits when the child thread complete its execution. if any. iv. vi.Task 1 creates the specified message queue as Read Write andreads the message present.Test the program application for creating an anonymous pipe with 512 bytes of size and pass the ‘Read Handle’ of the pipe to a second process using memory mapped object.The child thread processes the message posted by the mainthread and quits when it receives the ‘WM_QUIT’ messge. v.Create a POSIX based message queue for communicating between twotasks as per the requirements given below:i.Create two tasks(Task1 & Task2) with stack size 4000 &priorities 99 & 100 respectively. Use event object for indicating the availability of data on the pipe and mutex objects for synchronizing the access in the pipe.i. 6. iii. iv. from the message queue and prints it on the console. iii. ii. The 2nd process reads the data written by the pipe server to the pipe and displays it on the console. ii.The main thread sends user defined messages and the message ‘WM_QUIT’ randomly to the child thread.Task2 open the message queue and posts the message ‘Hi fromTask2’. Handle all possible error scenarios appropriately. The first process writes a message ‘ Hi from Pipe Server’.The main thread creates a child thread with default stack size andname ‘Child_Thread’.The messaging mechanism between the main thread and childthread is synchronous. 5. fault simulation Techniques. combinatorial optimization.G. Sequential Circuit Optimization: Sequential circuit optimization using state based models. algorithm for delay evaluation and optimization. sequential circuit optimization using network models. Microelectronic design styles. Two Level Combinational Logic Optimization: Logic optimization. minimization of Boolean relations. Scheduling wither source and without resource constraints. .P. Types of simulators. dataflow and sequencing graphs. design for Testability (DFT) Techniques. directed graphs. structures logic networks.As and Anti fuse based F. compilation and optimization techniques. Testing: Simulation. Scheduling Pipe lined circuits.P. Synthesis of testable network. Automatic test pattern generation methods(ATPG). basic components of a simulator. operation on two level logic covers. HDLs used in synthesis. of Lecture Hours : 50 IA Marks : 50 Exam Hours : 03 Exam Marks : 100 Introduction: Microelectronics. Schedule Algorithms: A model for scheduling problems. tractable and intractable problems. of Lecture Hours /week : 04 Total no. algebraic model. algorithms for linear and integer programs. specific problems and algorithms for library binding (lookup table F. Algorithms. undirected graphs. abstract models. semiconductor technologies and circuit taxonomy. algorithms for library binding. Cell Library Binding: Problem formulation and analysis. algorithms for logic minimization.Synthesis and Optimization of Digital Circuits Subject Code : 14EVE41 No. rule based system for logic optimization. computer aided synthesis and optimization. state diagrams. structural hardware language.As). Scheduling algorithms for extended sequencing models. Hardware Modeling: Hardware Modeling Languages. graph optimization problems and algorithms. Multiple Level Combinational Optimizations: Models and transformations for combinational networks. rule based library binding. Boolean algebra and Applications. Behavioural hardware language. Graphs: Notation. symbolic minimization and encoding property. principles. distinctive features.G. “Logic Synthesis”. 1994. Pearson Education (Asia) Pte. 2000 . 2. SrinivasDevadas. KevinSkahill. and Kurt Keutzer.. 2003. “Principles of CMOS VLSI Design: A System Perspective”. Eshragian.Reference Books: 1. 2000. USA. Giovanni De Micheli. NeilWeste and K. “VHDL for Programmable Logic”. 3. “Synthesis and Optimization of Digital Circuits”. Pearson Education(Asia) Pvt.. AbhijitGhosh. McGraw-Hill. 4. Tata McGraw-Hill. 2nd edition. Ltd. Ltd. CMOS Multiplexers. Super Buffers.NOR.diode logic. Strategies encompassing hierarchy. regularity. NOR. NMOS. PHI Publication . of Lecture Hours /week : 04 Total no. structured design methods. Bi-CMOS and Steering Logic: Introduction. Barrel shifter. System Design: CMOS design methods. super buffers.An NMOS super buffer. processing challenges to further CMOS miniaturization Beyond CMOS: Evolutionary advances beyond CMOS. Reference Books: 1. and AOI Logic. pass logic. switches.CMOS. programmable structure. under bias. small signal operation of MESFETS and MOSFETS. General functional blocks -NMOS and CMOS functional blocks. modularity & locality. designing of transistor logic. McGraw-Hill International publications 3. programmable logic. Cambridge publications 2. carbon Nanotubes. comparison between CMOS and BI . Kevin F Brennan “Introduction to Semi Conductor Device”. Short Channel Effects and Challenges to CMOS: Short channel effects. Defect tolerant computing. Dynamic ratio less inverters. Special Circuit Layouts and Technology Mapping: Introduction. CMOS super buffers. quantitative description of MESFETS. molecular and biological computing Mole electronics-molecular Diode and diode. Wire routing and module layout. D. large capacitive loads. MESFETS: MESFET and MODFET operations.APucknell “Basic VLSI Design”. of Lecture Hours : 50 IA Marks : 50 Exam Hours : 03 Exam Marks : 100 Review of MOS Circuits: MOS and CMOS static plots. computing. tactile computing. CMOS Chip design Options. scaling theory. Eugene D Fabricius “Introduction to VLSI Design”. Gate arrays standard cell approach. RC delay lines. conventional vs. NAND-NAND. Talley circuits. Programmable inter connect.Advances in VLSI Design Subject Code : 14EVE421 No. MIS Structures and MOSFETS: MIS systems in equilibrium. Full custom design. tri state super buffer and pad drivers. Wayne Wolf. “Modern VLSI Design” Pearson Education.4. 2002 . SecondEdition . DFT. Quantization.Image and Video Processing Subject Code : 14ELD422 No. MTF of the visual system. Chap. Least squares filters. Transform operations. Visual quantization.1. AR models. Structure.4) Image Transforms: Introduction.6) Image Enhancement: Point operations. generalized inverse. Inverse &Wiener filtering. (Ref. Boundary representation.1. Image segmentation. Blind de-convolution.1. Smoothing splines and interpolation. Coordinate transformation& geometric correction. Transform features.2) Image Perception: Light. Color Image enhancement. Z Transform. DST. Monochrome vision models. Matrix theory. Slant. Hadamard. Color difference measures. Bayesian methods. Limitations in sampling & reconstruction. one dimensional Causal models. Discrete Random fields. Fidelity criteria. Chap. KLT. Fourier Domain filters. Moment representation.7) Image Filtering & Restoration: Image observation models. SVD transform. (Ref. Optimal quantizer. Color coordinate systems. Shape features. Random signals. (Ref.1. Color vision model. Chromaticity diagram. Properties of unitary transforms. linear prediction in two dimensions.8) Image Analysis & Computer Vision: Spatial feature extraction. Scene matching & detection. Multi-spectral image enhancement. Chap. of Lecture Hours : 50 IA Marks : 50 Exam Hours : 03 Exam Marks : 100 Introduction: 2D systems.3) Image Sampling and Quantization: Introduction.Chap. (Ref. of Lecture Hours /week : 04 Total no. Chap. Chap.1. Texture.1. Color representation. Boundary Extraction. DCT. Compander. Haar. Histogram modelling. false color and Pseudo-color. Optical & Modulation transfer function. Visibility function.5) Image Representation by Stochastic Models: Introduction. Chap. Edge detection.(Ref. Luminance. Region representation. Spectral density function. 2D orthogonal & unitary transforms. Brightness. (Ref. Temporal properties of vision. Classification Techniques. (Ref. Maximum entropy restoration. Mathematical preliminaries – Fourier Transform.1. (Ref. Contrast. 2D sampling theory. Non-causal representations. SVD and Iterative methods.1.9) . Chap. spatial operations. MPEG 2. E.Image Reconstruction from Projections: Introduction. “Digital Video Processing”. Ltd/Prentice Hall of India. Pixel coding. Inter-frame coding." Pearson Education (Asia) Pte. 2004. 2004.H.263./Prentice Hall of India. Gonzalez and R. 4. “Digital Image Processing” 2nd edition. Drew. Anil K. Pearson Education (Asia) Pte. Chap.11) Video Processing: Fundamental Concepts in Video – Types of video signals. Li and M. 2. Transform coding. USA. Digital video. Analog video. Search for motion vectors.1. Radon Transform. Ltd. 3. Projection theorem. coding of two tone images. Image compression standards. Content based video indexing. 3D tomography. MPEG 4. Color models in video. Prentice Hall. Fan beam reconstruction. C. “Fundamentals of Multimedia” Pearson Education (Asia) Pte. (Ref. H. Ltd. MPEG I. “Fundamentals of Digital Image Processing.261. Back projection operator. 1995.1. Predictive techniques. M. . Tekalp.Chap. Video Compression Techniques – Motion compensation. MPEG 7 and beyond. (Ref. Fourier reconstruction. R.. (Ref.10) Image Data Compression: Introduction. Z. Woods.S. 2004.4) Reference Books: 1. Jain. Inverse Radon transform. 11) Adaptive Filters: Applications of Adaptive Filters. M-Channel QMF bank. Roberto Cristi. “Digital Signal Processing: A Computer Based Approach”. “Digital Signal Processing”. Frequency-Domain Sampling: The Discrete Fourier Transform. Design of IIR Filters from Analog Filters.1Chap.1 Chap.1 Chap. It is intended to introduce a basic course in multirate signal processing especially meant for students of branches eligible for M Tech courses in EC related disciplines. Properties of the DFT. 1 & 7) Design of Digital Filters: General Considerations. Two Channel Quadrature Mirror Filter banks. India. (Ref. of Lecture Hours : 14ESP423 : 04 : 50 IA Marks : 50 Exam Hours : 03 Exam Marks : 100 Goal of the course – Advances in Digital Signal Processing involve variable sampling rates and thus the multirate signal processing and hence their applications in communication systems and signal processing. Introduction and Discrete Fourier Transforms: Signals. Prentice Hall 1996. 2007. Adaptive Direct Form Filters-RLS Algorithm. Linear Filtering Methods Based on the DFT (Ref. Sampling rate conversion by an arbitrary factor. (Ref.10) Multirate Digital Signal Processing: Introduction. Cengage Publishers. The Concept of Frequency in Continuous-Time and Discrete-Time Signals. Systems and Processing. . Design of FIR Filters. Adaptive Direct Form FIR Filters. Multistage implementation of Sampling rate conversion. III Ed. India.K. 3. Digital Filter banks. Frequency Transformations. Sampling rate conversion of Band Pass Signals.13) Reference Books: 1. 2. Classification of Signals. Mitra.The LMS Algorithm. (Fourth Edition).Modern DSP Subject Code No. Sampling rate Conversion by a factor ‘I/D’. Proakis and Manolakis. “Modern Digital Signal Processing”. EL Dimation by a factor ‘D’. Tata McGraw Hill. 2003.1 Chap. (Ref. Analog-to-Digital and Digital-to-Analog Conversion. (Erstwhile Thompson Publications). S. Applications of Multirate Signal Processing. Interpolation by a factor ‘I’. of Lecture Hours /week Total no. implementation of Sampling rate conversion. . “Digital Signal Processing. E. Ifeachor and B W Jarvis. Pearson Education. India.” II Edition. a practitioners approach.4.C. 2002 Reprint. Scheduling and Structuring Code for Parallelism. Hardware Support for Compiler Speculation. Case studies. Some topics in Pipelining. reporting and summarizing Performance. Fallacies and pitfalls. Case study of Pentium 4. Definition and examples of real faults and failures . Defining computer architecture. Case study of AMD Opteron memory hierarchy. of Lecture Hours /week Total no. Introduction to Storage Systems. Trends in power in Integrated Circuits. Dependability. Designing and evaluating an I/O system – The Internet archive cluster. Performance and Price-Performance. and pitfalls with respect to pipelining. Concluding Remarks. Hardware and Software for VLIW and EPIC Introduction: Exploiting Instruction-Level Parallelism Statically. reliability measures. Introduction to limits in ILP. Performance and efficiency in advanced multiple-issue processors. Instruction –Level Parallelism. Crosscutting issues. Crosscutting issues in the design of memory hierarchies. Fallacies and pitfalls in the design of memory hierarchies. Advanced topics in disk storage. Classes computers. Implementing Cache Coherence. Crosscutting issues. The Intel IA-64 Architecture and Itanium Processor. Performance Measurement of Parallel Processors with Scientific Applications. Interprocessor Communication: The Critical Performance Issue. Fallacies and pitfalls. Measuring. Fallacies and pitfalls. fallacies. ILP. Trends in Technology. Hardware Support for Exposing Parallelism: Predicated Instructions. Case study of NetAA FAS6000 filer. Detecting and Enhancing LoopLevel Parallelism. of Lecture Hours : 14EVE424 : 04 : 50 IA Marks : 50 Exam Hours : 03 Exam Marks : 100 Introduction and Review of Fundamentals of Computer Design: Introduction. Large-Scale Multiprocessors and Scientific Applications Introduction. . The Custom Cluster Approach: Blue Gene/L. Synchronization: Scaling Up. Performance of Scientific Applications on Shared-Memory Multiprocessors. and benchmarks. Characteristics of Scientific Applications. I/O performance. Storage Systems: Review of basic concepts. Concluding Remarks. Quantitative Principles of computer design.Advanced Computer Architecture Subject Code No. Memory Hierarchy Design. Trends in cost. Its Exploitation and Limits on ILP: Introduction to pipelining. Basic concepts and challenges of ILP. Queuing theory. Reference Books: 1. Speeding Up Integer Multiplication and Division. 2007. Floating-Point Multiplication. Programmability”. “Computer Architecture A Quantitative Approach”. More on Floating-Point Arithmetic. Elsevier. Fallacies and Pitfalls. Division and Remainder. Floating Point. “Advanced Computer Architecture . Floating-Point Addition. 2. Kai Hwang. 2nd Edition .Parallelism. 4th Edition. Speeding Up Integer Addition. Scalability. Hennessey and Patterson.Computer Arithmetic: Introduction. Basic Techniques of Integer Arithmetic. Parallelism . Lysaght and W. “Practical FPGA Programming in C”. Tools and flows”. Prentice-Hall. state of the art.RC Architectures .Partial Reconfiguration .Placement & routing . Thibault. Graham. 2004.Systolic arrays -Pipelining . Prentice-Hall. “Introduction to Reconfigurable Computing: Architectures.Basic concepts and related fields of study . “Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays”.High-level Design High-level synthesis .Numerical Analysis -Performance Analysis/Prediction . future trends . Bobda. 2007. of Lecture Hours : 14 EVE425 : 04 : 50 IA Marks : 50 Exam Hours : 03 Exam Marks : 100 Introduction : Goals and motivations .Architectural design space explorations. 2005.Soft-core microprocessors. Parallel Processing : RC Application Design .Bottlenecks .Design tools. of Lecture Hours /week Total no. C. and other metrics .Algorithm analysis and speedup projections . Springer.System synthesis .Performance. Wolf.Optimizations . Fpga Design : FPGA Physical Design Tools -Technology mapping . 6. 3.Fault Tolerance. Springer.Special Topics .System architectures -System design strategies . “FPGA Based System Design”. 2005. 5. .Logic minimization. Architectures and Applications for Reconfigurable Computing”.Communication . power. C. Algorithms and Applications”.Small-scale architectures . Reference Books: 1. Springer. Rosenstiel. M. D. W.Bioinformatics . 2004.HPC architectures . Newnes.Fine-grained architectures Coarsegrained architectures .HW/SW partitioning .High-level languages . Maxfield. Case Study : Case Studies.History. “New Algorithms.System services .Register transfer (RT)/Logic Synthesis Controller/Data path synthesis . Gokhale and P. 2.Signal and image processing .Reconfigurable Computing Subject Code No. P.Device characteristics . “The Design Warrior's Guide to FPGAs: Devices. 2005. 4.HPEC architectures . Architectures : Hybrid architectures. Pellerin and S.Security . 7. Cofer and B. Harding. 2005. R. “Rapid System Prototyping with FPGAs: Accelerating the Design Process”. . Newnes.