www.jntuworld.com || www.android.jntuworld.com || www.jwjobs.net || www.android.jwjobs.net w.e.f 2009-2010 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY: KAKINADA KAKINADA 533 003 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING M. Tech- I Semester Specialization: VLSI & ES COURSE STRUCTURE Code Core Name of the Subject 1. VLSI Technology & Design 2. Analog & Digital IC Design 3. Embedded Systems Concepts 4. Embedded System Design L 4 4 4 4 4 P C INT 8 8 8 8 8 40 40 40 40 40 Elective I 1.Degital System Design 2. Embedded Software Design Elective II 1.VHDL Modeling of Digital Systems 4 2.Hardware Software Co-Design Laboratory 1.HDL Programming Laboratory J T N W U R O 8 4 4 D L 60 60 60 60 60 60 60 EXT TOTAL 100 100 100 100 100 40 100 40 100 www.jntuworld.com || www.jwjobs.net www.jntuworld.com || www.android.jntuworld.com || www.jwjobs.net || www.android.jwjobs.net w.e.f 2009-2010 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY: KAKINADA DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING M. Tech- I Semester VLSI TECHNOLOGY & DESIGN UNIT – I REVIEW OF MICROELECTRONICS AND INTRODUCTION TO MOS TECHNOLOGIES: (MOS, CMOS, Bi CMOS) Technology trends and projections. UNIT – II BASIC ELECTRICAL PROPERTIES OF MOS, CMOS & BICOMS CIRCUITS: Ids-Vds relationships, Threshold voltage Vt, Gm, Gds and Wo, Pass Transistor, MOS,CMOS & Bi CMOS Inverters, Zpu/Zpd, MOS Transistor circuit model,Latch-up in CMOS circuits. UNIT – III LAYOUT DESIGN AND TOOLS: Transistor structures, Wires and Vias , Scalable Design rules ,Layout Design tools. UNIT – IV LOGIC GATES & LAYOUTS: Static complementary gates, switch logic, Alternative gate circuits, low power gates, Resistive and Inductive interconnect delays. UNIT – V COMBINATIONAL LOGIC NETWORKS: Layouts, Simulation, Network delay, interconnect design, power optimization, Switch logic networks, Gate and Network testing. UNIT – VI SEQUENTIAL SYSTEMS: Memory cells and Arrays, clocking disciplines, Design ,power optimization, Design validation and testing. UNIT – VII FLOOR PLANNING & ARCHITECTURE DESIGN: Floor planning methods, off-chip connections, High-level synthesis, Architecture for low power, SOCs and Embedded CPUs, Architecture testing. UNIT – VIII INTRODUCTION TO CAD SYSTEMS (ALGORITHMS) AND CHIP DESIGN: Layout Synthesis and Analysis, Scheduling and printing; Hardware/Software Co-design, chip design methodologies- A simpleDesign exampleTEXT BOOKS: 1. Essentials of VLSI Circuits and Systems, K. Eshraghian et . al( 3 authors) PHI of India Ltd.,2005 J T N W U R O D L www.jntuworld.com || www.jwjobs.net 1990. CURRENT MIRRORS AND SINGLE STAGE AMPLIFIERS: simple COMS.E Weste. SEQUENCIAL IC DESIGN USING VHD: VHDL modeling for larches. interfacing comparison of logic families. CMOS Circuit Design.f 2009-2010 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY: KAKINADA DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING M. TTL. Cascode Wilson Wilder current mirrors. J T N W U R O D L UNIT-III LOGIC FAMILIES & CHARACTURISTICS : COMS.jwjobs. K. logic families COMS / TTL. shift registers. fifth Indian Reprint. adders and subtractors .e. Wayne Wolf . Principals of CMOS Design – N. Common Source amplifier source follower. 3 w.switch sharing fully differential filters – charged injections-switched capacitor gain circuits parallel resistor –capacitor circuit – preset table gain circuit – other switched capacitor circuits – full wave rectifier – peak detector sinusoidal oscillator.Noise in common source stage noise band width.jntuworld. 3rd Edition. REFERENCES: 1.net . ECL.parasitic sensitive integrator parasitic insensitive integrators signal flow graph analysis-First order filters.com || www.I Semester ANALOG AND DIGITAL IC DESIGN UNIT-I OPERATIONAL AMPLIFIERS: General considerations one – state op-amps.Voltage controlled oscillator case study: Analysis of the 560 B Monolithic PLL.jwjobs.android. encoders. Modern VLSI Design.. Tech. Li Boyce.com || www.net 2. 3JT current mirror. 2004.jntuworld.The phase locked loop in the locked condition Integrated circuit PLLs – phase Detector. common gate amplifier NOISE: Types of Noise – Thermal Noise-flicker noise. Introduction to VLSI Design – Fabricius. COMBINATIONAL LOGIC DESIGN USING VHDL: VHDL modeling for decoders.comparison I/P range limitations slew rate.www.net || www.Noise in opamps. flip flaps. MGH International Edition.Pearson Education. www. 3. two stage opamps-gains boosting stage. Layout and Simulation – Baker.android.Eshraghian. comparison. Adison Wesley. FSMs.jntuworld.jwjobs.com || www. PHI. counters. 2005. 2. UNIT-II PHASED LOCKED LOOP DESIGN: PLL concepts. SWITHCHED CAPACITORS CIRCUITS: Basic Building blocks op-amps capacitors switches – non-over lapping clocks-Basic operations and analysis-resistor equivalence of la switched capacitor. 2nd Edition. multiplexers.H. Douglas J Smith.com || www.jntuworld. 2. Prentice Hall India.android.(2002) 3. “Digital Design Principles & Practices”. Digital Integrated Circuit Design by Ken Martin.www.jwjobs. TMH 4. Analysis and design of Analog Integrated Circuits. Digital Integrated Circuit Design Oxford University. Behzad Razavi.jntuworld.latched comparator NYQUIST RATE D/A CONVERTERS: Decoder based converter resistor storing converters folded resister string converter – Binary scale converters – Binary weighted resistor converters – Reduced resistance ratio ladders – R-2R based converters – Thermometer code current mode D/A converters. Synthesizing and simulating ASICs and FPGAs using VHDL or Verilog. Pearson Education & Xilinx Design Series.net . Doone Publications.com || www. John Wiley & Sons.jntuworld. UNIT-V COMPORATORS: Using an op-amp for a comparator-charge injection errors. (2002) 4. REFERENCES: 1.net UNIT-IV DIGITAL INTEGRADED SYSTEM BUILDING BLOCKS: Multiplexers and decoders – barrel shifters counters digital single bit adder MEMORIES: ROM: Internal structure 2D decoding commercial type timing and applications CPLD: XC 9500 series family CPLD architecture – CLB internal architecture. 3. J T N W U R O D L www. 3rd Ed. “Verylog HDL-A Guide to Digital Design and Synthesis”. DAC based successive approximation – flash converters time interleaved A/D converters. (1999). Digital Design Principles & Practices” by John F Wakerly. a practical Guide for Designing. Samir Palnitkar. Design of Analog CMOS Integrated Circuits. 3rd Ed. Ken Martin. Meyer. NYQUIST RATE A/D CONVERTERS: Integrating converters – successive approximation converters. FPGA: Conceptual of view of FPGA – classification based on CLB internal architecture I/O block architecture.jwjobs.net || www.android. 2. John Wiley & Sons. Ken Martin. Pearson Education & Xilinx Design Series. Analog Integrated circuit Design by David A Johns. Oxford University 2000 5. I/O block internal structure . John F Wakerly.com || www. Hurst Lewis.2000. “HDL Chip Design.(2002) SUGGESTING READOMG 1. by Gray.jwjobs. VC++ AND JAVA Interprocess communication and synchronization of processes.f 2009-2010 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY: KAKINADA DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING M.jwjobs. C++. and advanced I/O buses between the network multiple devices. PCI-X and advanced buses.net . problem of sharing data by multiple tasks and routines. memory devices. use of target systems.net w. UNIT V: HARDWARE – software co-design in an embedded system. interrupt servicing mechanism UNIT IV: PROGRAMMING CONCEPTS AND EMBEDDED PROGRAMMING IN C. DMA. interfacing processors.jntuworld. UNIT II: DEVICES AND BUSES FOR DEVICE NETWORKS I/O devices.com || www.I Semester EMBEDDED SYSTEMS CONCEPTS UNIT I: AN INTRODUCTION TO EMBEDDED SYSTEMS An Embedded system. multiple processes in an application.jntuworld. profibus foundation field bus. software embedded into a system. use of scopes and logic analysis for system.net || www. J T N W U R O D L www.android. use of software tools for development of an embedded system. hardware tests. interprocess communication.com || www.jwjobs. exemplary embedded systems.e. allocation of memory to program cache and memory management links. PCI. UNIT III: DEVICE DRIVERS AND INTERRUPTS SERVICING MECHANISM Device drivers. task and threads. device drivers for internal programmable timing devices.android. parallel port and serial port device drivers in a system. memories and Input Output Devices. embedded system design and co-design issues in system development process. memory selection for an embedded systems. design cycle in the development phase for an embedded system. embedded system – on – chip (SOC) and in VLSI circuit. embedded system project management. Processor selection for an embedded system. Issues in embedded system design. Tech. serial communication using the “I2 C” CAN.jwjobs. processor in the system.com || www.jntuworld. segments and blocks and memory map of a system. other hardware units.www. Processor and memory organization – Structural Units in a Processor. timer and counting devices. host systems or computer parallel communication between the networked I/O multiple devices using the ISA. Board Memory and performance. Auxiliary Memory. Explanation about above drivers with suitable examples. An embedded software primer by David Simon.I Semester EMBEDDED SYSTEM DESIGN UNIT – I Introduction An Embedded System-Definition. w. Current Technologies. Bus performance.jwjobs. Embedded systems design:Real world design be Steve Heath. Tech.android. Embedded Processors – ISA architecture models. Newton massUSA 2002 4. Examples. PEA 3.com || www. I/O components and performance. Memory device drivers. UNIT – IV Embedded Software –I Device drivers. Integrating the Bus with other board components.net TEXT BOOK: 1. hardware design concepts.jntuworld. software development.net .net || www. RAM. introduction to processor based embedded system design concepts. interfacing the I/O components.android. Device Drivers for interrupt-Handling.jntuworld. Data communication by Hayt.jwjobs. www.com || www. Butterworth Heinenann.jwjobs. Embedded systems: Architecture. processor performance.e. On-board bus device drivers.www.jntuworld. Embedded system design by Arnold S Burger.com || www. Board buses – Bus arbitration and timing. Board Memory – ROM. Board I/O drivers. programming and design by Rajkamal.f 2009-2010 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY: KAKINADA KAKINADA 533 003 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING M. CMP 2. Integration in system Design. processor in an embedded system and other hardware units. UNIT – III Embedded Hardware –II J T N Embedded Hardware – I W U R O D L Embedded board Input / output – Serial versus Parallel I/O. Internal processor design. Memory Management of External Memory. Embedded system design flow. TMH REFERENCE: 1. UNIT – II Embedded hardware building blocks. com || www.www. “Embedded Systems: Architecture. Tammy Noergaard “Embedded Systems Architecture: A Comprehensive Guide for Engineers and Programmers”.jwjobs. “Embedded system Design: A Unified Hardware/Software Introduction”. I/O and file system management. OS performance guidelines. Getting embedded software into the target system. CMP. Tony D. 2008.com || www. Givargis. Middleware and Application Software – Middle ware. John Wily & Sons Inc. simulators.Ltd. Rajkamal. TMH Pu blications. Application layer software examples.jntuworld. System Boot-Up.jntuworld.2002. J T N W U R O D L www.jwjobs.net . 2007. Laboratory tools. Memory Management. Middleware examples.net UNIT – V Embedded Software –II Embedded operating systems – Multitasking and process Management. introduction to embedded software development process and tools. 2. Second Edition. “Embedded System Design”. Debugging tools. 3. Elsevier(Singapore) Pte. OS standards example – POSIX.com || www. testing on host machine. UNIT-VIII Embedded System Design Examples Case studies. UNIT-VII Embedded System Design Implementation and Testing Implementing the design-The main software utility tool.android. Frank Vahid. TEXT BOOKS: 1. UNIT – VI Embedded System Design and Development Embedded system design and development lifecycle model. linking and locating software. creating an embedded system architecture.android. Board support packages. Arnold S Burger.Host and Target machines. 2. Translation tools. Programming and Design”. CAD and the hardware. issues in Hardware-Software design and co-design. “Embedded System Design”.jntuworld. Science Publishers.Processor design approach of an embedded system –Power PC Processor based and Micro Blaze Processor based Embedded system design on Xilinx platform-NiosII Processor based Embedded system design on Altera platform-Respective Processor architectures should be taken into consideration while designing an Embedded System.Publications.jwjobs. Peter Marwedel. 2005. REFERENCE BOOKS: 1.net || www. UNIT – IV TEST PATTERN GENERATION: D – algorithm. flow table. races. Machine identification. Z. Nolman Balabanian. N. Signature analysis and testing for bridging faults. Kohavi algorithm. PODEM. FPGAs.www. PLA minimization and PLA folding. bridging faults. state assignments.jwjobs. UNIT – III FAULT MODELING: Fault classes and models – Stuck at faults.android. UNIT – VI PROGRAMMING LOGIC ARRAYS: Design using PLA’s.e.com || www.jntuworld. Reduction of state tables. Kohavi – “Switching & finite Automata Theory” (TMH) 2. TEST GENERATION: Fault diagnosis of Combinational circuits by conventional methods – Path Sensitization technique.I ) UNIT – I DESIGN OF DIGITAL SYSTEMS: ASM charts.net .I Semester DIGITAL SYSTEM DESIGN ( Elective. UNIT – II SEQUENTIAL CIRCUIT DESIGN: design of Iterative circuits. Boolean difference method. Test generation and Testable PLA design. Design of fault detection experiment. sequential circuit design using CPLD.com || www. UNIT – VIII ASYNCHRONOUS SEQUENTIAL MACHINE: fundamental mode model.jwjobs.android. minimal closed covers. TEXT BOOKS: 1. UNIT – V FAULT DIAGNOSIS IN SEQUENTIAL CIRCUITS: State identification and fault detection experiment.f 2009-2010 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY: KAKINADA DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING M. state reduction. transition and intermittent faults. N.com || www.net || www. design of sequential circuits using ROMs and PLAs. cycles and hazards. UNIT – VII PLA TESTING: Fault models. Tech.jntuworld. Biswas – “Logic Design Theory” (PHI) 3.net w. Hardware description language and control sequence method. Random testing. Bradley Calson – “Digital Logic Design Principles” – Wily Student Edition 2004.jwjobs. J T N W U R O D L www.jntuworld. transition count testing. Joint Test Action Group (JTAG) and Nexus. Iteration and Implementation. Flash Memory. Jaico Publications 2. Testing: Why Test? When to Test? Which Test? When to Stop? Choosing Test cases. Memory Organization. 4 w.jwjobs. Tool chain Availability. RTOS Availability. ROM Emulator.android. Roth Jr. Performance Testing Maintenance and Testing.com || www.net REFRENCE BOOKS: 1. Friedman – “Digital System Testing and Testable Design”. Abramovici.jntuworld. Detailed hardware and software design. Breues. Special Pentium Registers. J T N W U R O D L www. Special Software Techniques: Manipulating the Hardware. Hardware Trends. Charles H.e.I Semester EMBEDDED SOFTWARE DESIGN (Elective – I) UNIT 1 Pentium Processor: Introduction to the Pentium Microprocessor. Other issues in the Selection process. UNIT 3 Development Environment: The Execution Environment. – “Fundamentals of Logic Design”.f 2009-2010 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY: KAKINADA DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING M. Testing Embedded Software.net . UNIT 4 BDM: Background Debug Mode. Selection Process: Packaging the Silicon. The Future. Watchdog Times.net || www. M. ICE – Integrated Solution: Bullet Proof Run Control. Tech.www. UNIT 2 Embedded Design Life Cycle: Introduction. 3.jwjobs. Setting the Trigger. M. Product Specification. Hardware/Software integration. Basic Tool Set: Host – Based Debugging. Hardware Break points. Partitioning decision : Hardware/Software Duality. Remote Debuggers and Debug Kernels. ASICs and Revision Costs. Logic Analyzer.android.jntuworld. Timing Constrains. D. Product Testing and Release. Frederick. Real time trac. Interrupts and Interrupt service Routines (ISRs). Pentium Memory management. System Startup. J.jwjobs. Adequate Performance. A. Hill & Peterson – “Computer Aided Logic Des ign” – Wiley 4th Edition. A. Usage Issue. Design Methodology.jntuworld.com || www. Overlay memory. Maintaining and upgrading existing products.com || www. Hardware/software partitioning. Allocating Buffer Memory. Design Libraries.e. MSI-Based Design.com || www. Bary B Brey. Buffering and Other Data Structures: What is a buffer? Linear Buffers. 2. Packaging Parts And Utilities.com || www.jwjobs.I Semester VHDL MODELLING OF DIGITAL SYSTEMS (Elective. Utilities For High –Level Descriptions-Type Declaration And Usage.jntuworld.jwjobs. Place And Route. UNIT III DESIGN ORGANIZATIN AND PARAMETERIZATION: Definition And Usage If Subprograms. Subprogram Parameter Types And Overloading.II) UNIT I INTRODUCTION : An Overview Of Design Procedures Used For System Design Using CAD Tools. Three State Bussing AGeneral Data Flow Circuit. VHDL Operators. Sequential Wait Statements Formatted ASCII I/O Operators. UNIT II BASIC CONCEPT IN VHDL: Characterizing Hardware Languages. “Embedded Systems”. Emulation and debugging techniques. Open Collector Gates. State Machine Description. Controller Description VHDL Operators.net UNIT 5 Writing Software for Embedded Systems: The compilation Process. Downloading.android.www. J T N W U R O D L www. Directional Buffers. Using alternative Libraries. Tech. UNIT IV DATA FLOW DESCRIPTION IN VHDL Multiplexing And Data Selection.jntuworld. w. Examples Using Commercial PC Based On VHDL Elements Of VHDL Top Down Design With VHDL Subprograms. Behavioral Description Of Hardware: Process Statement Assection Statements. Bergur. Design Verification Tools. Memory and Performance Trade-offs.net || www. Signal Assignments.android. Circular Buffers. FIFOs.jntuworld. Updating Basic Utilities. User Defined Attributes. Objects And Classes. Writing a Library. Double Buffering. TEXT BOOKS: 1. Concurrent And Sequential Assignments. Other Types And Type Related Issues. Design Configuration. Memory Leakage. Modeling A Test Bench Binding Alternative Top Down Wiring. Packing Basic Utilities. “Microprocessors and Microcontrollers”. Porting Kernels. Native Versus CrossCompilers. Linked Lists. Runtime Libraries. Design Parametrization. Wiring Interactive Networks. Buffer Exchange. Predefined Attributes.com || www.net . Synthesis.jwjobs. Buffer Under run and Overrun. Simulation. using a standard Library. Design Entry.f 2009-2010 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY: KAKINADA DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING M. C extensions for Embedded Systems. Structural Specification Of Hardware: Parts Library Wiring Of Primitives. Optimization. VHDL As A Modelling Language. A Generic Co-Design Methodology. Z. TEXT BOOKS: 1. Behavioural Description Of Parawan.jwjobs.SYNTHESIS ALGORITHMS : Co – Design Models. Future Developments in Emulation and Prototyping. Architectures for Control Dominated System and Data – Dominated Systems. A More Realistic Parwan. System Communication infrastructure.com || www. Target Architectures and Application System Classes.com || www.android.net UNIT V CPU MODELLING FOR DESCRIPTION IN VHDL: Parwan CPU.com || www. (2/E). Bussing Structure.I Semester R O D L www.jntuworld. (3/E) Mcgraw Hill 10 w.f 2009-2010 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY: KAKINADA DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING HARDWARE SOFTWARE CO-DESIGN ( Elective-II ) UNIT I CO – DESIGN ISSUES AND CO. Tech. J T N W U M.jwjobs.jntuworld. Hardware – Software Synthesis Algorithms : Hardware – Software Partitioning. Prototyping and Emulation Environments. Languages. PERRY : VHDL. Data Flow Description Test Bench For The Parwan CPU.e. Interface Design And Modeling.NAWABI : VHDL Analysis And Modelling Of Digital Systems. Mcgraw Hill. (1998) REFERENCE: 1. Distributed System CoSynthesis.www.jwjobs. UNIT II PROTOTYPING AND EMULATION AND TARGET ARCHITECTURES : Prototyping and Emulation techniques.jntuworld.net .android. Architectures. Architecture Specialization Techniques.net || www. com || www. coordinating Concurrent Computations. UNIT IV DESIGN SPECIFICATION AND VERIFICATION : Design. Design representation for system level synthesis. Practical Consideration in a compiler Development Environment.jwjobs. Heterogeneous Specifications and Multi Language Co – Simulation. Concurrency.www.net UNIT III COMPILATION TECHNIQUES AND TOOLS FOR EMBEDDED PROCESSOR ARCHITECTURES : Modern Embedded Architectures.com || www.android. Interface Verification UNIT V LANGUAGES FOR SYSTEM – LEVEL SPECIFICATION AND DESIGN : System – Level Specification.net .jwjobs. Embedded Software Development needs.jwjobs.jntuworld. Kluwer Academic Publishers J T N W U R O D L www.jntuworld. TEXT BOOKS : 1. Design Verification. Hardware / Software Co – Design Principles and Practice.Design Computational Model.net || www. Compilation Technologies. interfacing components.Design. The cosyma system and Lycos system. The Co. Co. Verification Tools.com || www.jntuworld.android. Implementation Verification. System level specification Languages. net || www.jntuworld. Implementation of Designed Digital Circuits using FPGA and CPLD devices.e.com || www. Place and Route techniques for major FPGA vendors such as Xilinx.www.jntuworld.f 2009-2010 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY: KAKINADA DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING M.com || www. Verification of the Functionality of Designed circuits using function Simulator. 3. 6. J T N W U R O D L www.android. Synthesis of Digital circuits 5. Tech. Timing simulation for critical path time calculation.I Semester HDL PROGRAMMING LABORATORY 1.jwjobs.net w.jntuworld. 4.net .android.com || www. Digital Circuits Description using Verilog and VHDL 2. Altera and Actel etc.jwjobs.jwjobs. System Modeling & Simulation Elective IV 1. Advanced Microcontrollers and Processors Laboratory Embedded Systems Laboratory J T N W U R O 4 4 4 4 4 4 4 - D L 8 8 8 8 8 40 40 40 40 40 8 40 4 40 IN T EXT TOTAL 60 60 60 60 60 100 100 100 100 100 60 100 60 100 www.net .jntuworld.jwjobs.e.android.com || www.www.II Semester Specialization: VLSI & ES COURSE STRUCTURE Code Core Name of the Subject L P C 1. Algorithms for VLSI Design Automation 2. Embedded and Real Time Systems 3.net || www.jwjobs.Design of Fault Tolerant Systems 2.android. Low Power VLSI Design Elective III 1. DSP Processors & Architecture 4.com || www. 2009-10 JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY: KAKINADA KAKINADA 533 003 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING M.CPLD and FPGA Architecture and Applications 2.com || www. Tech.jwjobs.f.jntuworld.net w.jntuworld. Assignment and Scheduling. Two – Level Logic Sysnthesis. High – level Transformations. Floorplanning and Routing Problems. Allocation.jwjobs. Design Automation tools. Tabu search. Placement. Computational Complexity. Internal representation of the input algorithm. J T N W U R O D L UNIT VIII PHYSICAL DESIGN AUTOMATION OF MCM’S: MCM technologies. Placement – Chip array based and full custom approaches.com || www. Topologic routing. Branch and Bound. Switch level modeling and simulation UNIT V LOGIC SYNTHESIS AND VERIFICATION: Basic issues and Terminology. routing and programmable MCM’s. Concepts and Algorithms UNIT IV MODELLING AND SIMULATION: Gate Level Modelling and Simulation. Dynamic Programming. Some Scheduling Algorithms.com || www. UNIT VII PHYSICAL DESIGN AUTOMATION OF FPGA’S: FPGA technologies.Physical Design cycle for FPGA’s partitioning and Routing for segmented and staggered models. Algorithmic Graph Theory. Multiple stage routing.net ALGORITHMS FOR VLSI DESIGN AUTOMATION UNIT I PRELIMINARIES: Introduction to Design Methodologies. Partitioning.android.net . Genetic Algorithms. Routing – Maze routing. UNIT III Layout Compaction.jwjobs. Tractable and Intractable Problems UNIT II GENERAL PURPOSE MTHODS FOR COMBINATIONAL OPTIMIZATION: Backtracking. www.com || www. Local Search. UNIT VI HIGH LEVEL SYNTHESIS: Hardware Models.jntuworld. Simulated Annealing.net || www. Integrated Pin – Distribution and routing.jntuworld.jwjobs.www. Binary – Decision diagram. Some aqspects of Assignment problem. Integer Linear Programming.android.jntuworld. MCM physical design cycle. android. S.net || www.jwjobs.jntuworld.android. Wiley.com || www.com || www. 1998 J T N W U R O D L www. Naveed Sherwani. John wiley & Sons (Asia) Pvt. Springer International Edition. 2005 REFERENCES: 1.com || www.Ltd.jwjobs. 3rd edition.jwjobs. Algorithms for VLSI Design Automation.jntuworld. 2nd Edition. 2.jntuworld. Pearson Education Asia.Gerez. 1999. 1993 Modern VLSI Design: Systems on silicon – Wavne Wolf.www.net TEXT BOOKS: 1. Computer Aided Logical Design with Emphasis on VLSI – Hill & Peterson. WILEY student edition. Algorithms for VLSI Physical Design Automation.H.net . jntuworld.jwjobs.net . J T N W U R O D L www.android. RS232/UART. custom purpose processor design(RT -level). Application specific Instruction –Set processors (ASIPs)-Micro controllers and Digital signal processsors. models Vs Languages.USB. Logic synthesis. concurrent process model. UNIT II: GENERAL PURPOSE PROCESSORS Basic architecture. Systems Synthesis and Hard ware/Software Co-Design. Behavioral Synthesis.com || www. operations. Ethernet. UNIT V: EMBEDDED/RTOS CONCEPTS-I Architecture of the Kernel. Pipes-Signals. concurrent processes. UNIT VI: EMBEDDED/RTOS CONCEPTS-II Mailboxes.using state machines. RS422/RS485. Automation. Semaphores.net EMBEDDED AND REAL TIME SYSTEMS UNIT I: INTRODUCTION Embedded systems over view. IEEE1394 Firewire.com || www. UNIT VII: EMBEDDED/RTOS OCNCEPTS-III Timers-Memory Management-Priority inversion problem-embedded operating systemsEmbedded Linux-Real-time operating systems-RT Linux-Handheld operating systemsWindows CE.jwjobs. design challenges. real-time systems.jntuworld. Mutex. interrupt service routines. processor technology. optimizing custom single purpose processors. development environment. Tasks and task scheduler.jwjobs. Single purpose processors RT-level combinational logic.android.net || www. RT synthesis. UNIT IV: COMMUNICATION PROCESSES Need for communication interfaces. programmer’s view.www. Implementation. synchronization among processes. Trade-offs. Verification.jntuworld. Blue tooth.11. Hardware/Software co-simulation. Infrared. sequential logic(RTlevel). Message Queues.com || www. finite state machines with data path model(FSMD). program state machine model(PSM. UNIT VIII: DESIGN TECHNOLOGY Introduction. Event Registers. Reuse of intellectual property codes. IEEE 802. communication among processes. Synthesis. data flow model. parallel evolution of compilation and synthesis. UNIT III: STATE MACHINE AND CONCURRENT PROCESS MODELS Introduction. Design technology. REFERENCE BOOKS 1.KVKK prased. An Embedded Software Primer.android.com || www.jntuworld.com || www. Introduction to Embedded Systems . 2.2002.Valvano. 3.David E.com || www.jntuworld.android.Raj Kamal. Tony D.www.Embedded System Design-A Unified Hardware/Software Introduction.jwjobs. Leaarning. Dreamtech press-2005. Embedded Microcomputer Systems-Jonathan W.2005 Books/Cole. pearson Ed.jwjobs.Thomson *** J T N W U R O D L www. Inc.Givargis.Simon.net || www. 2.net .jntuworld. Embedded/Real Time Systems.jwjobs.Frank Vahid.net TEXT BOOKS 1. John Wiley & Sons. TMS-2002. 2-D Signal Processing. UNIT III ARCHITECTURES FOR PROGRAMMABLE DSP DEVICES Basic Architectural features. Memory space of TMS320C54XX Processors. Dynamic Range and Precision.jwjobs. Digital filters. A Digital signal-processing system. Decimation Filters. Compensating filter. Discrete time sequences. Pipeline Programming models. Decimation and interpolation. UNIT V J T N W U R O D L PROGRAMMABLE DIGITAL SIGNAL PROCESSORS Commercial Digital signal-processing Devices. Speed Issues. UNIT IV EXECUTION CONTROL AND PIPELINING Hardware looping. Programmability and Program Execution. Data Addressing modes of TMS320C54XX DSPs. A/D Conversion errors. www. Data Addressing modes of TMS320C54XX Processors.com || www. PID Controller. Data Addressing Capabilities.com || www.jwjobs. Interrupts of TMS320C54XX processors. Stacks. Pipeline Operation of TMS320C54XX Processors. D/A Conversion Errors. Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT). Adaptive Filters. Address Generation Unit. Features for External interfacing.android.jwjobs. DSP Computational Building Blocks. The sampling process.jntuworld.jntuworld. Analysis and Design tool for DSP Systems MATLAB. UNIT II COMPUTATIONAL ACCURACY IN DSP IMPLEMENTATIONS Number formats for signals and coefficients in DSP systems. Relative Branch support.net || www. On-Chip Peripherals. Program Control.com || www.www. Sources of error in DSP implementations. Pipelining and Performance. Pipeline Depth. IIR Filters. Bus Architecture and Memory. UNIT VI IMPLEMENTATIONS OF BASIC DSP ALGORITHMS The Q-notation. DSP Computational errors. Interpolation Filters. DSP using MATLAB.net DSP PROCESSORS AND ARCHITECTURES UNIT I INTRODUCTION TO DIGITAL SIGNAL PROCESING Introduction. Branching effects.net . Interrupts. FIR Filters.android. Interrupt effects. Interlocking. TMS320C54XX instructions and Programming. Linear time-invariant systems.jntuworld. Thomson Publications. CODEC programming. Digital Signal Processors. S. 2000. UNIT VIII INTERFACING MEMORY AND I/O PERIPHERALS TO PROGRAMMABLE DSP DEVICES Memory space organization.jwjobs. Direct memory access (DMA). McBSP Programming. Interrupts and I/O. 2005. Digital Signal Processing – Avtar Singh and S. 2. John Wiley. External bus interfacing signals.net || www. Srinivasan.jntuworld. A CODEC-DSP interface example. A Butterfly Computation. Architectures & Features – Lapsley et al.android. J T N W U R O D L www. Parallel I/O interface. Memory interface. Bit-Reversed index generation. Digital Signal Processing – Jonatham Stein. a CODEC interface circuit. Programmed I/O. Computation of the signal spectrum. Overflow and scaling. Bhaskar. TEXT BOOKS 1.jntuworld. TMH. DSP Processor Fundamentals.jwjobs.jntuworld. 2.android.com || www. An 8-Point FFT implementation on the TMS320C54XX. A Multichannel buffered serial port (McBSP). Venkata Ramani and M.net .jwjobs.net UNIT VII IMPLEMENTATION OF FFT ALGORITHMS An FFT Algorithm for DFT Computation. Programming and Applications – B.com || www. 2004.www. Chand & Co.com || www. Architecture. 2004. REFERENCES 1. jwjobs.net LOW POWER VLSI DESIGN UNIT I LOW POWER DESIGN.net .voltage low power design. Design perspective. Integrated Analog/Digital CMOS Process. Integration and Isolation considerations. UNIT V Analytical and Experimental characterization of sub-half micron MOS devices.jntuworld.jntuworld.SOI CMOS. UNIT IV DEVICE BEHAVIOR AND MODELING: Advanced MOSFET models. lateral BJT on SOI.VOLTAGE LOW POWER LOGIC CIRCUITS: Comparison of advanced BiCMOS Digital circuits. J T N W U R O D L TEXT BOOKS 1. limitations. Silicon-on-Insulator.com || www.jwjobs. Bipolar models. CMOS/BiCMOS ULSI low voltage. AN OVER VIEW: Introduction to low.2002 www.jwjobs. UNIT VI CMOS AND Bi-CMOS LOGIC GATES: Conventional CMOS and BiCMOS logic gates. Performance evaluation UNIT VII LOW. MOSFET in a Hybridmode environment. ESD-free Bi CMOS . UNIT III LOW-VOLTAGE/LOW POWER CMOS/ BICMOS PROCESSES: Deep submicron processes .com || www. Digital circuit operation and comparative Evaluation. limitations of MOSFET models. UNIT VIII LOW POWER LATCHES AND FLIP FLOPS: Evolution of Latches and Flip flops-quality measures for latches and Flip flops.jntuworld.android. future trends and directions of CMOS/BiCMOS processes.com || www. UNIT II MOS/BiCMOS PROCESSES : Bi CMOS processes.android.www. low power by Yeo Rofail/ Gohl(3 Authors)-Pearson Education Asia 1st Indian reprint.net || www. and other National and International Conferences and Symposia.com || www.com || www. IEEE Trans Electron Devices.jntuworld.www.android. IEEE J. Digital Integrated circuits . N.Solid State Circuits.jwjobs. J. VLSI DSP systems .jntuworld.jwjobs.com || www.net .Rabaey PH.J 1996 2. J T N W U R O D L www. CMOS Digital ICs sung-moKang and yusuf leblebici 3rd edition TMH2003(chapter 11) 3. John Wiley & sons.net REFERENCES 1.jwjobs. Parhi.android.net || www.jntuworld. 2003 (chapter 17) 4. Time redundancy and software redundancy. totally self-checking PLA design. use of control and syndrome testable design. UNIT VII J T N W U R O D L DESIGN FOR TESTABILITY FOR SEQUENTIAL CIRCUITS: Controllability and observability by means of scan register.jntuworld.net . Test pattern generation for BIST exhaustive testing.net DESIGN OF FAULT TOLERANT SYSTEMS (ELECTIVE III) UNIT I BASIC CONCEPTS: Reliability concepts. Multiple-input Signature Register.com || www.jwjobs. Pseudorandom testing.android. classic scan design.net || www.jwjobs. Failure & Faults. UNIT VI Theory and operation of LFSR. OR-AND-OR design. Relation between reliability and Meantime between failure.com || www. LFSR as Signature analyzer. Design of Totally Self Checking checker. UNIT VIII BUILT IN SELF TEST: BIST concepts.jntuworld. dynamic. pseudo exhaustive testing. UNIT V DESIGN FOR TESTABILITY FOR COMBINATIONAL CIRCUITS: Basic concepts of testability. Level Sensitive Scan Design (LSSD).www. Use of error correcting code. Berger code. UNIT IV FAIL SAFE DESIGN: Strongly fault secure circuits. Reliability and failure rate. Maintainability and Availability. hybrid. constant weight patterns. TEXT BOOKS: www. Low cost residue code. UNIT II FAULT TOLERANT DESIGN: Basic concepts – Static.jwjobs. Storage cells for scan design. Reliability of series. controllability and observability. Triple Modular Redundant System.android. the Reed Muller’s expansion technique. Parallel and Parallel-Series combinational circuits. Siftout redundancy (SMR). fail-safe design of sequential circuits using partition theory and Berger code. SMR Configuration. Checkers using m out of n codes. Generic offline BIST architecture.com || www.jntuworld. Self purging redundancy. UNIT III SELF CHECKING CIRCUITS: Basic concepts of Self checking circuits. net || www.com || www.android. A.www. D.android. M.com || www. Abramovili. Lala – “Fault Tolerant & Fault Testable Hardware Design” (PHI) 2. M. Breues.net .jntuworld. Parag K.jwjobs.com || www.jntuworld.jwjobs.jntuworld. J T N W U R O D L www.A.net 1.jwjobs. Friedman – “Digital Systems Testing and Testable Design” Jaico publications. Classification of Software.jntuworld. petri nets & analysis. Poisson processes.jwjobs. Types of Queues. Object Oriented Simulation. Extend and others.net SYSTEM MODELLING & SIMULATION (ELECTIVE III) UNIT I Basic Simulation Modeling. UNIT V EXOGENOUS SIGNALS AND EVENTS: Disturbance signals.com || www. General purpose simulation packages – Arena. simulating a poison process. Desirable Software features. Techniques for increasing model validity and credibility.jntuworld.jwjobs. Models and Simulation. Linear Systems. Discrete Time Markov processes. the exponential distribution. Simulation of Inventory System. simulating queing systems. state machines.www. Motion Control models. UNIT VI J T N W U R O D L MARKOV PROCESS Probabilistic systems. www.android. Systems. numerical experimentation.net .com || www. Continuous – Time Markov processes. UNIT VII EVEN DRIVEN MODELS: Simulation diagrams. Discrete Event Simulation.com || www. delays. Random walks.android. Alternative approach to modeling and simulation. UNIT IV MODELING TIME DRIVEN SYSTEMS: Modeling input signals.jntuworld. Queing theory. System Integration. Multiple servers. UNIT III BUILDING SIMULATION MODELS: Guidelines for determining levels of model detail. UNIT II SIMULATION SOFTWARE: Comparison of simulation packages with Programming Languages. System encapsulation. Examples of application oriented simulation packages. Simulation of Single server queing system.net || www.jwjobs. Alpha/beta trackers.net || www. Simulation Modeling and Analysis – Averill M.com || www.jntuworld.jntuworld.net . PHI. Searches.jwjobs. TMH. W.Law. 2. An introduction – Frank L.com || www.jwjobs. multidimensional optimization.Severance.jwjobs. System Modeling & Simulation. modeling and simulation methodology.com || www.jntuworld. 2003 REFERENCE BOOKS: Systems Simulation – Geoffery Gordon.www. John Wiley&Sons. 3rd Edition.android.David Kelton. 1978 J T N W U R O D L www.android.net UNIT VIII SYSTEM OPTIMIZATION: System identification. 2001. TEXT BOOKS: 1. linked state machine. UNIT.3 and their speed performance UNIT-IV Finite State Machines (FSM): Top Down Design.www. UNIT-II CPLDs: Complex Programmable Logic Devices: Altera series – Max 5000/7000 series and Altera FLEX logic-10000 series CPLD. PLA. UNIT-V J T N W U R O D L FSM Architectures: Architectures Centered around non registered PLDs. Complex design using shift registers.jntuworld. design flow. Programming. State Transition Table .Logic blocks.jntuworld. Alternative realization for state machine charts using microprogramming. UNIT – III FPGAs: Field Programmable Gate Arrays. One_Hot state machine.jwjobs. Synchronization.android.com || www.com || www. PAL.com || www. Architectures. Case studies Xilinx XC4000 & ALTERA’s FLEX 8000/10000 FPGAs: AT &T ORCA’s (Optimized Reconfigurable Cell Array): ACTEL’s ACT-1. www. State assignments for FPGAs. AMD’s.jwjobs.jntuworld. technology mapping for FPGAs.net || www. Design of state machines centered around shift registers. Finite State Machine-Case study. Use of ASMs in one-hot design method. Extended Petri-nets for parallel controllers.2.net CPLD AND FPGA ARCHITECTURE AND APPLICATIONS (ELECTIVE IV) UNIT –I Programmable logic Devices: ROM. Meta Stability.CPLD (Mach 1 to 5). Petrinets for state machines-Basic concepts and properties. Realization of state machine charts using PAL. Lattice pLSI’s architectures – 3000 series – Speed performance and in system programmability. Applications and Implementation of MSI circuits using Programmable logic Devices.android.jwjobs. routing architecture. CPLD. Applications of onehot design method. encoded state machine. FPGA – Features.VI Design Methods: One –hot design method. Cypress FLASH 370 Device technology.net . J. S. REFERENCES: 1.www. TEXT BOOKS: 1. 1994. UNIT . Prentice Hall.jntuworld.Z.Francis.jntuworld. R. Digital Design Using Field Programmable Gate Array.com || www. Edr.com || www. 4 Edition Jaico Publishing House. data path designing. Field Programmable Gate Array Technology .S. 2007. 1994. 2. J T N W U R O D L www. Mourad. Fundamentals of logic design-Charles H. parallel controllers.net UNIT-VII System Level Design: Controller. J.TINDER. Roth. Trimberger. Field programmable gate array. 2nd Edition. Engineering Digital Design . Brown. System level design using mentor graphics EDA tool (FPGA Advantage).net || www. 2.G.jwjobs. BSP. Digital front end digital design tools for FPGAs & ASICs.net .jntuworld. P.jwjobs. Functional partition. th 3. multiplexers.Vranesic.com || www.RICHARD F.jwjobs.Rose .Chan & S. parallel adder sequential circuits.K. Design flow using CPLDs and FPGAs. Kluwer Academic Publications.VIII Case studies: Design considerations using CPLDs and FPGAs of parallel adder cell. Academic press.android. counters.android. PART-3: Experiments on USB J 1.www. Program and verify I2C-based memory devices. PART-1: Experiments on ARM 9 and DSP Board 1. PART-2: Experiments on I2C Development Board 1.jntuworld. large buffer transfer through direct writes to and reads from DSP memory. Real-time capture and delayed-download capture 2. Basic message transferring concepts in DSP/BIOS™ LINK. 3. Basic data streaming concepts in DSP/BIOS™ LINK. Passively monitor an I2C bus in real-time with bit-level timing down to 20 ns.android. 3. Automatic Speed Detection 4.jwjobs. 2.jwjobs. 2.jntuworld.jwjobs.android.com || www.jntuworld.com || www. High-Speed USB Chirp Detection 3.net . Digital I/O for synchronizing T N W U R O Analyzer D L ****** www. Simulate an I2C master or slave device.net EMBEDDED SYSTEMS LABORATORY The students are required to conduct the following experiments with the necessary Hardware equipment and Software tools. Hardware-based packet suppression 5. A combination of data streaming and messaging concepts in DSP/BIOS™ 4.net || www.com || www.