Vignan BTech Syllabus.pdf

March 21, 2018 | Author: devyani_patil | Category: P–N Junction, Digital Signal, Bipolar Junction Transistor, Low Pass Filter, Electronic Engineering
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CONTENTPage No 1 Academic calendar 2 2 Pulse & Digital Circuits 3 3 Switching Theory & Logic Design 54 4 Electronic Circuit Analysis 102 5 Electromagnetic Theory & Transmission Lines 149 6 Principles Of Electrical Engineering 195 7 Pulse & Digital Circuits Laboratory 250 8 Electronic Circuit Analysis Laboratory 252 9 Electrical Engineering Laboratory 255 ACADEMIC CALENDAR VIGNAN INSTITUTE OF TECHNOLOGY AND SCIENCE DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT ACADEMIC CALENDAR B. Tech Academic Year 2013 - 2014 - II - Semester S.No Event Date th 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. Submission of abstracts of main project by IV years Faculty orientation program Commencement of Class work Spell for UNIT – I Instructions Fresher’s day Spell for UNIT – II Instructions Alumni meet VIGNAN TARANG Spell for Unit-III Instructions st nd Assignment -1/ Unit test-1 on I & II Units Submission of results & week students list to Dept Spell for Unit-IV Instructions University I-Mid-Exam- II & IV Year rd University I-Mid-Exam- III Year Spell for UNIT – V Instructions for II &IV years rd Spell for UNIT – V Instructions for III year LAB INTERNAL-1 Commencement of Special classes for Slow learners Spell for UNIT – VI Instructions for II &IV years rd Spell for UNIT – VI Instructions for III year 16-12-13 28-11-13 to 05-12-13 09-12-13 09-12-13 to 21-12-13 14-12-13 23-12-13 to 04-01-14 29-12-13 02-01-14 to 04-01-14 06-01-14 to 25-01-14 06-01-14 to 10-01-14 20-01-14 27-01-14 to 07-02-14 10-02-14 to 12-02-14 13-02-14 to 15-02-14 13-02-14 to 25-02-14 17-02-14 to 27-02-14 17-02-14 to 22-02-14 24-02-14 26-02-14 to 10-03-14 01-03-14 to 12-03-14 21. 22. 23. 24. Submission of Mini project title along with guide for III year 04-03-13 Spell for Unit – VII Instructions for II &IV years 11-03-14 to 24-03-14 Spell for UNIT – VII Instructions for III year 13-03-14 to 27-03-14 Assignment-II / Unit test on Vth & VIth Units 17-03-14 to 21-03-14 25. Submission of results & week students list to Dept 26. Spell for Unit- VIII Instructions for II & IV year 19-03-14 to 22-03-14 25-03-14 to 05-04-14 27. Spell for Unit- VIII Instructions for III year 28-03-14 to 09-04-14 28. Thanks giving party 01-04-14 29. Farewell to final years from staff and pre final years and student memoir distribution 30. LAB INTERNAL-2 31. University II-Mid-Exam- II & IV Year 03-04-14 32. University II-Mid-Exam- III Year 10-4-14 to 12-4-14 33. Practical Examinations for II Year 10-04-14to 14-04-14 34. Final Project demo and draft copy submission 28-03-14 35. Practical Examinations for III Year 15-04-14 to 17-04-14 36. EXTERNAL PROJECT VIVA (IV years) 15-04-14 37. End Semester Examination 21-04-14 to 03-05-14 38. Commencement of next semester 16-06-14 rd 24-03-14 to 29-03-14 07-4-14 to 09-4-14 Note: class review meeting for II and III year students and faculty on every Thursday at 1:00 pm onwards Cc: principal All staff members HOD,ECE PULSE &DIGITAL CIRCUITS MS. VijayALAXMI Associate. Professor & Mrs.P.Padmaja Assistant Professor COURSEFILE Department of ELECTRONICS AND COMMUNICATION ENGINEERING VIGNAN INSTITUTE OF TECHNOLOGY AND SCIENCE VIGNAN HILLS, DESHMUKHI VILLAGE, POCHAMPALLY (MANDAL) NALGONDA (DISTRICT) - 508284 Sponsored by Lavu Educational Society (Approved by AICTE and Affiliated to JNT University, Hyderabad) COURSE OBJECTIVE Pulse and Digital Circuits Course Objective COURSE OBJECTIVE 1. To understand the concepts of wave shaping and to design various circuits for any application. 2. Understand the principles of digital electronics and abstractions on which the design of digital systems is based. These include TTL and CMOS digital systems. 3. Use these engineering abstractions to analyze and design simple digital circuits. 4. Build digital logic gates and take measurements of such parameters as propagation delay, noise margins, fan-out. Compare the measurements with the behavior predicted by mathematic models and explain the discrepancies. 5. Understand the relationship between the mathematical representation of circuit behavior and corresponding real-life effects. 6. Obtain V-I characteristics of TTL and CMOS inverters and determine their noise margins. 7. Understand the operation of various memory units. 8. Implement multivibrators/timing circuits of specified duty cycles. 9. Understand the principle and operation of BiCMOS and GaAs circuits. 10. Learn VLSI fabrication techniques. 11. Appreciate the practical significance of the systems developed in the course. 12. Understand the, transistor switch, and logic families of TTL and CMOS. 13. Understand how to use and implement ADC and DAC, and how to design the timing circuits. 14. To provide the student with an understanding of the transistor level design of the most commonly used BJT and MOSFET logic families. Emphasis is placed on design and analysis of the logic gate hardware rather than logic design via inter-connection of standard gates. Dynamic response of the logic gates and other specialized pulse and switching circuits is a key topic including transmission line effects for high frequency circuits. Vignan Institute of Technology & Science II Year B.Tech. 2nd Semester Page 5 Syllabus . pulse. Transfer characteristics of clampers. Transistor as a switch. Transistor miller time base generator. Astable Multivibrators and Schmitt trigger using transistors UNIT V: TIME BASE GENERATORS : General features of a time base signal. square and ramp inputs. low pass RC circuits. Clamping circuit theorem. transistor-switching times. Unidirectional and Bi-directional sampling gates. Transfer characteristics of clippers. practical clamping circuits. Emitter coupled clipper. clamping circuits using diode with different inputs. clamping operation. UNIT III: SWITCHING CHARACTERISTICS OF DEVICES: Diode as a switch. Synchronization of a sweep circuit with symmetrical signals. Frequency division in sweep circuit. Transistor Bootstrap time base generator. attenuators. saturation parameters of Transistor and their variation with temperature. OR gates using Diodes. its applications in CRO probe. Transistor clippers. clipping at two independent levels. effect of diode characteristics on clamping voltage. Monostable. UNIT IV: MULTIVIBRATORS : Analysis and Design of Bistable. Current time base generators. Diode Transistor Logic. Reduction of pedestal in gate circuits. Sine wave frequency division with a sweep circuit.VII: SAMPLING GATES: Basic operating principles of sampling gates. Comparators. 2nd Semester Page 7 . step. Ringing circuit UNIT II: NON-LINEAR WAVE SHAPING : Diode clippers. UNIT VI: SYNCHRONIZATION AND FREQUENCY DIVISION : Principles of Synchronization. Resistor. Vignan Institute of Technology & Science II Year B. Applications of sampling gates. piecewise linear diode characteristics. UNIT.Pulse and Digital Circuits Syllabus SYLLABUS UNIT I:LINEAR WAVESHAPING: High pass.Tech. Design of transistor switch. Miller and Bootstrap time base generators – basic principles. Transistor Logic. RL and RLC circuits and their response for step input. UNIT-VIII: REALIZATION OF LOGIC GATES USING DIODES & TRANSISTORS: AND. their response for sinusoidal. applications of voltage comparators. methods of generating time base waveform. Astable relaxation circuits. RC network as differentiator and integrator. Monostable relaxation circuits. Break down voltage consideration of transistor. Wave Generation and Shaping . PHI.com/ JOURNALS 1. Circuits and Systems (ISSN: 0975-4768) Active and Passive Electronic Components (ISSN: 0882-7516) Journal of Electronic Testing (ISSN: 0923-8174) Vignan Institute of Technology & Science II Year B. Pulse. REFERENCE BOOKS 1. 3. Millman and H.David A. 2. http://www.. 3.L. 2002 . McGraw-Hill. 4th Edn.guidecircuit. 4.com/ http://www. 1991. 2. Pulse and Digital Circuits – A.R. Pulse.onsemi.Tech. Strauss. Digital Circuits and Computer Fundamentals .htm http://buildinggadgets.Venkataraman. Anand Kumar. Solid State Pulse circuits . Digital and Switching Waveforms .Pulse and Digital Circuits Syllabus TEXT BOOKS 1.kpsec.htm http://www. WEBSITES 1. IEEE Transaction on Electronic Devices (ISSN: 0018-9383) Journal of Active and Passive Electronic Devices (ISSN: 1555-0281) International Journal of Micro and Nano Electronics. Bell. 5. 2. 2. 2nd Semester Page 8 . 4.freeuk.com/symbol.com/index_circuitlinks. 3.J. Taub. PHI. 2005. STUDENT'S SEMINAR TOPICS . Ringing circuits 3. Miller time base generators – basic principles 10. 2nd Semester Page 10 . High pass filter response for square-wave input 2. UJT relaxation oscillator 7. Principles of Synchronization 8.Tech.Pulse and Digital Circuits Seminar Topics STUDENTS SEMINAR TOPICS 1. Zener slicer working 4. Bootstrap time base generators – basic principles Vignan Institute of Technology & Science II Year B. Triggering methods of bistable multivibrator 6. Diode Switching times 5. Working principle and VI characteristics of UJT 9. LECTURE PLAN . Response of high pass and low pass circuits for: Sine input 1 Black board and Chalk 6. Attenuators 1 Black board and Chalk 10. Step and Pulse input 1 Black board and Chalk 7. Different types of inputs 1 Black board. Diode clippers 1 Black board and Chalk 16.No No of Periods Method of Teaching Actual Date of Completion Remarks UNIT I:LINEAR WAVESHAPING 1. Chalk and LCD Projector 5. LINEAR WAVESHAPING: Introduction 1 Black board and Chalk 4. Response of RL circuits for step input 1 Black board. Applications of attenuators in CRO probe 1 Black board and Chalk 11. Response of RLC circuit for step input 1 Black board and Chalk 13. Square input 1 Black board and Chalk 8. Ringing circuits 1 Black board and Chalk Black board and Chalk --- UNIT II: NON-LINEAR WAVE SHAPING 14.Tech 1st Semester Page 12 . Ramp input 1 Black board and Chalk 9.Pulse and Digital Circuits Lecture Plan LECTURE PLAN NAME OF THE TOPIC Proposed Date S. Introduction 1 --- 2. Introduction to PDC 1 3. NON LINEAR WAVE SHAPING: Introduction 1 Black board and Chalk 15. Chalk and LCD Projector 12. Clipping circuits 1 Black board and Chalk Vignan Institute of Technology & Science II B. Pulse and Digital Circuits Lecture Plan 17. Comparators 1 Black board and Chalk 23. Chalk and LCD Projector 33. Chalk and LCD projector 29. Clamping operation 1 Black board and Chalk 25. Effect of diode characteristics on clamping voltage 1 UNIT III: SWITCHING CHARACTERISTICS OF DEVICES 28. Practical clamping circuits 1 Black board. Chalk and LCD Projector 27. Breakdown voltage consideration of transistor 1 Black board. Chalk and LCD Projector UNIT IV: MULTIVIBRATORS 34. Saturation parameter of transistor and their variation with temperature 1 Black board. Clamping circuits using diode with different inputs 1 Black board and Chalk 26. Multivibrators 1 Black board and Chalk 35. Chalk and LCD Projector 32. Applications of voltage comparators 1 Black board and Chalk 24. Analysis of waveforms 1 Black board and Chalk 19. Analysis of Bistable multivibrators. Transfer characteristics of clippers 1 Black board and Chalk 21. piecewise linear diode characteristics 1 Black board. Design of transistor switch 1 Black board. Chalk and LCD Projector 30. Emitter coupled clipper 1 Black board and Chalk 22. Transistor as a switch 1 Black board. Transistor switching times 1 Black board. Chalk and LCD Projector 31.Tech2 ndSemester Page 13 . Clipping at two independent levels 1 Black board and Chalk 20. 1 Black board and Chalk Vignan Institute of Technology & Science II B. Transistor clipper 1 Black board and Chalk 18. Diode as a switch. Tech2 ndSemester Page 14 . Design monostable Multivibrators 1 Black board and Chalk 39. Chalk and LCD Projector 54. Frequency division in sweep circuit 1 Black board. Transistor miller time base generator 1 Black board and Chalk 47. Design astable Multivibrators 1 Black board and Chalk 41. Analysis monostable Multivibrators 1 Black board and Chalk 38. Miller time base generator. Methods of generation of time base waveform 1 Black board and Chalk 44. General features of a time base signal 1 Black board and Chalk 43. Principles of Synchronization. Chalk and LCD Projector 51. Schmitt trigger using transistors 1 Black board and Chalk UNIT V: TIME BASE GENERATORS 42. Bootstrap time base generator 1 Black board and Chalk 46. frequency division 1 Black board and Chalk 50. Synchronization in monostable relaxation 1 Black board and Chalk 53. Analysis astable Multivibrators 1 Black board and Chalk 40. Frequency division in monostable relaxation circuits 1 Black board. Transistor bootstrap time base generator 1 Black board and Chalk 48. 1 Black board and Chalk 45. Frequency division in astable relaxation circuits 1 Black board and Chalk Vignan Institute of Technology & Science II B. Synchronization in astable relaxation circuits 1 Black board and Chalk 52. Design of Bistable Multivibrators 1 Black board and Chalk 37. Current time base generator 1 Black board and Chalk UNIT VI: SYNCHRONIZATION AND FREQUENCY DIVISION 49.Pulse and Digital Circuits Lecture Plan 36. Unidirectional sampling gates 1 Black board and Chalk 59. Totempole nand gate 1 69. Revision on I and II Units 1 Black board and Chalk 71. Revision on III and IV Units 1 Black board and Chalk 72. 1 Black board and Chalk 66. Sine wave frequency division with a sweep circuit 1 Black board and Chalk UNIT. Introduction to logic gates 1 Black board and Chalk 65. Problems 1 Black board and Chalk 70. Diode transistor logic 1 68. Basic operation principles of sampling gates 1 Black board and Chalk 58. Chalk and LCD Projector II B. Bi. Application of sampling gates. Revision on VII and VIII Units 1 Black board and Chalk Vignan Institute of Technology & Science Black board. Reduction of pedestal in gate circuits 1 Black board and Chalk 61.VII: SAMPLING GATES 57. 1 Black board and Chalk UNIT-VIII: REALIZATION OF LOGIC GATES USING DIODES & TRANSISTORS 64.Tech2 ndSemester Page 15 . Bi. Synchronization of a sweep circuit with symmetrical signals 1 Black board and Chalk 56. Comparision of all logical families.directional sampling gates using transistor 1 Black board and Chalk 62. OR. Revision on V and VI Units 1 Black board and Chalk 73. Transistor logic 1 Black board and Chalk 67. Chalk and LCD Projector Black board. Four diode and six diode sampling gate 1 Black board and Chalk 63. AND & NOT gate using diodes and transistors.Pulse and Digital Circuits Lecture Plan 55.directional sampling gates using diode 1 Black board and Chalk 60. LEARNING OBJECTIVES . Tech2 nd Semester Page 17 . Explain transistors clippers. Define comparator. 8. 6.Pulse and Digital Circuits Learning Objective LEARNING OBJECTIVES UNIT I: LINEAR WAVE SHAPING At the conclusion of this unit student will 1. 13. 10. 7. Explain clipping at two independent levels using diode.Define forward recovery time. 2. Explain different types of inputs signals. 3. 9. Explain positive clipper. 14. Explain clamping circuit theorem 11. Explain single ended clipping circuits. Explain positive clamping. Explain high pass RC circuit. 4. Explain RC network as differentiator. Vignan Institute of Technology & Science II B. 3.Explain how a diode acts as a switch. UNIT II: NON LINEAR WAVE SHAPING At the conclusion of this unit student will 1. Explain diode clippers. Explain RC network as integrator. Explain voltage comparator circuits. 12. Explain the function of rectifier UNIT III: SWITHING CHARACTERISTICS OF DEVICES At the conclusion of this unit student will 1. Explain RL and RLC circuits. Explain transfer characteristics of clamper. Name the devices that can be used as switches. 6. Define ringing circuit. Define linear wave shaping. 5. 2. 4. Explain low pass RC circuit 3. 5. 9. 8. Define attenuators. 7. Explain negative clipper. Define clamping. Explain negative clamping. 2. Explain transistor switching time. 5. 8. 9.Define the term upper triggering point.Define ac coupling. 6.Explain symmetrical triggering.Define triggering.Define resolution time.Discuss the application of bistable multivibrator. 13. 12.Define fall time.Define the term lower triggering point. 3.Define loop gain. Vignan Institute of Technology & Science II B. 15. 10.Discuss the types of multivibrator. 9. 18.Define transition time of a diode.Explain zener break down. 6.Explain collector catching diodes.Define resolving time. 16.Define rise time.Define reverse recovery time. 4.Define storage time. 19. 7.Define dc coupling. 5.Explain monosatable multivibrator. 11.Pulse and Digital Circuits Learning Objective 4.Define quasi stable state.Explain the stable state of a binary.Define transition time.Write a short note communicating capacitor. 12. 14.Explain unsymmetrical triggering.Explain diode switching time. 8. 15.Explain Schmitt trigger. 14.Justify the transistor acts as a switchList out the applications of BJT 10. 7. 20.Explain the three region of operation of a transistor. UNIT IV: MULTIVIBRATORS At the conclusion of this unit student will 1.Define storage time of a diode. 17.Explain avalanche break down. 13. 16. 2.When does the transistor acts as a closed switch and an open switch.Define multivibrator. 21. 11.Define settling time.Tech2 nd Semester Page 18 . Compare sine wave synchronization with pulse synchronization. 2.Define displacement error.Explain synchronization with frequency division.Explain how the synch signal affects the frequency of operation of the sweep generator.Explain relaxation circuit.Explain frequency division by an astable blocking oscillator. 6.Explain sampling gates.Explain synchronization of a sweep circuit with symmetrical signals.Explain synchronization on one to one basis. 3. 10. 4. 5. UNIT. 11. 3.Drive the relation between different types of errors. 8. 10. 5.Define restoration time.Explain frequency division by an astable mutlivibrator. Unit V: TIME BASE GENERATORS At the conclusion of this unit student will 1.Why time circuits are called sweep circuits.Explain astable multivibrator.Explain frequency division with respect to a sweep circuit. UNIT VI: SYNCHRONIZATION AND FREQUENCY DIVISION At the conclusion of this unit student will 1.Define transmission error.Explain the principles of synchronization.Define sweep time.List the application of time base generators. 6.Define slope error.Explain the working of transistor current time base generators. 2.Tech2 nd Semester Page 19 . 9. 7. Vignan Institute of Technology & Science II B.VII: SAMPLING GATES At the conclusion of this unit student will 1. 11. 9.Explain the principle of miller ad boot strap time base generators. 4.Pulse and Digital Circuits Learning Objective 22.Name some negative resistance used in relaxation oscillators. 7. 12.Explain the methods of generating a time base waveform. 8.Explain synchronization of sweep generator with pulse signals. Give some example of it. Pulse and Digital Circuits Learning Objective 2.Explain diode transistor logic. 7.Draw the NOT logic using transistor.Draw the OR logic using diodes.Define pedestal. 9. 2.Why sampling gates are called as linear gates.Differentiate sampling gate and logic gates. 6.Explain the working of bidirectional gates using transistor.Explain the working of four diode gate. 5. 10. 5.Draw the AND logic using diodes. 4. UNIT-VIII: LOGIC GATES At the conclusion of this unit student will 1. 3.Tech2 nd Semester Page 20 .Define gate signal. Vignan Institute of Technology & Science II B.Explain the working of six diode gate.Explain the transistor logic.Explain bidirectional sampling gate.Explain unidirectional sampling gate. 4. 3. 8. OBJECTIVE TYPE QUESTIONS . The condition for perfect compensation in an attenuator is a) R1 = R2 b) C1=R2C2/ R1 c) C1= C2 d) None [ ] a) RC = T b) RC << T c) RC >>T d) None 8. The response of a RLC circuit to a step input for damping constant k = 1. The condition for a RLC circuit to ring for many cycles is ( k is damping constant) a) k > 1 b) k < 1 c) k = 1 d) None [ ] 11. but attenuates high frequency is called [ ] a) High pass RC circuit b) Low pass RC circuit c) Both a & b d)None 9. The circuit which passes low frequencies readily . A High pass RC circuit acts like a differentiator for the condition ( RC = Time constant of the circuit & T= Time period of the input signal ) [ ] a) RC = T b)RC>>T c) RC<<T d) None 4. The response of an integrator circuit to a square wave input is a) sine wave b) triangular wave c) pulse d) ramp [ ] 7. corresponds to [ a)over damping b) critical damping c) under damping d) none 12. A low pass RC circuit acts like an integrator for the condition ( RC = Time constant of the circuit & T= Time period of the input signal ) [ ] 6. the output (Vo) is taken across a) Resistor b)capacitor c) inductor d) none [ ] 10. In a high Pass RC circuit. Attenuator is used to [ a)Reduce the amplitude of a signal b) increase the amplitude of a signal c) change the frequency of the signal d) none Vignan Institute of Technology & Science ] ] ] II B. The response of a high pass RC circuit to a step input of amplitude V is a) V(1-e-t/RC ) b) Ve-t/RC ) c) V d)None [ ] 2. The response of a series RL circuit to a pulse input for smaller time constant is a) ramp b) exponential c)spikes d) None [ 13.Tech2 nd Semester Page 22 .Pulse and digital circuits Objectives Questions OBJECTIVE TYPE QUESTIONS UNIT I: LINEAR WAVE SHAPING 1. The response of a differentiator circuit to a pulse input is a) ramp b) spikes c) square d) none [ ] 3. The response of a low-pass RC circuit to a step input is a) ramp b) square wave c)exponential rise d) exponential decay [ ] 5. a comparator is a basic building block in a system used to analyze the -------.The breakdown occurring due to direct rupture of bonds because of existence of strong electric field is a)avalanche breakdown d)none[ ] 6. the semiconductor diode current equation is given by a) I=(1-eV/ηVt ) b) I=Io (e1/ηVt -1) c) I=Io (eV/ηVt -1) ] d) I=Io (1-e1/ηVt ) 4.distribution of noise generated in active device [ a) Both frequency and phase b) Amplitude c) Phase ] d) Frequency 5. when ramp input is applied to a High pass RC circuit for the condition RC >> T is [ ] a) T/RC b)T/4RC c) T / 8RC d) T / 2RC 16. zener diode has ---------.Pulse and digital circuits Objectives Questions 14) The time constant of a series RL circuit is a) LR b) L/R c) R/L d) None [ ] 15 The expression for transmission error (et).Vm 8. The circuit which converts sinusoidal wave form into square under some special condition is [ a) Dc restorer b) Double ended clamper c) Attenuator d) Clamper 2.Tech2 nd Semester Page 23 . when ramp input is applied to a Low pass RC circuit for the condition RC << T is [ ] a) 2RC / T b) 4RC / T c) RC / T d) None ANSWERS: 1 (b) 9 (a) 2 (b) 10 (b) 3 (c) 11 (b) 4 (a) 12(c) 5 (c) 13 (a) 6 (b) 14 (c) 7 (b) 15 (d) 8 (b) 16 (b) UNIT II: NON LINEAR WAVE SHAPING 1.Under steady state the output is given by.temperature coefficient a) some times positive and sometimes negative b) Only NEGITIVE c) Both positive and negative d) Only positive [ ] [ ] 3. when the circuit and input are as shown in the figure[ a) Vo = Vi .The circuit which converts sinusoidal wave form into square under some special condition is [ ] a) Dc restorer b) Zener breakdown c) Forward breakdown b) Double ended clamper c) Attenuator d)none 7. The expression for transmission error (et ).the application of voltage comparartor a) ohm meter b) voltmeter c)ammeter d) b)R+L c) RL 10the disadvantage of shunt clipper Vignan Institute of Technology & Science d) Vo = Vi / Vm [ ] [ ] [ ] phasemeter 9.time constant or RLciruit a) R/L ] d) L/R II B.Vm b) Vo = Vi + Vm c) Vo = Vi . common base configurations is little used because [ ] a) High voltage gain b) High current gain c) It has low input impedance d) High input impedance 8.the following condition must be satisfied [ ] 2.8 v d) 0.the negative clamper is also called [ ] a) Positive peak clamper b) Negative peak clamper c) Positive peak clipper d) Negative peak clipper ANSWERS: 1 (d) 2 (b) 3 (c) 4 (b) 5 (b) 6 (d) 7 (c) 8 (d) 9 (d) 10 (a) 11 (a) UNIT III: SWITHING CHARACTERISTICS OF DEVICES 1.rise in temperature [ ] a) toff =tf +ts a) 30 c b) toff =tf +ton b) 50 c c) toff =tfd +ts c) 70 c d) toff =ton +t.when does the transistor act as a closed switch a) both junctions are forward biased b) input junction is reverse biased and output junction is forward biased Vignan Institute of Technology & Science II B.1v c) 0.if the transistor is indeed in saturation .3 v c) 0.1v b)0. smallest times between two successive triggers is ----------a) Restoring time b) Storage time c) Delay time [ ] [ ] [ ] [ ] d) Rise time 10.Pulse and digital circuits Objectives Questions a) Round shaped edges of input waveform b) No transmission of signal c) Transmits same signal d) Doubles amplitude of input waveform 11.s d) 10 c 5) The Vce of the n-p-n transistor is a)-0.temperature coefficient a) some times positive and sometimes negative b) Only NEGITIVE c) Both positive and negative d) Only positive 11) Turn off time of the transistor is =------a) toff =tf +ts b) toff =tf +ton c) toff =tfd +ts d) toff =ton +ts 12.7 v b) 0.Tech2 nd Semester Page 24 . the Vce (sat) of Si n-p-n transistor at 27 c is [ ] a) 0.rise in temperature [ ] a) ic=iB/hfe(min) b) iB>iC/hfe(min) a) 30 c C) iB=iC+Vce d) iB=iC b) 50 c c) 70 c d) 10 c 3. Turn off time of the transistor is =------- [ ] 4T The reverse saturation current increases approximately for every ------.The reverse saturation current increases approximately for every ------.1 v 9.7 v [ ] [ ] d)0 v 6.zener diode has ---------.the capacitance which appears across a reverse biased function of a diode is called a) Diffusion capacitance b) Fixed capacitance c) Transition capacitance d) Valuable capacitance 7. transiton capacitance of diode is given as λn/(VB)3 a) b) λ/(VB)n [ ] c) n/VB d) (VB)n /λ 15.which of the following is the fastest switching device a) MOSFET b) DIODE c) JFET [ ] b) minority carriers c)concentration of majority carriers d) none of the above 18. m V /c c) 1.Tech2 nd Semester Page 25 .in a transistor leakage current mainly depends on a) temperature [ b) 15 c) 1 [ ] d) 10 19.for an ideal p-n junction diode the current I=Io (eV/ηVt -1) than what is the value η for Ge a)5 ] d)BJT 17.a large signal approximation which often leads to a sufficient accurate solution is the -----------representation a) Ebers model [ b) Hybrid model c) Pi model ] d) Piecewise linear 22.5 m V /c to 8.5 V /c to -2.0 m V /c 20the maximum reverse biasing voltage which may be applied before breakdown between collector and base terminals is a) BVCEO [ b) VCE c) VCB ] d) BVCBO 21.5 m V /c to -8. if the VCB of n-p-n transistor in CE configuration is negative when the transistor is in a) Active region b) Cut off region c) Saturation region [ ] d) Inverted ANSWERS: Vignan Institute of Technology & Science II B.Pulse and digital circuits Objectives Questions c) input junction is forward biased and output junction is reverse biased d) both junctions are reverse biased 13. at constant base and collector current forward B-E voltage has typical temperature sensitivity in the range of [ ] a) -7.the base width in a junction transistor is deliberately chosen small so that [ ] a) the concentration of injected carrier is small b) the majority carriers easily reachs the collector c) the electric field s large d) to reduce the recombination of injected minority carriers 16.0 m V /c b) -1. the collector to emitter breakdown voltage with base not open ckt is BVCER is given by [ ] BVCBOn√ (1-ICORB/Vγ) b) BVCEO√ (1-ICORB/Vγ) c) BVCBO√ (1-ICORB/Vγ) d) BVCEOn√ (1-ICORB/Vγ) 24.in the diode the time required for minority charge carriers to move into the other side of the PN junction and become majority charge carrier is called a) Delay time b) Transition time [ c) Reverse recovery time ] d) Storage time 23.when does the transistor act as open swit [ ] a) input junction is reverse biased and output junction is forward biased b) both junctions are forward biased c) both junctions are reverse biased d) input junction is forward biased and output junction is reverse biased 14.5m V /c to -2 m V /c d) -7. the commutating capacitor are also called a) speed up capacitor b) varicap c) tuning capacitor d) delay capacitor Vignan Institute of Technology & Science II B.The Schmitt Trigger is also called as ] [ a. gating circuit c. T=0.the pulse width or gate width of monoshot is a) RC b) 2 RC c) 0. ic sat=4 mA.63RC c. T=1. collector coupled binary c.Pulse and digital circuits Objectives Questions 1 (b) 9 (a) 2 (d) 10 (b) 3 (d) 11 (a) 4 (a) 12 (a) 5 (b) 13 (c) 6 (c) 14 (b) 7 (c) 15(d) 8 (b) 16(d) 17 (a) 18 (c) 19 (b) 20 (d) 21 (d) 22(d) 23(a) 24(c) UNIT IV:MULTIVIBRATORS 1. Bistable Multivibrator c.69RC b. none 11. square wave generator ] [ ] [ ] [ ] [ ] [ ] [ ] d. the capacitor which assists the binary in making abrupt transition between states are called [ ] a)delay b) Storage c) commutating d) translation 4.2V 14. gating circuit c. any of the two d. The time period of the quasi stable state in a Monostable Multivibrator is given by a. if VTP=5.312 then the value of hysterisis in schimmit trigger is a) 1.81 V b) 5.Tech2 nd Semester Page 26 . Astable Multivibrator d.assume n-p-n(Si) transistor then Rc is = [ ] a) 2.12 and LTP =3. monostable vibrators generates [ ] a) Pulse wave form b) Ramp signal c) Sine wave d) Square wave 5.hfe(min)=20. voltage to frequency converter b.in a design of fixed bias binary VCC =VBB =12v . Schmitt trigger b. Monostable Multivibrator b. Schmitt Trigger [ 7. The Monostable Multivibrator has one of the following applications a. none 8.38RC d.4 V c) 4. -------.69 RC d)none 13. none 9.5 kΩ d) 100Ω 2) The duration of quasi stable state of a mono shot is----- [ ] a) Fall gate b) Gate time c) Storage time d) Recovery time 3.925 kΏ b) 200Ω c) 0. comparator d.8 V d) 3. T=0.Are basically regenerative circuits comprising of two cross coupled active devices [ ] a)filters b) Multivibrators c) Attenuators d) Clampers 6.The Astable Multivibrator has one of the following applications a. emitter coupled binary b.T=RC 12.Which one of the following circuits converts any arbitrary waveform into a square wave a. Waveform can have either positive slope or negative slope [ ] (a) Ramp (b) square (c) Trapizoidal (d) Rectangular Vignan Institute of Technology & Science II B. ic(max) =2 mA. Sweep speed error is defined as (a) initial ramp speed/final ramp speed (b) initial ramp speed-final ramp speed/ initial ramp speed (c) initial ramp speed +final ramp speed/initial ramp speed (d) final ramp speed/ initial ramp speed 4.no of triggers required for monostable multi to change from stable state to quasi stable state and vice versa [ ] [ ] 21. the schmit trigger can be used as a a) filter [ b) attenuator c) comparator d) clamper 17.hfe=20 a) 1Ω b) 4. a ckt which can indefinitely exist in either of two stable state and which can be induced to make abrupt transition from one state to other by means of external excitation a) monoshot b) oscillator c) binary [ ] d) attenuator 18. monostable multi vibrators generates a) Square b) Pulse c) Sine d) Ramp specifications f=10 KHZ .35 KΩ c) 3 KΩ d) 2KΩ 22. The input impedance of bootstrap integrator Is [ ] [ ] [ ] (a) low (b) high (c) moderate (d) Too high 2.Tech2 nd Semester Page 27 .the binary is sometimes referred to as a) Norton’s ckt [ b) Eccless Jordon ckt c) Thevinins ckt ] d) Millimans ckt ANSWERS: 1 (a) 12 (c) 2 (b) 13 (a) 3 (c) 14 (a) 4 (b) 15 (b) 5 (b) 16 (c) 6 (d) 17 (c) 7 (a) 18 (c) 8 (a) 19 (a) 9 (b) 20 (b) 10 (a) 21 (b) 11 (a) 22(b) UNIT V: TIME BASE GENERATORS 1.Vcc=9 V. find the value of collector resistor in a collector coupled stable multi for the following [ ] a) 1 b) 2 c) 3 d) 4 20. A set of coil is called as (a) magnetic coil (b) LOT (c) yoke (d) sweep coil 3. a stable state of binary is one in which the current and voltages satisfy kirrchofs laws and are constant and the condition satisfied that loop gain is a) =1 b) <1 c) >>1 ] [ ] d) >1 16.Pulse and digital circuits Objectives Questions 15. which of the following is the advantage of emitter coupled over collector coupled multivibrator a) inherently self starting b) low power dissipation c) less noisy d) only one trigger signal is enough 19. suply voltage and transistor parametres 6.Pulse and digital circuits Objectives Questions 5. Difference between the input and output divided by the input is called as (a) transistor error (b) et (c) translational error (d) translational & transmission error 9. Millers sweep circuit produces type of waveform [ ] (a) negative going ramp (b) Sinusodalwave (c) positive going ramp (d) squarewave 15. For a basic Bootstrap integrator the transistor is connected as (a) common base (b) common emitter (c) Common collector configuration (d) emitter follower 19. recycling arrangement.Tech2 nd Semester Page 28 .Non-return to zero (b) Rise or fall. The biggest disadvantage of Bootstrap using Darlington circuit is (a) gain greater than unity (b) gain of the composite amplifier is smaller than each stage (c) gain less than unity (d) gain of comosite amplifier is too large 14. Slope error is given by (a) final slope/initial slope [ ] [ ] (b) initial slope+final slope/final slope (c) initial slope-final slope/initial slope (d) Initial slope/final slope 13. supply voltage and gain (d) loop gain. The duration during which the voltage level decreases to the initial level is Known as [ ] [ ] [ ] (a) Trace (b) Retrace interval (c) sweep interval (d) Signal reconstruction 8. In integrator neither terminals of the capacitor are connedcted to ground (a) Emitter follower (b) Source follower (c) Bootstrap (d) Miller Integrator 11. The three different stages of ramp waveforms are (a) Recycling . (c) Rise or fall. Millers Integrator generates a ramp voltage [ ] (a) sinusoidal (b) non-linear (c) linear (d) Cosinusoidal 16.transmisssion error (a) Transmission error (b) True (c) Sweep error (d) False 17. Current time base generators are used in [ ] [ ] [ ] (a) In Radar screen scanning (b) Tv scanning (c) Sonar application (d) where large raster area is to be scanned 10. The maximum deviation in rate of change of sweep voltage with time is called differential linearity Vignan Institute of Technology & Science II B. recycling (d) Recycling only 12. The variations in phase delay occur due to variations in factors like and [ ] (a) Q point only (b) current gain & voltage gain (c) Q-point. The error arising due to transmission through a linear network is known as . Current time base generators are used in [ ] [ ] (a) In Radar screen scanning (b) Tv scanning (c) Sonar application (d) where large raster area is to be scanned 18. return to original. The phenomenon of charging and discharging of a capacitor in a pulse digital circuit is called as (a) Relaxation circuit (b) Timing circuit (c) Stable circuit (d) unstable circuit 7. one Frequency being twice the other then it is termed as [ ] (a) frequency matching (b) No synchronization occurs (c) synchronization (d) synchronization with frequency division 6.Pulse and digital circuits Objectives Questions (a) False (b) Sweep voltage (c) Sweep error (d) True 20. If synchronisation is achieved with different frequencies . one Frequency being twice the other then it is termed as [ ] [ ] (a) No synchronization occurs (b) frequency matching (c) synchronization (d) synchronisation with frequency division 2. A sampling gate is also termed as Vignan Institute of Technology & Science [ ] II B. When two generators produce waveforms at different frequencies..Tech2 nd Semester Page 29 . If synchronization is achieved with different frequencies . it is Essential for proper synchronization that the frequency of one generator is an of that of the other generator. When two generators with equal frequencies run in synchronism the Synchronization is said to be on (a) many to one (b) one-to-one basis (c) one-to many (d) multiplexing 7. The biggest advantage of Triggered sweep circuit is [ ] (a) slow wave operation (b) Free running operation (c) Complex operation (d) Fast running operators 8. When two generators with equal frequencies run in synchronism the Synchronisation is said to be on (a) one-to many (b) multiplexing (c) one-to-one basis (d) many to one [ ] [ ] 4. The variations in phase delay are called as (a) Sampling gates (b) phase jitters (c) phase shifters (d) Blocking jitters 3.. one Frequency being twice the other then it is termed as [ ] (a) No synchronization occurs (b) synchronization (c) frequency matching (d) synchronization with frequency division 9. (a) odd multiples (b) secondary harmonies (c) even multiples (d) integral multiple 5. If synchronization is achieved with different frequencies . ie. ie. ie.. The Sweep speed error in a current time base generator is given by [ ] (a) IL[RL + Rcesat]/Vcc (b) (VCC/RL)IL (c) (RL/VCC) (d) [RL + RCE]/Vcc ANSWERS: l (b) 11 (b) 2 (c) 12 (c) 3 (b) 13 (b) 4 (a) 14 (a) 5 (d) 15 (c) 6 (a) 16 (c) 7 (b) 17 (b) 8 (b) 18 (b) 9 (b) 19 (a) 10 (d) 20 (a) UNIT VI: SYNCHRONIZATION AND FREQUENCY DIVISION 1. Pulse and digital circuits Objectives Questions (a) linear gate (b) time-selection gate (c) time selection & linear gates (d) non-linear gate 10. Sampling gate for which input voltage is (a) dc only (b) Sampling of acsignal (c) ac only (d) Either dc or ac 14. stray signals are (a) Introducing distortion (b) affects synchronization severely (c) doesn’t affect synchronization (d) unwanted noisy signals 16. If synchronization is achieved with different frequencies . ie. Synchronization of sweep circuit can be obtained by [ ] (a) Non identical phase signals (b) Symmetrical signals (c) identical phase signals (d) unsymmetrical signals 18. In a Sinusoidal synchronization signal UJT is used as a switch beause (a) negative resistance voltage controlled device(b) negative resistance current controlled device (c) voltage divider (d) Current divider 17. Monostable relaxation circuit is used as a (a) time division (b) both time and frequency (c) frequency division (d) only frequency multiplexing 12. The biggest disadvantage of sampling gate is (a) fast rise of control voltage (b) the slow rise of control current (c) the slow rise of control voltage (d) Risetime fall time ANSWERS: Vignan Institute of Technology & Science II B. a divider circuit with a division factor n can be built (a) TO < nTp (b) TO > nTp (c) TO = 2nTp (d) TO = nTp 13. one Frequency being twice the other then it is termed n as [ ] [ ] (a) frequency matching (b) No synchronization occurs (c) synchronization (d) synchronization with frequency division 20. Monostable relaxation circuit is used as a (a) both time and frequency (c) only frequency multiplexing [ ] (b) time division (d) frequency division 19..Tech2 nd Semester Page 30 . Synchronization of sweep circuit can be obtained by [ ] [ ] [ ] [ ] (a) Non identical phase signals (b) identical phase signals (c) Symmetrical signals (d) unsymmetrical signals 11. By making —————. When two generators with equal frequencies run in synchronism the Synchronisation is said to be on a [ ] [ ] [ ] (a) many to one (b) multiplexing (c) one-to many (d) one-to-one basis 15. Chopper amplifier is also known as [ ] (a) Waveform generator (b) modulator (c) signal generator (d) Non-linear wave form generator 11. The interval of time is selected by means of an externally applied signal is Termed as (a) ramp (b) square wave (c) sync pulse (d) gating signal 7. Advantages of Diode sampling gate over the transistor Sampling gate are (a) Linearity only (b) Non-linearity of operation and elimination of pedestal (c) Linearity of operation and elimination of pedestal (d) stable operating point achievement 5. The biggest disadvantage of sampling gate is 10 (c) 20 (c) [ ] [ ] (a) the slow rise of control voltage (b) the slow rise of control current (c) Rise time fall time (d) fast rise of control voltage 2. [ ] (a) XOR gate (b) Sampling gate (c) OR gate (d) nor gate Vignan Institute of Technology & Science II B. Chopper amplifier is also known as (a) modulator [ ] [ ] (b) signal generator (c) Non-linear wave form generator (d) Waveform generator 6. A is basically a transmission circuit which allows input signal to pass through it during selected interval and blocks its passage outside this this time interval. Sampling gate for which input voltage is [ ] [ ] (a) ac only (b) Sampling of acsignal (c) dc only (d) Either dc or ac 4. A Sampling gate which can handled the input signal excursion of both polarities is termed as [ ] (a) multidirectional gate (b) n-directional gate (c) Bi-directional gate (d) unidirectional gate 9.VII :SAMPLING GATES 1.Pulse and digital circuits 1(d) 11 (c) 2 (d) 12 (b) 3 (c) 13 (d) Objectives Questions 4 (d) 14 (d) 5 (d) 15 (b) 6 (b) l6 (b) 7 (b) 17 (d) 8 (d) 18 (d) 9 (c) 19 (d) UNIT. The parametres of a Non-ideal switch are [ ] (a) Analog channel & digital control line control parameters (b) Analog & Digital (c) Digital and analog control (d) Digital switch control 10. The parameters of a Non-ideal switch are (a) Digital and analog control (b) Digital switch control (c) Analog & Digital (d) Analog channel & digital control line control parameters 3.Tech2 nd Semester Page 31 . The time interval for transmission is selected by means of an externally applied signal Called as (a) Gating signal (b) control signal (c) Logic signal (d) Threshold signal [ ] 8. Which of the following logic family is called TRISTATE gate (a) TTL (b) RTL (c) ECL (d) DTL 5. Differential signals are used in the following logic family (a) .Pulse and digital circuits Objectives Questions ANSWERS: l (a) 2 (d) 3 (d) 4 (c) 5 (a) 6 (d) 7 (a) 8 (c) 9 (a) 10 (b) 11(b) UNIT-VIII: LOGIC GATES 1. Complementary output is available in which of the following logic families [ ] [ ] [ ] [ ] [ ] (a) RTL (b) TTL (c) ECL (d) DTL 2.Tech2 nd Semester Page 32 . MSI & SSI (d) MSI and SSI [ ] [ ] [ ] 7. What will be the fan-out of the Combined gate if each has fan-out of 5? [ ] [ ] [ ] [ ] (a) five (b) two (c) eight (d) ten 12. Two basic technologies for digital ICs are bipolar and MOS Bipolar technology is preferred for (a) LSI & MSI (b) LSI only (c) LSI. The ECL can be used to switch frequencies as high as Vignan Institute of Technology & Science II B. Which of the following flip-flops is used as latch (a) ECL (b) TTL (c) ISL (d) CMOS 9.margin of ECL family is given by ——– (a) 200 milli watt (b) 10 milli watt (c) 250 milli watt (d) 110 milli watt 3. The programmable logic device (PLD) having a programmable AND-array at the Input and]programmable OR array at the output is called [ (a) programmable gate array(PGA) (b) programmable array logic (PAL) (c) programmable logic Array (PLA) (d) ASIC ] 11. Complementary output is available in which of the following logic families (a) TTL (b) DTL (c) ECL (d) RTL 8. An IC that is a 4-bit latch is (a) 7400 (b) 7446 (c) 7410 (d) 7475 14. The noise . An AND gate is a [ ] (a) Multiplexing circuit (b) sequential circuit (c) combinational circuit (d) Memory circuit 10. The cost of Schottky clamped TTL is ———— (a) low (b) average (c) very high (d) moderate 13. The IC74147 which acts like (a) AND gate (b) adder (c) multiplexer (d) encoder 4. Two similar RTL gates are wire-ANDed.RTL (b) DTL (c) TTL (d) ECL 6. The cost of Schottky clamped TTL is ————(a) very high (b) moderate (c) low (d) average 23. In Boolean algebra .Tech2 nd Semester Page 33 . Name the logic family which can always be Wire-Ored (a) DTL (b) TTL (c) RTL and DTL (d) IIL 22. A NAND circuit with positive logic will operate as (a) NOR with negative logic (b) AND with negative logic (c) AND with positive logic (d) OR with negative logic 20.Pulse and digital circuits Objectives Questions (a) 100MHz (b) 1MHz (c) 1GHz (d) 500MHz 15. ¯ Y (c) ( ¯X + ¯ Y ) ( ¯X + ¯ Y ) (d) XY 17. Which of the following logic has the fan-out more than 90 [ ] [ ] (a) TTL (b) 8ns ECL (c) 4nsECL (d) CMOS 16. Fan-in for a TTL gate is given by [ ] [ ] (a) 5 (b) 8 (c) 6 (d) 7 19. NOR operation is (a) ¯X + ¯ Y (b) ¯X . Power dissipation of logic family is defined as the supply power required for the gate to operate with ————–duty cycle at a certain specified frequency [ ] (a) 50% (b) 25% (c) 100% (d) 75% 18. The programmable logic device (PLD) having a programmable AND-array at the Input and programmable OR array at the output is called (a) programmable gate array(PGA) [ ] [ ] [ ] [ ] (b) programmable array logic (PAL) (c) programmable logic Array (PLA) (d) ASIC 21. A+A+A+ ——– +A is same as (a) An (b) nA (c) Zero (d) A ANSWERS: 1 (c) 9 (c) 17 (a) 2 (c) 10 (c) 18 (b) 3 (d) 11 (d) 19 (a) 4 (a) 12 (b) 20 (c) Vignan Institute of Technology & Science 5 (c) 13 (d) 21 (c) 6 (a) 14 (d) 22(d) 7 (c) 15 (b ) 23(d) 8 (a) 16 (b) II B. ESSAY TYPE QUESTIONS . a) The output of a high pass RC circuit for a symmetrical square wave input is shown in figure. shown in Figure.1 7. Derive the expression for percentage tilt in the output. a) Explain the response of RC low pass circuit for exponential input signal.1. b) Derive the expression for percentage tilt for a square wave output of RC high pass circuit. a) Draw the series RLC circuit and derive expression for its transfer function. (b) What is meant by an attenuator and explain the application of an attenuator in a CRO probe. Calculate the tilt and undershoot. Also sketch the output waveform. m Vignan Institute of Technology & Science II B.a) Prove that an RC circuit behaves as a reasonably good integrator if RC > 15T. Where T is the period of an input ‘E sin ωt’. Figure. 5.Tech2 nd Semester Page 35 . 4. (a) A pulse of amplitude 5 V and duration 20 μ sec is applied to High pass RS circuit having R= 10 k and C = 1000 pf. While sketching the response of compensated attenuator for perfect compensation. b) Derive the expression for percentage tilt for a square wave output of RC high pass circuit. 3. show that the condition for perfect compensation is R C = R C .1 is applied to a high-pass RC circuit.Pulse and Digital Circuits Essay Type Questions ESSAY TYPE QUESTIONS 1 a) A symmetrical square wave whose peak-to-peak amplitude is 2V and whose average value is zero as applied to on RC integrating circuit.1 b) Explain about RLC Ringing Circuit.2 RC ii) T = 10 RC [7+8] Figure. Calculate the output V0 (t) Sketch the output waveform. over compensation and under compensation. 1 1 2 2 6.What is an attenuator? Draw the circuit of compensated attenuator. b) A ramp input. 2. Find the peak to peak value of the output amplitude. Draw to scale the output waveform for the following cases: i) T = 0. The time constant is equals to half -period of the square wave. Vignan Institute of Technology & Science II B.a) Prove that an RC circuit behaves as a reasonably good integrator if RC > 15T.1. output waveform for the given f r γ V i 2. m b) What is the ratio of the rise time of the three sections in cascade to the rise-time of Single section of low pass RC circuit? UNIT II: NON LINEAR WAVE SHAPING 1. The signal input has no tilt and is coupled to the oscilloscope via a 4. The signal input has no tilt and is coupled to the oscilloscope via a 4. Sketch the steady-state output waveform and derive the necessary expressions.Pulse and Digital Circuits Essay Type Questions b) What is the ratio of the rise time of the three sections in cascade to the rise-time of Single section of low pass RC circuit? 8.1 b) An oscilloscope displays a 5Hz square wave with 6% tilt. sketch the transfer characteristic.Tech2 nd Semester Page 36 . Derive the expression for percentage tilt in the output. Where T is the period of an input ‘E sin ωt′. Explain how it provides undamped oscillations. Calculate the input resistance of oscilloscope.a) A square wave input as shown in figure.a) Draw the diode differentiator comparator circuit and explain its operation when a ramp input signal is applied. ii) If R = 50Ω. b) For a shunt diode clipper circuit V = 20 sin ωt. R = ∞ and V = 0. V = 10V is obtained from a potential divider i R circuit using 100V supply and 10K potentiometer i) Draw the circuit diagram. Calculate the input resistance of the oscilloscope.7μF capacitor. b) An oscilloscope displays a 5Hz square wave with 6% tilt. Figure. 9.7μF capacitor. 10. a) Explain RC double differentiator circuit.a)The output of a high pass RC circuit for a symmetrical square wave input is shown in Figure.2 is applied to a negative clamper circuit. c) Draw the basic ringing circuit. 3.1 4.1.2 b) Explain negative peak clipper with and without reference voltage. Sketch the output voltage V to the same time scale & transfer characteristic. Forward and reverse direction tilt iii. (Assume ideal diodes). C = 1μF.Tech2 nd Semester Page 37 . a) Draw the basic circuit diagram of negative peak clamper and explain its operation. Assume ideal diodes. b) Determine Vo for the network shown in Figure.2. 6. f i.1 b) Write a short note on voltage comparators. Also sketch the transfer characteristics.2 is applied to the circuit shown in figure. A / A f r Figure.a) State and prove clamping circuit theorem.1. ii.1 for the given 16V P-P sine wave input. R = 10K & Diode forward S resistance.1 5. a) A square wave input of period T=1000 μ sec. Vpeak = 10V and Duty cycle = 0. Figure. R = 100Ω. Assume ideal diodes. an input voltage V linearly varies from 0 to 150V is applied. b) For the circuit shown in figure. O Figure. i Sketch the output voltage V and transfer characteristics.Pulse and Digital Circuits Essay Type Questions Figure. a sine wave input of 100V peak is applied. b) For the circuit shown in Figure. Given. Sketch the output waveform with voltage levels at steady state.a) Draw the basic circuit diagram of a DC restorer circuit and explain its operation. O Vignan Institute of Technology & Science II B. R = 100Ω. Sketch the f r steady state output voltage indicating all voltages and time constants.a) State and prove clamping circuit theorem b) In the diode circuit shown in figure. R = ∞ and V = 0. R = 10K & Diode forward S resistance.1a. Figure. output waveform for the given f γ r V. for the given square wave input with T1 = 2μsec and T2 = 1μsec.1b. Vγ=0. sketch the transfer characteristic. f i.2 is applied to the circuit shown in figure. Vpeak = 10V and Duty cycle = 0. b) For a shunt diode clipper circuit V = 20 sin ωt.1a Figure. C = 1μF. Sketch the output waveform with voltage levels at steady state. 9.Tech2 nd Semester Page 38 .1b a) Input signal b) Diode circuit 8. a) Explain negative peak clipper with and without reference voltage. V = 10V is obtained from a potential divider i R circuit using 100V supply and 10K potentiometer i) Draw the circuit diagram. Explain its operation with its transfer characteristic and necessary expressions.1. b) Draw the circuit diagram of an Emitter-Coupled clipping circuit.2 7. R = 100Ω. ii. Given. Forward and reverse direction tilt iii. R = 10K. shown in figure. i 10. R = 100Ω. a) A square wave input of period T=1000 μ sec. A / A f r Vignan Institute of Technology & Science II B. a) Draw the diode differentiator comparator circuit and explain its operation when a ramp input signal is applied. ii) If R = 50Ω.Pulse and Digital Circuits Essay Type Questions Figure. the diode has R = 100Ω. 3. iii. b) Calculate the maximum operating frequency of a diode with storage time of 1ns and transition time of 8ns. b) A germanium transistor is operated at room temperature in the CE configuration. when input voltage is +5V. CE 5. Figure. I = -2μA. ii. Turn-ON time. Given R = 1K b & V CC C = +5V. a) Explain how transistor can be used as a switch in the circuit. v. b) A germanium transistor is operated at room temperature in the CE configuration. the collector-circuit resistance is 200 Ω and the base current is 20 percent higher than the minimum value required to drive the transistor into saturation.7V. Assume the following transistor parameters: I = -5μA. the collector-circuit resistance is 200 Ω and the base current is 20 percent Vignan Institute of Technology & Science II B. The supply voltage is 6 V. a) Explain the switching characteristics of a bipolar junction transistor. Fall time. Rise time. 2 uses a silicon transistor with h = 100 and V = 0. under what condition a transistor is said to be ‘OFF’ and ‘ON’ respectively.Pulse and Digital Circuits Essay Type Questions Figure.Tech2 nd Semester Page 39 . i. Find V (Sat) and co EO FE bb' BE V (Sat). vi. Find FE BE the value of R which saturates the transistor. Turn-OFF time. 4. a) Write about diode switching times. Storage time. 2. Delay time.2 b) Write about diode switching times. and r = 250Ω. b) Explain Zener & Avalanche breakdown mechanisms in diodes. h = 100. UNIT III: SWITHING CHARACTERISTICS OF DEVICES 1. iv.1 b) Write a short note on voltage comparators.a) The circuit shown in figure. The supply voltage is 6 V. a) Explain the terms pertaining to transistor switching characteristics. Pulse and Digital Circuits Essay Type Questions higher than the minimum value required to drive the transistor into saturation. (a) Explain the terms pertaining to transistor switching characteristics. b) For the CE transistor circuit shown in Figure. Turn-on time. CC C Calculate the power dissipation in the transistor. Delay time. b) What are transpose capacitors? Explain how the commutating capacitors will increase the speed of a fixed-bias binary 3. Fall time. a) Explain the phenomenon of “latching” in a transistor switch. (b) Give the expression for risetime and falltime in terms of transistor parameters and operating currents.(a) Diode switching times (b) Switching characteristics of transistors (c) FET as a switch UNIT IV:MULTIVIBRATORS 1. ii. co EO FE bb' BE CE 6. and r = 250Ω. 2. 9. Assume the following transistor parameters: I = -5μA. b) Explain the diode switching characteristics.5K. verify that YY Vignan Institute of Technology & Science II B. Draw the circuit diagram for Schmitt trigger and explain its operation. 10. h = 100. Turn-off time. 4. What are the applications of the above circuit? Derive the expressions for UTP and LTP. Find V (Sat) and V (Sat). vi. V = 15V and R = 1.Draw and explain the circuit of Astable Multivibrator with necessary waveforms and also derive the expression for its frequency of oscillations. a) With neat sketches and necessary equations. b) Explain Zener & Avalanche breakdown mechanisms in diodes. I = -2μA. the resistor R is connected to an auxiliary supply V1 instead of V . Storage time.2. iii.2. If Q2 is in saturation or clamp and if Q1 is OFF in the stable state. i. 7.Tech2 nd Semester Page 40 . Rise time.In the monostable circuit shown in figure. explain in detail about transistor switching times. v. when it is in i) cut-off ii) saturation. Figure.2 8.a) Explain different triggering methods of binary circuits. iv. a) Explain the transistor switch in saturation region. i.Pulse and Digital Circuits Essay Type Questions the gate time T is given by equation. a. 4 . IC(sat)=10mA hFE=50 and assume Si transistors. b. Explain the operation of Astable Multivibrator and derive the expression for time-period of output square wave. The supply voltag VCC=10V. pulse width=10μsec. a. R = 10 K ohms. (a) Draw the circuit diagram of a Schmitt trigger circuit and explain its operation. Assume Si transistor. V =10V. b. a. h (min) = 20. (b) Explain how an Schmitt trigger circuit acts as a comparator. (assume Si transistors) 9.05 μF. C = 0. 2. Output pulse width tp= 200μS. Design collector coupled fixed-bias Bistable Multivibrator to operate from ±6Vsupply. What is the slope error of the sweep? iii. duty cycle=40%. VCC=10V. Explain the operation of Monostable Multivibrator wit h circuit diagram and derive the expression for output pulse width. IC(sat)= 10mA. What is the retrace time Tr for C to discharge completely? v. 5. VBB= -5V. RB = 150 K ohms. Derive the Expressions for its UTP and LTP. Define UTP and LTP. 7. Explain the operation of Fixed-Bias Bistable multivibrator with circuit diagram and wavefoms. ii. C fe CC 6. 1.5V. 8. IC(sat)=10mA hFE=50 and assume Si transistors. The gating waveform has a duration of 300 μs.Tech2 nd Semester Page 41 . b) With a neat sketch. T = τ ln (V +I R − V ) / (V YY 1 Y σ YY − V ) with V γ YY replaced by V1. explain: i) stable-state ii) loop-gain iii) quasi stable-state b) Design a collector coupled astable multivibrator for the following specifications with silicon transistor. 10.1Kohms. hFE=20 .(a) How are linearly varying current waveforms generated? (b) In the boot strap circuit shown in figure5 Vcc = 25 V. 3.Given IC(sat)= 1mA. transmission error and displacement error pertaining to sweep circuits. hre = 2. UNIT V: TIME BASE GENERATORS 1.VBE(off)= -0. b. What is the sweep speed and the maximum value of the sweep voltage? iv. Define sweep speed error. Design the Astable Multivibrator to generate 1 KHz square wave. Calculate the recovery time T1 for C1 to recharge completely. explain the frequency division by a factor of 2 in sweep generators.a) With the help of a circuit diagram and waveforms.5 x 10−4 K ohms hfe =50 hoe = 1/40K ohms. VEE = -15 V. The transistor parameters are hie = 1. I (sat) = 10mA. b. The supply voltag VCC=10V. hFE=35.(a) What is a Linear time base generator? Give its Applications Vignan Institute of Technology & Science II B. Draw the waveform of IC1 and Vo .a. labeling all current and voltage levels. Design the Astable Multivibrator to generate 5 KHz square wave. a) With reference to multivibrators. explain frequency division of an astable multivibrator with pulse signals. Also derive the expressions for the same with respect to an exponential sweep circuit. Design collector coupled monostable multivibrator for the following specificatios. Explain the operation of Schmitt trigger wit h circuit diagram and and waveforms. Find the i.peak amplitude 100V and frequency 1 kHz. the recovery time 7. (b). and iv. over what range of frequency may the pulse source be varied? Vignan Institute of Technology & Science II B. (a) With the help of a circuit diagram and waveforms. Define the terms slope error. (a) What is a linear time base generator? (b) Write the applications of time base generators. RB1 = RB2 = 0 and C= 0. (c) What is Synchronization on one-to-one basis? 4. displacement error and transmission error of voltage time base waveform 6.01 μF. (a) Explain the method of synchronization of a sinusoidal oscillator with pulses.to .(a) Draw and clearly indicate the restoration time and flyback time on the typical waveform of a time base voltage. (c) Define the sweep speed error. a) With the help of a circuit diagram and waveforms. (a) With the help of neat diagram explain the working of transistor Bootstrap time base generator. transmission and displacement errors (c) Explain how UJT is used for sweep circuit? 10. the duration of the sweep.Pulse and Digital Circuits Essay Type Questions (b) Write the differences between the voltage and current time base generators? (c) Why the time base generators are called sweep circuits? 5. (a) If the amplifier gain is different from unity in a bootstrap circuit. (b) The relaxation oscillator. the slope and displacement error iii. Explain the basic principles of Miller and Bootstrap time base generators. 9. (b) Describe frequency division employing a transistor monostbale multivibrator.8V. Over what frequency range may the sync pulse frequency bevaried if 1 : 1 synchronization is to result? If 5 : 1 synchronization is to beobtained (fP /fS = 5). (a).Tech2 nd Semester Page 42 . (a) Draw the circuit diagram of fixed amplitude sweep circuit and explain its operation. explain frequency division of an astable multivibrator with pulse signals.6V and goes to OFF state when Vc = 2. (b) Draw the circuit diagram of transistor Miller time base generator and explain its working. generates an output signal of peak . the UJT fires when Vc = 10. (b) Draw a simple current sweep circuit and explain its working with the help of diagrams. b) Describe synchronization with 2:1 frequency division with neat waveforms 2. (b) Derive the relation between the slope. the amplitude of sweep signal ii. 3. VY Y = 50V. 8. explain frequency division of an astable multivibrator with pulse signals. (b) Compare sine wave synchronzation with pulse synchronization. displacement error and transmission error of time-base signal UNIT VI: SYNCHRONIZATION AND FREQUENCY DIVISION 1. what is the effect on the sweep voltage? What is the effect of amplifier bandwidth on the sweep output? (b) In UJT sweep circuit VBB = 20 V. R = 5k . when running freely. Synchronizing pulsesare applied of such amplitude that at each pulse the breakdown voltage is lowered by 20V. (a) Describe the sine wave frequency division with a sweep circuit. b) Derive expressions for gain and minimum control voltages of a bi-directional two. min b) Explain the application of sampling gate in a sampling scope.a) What is relaxation oscillator? Name some negative resistance devices used as relaxation oscillators and give its applications. 4. 10. (b) With the help of a circuit diagram and waveforms. over what range of sync signal frequency will the sweep remain in 1:1 synchronism with the sync signal? 8. explain the frequency division by an astable multivibrator? 6.diode gate. 2. Derive expressions for its gain (A) and V . Vp=16V and η=0. A sinusoidal synchronizing voltage of 2V peak is applied between bases and the natural frequency of the sweep is 1kHz. min b) Explain the application of sampling gate in a sampling scope. (a) Explain how monostable multivibrator is used as frequency divider? (b) Draw and explain the block diagram of frequency divider without phase jitter.(a) Why are sampling gates called linear gates? Vignan Institute of Technology & Science II B. b) Illustrate the principle of sampling gates with series and parallel switches and compare them.Pulse and Digital Circuits Essay Type Questions 5. 7. (a) Explain the factors which influence the stability of a relaxation divider with the help of a neat waveforms. (b) A UJT sweep operates with Vv = 3V.diode gate. 8. Derive expressions for its gain (A) and V . a) Explain the operation of a six . b) Briefly describe the operation of chopper amplifier. Explain its working with waveforms. (a) What is relaxation oscillator? Name some negative resistance devices used as relaxation oscillators and give its applications. the operation of unidirectional sampling gate for multiple inputs. 6. b) Explain with circuit diagram the operation of a two input sampling gate which does not have any loading effect on control signal. explain the frequency division by an astable multivibrator? 9.Tech2 nd Semester Page 43 . (a) What do you mean by synchronization ? (b) What is the condition to be met for pulse synchronization? (c) Compare sine wave synchronization with pulse synchronization? 7. (b) Explain the terms phase delay and phase jitter. 5.5.diode sampling gate.a) Explain the operation of a six . 3.VII :SAMPLING GATES 1. a) Draw the circuit of FOUR-DIODE sampling gate. a) Draw the circuit of FOUR-DIODE sampling gate. a) Illustrate with neat circuit diagram. (b) With the help of a circuit diagram and waveforms.a) Draw the circuit diagram of an astable multivibrator to obtain frequency division by 6. UNIT. a) Illustrate the principle of sampling gates with series and parallel switches and compare them. b) Briefly describe the operation of chopper amplifier. Explain its operation & derive expressions for gain and minimum control voltage in the circuit. a) Draw the circuit of two-diode bi-directional sampling gate. a) Explain about DTL NAND gate. define: i) Positive & negative logic system ii) Fan-in & fan-out b) Draw and explain the circuit diagram of a diode OR gate for positive logic. 9. 4. c) Define positive and negative logic systems. a) Realize two-input AND & OR gates using diodes and explain their operation with the help of truth-tables. 5. b) Draw the circuit diagram of Resistor-transistor logic NOR gate and explain its operation. a) With reference to logic families.(a) Explain the effect of circuit capacitances on the operation of a bi-directional diode gate. 8.Tech2 nd Semester Page 44 .a) Define positive and negative logic system b) Define fan-in and fan-out c) Draw and explain the circuit diagram of a diode OR gate for positive logic. a) Explain about DTL NAND gate. (b) In the circuit of figure 2 consider that RL=RC=100K ohms and that R2=2 K ohms. c) Define positive and negative logic systems. 7.(a) Explain the basic principles of sampling gates using series switch and also give the applications of sampling gates. b) Give some applications of logic gates. UNIT-VIII: LOGIC GATES 1. b) Realize a three-input NOR gate using Resistor Transistor Logic and explain its operation with the help of truth-table.Pulse and Digital Circuits Essay Type Questions (b) What are the other names of a gate signal? (c) Compare the unidirectional and bi-directional sampling gates. 6. b) Give some applications of logic gates. and Vcmin. a) Realize NAND & NOR gates using CMOS Logic and explain their operation with the help of truth-tables. a) With reference to logic families. 2. compute A. 10. Vnmin. (b) Explain the effect of control voltage on gate output of unidirectional sampling gate using diode with some example. a) Realize two-input AND & OR gates using diodes and explain their operation with the help of truth-tables. b) Realize a three-input NOR gate using Resistor Transistor Logic and explain its operation with the help of truth-table 3. define: i) Positive & negative logic system Vignan Institute of Technology & Science II B. Rf=50 ohms for Vs=25V. Pulse and Digital Circuits Essay Type Questions ii) Fan-in & fan-out b) Draw and explain the circuit diagram of a diode OR gate for positive logic. Shown in figure Vignan Institute of Technology & Science II B. 10.Tech2 nd Semester Page 45 . Sketch the output waveform.(a) Draw and explain the circuit diagram of integrated positive DTL NAND gate (b) Consider a two input positive logic diode OR and AND gates. 9 (a) Why totem pole is used in DTL? Draw the circuit diagram and explain a DTL gate with this. (b) Verify the truth table of RTL NOR gate with the circuit diagram of two inputs. ASSIGNMENt QUESTIONS . Calculate and plot the output waveform under the following conditions: The upper 3-db frequency is i) 10MHz ii) 0. Also calculate and plot the output for the first two cycles.Tech2 nd Semester Page 47 .1 2. the time for the capacitor to charge to 63. Calculate the maximum and minimum values of the output voltage with respect to ground under steady state conditions. fig ure1. Figure 2. A pulse generator with an output resistance R s = 500Ω is connected to an oscilloscope with an input capacitance of Ci=30 pf. 2. A 10V step is switched on to a 50kΩ resistor in series with a 500pf capacitor. Draw the transfer characteristics for the circuit shown in figure 2. Determine the fastest rise time that can be displayed.2% of its maximum voltage. An ideal 1µs pulse is fed to an amplifier. The periodic waveform shown in figure 1. The input voltage vi to the two level clipper show in figure 2.Pulse and Digital Circuits Assignment Questions ASSIGNMENT QUESTIONS Unit I: LINEAR WAVE SHAPING 1. 3. Vignan Institute of Technology & Science II B.1MHz. Calculate the rise time of the capacitor voltage.1.2 varies linearly from 0 to 150V.1 is applied to an RC integrating network whose time constant is 10µs. 4.1 UNIT II: NON LINEAR WAVE SHAPING 1. Sketch the output waveform. Assume ideal diodes. Sketch the output voltage vo to the same time scale as the input voltage. the time for the capacitor to be completely charged. Also draw the output Waveform for a sinusoidal input of amplitude of 20V. (a) Draw the basic circuit diagram of negative peak clamper circuit and explain its operation. 4.Tech2 nd Semester Page 48 .Pulse and Digital Circuits Assignment Questions figure 2.(a) Draw the diode comparator circuit and explain the operation of it when ramp input signal is applied.(a) For the circuit shown in figure 2a .2 3. (b) What is meant by comparator and explain diode differentiator comparator operation with the help of ramp input signal is applied 6. (b) Explain positive peak clipping with reference voltage. Assume ideal Diodes. Vi is a sinusoidal voltage of peak 100 volts. Assume ideal diodes. (a) Determine Vo for the network shown in figure 1 for the given waveform. Sketch one cycle of output voltage. Vignan Institute of Technology & Science II B. (b) Explain the operation of two level slicer. Determine the maximum diode Current. 5. Draw the shunt clipper that clips the sine wave signal above +5V and explain its Working with waveforms.5K Ω. a. b. a. State and prove clamping circuit theorem with relevant circuit and waveforms 9. b. Calculate the minimum level of base current to achieve saturation in case.1 2. b. b. A common. Explain its Working with transfer characteristics. figure 3. Draw the diode shunt clipper that clips the sine wave signal above +5V and below -5V. 10 a. a. Draw the circuit of combinational clipper and explain with its transfer Characteristics 8. Explain the working of an Emitter coupled clipper with circuit diagram.2 Vignan Institute of Technology & Science II B. Explain the operation of negative clamper circuit using diode.figure3.1) has Vcc = 20V and a collector resistor which can be either 20k Ω or 2k Ω. For CE transistor with Vcc = 15 V. UNIT III: SWITHING CHARACTERISTICS OF DEVICES 1. State and prove clamping circuit theorem with relevant circuit and waveforms.Tech2 nd Semester Page 49 .emitter circuit (figure 3. Explain the operation of positive clamper circuit using diode. Calculate the transistor power dissipation a) At cut off and at saturation. Rc= 1.Pulse and Digital Circuits Assignment Questions 7. Icbo = 10nA at 25 deg C and zero base to emitter voltage at cut off.2 Vignan Institute of Technology & Science II B. Vbe(sat) = 1V.b)if the reverse saturation current doubles for every 10 deg C rise in temp.R2 = 27k Ω. Rc = 1. For the astable multivibrator shown in figure 4. R1= 4. find the frequency of oscillation and duty cycle of the output waveform.1 uses n p n silicon transistors with Vce(sat) =0.2 UNIT IV:MULTIVIBRATORS 1. figure 4.2 if R1=20k Ω. R2= 10k Ω.Tech2 nd Semester Page 50 . The fixed bias binary shown in figure 4.02µF and C2=0.Pulse and Digital Circuits Assignment Questions figure3.the circuit parameters are Vcc = Vbb = 6V.what is the maximum temperature at which the circuit can operate properly with one device remaining OFF? figure 4.1 2. C1= 0. Find a) hfe(min) and stable state voltages and currents.7k Ω.5V.015µF.2k Ω. Calculate the component values of the UJT sweep circuit to generate an output sweep frequency of 10kHz with a sweep time of 12V. if a voltage to frequency converter generates oscillations of frequency twice of that whenV = Vcc.2.Pulse and Digital Circuits Assignment Questions 3. 5.82. when running freely. 2.6. generates an output signal of peak . (a) Describe the sine wave frequency division with a sweep circuit.Tech2 nd Semester Page 51 . 3. (Note: the specification from the data sheet are given as ή = 0.01µF. (b) Compare sine wave synchronzation with pulse synchronization. figure 5. UNIT V: TIME BASE GENERATORS 1. Synchronizing pulses Vignan Institute of Technology & Science are applied of such II B. In the UJT sweep circuit of figure 5.and C=0. (b) The relaxation oscillator. Design a relaxation oscillator to have 2 kHz output frequency. Rbb = 5k Ω. Vyy=50V. figure 5. Explain monostable relaxation circuits as dividers. using 2N3980 and a 20V supply. Iv =1 mA and Veb(sat)= 3V. b) the slope and displacement errors. The specification of UJT are given as ή = 0.Vv = 2V.5mA.to peak amplitude 100V and frequency 1 kHz. Find the ratio Vcc/V. Rb1=Rb2=0 Ω. c)the duration of the sweep. 2.2. 3. Explain phase delay and phase jitters.1. figure 5. find a) the amplitude of a sweep signal.1 Vbb=20V. Using UJT characteristics. and Vbb = 18 V. (c) What is Synchronization on one-to-one basis? 4. and d) the recovery time. (a) With the help of a circuit diagram and waveforms.68 to 0. Iv = 1. Ip = 2µA. R=5k Ω. explain frequency division of an astable multivibrator with pulse signals. Ip =8µA. Calculate the output amplitude.2 UNIT VI: SYNCHRONIZATION AND FREQUENCY DIVISION 1. Explain unidirectional and bidirectional sampling gates 6. (a) What do you mean by synchronization ? (b) What is the condition to be met for pulse synchronization? (c) Compare sine wave synchronization with pulse synchronization? UNIT. a.VII :SAMPLING GATES 1. Realization of NAND and NOR gate using diode and transistors. What are the applications of sampling gates. Realization of universal gates using NAND and NOR gates. b. Explain basic operating principle of sampling gates. Vignan Institute of Technology & Science II B. UNIT-VIII: LOGIC GATES 1. Explain about sampling scope. over what range of frequency may the pulse source be varied? 5. 2. b. Explain about chopper amplifier. Over what frequency range may the sync pulse frequency be varied if 1 : 1 synchronization is to result? If 5 : 1 synchronization is to be obtained (fP /fS = 5). (b) With the help of a circuit diagram and waveforms.Tech2 nd Semester Page 52 . explain the frequency division by an astable multivibrator? 6.Pulse and Digital Circuits Assignment Questions amplitude that at each pulse the breakdown voltage is lowered by 20V. 2. (a) Why are sampling gates called Selection circuits? (b) What are the advantages of unidirectional sampling gates? (c) What are the applications of sampling gates? 7.resistor logic OR gate and explain its operation.(a) What is sampling gate? Explain how it differ from Logic gates? (b) What is pedestal? How it effects the output of a sampling gates? (c) What are the drawbacks of two diode sampling gate? . 3. (a) Draw the circuit diagram of diode . Explain unidirectional and bidirectional sampling gates. Explain the Basic operating principle of sampling gate. 4. a. 3. 5. (a) What is relaxation oscillator? Name some negative resistance devices used as relaxation oscillators and give its applications. Draw the circuit of 3-input OR gate using diodes and resistors and explain with truth table. (b) The transistor inverter (NOT gate) circuit has a minimum value hfe = 30. Draw the circuit diagram of NAND gate using DTL logic and explain. VBB = 12V.resistor logic OR gate and explain its operation. Draw the circuit diagram of NAND gate using TTL logic and explain. VCC = 12V. Prove that circuit works as NOT gate. b. Prove that circuit works as NOT gate. VBB = 12V.2k. R1 = 15k and R2 =100k. a. VCC = 12V. 5.Pulse and Digital Circuits Assignment Questions (b) The transistor inverter (NOT gate) circuit has a minimum value hfe = 30. The input is varying between 0 and 12V 4. The input is varying between 0 and 12V. R1 = 15k and R2 =100k. ****THE END*** Vignan Institute of Technology & Science II B. Assume typical junction voltages. (a) Draw the circuit diagram of diode . RC = 2. RC = 2.Tech2 nd Semester Page 53 . b. Assume typical junction voltages. a.2k. 6. Draw the circuit of 3-input AND gate using diodes and resistors and explain with truth table. SWITCHING THEORY AND LOGIC DESIGN mr.sreehari AssT. POCHAMPALLY (MANDAL) NALGONDA (DISTRICT) . Hyderabad) . DESHMUKHI VILLAGE.S. Professor COURSEFILE Department of ELECTRONICS AND COMMUNICATION ENGINEERING VIGNAN INSTITUTE OF TECHNOLOGY AND SCIENCE VIGNAN HILLS.508284 Sponsored by Lavu Educational Society (Approved by AICTE and Affiliated to JNT University. COURSE OBJECTIVE . standard sequential devices. signals. This provides the platform to learn principles of digital systems logic design and distinguish between analog and digital representations. 2nd Semester Page 56 . Construct and analyze the operation of a latch flip-flop and its application in synchronization circuits. including counters and registers. Karnaugh maps including the minimization of logic functions to SOP or POS form. or time delay.  To fortify the documentation standards for logic designs. including PLDs.Switching theory and logic design Course Objective COURSE OBJECTIVE This course is a comprehensive study of principles and techniques of designing digital systems. It will be able to analyze a given combinational or sequential circuit using kmap and Boolean algebra as a tool to simplify and design logic circuits.  Know the fundamentals of Boolean algebra and theorems. flip-flops. It teaches the fundamentals of digital systems applying the logic design and development techniques.  To strengthen the principles of logic design and use of simple memory devices. and ROMS including its sequencing and control.  Analysis of logic circuits and optimization techniques to minimize gate count. Vignan Institute of Technology & Science II Year B. its conversions and binary arithmetic. and sequential circuits. IC count.Tech. RAMS. This provides the following key features  Understand the different number system.  To understand the logic design of programmable devices. Syllabus . Common Drain Amplifies. Pulse mode. Design of modulo-N Ring & Shift counters. Tabular Method. Multiplexer. Code-converters. Multigate Synthesis. Encoder.switching functions– Canonical and Standard forms-Algebraic simplification digital logic gates. Threshold Logic: Basic PLD’s-ROM. Decoder. Modular design using IC chips. sequence detector UNIT. Prime implicants. Capabilities and limitations of Threshold gate. The UJT UNIT-VIII: Algorothimic State Machines: Salient features of the ASM chart-Simple examples-System design using data path and control subsystems-control implementations-examples of Weighing machine and Binary multiplier. Switching theory and logic design-Bhanu baskar Vignan Institute of Technology & Science II Year B. PHI. Switching & Finite Automata theory – Zvi Kohavi. Prime –Implicant chart. Don’t care combinations. 3.VII: Sequential Circuits . properties of XOR gates – universal gates-Multilevel NAND/NOR realizations. MUX Realization of switching functions Parity bit generator. De-Multiplexer. Serial binary adder.Tech. FET as voltage variable resistor. PLA. simplification rules UNIT IV: Combinational Logic Design: Design using conventional logic gates. 2006. UNIT V: Programmable Logic Devices. TEXT BOOKS: 1. Steps in synchronous sequential circuit design.II: FET common source amplifiers.2nd Edition 2. 3rd Edition.Switching theory and logic design Syllabus SYLLABUS UNIT I: Number Systems & Codes: Philosophy of number systems – complement representation of negative numbers-binary arithmeticbinary codes-error detecting & error correcting codes –hamming codes UNIT II: Boolean Algebra And Switching Functions: Fundamental postulates of Boolean Algebra . Biasing FET. Hazards and hazard free realizations. Digital Design – Morris Mano.I: Classification of sequential circuits (Synchronous. PROM. TMH. UNIT VI: Sequential Circuits . Minimal SOP and POS forms. 2nd Semester Page 58 . Generalized FET amplifiers.Basic theorems and properties . Synthesis of Threshold functions. UNIT III: Minimization Of Switching Functions: Map method. Comparison of BJT and FET. PLD Realization of Switching functions using PLD’s. Asynchronous. Level mode with examples) Basic flip-flops-Triggering and excitation tables. Digital Logic Applications and Design – John M. 5th Edition. 2. 3.com/digital/gates3.asic-world.html en.Tech.Switching theory and logic design Syllabus REFERENCE BOOKS: 1. Thomson Publications.uwaterloo.wikipedia.html en.ca/Teaching/192/ASM.wikipedia. Thomson 2.org/wiki/Hamming_code www.phy-astr. An Engineering Approach To Digital Design – Fletcher.gsu.hyperphysics. 2006 WEBSITES: 1. 2004. 4. 3. www. Roth. Yarbrough.edu/hbase/electronic/dflipflop.org/wiki/Algorithmic_State_Machine www.ocho. PHI. Yarbrough. Fundamentals of Logic Design – Charles H. 2nd Semester Page 59 . Thomson Publications.ppt Vignan Institute of Technology & Science II Year B. 5. Digital Logic – Application and Design – John M. STUDENT'S SEMINAR TOPICS . Features of ASM chart 10. Mealy and Moore models 9.Tech. Shift counters 8. Basic flip flops 7. conversion of number format 2. 2nd Semester Page 61 . realization of universal gates 5. properties of Boolean Algebra with some examples 4. Sequence detector Vignan Institute of Technology & Science II Year B. Realization of logic gates 6. hamming codes 3.Switching theory and logic design Seminar Topics STUDENTS SEMINAR TOPICS 1. LECTURE PLAN . Tech 2nd Semester Page 63 . Introduction 2. TMH. Basic theorems and properties 2 13. Number representation 4. Chalk Black board and Chalk Black board and Chalk Black board and Text books referred --Switching & Finite Automata theory – Zvi Kohavi. 2006 Digital Design – Morris Mano.Electronic Devices & Circuits Lecture Plan LECTURE PLAN S. PHI. 2006 Digital Design – Morris Mano. 3rd Edition. PHI. Method of Teaching 2 Black board.2nd Edition Digital Design – Morris Mano. Binary arithmetic 5. TMH. 3rd Edition.2nd Edition Switching & Finite Automata theory – Zvi Kohavi. TMH. PHI. Canonical and standard forms 2 6. Fundamental postulates of Boolean algebra 2 12. 2006 Digital Design – Morris Mano. 2006 Digital Design – Morris Mano. Binary codes.weighted codes 2 11. TMH. 3rd II B. Switching functions 2 14.No NAME OF THE TOPIC No of Periods UNIT I: Number Systems & Codes 1 Black board and 2 Chalk Black board and 2 Chalk 1. 3rd Edition. 2006 Digital Design – Morris Mano.2nd Edition Digital Design – Morris Mano. PHI. PHI. 10. 3rd Edition. 2006 Digital Design – Morris Mano. Chalk Black board and Chalk Black board and Binary codes.Nonweighted codes 2 Chalk Black board and Error detecting codes 2 Chalk Black board and Error correcting codes 2 Chalk Black board and Hamming codes 2 Chalk Complement representation of negative Black board and 2 numbers Chalk UNIT II: Boolean Algebra And Switching Functions Vignan Institute of Technology & Science Black board. 3rd Edition. TMH. 9. 8. 3rd Edition. PHI. 3rd Edition.2nd Edition Switching & Finite Automata theory – Zvi Kohavi.2nd Edition Switching & Finite Automata theory – Zvi Kohavi. 2006 Switching & Finite Automata theory – Zvi Kohavi. PHI. History of number systems 3. PHI. 7. 2006 II B.Tech 2nd Semester Page 64 . 18. TMH.2nd Edition Digital Design – Morris Mano. Chalk 27. 3rd Edition. PHI. Chalk Vignan Institute of Technology & Science Edition. TMH. 2006 Digital Design – Morris Mano.2nd Edition Digital Design – Morris Mano. 2006 Digital Design – Morris Mano. 2006 Digital Design – Morris Mano. Multiplexer 1 Black board. PHI. PHI. 3rd Edition. 25. Lecture Plan Chalk Algebraic simplification digital logic gates. 22. Chalk 29. PHI. 2006 Switching & Finite Automata theory – Zvi Kohavi. 16. Chalk 28. 2006 Digital Design – Morris Mano. 2006 Digital Design – Morris Mano. PHI. 3rd Edition. PHI. 19. 21. 20. PHI. Black board and 2 properties of XOR gates Chalk Black board and Universal gates 3 Chalk Black board and 2 Multilevel NAND/NOR realizations Chalk UNIT III: Minimization Of Switching Functions Black board and Map method 2 Chalk Black board and Prime implicants 2 Chalk Black board and Don’t care combinations 2 Chalk Black board and Minimal SOP and POS forms 2 Chalk Black board and Tabular method 2 Chalk Black board and Prime – implicant chart 2 Chalk Black board and Simplification rules 2 Chalk UNIT IV: Combinational Logic Design Black board and Design using conventional logic gates 2 Chalk 26. 3rd Edition. 17. 2006 Digital Design – Morris Mano. 3rd Edition. 24. 2006 Switching & Finite Automata theory – Zvi Kohavi. PHI. Decoder 1 Black board. 3rd Edition. TMH. 2006 Digital Design – Morris Mano. 3rd Edition. 3rd Edition. 3rd Edition. TMH. PHI. 2006 Digital Design – Morris Mano. 23. 2006 Digital Design – Morris Mano. Encoder 1 Black board.2nd Edition Switching & Finite Automata theory – Zvi Kohavi.2nd Edition Switching & Finite Automata theory – Zvi Kohavi.Switching theory and logic design 15. 3rd Edition. De-multiplexer 1 Black board. PHI. 3rd Edition. PHI. 40. 2006 Digital Design – Morris Mano. 3rd MUX realization of switching functions 2 Black board. 2006 Black board and Digital Design – Morris Mano. TMH. PHI. 37. 2006 Black board and Switching & Finite Automata theory – Zvi Hazards and hazard free realization 2 Chalk Kohavi. PHI. TMH. 2006 Black board and Digital Design – Morris Mano. 3rd 2 pulse mode. 31. 45. 3rd Realization of switching functions using PLD’s 2 Chalk Edition. 36. 2006 Digital Design – Morris Mano. Chalk Edition. 43.2nd Edition Black board and Digital Design – Morris Mano. PHI. Threshold Logic Black board and Digital Design – Morris Mano. 3rd Basic PLD’s 2 Chalk Edition. 42. 2006 Black board and Digital Design – Morris Mano. Lecture Plan Digital Design – Morris Mano. 2006 Digital Design – Morris Mano. 35. PHI.2nd Edition UNIT V: Programmable Logic Devices. 3rd Capabilities and limitations of threshold gates 2 Chalk Edition. PHI. 3rd Edition. PHI. level mode with examples) Chalk Edition. 2006 UNIT VI: Sequential Circuits – I Classification of sequential circuits(synchronous.Tech 2nd Semester Page 65 . PHI. PHI. 3rd Multi gate synthesis 2 Chalk Edition. 33. 3rd PROM 2 Chalk Edition. PHI. 3rd Parity bit generators 2 Black board. 3rd ROM 2 Chalk Edition. 34. 2006 Black board and Switching & Finite Automata theory – Zvi Synthesis of threshold functions 2 Chalk Kohavi. PHI. 32. PHI. 44. Black board and Digital Design – Morris Mano. 3rd 2 Black board.Switching theory and logic design 30. 3rd Modular design using IC chips Vignan Institute of Technology & Science 2 Black board. 3rd PLD 2 Chalk Edition. 2006 Black board and Digital Design – Morris Mano. Chalk Code-converters Edition. 2006 Black board and Digital Design – Morris Mano. 2006 Black board and Digital Design – Morris Mano. 39. PHI. 41. PHI. Chalk Edition. 3rd PLA 2 Chalk Edition. Chalk II B. 2006 Basic flip-flops – triggering and excitation tables 3 Black board and Digital Design – Morris Mano. PHI. 38. 2006 Digital Design – Morris Mano. PHI. 2006 Digital Design – Morris Mano. Partition techniques 1 53.VII: Sequential Circuits . 57. 3rd Edition. 3rd Edition. TMH. 3rd Edition. 2006 Digital Design – Morris Mano.Tech 2nd Semester Page 66 . 2006 Switching & Finite Automata theory – Zvi Kohavi. PHI. 47. 49. PHI. 3rd Edition. 3rd Edition. 48. Chalk Black board and Chalk UNIT-VIII: Algorothimic State Machines Black board and Salient features of ASM chart 1 Chalk Black board and Simple examples 2 Chalk Black board and System design using path and control subsystem 2 Chalk Black board and Control implementations 1 Chalk Examples of weighted machine and binary Black board and 1 multiplier Chalk Black board and Revision on I and II Units 1 Chalk Vignan Institute of Technology & Science 1 Edition. 2006 Digital Design – Morris Mano. PHI. 2006 Digital Design – Morris Mano. PHI. 2006 Digital Design – Morris Mano. 3rd Edition. PHI. 2006 Digital Design – Morris Mano. 60. Black board.Switching theory and logic design 46. Merger chart methods 1 54. 2006 Digital Design – Morris Mano. Chalk Black board and Chalk Black board and Chalk Black board. Concept of minimal cover table 55. 2006 Digital Design – Morris Mano. Mealy and Moore models 2 51. Minimization of completely specified and incompletely specified sequential machines 1 52. 58. PHI. 3rd Edition. sequence detector 2 Chalk UNIT. PHI. PHI. 59. PHI.II Black board and Finite state machine-capabilities and limitations 1 Chalk 50. 2006 Digital Design – Morris Mano. 2006 Digital Design – Morris Mano. 3rd Edition.2nd Edition Digital Design – Morris Mano. 3rd Edition. 2006 Digital Design – Morris Mano Notes II B. 3rd Edition. PHI. PHI. 56. Lecture Plan Chalk Black board and Steps in synchronous sequential circuit design 1 Chalk Black board and Design of modulo-N ring and Shift counters 2 Chalk Black board and Serial binary adder. 3rd Edition. 3rd Edition. Revision on III and IV Units 1 62.Switching theory and logic design Lecture Plan 61.Tech 2nd Semester Page 67 . Revision on V and VI Units 1 63. Revision on VII and VIII Units 1 Vignan Institute of Technology & Science Black board and Chalk Black board and Chalk Black board and Chalk Notes Notes Notes II B. LEARNING OBJECTIVES . non-weighted codes. gray code. 000010001010 Why the binary number system is used in computer design? Given the binary numbers a=1010. What is the necessity of binary codes in computers? Encode the decimal numbers 0 to 9 by the means of the following weighted binary codes: 421 2421 6 4 2 -3 Explain how to subtract BCD numbers.c Convert (2AC5. Write a brief about hamming codes and hamming distance.01 c=1001. Also.Tech 2nd Semester Page 69 . excess-3 code. indicate what the original data was a. If one is incorrect. perform the following: a+c a-b a.1. repetition codes. 111110001100 c. by stating the rules for generating borrows and applying the correction factor with suitable examples Determine which of the above codes are self-complimenting and why Encode 11 information bits with suitable parity groups of distance-4 hamming code Write brief about reflective code. cryptographic hash functions. checksums. indicate what the correct code should have been. 010101100011 b. Perform the following (i) 10100.Switching theory and logic design Learning Objective LEARNING OBJECTIVES UNIT I: Number Systems & Codes At the conclusion of this unit student will 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 What is gary code? What are the rules to construct gray code? Develop the 4 bit gray code for the decimal 0 to 15 List the XS3 code for decimal 0 to 9 What are the rules for XS3 addition? Add the two decimal numbers 123 and 658 in XS3 code Test if these code words are correct. assuming they were created using an even parity hamming code.1 b=101.11012=?16 (ii) 75310=?5 (iii)593BCD-971BCD=?BCD UNIT II: Boolean Algebra And Switching Functions At the conclusion of this unit student will 1 2 3 4 State the laws of Boolean algebra List out the basic operations of Boolean algebra Represent diagrammatically the basic gates Relate the basic operations & laws of Boolean algebra to circuits composed of basic gates Apply these laws to the manipulation of algebraic expressions including Vignan Institute of Technology & Science II B.D)16 to binary and then to octal. sequential codes. cyclic redundancy checks(CRCs). 11.29. D) = AB’C’ + AC + A’CD’ (b) F (W.31) 4 Realize XOR gate using minimum number of NAND gates 5 Simplify the following Boolean expressions using K-map and implement them using NOR gates: (a) F (A.z ( 4.9.3.29. E) = ∑(0.5.7.5. 14.11.28.E) = ∑(0.C.B.6.13.2. 13. a) F (A. Y.151.E) = ∑(4.B. 12.15.27.11.31) + ∑d(11.27. multiplexer and de-multiplexer circuits 2. 5.D.D.3.z ( 0.18.20.C.14.15) (4M) b) F = ∑w.26.21.10.4.2. D.28.D (1.29.y. C.20.15) + d(0.4. C.30) 2 Using Karnaugh maps.17. UNIT IV: Combinational Logic Design At the conclusion of this unit student will 1.7.21. b.20.y.Multiplying out an expression to obtain a sum of products.7. find minimal SOP expressions for the following logic functions.13.Simplifying an expression by applying one of these laws d.B. find minimal SOP expressions for the following logic functions.12.C.12) (6M) c) F = ∑A. a) F = ∑w.1.14.1.9.25.22) b) F(A.25. B.2.Switching theory and logic design Learning Objective a.14.30)+ d(1.Tech 2nd Semester Page 70 .5.8. X.10. Realize 5-32 line decoder using multiple 3-8 line 74x138 decoders Vignan Institute of Technology & Science II B.5.6. Discuss about the IC chips of decoder.22.Factoring an expression to obtain a product of sum c. Z) = W’X’Y’Z’ + WXY’Z’ + W’X’YZ + WXYZ 6 Design BCD to Gray code converter and realize using logic gates 7 Design 2*4 decoder using NAND gates.1.24.Finding the complement of an expression 5 Define the Exclusive –OR & equivalence operations 6 Draw a circuit that uses two OR gates & two AND gates to realize the following function:F=(V+W+X)(V+X+Y)(V+Z) 7 prove the following function using truth tables:w’xy+wz=(w’+z)(w+xy) factor to obtain a product of sum: A’B’C+AC’D+ABC+BC’D’ 8 State and prove Boolean laws 9 Which gate can be used as parity checker? Why? 10 Simplify the following Boolean functions to minimum number of literals: (a+b)’(a’+b’)’ y(wz’+wz)+xy 11 realize XOR using minimum number of NAND gates 12 prove AND-OR network is equivalent to NAND-NOR network UNIT III: Minimization Of Switching Functions At the conclusion of this unit student will 1 Obtain the prime-implicant chart for the following logic function and obtain the minimal expression F (A. 9) 3 Using 5-variable Karnaugh maps.x.10. B.x. 15) + d(7.8.7. bit serial adder and explain its operation.31) Realize using 2n-1x1 multiplexer 4. Design logic circuit for parity bit generator 6. UNIT VI: Sequential Circuits . Write short notes on PLD’S Draw the basic macro cell logic diagram and explain. D=10.7. C=11. 2. 3. 6…. 9.27.x. Determine the ROM size to realize the following logic functions a) BCD to Excess -3 code converter b) 5-32 line decoder 1.z) = ∑m (1.20.I At the conclusion of this unit student will 1. 6. 11.13. 4.25. 5. Draw the block diagram of a 4 . What is meant by Asynchronous sequential circuits? Design Asynchronous modulo-10 counter. 10. Unit V: Programmable Logic Devices. F(n)= ∑m( 5. Design a clocked synchronous state machine using D flip flops of the following state/output table? Use two state variables.15) Realize using De-Multiplexer 8.9.6. Derive a PLA programming table for the combinational circuit that squares a 3 bit number. Draw the logic diagram of a 4 bit binary ripple counter using positive edge triggering.Switching theory and logic design Learning Objective 3.5z Briefly describe about the Programmable Array Logic with suitable diagrams Draw the functional diagram 5-32 line decoder using PLA Draw the functional logic diagram of PLA and explain its operation Realize logic expressions of seven segment display with suitably sized ROM Explain the general CPLD configuration with suitable block diagram.4. 4. Explain the differences between multiplexers and De-multiplexers with the help of neat logic diagrams.5x + 3y -1. Design modulo-11 counter with counting sequence 4. 6….14.13.29. What is decoder? How do you convert a decoder in to a De-Multiplexer 7. 7. Q1 Q2 with state assignments A=00. (ii) Synchronous counters Design a 4-bit ripple down counter using T flip-flop and no other components. 8. 8.(X + Y + Z ) 5.y. Vignan Institute of Technology & Science II B. Find all of the static hazards in the two level AND-OR or OR-AND realizations of the following logic expressions? Design a hazard free circuit that realizes the same logic function. Draw the circuit diagram of master and slave JK flip flop? Explain its operation.7. 9. 5. 10. 3. 14. B=01. Draw the circuit of JK Flip Flop using NAND gates and explain its operation.15. Write short notes on the following: (i) Triggering of Flip-Flops . 7. 2.. Threshold Logic At the conclusion of this unit student will Draw the logic diagram of Programmable Logic Array? Explain its operation Realize threshold function f = 2. Draw and explain the working of 4 bit UP/DOWN synchronous counter. 6. F(w. 5. 5.16. 4.(W + X + Z ).5.Tech 2nd Semester Page 71 . F = (W + Y + Z ). Tech 2nd Semester Page 72 .II At the conclusion of this unit student will 1. If w1=w2 during any four consecutive clock cycles. It’s function is to compare the i/p sequence on the two i/p’s.Switching theory and logic design Learning Objective UNIT. For the machine given below find a minimum state reduced machine using Merger table.VII: Sequential Circuits . Vignan Institute of Technology & Science II B. Explain the state minimization procedure with the help of example. Explain the path sensitisation method with an example 4. (b) A sequential circuit has 2 inputs w1=w2 and an output z. Discuss about the capabilities and limitations of Final State Machines 3. Write the differences between Mealy and Moore type machines. 2. the circuit produces z=1 otherwise z=0 w1= 0110111000110 w2= 1110101000111 z=0000100001110 5. on every clock rising edge code on BA changes from 00 01 10 11 00 and repeats. Draw the ASM chart for binary multiplier and realize using JK flip flop & gates. then circuit holds present state. if X= 1. Draw an ASM chart for designing a circuit which is used to count the number of bits in a register that have a value 1.” 2. 4.Switching theory and logic design 6.Tech 2nd Semester Page 73 . Design the synchronous state machine to generate the following sequence of states 35791 Vignan Institute of Technology & Science II B. Draw the timing diagram. 5. clock and outputs A and B. 3. If x=0. Discuss the procedure to implement an ASM chart using Multiplexer. Learning Objective Find the equivalent partition and reduced machine for the machine given below UNIT-VIII: Algorothimic State Machines At the conclusion of this unit student will 1. Draw the ASM chart and state table for the synchronous circuit having the following description “The circuit has a control input X. OBJECTIVE TYPE QUESTIONS . 10101 (d) 0.001 (d)10100. 1k-byte is precisely equal to: [ (a)1020bits (b)1012bits (c)1000bits (d)1024bits 5.010 (b)10100.001 (c)10101. Binary 1000 when multiplied by binary 1111 results in binary: (a)1110000 (b)1111111 (c)1111000 [ (d)1111100 4. Binary coded decimal (BCD) numbers express each decimal digit as : [ ] (a)bit (b)byte (c)unit (d)nibble 9.10101 Vignan Institute of Technology & Science [ ] [ [ ] ] (d)1.Tech 2nd Semester Page 75 .10100 II B. ASC-II code is used as: (a) a7-bitcode (c) an alphanumeric code 7.Switching Theory and logic design Objectives Questions OBJECTIVE TYPE QUESTIONS UNIT I: Number Systems & Codes: 1. (d) Even bit positions and odd bit positions 10. In hamming code parity bits are placed in which positions and the data are placed in which positions? [ ] (a) odd bit positions are parity bits and even bit positions are data bits (b) starting from LSB are parity bits and remaining are data bits (c) All bit positions that are power software used as parity bits and All other bit positions are for the data to be encoded.10100 (b) 1. ] ] [ ] (d) 2’s compliment [ ] (b) a 4-bitcode (d) a 6-bitcode Conversion from decimal to hex requires repeated division by (a)16 (b)4 (c)10 (d)8 [ ] 8.10100 (c) 1.10101 (b)0. The 2‘s compliment of binary number 001011 is [ ] (a) 0. Pick out the code from the following which is not a self complementing code (a) 3321code (b)2421code (c)8421code (d)642-3 13. The1’s compliment of 1’s compliment of a given number is (a)1’s compliment (b)9’s compliment (c)the same number itself 6.100 2.10100 (c)0.125 may be written in binary system as: [ ] (a)10101. Decimal number 21. Decimal equivalent of octal number 57 is [ ] (a) 47 (b) 67 (c) 57 (d) 37 12. Decimal number 15 may be written in binary system as: (a)1110 (b)1100 (c)1001 (d)1111 14.10101 11. The2‘s compliment of binary number 001011 is (a)1. The largest positive number that can be stored in a computer that has16-bitword length and uses twos complement arithmetic is [ ] (a)32767 (b)32768 (c)32 (d)65536 3. The dual of a Boolean theorem is obtained by (a) inter changing all zeros and ones only (b) inter changing operators and identity elements (c) changing all ones to zeros only (d) changing all zeros to ones only 2. In a digital system performance accuracy depends on [ ] A) nature of devices used B) number of gates C) word length D) propagation delay ANSWERS: 1© 11(a) 21. [ ] a)Gray code (b) Xs-3 code (c) 8421 code (d) All of these 23.(b) 5© 15(a) 25.Switching Theory and logic design Objectives Questions 15.(a) 3© 13(a) 23.11 (c)101. Hexa decimal equivalent of decimal number 1000 is: (a)3E8 (b)3E7 (c)3CF [ ] [ ] [ ] (d)4E8 16.1011 [ ] (a)101. The following code is not a BCD code. Excess-3 equivalent of decimal number 10is: [ ] (a)1101 (b)1011 (c)1110 (d)1001 20.10 (d)100. In the Hamming code 1001101. Binary division 10010.error has occurred in position [ ] (a)5 (b)1 (c)4 (d)7 21. The1’s compliment of 1’s compliment of a given number is (a)9’scompliment (b)1’scompliment (c)2’scompliment (d)the same number itself 18. the sum will contain at the most A) n bits B) n+1 bits C) n+2 bits D) n +n bits 25. AB+A+1= (a) B (b) 1 (c) A (d) 0 3.(a) 4(d) 14(d) 24.Tech 2nd Semester Page 76 . When two n bit binary numbers are added . The minimum number of bits required to represent negative numbers in the range of -1 to -11 using 2’s complement arithmetic is [ ] (a)2 (b) 3 (c) 4 (d) 5 22.(d) 2(a) 12(d) 22.11 19. The NAND can function as NOT gate if (a) one input is set to 0 (b) inputs are left open (c)inputs are connected together (d)one input is set to 1 5.11 (b)110. A 15-bit hamming code requires [ ] (a)4 parity bits (b) 5 parity bits (c) 15 parity bits (d) 7 parity bits 24. AB+A+0= Vignan Institute of Technology & Science [ ] [ ] [ ] [ ] [ ] II B. Decimal number 74 may be written in binary system as: (a)1001010 (b)1001011 (c)1001001 (d)1000111 17.(c) 6© 16© 7(a) 17(d) 8(d) 18© 9© 19© 10(a) 20© UNIT II: BOOLEAN ALGEBRA AND SWITCHING FUNCTIONS 1. Which of the following gates is known as coincidence detector? (a)NOT gate (b)AND gate (c)NAND gate (d)OR gate 4. NOT (b)NAND.OR.NOR (d)NOT. The logic expression (A+B)( A’+B’) can be implemented by giving the inputs A and B to a two-input [ ] (a)NOR gate (b) NAND gate (c) X-OR gate (d) X-NOR gate 22.NAND 20. .the output is 1 If and only if one input is 1? [ ] (a)AND (b)XOR (c)NOT (d)NORD 15. In Boolean algebra ‘0’ is called [ ] (a)additive identity (b)multiplicative inverse (c)multiplicative identity (d)additive inverse 19.OR. two (b)two or more. one (d)one or more. A gate can have input signals and output signals [ ] (a) two. The Boolean expression (XYZ+YZ+XZ) after simplification [ ] (a)Z (b)X (c)(X+Y)Z (d)YC 12. An OR gate has 36 inputs. Which of the following Boolean algebraic expressions is incorrect? [] (a)A+ A’B=A+B (b) A+AB=B (c) (A+B)(A+C)=A+BC (d) (A+B’ )(A+B)=A 23. How many input words are there in its truth table? [ ] (a) 64. How many input words are there in its truth table? [ ] (a)64. Which of the following Boolean algebra statements represent Commutative law [ ] (a)A+(B+C)=(A+B) (b)A+B=B+A (c)A(B+C)=AB+AC (d)A(BC)=(AB)C 10. The basic gates are [ ] (a)AND. In which of the following gates. Identify the pair of basic gates from the following [ ] (a)AND. AB+A’B+1= [ ] (a)B (b)1 (c)0 (d)A 16. the output is 0 If and only if [ ] atleast one input is 0? (a)NOT (b)NOR (c)OR (d)AND 13.Which of the following gates are added to the inputs of The OR gate to convert it into NAND gate [ ] (a)OR (b)NOT (c)AND (d)XOR 21.two or more (c)one.NOT (b)AND.the output is 0 If and only if atleast one input is1? [ ] (a)AND (b)NOT (c)XOR (d)NOR 18.000.ORNOR (c)NAND. Which of the following gates are added to the inputs of The OR gate to convert it into NAND gate? [ ] (a) NOT (b) OR (c) AND (d)XOR 8. one 7.Tech 2nd Semester Page 77 .NOR (d)AND.AND (c)OR.NAND 14.000 (b)6 (c) 64 (d)36 11. Boolean algebra can be used to [ ] (a)Minimize the number of switches circular statement (b)perform arithmetic calculations (c)Solve the mathematical problems (d) simplify any algebraic expressions 9. The minimum number of bits required to represent negative numbers in the range of -1 to -11 using 2's complement arithmetic is [ ] (a)2 (b)3 (c)4 (d) 5 Vignan Institute of Technology & Science II B.000 (b)36 (c)6 (d)64 17.In which of the following gates.Switching Theory and logic design Objectives Questions (a) B (b)1 (c)0 (d)A 6.000. In which of the following gates. An OR gate has 6 inputs. Which of the following code is used in K-map for representing the minterms ? (a) Graycode (b)BCD (c)8421 (d)Excess-3codeA [ ] 10.(d) 5(d) 15(b) 6(d) 16© 7(a) 17(a) 8(a) 18(d) 9(d) 19(a) 10(d) 20(b) UNIT III: Minimization Of Switching Functions 1. The Essential Prime Implicant of the function covers all the Minterms then there resultant expression is a [ ] (a)logical expression (b)arithematic expression (c)not a unique expression (d)Unique expression 8. The minterm.(c) 2(b) 12© 22.B. designator of the term B‘CD is (a)12 (b)15 (c)11 (d)10 [ ] 5. The necessary condition to combine the two minterms is Both minterm values must Be differentiated by power of [ ] (a)2 (b)6 (c)4 (d)3 6.A Prime Implicant which includes at least a1cell that is not covered by any other Prime Implicant is called [ ] (a)self complimenting (b)Dominent (c)essential prime implicant (d)prime implicant itself 11. In Don’t care a minterm /maxterm in a logic function which (a)is always‘0’ (b) must be included (c)may or may not be included (d)ignored [ ] 9. A 1ine cell of k-map can be combined with three other1‘sin Only one combination The resulting term of these four 1‘s is [ ] (a) not prime implicant (b)Don’t care (c)Essential Prime Implicant (d)Minterm 4.D)=1then the K-map contains number of Logic1‘s is (a)8 (b)32 (c)4 (d)16 [ ] 7. its equivalent Binary representation is (a)000 (b)101 (c)111 (d)010 [ ] 3.Switching Theory and logic design Objectives Questions 24.Tech 2nd Semester Page 78 . If F(A.(d) 4© 14(a) 24.The X mark in a cell may be assumed to be Upon which one leads to a simpler expression (a)1or a 0 depending (b)only 0 (c) only 1 (d) always 2 [ ] Vignan Institute of Technology & Science II B.C. What is the minimum number of NOR gates required to realize an X-OR gating [ (a)2 (b)3 (c)4 (d) 5 ] ANSWERS: 1(a) 11© 21.(b) 3© 13(a) 23. The given max term is A+B+C. Which of the following code is used in K-map for representing them interms? (a)BCD (b) Graycode (c)8421 (d) Excess-3code [ ] 2. Each term in the standard SOP form is called a A) minterm B) maxterm C) don't care D) literal ANSWERS: 1(b) 9(a) 2(a) 10(b) 3(c) 11(b) 17.Switching Theory and logic design Objectives Questions 12.which contains all the variables either in complemented or uncomplemented form [ ] (a)product (b)exclusive (c)difference (d) sum 13. What is the number of inputs. ROM is an example for (a)Combinational digital circuit (c) Both combinational and sequential [ ] (b)Registers (d)sequential digital circuit 2. The number of cells in a 6-variable K-map is (a)64 (b)6 (c)12 (d)36 [ ] 14. 18. two OR gate [ ] (b)two-half-adder.the base(radix) of the number system is [ ] a)5 (b) 6 (c) 7 (d) 8 17.(d) 18.A maxterm is term. The hexadecimal number system is used in digital computers and digital systems to [ ] (a) Perform arithmetic operations (b) Perform logic operations (c) Perform arithmetic and logic operations (d) Input binary data into the system. The necessary condition to combine the two minterms is Both min term values must Be differentiated by power of [ ] (a)4 (b)3 (c)6 (d)2 16. In a single input-variable Change might cause a momentary incorrect output and output is constant [ ] Vignan Institute of Technology & Science II B. If sqrt(41)=5. two OR gates (d)two-half-adder.(b) UNIT IV: Combinational Logic Design 1.outputs of a decoder that accepts 64 different input combinations? (a)5 (b)64 (c)6 (d)7 [ ] 5. one OR gate (c)one half-adder.(c) 19. one OR gates 4.(a) 4(c) 12(b) 5(a) 13(a) 6(d) 14(a) 7(d) 15(d) 8(c) 16. A full adder can be realized by (a)one half-adder. decoder with ‘n’ inputs produces maximum of number of minterms (a)2n (b) 2n-1 (c)2n-1 (d)2n 3. A minterm corresponding to Don’t care condition may have a value of (a)0or1 (b)only1 (c)don’t care (d)only0 [ ] 15.Tech 2nd Semester Page 79 . The code used for labeling cells of the K-map is A) natural BCD B) Hexadecimal [ ] [ D) Octal ] C) Gray 19. adder C) counter D) multiplexer ANSWERS: 1 (a) 13.The size of the decoder required to implement 3-variable Boolean Function is (a)3 to 8 line (b)2 to 4 line (c) 4 to 8 line (d) 4 to 16 line [ ] 8. In which of the following adder circuits is the carry ripple delay eliminated? A) half .A1in a cell of k-map can be combined with three other 1‘s in Only one combination The resulting term of these four1‘s is [ ] (a)Minterm (b) Essential Prime Implicant (c)not prime implicant (d) Don’t care 11.adder B) full .adder C) parallel adder D) carry-look-ahead adder 16) A serial adder requires only one A) half . fixed O R gates 2.Switching Theory and logic design (a) static hazard (c)Dynamic hazard Objectives Questions (b)Delay problem (d)synchronization 6.An one-of-16 line decoder can be constructed by using number Of one-of-2lined Encoder (a)6 (b)3 (c)4 (d)5 [ ] 7.A 6-to-64 decoder can be obtained by cascading of (a)four number 4-to16 decoders and one 2:4 decoder (b) cannot possible (c)five number 4-to16 decoders (d)three number 4-to16 decoders and two 2:4 decoder 13.The gate is either [] (a)a NOR or an X-NOR (b) a NAND or an X-OR (c) an OR or an X-NOR (d) an AND or an X-OR 15. The gate is [] (a)NOR (b) AND (c) NAND (d) None of these 14. A gate is enabled when its enable input is at logic 0. The PROM consists of (a) Programmable OR . The output of a logic gate is 1 .(a) 2 (d) 14(a) 3 (d) 15(d) 4© 16(b) 5 (a) 6 (d) 7 (a) 8 (b) 9 (b) 10 © 11 © 12 (a) UNIT V: Programmable Logic Devices.The circuit used for parallel to serial conversion of data is known as (a)Adder (b)Multiplexer (c)parity encoder (d) Demultiplexer [ ] 9.Tech 2nd Semester Page 80 . its contents .The race hazard problem occurs due to: [ ] (a)fixed low logic circuit (b)time-delay in circuits due to high speed logic (c)faulty design of logic circuits (d)non-redundant form of the circuit 10. [ ] (b) fixed OR and AND gates (d) Programmable OR and AND gates When the power supply of a ROM is switched off . [ ] ( a) become all zeroes ( b ) are unpredictable ( c ) becomes all ones ( d ) remain intact Vignan Institute of Technology & Science II B.The number of full adders required to add two 4-bit data in a Serial adder (a)2 (b)1 (c)4 (d)16B [ ] 12.adder B) full . Threshold Logic 1. fixed AND gates (c) Programmable AND . when all its inputs are at logic 0. The parameters of a threshold element are ( a) weights as signed to input variables and T ( c ) weights as signed to input variables 6. The Decoder has [ ] ( a) fixed OR and AND gates ( b ) Programmable OR.fixed AND gates ( d ) Programmable AND.(a) 13. The ROM programmed during manufacturing process itself is called [] a)MROM (b) PROM (c) EPROM (d) EEPROM 13. nor output variables nor T values ( d ) value of T [ ] ( b )Programmable OR . A ROM has 16 address lines and 8 data lines . A memory in which the contents get erasedwhen power failure occurs is [ ] a)EAROM (b) PROM (c) ROM (d) RAM 14. A switching function Y can be decomposed into two threshold functions f 1 and f 2 . It is organized as ( a) 6 4K × 8 ( b ) 1 28 K × 4 ( c ) 6 4K × 1 6 [ ] ( d ) 3 2K × 1 6 4. A threshold function ( a) is not a unite function ( c ) may be a unite function [ ] ( b ) value of T ( d ) weights assigned to input variables and T [ ] ( b ) is always a unite function ( d ) may or may not be a unite function 11. A PLA is a ( a) Field programmable ( c ) Can be erased and programmed [ ] ( b ) neither input . The function Y can be implemented using [ ] ( a) 2 threshold elements interconnected to perform NAND operations ( b ) 2 threshold elements interconnected to perform OR operations ( c ) 2 threshold elements interconnected to perform NOR operations ( d ) 1 threshold element 5.(d) 14. fixed OR gates 12. Four RAM chips of 16×4 size have their busses connected together . The Decoder has ( a) fixed OR and AND gates ( c ) Programmable OR and AND gates 7.fixed OR gates [ ] ( b ) Can be programmed by user ( d ) Mask programmable 8. fixed AND gates ( c ) Programmable OR and AND gates ( d ) Programmable AND.(a) 15(a) 5 (a) Vignan Institute of Technology & Science 6 (a) 7 (d) 8© 9 (d) 10 (d) 11 (a) II B.Tech 2nd Semester Page 81 . The parameters of a threshold element are ( a) output variables ( c ) weights assigned to input variables 10.This system will be of size ( a) 256 ×1 ( b ) 16 ×4 ( c ) 1 6 ×1 6 ( d ) 32 ×8 [ ] 9. The ROM programmed during manufacturing process itself is called [ ] A) MROM B) PROM C) EPROM D) EEPROM 15 The data bus width of a ROM of size 2048 x 8 bits is [ ] A) 8 B) 10 C) 12 D) 16 ANSWERS: l (a) 2 (d) 3 (a) 4 (b) 12.Switching Theory and logic design Objectives Questions 3. K flip .flop (d) D flip . R = 1 ( d ) S = 1 .(d) 11.t n s =next state decoder delay.Flops when ( a) One of the input combinations ( 0 . then maximum frequenc y of edge triggered flip flop is [ ] ( a) 1 /( t s e t u p + t n s ) ( b ) 1 /( t p d + t n s ) ( c ) 1 /( t s e t u p + t n s + t p d ) ( d ) 1 /( t s e t u p + t p d ) 3.(b) 10. Which of the following input combinations is not used in a RS flip flop ? ( a) S = 0 .Race around condition occurs in JK Flip . If t set up =set up time .flop c)T flip . A johnson counter is also called as — — — — — — — ( a) Inverse counter ( b ) Inverse feedback counter ( c ) Direct counter ( d ) Direct feedback counter 6 . A single literal term in SOP expression [ ] [ ] a)Requires an inverter for PLA implementation b)Requires an AND gate for PLA implementation c)Doesn’t requires an AND gate for PLA implementation d) Doesn’t requires an inverterfor PLA implementation 10. A sequential circuit with m flip flops and n inputs needs — — — rows in the state table ( a) 2 m -n -1 ( b ) 2 m ( c ) 2 m + n ( d ) 2 n [ ] 5. 1) is present ( c ) both the inputs are 0 2. R = 0 ( c ) S = 1 .Flops when [ ] ( b )the inputs are complementary ( d ) both the inputs are 1 ( a) One of the input combinations (0.Tech 2nd Semester Page 82 . R = 0 [ ] 4. Race around condition occurs in JK Flip . A counter that does not use any additional logic gate is — — — — — ( a) Pre settable counter ( b ) Johnson counter ( c ) Ring counter ( d ) Up counter 9. When an inverter is placed between the inputs of anS – R flip – flop. Flip – flops can be used to make a)Latches [] (b) Bounce – elimination switches c) Registers (d) All of the above 12. the resulting flip – flop is a [ ] a)J . Which of the following flip flop is used as a latch? [ ] A) J-K flip flop B) Master-slave flip flop C) T flip flop D) D flip flop ANSWERS 1(d) 2© 3© 4© 5 (b) 9.flop 11. A combinational PLD with a programmable AND array and a programmable OR array is [ A) PLD B) PROM C) PAL ] D) PLA 13.(c) 12(d) 13(d) Vignan Institute of Technology & Science 6 (d) 7© 8 (a) II B. 1) is present ( c ) both the inputs are 0 [ ] [ ] ( b ) the inputs are complementary ( d ) both the inputs are 1 7. t pd = propagation delay time . R = 1 ( b ) S = 0 .flop (b) Master – slave flip .Switching Theory and logic design Objectives Questions UNIT VI: SEQUENTIAL CIRCUITS – I 1 . The flip flops used in shift registers are — — — — — — ( a) R S ( b ) T ( c ) D ( d ) J K [ ] 8. The number of directed arc semanating from any state in a state diagram is [ ] ( a) an arbitrary number ( b ) 2n where n is number of Flip .0 G D.(d) 9.Switching Theory and logic design Objectives Questions UNIT.0 G.0 F E.Flops in the circuit ( c ) independent of the number of inputs ( d ) 2n .II 1. The circuit can be represented by [] a)Mealy model (b) Moore model c)Either Mealy or Moore model (d) Neither Mealy or Moore model 8.(b) 8. An Algorithmic State machine is same as ( a) clocked sequential circuit ( b ) synchronous clocked sequential finite state machine ( c ) finite state machine ( d ) synchronous sequential circuit 2. 0 B C.VII: Sequential Circuits . For designing a finite state machine k – maps can be used for minimizing the [] a)Excitation expressions of flip . An algorithmic state machine is the same as A) synchronous sequential circuit B) clocked sequential circuit C) finite state machine D) all of the above 10.0 B. While constructing a state diagram of a sequential circuit from the set of given statements [ ] ( a) redundant states must be avoided ( b ) minimum number of states must only be used ( c ) Only input states must be used ( d ) redundant states must be used 3.where n is the number of inputs 2.0 C B. The output of a clocked sequential circuit is independent of the input.0 E F.(d) 10.0 D.1 B. For a 8 state machine if P4 = ( A ) ( B ) ( C D ) ( E FG ) (H ) then its P3 partition may be ( a) ( A B ) ( C D ) ( E F ) (G H ) ( b ) ( C D ) ( A ) ( B ) ( E FG ) (H ) ( c ) ( A B C ) (D E F ) (G H ) ( d ) ( A B ) ( C D ) ( E H ) (FG ) 4. 0 C . The example of a Mealy machine is ( a) Serial Adder ( b ) Binary Counter ( c ) Half adder ( d ) Sequence detector [ ] [ ] 5.0 ( a) 0 00 ( b ) 0 10 0 ( c ) 0 11 10 ( d ) 1 01 1 6. [ ] An asm chart of the mealy model [ ] ( a) contains only state and decision boxes Vignan Institute of Technology & Science II B.0 A.(a) UNIT-VIII: Algorithmic State Machines 1.0 A. Distinguishing sequence for states A and F Present State Next State X = 0 Output X = 1 A E .0 D G. Moore type of outputs are A) independent of inputs B) dependent only on the inputs C) dependent on present state and inputs D) dependent on hardware used for implementation ANSWERS: l (d) 2 (d) 3 (b) 4 (b) 5 (d) 6 (c) 7.Tech 2nd Semester Page 83 .flops (b) Number of flip – flops c)Output logic expressions (d) Excitation and output logic expressions 9. The example of a Mealy machine is ( a)Half adder ( b ) Serial Adder ( c ) Binary Counter ( d ) Sequence detector [ ] 7. While constructing a state diagram of sequential circuit from the set of given statements [ ] a)A minimum number of states must only be used b)Redundant states may be used c)Redundant states must be avoided d)None of the above 7. In ASM chart Mealy type of outputs ( a) can be represented by writing output state variables inside state box ( b ) can be represented inside decision boxes ( c ) can be represented by conditional output boxes ( d ) cannot be represented [ ] 6. Which of the following is true [ ] ( a) A partition P is said to be a refi nement of partition Q if P is 5 ( b ) A partition P is said to be a refinement of partition Q if P is greater than Q ( c ) A partition P is said to be a refinement of partition Q i f P i s 190 ( d ) A partition P is said to be a refinement of partition Q if P is smaller than Q 4. 8. A program table is used for ( a) Merger table ( b ) A S M ( c ) P L A ’ s ( d ) Partition tables [ ] 5. A synchronous sequential circuit can be described by [ ] A)a state diagram B) a state table C) an ASM chart D) any one of the above 10 A state box in an ASM chart [ ] A) is included only in one ASM block B) is not included in any ASM block C) may be included in any no.(a) II B. An ASM chart consists of [] a)Only state boxes (b) only decision boxes c)Only decision and conditional output boxes (d) All the above.Tech 2nd Semester Page 84 . of ASM blocks D) may be shared by two ASM blocks ANSWERS 1 (b) 2 (d) 3 (b) 4 (c) 5 (a) Vignan Institute of Technology & Science 6 (b) 7 (d) 8 (a) 9. Moore type outputs are [] a)Independent of the inputs b)Dependent only on the inputs c)Dependent on present state and inputs d)Any one of the above 9.Switching Theory and logic design Objectives Questions ( b )doesnot contain conditional output box ( c ) outputs are represented by writing output state variable inside state box ( d ) contains conditional output box 3.(d) 10. ESSAY TYPE QUESTIONS . Encode the decimal number 365 in: i. Convert the following numbers: i. Convert the following to Decimal and then to Binary. a)Convert the number (17. (95. Convert (235.01101001)2 to octal iv. a . 0110101 iii. base 5 and base 2. a . sign-1’s complement and sign-2’s Complement representation 3.Switching Theory and logic design ESSAY Questions ESSAY TYPE QUESTIONS UNIT I: Number Systems & Codes 1.0101)2 to base 8 and base 4 iii. c) Justify the statement that “Gray code is a class of reflected code”. (a) 123416 (b) 12EF16 (c) 101100112 (d) 100011112 (e) 35210 (f) 99910 6. (a) 101116 (b) ABCD16 (c) 72348 (d) 77668 (e) 12810 (f) 72010 7. ASCII 5.125)16to base 10. (6753)8 to base 10 ii. a / b 4. 10110 iv. BCD iii. Represent +65 and -65 in sign-magnitude. (00111101. 1011011 ii. Binary ii. base 4. Obtain the 1's complement and 2's complement of the binary numbers i. Convert (1596. Convert the following to Decimal and then to Octal.675)10 to hexadecimal ii. Convert (10110001. Given a = 10101001 and b = 1101 find: i. Vignan Institute of Technology & Science II B. 00110 9. b iv.0657)8 to Binary 8.b iii.75)10 to base 2.Tech 2nd Semester Page 86 . a + b ii. b) Perform the binary arithmetic operations on (-14)-(-2) using signed 2's complement representation. Convert (11110. i.1011)2 to decimal iii. 2. b) Use 2’s complement form perform subtraction.9) F2 = π(3. Write short notes on Universal gates 5. What are Logic Gates? How do the Gates differ from Logic operators? Explain Positive Logic and negative logic.5. 12.14) 7. Draw the truth table and write Boolean expression for the following: i.65)10= (-----------)2. a)Convert the number (234)10 to base 16. XOR gate iv. Give the truth table and symbols for each. a)Develop a Gray code for (42)10and (97)10and convert the same to Hex sequence. State and prove the following Boolean laws: i. 8. Commutative ii. G is a 0 if any of the three variables X.11 11.11.6. Vignan Institute of Technology & Science II B. Prove the following: i. NAND gate 9. b) Explain different error detecting and correcting codes in digital system. ii. Define the following with an example i. Y and Z are 1s. Explain each term with examples.Tech 2nd Semester Page 87 . 4. AND gate ii. Distributive. Maxterm 3. G is a 1 for all other conditions. Minterm iv. base 8 and base 2. b) find the Canonical POS form of F= Y’Z + XY +X’YZ’ c) find the sum of -8+2 in 2’s complement form UNIT II: Boolean Algebra And Switching Functions 1. Standard form iii. a) Convert the following to the required form. Write the Min terms and Max terms for the following functions F1= ∑(1.1101-101. XY’ + Y’Z = XY’Z + XY’Z’ +X’Y’Z 2. F is a 1 only if X is a 1 and Y is a 1 or if X is 0 and Y is a 0. Define the function of the following gates with the help of circuit diagram of each with an output connected to an LED.Switching Theory and logic design ESSAY Questions 10. OR gate iii. Associative i. For the given function find the min term designation and max term designation F = A'BC + ABC' + ABC + A'B'C 6. XYZ + XYZ’ + XY’Z + X’Y’Z +X’YZ’ = Y’Z + XY +X’YZ’ ii. Canonical form ii.7.7.4. i) (A98B)12= (---------)3ii) (38. i. i) 1101010-110100 ii) 10011. 2. Reduce the following function using K.3. 4. What do you mean by K-map? Name its advantages and disadvantages 3.Tech 2nd Semester Page 88 . Expand A + B C + ABD + ABCD to minterms and maxterms. 3.Switching Theory and logic design ESSAY Questions 10. find the minimal expression for the out put (Y) using K-map Inputs A B C D Output(Y) 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 0 1 0 0 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 1 0 1 1 0 0 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 0 4. a)State and Prove the Huntington postulates of Boolean Algebra. Reduce the following function using K. 1. Prove that NAND and NOR gates are Universal gate 11.z) = xy + z' 12. F=∑(1. (a) Prove the following entity : XY’ + Y’Z = XY’Z + XY’Z’ +X’Y’Z (b)simplify the given function to minimum number of literals.C) = A'BC' + ABC + B'C' + A'B' 13.B. b)Find the complement of the function and represent in sum of minterms F(x.4. For the truth table given below . Simplify the following function and realize using universal gates F(A.7) UNIT III: Minimization Of Switching Functions 1.map and implement it in AOI logic as well as NOR logic F= π M(0. 7) 2.map and implement it using NAND Vignan Institute of Technology & Science II B.2.y. 5.6. 1. Design a 16x1 mux using 4x1 mux UNIT IV: Combinational Logic Design 1. The circuit should perform binary addition when the carry in is 0 and should perform binary subtraction using 2's complement addition when the input carry is 1 Vignan Institute of Technology & Science II B.13. 2. 2. iii) Find a minimal expression for T and realize using basic gates. 7. What do you mean by dont care combinations? 7. 9) + d(10.9.x.7. For the given function T(w.8. 4.15) i) Show the map ii) Find all prime implicants and indicate which are essential.15) Simplify the following using Tabular method.C.15) i) Show the map ii) Find all prime implicants and indicate which are essential. 8.B.6.B.x.7. 5. Implement the following multiple output combinational logic using a 4 line to 16 line Decoder.12.3. 3. Simplify the Boolean function using K-map F= ∑m(0. 6. 6.C.4. then wx + y'(w' + z') = wx + xz + x'z' + w'y'z. 8.y.8. 14.OR circuit made by five NAND gates and the EXCLUSIVE ?OR circuit made by four NAND gates as shown in figure.11.6. What you mean by min terms and max terms of Boolean expressions. Is it unique? 13. 12. Explain the type of Hazard if any in the EXCLUSIVE .3. Prove that if w'x + yz' = 0. 3.D) = ∑(3. F(A.5. 5. Construct a combinational logic circuit which converts a decimal number into an equivalent Excess -3 number.z) = ∑(0. Design a Logic circuit which accepts two 5 bit binary numbers. Y1 = ¯ A ¯ C + A CD + A C + ABC + A C + A CD Y2 = ¯ A ¯ CD + ¯ AB ¯ C + ¯ AB ¯ CD + AB ¯ CD Y3 = ¯ ABCD + ABC + ABCD 3.14. Is it unique? 11 Simplify the following function using K-map.11. List the applications of Multiplexer and Demultiplexer. iii) Find a minimal expression for T and realize using basic gates. F(A. F= ∑m(0. For the given function T(w.14) 12. 13.y.4.z) = ∑(0.8. 11.9.2. 15) 9. 4. 4. 1. ) 6. A combinational circuit is defined by the following three functions F1 = ¯x¯y + xyz F2 =¯x + y F3 =xy + ¯x¯y Design the circuit with a decoder and external gates.Switching Theory and logic design ESSAY Questions logic. 5.1.13. Implement the same using (a) Multiplexer (b) Decoder 6.D) = ∑(1.6.2.4.7.Tech 2nd Semester Page 89 .3. 10.11.15)+ d∑ (9. 5.7.C. (a) F1 (A. Write short notes on Integrated circuits. 5.9. B.14)+ d∑ (2.3.3. What is PAL? How does it differ from PROM and PLA? 7. 8.(a)define static hazard.4) Unit V: Programmable Logic Devices. Derive the PLA programming table for the combinational circuit that squares a 3 bit number. Classify the ICs based on the levels of integration. B. 1. Simplify the following using Tabular method. a)Design a 64:1 MUX using 8:1 MUXs.8) (d) F4 (A. Tabulate the PLA programming table for the four Boolean functions.B. 8. 6) (b) F2 (A. and f3.8.illustrate with example (b)design a combinational circuit that convert a given binary code to excess-3 code Vignan Institute of Technology & Science II B.12.D) = ∑(1.Switching Theory and logic design ESSAY Questions 7. 7) (c) F3 (A.7) 6.7. For the given 3-input. 2. b)Design a 4 bit parallel adder using Full adder modules. Implement the following functions using PAL and PLA F1 = ∑m(2. 9. F(A.6. Realize 16 × 1 Mux using only 2 × 1 Mux.13.13. 10.Tech 2nd Semester Page 90 . C) = ∑m (1. 4-output truth table of a combinations circuit. Threshold Logic 1.3. Design a switching circuit that converts a 4 bit binary code into a 4 bit Gray code using ROM array. C) = ∑m (0. b) What are the capabilities and limitations of threshold gate? 9. a) Design a square generator logic for 4 bit input using ROM. B. 4. 2. Design a 2-bit comparator which compares the magnitude of two numbers X andY and generates three output f1.15) 5.11) F2 = ∑m(1. What are the different types of programmable devices? 4.f2. Minimize the following. B.11. C) = ∑m (2.5. Discuss on PLDS. tabulate the PAL programming table for the circuit 3.5.2.6. C) = ∑m (1.4. Switching Theory and logic design ESSAY Questions UNIT VI: Sequential Circuits – I Compare synchronous & Asynchronous circuits 2. Design a Mod-6 synchronous counter using J-K flip flops 3. Design a sequence detector which detects 110010 Implement the sequence detector by using D - type flipflops 4. Classify the required circuits into synchronous, asynchronous, clockmode, pulse mode with suitable examples 5. Find a modulo-6 gray code using k-Map & design the corresponding counter 6. Compare synchronous & Asynchronous. 7. Compare synchronous & Asynchronous. 8. Write the conversion procedures of the ip ops. Convert T flipflop to JK flipflop. (a)Convert SR ip op to T flipflop (b) Convert D flipflop to T flipflop. 9. Design a 4-bit Bidirectional Shift Register. 10. .a) Convert RS flip flop to a i) D-latch ii) T-latch. b) Design a FSM which detects 0011 patternand set z = 1 for all other patterns z = 0 11. a) What is meant by clock skew? How to handle it? b) Explain the term Race around condition.How is it satisfied by Master-slave Flip-Flops. 11. 12. a) Convert RS flip flop to a i) D-latch ii) T-latch. b) Design a FSM which detects 0011 patternand set z = 1 for all other patterns z = 0 1. UNIT- VII: Sequential Circuits – II 1. Determine the equivalence classes for the given state - table. 2. Obtain final transition table. Vignan Institute of Technology & Science II B.Tech 2nd Semester Page 91 Switching Theory and logic design ESSAY Questions 3. A clocked sequential circuit is provided with a single input x and single output Z. Whenever the input produce a string of pulses 1 1 1 or 0 0 0 and at the end of the sequence it produce an output Z = 1 and overlapping is also allowed (a) Obtain State - Diagram. (b) Also obtain state - Table. (c) Find equivalence classes using partition method & design the circuit using D flipflops. 4. Construct the compatibility graph and obtain the minimal cover table for the sequential machine described by the state table given 5. The state table of a sequential machine is shown below. Obtain the compatibility graph using. (a) Merger graph (b) Merger Table 6. a) Design a modulo 10 counter JK flipflops. b) What are the rules to develop a Merger chart? 7. Construct the state diagram and primitive flow table for an asynchronous machine that has two inputs and one output. The input sequence xy = 00, 01, 10 causes the output to become 1. The next input change then causes the output to return to 0. No other inputs will produce a 1 output. 8. Write the usage of merger graph with example. 9. A clocked sequential circuit is provided with a single input x and single output Z. Whenever the input produce a string of pulses 1 1 1 or 0 0 0 and at the end of the sequence it produce an output Z = 1 and overlapping is also allowed (a) Obtain State - Diagram. (b) Also obtain state - Table. (c) Find equivalence classes using partition method & design the circuit using D flipflops. Vignan Institute of Technology & Science II B.Tech 2nd Semester Page 92 Switching Theory and logic design ESSAY Questions UNIT-VIII: Algorothimic State Machines 1. (a) For the given ASM chart obtain its equivalent state diagram 8. (b) Design the circuit using mulitiplexes. 2.(a) Draw the state diagram. (b) Design the control unit using D flip-flops and a decoder. Vignan Institute of Technology & Science II B.Tech 2nd Semester Page 93 Switching Theory and logic design ESSAY Questions 3. Draw the ASM chart for the following state transistion, start from the initial state T1, then if xy=00 go to T2, if xy=01 go to T3, if xy=10 go to T1, other wise go to T3. 4. Show the exit paths in an ASM block for all binary combinations of control variables x, y and z, starting from an initial state. 5.Draw an ASM chart to convert D-Flip op to T flip flop 6. Give the procedure to design a data processing unit and a control unit 7. Draw an ASM chart for designing a circuit which is used to count the number of bits in a register that have a value 1 8. Discuss the procedure to implement an ASM chart using Multiplexer. 9. Design a binary multiplier and its control logic by drawing ASM chart and realize the same using decoder, MUX and D flipflops 10. Design a control logic through ASM Chart for the sequence detector which detects 1100 and resets flip flop F to 0 and flip flop E to 1. The patterns come from 4 bit counter A. 11. Draw an ASM chart for designing a circuit which is used to count the number of bits in a register that have a value 1 Vignan Institute of Technology & Science II B.Tech 2nd Semester Page 94 ASSIGNMENT QUESTIONS 5.0647)8 to Binary.675)10 to hexadecimal ii. (BC’+A’D)(AB’+CD’) iii. i. 8. i. i. Perform the subtraction with the following unsigned binary numbers by taking the 2’s complement of the subtrahend. (a) 10010 10000 (b) 11010 1000 (c) 1101 110000 (d) 1001100 1011100. Explain the complement representation of negative numbers with examples. 4. AB+A(B+C)+B’(B+D) ii. Express the following functions in sum of minterms and product of maxterms. Give a brief description about the following number systems with suitable examples. Obtain the Dual of the following Boolean expressions. Construct an even parity seven bit code to transmit the data 1101. of literals. A’B+A’BC’+A’BCD+A’BC’D’E iv. Decimal number system ii. Find the 10th element in the base 3 number system. 7.Switching Theory and logic design Assignment Questions ASSIGNMENT QUESTIONS UNIT I: Number Systems & Codes 1. x’yz+xz iv. ABC+A’B+ABC’ ii. 6. Binary number system iii.Tech 2nd Semester Page 96 . 1010111 ii. i. i. Hexadecimal system.1011)2 to decimal iii. Convert (10010. Convert (2598. ABEF+ABE’F’+A’B’EF 3. xy+x(wz+wz’) 2. 00010 UNIT II: Boolean Algebra And Switching Functions 1. Simplify the following Boolean expressions to minimum no. Octal number system iv. Convert (10111101. 2. 3. A+B+A‘B’C iii. Obtain the 1’s complement and 2’s complement of the following binary numbers. Convert (465. i. 0111001 iii. 1001 iv.(xy+z) (y+xz) Vignan Institute of Technology & Science II B.01101001)2 to octal iv. Z) = W’X’Y’Z’ + WXY’Z’ + W’X’YZ + WXYZ.5. (x’y’+z)’+z+xy+wz to three literals iii.13) 5. i.Y.3. Simplify the following Boolean expressions.D) = _(2. What are the advantages of Tabulation method over K-map? 6. B’D+A’D+BD 4.Switching Theory and logic design Assignment Questions ii. Draw the Truth table. B’C’D+(B+C+D)’+B’C’D’E ii. A’B’C+ABC?+A’B’C’D iii.y. Justify each step with a reference to a theorem or postulate.7. 4. 10. Simplify the following Boolean expressions using K-map and implement them using NOR gates: (a) F (A. Simplify the following Boolean function using Tabulation method. A’B’C’+A?BC’+AB’C’+ABC’ iv. Determine the canonical Product of sum form for the function and simplify using k-map (a) Y(x. A’C’+ABC+AC’ to three literals ii. Draw the circuit diagram.12. D. (A’+C)(A’+C’)(A+B+C’D) to four literals 6. Verify the following Boolean algebraic expression. Obtain the complement of the following Boolean expressions. Obtain the complement of the following Boolean expressions. B. i. B. Minimize the following Boolean function using K-map F = π (2. Implement Y = AB’+CD + (A’B+C’D’) using NAND gates 8.c) = (ab + c')(ac + b') 2. (AB +C +D) (C’ +D) (C’ +D +E) = ABC’ + D UNIT III : Minimization Of Switching Functions 1. i. Minimize the Boolean function using K-map.c) = ab' + bc (c) Y(w. D) = AB’C’ + AC + A’CD’ (b) F (W. AB+ABC’ 5. 7.b. Y(A. X. 8. 7.X. AB’C+AB’D+A’B’ ii.Z) = XZ + W’XY’ + WXY + W’YZ + WY’Z Vignan Institute of Technology & Science II B. C.y.z) = x(y'+z) (b) Y(a. AB+(AC)’+(AB+C) iii.10.8.Tech 2nd Semester Page 97 .x. F(W. ABCD+ABC’D’+A’B’CD iv. List the Boolean function simplification rules using Tabulation method. AB+(AC)’+AB’C 7. A’B(D’+C’D)+B(A+A’CD) to one literal iv. Design a combinational logic circuit with 4 inputs A. 12). 3. 9. 8.C.b. Simplify the following Boolean expression using K-map and implement using NAND gates.z) = wxy' + x(y'+z) (d) Y(a. Y.B. C. The output Y goes HIGH if and only if B and C inputs go HIGH. Realize the function F(A. 3. Implement the following functions using appropriate DECODER F1 =∑ m(2.z) = ∑(0.x.5.z) = ∑(0. What is Encoder? Design Octal to Binary Encoder.2. 2. Threshold Logic 1. Implement the following boolean functions using PLA.4.9.2.4. 2. Design excess-3 to BCD converter using (a) ROM (b) PAL. Implement the same in a PAL.1. Implement the following functions using PROM F1 = ∑m(0.12.4.5.3.4.8. Z) = ∑m (1.y.11.5. f1(w.10.15) 4.7) x2(p.6.11.B. Design a 2-bit comparator using NAND gates.11.7.6.3.R) ∑(0. Implement the following functions using PLA x1(P.14) F4 = ∑m(2.Switching Theory and logic design Assignment Questions UNIT IV: Combinational Logic Design 1.12) F2 =∑ m(1.C.5. F1(X. Design an arithmetic circuit that adds 2 binary digits.2. Design a 4 bit Parallel adder using full adders.10. Y.1.13.x.D) = π(1.14) +d(0.7.9.6. 4.8.4.2. This circuit must produce an output 1 if and only if an odd number of inputs have value 1.6.3.7.y.6.3. Z) = ∑m (0. Vignan Institute of Technology & Science II B.R) = ∑(1.7) Write the PLA program table and draw the internal connections to implement the functions.12) F2 = ∑m(1.Q. 5. The circuit should have 2 outputs. 6. Y.15).6).4.10) F3 =∑ m(1.5.15) using (a) 16:1 Mux (b) 8:1 Mux (c) 4:1 Mux.Q.7. 5.13) f2 (w.8.4.Tech 2nd Semester Page 98 .3. Implement the Boolean functions F1 and F2 of a combinational logic circuit using PLA. 6.5.9.7) F2(X. Unit V: Programmable Logic Devices.8) 7.5. 3.9.3. Write short notes on PLD’S 7. What is decoder? Construct 3*8 decoder using logic gates and truth table. 8.2.8. Design a 3 bit Parallel parity-bit generator. one for the sum and the other for the carry. Design a full adder circuit using 2 half adders.9. Design a 8-bit Ring counter. Design a clocked D flip flop. Explain the effects of level triggering in a JK flip flop. 6. Design a JK flip flop using AND gates and NOR gates. Explain the Race around condition. Show a standard form of the corresponding reduced machine. Design a Parallel in Parallel out Shift Register. Give the symbol of edge triggered D flip flop. Derive a PLA programming table for the combinational circuit that squares a 3 bit number. Explain with an example. 3. Find the equivalence partition for the machine shown below. Show that the characteristic equation for the complement out put of a JK flipflop is Q′ (t + 1) = J ‘Q′ + kQ UNIT.VII: Sequential Circuits – II 1.Switching Theory and logic design Assignment Questions 8. 9. Explain the operation of the JK flip flop with the help of characteristic table and characteristic equation. Explain its operation with the help of characteristic table and characteristic equation. 4-output truth table of a combinations circuit. 3. 2. 7. Design a Serial in and parallel out Shift Register. What is the advantage of choosing D-flipflops in sequential circuits. For a given 3-input. 2.Tech 2nd Semester Page 99 . 5. Vignan Institute of Technology & Science II B. Discuss the disadvantages due to level triggering. 4. Convert T flip flop to D flip flop. tabulate the PAL programming table for the circuit UNIT VI: Sequential Circuits – I 1. Design a synchronous sequential circuit which goes through the following states. 4. Draw the ASM chart for the state diagram. Explain the following related to sequential circuits with suitable examples. Vignan Institute of Technology & Science II B. Control circuit using multiplexers for Binary multiplier. Explain the sequence of operations of each block.bit serial adder and explain its operation 8. Design a sequential logic circuit of a 4 bit counter to start counting from 0000 to 1000 and this process should go on. Draw the ASM chart and design the Data processing unit and the control unit. (a) State diagram (b) State table (c) State assignment 6. Explain merger chart methods of minimal convertable. 7. Also design the Data path circuit and control circuit. 3. find the equivalent partition and a corresponding reduced machine in standard form.Tech 2nd Semester Page 100 .Switching Theory and logic design Assignment Questions 4. 2. Design the ASM chart. For the machine shown. Draw the logic diagram of a 4 bit binary ripple counter using positive edge Triggering. Draw the block diagram of a 4 . 5. Draw the State diagram of a sequence detector which is designed to detect the pattern 1001 and allowing the overlapping in the input sequence. UNIT-VIII: Algorithmic State Machines 1. Data path circuit. Design the control unit using PLA control. 5..6.3. draw the equivalent ASM chart as shown in figure 6. as shown in figure 8a obtain its ASM chart ****THE END*** Vignan Institute of Technology & Science II B..Switching Theory and logic design Assignment Questions 1.5. Design the ASM chart to implement the above mentioned design.. For the given state diagram.. For the given control state diagram.Tech 2nd Semester Page 101 .1.3..3.5.. P. n. Professor COURSEFILE Department of ELECTRONICS AND COMMUNICATION ENGINEERING VIGNAN INSTITUTE OF TECHNOLOGY AND SCIENCE VIGNAN HILLS.A.HATHIRAM Asst.508284 Sponsored by Lavu Educational Society (Approved by AICTE and Affiliated to JNT University.ELECTRONIC CIRCUIT analysis Mrs.professor & Mr. POCHAMPALLY (MANDAL) NALGONDA (DISTRICT) . DESHMUKHI VILLAGE.Harshavardhini Assoc. Hyderabad) . COURSE OBJECTIVE . Learn about BJT operation BJT DC Analysis and DC Load Lines. The limitations of common current sources.• Learn about differential pairs. The properties of negative feedback. A frequency dependent and more complete Hybrid-p model. Vignan Institute of Technology & Science II Year B. current sources and multi-stage amplifier design. Overview of Single-Stage. To begin estimating frequency responses of BJT amplifiers by learning about The junction capacitances of BJT’s and their effects on frequency response. The basics of feedback.Tech. Some realistic circuit examples and how to analyze them. analyze. The basic feedback topologies.• Learn about feedback as it applies to amplifiers. double stage BJT Amplifiers. analyze and test multistage amplifiers. and test basic amplifiers. An example of the “ideal” feedback case. 2nd Semester Page 104 . The diffusion capacitance of BJT’s and its effect on frequency response. Find out how bipolar transistors really work in circuits. Design and use of current sources in multi-stage amplifiers.• Learn how to design. The basics current source circuits.Electronic circuit analysis Course Objective COURSE OBJECTIVE The course provides a comprehensive understanding of the basic theory of Some practical knowledge about the design and analysis of basic analog Circuits. Learn how to design. BJT small-signal model hybrid pi looking “in” each terminal. Syllabus . UNIT-3: BJT Amplifiers. Efficiency of class B amplifier. Common Gate stage Cascode and Folded Cascode amplifier and their frequency response UNIT-5: Feedback Amplifiers Concepts of Feedback. General characteristics of Negative Feedback Amplifiers. UNIT-7:Large Signal Amplifiers Classification. Emitter follower at higher frequencies. 2nd Semester Page 106 . Different coupling Schemes used in amplifiers-RC Coupled amplifier. UNIT-2: Multi Stage Amplifiers Analysis of Cascaded RC Coupled BJT amplifiers. CE Short circuit Gain. class-B Push-pull Vignan Institute of Technology & Science II Year B. Condition for Oscillations. and The Hybrid –pi (?)-Common emitter transistor model. Analysis of CE. Gain-Bandwidth Product. Analysis of CE amplifier with emitter follower.Frequency Response Logarithms. Current Gain with resistive Load. Wien-Bridge& Crystal Oscillators. Source follower. Single stage CE Transistor Amplifier Response. MOS Small Signal model. Effect of coupling and bypass Capacitors. CC and CB Configurations with simplified Hybrid Model.Tech. and Colpitts Oscillators. Frequency response of BJT Amplifier. Efficiency of Class A Amplifier. common source amplifier with Resistive load. Cascode amplifier. Illustrative problems. UNIT-4: MOS Amplifiers Basic concepts. Transformer Coupled amplifier. Darlingtonpair. Decibels. miller’s theorem and its dual. Class A large signal Amplifiers. Direct Coupled amplifier. Voltage series. RC Phase shift Oscillators-Hartley. Transformer Coupled class A Audio power amplifier. Diode connected Load and Current Source Load. UNIT-6: Oscillators Classification of Oscillators. Voltage shunt.Electronic circuit analysis Syllabus SYLLABUS UNIT-1: Single Stage Amplifiers Classification of amplifiers-Distortion in amplifiers. Design of single RC Coupled amplifier BJT. Class B Amplifier. General frequency considerations. Analysis at Low and High frequencies. Classification of Feedback amplifiers. Current series and Current shunt feedback configurations . effect of Feedback an amplifier characteristics. Stability of Oscillators. com/ JOURNALS 1.Suresh kumar.BSP 4. Journal of Active and Passive Electronic Devices (ISSN: 1555-0281) 3.TMH REFERENCES: 1.htm 3. 2nd Semester Page 107 . Integrated Electronics – J. UNIT-8: Tuned Amplifiers Introduction.Electronic circuit analysis Syllabus Amplifier. Journal of Electronic Testing (ISSN: 0923-8174) Vignan Institute of Technology & Science II Year B.Thermal stability and Heat Sinks.Millman and C. Smith.oxford university press.9th Edition. Small Signal Tuned amplifiers. Thomson PWS Publ. Stagger tuned amplifiers.Pull Amplifier. Stability of tuned Amplifiers. Effect of Cascading Single Turned amplifiers on bandwidth.. Distortion in power amplifiers . Electronic Devices and Circuits Theory – Robert L. International Journal of Micro and Nano Electronics.H. Complementary symmetry class B Push.2008. Electronic Devices and Circuits – S.S. Micro Electronic Circuits: Analysis and Design – M.Salivahanan. 1999.htm 4. IEEE Transaction on Electronic Devices (ISSN: 0018-9383) 2. 5th ed. and K.Lal kishore.Vallavaraj.guidecircuit. Rashid. WEBSITES 1. 2. Electronic Devices and Circuits.A. Design of analog CMOS integrated circuits-Behzad Razavi.2006.N.com/index_circuitlinks. Micro Electronic Circuits – Sedra A. Boylestad and Louis Nashelsky.Bell-5ed. http://www. Tata McGraw Hill. Active and Passive Electronic Components (ISSN: 0882-7516) 5.kpsec.C.Halkias. 2. Effect of Cascading Double Tuned amplifiers on bandwidth.C.com/symbol.Tech.freeuk. http://buildinggadgets. Electronic circuit analysis-K. TEXT BOOKS 1.David A. Pearson/Prentice Hall.TMH 3. http://www. http://www.2004.2ed.onsemi.. Oxford University Press. 3. Q-Factor.com/ 2. Circuits and Systems (ISSN: 0975-4768) 4.2009. STUDENT'S SEMINAR TOPICS . General characteristics of Negative Feedback Amplifiers 7. RC Phase shift Oscillators 9. Analysis of Cascaded RC Coupled BJT amplifiers Need for biasing 3. CC and CB Configurations with simplified Hybrid Model 2. Current series and Current shunt feedback configurations 8. Effect of Cascading Single Turned amplifiers on bandwidth 12.Electronic circuit analysis Seminar Topics STUDENTS SEMINAR TOPICS 1. Darlington pair 4.Tech. Effect of Cascading Double Tuned amplifiers on bandwidth Vignan Institute of Technology & Science II Year B. Analysis of CE. Effect of coupling and bypass Capacitors 5. 2nd Semester Page 109 . Analysis at Low and High frequencies. Diode connected Load and Current Source Load 6.Pull Amplifier 10. Complementary symmetry class B Push. Class B Amplifier 11. Efficiency of Class A Amplifier. LECTURE PLAN . C.Millman and C.C. Tata McGraw Hill.Halkias.Millman and C. input and output impedance. 5 Analysis of BJT amplifiers for band width calculations 2 Black board and Chalk Integrated Electronics – J. 9 Revision class on Unit -1 1 Black board and Chalk Integrated Electronics – J.C.Halkias.Halkias. current gain. UNIT-2: MULTI STAGE AMPLIFIERS 10 Basic structure of Multi Stage Amplifier and need for Multi Stage Amplifier. Tata McGraw Hill. II B. 1 11 Different types of coupling methods used in multi stage amplifiers. Chalk and LCD Projector Integrated Electronics – J.Millman and C. Tata McGraw Hill.Halkias.C. Tata McGraw Hill.Tech 2nd Semester Page 111 . input and output impedance.Millman and C.Millman and C.C. Integrated Electronics – J. 6 Analysis of the small signal low frequency FET amplifiers for voltage gain. Tata McGraw Hill.Millman and C. 7 Analysis of FET amplifiers for band width calculations 1 Black board and Chalk Integrated Electronics – J. Tata McGraw Hill. Chalk and LCD Projector Integrated Electronics – J.Millman and C.C. 1 Vignan Institute of Technology & Science Black board and Chalk Black board.No NAME OF THE TOPIC Text books referred --- 1 Introduction 1 2 Introduction to ECA 1 3 Review of BJT circuit analysis 1 4 Analysis of the small signal low frequency BJT amplifiers for voltage gain.Millman and C.C. 8 Miller’s Theorem and its significance in amplifier circuit analysis 1 Black board and Chalk Integrated Electronics – J. Tata McGraw Hill.Halkias.Electronic circuit analysis Lecture Plan LECTURE PLAN No of Method of Period Teaching s UNIT-1: SINGLE STAGE AMPLIFIERS S. Tata McGraw Hill. Black board and Chalk Black board and Chalk --Integrated Electronics – J. Tata McGraw Hill. 2 Black board and Chalk Integrated Electronics – J.Halkias.Halkias.C.Halkias.Halkias.Millman and C.C. 2 Black board. Revision class on Unit-2 1 1 1 1 1 Black board and Chalk Black board and Chalk Black board and Chalk Black board and Chalk Black board and Chalk Integrated Electronics – J.C.C. Tata McGraw Hill.Millman and C. 19 Analysis at Low and High frequencies 17 1 Black board and Chalk Integrated Electronics – J.Halkias. Integrated Electronics – J.Halkias UNIT-4: MOS AMPLIFIERS 26 Explain Basic concepts of MOSFET amplifiers. Tata Integrated Electronics – J.Halkias. Decibels General frequency considerations BJT high frequency hybrid PI model and its importance. 22 CE Short circuit Gain. Tata McGraw Hill. Tata McGraw Hill. two stage RC coupled amplifier.C.Tech 2ndSemester Page 112 .Millman and C.Halkias.Halkias.Halkias.Halkias.Halkias Integrated Electronics – J.C.Halkias. 1 24 Gain-Bandwidth Product.Millman and C.Millman and C.Millman and C.Millman and C.Halkias Integrated Electronics – J. Tata McGraw Hill.C.Millman and C.C.Millman and C. 1 Black board and Chalk 25 Revision class on Unit -3 1 Black board and Chalk 20 1 1 Black board and Chalk Black board and Chalk Black board and Chalk Integrated Electronics – J. Analysis of JFET multi stage amplifiers CD-CS and two stageRC coupled amplifier.C.Millman and C. Integrated Electronics – J.Millman and C.Electronic circuit analysis 12 13 14 15 16 Lecture Plan Analysis of BJT multi stage amplifiers CC-CC.Halkias II B.C.Millman and C. Emitter follower at higher frequencies. Analysis of JFET multi stage amplifiers CD-CG amplifier.C.C. Analysis of BJT multi stage amplifiers CE-CC amplifier. Chalk and Integrated Electronics – J. 1 Black board and Chalk Integrated Electronics – J.Millman and C.Halkias. Tata McGraw Hill.Millman and C.C. Integrated Electronics – J. Tata McGraw Hill.C.C. Black board and Chalk Black board and Chalk Integrated Electronics – J.Halkias. Tata McGraw Hill. Frequency response of BJT Amplifier Relation between hybrid PI parameters and H parameters.Millman and C.C.C.Halkias Integrated Electronics – J.Halkias Integrated Electronics – J. Integrated Electronics – J.FREQUENCY RESPONSE 18 Logarithms. Tata McGraw Hill.Halkias 1 21 Hybrid PI parameter variation with Ic and Vce and Temperature Effect of coupling and bypass Capacitors CE amplifier high frequency analysis using hybrid PI model. Vignan Institute of Technology & Science 1 Black board. UNIT-3: BJT AMPLIFIERS. Current Gain with resistive Load 1 23 Single stage CE Transistor Amplifier Response.Millman and C.Millman and C. Integrated Electronics – J.C. C.C.C.C.Millman and C.C.C.Halkias UNIT-5: FEEDBACK AMPLIFIERS 36 The basic concepts of feedback.C.Electronic circuit analysis Lecture Plan LCD Projector 27 Explain Basic concepts and MOS Small Signal model.C.Millman and C.Halkias Integrated Electronics – J.Halkias Integrated Electronics – J.Millman and C.Halkias Integrated Electronics – J.Millman and C. 1 28 common source amplifier with Resistive load. Chalk and LCD Projector Black board.C.Halkias Black board.Millman and C.Halkias Integrated Electronics – J.Halkias II B.Halkias Integrated Electronics – J.Tech 2ndSemester Page 113 .Halkias Integrated Electronics – J. 1 31 Common Gate stage. classification of feedback amplifiers General characteristics of Negative Feedback Amplifiers.Halkias Integrated Electronics – J.Halkias Integrated Electronics – J. Chalk and LCD Projector Black board. 1 32 Folded Cascode amplifier 1 33 Explain their frequency response 1 34 Revision class on Unit -4 1 Integrated Electronics – J.Millman and C.Halkias Integrated Electronics – J. 1 29 Explain common source amplifier with Resistive load and derive the Maximum voltage gain 1 30 Source follower with small signal model. Chalk and LCD Projector Black board.C. Chalk and LCD Projector Black board. 1 40 Current series feedback amplifiers and with transistor 1 35 Vignan Institute of Technology & Science 1 1 Black board and Chalk Black board and Chalk Black board and Chalk Black board and Chalk Black board and Chalk Black board and Chalk Integrated Electronics – J.Halkias Integrated Electronics – J.Millman and C. Chalk and LCD Projector Black board and Chalk Integrated Electronics – J.Millman and C.C.Millman and C.Millman and C.Millman and C.Millman and C.Halkias Integrated Electronics – J.Millman and C.Millman and C. Chalk and LCD projector Black board.C. 37 Effect of Feedback an amplifier characteristics 1 38 Voltage series feedback amplifiers 1 39 Voltage shunt feedback amplifiers and with transistor.C.C. 1 55 Analysis of Inductive coupled Class A power amplifier.Halkias Integrated Electronics – J.C.C.Millman and C.Millman and C. 1 45 RC Phase shift Oscillators.C.Halkias Integrated Electronics – J.C. 1 44 Classification of Oscillators and Condition for Oscillations.C. 1 46 Wien-Bridge. 1 42 Illustrative problems 1 43 Difference between positive FB and negative FB amplifiers. 1 56 Analysis of Class B Power amplifiers.C.Millman and C.C.Millman and C.Millman and C.Millman and C. Chalk and LCD Projector Black board and Chalk Black board and Chalk Black board Integrated Electronics – J.Millman and C.Halkias Integrated Electronics – J.C.Halkias Integrated Electronics – J.Millman and C.Millman and C.Millman and C. 1 53 Classification power amplifiers and their operations 1 54 Analysis of Class A Series – fed and transformer coupled power amplifier.Halkias Integrated Electronics – J.Millman and C.Halkias II B.Millman and C.Millman and C.Halkias Integrated Electronics – J.C.Halkias Integrated Electronics – J.C. 1 Black board and Chalk Black board and Chalk Black board and Chalk Integrated Electronics – J.Halkias Integrated Electronics – J.Halkias Integrated Electronics – J.Halkias UNIT-7:LARGE SIGNAL AMPLIFIERS 52 DC and AC load lines.Halkias Integrated Electronics – J.Millman and C.Electronic circuit analysis Lecture Plan 41 Current shunt feedback amplifiers. 1 47 Hartley oscillator 1 48 Colpitt’s oscillator 1 49 Crystal Oscillators.C. Chalk and LCD Projector Black board and Chalk Integrated Electronics – J.Millman and C.Halkias UNIT-6: OSCILLATORS 50 Stability of Oscillators.C. 1 51 Revision class on Unit -6 1 Black board and Chalk Black board and Chalk Black board and Chalk Black board and Chalk Black board and Chalk Black board and Chalk Black board.C.Halkias Integrated Electronics – J.C.Halkias Integrated Electronics – J.Millman and C.Tech 2ndSemester Page 114 . 1 Vignan Institute of Technology & Science Black board and Chalk Black board.C.Halkias Integrated Electronics – J.C. Notes Notes Notes Notes II B. Integrated Electronics – J.Millman and C. 1 and Chalk Black board and Chalk Black board and Chalk Integrated Electronics – J.Halkias Integrated Electronics – J.Millman and C.Halkias UNIT-8: TUNED AMPLIFIERS 59 Introduction about tuned amplifiers.Millman and C.C.C. 1 62 63 Effect of Cascading Single Turned amplifiers on bandwidth.Halkias Integrated Electronics – J.C. 1 65 Stability of tuned Amplifiers 1 66 Problems.Halkias Integrated Electronics – J.C. resonant frequency 1 60 Q-Factor and problems. 1 Stagger tuned amplifiers Stability of tuned Amplifiers.Millman and C.Halkias 1 64 Vignan Institute of Technology & Science Black board and Chalk Black board and Chalk Black board and Chalk Black board and Chalk Black board and Chalk Black board and Chalk Black board and Chalk Black board and Chalk Black board and Chalk Black board and Chalk Black board and Chalk Integrated Electronics – J. Effect of Cascading Double Tuned amplifiers on bandwidth.Halkias. Tata McGraw Hill.C.Millman and C.C. 1 67 Revision on I and II Units 1 68 Revision on III and IV Units 1 69 Revision on V and VI Units 1 70 Revision on VII and VIII Units 1 Integrated Electronics – J.Halkias Integrated Electronics – J. 1 61 Small Signal Tuned amplifiers.C.C.C.Electronic circuit analysis Lecture Plan 57 Heat sink and its design.Halkias Integrated Electronics – J.Millman and C.Millman and C.Tech 2ndSemester Page 115 .Halkias.Millman and C. Tata McGraw Hill.Halkias Integrated Electronics – J.Millman and C. 1 58 Revision class for Unit 7.C.Millman and C. LEARNING OBJECTIVES . 9.Tech 2nd Semester Page 117 . Derive an equation for CE current gain with load. Explain the effect of coupling and bypass Capacitors. CD-CG and two stage RC coupled amplifier. Explain the procedure to make analysis of BJT multi stage amplifiers CC-CC. 5. 5. Explain the variation of hybrid PI parameters with Ic and Vce and Temperature. Define high frequency and low frequency response of BJT amplifiers. Explain Emitter follower at higher frequencies. Explain the procedure to make analysis of BJT difference amplifier UNIT III: BJT AMPLIFIERS.FREQUENCY RESPONSE At the conclusion of this unit student will 1. 6. 11. 3. 2. 7. 2. Define Logarithms. Vignan Institute of Technology & Science II B.CE-CC and two stage RC coupled amplifier. 10. Draw the BJT CE high frequency hybrid PI model and explain about the model parameters. 4. input and output impedance for small signal low frequency BJT amplifiers Derive equations for voltage gain. Decibels. Derive an equation for CE short circuit current gain. 7. Derive equations for relation between hybrid PI parameters and H parameters. 1 2 3 4 Explain different types of coupling methods used in multi stage amplifiers. Derive equations for relation between Gain-Bandwidth Product. Define small signal operation of BJT Define low frequency operation of BJT Draw the small signal low frequency models of BJT Derive equations for voltage gain.Electronic circuit analysis Learning Objective LEARNING OBJECTIVES UNIT I: SINGLE STAGE AMPLIFIERS At the conclusion of this unit student will 1. 4. 3. current gain. Explain the procedure to make analysis of JFET multi stage amplifiers CD-CS. 6. 8. Explain Single stage CE Transistor Amplifier Response. input and output impedance for small signal low frequency Explain the 3db band width of an amplifier Derive equations for 3db band width BJT amplifiers Explain Miller’s Theorem and its significance in amplifier circuit analysis UNIT II: MULTI STAGE AMPLIFIERS At the conclusion of this unit student will Explain the need for multi stage amplifiers. 8. 7. Explain Current shunt feedback amplifiers. Explain the operation of Class A and Class B amplifiers. 5. 7. 5. 8. Explain Folded Cascode amplifier. Explain Current series feedback amplifiers. 10. Derive the frequency of Oscillation for RC phase shift oscillator. Explain the difference between positive FB and negative FB amplifiers. 2. Derive an equation for maximum efficiency of series –fed Class A power amplifier.VII: LARGE SIGNAL AMPLIFIERS At the conclusion of this unit student will 1. classification of feedback amplifiers. Explain Cascode amplifier. 3. Define DC and AC load lines of the amplifiers. Vignan Institute of Technology & Science II B. 5. 6. 2.Electronic circuit analysis Learning Objective UNIT IV: MOS AMPLIFIERS At the conclusion of this unit student will 1.Tech 2nd Semester Page 118 . Explain Wien bridge oscillator. 5. Explain Voltage shunt feedback amplifiers. 3. Explain General characteristics of Negative Feedback Amplifiers. Explain Source follower Explain Common Gate stage. Distinguish among Class A. Explain common source amplifier with Resistive load. UNIT. 6. Explain Voltage series feedback amplifiers. UNIT V: FEEDBACK AMPLIFIERS At the conclusion of this unit student will 1. UNIT VI: OSCILLATORS At the conclusion of this unit student will 1. 4. Explain Basic concepts and MOS Small Signal model. 6. Explain the Classification of Oscillators. Derive the frequency of Oscillation for colpitts oscillator. 3. 4. 4. 4. 2. Explain effect of Feedback an amplifier characteristics. 2. Condition for Bharkhausen criterion for Oscillation. 3. Derive the Condition for Oscillations. 9. Derive an equation for maximum efficiency of transformer coupled Class A power amplifier. Explain the Stability of Oscillators. Explain their frequency response. Explain Crystal Oscillators. 7. Explain the basic concepts of feedback. Derive the frequency of Oscillation for Hartley oscillator. B and C amplifiers. Explain different methods to stabilize tuned amplifiers. Explain the frequency response characteristics of Tuned amplifiers. Explain the applications of Tuned amplifiers. Explain how instability takes place in Tuned amplifiers. Explain the need for Tuned amplifiers. Explain the need for Stagger tuning in Tuned amplifier. Derive an equation for maximum efficiency of transformer coupled Class A power amplifier. 5. 9. Explain the need and operation of single and double tuned amplifiers. 10. 7. 2. Derive an equation for maximum efficiency of Class B power amplifier. 3. 4. Explain the operation of Class D and Class S power amplifiers. 6. 8.Tech 2nd Semester Page 119 . UNIT-VIII: Tuned Amplifiers At the conclusion of this unit student will 1. Explain the operation of Class B Push pull and complimentary Symmetry circuits.Electronic circuit analysis Learning Objective 6. Explain the frequency response characteristics of Stagger Tuned amplifiers. Explain the need for Heat sinks in power amplifiers. Vignan Institute of Technology & Science II B. And give the design procedure for Heat sink design. 7. 8. OBJECTIVE TYPE QUESTIONS . 5*10-2 c) 2.5*10-3 9.Tech 2nd Semester Page 121 . b) Are obtained from different characteristics c) Are defined by using open and short circuit terminations d) Apply to circuit contained in a black box 2 the smallest of the four h-parameters of a tristor is. the current gain of a typical CE amplifier stage has magnitude of the order of a) 0. the current gain of atypical CE amplifier stage has Magnitude of the order of. a)0.5*10-6 b) 2. 9 Parameter hoe of a typical tristor is of the order of a) 2.98 b) 5 c) 50 d) 400 Vignan Institute of Technology & Science II B.Electronic circuit analysis Objectives Questions OBJECTIVE TYPE QUESTIONS UNIT I: Single stage amplifiers 1 the h parameters are called hybrid because they [ ] [ ] [ ] [ ] [ ] [ ] [ ] [ ] [ ] [ ] [ ] a) Are mixed with other parameters.5 μS b) 25 μS c) 250 μS d) 2. a) h11 b)h12 C) h21 3 d) h22 Typical value of hie is a) 1KΩ b) 10KΩ c) 25KΩ d) 50KΩ 4 5 6 The voltage gain of tristor amplifier is lowest in a) CE configuration g b) CB configuration c) CC configuration d) Same in all configurations Tristor amplifier has Lowest input Impedance in a) CB configuration b) CE configuration c) CC configuration r d) Same in all configurations Parameter hfe of a typical tristor is of the order of a) 5 b) 50 c) 500 d) 2000 7 Parameter hie of a typical tristor is et the order of a) 1OOKΩ 8 b) 1000Ω c) 1O000KΩ d) 10OKΩ Parameter h of ¤ typical tristor is of the order of a)2.98 b) 5 c) 50 d) 400 11 With load impedance of 4Ω.5*10-4 d) 2.5 mS 10 With load impedance of 4Ω. C 20 c II B. the input resistance of a typical CE amplifier stage has magnitude of the order of [ ] a) 10 Ω b) 100 Ω c) 1000 Ω d) None 13 With source resistance Rs of 1000 Ω. the input Resistance RI a) Remain unaltered b) Reduces c) Increase normally d) Increase very much 17 The current gain of tristor amplifier is lowest in a) CB configuration b) CE configuration c) V CC configuration d) same in all configurations 18 The voltage gain of tristor amplifier stage is lowest fn a) CB configuration b) CE configuration c) CC configuration d)4 Same in all configurations 19 Tristor amplifier stage which has lowest output impedance in a) CB configuration b) CE configuration c) CC configuration d) Same in all configurations 20 Tristor amplifier stage has highest input impedance in a) CB configuration [ ] [ ] [ ] [ ] [ ] b) CE configuration c) CC configuration d) Same in all configurations Answers: 1.98 [ b) 5 c) 50 ] d) 500 15 With typical load resistance of 4KΩ the voltage gain of a typical CC amplifier stage is of the order a) 0.Electronic circuit analysis Objectives Questions 12 with load impedance of 4 Ω.99 V [ b) 5 V c) 20 V ] d) 200 V 16 In a CE amplifier stage on introducing a resistor RE in the emitter circuit. C 14 a Vignan Institute of Technology & Science 5.d 12 d 3.b 16d 7. the output impedance of a typical CE amplifier Stage is ofthe order of a) 5OOK Ω [ b) 5KΩ c) 50KΩ ] d) 50OKΩ 14 With typical load impedance of 4KΩ. the current gain of a typical CB amplifier stage Is of the order of a) 0. B 19 c 10.Tech 2nd Semester Page 122 .b 17a 8.c 11 d 2. C 18 c 9.a 13 d 4.a 15a 6. the phase shift introduced at high 3-dB frequency ls. the high 3-all frequency fh. the high 3-dB frequency may be increased by. a) Remains unaltered b) Increases c) Decreases d) May increase or decrease 8) The 3dB frequency of an amplifier is one at which gain reduces to.E.C coupled amplifier stage. 3) In an R. the phase shift introduced in the middle frequency ls. the low 3-dB frequency may be reduced by.C coupled amplifier stage as the value of total effective shunt capacitance Increases. One advantages of transformer coupling in transistor amplifiers is that.C coupled amplifier. a) Reducing the value of coupling capacitor Cb b) Increasing the value of coupling capacitor Cb c) Reducing the total effective shunt capacitance d) Increasing the total effective shunt capacitances. a) Zero b) 180° c) 270° d) 90° [ ] 5) In single stage R.C coupled amplifier stage as the value of coupling capacitor C b is increased the low 3 dB frequency [ a) Remains unaltered b) Increases c) Decreases ] d) May increase or decrease 7) In an C.C coupled amplifier.C coupled amplifier stage. a) Unity b) Zero c) 1/√2 of its midband value [ ] [ ] d) Half of its midband value 9).C coupling amplifier. [ ] [ ] a) It is simple and less expensive than other coupling methods b) It provides excellent response c) Low power supply may be used d) High efficiency and high power output is obtained 10) An advantage of RC coupled amplifier is it's Vignan Institute of Technology & Science II B.Tech 2nd Semester Page 123 . a) Reducing the value of coupling Cb b) Increasing the value of coupling capacitor Cb c) Reducing the total effective shunt capacitance in the output circuit d) Reducing the total effective shunt capacitance in the input circuit of hybrid-π model 4) in single stage R. 2) In an R. the reduction In voltage gain in the low frequency Range results due to. a) Zero b) 180° c) 135° d) 225° [ ] 6) In an R. R. a) Coupling capacitor Cb [ ] [ ] [ ] b) Shunt capacitance in the input circuit c) Shunt capacitances in the output circuit d) Input impedance of the next stage.Electronic circuit analysis Objectives Questions UNIT II: Multi stage amplifiers 1) In an R. a) 1000 pF b) 0. c 17.c 15.c 14 c 6.b 11 d 3.C coupling c) Trformer coupling d) Inductor coupling 14) Transistor amplifier stage has highest input Impedance in a) CB configuration b) CE configuration c) CC configuration d) same in all configurations 15) In a RC coupled amplifier by pass capacitor (Cc) is used for a) Decrease the load value b) Increase the load value c) Attain proper stability d).C resistance in the collector circuit is low c) Collector voltage is stepped down d) Flux linkages are incomplete 13) ln cascade amplifier the coupling method capable of providing highest gain is a) RC coupling b) D. d 18 b UNIT III: BJT Amplifiers.c 16.Tech 2nd Semester Page 124 . typical value of coupling capacitor is.c 8.b 2.1 μF c) 0. b 13 c 5.d 12 b 4.Electronic circuit analysis Objectives Questions a) High efficiency b) Economy c) Excellent frequency response d) Good impedance matching.c 7.b 9.Frequency Response 1) α-cut off frequency of BJT. coupling capacitor (CC) is used a)To Match the next stage b) To limit the bandwidth c) To isolate the D. 11) in an RC coupled tristor amplifier.C component d) To control the output voltage 17) The effective load for 1st stage in multistage amplifier having identical stages a) Less than last stage b) Equal to the last stage c) Greater than last stage d) None of the above 18) An amplifier having a gain of 100 gives an output of 2v then input signal a) 200V b) 20 mV c) 50 V d) 2 mV Answers: 1.01 μF [ ] [ ] [ ] [ ] [ ] [ ] [ ] [ ] d) 10 μF 1 2) Transformer coupling provides high efficiency because the a) Collector voltage is stepped up b) D.a 10. Decrease VCE 16) In a RC coupled amplifier. a) Increases with increase in base width [ ] b) Increase with increase in emitter width c) Increase with increase in collector width d) Increase with decrease in base width Vignan Institute of Technology & Science II B. ¶ parameters are independent of frequency only when 2¶f*w2 /6Db a) = 1 b) > 1 c) C< 1 d) << 1 12) gm of a tristor a) A varies directly with VCE b) varies inversely with VCE c) Varies directly as (VCE)2 d) is independent of | VCE | 13) gm of a tristor is proportional to a)1/t b)1/t2 c)1/√t 14) The base-emitter resistance rb’e d)1/√c a) is independent of T b) is independent of Ic Vignan Institute of Technology & Science II B. reaches a minimum and then decreases with further increase of IC d) is not a function of IC 3) A npn transistor has fß = 1MHz and ßo = 200. a) 200MHz . the hybrid. 220MHz [ ] [ ] [ ] [ ] [ ] [ ] [ ] [ ] [ ] [ ] [ ] 4) The ft of BJT ls related to Gm . C¶. c) 2¶fT d) fT/2¶ 11) According to Giacolletto. and fα are respectively.Electronic circuit analysis Objectives Questions 2) The CE short-circuit gain ß of a tristor [ ] a) is a monotonically increasing function of IC b) is a monotonically decreasing function of IC c) increases with IC for low values of IC . and Cµ as as fT = ------------------5) An npn transistor (with Cµ = 0.. Hybrid-¶: model is valud a) up to fT/3 b) up to fT c) up to 3fT d) upto fT/2 8) fT is the frequency at which the short-circuit gain becomes a) 1/√2 b)2 c) 1/2 d) 1 9) gb’e = a) hfegm b) hfe/gm c) gm/ hfe d) none 10) CE = gm/P' P a) fT b) ¶ft.Tech 2nd Semester Page 125 .3 pF) has { ft of 400 MH at a die bias of ic = 1 mA The value of C¶ is a) 15 b) 30 c) 50 d) 96 6) The hybrid-pi model can be used at a) Low frequencies only b) High frequencies only c) At both low and high frequencies d) In the mid frequency region only 7). Its ft. 199MHz c) 199MHz . 200MHz A d) 201MHz .l 201MHZ A b) 2000MHz . a 14.d 13.d 19.c 7.a 6.c 11. decreases c) because of (a) CE decreases with increasing VCE d) because of (b) CC decreases with increasing VCE 17) The collector capacitance b) is proportional to (VCE) —n a) depends on VCE c) Decreases with increase in VCE d) all the above 18) With increase ln VCE a) CC decreases b) CE decreases c) gm decreases d) a + b .Electronic circuit analysis Objectives Questions c) is directly proportional to T and inversely proportion to IC d) is directly proportional to IC and inversely.d 17.d 9. d 18. d 4.c 15.Gm/2¶( Cµ+ C¶) 5. Effective base width. c 3.c 10.1 pF c) 100 pF [ ] [ ] d) 1 pF 3 The dynamic drain resistance of MOSFET is of the order of Vignan Institute of Technology & Science ] d) 0. y proportional to T 1 5) The emitter capacitance CE ls proportional to a) Ic [ ] [ ] [ ] [ ] [ ] [ ] c) √Ic d)1/√ Ic b)1/ Ic 1 6) As vce increases a) the effective base width increases b) the. 19) The parameters that are independent of VCE a) gm b) CE C)CC d) all 20) With increasing temperature a) rb’e increases b) rb’e decreases c) rb’e does not change d) CC increases Answers: 1. a UNIT IV: MOS Amplifiers 1) The transconductance (gm) of a MOSFET is of the order of a) 100 mhos b) 50 mhos c) 0.01 mhos b) 0.d 12.a 16.Tech 2nd Semester Page 126 .a 8. d 2.1 mhos 2) Interelectrode capacitances in a MOSFET are of the order of a) 1 pF [ II B. a 20. D 2.is commonly used as a voltage buffer 7. b) Voltage—series type c) Current-series type d)Current—shunt type 4 Positive feedback is used in a) Amplifiers b) Transistor c) oscillators [ ] [ ] [ ] d) None 5 When the feedback energy (voltage or current) is out of phase with the input signal and thus opposes it. SOURCE FOLLOWER 7. ------------------. B 6. a) Direct feedback b) Positive feedback c) Regenerative feedback d) Degenerative feedback Vignan Institute of Technology & Science II B.Electronic circuit analysis b) 100M Ω a) 1OKΩ Objectives Questions c) 500k Ω d) 5M Ω 4 A MOS tristor itself can be used as a current if it operates in a) Triode region b) cut-off region c) Saturation region d) None of the above. LOW Unit V: Feedback Amplifiers 1 The negative feedback in an amplifier [ ] [ ] a) Reduces the voltage gain b) Increases the voltage gain c) Does not affect the voltage gain d) Can convert it in to an oscillator if the amount of feedback is enough 2 Negative feedback in amplifiers a) Lowers its lower cut-off frequency b) Raises its upper act—off frequency A c) Increases the band-width d) Current-shunt type 3 Emitter follower Is a) Voltage-shunt type. SOURCE 8. Common gate amplifier has----------------------.terminal of MOSFET 8. A 3.input impedance Answers: 1.Tech 2nd Semester Page 127 .input is applied at a -----------. 5 An important property of the cascade structure is its a) Low input impendence b) High—output impedance c) Low output impedance d) High output impedance [ ] [ ] 6. C 5. it is called. A 4. In a common gate amplifier . current sampling [ ] a) Does not alter the output resistance b) Tends to increase the output resistance c) Tends to decrease the output resistance d) Produces the same effect on input resistance as voltage sampling I4 In a negative feedback amplifier. voltage sampling a) Does not alter. series mixing [ a) Does not alter the input resistance. input resistance d) Produces the same effect on input resistance as shunt mixing 13 In negative feedback amplifier.Tech 2nd Semester Page 128 . c) Tends to decrease the input resistance ] b) tends to increase the. the output impedance a) Decreases b) Increases c) Remains same [ ] [ ] [ ] [ ] [ ] [ ] d) None All 9 The voltage shunt feedback a) Increases both the input and output impedances b) Increases input impedance and decreases output impedances c) Decreases both the input and output impedances d) None 10 The current series feedback a) Increases both the input and output impedances b) Decreases both the input and output impedances c) Increases input impedance and decreases output impedance d) None 11 In a negative feedback amplifier.-the output resistance [ ] b) tends to increase the output resistance c) Tends to decrease the output resistance a d) Produces the same effect on input resistance as current sampling 15 In a feedback amplifier. loop gain is Vignan Institute of Technology & Science [ ] II B. shunt-mixing a) Does not alter the output resistance b) Tends to increase the input resistance C) tends to decrease the input resistance d) Produces the same effect on input resistance as series mixing 12) In a negative feedback amplifier.Electronic circuit analysis Objectives Questions 6 The advantages of negative feedback is a) Reduction is distortion b) Stability in gain c) Increased bandwidth d) All 7 In voltage series feedback a) Increases the input impedance b) Decreases the gain c) Decreases the output impedance d) All the above 8 In current-shunt feedback. What is the gain of the amplifier with original distortion and With reduced distortion? a) 6.5 b) 60.C 11.B 18 B 19.A 17. depending on the feedback factor b) Will always be unstable at high frequencies .D 7. a) Tuned collector oscillator Vignan Institute of Technology & Science b) Hartley oscillator II B. 6 18 Transmission gain in negative feedback amplifier a) A/(1+/ Aß ) b) Aß C) 1/ Aß d) A/(1. 90 d) 1. a) An amplifier [ ] [ ] [ ] b) An amplifier with feedback c) Converter of a.B 14.D 8. c) Will be stable for all frequencies.C 5. d) Just like an alternator 2 For sustaining oscillations in an oscillator a) Feedback factor should be unity b) Phase shift should be zero c) F Feedback should be zero d) Both (a) and (b) 3 For generating 1KHz frequency. d) Will oscillate at low frequencies Answers: 1A 2.A 20.B 9.C 15.Aß) 19 Negative feedback a) Decreases lower cut off and increase higher cut off frequencies b) Decreases higher and lower cut off frequencies c) Increases higher and lower cut off frequencies d) None 20 An amplifier with resistive negative feedback has two left half plane poles in its Open-loop transfer function. sensitivity D equals a) 1+ Aß b) 1.Aß c) Aß [ ] [ ] [ ] [ ] [ ] d) 1/( Aß+1) 1 7 It is desired to reduce total harmonic distortion of an amplifier from 85 to 20% by use of 5% feedback. C 12. C 10.Electronic circuit analysis a) 1/Aß Objectives Questions c) — Aß b) Aß d) -1/ Aß 16 in a feedback amplifier.B 13.C 16. to d.D 6.C 3.B 4. 1.c. the most suitable circuit is.Tech 2nd Semester Page 129 . the amplifier a) May be unstable.c.5.C UNIT VI: Oscillators 1 An electronic oscillator is. 15 c) 15. d) Wide range of high purity sine waves is to be generated 16 Electronic oscillator is better than mechanical one because Vignan Institute of Technology & Science [ ] II B.Wein bridge oscillator is most often use whenever a) Square output waves are required [ ] [ ] [ ] b) High feedback ratio is needed A c) Extremely high resonant frequencies are required .Electronic circuit analysis Objectives Questions c) Collpitt’s oscillator d) Wein bridge oscillator 4 The phase difference between input and output voltage of an oscillator is. a) 180° b) 360° c) 90° b) AB = 1/29 c) AB = 29 a) Amplifier without feedback b) Amplifier with positive feedback c) Amplifier with negative feedback d) ac to dc converter 7 The maximum phase shift produce by an ideal section of the RC circuit Is b) 90° c) 30° [ ] [ ] [ ] [ ] d) AB = 3 6 An electronic oscillator contains a) 45° ] d) 270° 5 Barkhausen criteria says a) AB = 1 [ d) 60° A 8 The phase shift introduced by RC network section is a) Greater than introduced by the amplifier b) Less than introduced by the amplifier c) Equal to that introduced by the amplifier d) None of these 9 The number of RC sections required in phase shift oscillator is at least a) One b) Two c) Three [ ] [ ] [ ] [ ] d Four 10 The phase shift oscillator can produce a) Rectangular wave shapes b) Sine waves c) Irregular wave shapes d) DC voltages 11 The weinbridge oscillator uses a) Negative and positive feedback both b) Negative feedback only c) Positive feedback only d) None of the above 12 In oscillator circuit the energy feedback to its input terminal from the a) 90° out of phase with the input signal b) 180° out of phase with input signal c) In phase with the input signal d) None 13 To generate a 1 MHZ signal.Tech 2nd Semester Page 130 . it will a) Produces high frequency whistles b) Stop oscillating c) Produce damped waves continuously d) Become an amplifier 15 . the most suitable circuit is a) Colpitts oscillator b) Phase shift oscillator c) Wein bridge oscillator d) None of the above 14 lf Barkhausen criterion is not fulfilled by an oscillator circuit. maximum theoretical efficiency is a) 78.D 12.C 17.C 3.5% II B.A 15.Tech 2nd Semester Page 131 .5% 5 Of the following power-amplifiers.VII: Large Signal Amplifiers 1 ln class-A large signal amplifiers.D 6. conduction angle is a) 360° b) 180° c) 180°-360°' b) 50%.B 7. c) 78.Electronic circuit analysis Objectives Questions a) It can produce 20Hz to 20OHz b) It has better frequency stability c) It has higher efficiency d) none 17 The current amplification factor in radian square of Colpitt’s oscillator is a) C1 C2 b) C1 – C2 c) C1/C2 [ ] [ ] d) C1 +C2 18 The feedback factor B at frequency of oscillation of Wein bridge oscillator is a) -1/29 b) 3 c) 1/29 d) 1/3 19) In tuned collector oscillator.amplifiers.B 16.5 [ b) 25% c) 50% d) 78.A 14.5% 8 Maximum theoretical conversion efficiency of class A transformer coupled amplifier is a) 15% b) 25% C) 50% 9 Maximum theoretical collector circuit efficiency of class B amplifier is Vignan Institute of Technology & Science d) 78.A 2. frequency w of oscillation is where wo.C 5.5% b) 50% c) 25% b) Class-B [ ] [ ] [ ] [ ] [ ] [ ] [ ] c) Class-AB d)Class-C 6 For a class-B amplifier. which has maximum theoretical efficiency a)Class-A [ d) 25% 4 In transformer coupled power.B 8.C 11.amplifier.A 4. C 9.D 13.B 19. A UNIT. is frequency of resonance a) >wo b) w/hfe C) <wo d) =wo [ ] Answers: 1.5% ] d) < 180° 3 In series-fed class-A power amplifier maximum theoretical efficiency is a) 28. Q-point is located a) Below cut-off b) At cut-off c) On center of load line d) below midpoint of load line 2 In class-A power.C 18. a) 15% ] d) 28.D 16.D 10. Q-point is located · a) Below cut off b) on cut-off c) Below midpoint of load line d) none of the above 7 Maximum theoretical conversion efficiency of class A series fed amplifier is. the frequency response depends on.a 10.5% 10 In the output of a push pull amplifier.. Collector dissipation to maximum ac power output is about a) 0.d 13.a 12.b 3. a)1/2¶√LC b) 1/√LC [ c) 1/2¶√LC*√1-CR2/ L ] d) 1/2¶√LC*√1-CR/ L2 2 At resonance the impedance of a parallel tuned circuit formed by capacitor C (lossless) and inductor L (with series resistance R) approximately equals a)L/CR b)LC/R c)LR/C b)2 f0/Q0 c) Q0 f0/ ] [ ] [ ] d)1/LCR 3 3-dB bandwidth in Hz of a parallel tuned circuit equals. b) D=√D22+D32+D42+……. a) √2 f0/Q0 [ √2 d) f0/Q0 Where f0 is the frequency of resonance and Qo is the effective Q at resonance. 16 The main purpose of using transformer coupling in a class A amplifier is to make it more a) Efficient b) Less costly c) Less bulky d) Distortion free [ ] Answers: 1...d 2. 4 In a Single tuned capacitance coupled amplifier...a 7. C) D=√B0+D22+D32+D42+……...c 9.. d 11. total harmonic distortion is given by a) D=D2+D3+D4+ .Electronic circuit analysis a) 15% Objectives Questions b) 25% c) 50% d) 78..d 6.b 5./ (√D22+D32+D42+……. d) D= D2+D3+D4+ .5 [ ] [ ] d) 0.c 16. then maximum output power Pmax equals 2 a) Vcc /RL b)√VCC/2RL 2 c)Vcc /2√RL ] [ ] [ ] d)Vcc /2RL 14 Class B push pull amplifier suffers from a) Crossover distortion b) Inter modulation distortion c) Excessive harmonic distortion d) Phase distortion 15 A push pull amplifier a) Eliminates add harmonics [ 2 b) Eliminate even harmonics st c) Is a 1 stage of an audio amplifier d) Uses single transistor.) 13 in a class B amplifier.. the ratio of the maximum...4 c) 0.b 8.25 · b) 0...a UNIT-VIII: Tuned Amplifiers 1 Following is the expression for frequency (Hz) of a parallel tuned circuit formed by capacitor C (lossless) and inductor L (with series.b 14. resistance R).b 4..b 15.. a) Only the input circuit Vignan Institute of Technology & Science b) Only the output circuit II B.Tech 2nd Semester Page 132 .75 12 ln a large signal amplifier. the most disturbing harmonic distortion is the a) Second harmonic b) Third harmonic c) Fourth harmonic [ ] d) Fifth harmonic 11 in c class B push pull amplifier. the effective Q of the output circuit at resonance depends.a 3.Tech 2nd Semester Page 133 . tapping on the coil is used to. [ a) Only at the frequency of resonance fo b) at one more frequency other than fo c) at two more frequencies other than f0 d) at 4 more frequencies other than f0 ] Answers: 1. c 8. a) Permit use of smaller coiled b) Permit use of smaller tuning capacitor c) Permit maximum transfer of power d) Permit adjustment of 3-dB bandwidth 9) ln a double tuned amplifier with coupling greater than critical. [ a) Only on inductance L ] b) Only on capacitance C c) Only on effective shunt resistor Ri d) on suscuptance of L (or C) and shunt resistance Ri 6 In a capacitance coupled single tuned amplifier. maximum transfer of power takes place. phase angle of the relative voltage gain A/Am equals. [ a) arc tan (2δQe) b) -arc tan (2δQe) c) arc tan (δQe) ] d) -arc tan (δQe) 7 The 3-dB bandwidth (radians/sec) of a single tune capacitance coupled amplifier is. b 7. b II B. b Vignan Institute of Technology & Science 5.c 2. d 6. d 4.Electronic circuit analysis Objectives Questions c) Both input and output circuits ‘d) Neither input circuit nor output circuit 1 5 In a capacitance coupled single tuned amplifier. a) Req C b) C/ Req c)1/ Req C d) Req/C [ ] [ ] 8 ln a single tuned tapped capacitance coupled amplifier. c 9. ESSAY TYPE QUESTIONS . RI1.Electronic circuit analysis Essay Questions ESSAY TYPE QUESTIONS UNIT I: SINGLE STAGE AMPLIFIERS 1 Draw the AC equivalent of a CE amplifier with fixed bias using h-parameter model and 2 Derive the expression for Ri. VCC 12kOhm 3.hfe=75. AV. Ro. and RO’ by using below figure. Av & Ai of CB configuration 5 Draw ac equivalent circuit for a CE Amplifier (i) with bypassed emitter resistor and find AVS & AIS (ii) with an un bypass emitter resistor and find RI & RO 6 A transistor with hie=1. (a) For the circuit shown in figure1. Calculate AI.AI and Avs for CE amplifiers 3 Draw the equivalent circuit of a CE amplifier with un bypassed emitter resistor using 4 h. estimate A i. AIS.hre=200*10 -4.5kOhm Vo 1uF 37kOhm 1uF Q1 2.5kOhm 1. Av.Parameter model and derive the equations for Zin. RI.2kOhm BC107BP 1uF V1 37kOhm 320 Ohm 1uF Ri1 Ri 7. AVS.2k.hoe=20microA/V is connected in CE configuration given below. RO. Zout.Tech 2nd Semester Page 135 . Ri & Ro using resonable Vignan Institute of Technology & Science II B. Av. 9. (b) For a CE amplifier. input impedance. hie = 2k. (a) When n-identical stages of amplifier are cascaded. 10. (b) Draw the simplified hybrid model for the CC circuit and derive expressions for input Resistance. (b) Explain the effect of coupling capacitor in a CE amplifier on low frequency response of amplifier. Derive the expression for lower and upper cutoff frequencies. 8.Electronic circuit analysis Essay Questions approximations. hre is negligible & hoe = 105 mhos (b) Draw the ciruit diagram of Emitter follower and derive the equation for voltage & current gains. and output Vignan Institute of Technology & Science II B. The h parameters for the transistor are given as h fe = 100. (a) Obtain CC 'h' parameters interms of CE parameters. (a) Prove that the following two networks (a) & (b) shown in figure 6 have the same currents if excited by same voltages.Tech 2nd Semester Page 136 . calculate the voltage gain. output resistance voltage gain and current gain. Av & Ro using hie=50. calculate the mid frequency voltage gain and lower 3-dB point. 2. hoe = 24µA/V. Derive the expression for fT and fβ of CE amplifier using high frequency model. Calculate value of fH. UNIT II: MULTI STAGE AMPLIFIERS 1. Calculate Darlington pair Ri. (a) Write the equation for overall gain of a n .  (b) Derive the expression for the CE short -circuit current gain as a function of frequency. hre = 2. 8. (b) How does the frequency response an amplifier change with cascading of amplifier stages? (c) Explain the choice of configuration in a cascade of amplifiers. The circuit details are Rs=600Ω.Av. R2=2. A high frequency amplifier uses a transistor which is driven from a source with Rs=0. hie = 1. Derive the gain bandwidth product for voltage and gain bandwidth product of current. 3. hfe = 50. (iv) Output impedance 7. if RL=1k. 5. (iii) voltage gain. Derive the expression for the CE short-circuits current gain Ai with resistive load. (a) Prove that hfe=gm rb’e (b) How does gm vary withIC .FREQUENCY RESPONSE 1. Explain cascade amplifier and derive AI. hoe=25µA/v.VCE &T ? (c) Draw the small-signal high frequency CE model of a transistor. (b) A Silicon PNP transistor has an f fT = 400MHz. RL=5kΩ RE=1k Ω. (i) Discuss the effect of emitter bypass capacitor on low frequency response of BJT amplifiers. 5.1k. hre=2. If R L = 10k. 2. Assume typical values of hybrid π parameters 6. current gain.R1=15kΩ . Rs=3kΩ & RE=3kΩ. Explain the effect of emitter bypass capacitor CE on low frequency response. Explain the different types of coupling schemes 6. (a) Explain why the upper 3-dB frequency for current gain is not the same as fH for voltage gain. What are the different types of distortion in amplifiers and explain in detail. (a) How the bandwidth is efected in multistage amplifier? (b) What are the advantages of direct coupled amplifiers? (c) What is the use of transformer coupling in the output stage of multi-stage amplifier? 8.Vcc=12v. 4.5104.Electronic circuit analysis Essay Questions Impedance.stage cascaded Amplifier. The transistor has h-parameter of hfe=400 and hie=10kΩ.A&Ais Darlington pair and derivation.Ai. and CE=50µf. Compare emitter follower and Darlington emitter follower configurations in respect of. a) Define f and fT and also establish the relationship between ff and fT . What is the base thickness? (c) In terms of what parameters is the high frequency response of a CE stage obtained? Vignan Institute of Technology & Science II B.2kΩ.5×10-4 . 4. 7. (i) Current gain. (ii) For the CE amplifier. 3.Tech 2nd Semester Page 137 . UNIT III: BJT AMPLIFIERS. (ii) input impedance. 6mA & VP = -4V. find R 1 and the efective input impedance. 3. If the quiscent drain to ground voltage is 10V. assuming blocking capacitor to be large and4dgm= = 4mA/V and rd =5K[8 Vignan Institute of Technology & Science II B. 2.Electronic circuit analysis Essay Questions UNIT IV: MOS AMPLIFIERS 1. Derive the expression for voltage gain for CS amplifier with resistive load. Explain the cascode amplifier with current source load 7. (a) Derive the equation for voltage gain of a Common Source FET amplifier. 6. Draw and explain the CG amplifier. 10.channel FET having IDSS = 2mA. 9. 5.(a) Derive an expression for voltage gain of a common source FET amplifier with and without source resistance included in the circuit (b) Calculate the voltage gain of the FET amplifier shown in the figure 7. (b) The amplifier shown in figure 2 uses an n . Draw and explain the source follower circuit. Derive the expression for the voltage gain at low frequencies. 4. VP = -2V. If Vi = 10V find VO.Tech 2nd Semester Page 138 . What is the maximum value of voltage gain? (b) The FET shown in figure 5 has the following parameters: IDSS = 5. Draw and explain the CS stage with diode connected load. Draw and explain the folded cascade amplifier. State the advantages and disadvantages of source follower circuit. 8. (a) Sketch the circuit of a CS amplifier. 5. If the frequency of oscillation is 150 KHz.04 mH and C = 0. A) Draw the circuit of a voltage shunt forward bias using BJT and derive expression for all the parameters. (a) Why a FET cannot be explained with h-parameters? (b) Derive an expression for Trans .1 3. Rif. 7. 6.what are the advantages &disadvantages of positive and negative FB? B) Calculate transistance gain. How input and output impedance are affected in each case? B) What are the advantages and disadvantages of negative feedback? 2. determine the values of open loop gain A and feedback ratio β. find L11.the basic amplifier trans resistance Rmf=50kΩ.Electronic circuit analysis Essay Questions 11. (a) Derive an expression for frequency of oscillation of a RC phase-shift oscillator using a FET.1kΩ. A) Classify the amplifiers based on feedback topology and give their block diagrams. B) An amplifier has voltage gain with feedback of 100. Neglect mutual inductance. R0=40kΩ. R0f of the shunt-shunt feedback amplifier . (a) What are the characteristics of an amplifier that are modified by negative feedback? (b) Draw the four types of feedback amplifiers naming them. Draw the circuit diagram of current shunt feedback and derive the expressions for input and output resistance 4. (b) In a Hartley oscillator L 2 = 0. (c) Define sensitivity & Desensitivity factors in feedback Amplifiers.004 µF . (c) Draw and explain the FET high frequency model. hie=1. Vignan Institute of Technology & Science II B. Derive an expression for the transfer gain of a feedback amplifier. A) Explain the concept of FB as applied to electronic amplifier circuits .RL=4kΩ.β=0. UNIT V: FEEDBACK AMPLIFIERS 1.Tech 2nd Semester Page 139 .if the gain without feedback changes by 20%.conductance using FET model. Electronic circuit analysis Essay Questions UNIT VI: OSCILLATORS 1. Draw the circuit diagram of a RC phase shift oscillator using BJT .derive the expression for frequency of oscillations. 2. What are the factors that affect the frequency stability of an Oscillator? How frequency can be improved in oscillators? 3. A) Explain necessary condition for oscillators. B) A FET phase shift oscillator has gm=5mhos and rd=50kΩ. The Feedback resistance is 100kΩ and the capacitor value is 64.79PF.calculate the frequency of the oscillator and the value of Rd. 4. (i) Classify various oscillators based on output waveforms, circuit Components, operating frequencies and feedback used. ii) A FET phase shift oscillator has gm=5mhos and rd=50kΩ. The feedback resistance is 100kΩ and the Capacitor value is 64.79PF.calculate the frequency of the oscillator and the value of Rd. UNIT VII: LARGE SIGNAL AMPLIFIERS 1. Explain about class-A, class-B, class-C and class-AB operation of power amplifiers? B) A single transistor operates as an ideal class-B amplifier .if D.C current drawn from the supply is 2.5 mA; calculate the A.C power delivered to load for load resistance of 2kΩ. 2. Explain how the overall distortion is reduced in a push-pull configuration through relevant mathematicalexpressionsandcircuit diagrams. B) A transistors supplies 0.85w to a 4 kΩ load, the zero signal D.C collector current is 3 mA and the D.C collector current is 31 mA and the D.C collector current with small signal is 34mA. Determine the second harmonic distortion. 3. Derive the expression for maximum collector power dissipation Pd max in the case of class – b power amplifiers .what is its maximum efficiency? 4. Explain thermal stability and heat sinks. B) A silicon power transistors is operated with a heat sink having thermal resistance θsA=1.5 0 C/W the transistors rated at150w (250) has θJc=0.50C/W and the mounting insulation has θJc=0.60C/W Calculate the maximum power that can be dissipated if the ambient temperature is 400c and Tjmax=2000c? 5. (a) What is push-pull configuration and how does this circuit reduce the harmonic distortion? (b) For a class B amplifier providing a 20V peak signal to a 16 load operates on a power supply of Vcc = 30V. Determine the input power, output power and circuit efficiency. Vignan Institute of Technology & Science II B.Tech 2nd Semester Page 140 Electronic circuit analysis Essay Questions 6. a) What is a class B amplifier? Where is it employed? Give its circuits, design equations, characteristics & limitations. (b) A transformer coupled class A large signal amplifier has maximum and minimum values of collector to emitter voltage of 25V and 2.5V. Determine its collector efciency. 7. (a) A transistor supplies 0.8W to a 5K load. The zero signal dc collector current is 30mA, and the dc collector current with signal is 36mA. Determine the percent second harmonic distortion. (b) Define conversion efciency. Determine the maximum value of conversion efciency for a series - fed class A power amplifier. UNIT-VIII: TUNED AMPLIFIERS 1. (i)Derive an expression for tuning frequency of a single tuned amplifier in terms of quality factor and bandwidth of the amplifier. (ii) What is the need for stagger tuning in amplifiers? Compare the frequency response characteristics of the single tuned and double tuned amplifier with stagger tuned amplifier. 2. A) Explain the operation of a stagger tuned amplifier what is the effect of cascade in the tuned amplifiers. B) Discuss elaborately in the stability of tuned amplifiers. 3. A) Explain in detail the effect of cascading single tuned amplifiers and hence derive the expression for band width of n-stage amplifier. B) The band width for single tuned amplifier is 20khz.calculate the bandwidth of such three stages are cascaded .also calculate the bandwidth for 4 stages. 4. A) Draw the ideal and actual frequency response curves of a single tuned amplifier. B) Derive the expression for Q-factor of a capacitor. 5. A) draw and explain the circuit diagram and equivalent circuit using high frequency hybrid ∏ model of a single tuned capacitance coupled BJT amplifier B) Also draw and explain the obtained modified high frequency equivalent circuit after applying miller’s theorem 6. (a) Draw the equivalent circuit of a double tuned amplifier and derive the expression for gain at resonance. (b) Derive the expression for effective bandwidth of cascaded tuned amplifier 7. (a) Draw the equivalent circuit of a single tuned capacitive coupled ampifier and derive the expression for gain at resonance. (b) Draw the circuit diagram for tuned RF amplifier and explain its working. 8. (a) Draw the frequency response of tapped single tuned capacitance couplped amplifier and derive the expression for L for maximum power transfer. Vignan Institute of Technology & Science II B.Tech 2nd Semester Page 141 Electronic circuit analysis Essay Questions (b) Draw the circuit of double tuned amplifier and explain its working. 9. (a) Draw the electrical model of a piezoelectric crystal. (b) Sketch the reactance Vs frequency function. (c) Over what portion of the reactance curve do we desire oscillations to take place when the crystal is used as part of a sinusoidal oscillator? Explain. Vignan Institute of Technology & Science II B.Tech 2nd Semester Page 142 ASSIGNMENT QUESTIONS Electronic circuit analysis Assignment Questions ASSIGNMENT QUESTIONS UNIT I: SINGLE STAGE AMPLIFIERS 1. Write short notes on transistor as amplifiers. 2. Explain the single stage CE amplifiers. 3. Explain the need of C1 and C2 in CE amplifiers. 4. Comment on h-parameters with operating point and list the benefits of h-parameters 5. Draw the small signal low frequency equivalent circuit of BJT and explain each parameter of this circuit. 6. Draw ac equivalent circuit for a CE Amplifier (i) with bypassed emitter resistor (ii) with an un bypass emitter resistor 7. Using the approximate h-parameters mode .derive expressions for current gain, input resistance, voltage gain and output admittance of a CE Amplifier with a resistor in emitter circuit. 8. (a) Draw a typical CE amplifier and explain the functions of each component in it. (b) For a CE amplifier ,what is the maximum values of Rs for which Ro differ by not more than 10% of its value Rs=0; Given hie=1.1k, hfe=50, hre=2.5*10¯4, hoe=25µA/v 9. For the emitter follower with Rs=0.5k and RL=5K, calculate AI ,Ri, AV, AVs, and Ro assume hfe=50,hie=1k,hoe=25µA/v. 10. Calculate Ai,Ri,Av and Ro for the above CB Amplifier with RL=5K,Rs=500 ohms, hfe=50,hie=1k,hoe=50k,Re=10k and Rc=10k. 11. (a) Discuss the classification of amplifiers based on frequency range, type of coupling, power delivered and signal handled. (b) For the common gate Amplifier, derive expression for voltage gain, input impedance, out impedance. 12. Give the significance of Miller’s Theorem and Dual of Miller’s Theorem in the amplifier circuit analysis. UNIT II: MULTI STAGE AMPLIFIERS 1. Explain the need for multi stage amplifiers. 2. Draw and explain the block diagram of two stage cascaded amplifier. 3. Explain the procedure to find out the 3db band width of the multi stage amplifier. 4. Explain the procedure to find out the overall voltage gain, current gain, input and output impedances of the multi stage amplifier. Vignan Institute of Technology & Science II B.Tech 2nd Semester Page 144 Compare the three types of coupling methods used in multistage amplifiers. Discuss the effect of an emitter bypass capacitor on low frequency response. Discuss the effect of an emitter bypass capacitor on low frequency response. 3. 2. Explain how the hybrid parameter varies with temperature. Iv) Output impedance.Electronic circuit analysis 5. the transistors are identical with hfe=76. Calculate the lower cut off frequency of the individual stages.5k and hre=0. Assignment Questions Three identical non interacting amplifier stages in cascade have an overall gain of 1db down at 30Hz compared to midband. In hybrid π model of a transistor at high frequencies. 9. For the circuit shown in below figure. hie=1. Discuss about different types of distortions that occur in amplifier circuits. Draw the circuit diagram of single stage RC coupled BJT amplifier. 7.FREQUENCY RESPONSE 1. show that gm is proportional to the collector current. Calculate Avs and Ais. What is the order of magnitude of each resistance in the hybrid. 8. 4. 6. 10. VCC -12V R1 10kOhm Q1 Q2 2N3702 R3 1kOhm 2N3702 R2 5kOhm UNIT III: BJT AMPLIFIERS.model? Vignan Institute of Technology & Science II B.Tech 2nd Semester Page 145 . Draw the circuit of single stage RC coupled BJT amplifier. Compare emitter follower and Darlington emitter follower configurations in respect of . i) current gain ii) input impedance iii)voltage gain. Distinguish between the high frequency and the low frequency operation of BJT amplifiers and give their analysis techniques. 5. 6. . determine the values of open loop gain and feedback ration β. 11. 7. 9. Derive the expression for voltage gain for CS amplifier with resistive load. 10. 2. 8. 4. find the feedback ratio. Draw and explain the small signal model of MOS. Explain linear and non-linear systems. 5. 2. Draw and explain the common source stage of MOSFET amplifier. Draw the circuit diagram of voltage series feedback and derive expression for input resistance and output resistance. An amplifier has a mid band gain of 125 and bandwidth of 250KHZ.Draw and explain the folded cascade amplifier. 9. Draw the circuit diagram of current series feedback and derive expression for input resistance and output resistance. UNIT V: FEEDBACK AMPLIFIERS 1. Draw the circuit diagram of current shunt feedback and derive expression for input resistance and output resistance. What are the different types of feedback amplifiers? Give their equivalent circuits. 7. With the help of general block diagram explain the term feedback. UNIT IV: MOS AMPLIFIERS 1.Electronic circuit analysis Assignment Questions 6. Draw and explain the source follower circuit. Draw the small signal equivalent circuit for an emitter follower stage at high frequencies and explain the working of it. Draw and explain the CS stage with diode connected load. find the new bandwidth and gain. 3. An amplifier has voltage gain with feedback is 100. Draw the frequency response of an amplifier with and without feedback and show the bandwidth for each case and how curves are related to gain bandwidth product. Draw the circuit diagram of voltage shunt feedback and derive expression for input resistance and output resistance. 6. Vignan Institute of Technology & Science II B. If the gain without feedback changes by 20% and the gain with feedback should not vary by more than 2% .Tech 2nd Semester Page 146 . Draw and explain the CG amplifier. input and output impedance. Explain the cascode amplifier with current source load 10. State the advantages and disadvantages of source follower circuit. 8. Draw the practical circuit for current series feedback and find the voltage gain. II) if the bandwidth is to be restricted to 1MHZ. 5. 3. 4. I) if 4% negative feedback is introduced. State the transfer gain of each configuration and define feedback factor. Give the different analysis techniques to make the analysis of power amplifier. a. Explain the operation of Colpitts oscillator. operating frequencies and feedback used.Electronic circuit analysis Assignment Questions UNIT VI: OSCILLATORS 1. 2. Draw the circuit diagram of RC phase shift oscillator and explain its operation.Tech 2nd Semester Page 147 . What is thermal resistance? What is the unit of thermal resistance? Vignan Institute of Technology & Science II B. With the help of a neat circuit diagram. explain the operation of a push-pull configured class B power amplifier. 5. equivalent circuit of a crystal. Compare and contrast push-pull and complementary symmetry configurations for class B power amplifiers. 9. Discuss and explain the basic tank circuit of LC oscillator and derive the condition for the oscillatons. What do you mean by harmonic distortion? How this distortion can be minimized in power amplifier. 6. UNIT. Compare the various classes of operation of power amplifiers based on a) operating cycle b) position of Q point c) efficiency. explain the operation of a complementary Symmetry configured class B power amplifier. Give the expression for the d. 4. circuit components. power output and efficiency of a series fed. Explain the principal operation of a wien bridge oscillator? 6. 5. 10. Explain the operation of Hartley oscillator. What are the advantages of crystal oscillators? 11. 4. power input. directly coupled class A amplifiers. 8. State and explain the barkhausen criterion. Mention the difference between Voltage amplifiers and power amplifiers. 8. With the help of a neat circuit diagram. What are the advantages and disadvantages of positive and negative feedback amplifiers? 2. What is piezoelectric effect? Draw and explain a. What is frequency stability of Oscillator? What are the factor effecting the frequency stability.VII: LARGE SIGNAL AMPLIFIERS 1. State the formula for the frequency.c. 9. Explain the concepts of feedback as applied to electronic amplifier circuits. 7. Derive the formula for the frequency. 7.c. Classifies various oscillators based on output waveforms.c. 3. 3. Tech 2nd Semester Page 148 . What are the requirements of tuned amplifier? Classify tuned amplifiers. What do you mean by unloaded Q and loaded Q? 3. 8. show that conversion efficiency is 50%. 4. 13. class B and class C with respect to conduction angle. 10. Distinguish between the single tuned and double tuned amplifiers. ****THE END**** Vignan Institute of Technology & Science II B. What do you mean by tuned amplifier? 2. Explain the stabilization techniques used in tuned amplifiers. 6. How do you avoid the cross over distortion in power amplifier circuit? Discuss in detail. Sketch the output waveforms for class A. Distinguish between the power amplifiers and the tuned amplifiers. What is the effect of cascading single tuned amplifers on bandwidth? Derive expression for it. 11. In transformer coupled class A power amplifier. 5. What is the need for stagger tuning in amplifiers? Compare the frequency response characteristics of the single tuned and double tuned amplifier with stagger tuned amplifier. Write short notes on requirement and types of heat sinks for power dissipation in large signal amplifiers. Derive the equation for the 3dB bandwidth capacitance coupled single tuned amplifier. 7. 9. Draw a simple series fed class A amplifier circuit and derive the relationship for output power in terms of load resistance RL? 14. 11. 12. Derive an expression for tuning frequency of a single tuned amplifier in terms of quality factor and bandwidth of the amplifier. Discuss advantages and disadvantages of tuned amplifiers. 12.Electronic circuit analysis Assignment Questions 10.. Discuss in detail the cross over distortion. Draw the ideal and actual frequency response curves of a single tuned amplifier. UNIT-VIII: TUNED AMPLIFIERS 1. upender Asst. PRAKASAM Asst.Professor & Mr.P. V.professor COURSEFILE Department of ELECTRONICS AND COMMUNICATION ENGINEERING VIGNAN INSTITUTE OF TECHNOLOGY AND SCIENCE VIGNAN HILLS.Electromagnetic theory &transmission lines Mr. DESHMUKHI VILLAGE. POCHAMPALLY (MANDAL) NALGONDA (DISTRICT)-508284 Sponsored by Lavu Educational Society (Approved by AICTE and Affiliated to JNT University. Hyderabad) . COURSE OBJECTIVE . It will be clear subsequently. would need few MW of power in the absence of proper antennas. the time varying electric and magnetic fields always constitute a wave phenomenon called the electromagnetic wave. antenna research is still very active. The circuit approach then has to be re-investigated with inclusion of the space into the analysis. which can be established with few watts of power. the Ampere's law and the Faraday's low of electromagnetic induction.Electromagnetic Theory And Transmission Lines Course Objective COURSEOBJECTIVE At low frequencies. impedance matching play a vital role in high speed communication networks. and the physical size of the electrical components plays no role in the circuit analysis. As the frequency increases however. In the era of high speed computers. efficient. which can be derived from the physical laws like the Gauss Law. Even a change in the length of a simple connecting wire may alter the behavior of the circuit. or the circuit theory is rather a special case of the electromagnetic theory. which can launch and receive electromagnetic waves efficiently. This approach is then called the transmission line approach. design of compact. the static electromagnetic and the time varying electromagnetic. they find wide applications in high frequency circuit design. The electromagnetic theory is the generalization of the circuit theory. inductance etc. As the frequency increases. However. The voltage and currents exist in the form of waves. like the bit distortion. One can then conveniently divide the subject of electromagnetic in two parts. multi-frequency antennas have received a new impetus in the last decade. As the frequency increases the inadequacy of the circuit approach is felt and one is forced to follow the electromagnetic field approach. Although every phenomena of electricity and magnetism can be analyzed in the frame work of electromagnetic theory. Also at high frequencies. The communication. An antenna is a device.Tech 2nd Semester Page 151 . the space starts playing a role in the performance of the circuit. the transit time of the signals cannot be ignored. Vignan Institute of Technology & Science II B. which is the prime subject of discussion. signal reflection. that is to say that. an electrical circuit is completely characterized by the electrical parameters like resistance. But for the large antennas. the phenomena related to the electromagnetic waves. the communication between an earth station and a satellite is practically impossible. With recent advances in mobile communication. The phenomenon of electromagnetism in totality is governed by the four Maxwell's equations. at low frequencies the circuit approach is adequate. the size of the components becomes important. The primary objective of a transmission line is to carry electromagnetic energy efficiently from one location to other. where data rates are approaching to few Gb/sec. any discontinuity in the circuit path leads to electromagnetic radiation. Syllabus . II Convection and conduction currents. electric field intensity-fields due to the different charge distributions. illustrative problems Vignan Institute of Technology & Science II B. surface impedance. ampere’s circuital law and applications. illustrative problems. infinite line concepts. sinusoidal variations. polarization.propogation constant. poission’s and Laplace’s equations. gauss law and applications. relations between E and V. ampere’s force law. power loss in a plane conductor. coaxial. dielectric constant. inductances and magnetic energy.Tech 2nd Semester Page 153 . poynting vector and poynting theorem-applications. phase and group velocities. relaxation time. Brewster angle. wave propagation in good conductors and good dielectrics. UNIT-III: MAGENTO STATICS Biot-savart’s law.Electromagnetic Theory And Transmission Lines Syllabus SYLLABUS UNIT-I: ELECTROSTATICS – I Coulomb’s law. isotropic and homogeneous dielectrics. uniform plane waves-definition. illustrative problems UNIT-IV: MAXWELL’S EQUATIONS (TIME VARYING FIELDS) Faraday’s law and transformer emf. illustrative problems UNIT-VI: EM WAVE CHARACTERISTICS – II Reflection and refraction of plane waves-normal and oblique incidences. critical angle and total internal reflection. continuity equation. forces due to magnetic fields. Maxwell’s equations in different final forms and word statements. magnetic flux density. spherical capacitors. illustrative problems UNIT-VII: TRANSMISSION LINES – I Types. primary & secondary constants. transmission line equations. illustrative problems UNIT-II: ELECTROSTATICS. conductors and dielectrics-characterization. conditions at a boundary surface: dielectric-dielectric and dielectric-conductor interfaces. electric flux density. distortion-condition for distortion less ness and minimum attenuation. wave propagation in lossless and conducting media. Maxwell’s two equations for magneto static fields. electric potential. expressions for characteristic impedance. capacitance-parallel plate. all relations between E &H. energy density. losslessness/low loss characterization. loading – types of loading. for both prefect conductor and perfect dielectrics. magnetic scalar and vector potentials. Maxwell’s two equations for electrostatic fields. inconsistency of ampere’s law and displacement current density. parameters. illustrative problems UNIT-V: EM WAVE CHARACTERISTICS – I Wave equations for conducting and perfect dielectric media. and John A.7 ed. http://www. London Vignan Institute of Technology & Science II B.2006.UHF lines as circuit elements.New Delhi 2. 2001.. illustrative problems.B uck. springer(India) Pvt .nptel. http://www.1999.press 2.TMH 3.PHI 3.2005..C Jordon and K.oxford univ.Electromagnetic Theory And Transmission Lines Syllabus UNIT-VIII: TRANSMISSION LINES – II Input impedance relations.2008. IEE.Tech 2nd Semester Page 154 ..enzim.2000. TEXTBOOKS: 1. single and double stub matching.(Tech. Networks.hu/~szia/emanim/emanim.India Publications). http://www.emtalk. Transmission lines and networks –Umesh sinha. CSWR.iitm. IEE Electromagnet Waves Ser.com 3. Elements of electromagnetic-matthew N.Hayt Jr.htm JOURNALS 1. Electromagnetic waves and radiating systems-E.. Lines and fields –John D. Journal of Electromagnetic Waves and Applications (JEMWA) 2.in/courses 2. Engineering electromagnetic-Nathan ida.. Ltd. Engineering electromagnetic. SC and OC lines .O Sadiku.PHI WEBSITES 1. 2 ed.New Delhi REFERENCES: 1.2ed.reflection coefficient.ac.satya prakashan.William H.Ryder.G Balmain.2 ed.4th edition. significance of Zmin and Zmax smith chart-configuration and applications. STUDENT'S SEMINAR TOPICS . Electromagnetic Theory And Transmission Lines Seminar Topics STUDENTS SEMINAR TOPICS 1. Electric field intensity due to infinite line charge 2. Electric field intensity due to infinite surface charge. 3. Electric potential. 4. Boundary conditions for electro statistics. 5. Gauss’s law applications. 6. Different types of capacitors. 7. Maxwell equations. 8. Ampere’s circuital law applications. 9. Uniform plane waves. 10. Reflection and refraction of electromagnetic waves. 11. Different characteristics of electromagnetic waves. 12. Poynting vector theorem. 13. Lorentz gauge force equation 14. Equations of transmission lines 15. Single and double stub matching. 16. Short circuit and open circuit transmission lines. Vignan Institute of Technology & Science II B.Tech 2nd Semester Page 156 LECTURE PLAN Electromagnetic Theory And Transmission Line Lecture Plan LECTUREPLAN S.No NAMEOFTHETOPIC MethodofTeaching Textbooksreferred UNIT-I:ELECTROSTATICS-I 1. Introduction to vector algebra Black board and Chalk 2. Co-ordinate systems-Cartesian ,cylindrical and spherical Black boardand Chalk 3. Electric charge, electrostatic law,coulombs law Black boardand Chalk 4. Electric Field Intensity,fields due to infinite line charge Black board,and Chalk 5. Fields due to infinite surface charge,volume charge Black board and Chalk 6. Electric Flux Density, Gauss law Black board and Chalk 7. Gauss Law Applications-E due to Infinite Line, Surface Charge and Volume Charge Black board and Chalk 8. Electric potential, relation between E and V Black board and Chalk 9. Maxwell’s Two Equations for Electrostatic Fields Black board and Chalk 10. Energy Density Black board and Chalk 11. Boundary conditions Black board and Chalk 12. Problems Black board and Chalk Elements of Electromagnetics-Matthew N.O.Sadiku,4ed.,2008,Oxford Univ.Press Elements of Electromagnetics-Matthew N.O.Sadiku,4ed.,2008,Oxford Univ.Press Elements of Electromagnetics-Matthew N.O.Sadiku,4ed.,2008,Oxford Univ.Press Elements of Electromagnetics-Matthew N.O.Sadiku,4ed.,2008,Oxford Univ.Press Elements of Electromagnetics-Matthew N.O.Sadiku,4ed.,2008,Oxford Univ.Press Elements of Electromagnetics-Matthew N.O.Sadiku,4ed.,2008,Oxford Univ.Press Elements of Electromagnetics-Matthew N.O.Sadiku,4ed.,2008,Oxford Univ.Press Elements of Electromagnetics-Matthew N.O.Sadiku,4ed.,2008,Oxford Univ.Press Elements of Electromagnetics-Matthew N.O.Sadiku,4ed.,2008,Oxford Univ.Press Elements of Electromagnetics-Matthew N.O.Sadiku,4ed.,2008,Oxford Univ.Press Elements of Electromagnetics-Matthew N.O.Sadiku,4ed.,2008,Oxford Univ.Press Elements of Electromagnetics-Matthew N.O.Sadiku,4ed.,2008,Oxford Univ.Press UNIT-II:ELECTROSTATICS-II 13. Convection and conduction currents Vignan Institute of Technology & Science Black board and Chalk EngineeringElectromagneticsWilliamH.HaytJr.andJohna.Buck,7ed.,2006,YMH II B.Tech 2nd Semester Page 158 Electromagnetic Theory And Transmission Lines 14. Different types Dielectrics-Isotropic And Homogeneous, Dielectric Constant 15. Continuity Equation, Relaxation Time 16. Poisson’s and Laplace’s Equations, Capacitance 17. Different types of Capacitors- Parallel Plate Capacitor 18. Coaxial Capacitor 19. Spherical Capacitor 20. Boundary conditions 21. Related Problems 22. Related Problems 23. 24. 25. 26. 27. 28. 29. Lecture Plan Black board and Chalk Black board and Chalk Black board and Chalk Black board and Chalk Black board and Chalk Black board and Chalk Black board and Chalk Black board and Chalk Black board and Chalk EngineeringElectromagneticsWilliamH.HaytJr.andJohna.Buck,7ed.,2006,YMH EngineeringElectromagneticsWilliamH.HaytJr.andJohna.Buck,7ed.,2006,YMH EngineeringElectromagneticsWilliamH.HaytJr.andJohna.Buck,7ed.,2006,YMH EngineeringElectromagneticsWilliamH.HaytJr.andJohna.Buck,7ed.,2006,YMH EngineeringElectromagneticsWilliamH.HaytJr.andJohna.Buck,7ed.,2006,YMH EngineeringElectromagneticsWilliamH.HaytJr.andJohna.Buck,7ed.,2006,YMH EngineeringElectromagneticsWilliamH.HaytJr.andJohna.Buck,7ed.,2006,YMH EngineeringElectromagneticsWilliamH.HaytJr.andJohna.Buck,7ed.,2006,YMH EngineeringElectromagneticsWilliamH.HaytJr.andJohna.Buck,7ed.,2006,YMH UNIT-III: MAGENTO STATICS Black board and Chalk EngineeringElectromagneticsBio t-Sarvat’s Law ,Ampere’s Circuital Law WilliamH.HaytJr.andJohna.Buck,7ed.,2006,YMH Black board and Chalk EngineeringElectromagneticsAmpere’s Circuital Law Applications, Magnetic Flux Density WilliamH.HaytJr.andJohna.Buck,7ed.,2006,YMH Black board and Chalk EngineeringElectromagneticsMaxwell’s Two Equations for Magnetostatic Fields WilliamH.HaytJr.andJohna.Buck,7ed.,2006,YMH Black board and Chalk EngineeringElectromagneticsMagnetic Scalar And Vector Potentials WilliamH.HaytJr.andJohna.Buck,7ed.,2006,YMH Black board and Chalk EngineeringElectromagneticsForces due to magnetic Fields, Lorentz Gauge Equation WilliamH.HaytJr.andJohna.Buck,7ed.,2006,YMH Black board and Chalk EngineeringElectromagneticsAmpere’s Force Law WilliamH.HaytJr.andJohna.Buck,7ed.,2006,YMH Black board and Chalk EngineeringElectromagneticsInductances And Magnetic Energy WilliamH.HaytJr.andJohna.Buck,7ed.,2006,YMH Vignan Institute of Technology & Science II B.Tech 2nd Semester Page 159 Electromagnetic Theory And Transmission Lines 30. 31. 32. 33. 34. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. Lecture Plan Black board and Chalk EngineeringElectromagneticsWilliamH.HaytJr.andJohna.Buck,7ed.,2006,YMH UNIT-IV:MAXWELL’SEQUATIONS(TIMEVARYINGFIELDS) Black board and Chalk ElementsofElectromagneticsFaraday’s Law and Transformer Emf MatthewN.O.Sadiku,4ed.,2008,OxfordUniv.Press Inconsistency Of Ampere’s Law And Displacement Current Black board and Chalk ElementsofElectromagneticsDensity MatthewN.O.Sadiku,4ed.,2008,OxfordUniv.Press Maxwell’s Equations in different final forms and Word Black board and Chalk ElementsofElectromagneticsStatements. MatthewN.O.Sadiku,4ed.,2008,OxfordUniv.Press Boundary conditions-Dielectric-Dielectric and DielectricBlack board and Chalk ElementsofElectromagneticsConductor Interfaces MatthewN.O.Sadiku,4ed.,2008,OxfordUniv.Press ElementsofElectromagneticsproblems Black board and Chalk MatthewN.O.Sadiku,4ed.,2008,OxfordUniv.Press UNIT-V:EMWAVECHARACTERISTICS-I Black board and Chalk Electromagnetic Waves and Radiating SystemsWave Equations For Conducting And Perfect Dielectric Media E.C.Jordan and K.G.Balmain, 2ed.2000, PHI Black board and Chalk Electromagnetic Waves and Radiating SystemsDefinition of Uniform Plane Waves E.C.Jordan and K.G.Balmain, 2ed.2000, PHI Black board and Chalk Electromagnetic Waves and Radiating SystemsRelation between E&H, Sinusoidal Variations E.C.Jordan and K.G.Balmain, 2ed.2000, PHI Black board and Chalk Electromagnetic Waves and Radiating SystemsWave propagation in Lossless and Conducting Media E.C.Jordan and K.G.Balmain, 2ed.2000, PHI Wave propagation in Good Conductors and Good dielectric Black board and Chalk Electromagnetic Waves and Radiating SystemsMedia E.C.Jordan and K.G.Balmain, 2ed.2000, PHI Black board and Chalk Electromagnetic Waves and Radiating Systemspolarization E.C.Jordan and K.G.Balmain, 2ed.2000, PHI Black board and Chalk Electromagnetic Waves and Radiating SystemsRelated problems E.C.Jordan and K.G.Balmain, 2ed.2000, PHI UNIT-VI:EMWAVECHARACTERISTICS-II Black board and Chalk Electromagnetic Waves and Radiating SystemsReflection Of Plane Wave-Normal Incidence for perfect conductor E.C.Jordan and K.G.Balmain, 2ed.2000, PHI Black board and Chalk Electromagnetic Waves and Radiating SystemsReflection Of Plane Wave-Normal Incidence for perfect dielectric E.C.Jordan and K.G.Balmain, 2ed.2000, PHI problems Vignan Institute of Technology & Science II B.Tech 2nd Semester Page 160 57. NewDelhi.2000. Satya Introduction To Transmission Lines–Types. PHI Black board and Chalk Electromagnetic Waves and Radiating SystemsSurface Impedance. primary and secondary constants Prakasham.C.2000.2000. 49.2001.Jordan and K.G. 55. Lecture Plan Black board and Chalk Electromagnetic Waves and Radiating SystemsE.Jordan and K.C.Balmain. 47.C.G.Balmain.Electromagnetic Theory And Transmission Lines 45. PHI Black board and Chalk Electromagnetic Waves and Radiating SystemsRefraction Of Plane Wave-Oblique Incidence for perfect conductor E.Jordan and K. Critical Angle and Total Internal Reflection E.Jordan and K.C. 51. 2ed. 2ed.Jordan and K. PHI Black board and Chalk Electromagnetic Waves and Radiating SystemsRefraction Of Plane Wave-Normal Incidence for perfect conductor E. phase and group velocities Black board and Chalk Transmission Lines and Networks-Umesh Sinha. India Publications).G. PHI Black board and Chalk Electromagnetic Waves and Radiating SystemsRefraction Of Plane Wave-Normal Incidence for perfect dielectric E.C. PHI Black board and Chalk Electromagnetic Waves and Radiating SystemsPower loss in a plane conductor E. India Publications).Jordan and K. 2ed.Jordan and K.G.G. PHI Black board and Chalk Electromagnetic Waves and Radiating SystemsPoynting Theorem.Balmain. 2ed. 2ed.Balmain.C.2001.2000.C. (Tech.Balmain.Balmain. Satya Derivation of characteristic impedance Prakasham. pointing Vector E.G. 2ed.C. 56. PHI UNIT-VII: TRANSMISSION LINES – I Black board and Chalk Transmission Lines and Networks-Umesh Sinha. (Tech. 2ed. 46.C. PHI Black board and Chalk Electromagnetic Waves and Radiating SystemsReflectionOfPlaneWave--ObliqueIncidenceforperfectdielectric E. 2ed. PHI Refraction Of Plane Wave—Oblique Incidence for perfect Black board and Chalk Electromagnetic Waves and Radiating Systemsdielectric E.Jordan and K.G.Balmain.2001.Jordan and K.G.G.Balmain. Parameters Prakasham. India Publications). 52. Black board and Chalk Transmission Lines and Networks-Umesh Sinha.C. PHI Black board and Chalk Electromagnetic Waves and Radiating SystemsRelated problems E.2000.Applications E.Jordan and K.2000.G. PHI Black board and Chalk Electromagnetic Waves and Radiating SystemsBrewster Angle.Balmain. 2ed. 53.2000. 48.2000. 2ed. NewDelhi. 54.G. 2ed.2000.2000.2000. 59. Black board and Chalk Transmission Lines and Networks-Umesh Sinha.Jordan and K. NewDelhi.C. Satya Transmission line equations. Propagation constant.Balmain. (Tech. Satya Reflection Of Plane Wave-Oblique Incidence for perfect conductor Vignan Institute of Technology & Science II B.Balmain. 50.Tech 2nd Semester Page 161 . 58. Satya Infinite And Finite Transmission Lines Prakasham. India Publications). NewDelhi. India Publications). Input Impedance Relations Prakasham. (Tech. (Tech. 63. (Tech.2001. Satya Significance if Zmin and Zmax Prakasham.2001. Black board and Chalk Transmission Lines and Networks-Umesh Sinha. (Tech. Black board and Chalk Transmission Lines and Networks-Umesh Sinha. India Publications). 65.2001. NewDelhi. (Tech. Satya Types of loading Prakasham. India Publications).2001. 61. NewDelhi. 62. (Tech. Satya λ/2 line impedance transformations Prakasham. Black board and Chalk Transmission Lines and Networks-Umesh Sinha.2001. NewDelhi. Vignan Institute of Technology & Science II B. (Tech. Black board and Chalk Transmission Lines and Networks-Umesh Sinha. India Publications).2001. India Publications). Satya Reflection coefficient. Satya problems Prakasham.2001. 68. Satya λ/8 line impedance transformations Prakasham. Satya Short Circuit And Open Circuit Lines. NewDelhi. UNIT-VIII:TRANSMISSIONLINES-II Black board and Chalk Transmission Lines and Networks-Umesh Sinha. India Publications).Tech 2nd Semester Page 162 . NewDelhi. Black board and Chalk Transmission Lines and Networks-Umesh Sinha. 64. VSWR Prakasham. 67. NewDelhi.2001. Black board and Chalk Transmission Lines and Networks-Umesh Sinha. Satya Condition For Distortionlessness And Minimum Attenuation Prakasham. (Tech.Electromagnetic Theory And Transmission Lines 60.2001. 69. (Tech. 66. (Tech. India Publications). Black board and Chalk Transmission Lines and Networks-Umesh Sinha. India Publications). Lecture Plan Prakasham. NewDelhi. India Publications). NewDelhi. NewDelhi. India Publications). Black board and Chalk Transmission Lines and Networks-Umesh Sinha.2001.2001. (Tech. Satya λ/4 line impedance transformations Prakasham. NewDelhi. Black board and Chalk Transmission Lines and Networks-Umesh Sinha. II B. Problems 74.2001. India Publications). NewDelhi. Black board and Chalk Transmission Lines and Networks-Umesh Sinha. Configuration And Applications Of SMITH CHART 71. Satya Prakasham. NewDelhi. NewDelhi. Black board and Chalk Transmission Lines and Networks-Umesh Sinha. (Tech. Satya Prakasham.Electromagnetic Theory And Transmission Lines 70. (Tech. India Publications). India Publications).Tech 2nd Semester Page 163 . (Tech. Satya Prakasham. NewDelhi. (Tech. Black board and Chalk Transmission Lines and Networks-Umesh Sinha. Satya Prakasham. (Tech.2001. Revision 75. Double stub matching 73. Black board and Chalk Transmission Lines and Networks-Umesh Sinha. Revision 76. NewDelhi. India Publications). Single stub matching 72.2001. Satya Prakasham. Black board and Chalk Transmission Lines and Networks-Umesh Sinha. Satya Prakasham. India Publications). (Tech.2001.2001.2001. Satya Prakasham. India Publications).2001. Black board and Chalk Transmission Lines and Networks-Umesh Sinha. India Publications). Revision Vignan Institute of Technology & Science Lecture Plan Black board and Chalk Transmission Lines and Networks-Umesh Sinha. NewDelhi. (Tech. NewDelhi. LEARNING OBJECTIVES . 2. UNIT III: MAGNETOSTATICS At the conclusion of this unit student will 1. Explain columb’s law. 3. Define magnetic field. Vignan Institute of Technology & Science II B. 9. 7. Define relaxation time. 3. 6. 9. Explain the field theory.Tech 2nd Semester Page 165 . Define energy density. Describe boundary conditions for magnetic field. 6. 8. 4. Describe vector algebra and vector calculus. 7. 5. Solve the problems based on electrostatics. 10. Define gauss’s law. Deduce the relation between potential and electric field intensity. Explain magnetic flux. 5. 14. Explain about isotropic and homogenous media. UNITII: ELECTROSTATICS-II At the conclusion of this unit student will 1. Deduce poisson’s and Laplace equations.Electromagnetic Theory And Transmission Lines Learning Objective LEARNINGOBJECTIVES UNITI: ELECTROSTATICS-I At the conclusion of this unit student will 1. Explain Ampere’s Circuital Law. Derive continuity equation. 4. Explain the applications of gauss’s law. Derive the Maxwell’s equations for electro statics fields. 4. 15. 6. 7. 3. Define electric field. Explain electrostatic law. Derive an expression for the electric field intensity due to different charge distributions. Define dielectric constant. Explain the function of different types of capacitor. 13. 2. Derive magnetic field intensity due to different current elements. Differentiate conduction current and convection current 2. Classify the charges. 12. Define electric field intensity. Describe electric potential. Explain inductance. 5. Explain the magnetic energy. 8. Derive Maxwell’s equation for magnetostatics. State Biot-savart’s Law. 11. Explain reflection of Plane Waves at normal and oblique incidences for both perfect and perfect dielectrics. 5. State critical angle. Define displacement current density. Give the word statements of Maxwell’s Equations. 7. Define pointing vector 8. Explain Transformer emf. Derive the power loss in plane conductor. Explain refraction of Plane Waves at normal and oblique incidences for both perfect and perfect dielectrics. 6. Explain inconsistency of Ampere’s Law 4. Define transmission line. State pointing vector theorem. Define polarization. Differentiate different types of transmission lines. Define Uniform Plane Wave. Derive relation between E&H. Derive wave Equations for conducting and perfect dielectric media.Electromagnetic Theory And Transmission Lines Learning Objective UNIT IV: MAXWELL’S EQUATIONS (TIME VARYING FIELDS) At the conclusion of this unit student will 1. Explain wave propagation in lossless and conducting media. Explain wave propagation good conductors and good dielectrics. Define Brewster Angle 4. 7. Derive Maxwell’s Equations in different Final Forms 6. 6. 3. 2.Tech 2nd Semester Page 166 . Vignan Institute of Technology & Science II B. UNIT VI: EM Wave Characteristics-II At the conclusion of this unit student will 1. 9. 4. Define surface impedance. Explain total internal reflection. 2. UNIT-VII: TRANSMISSION LINES-I At the conclusion of this unit student will 1. Explain sinusoidal variations. 3. 2. 4. 7. Derive transmission line equation. 5. Define Faraday’s Law 2. State primary and secondary constants of transmission lines. 3. 3. 5. Analyze the conditions at aboundary surface UNIT V: EM WAVE CHARACTERISTICS-I At the conclusion of this unit student will 1. UNIT-VIII: TRANSMISSION LINES-II At the conclusion of this unit student will 1 Derive input impedance relations 2 Explain short circuit and open circuit lines. phase and group velocities. 8. 8 Explain applications of smith chart. 9 Explain single and double stub matching. 9. Derive the expression for characteristic impedance. Explain infinite line concepts. 3 Define reflection coeffieient. 6.Tech 2nd Semester Page 167 .λ/4. λ/8lines. 5 Derive impedance transformations. Derive condition for distortion less ness and minimum Attenuation. Vignan Institute of Technology & Science II B. propagation constant. 6 Explain significance of Zmin and Zmax 7 Describe smith chart. λ/2.Electromagnetic Theory And Transmission Lines Learning Objective 5. 7. Define distortion. VSWR 4 Explain UHF Lines As Circuit Elements. Explain loading. OBJECTIVE TYPE QUESTIONS . az2π€0ρs 8. The E-field at a point ‘R’ distance away from an infinite surface of charge density ρs along an unit vector normal to the sheet is given by (a) ρ s2€0az (b) ρs2π€0an [ (c) ρL. the net force on a point charge placed at the centre of the square is (a) Zero [ (b) 2E0 (c) 4E0 ] (d) 2√2E0 7.Four point charges of same magnitude Q are placed at four corners of a square .an2€0 [ ] (a)For symmetrical charge distributions.0) ` a) (5/9) x1 0-3ar ] c) Maxwell ] d) Potential [ ] d) Gauss law 6. Determine D at(4. Identify the in correct statement for two point charges Q1=1nC and Q2=2nC that are ‘R’ distance apart (a)IfapointchargeQ3=-3nC is placed equidistant from Q1 and Q2.D 9.0. The statement “Induced voltage acts to produce opposing flux” is given by a) Coulomb’ slaw b) Lenz’ slaw ] d) (5/12) x10-3ar 4.Edl c)  E. (d)Gauss’s law states that ρv=.dl b) (5/18) x10-3ar c) (5/36) x10-3ar [ ] [ b) Electric field intensity c) Electric flux density 5. Force of attraction or repulsion between two point charges is given by a) Gauss’s Law b) Ampere’s Law c) Coulomb’s Law [ d) Divergence Theorem 2. electrical flux due to any closed surface is equal to the charge enclosed by the surface. Identify in correct statement ] (d) ρs. Potential difference between any two points is also written as a) W/Q b) Va.0. the net force on Q3 is zero (b)As the distance ‘R’ increases the force on Q2 decreases [ ] (c) The force on Q1 is same as that of force on Q2 Vignan Institute of Technology & Science II B. Identify the scalar among the following a) Force [ d) Both a&c 3.Tech 2nd Semester Page 169 .If the two charges on the left side of the square are positive and on the right side are negative.3) if there is a point charge 5mC at(4.Electromagnetic Theory And Transmission Lines Objectives Questions OBJECTIVETYPEQUESTIONS UNIT-I: ELECTROSTATICS – I 1. coulomb’s law the most provides convenient analysis compared to Gauss’ slaw (b)Gauss’s law is an alternative statement of coulomb’s law (c)According to Gauss’s law. 2). Electro static field being conservative does not mean [ ] (a) The work done inside a closed path inside the field is zero (b) It is the gradient of a scalar potential (c) The potential difference between any two points is zero (d) Its circulation is identically zero 18. If a pointcharge. The instant after the switch is closed [ ] (a) the voltage across the resistor is equal to the emf of the battery Vignan Institute of Technology & Science II B.7mV ] (d) 14. 3). 0) and (1.-4µC is located at (2. 1) assuming zero potential at infinity is (a) 14. 0. the permittivity of sea water is (a) 7.D 17. coulomb’s law the most provides convenient analysis compared to Gauss’ slaw (b)Gauss’s law is an alternative statement of coulomb’s law (c) According to Gauss’s law.7kV (c)-14. Identify in correct statement ] [ ] [ ] (d)-20nC 15. A charge Q is uniformly distributed in a sphere of radius a1 the charge density. (0.-1. The total flux leaving a cube of side 6m centered at the origin is (a) 30nC (b) 10nC (c) 20nC (b) 80×10-10F/m (c) 80only 16. 0.854×10-12N 14.7mV [ (b)-14.Tech 2nd Semester Page 170 . Value of proportionality constant of Coulomb’ slaw is (a) 9×10-9F/m (b) 9×109m/F (c) 136p×109m/F (d) 8. Point charges 30nC. separated by 1m in free space is (a)136p×109N [ (b)9×10-9N (c)9×109N ] (d)8. 5.Electromagnetic Theory And Transmission Lines Objectives Questions (d) the force on both Q1 and Q2 is along the line joining them 10. Sea water has €r=80. 0. A capacitor and resistor are connected in a series with a batter and a switch.07×10-10F/m [ (d) 1/80 (a)For symmetrical charge distributions.7µv 13. Magnitude of Coulomb’s force between two point charges of 1Coulmb each.-1) respectively.854×1012F/m [ ] 11. electrical flux due to any closed surface is equal to the charge enclosed by the surface (d) Gauss’s law states that ρV=.-20nC and 10nC are located at (-1. if the same charge Q is made to occupy a sphere of Radius a2=a1/4 is (a) 16timesmore (b) 4timesmore (c) 64timesmore (d) 2timesmore [ ] 12. the potential at a point (1. b 6.b 16. A and B 20.d 5.b 14. (c) The greatest at point R.a UNIT-II: ELECTROSTATICS. Answers 1.c 3.b 4.c 18. The capacitance of a co-axial cylinder of inner and outer diameters ‘a’ and ‘b’ respectively and of length L is given by (a) 2π€Llnba [ (b) 4π€1na- Vignan Institute of Technology & Science (c) Q2π€Ln (b/a) ] (d) 2π€Llnb/a II B. The diagram shows the electric field lines of a negative point charge.d 8.a 10.b 9. Electro static field being conservative does not mean [ ] [ ] (a) Its circulation is identically zero (b) The work done in side a closed path inside the field is zero (c) The potential l difference between any two points is zero (d) i t is the gradient of a scalar potential 2.b 13.II 1. Four charges are arranged on the corners of a square as shown below: [ ] At which point (or points) is the electric field equal to zero? (a)B and E (b) D and A (c). A and C (d).a 19. (d) The same at the three points. c 12.Tech 2nd Semester Page 171 . The strength of the electric field is [ ] (a) The greatest at point P.b 15.b 7.c 17.Electromagnetic Theory And Transmission Lines Objectives Questions (b)the voltage across the capacitor is equal to the emf of the battery (c) the voltage across the resistor is equal to zero (d)the current is equal to zero 19. c 2. (b) The greatest at point Q.b 20. Relaxation time of a dielectric material is given by (a) € /ρ (b) σ/€ (c) ρ/€ (d) €/σ 3.b 11. charge density inside a perfect conductor is zero if E is _________.V (d) 12Q. The dielectric strength of a material is defined as [ ] [ ] [ ] [ ] (a) The maximum Electric field (b)The maximum energy (c)The permittivity of the dielectric material (d)The amount of energy a dielectric can store with in itself 6. Vignan Institute of Technology & Science [ ] [ ] (d) none of these 14. (a) >>1 (b) <<1 (c) 0 (d) none of these 8. Capacitor stores energy in _________ field. (a) low ] [ ] [ ] (d) none of these II B. (a) same inside (b) infinite inside [ (c) zero inside (d) none of these 10.V 5.V)/2 ] 2 (c) Q. (a) same inside (b) infinite inside (c) zero inside (d) none of these 9. As per Gauss' Law. (a) >>1 (b) <<1 (c) 0 (d) none of these 7. (a) length ] (d) olcohol 13.Electromagnetic Theory And Transmission Lines Objectives Questions 4.[ (a) positive (b) negative (c) unity (b) high (c) both a & b (b) oxygen (c) CO2 (b) contrary (c) same (b) area(c) volume 15. The direction of electric dipole moment is _________ applied electric field. (a) orthogonal [ (d) can not say 12.The amount of work done W in moving a point charge ‘Q’ to a point ‘P’ where the potential is ‘V’ is given by [ 2 (b) Q. Electrostatic field is _________ a perfect conductor.Tech 2nd Semester Page 172 . Potential is _________ a perfect conductor.V (a) (Q. Insulators have their conductivity "σ" _________. Conductivity of dielectric is _________. Which of the following is not a non-polar dielectric? (a) water ] (d) zero 11. Metals have their conductivity "σ" _________. Electric polarization of a material is electric dipole moment per unit _________. a 12. Units of magnetic field intensity are (a) Webers/meter (b) Amperes/meter (c) Amperes (d)Webers (c) Ampere/meter (d) Weber [ ] [ ] 2.b 15.c 19. A toroid is _________ solenoid.a 16. Lorentz force equation describes an expression for force (a) On a moving charge with a velocity v in a magnetic field (b) On a moving charge in electric and magnetic fields (c) On a stationary or moving electric charge in an electric field (d) On a current element Idl in a magnetic field 4. Vector Magnetic Potential has units of (a)Amperes (b) Weber/meter 3. (a)zero ] (c) unity [ ] (d) none of these Answers 1. d 2.c 14.Tech 2nd Semester Page 173 .c 6. the dissipation factor should be _________. For a medium to be a quasi-conductor.Electromagnetic Theory And Transmission Lines (a) electric (b) magnetic Objectives Questions (c) gravity (d) none of these 16.c 9.b 13. (a) a long ] (d) none of these 18.b 8.a 20.d 18.a 4.a 7. (a) infinity [ (d) none of these 19.b 17. (a) electric (b) magnetic [ (c) gravity (d) none of these 17.a 10. Which of the following is not an inductor? (a) toroid [ (b) transmission line (c) solenoid (b) infinity (c) constant (b) a small (c) not a (b) zero ] [ ] (d) none of these 20.b 3. Magnetic field at any point inside a long solenoid is _________.c UNIT-III: MAGENTO STATICS 1. Magnetic energy stored in an inductor (L) carrying current (I) and placed in a magnetic field of intensity H is given by [ Vignan Institute of Technology & Science ] II B.d 11. Inductor stores energy in ________ field.b 5. Identify a non-example of convection current (a) Current flowing in copper rod (b) electron beam in a TV tube (c) Current flowing in vacuum (d) current through inert gases 8. (a) current and area direction ] [ ] (d) can not say 14. (a) same (b) opposite (c) none of these (c) both a & b 15. __________ gradient of magnetic scalar potential gives magnetic field intensity.p4.0) 10.0) (d)H=-af at(5.3p2. The relationship between electric field and time varying potential (a)E=-V (b) E=V (c)E=-V/d [ ] [ ] [ ] [ ] (d)E=×V 6. Magnetic dipole moment is a product of __________.0) (c)H=-afA/ mat(5. amperes is aligned along z-axis. (a) electric. describing Ohm’s law cannot be applied to (a)Conduction currents (b) Isotropic media (c)Homogeneous media (d) Convection currents 7. Which of the following is true for electrostatics? (b) ∇ =2 0V (a) E V=−∇ (c) Both (a) and (b) (b) Negative (c) Double (b) Ampere’s circuit law [ ] [ ] (d) Integral 12. Lorentz force equation comprises __________ and __________ forces. Find the in correct statement (a)H=-axA/mat(0.6ayat(-3.Electromagnetic Theory And Transmission Lines (a)W=12HI2 (b) w=12LH2 Objectives Questions (c)W=12LI2 (d)W=12I2H2. Steady magnetic fields are governed by __________ law.0) (b)H=-0. An infinite current element of 10p. magnetic (b) mechanical.5. (a) Biot-Savart law ] (d) None of these 11.8ax-0. The capacitance of a capacitor filled with a dielectric material (a)Is only dependent on the charge on the plates but is independent of the potential difference between the plates (b) Is independent of the charge on the plates but is dependent on the potential difference between the plates (c)Is independent of both charge on the plates and the potential difference between them (d)Is dependent on the both charge on the plates and potential difference between them 9. (a) Positive [ [ (c) both a & b ] (d) none of these 13.4. There will be force of attraction between two current-carrying conductors if the currents are in __________ direction. chemical [ (b) area and its direction (d) none of these [ ] (c) current area and its (d) none of these Vignan Institute of Technology & Science II B.Tech 2nd Semester Page 174 . 5. J=σE. induced current acts to produce an opposing flux. (a) Lenz’s (b) Gauss’s [ (c) Bio-savart’s (b) outside ] (d) Faradays 20.c 10.d 19. If the magnetic field H=10axA/m. induced emf persists. (a) inside ] (c) both a & b [ ] (d) none of these Answers : 1.a 7.Magnetic field in a Toroid is (a)NI2πr (b) Nil (c) Iρ2πa2 [ ] [ ] [ ] (d) 12πρ 4.b 2.a 15. Ampere's Circuital Law is analogous to __________ Law in electrostatics. Inductance of coil (a)Induces a reverse voltage to oppose the flow of current due to an applied voltage (b)Increases the flow of current when a reverse voltage is applied across it (c)Is directly proportional to the current producing magnetic flux Vignan Institute of Technology & Science II B. According to __________ Law.d 9. (a) first (b) second (c) third (b) Lenz’s ] [ ] (d) fourth 17.c 8. (d)Force on a current carrying conductor is dependent on the magnetic field in which it is placed.c 5. (c)Force between two current carrying conductors is not given by Lorentz'sForceequation. the force is dependent on the magnetic field based on Biot-Savart'slaw.Electromagnetic Theory And Transmission Lines Objectives Questions 16. Identify the incorrect statement [ ] (a)Magnetic force between two current elements is equal to the field produced by BiotSavartslaw (b)Between two current elements.b 3.b 12.c 13. as long as changes happen in magnetic flux. According to Faraday's __________ Law. the flux density in free space is (a) 4πaxµWb/m2 (b) 1. [ (a) large (b) medium (c) small (d) very small 19.a 6. Biot–Savart's Law can be applied to __________ length current-carrying conductors.a 14.b 18.c 16. Ampere's Circuital Law can be applied __________ the conductor.b 4.6πaxµWb/m2 (c) 40πaxµWb/m2 (d) 10πaxµWb/m2 3.Tech 2nd Semester Page 175 .d 11. 2.c UNIT-IV: MAXWELL’S EQUATIONS (TIME VARYING FIELDS) 1. (a) Bio-savart’s [ (c) Amperes (d) Faradays 18.a 17.b 20. The unit of magnetic susceptibility is (a)Henry/meter [ (d)F=e 8. (b) μπ024∫ Jdvrs ] (d)36π×107H/m 11. Conduction current through a wire is __________ displacement current in capacitor. [ (a) Volume Dipole moment (b) Dipole moment Volume (c) Dipole moment × Volume (d) None of these ] 14. Magnetic field intensity due to infinitely long co-axial transmission line at a radial distance. (a) Lenz’s (b) Gauss’s (d) Faraday’s (c) Biot–Savart’s 15. a being the inner conductor’s radius. Normal component of B is continuous at (a) μπ04∫Jdvrs ] [ (c) μπ02∫ Jdvrs ] ] (d) μπ022∫ Jdvr 13.Electromagnetic Theory And Transmission Lines Objectives Questions (d)Is inversely proportional to the magnetic flux produced 5. The constant of proportionality of Biot-Savart law is (a)1/4π (b)1/4πF/m (c)9×109F/m (b) No units (c) Amperes (b)F=IL×B (c)F=ev×B [ ] [ ] (d) Weber 7. ρ for ρ≤a. Magnetic vector potential for volume current is expressed as __________. (a) Magnetic induction (b) Magnetic field strength (c) Both (a) and (b) (d) None of these 17. The magnetic field at a point ρ distance away in the normal direction to an infinite current element is given by [ (a)H=I4πρ (cosα2-cosα1) aφ (b) H=I4πρaφ (c)H=I2πρaφ (d) H=Idlsinφ4πρ2. Maxwell's equations shelter on __________ law(s). (a) Inside (b) Outside [ (c) Both (a) and (b) (d) None of these 16. Vignan Institute of Technology & Science II B. Lorentz force equation is given by (a)F=e(E+v×B) ] (d)1/4πA/m 6.Tech 2nd Semester Page 176 . Magnetization is given as __________. (a) Faraday’s (b) Gauss’s (c) Amperes’ ] [ ] [ ] (d) None of these 18. Ampere’s Circuital Law is analogous to __________ Law in electrostatics. Value of permeability of free space is (a)4π×10-7H/m [ (b)136π×107H/m (c)4π×107H/m [ (a)Any discontinuity (b) Dielectric-Dielectric interface only (c)Conductor-conductor interface only (d) Dielectric-Conductor interface only 12.aφ ] 9. is (a)Iρ2πa2aφ [ (b) 2πρaaφ (c) Ia2πρ2aφ (d) Iρ22πa2aφ 10. Magnetic flux density is the same as __________. Ampere’s Circuital Law can be applied __________ the conductor. At the dielectric conductor interface a) The H is double of the incident field. Due to inconsistency of Ampere’s circuital law. Following Maxwell’s equation having following physical significance “The total electric displacement through the surface enclosing a volume is equal to the total charge within the volume” a)xH=J+ 3.Tech 2nd Semester Page 177 . b) is reflected at 300. The E is double of the incident field c) The H is half of the incident field a) can not be reflected ] d) Gauss law 4.b 7.D=  v d).a 11. The magnitude of the E at the dielectric-conductor interface.a 19.Electromagnetic Theory And Transmission Lines (a) same as (b) different from Objectives Questions (c) twice of (d) None of these 19. c 2.a 3. (a) infinity (b) unity [ (c) zero ] (d) None of these 20. (a) line [ (b) surface (c) volume ] (d) None of these Answers : 1. emf=  D t b)xE=- B t c).a` 17.H=J+G [ ] d)none 2.B=0 d is given by dt a) Ampere’s circuital law b) Faraday’s law c) Coulomb’s law a) Zero b) Infinity.a 5. The E is half of the incident field 5.c 20. the law changed as a)xH=J+G b)xH=J-G c).b 10.b 12.a UNIT-V: EM WAVE CHARACTERISTICS – I 1. Wave number has units of____________.c 4.b 6. conduction current is __________. b) meter Vignan Institute of Technology & Science ] d).c 14. In empty space. c) is reflected at 900 7. polarization ______________.b 9.b 15. c) Twice to that of the incident field d) half to that of the incident field 6.d 18.a 8. emf is closed __________ integral of non-conservational electric field that is generated by battery. [ [ ] [ ] d) none of these [ c) radians/meter ] d) none of these II B.a 13. At the Brewster angle.b 16. a) radians [ b). For a good conductor ________________. a)Unequal. a) ≥100 [ c) ≤1 b) =10 ] d) none of these 19. opposite c)Equal. For a good dielectric medium ____________. Standing wave consists of two travelling waves of ____________ amplitudes and _____________ is direction.Tech 2nd Semester Page 178 .H ] [ ] [ ] d) E X H 17.Electromagnetic Theory And Transmission Lines Objectives Questions 8. +βx ] d) λ+f 9.λ b) λ/f c) λf b) σ ≠ 0 c) none of these a) e -βx ] [ ] +αx -αx b) e [ d) can not say 10. Phase velocity is given as _________. a) [σ/ωЄ] = 0 [ b) [σ/ωЄ]<<1 c) [σ/ωЄ]>>1 [ b) [σ/ωЄ]<<1 c) [σ/ωЄ]>>1 16. a) small ] d) [σ/ωЄ] = ∞ 14. same b)Unequal. a) 0 to 1 [ b) 1 to 10 d) 1 to ∞ c) 10 to 100 21. a) a dc component [ d) zero is obtained as b) E + H ] d) [σ/ωЄ] = ∞ 15. a) σ = 0 [ c) e d) e 11. Wave attenuation is given as ______________. a) increse b) decrese c) remains unchanged d) none of these 12. Power density has _________________. opposite 20. ____________. same d)Equal. SNR ranges from ______.In the case of a perfect dielectric medium.H= ] [ ]   II B. In good conductors. a)f. H b) large c) infinity c) E . For a lossy dielectric medium. a) [σ/ωЄ] = 0 ] b) a second harmonic component c) both a & b d) none of these 18. Poynting Vector a) E . Wave speed in terms of frequency f and wavelength λ is expressed as _________. Reflection coefficient Γ is __________. phase constant ______________ as conductivity increases. a) ωβ b) β/ω [ c) ω/β d) none of these 13.Electric and magnetic fields are related by the following equation a) E   H b) E   H  Vignan Institute of Technology & Science c) E  H   d)E. rate of attenuation is __________. electric field strength is…………………….at the surface of the conductor and at multiples of half wavelengths from the surface. J s Js c) ETan [ ] [ ] [ ] d)none 31.Electromagnetic Theory And Transmission Lines Objectives Questions 22.Surface impedance is defined by E tan a) J S [ II B.m) Vignan Institute of Technology & Science ] d) none 30.Electric field vector is parallel to the boundary surface of perpendicular to the plane of incidence is called a) Horizontal polarization. In a good conductor. 28.Propagation constant 2 in time varying fields= a) (  j )( j ) E b) (  j )( j ) c) (  j )( j ) d) (  j )( j ) 25. b) Vertical polarization c) Both a&b d) none.The angle of incidence is equal to the angle of reflection is known as……… a) Law of sine’s b) Snell’s law c) Botha&b b) Etan.In case of reflection by a perfect conductor. ] [ ] b) Vertical polarization c) Both a&b d) none.Power loss per unit area of a plane conductor is given by( in Watts/ Sq. [ a) Minimum b) Maximum c) Zero d) none 27.Perpendicular polarization is also known as…………… a)Horizontal polarization. 29.  0   23.For a uniform plane wave traveling in Z direction.Identify the region that satisfies the equation <<1  a)   1  b)  1  a) Conductor c) b) Dielectric d) [ ] `[ ] [ ]   1  c) BothA&B d) none 24.Then the wave is said to have [ ] a) Horizontal polarization b) Circular polarization c) Linear polarization d) Elliptical polarization 26.Tech 2nd Semester Page 179 . Ex and Ey having the same amplitude and differed by a quadrature phase difference . normal incidence. c 13.d 21. Surface current doesn't exist b. Complete transmission takes place b. Short circuit on the transmission line d.c 14.a 7. Both reflection and transmission takes place d.a 6.b 26. At the dielectric conductor interface the wave a.a 31.c 18.a 12.b UNIT-VI: EM WAVE CHARACTERISTICS – II 1.b 33. The H is half of the incident field d.b 4. Free charge exists on the surface 3.b 24. Complete reflection takes place c.c 8.c 9.c 16. No transmission and no reflection take place.c 22. For normal incidence of the wave on perfect conductor a. Surface current exist c.d 17. The transmission line terminated any load.b 27. The E is half of the incident field Vignan Institute of Technology & Science II B. The transmission line terminated with its characteristic impedance b.Electromagnetic Theory And Transmission Lines a)I2R Objectives Questions 2 c) J Seff Rs b)V2/R d)none 32.d 32.b 10. The ideal conducting boundary is analogous to [ ] [ ] [ ] [ ] a.c 19. The E is double of the incident field c.a 25.c 30. Conduction current exist d.c 3. 2. At the dielectric conductor interface a.a 5.b 29. 4. a)Stokes theorem b) Poynting theorem c) Brewster angle d) Snell’s law 33.d 23. In dielectrics the ratio a) Power factor  is also known as  [ ] [ ] b) Dissipation factor c) Phase shift constant d) Angular velocity Answers: 1. Open circuit on the transmission line C.One of the following gives the measure of the rate of energy flow per unit area at any point.a 28. c 2. The H is double of the incident field b.d 11.Tech 2nd Semester Page 180 .b 15.d 20. The tangential components of Discontinuous across the boundary. Ampere/m2 d. Unity [ c. Low c. The tangential components of E are continuous across the boundary. The E is perpendicular to the plane of incidence and parallel to the reflecting surface c. The H is perpendicular to the plane of incidence and parallel to the reflecting surface b. b. A standing wave a.Electromagnetic Theory And Transmission Lines Objectives Questions 5.Tech 2nd Semester Page 181 . The E is parallel to the plane of incidence and perpendicular to the reflecting surface 12. V/A 15. Two 7. The unit for surface current a. The absorption of power in propagation through the dielectric is a. Unity d. The conductivity of an ideal conductor is a. Infinity c. Infinity b. The H is parallel to the plane of incidence and perpendicular to the reflecting surface d. The normal components of E are continuous across the boundary. Zero b. In between0and1 8. Zero d. Progresses with light velocity d. High b. Unity b. Angle of reflection b. Infinity [ ] [ ] [ ] [ ] [ ] d. Twice to that of the incident field d . The another name of Brewster angle is a. The normal components of H is continuous across the boundary 13.Half to that of the incident field 6. In the case of perpendicular polarization a. Equal to surface current 9. Zero c. Zero c. As per the boundary condition [ ] [ ] [ ] [ ] a. Does not progress 10. The magnitude of the E at the dielectric-conductor interface [ a. The dimension of a reflection coefficient is a. Infinity 14. No unit d. ampere/m3 11. Progresses with more than light velocity c. Zero b. polarizing angle Vignan Institute of Technology & Science II B. V/m c. For normal incidence of a wave on dielectric-conductor interface the magnitude of reflection coefficient is a. A/m b. Infinity ] ] d. Ampere b. c. The electric field with in a conductor is a. Progresses with less than light velocity b. d. Ampere/m c. Under total internal reflection the reflection coefficient for both polarizations is a.c 16.c 10.c 6. Infinite at the interface 20. An imaginary quantity c. Complete reflection takes place c. For total internal reflection the fields in the second medium a. Hysteresis and eddy current losses in loading coils lead to Vignan Institute of Technology & Science ] (d)Z0=Sqrt(C/L) [ ] II B. May be real or imaginary quantity 19.Tech 2nd Semester Page 182 . When incident angle is Brewster angle then a.b 3. If the wave travels from Denser to Denser medium d.b 4.a 17.a 15. A real quantity b. A complex quantity d. Magnitude change d.b 12. If the wave travels from Denser to Rarer medium c.Partial reflection only takes place b.b UNIT-VII: TRANSMISSION LINES – I 1. In a transmission line the voltage and current standing waves are (a) 00out of phase along the line (b) 2700out of phase along the line (c) 900out of phase along the line (d) 1800 out of phase along the line 3. Polarization change c.a 14.a 8. A phase change b.b 13.b 2. No change in the phase 17. The Total internal reflection can take place [ ] [ ] [ ] [ ] a.b 9.c 11. Partial transmission only takes place Answers: 1. The transmission line terminated with any load. Vanish completely b. Non polarizing angle 16. If the wave travels from Rarer to Rarer medium 18. The transmission line terminated with its characteristic impedance (b). No change with angle of incidence d. Short circuit on the transmission line (d). The ideal conducting boundary is analogous to [ ] [ ] (a). If the wave travels from Rarer to Denser medium b. 2. For a lossless line the characteristic impedance is (a)Z0= Sqrt (LC) (b) R0=Sqrt(1/LC) [ (c)R0=Sqrt(L/C) 4. No reflection takes place d.b 18. During total internal reflection wave under goes a.c 5. Angle of transmission Objectives Questions d. Open circuit on the transmission line parallel to the reflecting surface ©.Electromagnetic Theory And Transmission Lines c.d 19. Do not vanish c.b 7.b 20. Tech 2nd Semester Page 183 . Source impedance ] 14.R=G=0. Amp. 11.Equal to transmission coefficient ] 15. Which of the following is a one to one transformer? (a) λ line (b) λ/2line (c) λ/8line (d) λ/4line 8. The unit for attenuation constant is a. Load impedance b. Unity (b). Zero (c). Zero d. Infinity c. When a line is called as a flat line then standing wave ratio is (a). The SWR of a transmission line which is terminated with its characteristic impedances given by (a)infinity (b)zero (c)1 (d)2 [ ] [ ] 7. For a low loss line the phase velocity is a. Infinity [ ] (d). A transmission line operating at 1GHz has L=1micro henry/m. Characteristic impedance c. Decreases with frequency II B. dB/m b. Radian/m c. The ratio of positively traveling voltage wave to positively traveling current wave at any point on the transmission line is known as [ a. Increases with frequency Vignan Institute of Technology & Science b./m 13. Two 12.Electromagnetic Theory And Transmission Lines (a)Decrease in R (b) Decrease in L Objectives Questions (c) Increase in R (d) Increase in L 5.1mhos ] (d)0.01mhos 6.001mhos (c)0. Line impedance d. The velocity factor of a transmission line [ ] (a) is always greater than unity (b) Depend upon the permittivity of the surrounding medium (c) Is lease for air medium? (d) Is governed by skin effect 10.Then its characteristic admittance is (a)10mhos [ (b)0. In case the characteristic impedance of the line is equal to the load impedance [ ] (a) All the energy will pass to the earth (b) All the energy will be lost in transmission losses (c) The system will resonate badly (d) All the energy sent will be absorbed by the load. in a transmission line when termination impedance is equal to characteristic impedance of that line then The reflection coefficient is [ a. The VSWR in a short circuited loss less transmission line equals (a) Infinity (b) unity (c) zero [ ] (d) none of above 9. Volt/m d. C=1pF/m. Unity b. Inductive reactance c. Pure resistance d.b 10. In the single stub matching the location of the stub changes with a. Impedance 9. Capacitive reactance b. the SWR is (a) 4 (b) 2 (c)1/2 5. Source impedance c.b 9.C=LR/G (c).b 6.Tech 2nd Semester Page 184 .b 7. For minimum attenuation (a). Increases with square of frequency Answers: 1. [ (b). ±∞) 3.c UNIT-VIII: TRANSMISSION LINES – II 1. By connecting the stub at the load point ] ] (d). Matching cannot be obtained b.a 13. Load impedance b. Matching can be obtained c.a 4.b 5.b 11. 0) (d)(1. ∞) (b)(1.C=R/LG [ ] [ ] [ ] a.c 3. Matching can be obtained for a particular frequency d.a 12. Frequency 8.b 14.ForZL=200ohms. Matching cannot be obtained for a particular frequency Vignan Institute of Technology & Science II B. A stub with a short circuited load offers a. Approximately constant Objectives Questions d.c 15.Electromagnetic Theory And Transmission Lines c. On a smith chart for x=0circles the center is at (a)(0.c 8.C=LG/R [ ] [ ] [ ] (d)1/3 (d) ZR =Z0 = 0. Characteristic impedance d. A certain low loss line has Z0=400ohms. 1) [ (c)(1.c 2. In the single stub matching the location of the stub changes with (a)Frequency (b) Source impedance (c)Characteristic impedance (d) Load impedance 4.C=G/LR 7. Quarter wave transformer is (a)Frequency sensitive device (b) Current sensitive device (c)Voltage sensitive device (d) Power sensitive device 2. For a properly terminated line (a) ZR=ZO (b) Z/R > ZO (c) ZR < ZO 6. 4 13. Two very long loss less cables of Characteristic impedances of 36ohms and 100ohms respectively are to be joined for Reflection less transmission. 11.d II B. Narrow band system ] [ ] b. a.a 8.It has complete loss of energy due to radiation d. It has lower loss of energy due to radiation b.75ohms [ ] d. A single stub matching is a a.50ohms c. Band reject system 12.b Vignan Institute of Technology & Science 7. Pass band system d.a 11.a 6. It has higher loss of energy due to radiation C. [ b.1/3 c.b 3.c 13. Broad band system c.c 5. the SWR is a.100ohms Answers: 1.25ohms b. Its length is small. A certain low loss line has=400ohms.2 d.Tech 2nd Semester Page 185 .a 12.Electromagnetic Theory And Transmission Lines Objectives Questions 10.1. A short circuited stub is ordinarily preferred to an open circuited stub because a.For=200 ohms.a 10.b 9.c 4.b 2. ESSAY TYPE QUESTIONS . 4. 3. Define polarization. 4. Line charge ρl iii. Obtain expression for the capacitance of i. What is the inductance of a solenoid and write the expression for its inductance And also for magnetic field in a solenoid.Tech 2nd Semester Page 187 . Vignan Institute of Technology & Science II B.V/m also find ρV. Define magnetic flux density in two different forms.II 1.a coaxial capacitor.0 mm has a voltage 50 sin103 t volts applied to its plate. Define potential at a point and obtain its expression.Electromagnetic Theory And Transmission Lines Essay Questions ESSAYTYPEQUESTIONS UNITI:EECTROSTATICS-I 1. 2. 5. 2. what is the work required to be done. What is a lossy and lossless medium? 7. If a charge. 3. Find out electric flux density in free space if the electric field. State and explain Boundary conditions for electric field at a boundary surface Between a conductor and dielectric boundary. Electric susceptibility of the dielectric material is 4. What are the properties of dielectric materials? 2. E=6ax-2ay+3az. State equation of continuity and prove it. Determine the Electric Field "`E' due to i. 5.1m Find its inductance. 6. a parallel plate capacitor and ii. What is an isotropic and homogeneous medium? 6. 8. Explain about equipotential surfaces. Point charge Q ii. 7. P 3. UNIT II: EECTROSTATICS. 8. Explain the term Conduction Current Density". 9. A parallel plate capacitor with plate area of 5. A solenoid has 400turns with a length of 2m. The potential at a point A is 10volts and at B is 15 volts. What are the magnitudes of electric flux densities and polarization for a dielectric material in which E=150kV/m. It has a circular cross-section Of 0.75. Define the poisson's "and Laplace's" equation. Calculate the Displacement current assuming "εr=2" UNIT III: MAGNETOSTATICS 1. Prove J=ρV from fundamentals.0cm2 and plate separation of 3. Q=10μ C is moved from A to B. Evaluate the Coulomb's force. Electric Field intensity and potential due to a Line charge ` l' 10. ρ 9. What are the different types of current densities and define them. Surface charge" ρs at a point distance r' from the source. Tech 2nd Semester Page 188 . upto what depth can the wave penetrate the material. Describe the characteristics of paramagnetic materials.Find (a)E and H at the plate surface (b)Depth of penetration (c)The surface impedance. If magnetic field. A uniform plane wave in empty space has the electric field E(z)=ax100e Vignan Institute of Technology & Science -jβ0z V/m. B=10yaxmwb/m2. and what will be the wavelength of the wave in the material. A plane wave with E=2. State and explain Maxwell's equations obtained from Faraday's and Ampere's laws and their Magnetic field concepts & relationship.Electromagnetic Theory And Transmission Lines ESSAY Questions 4. Determine μr. The length of line is 10m. In region1 (z<0) and region2 (z>0). If E=2cos(ωt−βz)ax and H=2πcos(ωt−βz)ay. It is moving in free space impinging on a thick copper sheet located perpendicularly to the direction of propagation. A plane wave with E=2. Write Maxwells equations for Time Varying fields in integral and difierential form. 2o so that the fields satisfy all Maxwell’s equation.0 sin(ωt-10z)ay+cos(ωt-10z)azmA/m2. M and H. find η in terms of μo. 3. find volume charge density. Verify whether the fields E=10sin×sintay and H=10μ cos×costaz satisfy the Maxwell’s equations. II B.E1=1 ax+2ay+3az. UNIT IV: MAXWELL’S EQUATIONS (TIME VARYING FIELDS) 1. What is the frequency above which the materials cannot behave as a good conductor? If a plane wave of 15MHz is incident on the material. 2. State and prove Boundary Conditions for electric field between a conductor and a dielectric.€r1=1 and €r2=2. 7. σ1=σ2=0. Jb. 7. 4. Discuss the difierence between static fields and Time Varying fields. what is Magnetic flux density at the point. if the diameter of the each wire is 0. 3. 8. 2. J. UNITV: EM WAVE CHARACTERISTICS-I 1. μ. conduction current density given by J=3. 5. Differentiate conduction and displacement current densities. Derive the expression for surface impedance of a good conductor.0V/m and has a frequency of 3 State boundary conditions in scalar form. and E2 and D2. What is the inductance of a pair of transmission lines separated by1. 6.01m and the medium between the lines has μ=2μ.Anisotropic material has a magnetic susceptibility of 3 and the magnetic flux Density. 5. H=3ax+2ay.868m.0V/m and has a frequency of 300MHz. In a medium. 9.A/m exists at a point in free space. 4. 6. Find average power density absorbed by copper.B. Define complex Poynting vector and explain. 7. What is a standing wave? Define standing wave ratio? What is its relationship with the reflection coefficient? 5. UNIT. 4. and phase constant. The copper has μr=1. H in real-time form UNIT VI : EM WAVE CHARACTERISTICS-II 1. 2. Prove that a finite line terminated in its characteristic impedance behaves as An infinite line? Vignan Institute of Technology & Science II B.H (c)Express E. List out the applications of transmission lines.VII: TRANSMISSION LINES-I 1.2 r=1 and σ=5. For a plane wave reflecting at perfect dielectric. 2. β. with normal incident 6. From the fundamental voltage & current equations of transmission line. Define Brewster's angle and obtain an expression for the same in terms of Medium parameters. derive expression for input impedance Zin of the line. Explain about the parameters of the open wire line at high frequencies? 3. 9. What is the difference between lumped parameters and distributed parameters? Discuss in detail. What is skin effect? What is skin Depth? What is its relation with attenuation constant. 5. 8.Electromagnetic Theory And Transmission Lines ESSAY Questions Its frequency is 20MHz: (a)What is its direction of travel and amplitude? (b)Find B. Modify the expression for lossy & lossless cases.The wave has an electric field amplitude of E=2mV/m. 4.Tech 2nd Semester Page 189 . Explain the reflection of uniform plane waves with normal incidence at a plane dielectric boundary. List out propagation characteristics of EM waves in free space.8×107mho/m. Derive the Reflection coefficient for a parallel polarized wave at an angle of incidence between two media (losslessandµ1=µ2=µ0) 10. conductivity and frequency? Derive the expression for skin depth. Define intrinsic impedance of free space. A plane wave of frequency=2MHz is incident upon a copper conductor normally. 3. Write short note on: (a) Lossless transmission line (b)Distortion less line. 5. Derive Zin for a lossless transmission line when it is terminated by a: (a)ZL (b)open (c)short circuit.VIII: TRANSMISSION LINES-II 1. Find the characteristic impedance of a line a 1600Hz if the following measurements have been made on the line at1600Hz. In a transmission line. ZOC=750 and ZSC=500. 7. the attenuation constant and phase constant of a transmission line if the following measurements have been made on the line ZOC=550 and ZSC=660 2. A transmission line of length 0. Draw the suitable sketches.Electromagnetic Theory And Transmission Lines ESSAY Questions UNIT. Calculate the characteristic impedance. Find the: (a)Voltage reflection coefficient(b)VSWR (c)Input impedance of the line by using smith chart. 3. 4. 9. 10.Tech 2nd Semester Page 190 .name the types of distortions that occur and explain. To avoid distortion. Derive the condition form in attenuation with (a)L variable and (b)C variable. Explain the designing of Double Stub? 6. what is the condition for a Distortion less line" and derive An expression for the same in terms of line parameters. Explain the constructional features of Smith's chart and its importance. 8. Vignan Institute of Technology & Science II B.40λ has a characteristic impedance of 100 and is terminated is a load impedance of 200+j180. ASSIGNMENT QUESTIONS . 3. Determine μr. 5. Define magnetic flux density in two different forms. A parallel plate capacitor and ii. An isotropic material has a magnetic susceptibility of 3 and the magnetic flux Density. State and explain Gauss's law and prove that v 2. 3.Tech 2nd Semester Page 192 . What is the inductance of a pair of transmission lines separated by1.\ Line charge" and\ Surface charge" distributions and the`E'&V' expressions also to the above. The length of line is 10m. what is Magnetic flux density at the point. 2. 6. 4.868m. J. What is an isotropic and homogeneous medium? 4.II 1. Define the poisson's "and Laplace's" equation. If the diameter of the each wire is 0. A coaxial capacitor. Jb.01m and the medium between the lines Has μ=2μm. 2. if the Filament extends from Vignan Institute of Technology & Science II B.2. Homogeneous and isotropic media? Explain\Point charge".3) in Cartesian coordinates Caused by a current filament carrying a current of 10Amp along Z-axis. H=3ax+2ay. Find the `E' field intensity on the axis of a circular ring carrying a charge density `Q'C/m. What is a lossy and loss less medium? 5.Electromagnetic Theory And Transmission Lines Assignment Questions ASSIGNMENTQUESTIONS UNITI:EECTROSTATICS-I 1.A/m exists at a point in frees pace. What are Linear. Describe the characteristics of paramagnetic materials. μ. B=10yax mwb/m2. Define Electric field Intensity" and` potential V' due to\ point charges" and line charges" & explain. Explain the term Conduction Current Density UNITIII:MAGNETOSTATICS 1. 4. given examples of their applications UNIT II: EECTROSTATICS. Obtain expression for the capacitance of i. Find the electromagnetic field intensity atP(1. 3. M and H. If magnetic field. 2.8*107mho/m and J=sin(377t-117z)axmA/m2. Jd adjacent to TV receiver when the magnetic field of FM signal is H=2:0cos [3.0V/m and has a frequency of 300MHz.Electromagnetic Theory And Transmission Lines Assignment Questions UNIT IV: MAXWELL’S EQUATIONS (TIME VARYING FIELDS) 1.2 o so that the fields satisfy all Maxwell’s equation. A plane wave with E=2. Derive the expression for surface impedance of a good conductor.E1=1ax+2ay+3az. In a medium.σ=5. What is surface impedance and explain the power loss between Air & a conductor surface at normal Incidence. Find (a)E and H at the plate surface (b)Depth of penetration (c)The surface impedance UNIT VI: EM WAVE CHARACTERISTICS-II 1. σ1=σ2=0. 5. If E=2cos(ωt−βz)ax and H=2πcos(ωt−βz)ay.Tech 2nd Semester Page 193 . Differentiate conduction and displacement current densities. Find Jd in a metallic conductor at 50Hz if εr=1.0V/m and has a frequency of 3 State boundary conditions in scalar form. find η in terms of μo. 3. 2. Define Depth of propagation" Vignan Institute of Technology & Science II B. find volume charge density. 2. Evaluate the reflection coefficient.12(3*108t-y)]ax A/m.µr=1. It is moving in free space impinging on a thick copper sheet located perpendicularly to the direction of propagation.0sin(ωt-10z)ay+cos(ωt10z)azmA/m2. 3. 3. A plane wave with E=2. In region1 (z<0) and region2 (z>0). 6. UNIT V:EM WAVE CHARACTERISTICS-I 1. Find amplitude of the displacement current density. 4. and what will be the wavelength of the wave in the material. and E2 and D2. upto what depth can the wave penetrate the material. €r1=1 and €r2=2. What is the frequency above which the materials cannot behave as a good conductor? If a plane wave of 15MHz is incident on the material. A wave is incident from A iron to a perfect conductor normally. conduction current density given by J=3. 6. Explain in detail. Modify the expression for lossy & lossless cases. 2. Brewster's angle ii. Compare the impedance matching techniques such as i. Double Stub on transmission lines ****THE END*** Vignan Institute of Technology & Science II B. derive expression for input impedance Zin of the line. 3. Find the length and position of the stub. Single Stub iii. λ/4 ii. List out the applications of transmission lines. 4. From the fundamental voltage & current equations of transmission line. A load Impedance of 90-j25 is to be matched to a 50 line using single stub matching. 5.Electromagnetic Theory And Transmission Lines Assignment Questions 4.VIII: TRANSMISSION LINES-II 1. Obtain an expression for the Reflection and Transmission coefficients of uniform waves between two media for normal incidence. Explain Reflection and Refraction "of plane waves.VII: TRANSMISSION LINES-I 1. 2. What is the difference between lumped parameters and distributed parameters? Discuss in detail.Tech 2nd Semester Page 194 . UNIT. Explain about the parameters of the open wire line at high frequencies? UNIT.Critical angle. What are the conditions to be satisfied for i. Bhanu ganesh LUKKA Asst.508284 Sponsored by Lavu Educational Society (Approved by AICTE and Affiliated to JNT University. Hyderabad) . Professor COURSEFILE Department of ELECTRONICS AND COMMUNICATION ENGINEERING VIGNAN INSTITUTE OF TECHNOLOGY AND SCIENCE VIGNAN HILLS. DESHMUKHI VILLAGE. POCHAMPALLY (MANDAL) NALGONDA (DISTRICT) .PRINCIPLES OF ELECTRICAL ENGINEERING Mr. COURSE OBJECTIVE . and to be able to use this knowledge to analyze and design basic electrical application circuits. To understand the principles of operation. besides covering induction motors toward the end.RLC under transient conditions. working and analysis of these devices have been mentioned. the course helps in developing the understanding about filter networks.response of series RL. Apart from dc machines. attenuators. Vignan Institute of Technology & Science II Year B. two port network networks. ac machines like transformers and single phase induction motors have also been introduced whose principle of operation is must to be studied by every engineer as we come across or use these devices somehow in our routine life. An introduction to dc machines consisting of both generators and motors which help to the construction. transformers and dc machines in main . To extend the understanding of how electrical circuits and their functions fit into larger electrical systems in real time environment. 2nd semester Page 197 . attenuators and construction and operation of machines in detail and precise.RC.Tech. electrical characteristics and circuit models of the most important electrical devices. filters. Starting by explaining the fundamentals of transients like initial conditions.PRINCIPLES OF ELECTRICAL ENGINEERING Course Objective COURSE OBJECTIVE The course provides a comprehensive understanding of the basic theory of networks like Two port parameters. A review of machines is introduced in this course.transients. Syllabus . initial conditions. δ-type. interconnection of two port networks in series. UNIT-II: TWO PORT NETWORKS Impedance parameters. UNIT–VII :TRANSFORMERS: Principle of operation of single phase transformer – types – Constructional features – Phasor diagram on No Load and Load – Equivalent circuit. MOTORS: DC Motors – Types of DC Motors – Characteristics of DC motors – 3-point starters for DC shunt motor – Losses and efficiency – Swinburne’s test – Speed control of DC shunt motor – Flux and Armature voltage control methods. Transmission parameters. lattice attenuator UNIT – V :DC MACHINES: Principle of operation of DC Machines. constant k-low pass filter. characteristic impedance in pass band and stop bands. parallel and cascade configuration.Tech. high pass filter . Classification of filters. image parameters. illustrative problems. solution using differential equations approach and Laplace transform method. bridged T type attenuator. Hybrid parameters.C.T-Type . band pass filter and band elimination filter. classification of pass band and stop band.RC series RLC circuits for DC excitation.PRINCIPLES OF ELECTRICAL ENGINEERING Syllabus SYLLABUS UNIT-I: Transient Analysis( first and second order circuits) Transient response of RL. conditions for reciprocity and symmetry. conversion of one parameter to other.EMF equation – Types of generators –Magnetization and load characteristics of DC generators UNIT–VI :D. illustrative problems UNIT III : FILTERS. Losses and Efficiency of transformer and Regulation – OC and SC tests – Predetermination of efficiency and regulation Vignan Institute of Technology & Science II Year B. m-derived Tsection. Admittance parameters. 2nd Semester Page 199 . UNIT-IV: SYMMETRICAL ATTENUATORS: Symmetrical attenuators. filter networks . Synchros.E Kemmerly and S.C. 4.Dhanpat rai &Co. AC servomotor. Lines and Fields – Jhon. Stepper Motors – Characteristics TEXT BOOKS: 1.M. 8 ed… PE. 3. 2008. Network Analysis and Synthesis – C L Wadhwa. Engineering Circuit Analysis – W. 2. Network Analysis by N.PRINCIPLES OF ELECTRICAL ENGINEERING Syllabus UNIT–VIII:SINGLE PHASE INDUCTION MOTORS: Principle of operation . e ed… 2007. Lakshminarayana. Chakrabarthy.Shaded pole motors – Capacitor motors. Circuit Theory by A. 6 ed. Introduction to Electrical Engineering by Naidu and Kamakshaiah..ed…208 (Reprint). New Age International publishers.Tata McGraw Hill publications 3. Principles of Electrical Engineering by Sudhakar and Shyammohan Pillai. REFERENCE BOOKS: 1.(P) Ltd. Riedel.Hayt ad J. C. TMH.D.Ryder. Electric Circuits – Nilsson. PHI. 4. AC tachometers. 2. Networks.. BS Publications 2. Vignan Institute of Technology & Science . Durbin.Jagan.H. STUDENT'S SEMINAR TOPICS . 8.PRINCIPLES OF ELECTRICAL ENGINEERING Seminar Topics STUDENTS SEMINAR TOPICS 1. 2. Working principle of a dc motor. Vignan Institute of Technology & Science II Year B. 6. Phasor diagram of a Transformer under on-load. 12. Equivalent circuit of a Transformer. Design of a bridged T-attenuator. Construction of a stepper motor with characteristics. 9. Analysis of a series RC circuit during transient condition . Analysis of equivalent circuit of a single phase transformer.Tech. 2nd Semester Page 202 . Design of a two port network when any two two-port networks are in cascade. 5. Construction of a DC machine. Construction of a single phase transformer. 13. Design of a Band pass filter 4. 3. 11. Characteristics of dc generators. Characteristics of dc motors. 10. 7. LECTURE PLAN . Circuit Theory by A. Problems on transient response of RC circuit. Problems on h .chapter 12 1 Black board and Chalk Circuit Theory by A. 1 Black board and Chalk UNIT 2: TWO PORT NETWORKS Difference between a one port. 16. chalk. chalk. 4.Chakraborthy. h.chapter 12 1 1 Black board and Chalk Black board and Chalk Circuit Theory by A. h.Chakraborthy.Y parameters Hybrid parameters. conditions for reciprocity and symmetry for Z.Jagan.Chakraborthy.PRINCIPLES OF ELECTRICAL ENGINEERING Lecture Plan LECTURE PLAN S. Problems on transient response of RL circuit.ABCD parameters Inter relation ships between Z. initial conditions 1 Black board and Chalk Transient response of RL circuit using differential equations 1 Black board.Chakraborthy. 14. Admittance parameters Text books referred --Network analysis by N.Chakraborthy-chapter-12 Circuit Theory by A.ABCD parameters 1 Black board and Chalk Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 2 Previous question papers. 1 Black board and Chalk 1 Black board and Chalk 7. Chalk approach and Laplace transform method. Impedance 1 Black board and Chalk parameters.chapter 12 Circuit Theory by A. Problems on series RLC circuit..C. Transient response of RLC circuit using differential equations approach and Laplace transform method. ABCD parameters. conditions for reciprocity and symmetry for h.Tech 2nd Semester Page 204 .No 1.chapter 12 9. 2. Problems on Z. 11. 3.Y parameters. Circuit Theory by A. Transmission parameters Vignan Institute of Technology & Science 1 Black board. 6.chapter 8 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 1 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 1 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 1 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 1 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 1 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 1 12. 15.Chakraborthy-chapter-12 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 2 Previous question papers. 1 Black board and Chalk II B. Inter relation ships between Z. NAME OF THE TOPIC No of Periods Method of Teaching Introduction to PEE 1 Black board and Chalk UNIT 1: TRANSIENT ANALYSIS Transient response. 5.Y. ABCD parameters 1 Black board.Y. 1 Black board and Chalk 8. 1 Black board and Chalk Transient response of RC circuit using differential equations approach and Laplace transform method. 13. Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 2. two port network. Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 2. 10. problems 1 Black board and Chalk 26.attenuation constant. Chalk 1 UNIT-3: FILTERS - Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 2. problems 1 Black board and Chalk 27. 18. constant k-low pass filter. Chalk 30. Introduction. problems. basic laws required for 1 Black board. Unit test-I. 2nd Semester Page 205 . Lecture Plan interconnection of two port networks in series. Symmetrical attenuators.δ-Type. Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 2 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 2 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 3 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 3 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 3 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 3 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 3 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 3 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 3 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 3 UNIT-4 : ATTENUATORS 29. Problems on bridged T and lattice attenuators 1 Black board. Chalk 31.PRINCIPLES OF ELECTRICAL ENGINEERING 17. Classification of filters.problems 1 Black board. m-derived filters 1 Black board. 1 Black board. Chalk 33. interconnection of two port networks in cascade configuration. constant k-low pass filter. bridged T type attenuator 1 Black board. review on basic concepts.Tech. Classification of pass and stop bands 1 Black board and Chalk 24. Expression of filter networks 1 Black board and Chalk 23. Chalk 34. Vignan Institute of Technology & Science Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 4 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 4 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 4 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 4 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 4 Introduction to Electrical engineering by Naidu and Kamakshaiah Principles of Electrical Engineering by Sudhakar II Year B. Symmetrical –T attenuator 1 Black board. Chalk 32. problems 1 Black board and Chalk 28. Chalk and Principle of operation of DC Machines 35. constant k-high pass filter. pass band and stop band. constant k-band pass filter. problems 1 Black board and Chalk 25. problems 1 Black board and Chalk 1 Black board and Chalk 1 Black board and Chalk 19. UNIT-5 : DC MACHINES Introduction.II 21. lattice type attenuator 1 Black board. Image parameters 20. Chalk machines. filter networks 1 Black board and Chalk 22. parallel configuration. Construction of a dc machine 1 37. problems Flux and Armature voltage control methods Vignan Institute of Technology & Science Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 6 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 6 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 6 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 6. 2nd Semester Page 206 . Types of generators-derivations 1 Black board and Chalk 40. 50.PRINCIPLES OF ELECTRICAL ENGINEERING Lecture Plan 36.previous papers Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 6 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 6 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 6 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 6.Tech. Characteristics of dc series generator 1 Black board and Chalk 44. 47.previous papers Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 6 Principles of Electrical Engineering by Sudhakar II Year B. 46. Problems on types of generators 1 Black board and Chalk 42. 52. LCD Projector Characteristics of DC motors 1 Black board and Chalk Problems on types of motors 2 Black board and chalk 3-point starters for DC shunt motor 1 Black board and Chalk 1 Black board and Chalk 1 Black board and Chalk 1 Black board and chalk 1 Black board and Chalk 1 Black board. 53. Characteristics of dc shunt generator 1 Black board and Chalk 43. Principle of operation of DC Motors 1 Black board and Chalk Types of DC Motors 1 Black board and Chalk. 54. problems 1 Black board and Chalk 39. 49. Characteristics of dc compound generator 1 Black board and Chalk and ShyamMohan-chapter 4 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 5 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 5 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 5 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 5 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 5. single turn generator 1 LCD Projector Black board and Chalk and LCD Projector Black board and Chalk and LCD Projector 38. Problems on types of generators 1 Black board and Chalk 41.previous papers Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 5.previous papers Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 5 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 5 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 5 UNIT 6: DC MOTORS 45. 48. EMF equation. Chalk Losses in dc machines efficiency calculations Problems on efficiency calculations Swinburne’s test . 51. 63. 71. 67.PRINCIPLES OF ELECTRICAL ENGINEERING 55. 2nd Semester Page 207 . . Chalk. Problems on OC and SC tests 1 Black board and Chalk 69. Synchros Vignan Institute of Technology & Science 1 Black board and Chalk 1 Black board and Chalk and ShyamMohan-chapter 6 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 6. 61. Chalk. 64. 65. AC servomotor AC tachometers. 59.6 57. problems Lecture Plan 1 Black board and Chalk 1 UNIT 7 : TRANSFORMERS Black board and Chalk and 1 LCD Projector Black board. UNIT-8 : SINGLE PHASE INDUCTION MOTORS Principle of operation of single phase induction motors Black board . Projector.Tech. 62. 58. Problems on speed control methods 56.problems 1 Black board and Chalk Losses and Efficiency of transformer 1 Black board and Chalk 1 Black board and Chalk 1 Black board and Chalk OC and SC tests 1 Black board and Chalk 68. 72. Chalk and 1 LCD Projector board . Principle of operation of single phase transformer Constructional features Types of transformers Emf equation of a single phase transformer. Phasor diagram of a Transformer on No Load Regulation Problems on efficiency and regulation Capacitor motors. 1 Transformer models 1 Black board and Chalk 1 Black board and Chalk Phasor diagram of a transformer on Load 1 Black board and Chalk Equivalent circuit. Unit test in units 5. 70. 66.previous papers Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 7 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 7 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 7 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 7 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 7 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 7 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 7 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 7 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 7 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 7 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 7 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 7 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 8 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 8 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 8 Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 8 II Year B. LCD 1 Projector Shaded pole motors Black board and Chalk 1 60. Chalk and LCD Projector Black board and Chalk Black board and Chalk Black board and Chalk Black board and Chalk Principles of Electrical Engineering by Sudhakar and ShyamMohan-chapter 8 Notes Notes Notes Notes II Year B. 75. 77.Tech. 76. 2nd Semester Page 208 . Lecture Plan Synchros. 74. Stepper Motors 1 Revision on I and II Units Revision on III and IV Units Revision on V and VI Units Revision on VII and VIII Units 1 1 1 1 Vignan Institute of Technology & Science Black board.PRINCIPLES OF ELECTRICAL ENGINEERING 73. LEARNING OBJECTIVES . . . UNIT 3: FILTERS.Derive the conditions of reciprocity and symmetry.Determine the time constant of the given circuit and its effect on transient response . propagation constant of filter networks.Difference between transient response and steady state response. . .Design the constant K low pass filter .Explain the open circuit impedance parameters .Design the m-derived T and Π sections Vignan Institute of Technology & Science II B.Explain the short circuit admittance parameters . .Tech 2nd Semester Page 210 .Determine the relationship between one set of parameters with other types of parameters .Derive the expressions of characteristic impedance.Derive the initial conditions for different circuits.Obtain the different differential equations for different combinations of circuits.PRINCIPLES OF ELECTRICAL ENGINEERING Learning Objectives LEARNING OBJECTIVES UNIT-I: TRANSIENT ANALYSIS( first and second order circuits) At the conclusion of this unit student will .Analyze the two port networks when connected in series.Analyze the two port networks when connected in parallel.Derive the image parameters of a two port network when it is terminated. At the conclusion of this unit student will .Explain the meaning of steady state response .Explain the hybrid parameters of two port networks. UNIT II:TWO PORT NETWORKS At the conclusion of this unit student will .Solve series RL.low pass.Explain the difference between one-port and two port networks. . high pass and band pass filters .Define the different sets of two port parameters .Explain the definitions of different types of filters.Explain the ABCD parameters. .RC and RLC circuits to get transient response with dc excitation. . . . .Analyze the two port networks when connected in cascade.Explain the meaning of transient response . Explain the construction details of dc machine .Identify the types of generators -analyze the equations governing the shunt .Design the band pass filter.Explain the basic laws defined behind the operating principle .Tech 2nd Semester Page 211 .Explain types of dc motors .analyze the operation of a lattice attenuator.Identify the difference between generator & motor principle -Explain the principle of operation of a dc machine .derive the expression of emf of a dc machine.Design the constant K high pass filter.define the different laws used in explaining the principle of operation .Define the various Losses in dc motors .analyze the working of a bridged T type attenuator .PRINCIPLES OF ELECTRICAL ENGINEERING Learning Objectives . series and compound generators -Explain the Characteristics of dc generators UNIT-VI:DC MOTORS At the conclusion of this unit student will . .explain the starting of dc motors . UNIT-IV: SYMMETRICAL ATTENUATORS: At the conclusion of this unit student will -Define an attenuator -analyze the operation of T type attenuator . -analyze the difference between wave and lap windings .analyze the operation of δ type attenuator .Define the efficiency in dc motors -derive the condition for maximum efficiency in dc motors. . Vignan Institute of Technology & Science II B.Explain the Principle of operation of a dc motor .Explain the characteristics of dc motors . UNIT-V: DC MACHINES At the conclusion of this unit student will .Design the band elimination filter. Explain the Principle of operation of AC tachometers .Explain the Principle of operation of Shaded pole motor .Explain the Principle of operation of single phase induction motor -Explain the difference between the shaded pole. capacitor start & capacitor run motor .Explain the operation of single phase transformer -explain the difference between ideal and practical transformers. leading and u. Vignan Institute of Technology & Science II B.PRINCIPLES OF ELECTRICAL ENGINEERING Learning Objectives -determine the efficiency under no load conditions.Explain the phasor diagram of Ideal transformer on No Load and Load .Explain the applications of different types of motors.define the different types of Losses in a transformer . UNIT-VII: TRANSFORMERS At the conclusion of this unit student will . .Define the types of single phase transformers .Explain the Phasor diagram on Load under lagging. .Explain the Principle of operation of Capacitor motors .Explain the of operation of AC servomotor.Explain the stepper motor characteristics . .Explain the various speed control methods of a dc motor.Tech 2nd Semester Page 212 .Explain the Principle of operation of Synchros .f power factors -determine the parameters of a transformer by conducting open circuit test -determine the parameters of a transformer by conducting short circuit test UNIT-VIII : SINGLE PHASE INDUCTION MOTORS: At the conclusion of this unit student will .p.Define the efficiency of a single phase Transformer .Explain the Equivalent circuit of a single phase transformer .Define the regulation of a single phase Transformer . OBJECTIVE TYPE QUESTIONS . The max voltage developed across the capacitor is Vignan Institute of Technology & Science [ ] II B. For a second order system. The Transient current in an R-L-C circuit is oscillatory when a) R=0 [ c) R<2√L/C d) R=2√L/C 5. A rectangular voltage pulse of magnitude V and duration T is applied to a series combination of R . damping ratio δ is 0<δ<1. Double energy transient are produced in circuits consisting of a) two or more resistors b) resistance and inductance c) resistance and capacitance d) resistance . the applied DC voltage drops entirely across the a) R only b) L only [ c) C only ] d) R & L combinations 7. Which of the following does not have the same units as the others? The symbols have their usual meanings [ a) L/R c) √ LC b)RC ] d) 1 / √ LC 6.500 c) 0.c.Tech 2nd Semester Page 214 . Capacitor acts like for the a. signal in the steady state [ ] [ ] a) open b)closed c) not open not close d)none. The response of an LCR circuit to a step input is [ ] [ ] d) imaginary If the T F has a) over damped 1) poles on –ve real axis b) critically damped 2) poles on imaginary axis c) oscillatory 4) poles on +ve real axis 3) multiple poles on +ve real axis abc 5) multiple poles on -ve real axis a) 1 2 5 b) 1 5 2 c) 3 4 5 d) 1 5 4 10. then the roots of the characteristic polynomial are a) real but not equal b) real and equal c) complex conjugates 9. The transient current in a loss free L-C circuit when excited from an ac source is a /an -------sine wave a) over damped b) under damped c) un damped b) R>2√L/C ] [ ] d) critically damped 4.C. 2. Consider a DC voltage source connected to a series RC circuit. A DC voltage source is connected across a series RLC circuit.362 b) 0. When the steady state reaches.PRINCIPLES OF ELECTRICAL ENGINEERING Objectives Type Questions OBJECTIVE TYPE QUESTIONS Unit I: Transient analysis 1.632 ] d) 1. under steady state conditions.00 8.inductance and capacitance 3. the ratio of energy stored in the capacitor to the total energy supplied by the voltage source is equal to [ a) 0. The current through the inductor at time t is equal [ ] a) I0e-Rt/L b) I0 (1-e-Rt/L) c) I0e+Rt/L d) I0 (1-e+Rt/L) 15. there will be no switching transient if a) θ-ϕ=0 b) θ+ϕ=0 c) θ-ϕ=90 [ ] d) θ+ϕ=90 17. Transient current in a circuit results from a) voltage applied to the circuit b) impedance of the circuit c) changes in the stored energy in inductors and capacitors d) resistance of the circuit 16. when excited by an a. What is vc (o+ )? a) 0 [ d) none II B. Energy stored in a capacitor over a cycle. An inductor at t=0 with initial current I0 acts as a) Short b) open c) current source d) voltage source 14. suddenly at time t=0 the inductor is removed from circuit and connected to a resistor R.Tech 2nd Semester Page 215 . A series R – C – L circuit is driven by an ac voltage source. If an RL circuit having angle ϕ is switched in when the applied sinusoidal voltage wave is passing through an angle θ. An inductor L carries steady state current I0. An ideal voltage source will charge an ideal capacitor a) in infinite time b) exponentially c) instantaneously [ ] [ ] [ ] d) none 12.c source is a) same as that due to a dc source of equivalent magnitude b) half of that due to a dc source of equivalent magnitude c) zero d) none 13. Then the voltage across the following elements or the pair of elements cannot exceed the applied voltage a) C b)L c) R b) V c) can’t find Vignan Institute of Technology & Science ] [ ] d) R and L 18.PRINCIPLES OF ELECTRICAL ENGINEERING a) V(1-e-T/RC) b) VT/RC Objectives Type Questions c) V d) Ve-T/RC 11. Tech 2nd Semester Page 216 . switch S is closed at time t=0.d) 6 (c) 7 (b) 8 (c) 9 (b) 10 (a) 11 (c) 12 (c) 13 (c) 14 (a) 15 (c) 16 (a) 17 (c) 18 (b) 19 (c) 20 (d) Vignan Institute of Technology & Science II B. the rate of change of current through it was 4A/s. The RC network is [ ] a) a series combination of R and C b) a parallel combination of R and C c) A series combination of R and parallel combination of R and C d) a pure capacitor 20.5H ANSWERS: 1 (c) 2 (d) 3 (c) 4 (c) 5 (c. In the circuit shown. After some time when the current in the inductor was 6A. When a current source of value 1 is suddenly connected across a two terminal relaxed RC network at time t=0.5H c) 1.PRINCIPLES OF ELECTRICAL ENGINEERING Objectives Type Questions 19. the observed nature of the voltage across the current source is shown in the fig. The value of the inductor is a) Indeterminate b) 1.0H [ ] d) 0. Z12=Z21= 1Ω .PRINCIPLES OF ELECTRICAL ENGINEERING Objectives Type Questions UNIT II: Two port Networks 1. Then Z12 will be _____ ohms. Z22=3Ω.I2) = ( I1.B. condition for reciprocity in terms of h-parameters is (a) H12=h21 (b) h11=h22 (c) h11+h12=0 [ (d) h12=-h21 2. Two port networks are connected in cascade. Number of possible combinations generated by four variables taken two at a time in a two-port network is (a) 4 (b) 2 (c) 6 (b) 1/5 ] [ ] (d) 8 6. Z11 of the network is (a) 5/3 (b) 4/3 (c ) 2/3 ] [ ] [ ] (d) 1/3 11. In a two port network. The h-parameters h11.D (d) Hybrid parameter : (V1. When a number of two port networks are connected in parallel.5 [ ] (c) h11h22-h12h21=1 (d) Y11Y22-Y12Y21 =1 4. A two port network is a network inside a black box and has only _____ terminals (a) 2 ] (d) -0.[ (a)-2 (b) -1 (c) -0.Tech 2nd Semester Page 217 . A two port network is defined by I1=2V1+V2. h22 = Y22 10. the determinant of admittance matrix is (a) 5 [ (c) 1 (d) 2 7. With usual notations. A two port network is symmetrical if Z11-Z22=1 (b) AD-BC=1 ] (b) 2 pairs (c) 2 pairs of ports [ ] (d) 4 pairs of 5. h22=1/Z22 (c) h11=1/Y11 .h22 are related to Z & Y parameters as (a)H11=Z11. a two port resistive network satisfies the condition A=D=3/2B=4/3C.25 3. I2= 2V1+3V2. V2) ] [ ] [ ] AD-BC=1 9. h22=1/Z22 [ (b) h11=Z11 . If Z11=2Ω . Which one of the following pairs is correctly matched? (a)Symmetrical two port network : (b) reciprocal two port network : Z11=Z22 (c ) Inverse hybrid parameter : A. The combination is to be represented as a single twoport network. individual (a) Z matrices are added (b)Y matrices are added (c) chain matrices are added (d) h matrices are added 12. h22=Y22 (d) h11=1/Y11 . Parameters of the network are obtained by multiplying individual (a) Z-parameter matrix (b) AIBICIDI matrix (c) h-parameter matrix (d) ABCD matrix 8.C. The short – circuit admittance matrix of a two-port network is as shown Vignan Institute of Technology & Science [ II B. port network is shown in fig. In respect of the 2-port network shown in the fig. For the circuit shown identify the correct statement .PRINCIPLES OF ELECTRICAL ENGINEERING Objectives Type Questions The two-port network is a) Non reciprocal & passive b) Non-reciprocal & active c) Reciprocal & passive d) reciprocal & active. A 2. Yc (in units of mho) will be respectively [ Vignan Institute of Technology & Science ] II B. Zb is Z parameters of bottom circuit and Z is the Z parameters of complete circuit [ a) for any value of R1 and R2 Z = Za + Zb b) If R1 = R2 =0 then only Z = Za + Zb c) If R1 and R2 is equal to 1 ohm then only Z = Za + Zb d) None ] 14.Tech 2nd Semester Page 218 . The values of Ya.where Za is Z-parameters of top circuit . The parameter h21 for this network can be given by a) – ½ b) +1/2 c) – 3/2 [ ] d) + 3/2 14.Yb. Y12 = Y21 =–6 mho and Y22 = 6 mho. 13. The admittance parameters are: Y11 = 8mho. C = 1/5 .6 and –6 b) 2. then D = ? (a) 1 (b) 1/5 (c) 7/5 (d) 1/3 [ ] ANSWERS: 1 (d) 2 (d) 3 (c) 4 (b) 5 (c) 6 (c) 7 (d) 8 (d) 9 (c) 10 (b) 11 (b) 12 (a) 13 (a) 14 (b) 15 (c) 16 (d) 17 AD- 18.6 and 0 Objectives Type Questions c) 2. h11 and h12 are obtained by [ (a) short circuiting output terminals (b) opening input terminals (c) shorting input terminals (d) opening output terminals ] 20. Z parameters are also called _______ 19. The condition that a 2.Tech 2nd Semester Page 219 . three transmission parameters are A = 6/5 . For a two port bilateral network.port network is reciprocal can be expressed in terms of its ABCD Parameters as __________________ 18.0 and 6 d) 2. open 19 (a) 20 (c) BC = 1 circuit impedance parameters Vignan Institute of Technology & Science II B. B = 17/5 .6 and 8 16.The h parameters of the circuit shown in fig are [ ] 17.PRINCIPLES OF ELECTRICAL ENGINEERING a) 2. resonant frequency is (a)Above cut-off frequency [ (b) below cut=off frequency (c) a & b (d) none 9. Filters consists of ____ elements. Filters are constructed by using _________ 14. An ideal filter should have (a)Zero attenuation in pass band (b) infinite attenuation in stop band (c) Zero attenuation in stop band (d) all of the above 5. In m-derived high pass filter. Its passband is (a)0 Hz to 3. A highpass filter is [ (a)Passes all high frequencies ] (b) attenuates low frequencies (c) attenuates all frequencies below a designated cutoff frequency and passes all frequencies above cut off frequency (d) none 3. value of m is _______ 13. Z2 as series and shunt arm impedances is ________ Vignan Institute of Technology & Science II B. fc = 3. In a m-derived low pass filter. Pass band of a typical filter network with Z1.5KHz [ ] [ ] (d) 7KHz 4.Tech 2nd Semester Page 220 . A band elimination filter is one which [ ] (a) attenuates all frequencies below a designated cutoff frequency (b) attenuates all frequencies above a designated cutoff frequency (c)frequencies between f1.f2 are passed and all other frequencies are attenuated (d) none 11. (a) Only reactive (b) resistive (c) inductive (d) capacitive 15.5 kHz. Attenuation is sharp in stop band for k-type filter True/False 7. Propogation constant of symmetrical T and π-sections are same True/False 6. resonant frequency is ____ frequency (a) Above cut-off (b) below cut-off (c) a & b [ ] [ ] (d) none 12.PRINCIPLES OF ELECTRICAL ENGINEERING Objectives Type Questions UNIT III: FILTERS 1. In m-derived low pass filters. A low pass filter is [ (a) Passes all low frequencies ] (b) attenuates all high frequencies (c) passes all frequencies upto cut off frequency and attenuates all other frequencies (d) none 2. In a certain low-pass filter.f2 are attenuated and all other frequencies are passed (d) frequencies between f1. Attenuation is sharp in stop band for __________ filter (a) Constant-k (b) m-derived (c) both a&b ] [ ] (d) none 8. A band pass filter may be obtained by using a high pass filter followed by a low pass filter True/False 10.5 kHz (b) 0Hz (c) 3. PRINCIPLES OF ELECTRICAL ENGINEERING Objectives Type Questions 16. iterative impedance of a T network is _____ of open and short circuit impedances (a) Addition (b) division (c) subtraction (b) m<-1 ] [ ] (d) geometric mean 17. The value of m in order to have a sharp attenuation is (a) m > 1 [ (c) 0<m <1 (d) m=1 ANSWERS: 1 (c) 2 (c) 10 (c) 11 (b) 3 (a) 4 (a) 5 true 6 false 7 (b) 8 (a) 9 false 12 √1- 13 symmetrical T 14 (a) 15 -1 16 (d) 17 (c) (fc/f∞)2 or π networks <Z1/4Z2 < 0 UNIT IV: ATTENUATORS 1. An attenuator is used (a) To reduce frequency (b) to reduce signal (b) To increase signal amplitude (d) to increase frequency 2. Attenuation by a network in decibels is (a) 10 log20 (P1/P2) (b)20log(P1/P2) (c) 10log10(P1/P2) (a) R0(N-1)/N+1 (B) R0(N+1)/(N-1) (c) N+1/N -1 ] [ ] [ ] [ ] [ ] [ ] [ ] (D) N -1/N+1 (B) R0(N-1)/N+1 (C) R0(N2-1)/N+1 (d) N2-1/N+1 5. Characteristic impedance of symmetrical network (a)open circuit impedance (b) geometric mean of open and short circuit impedance (c) short circuit impedance (d) average of input and output impedances 6. 1 Bell unit of power = ____- decibels of power (a) ½ (b) 5 [ 2 4. The shunt arm of ∂ type attenuator is (b) R0(eὰ+1)/ eὰ+1 ] (d)100loge(P1/P2) 3. The value of series arm of T type attenuator 2 [ (c) 10 (d) 20 7. The parameters of attenuator are ___________ 8. If attenuation of an attenuator is 60db, then current ratio is (a) 500 (b)1000 (c) 750 (d) 250 9. Application of attenuator is _______ 10. General units of attenuation is (a) Degrees (b) nepers (c) radians (d) all the above 11. For attenuators, there will not be any phase shift in the signal true/False ANSWERS: 1 (b) 2 (c) 3 (a) 4 (a) 5 (b) 7 resistors 8 (b) 9. used as volume control in radio 10 (b) 11. true 6 (c) broadcasting stations Vignan Institute of Technology & Science II B.Tech 2nd Semester Page 221 PRINCIPLES OF ELECTRICAL ENGINEERING Objectives Type Questions Unit V: DC MACHINES 1.A dc generator is a machine that converts 2. (a) Electrical to mechanical energy (b) mechanical to electrical energy (c) low currents to high currents (d) all the above Mechanical energy source to drive a dc generator is [ ] [ ] [ ] [ ] [ ] [ ] (a)rotor (b) stator (c) prime mover (d) dc generator 3. Brushes that carry current to load are made of (a)carbon (b) mica (c) lead (d) graphite 4. In a dc generator ,emf is induced in (a) field coils (b) armature coils (c) brushes (d) commutator 5. Type of compound generator used for obtaining a constant terminal voltage (a) over compound (b) under compound (c) flat compound (d) none 6. If flux per pole is ф, then the value of flux in yoke section will be (a) ф (b) 0.5 ф (c) 1.2 ф (d) 1.1 ф 7. Emf generated by a dc generator depends upon [ ] (a) flux only (b) speed (c) flux and speed (d) terminal voltage 8. Commutator segments are insulated from each other by [ ] [ ] [ ] [ ] [ ] [ ] (a) mica (b) paper (c) wood (d) glass 9. Series generator has a ____ haracteristics (a) rising (b) constant (c) drooping (d) linear 10.Nature of current flowing in armature of dc machine (a) dc (b) alternating (c) pulsating (d) none 11.For a wave winding armature, number of parallel paths are (a) number of poles (b) 2 (c) speed (d) Eg 12. For a lap wound armature, number of parallel paths= ________ 13. The principle of operation of a dc generator is based on ________ 14. Fore finger incase of Fleming’s right rule gives (a) direction of voltage (c) direction of magnetic field (b) direction of armature (d) motion of the conductor 15. Central finger in case of Fleming’s right rule indicates ______ 16. Yoke of a dc machine is made up of (a) lead (b) cast steel (c) copper (d) paper Vignan Institute of Technology & Science II B.Tech 2nd Semester Page 222 PRINCIPLES OF ELECTRICAL ENGINEERING Objectives Type Questions 17. Commutator inn a dc generator is used for (a) reducing friction (b) converting dc to ac (c) collecting current from armature (d) convertinf ac to dc [ ] [ ] [ ] 18. In Fleming’s right rule , thumb indicates _________ 19._______ is the cause for building up of voltage in a self-excited generator 20. If speed of prime mover increases, generated emf (a) decreases (b) constant (c) increases (d) zero 21. In a compound generator, fluxes due to series and shunt fields______ each other. (a) add (b) oppose (c) do not depend on each other (d) none. ANSWERS l (b) 2 (c) 3 (a) 4 (b) 5 (c) 6 (b) 7 (c) 8 (a) 9 (a) 10 (b) 11 (b) 12 number 13 Faraday’s laws of 14 (c) 15 direction of induced of poles electro-magnetic induction 17 (d) 18 motion of the conductor 16 (b) 21 (a) emf 19 residual 20 (c) magnetism UNIT VI: DC MOTORS: 1. Hysteresis loss varies with frequency (f) as (a) f 2. (c) f 2 (d) f [ ] [ ] [ ] [ ] 2.6 Hysteresis loss varies with maximum flux density (B) as (a) B 3. (b) f 1.6 (b) B1.6 (c) B2 (d) B2.6. The shaft of electric motors is generally supported in (a) magnetic bearings (b) bush bearings (c) ball or roller bearings (d) cast iron bearings. 4. DC series motor application is to drive (a) where constant operating speed is needed (b) where load is intermittent (c) where load changes frequently (d) cranes, hoists,trains 5. A dc series motor should not be started at light or no-loads because it will [ ] (a)draw a dangerously large current (b) stall (c) run at dangerously high speed (d) none 6. In a dc series motor the torque developed is 20N-m at 10A of load current.If the load current is doubled, the new torque will be Vignan Institute of Technology & Science [ ] II B.Tech 2nd Semester Page 223 PRINCIPLES OF ELECTRICAL ENGINEERING Objectives Type Questions (a) 40 N-m (b) 60 N-m (c) 80 N-m (d) 100 N-m 7. A 440V shunt motor has an armature resistance of 0.4 ohm and a shunt field esistance of 220 ohms. The armature current when the current taken from the supply is 20A is (a) 20A (b) 1000A (c) 1.6A [ ] [ ] [ ] [ ] [ ] (d) 18A 8. The direction of force produced by each conductor can be determined by _________ 9. The induced emf in a motor is proportional to (a)current (b) parallel path (c) speed (d) all of the above 10. Condition of maximum efficiency in a dc machine is _______ 11. Which of the following tests is performed on no-load? (a) brake test (b) Swinburne test (c) load test (d) hopkinson’s test 12. The speed of a dc motor is ____ to flux of the machine (a) same (b) directly proportional (c) inversely proportional (d) constant 13. An electrical motor converts ___ to ______ energy (a) electrical,heat (b) electrical ,mechanical (c) mechanical,electrical (d) electrical, electrical 14. The torque which is available for doing useful work is [ ] [ ] [ ] (a) driving (b) shaft (c) field (d) none 15. Field flux method is used for speeds required_____ the rated speed. (a) below (b) same as (c) above (d) all of the above 16. Armature voltage method is used for speeds required_____ the rated speed. (a) below (b) same as (c) above (d) all of the above 17. In cumulative compound motors, the flux in series and shunt windings ___ to each other.[ ] (a) opposite (b) aid (c) both a& b (d) none 18. In differential compound motors, the flux in series and shunt windings ___ to each other. [ ] (a) opposite (b) aid (c) both a& b (d) none 19. The torque in a dc series motor varies as ____ of the load current [ ] [ ] (a) proportional to half (b) same as (c) less (d) proportional to square 20. The torque in a dc shunt motor varies as ____ to the load current (a) half (b) proportional (c) less (d) square ANSWERS: 1(a) 2 (b) 3 (c) 4 (d) 5 (c) 6 (c) 7 (d) 8 9 (c) 10 Fleming’s variable left hand losses = rule constant losses 11 (b) 12 (c) 13 (b) 14 (b) 15 (c) Vignan Institute of Technology & Science l6 (a) 17 (b) 18 (a) 19 (d) 20 (b) II B.Tech 2nd Semester Page 224 PRINCIPLES OF ELECTRICAL ENGINEERING Objectives Type Questions UNIT- VII: TRANSFORMERS 1. Open circuit test on a transformer is conducted to obtain (a) the leakage impedances (b) the ohmic loss (c) hysteresis loss only (d) core loss only (b) wrought iron (c) silicon steel ] [ ] (e) eddy current loss only. 2. Transformer-core laminations are made of (a) cast iron [ (d) cast steel. 3. Which component of the no load current of the transformer is opposite in phase to the induced emf ? (a) magnetizing component (b) core loss component (c) both (A) and (B) above (d) none of the above. [ ] 4. In transformers, the cylindrical winding with rectangular conductors is generally used for [ ] (a) low voltage winding (b) high voltage winding (c) tertiary voltage winding (d) any of the above. 5. The percentage of silicon in the core steel is (a) 1 to 2 percent (b) 2 to 3 percent (c) 4 to 6 percent (d) 8 to 10 percent. 6. In an oil filled transformer, oil is provided for (a) Cooling (b) Insulation (c) Lubricating [ ] [ ] [ ] [ ] [ ] [ ] (d) Both cooling and insulation (e) Preventing accumulation of dust. 7. The 'hum' in a transformer is due to (a) vibrations in cooling oil (b) vibration in laminations (c) sinusoidal voltage waveform (d) all of the above. 8. When load on a transformer is decreased _______ loss is decreased. 9. A transformer has negative voltage regulation when its load power factor is (a) zero (b) unity (c) laeding (d) lagging 10. Open circuit test on a transformer is performed with (a) direct current (b) indirect current (c) both (d) rated transformer voltage. 11. Transformer core is laminated in order to (a) decrease iron loss (b prevent eddy current loss (c) increase iron loss (d) none 12. A 2KVA transformer has iron losses of 150W and full load copper losses of 250W. The maximum efficiency of the transformer would occur when the total loss is [ ] [ ] (a) 500W (b) 400W (c) 300W (d) 275W 13. The maximum efficiency of a transformer will occur when ______ 14. An ideal transformer is one which Vignan Institute of Technology & Science II B.Tech 2nd Semester Page 225 A capacitor start single phase induction motor will usually have a power factor of (a) unity (b) 0. In case CRGO steel is used instead of hot rolled steel in electrical machines.8 leading (c) 0. 9 (c) 10 (d) 20 (a) 21 11 (b) copper 12 (c) 13 14 (a) 15 (d) 16 copper mutual losses induction 17 (c) 18 (d) 19 (a) higher = iron losses UNIT-VIII: Single phase motors 1. A transformer transforms (a) frequency (b) voltage (c) current (d) both b &c 19. The induced emf in a transformer ____ flux by _____. Vignan Institute of Technology & Science [ II B. capacitor run single phase induction motor is basically a (a) ac series motor (b) dc series motor (c) 2 phase induction motor (d) 3 phase induction motor.90 (d) leads 180 degrees 18. Then iron losses are [ ] (a) 77W (b) 467W (c) 847W (d) 133.6 leading ] [ ] (d) 0.PRINCIPLES OF ELECTRICAL ENGINEERING Objectives Type Questions (a) has no leakage reactance and no losses (b) does not work (c) same number of primary and secondary windings (d) none 15.Tech 2nd Semester Page 226 . A capacitor start.6 lagging. 180 (b) leads. Short circuit test on a transformer is conducted at (a) rated current (b) rated voltage (c) half load (d) all of the above 20. its efficiency will be __________ ANSWERS: l (d) 2 (c) 3 (b) 4 (a) 5 (c) 6 (d) 7 (b) 8.90 (c) lags. Transformer operates on the principle of _____ 17. The ratinf of a transformer is usually in [ ] [ ] [ ] [ ] (a) volts (b) amperes (c) KW (d) KVA 16. A 1-phase.7W 21. (a) lags.385 lag. 2200/200V transformer takes 1A at the HV side on no-load at a p. 2.f of 0. [ ] [ ] [ ] 10. 5. shading coils are used to (a) reduce windage losses (b) reduce friction losses (c) produce rotating magnetic field (d) to protect against sparking. Single phase motors generally get over heated due to (a) Overloading (b) Short windings (c) Bearing troubles (d) Any of the above. 6. Which single phase ac motor will you select for record players and tape recorders ? [ (a) Hysteresis motor (b) Shaded pole motor (c) Reluctance motor (d) Two value capacitor motor.PRINCIPLES OF ELECTRICAL ENGINEERING Objectives Type Questions 3. In a single phase capacitor motor the direction of rotation will be in the opposite direction to the original when [ ] [ ] [ ] (a) electrolytic capacitor is replaced by paper capacitor (b) two capacitors of equal value are used (c) capacitor is replaced by a resistance (d) capacitor is replaced by an inductor. In a shaded pole motor. the probable cause may be (a) open in auxiliary winding (b) open in main winding (c) blown fuses (d) any of the above.Tech 2nd Semester Page 227 . For ceiling fans generally the single phase motor used is (a) split phase type (b) capacitor start type (c) capacitor start and run type (d) permanent capacitor type.Is [ 4. If a single phase motor fails to start. 9. The torque developed by a split phase motor is proportional to (a) Sine of angle between lm and ls (b) Cosine of angle between lm and Is (c) Main winding current. Which of the following is the most economical method of starting a single phase motor [ (a) Resistance start method (b) Inductance start method (c) Capacitance start method (d) Split-phase method. Vignan Institute of Technology & Science II B. 7. A motor generally used in toys is (a) Hysteresis motor (b) Shaded pole motor (c) Two value capacitor motor (d) Reluctance motor. 8. A universal motor is one [ ] ] ] ] (a) which can run on any value of supply voltage (b) which has infinitely varying speed (c) which can operate on ac as well as dc voltage (d) which can work as single phase or three phase motor. 11. 12. Im (d) Auxiliary winding current. (b) shaded portion to the unshaded portion of the pole while the flux in the former lags that the latter. 16. 18. (b) 19. the rotor runs from the [ ] (a) shaded portion to the unshaded portion of the pole while the flux in the former leads that the latter. ] ANSWERS 1 (d) 2 (b) 3 (a) 4 (c) 5 (a) 6 (c) 7 (d) 8 (b) 9 (d) 10 (d) 11 (c) 12 (d) 13 (a) 14 (a) 15. 17. (c) 18. True/False 20. (d) Copper Quadrature Vignan Institute of Technology & Science II B. In a capacitor start motor. In capacitor motors.PRINCIPLES OF ELECTRICAL ENGINEERING Objectives Type Questions 13. the current is in ________ with that in the main winding. In a shaded pole induction motor. True 20. Which motor will make least noise ? [ (a) Capacitor motor (b) Universal motor (c) Shaded pole motor (d) Hysteresis motor. 14. (d) unshaded portion to the shaded portion of the pole while the flux in the former lags that the latter.Tech 2nd Semester Page 228 . (c) unshaded portion to the shaded portion of the pole while the flux in the former leads that the latter. 17. The principle of operation of a single phase induction motor depends upon rotating magnetic fields. In shaded pole motors the shading coil is normally made of __________ 16. (d) none 15. the capacitor is connected in series with (a) starting winding (b) running winding (c) compensating winding (d) none of the above. Single phase induction motor can be made self starting by [ ] [ ] (a) adding series combination of a capacitor and auxiliary winding in parallel with the main winding (b) adding an auxiliary winding in parallel with the main winding (c) adding an auxiliary winding in series with a capacitor and the main winding. A linear ac servo motor must have [ (a) high rotor reactance (b) high rotor resistance (c ) large air gap (d) both high motor resistance and reactance ] 19. ESSAY TYPE QUESTIONS . Derive an expression for the current response in R-L series circuit with a dc source? 4..A dc voltage of 20V is applied in R-L circuit where R=5 and C=1F ..A dc voltage of 100V is applied in the circuit shown in fig below and the switch is kept open.Tech 2nd Semester Page 230 . The switch K is closed at t=0 .find the complete expression for the current? 2.A dc voltage of 20V is applied in R-L circuit where R=5 and L=0.Find (i) Time constant (ii) maximum value of energy stored 3.PRINCIPLES OF ELECTRICAL ENGINEERING ESSAY Questions ESSAY TYPE QUESTIONS UNIT:1 DC TRANSIENT ANALYSIS 1.1H .Draw the network in Laplace domain and find I(S) 7.Derive an expression for the current response in R-L-C series circuit with a dc source? 8.Derive an expression for the current response in R-C series circuit with a dc source? 5.Define time constant? What is the importance of it? 6.Find Vignan Institute of Technology & Science II B. the switch is moved to position 2.1). In a series RL circuit with R = 3 ohm and L = 1 H. Then find the current ‘i’. the switch is closed on the position 1 at t = 0 there by applying a D.Switch is opened at t = 0 in the below circuit . (a) In the circuit shown in Figure 4. At t = 500_sec. 12. Vignan Institute of Technology & Science II B. find the current in 20Ω when the switch is opened at t = 0.PRINCIPLES OF ELECTRICAL ENGINEERING ESSAY Questions (i) Time constant (ii) maximum value of energy stored 9. 2) in to ‘S’ domain and determine the Laplace transform impedance.For the below circuit (Figure. 13. 10.Tech 2nd Semester Page 231 . 11.Transform the below circuit (Figure. a DC voltage of E = 50 V is applied at t = 0. voltage of 100V to series R-L circuit. Obtain the expression for current i(t) in the both intervals sketch i(t).C. Find the transient response of current and plot the response. Find the initial conditions at t = 0+ for i1. [8+7 Figure 4: Figure 5: 14. i2. UNIT II: TWO PORT NETWORKS 1. Derive the expression for i(t) of RC series circuit with zero initial conditions and show the variation of i with time t . Vc.Tech 2nd Semester Page 232 . di2/dt.PRINCIPLES OF ELECTRICAL ENGINEERING ESSAY Questions (b) The switch S is closed at t = 0 (Figure 5).Find the Z parameters of the network shown in figure below? Vignan Institute of Technology & Science II B. di1/dt. Tech 2nd Semester Page 233 . Z.PRINCIPLES OF ELECTRICAL ENGINEERING ESSAY Questions 2.5 V1 .2 V2 I2 = -0. Also find its equivalent _ network.3 mho Determine the (i) ABCD parameters and (ii) Equivalent  network Vignan Institute of Technology & Science II B. 5.2V1 + V Where V1 and V2 are the port voltages at port 1 and 2 respectively. For the two port network shown in the figure 6. ABCD parameters for the network. Obtain Z parameters of the below circuit (Figure. Find the Y.Find the Y parameters of the network shown in figure below? 3.0. 4.6 mho.2 mho and Y12=-0. 3) and from there Z – parameters derive h – parameters. the currents I1 and I2 entering at port 1 and 2 respectively are given by the equations.The Y parameters of a two port network are Y11=0.Y22=1. I1 = 0.Find the transmission parameters of the network shown in figure? 6. Obtain the Z parameters of the combination.Find the h parameters of the network shown in figure below? 8. Obtain the Y arameters of the combination? Vignan Institute of Technology & Science II B. Also verify by direct calculation? 12.Give the conditions for (i) symmetry (ii) reciprocity for Z parameters .Tech 2nd Semester Page 234 .Two identical sections of the network shown in figure below are connected in parallel. h parameters and ABCD parameters 11. Y parameters.PRINCIPLES OF ELECTRICAL ENGINEERING ESSAY Questions 7. Derive Y parameters in terms of ABCD parameters? 10.In a T network Z1=200 Z2=5-300and Z3=3900Find Z parameters and hence find Y parameters ? 9.Two networks shown in figures below are connected in series. parameters of the network shown in Figure Figure : Vignan Institute of Technology & Science II B. (c) Find the ABCD parameters for network shown in Figure 1.Obtain the input and output impedances of an amplifier having h11 = 2 ohm.Reciprocal and Symmetrical Networks.Find Z. (a) Define.PRINCIPLES OF ELECTRICAL ENGINEERING ESSAY Questions 13. h21 = 5.Determine the Z and Y. 16. h22 = 2 mho.Tech 2nd Semester Page 235 . (b) What is the condition for the given network to be reciprocal as well as Symmetrical in terms of ABCD parameters. 14. if it is driven by a source having an internal resistance of 4 ohm and is terminated through a load which draws maximum power from the amplifier. Y Parameters for the network. h12 = 1. Figure 1 15. Obtain the parameters of a symmetrical T attenuator with attenuation =25db and design impedance 500 ohms.Derive the design parameters of a band pass filter.Design a band elimination filter having design impedance of 600 and cutoff frequencies f1=2 KHz and f2=6 KHz 10. UNIT IV: ATTENUATORS 1. Derive the design parameters of a symmetrical T attenuator. Derive the design parameters of a symmetrical delta attenuator . 15. 2.Design a low pass  section filter having a cutoff frequency of 2 KHz to operate with a terminal load resistance of 400. Derive the design parameters of a lattice attenuator .Tech 2nd Semester Page 236 . design impedance of 5Ω and m = 0.4 11. 14. 9.Explain m-derived low-pass T-section and π-section in detail and the necessary design procedure. 7. 3.Design a band elimination filter having a design impedance of 500 and cut off frequencies f1=1KHz and f2=5KHz 6.Derive the expression for the characteristic impedance of a symmetrical T filter? 3.Derive the expression for the characteristic impedance of a symmetrical  filter? 4.Design a m – derived high pass filter with a cut – off frequency of 10KHz. Vignan Institute of Technology & Science II B.Derive the design parameters of a m-derived pass filter.Derive the design parameters of a low pass filter.Define filter? Give the classification of filters? 2.Design a high pass filter to have a design impedance of 500 and cut ff frequency of 1KHz? 5. 13.Design a low pass T section filter having a cutoff frequency of 1. Design a high pass  section filter having a cutoff frequency of1 KHz to operate with a terminal load resistance of 800.PRINCIPLES OF ELECTRICAL ENGINEERING ESSAY Questions UNIT III: FILTERS 1. What is a half section? What is its main characteristics? Why it is used? Derive expression for impedances as seen from the two-ports of an m-derived half section. 8. Derive the design parameters of a bridged T attenuator.5KHz to operate with a terminal load resistance of 600. 5. 4. 12. An attenuator is composed of symmetrical T-section having series arm each of 420 ohms and shunt arm of 740 ohms. 8. Assume brush voltage per brush as 1V 6. (a) Explain symmetrical _T-type attenuator with necessary equations in detail. 10. The emf generated by a 4 pole wave connected dc generator is 500V on load at a speed of 1000rpm. 9. Obtain the parameters of a symmetrical lattice attenuator with attenuation 25db and characteristic impedance of 800 ohms. each coil side consisting of 4 turns. Explain the characteristics of a dc series generator 5. (a) Design a T-type attenuator to have an attenuation of 40db and to work between source impedance of 400 ohms and load impedance of 900 ohms. Find the number of conductors required for a 4 pole wave wound generator to generate an induced emf of 220V. 8. Derive expression for and calculate the characteristic impedance of this network and attenuation per section.Tech 2nd Semester Page 237 . 7. Calculate the flux per pole. A shunt generator supplying a 200KW at 230V has a field circuit resistance of 150 ohms and an armature resistance of 0. Explain the characteristics of a dc shunt generator 4. Obtain the parameters of a symmetrical π attenuator with attenuation =20db to have a characteristic impedance of 100 ohms. Explain the constructional features of a dc machine 2. [10+5] 11. Draw the circuit diagram for symmetrical T-type attenuator. Unit V: DC MACHINES 1.25 ohms. What is an Attenuator? Explain different types of symmetrical attenuators in detail? 12.PRINCIPLES OF ELECTRICAL ENGINEERING ESSAY Questions 6. the flux per pole is 0. if the armature has 144 slots with two coil sides per slot. (b) Design a π-type attenuator to have an attenuation of 25db and to work between source impedance of 600 ohms and load impedance of 1000 ohms. Calculate a) full load current b) armature current c) generated emf d) field current. Explain the types of dc generators. Obtain the parameters of a bridged attenuator with attenuation 20db and terminated to a load of 400 ohms. Derive the emf equation of a dc machine 3. (b) Design a symmetrical _ π -type attenuator to give 20 db attenuation and to have a characteristic impedance of 200 ohms. 7.01 Wb and the speed of the machine is 1200 rpm Vignan Institute of Technology & Science II B. (b) Draw the circuit model of a DC shunt generator and write the relationship of currents and voltages. Derive the torque equation of a dc motor. Explain the characteristics of dc motors. Explain the power flow diagram of a) dc motor b) dc generator 5. each coil consisting of 3 turns.2 ohms respectively. Explain the various speed control methods of a dc motor 7. The field is excited by 150V dc supply. the resistance of armature. the ux per pole being 0. Compare DC generator and DC motor from principle of operation point of view and mention the application of each machine? UNIT VI: DC MOTORS 1. resistance of field and armature windings are 125 and 0. (a) Name the main parts of a DC machine and state the materials of which each part is made of and explain clearly the reasons to select these materials. Explain the principle of operation of a dc motor. A dc shunt motor rotating at 1500 rpm is supplied from a 250V the line current is 62 A. series field and shunt field are 0. Calculate the generated emf.05 ohms. Calculate the flux per pole required if the armature has 144 slots with two coil sides per slot.0.055 Wb. A long shunt compound generator supplies a load current of 75A at 440V.PRINCIPLES OF ELECTRICAL ENGINEERING ESSAY Questions 9. Find a) field current b) armature current c) load current and d) generated emf. Derive the condition for maximum efficiency of a dc machine Vignan Institute of Technology & Science II B.Tech 2nd Semester Page 238 . armature resistance is 0.02. Determine a) armature current b) back emf c) power developed by the armature if the rotational losses are 200 W 6. 12. 11. 240V separately excited generator is delivering rated load at rated voltage. Assume 1V drop per brush 10. if the number of conductors is 650. 4. (b)A Certain wave wound DC generator running at a speed of 300rpm is to generate an induced emf of about 535V. The wave connected armature of a four pole dc generator is required to generate an emf of 520V when driven at 600 rev/min. 14. field resistrance is 100 ohms.Determine the number of poles. 3.01 and 150 ohms respectively. (a) What is a DC generator? Explain its constructional details. 2. 13. A 220KW. The flux per pole is 34. 15. The field coils are all connected in series. (a) With a neat sketch. find the change in back e. if the coils are reconnected in two parallel groups of two in series. 12. Assume a total brush drop of 2V 10. Explain the constructional details of a single phase transformer 2.Tech 2nd Semester Page 239 .f from no-load to full-load. If the full load armature current is 20A and the no load armature current is 5A. 9. If the full load current is 28A.6 mWb and the total mechanical torque developed is 209 N-m. (a) A series wound motor runs normally.4 and 220 ohms respectively. 220 ohms respectively.The motor takes a current of 80A. In Swinburne’s test. The applied voltage is 500 V and total motor resistance is 3. when taking a current of 15 A. there is a 5% reduction of flux under full load due to armature reaction. Explain the principle of operation of a single phase transformer Vignan Institute of Technology & Science II B. 11. explain how the direction of rotation of DC motor can be reversed? (b) Derive the standard torque equation of DC motor from first principles. (b) A 250V. Calculate the line current taken by the motor and the speed at which it will run. taking 40A c) running as generator delivering 40A at 220V. (a) All general requirements of the electric traction are fulfilled by DC series motors compared to other DC motors". 14.88ohms . (b) A 220V motor has an armature circuit resistance of 0. It takes a no load current of 40a at 1000 rpm. It has armature and field resistance of 0. Determine a) the constant losses b) the full load efficiency when running as motor. Classify the different types of losses of a dc machine.m. 4-pole wave wound DC series motor has 888 conductors on its armature. Find the resistance to be connected inseries with armature if it has to take the same current at the same voltage at600 rpm.PRINCIPLES OF ELECTRICAL ENGINEERING ESSAY Questions 8. Find a) speed at full load b) speed regulation. Assume that flux is directly proportional to the current and ignore the losses.VII: TRANSFORMERS 1. Justify with related equations and characteristics.3 and Rf = 0. Themotor has Ra = 0. a dc shunt motor takes 4A at 220V. 13. Determine i) Speed ii) Gross torque developed if it has a flux per pole of 28 mwb.5. Assume flux is proportional to current.(a) Explain why Swinburnes test cannot be used to determine the effciency of DC series motor? (b) A 4 pole series motor has 944 wave-connected armature conductors at a certain load.A 220V series motor runs at 800 rpm. The load torque increases as the square of the speed. A 220V dc shunt motor has an armature resistance and shunt field resistances of 0. UNIT. Estimate the speed and current taken by the motor. the armature and field resistances are 0.2 .6. 8 power factor lagging.0Wb/sq. 5. derive the expression for the EMF equation of a single phase transformer.8A SC test data on LV side : 20V 1000W 200A Obtain the equivalent circuit as referred to primary side 7. 9. the primary and secondary turns and ii. Determine:i. Find peak value of the flux in the core and the secondary voltage. single phase transformer has 400 turns on the primary and 100turns on the secondary. Derive the expression of voltage regulation of a single phase transformer. The core cross section of a single phase transformer is 40cm2 that has N1= 80 and N2 = 40 and V1 = 220V at 50Hz. 11. The primary winding of a 50Hz single phase transformer has 500 turns and is supplied from 3300V supply. Derive the equivalent circuit of a single phase transformer 6.2200/220V. (b) A 40 KVA. Explain the operation of an ideal transformer under no load conditions along with necessary phasor diagrams. 10. single phase transformer is 1. 12. Derive the condition for maximum efficiency of a single phase transformer. Find efficiency at a) full load unity power factor b) full load 0. determine: i. [7+8] Vignan Institute of Technology & Science II B. A 100 kVA transformer has iron losses of 1. 50Hz. 14. area of the core. The secondary voltage and ii. A 75KVA. The primary is connected to 2000V. Find a) the kVA for maximum efficiency b) maximum efficiency. A 200KVA single phase 2200/1100 V. 13. If the emf per turn is 8 Volts. (a) From the fundamentals. 8.8 power factor lagging c) at three fourth 0. 50 Hz supply. Calculate the current in the primary winding of the transformer.PRINCIPLES OF ELECTRICAL ENGINEERING ESSAY Questions 3. single phase 50Hz transformer full load copper and iron losses are 1800W and 1000W.Tech 2nd Semester Page 240 . The secondary winding has 50 turns.m.5kW. Find the flux density and secondary induced emf 4. 50Hz transformer recorded the following readings during SC and OC tests: OC test data on HV side : 2200V 1700W 2. The maximum value of flux. Explain the operation of an practical transformer under load conditions along with necessary phasor diagrams for lagging and leading power factors. The maximum flux density in the core of 240/2400V.2 kW and full load copper lossesof 1. 22. ii.8 lagging and iii.65V. Find the full load regulation for load power factors of: i.8 power factor. determine the secondary current at which the maximum effciency occurs and the maximum effciency at 0. The equivalent leakage reactance as referred to the primary winding is 30 Ohm.8 leading. 450/120V. Explain the working of a capacitor start motor 4. Explain the operation of a single phase induction motor according to double field revolving theory 2. 0. 6600/250 V. Explain the principle of operation of synchros 8. Describe the types of tachometers with their working 7.3 ohm and 0.1-phase transformer are 8 ohm and 0. Explain the principle of operation of stepper motors including its characteristics 9.2A. (a) What are the different losses in a transformer? Derive the condition for maximum effciency of a single phase transformer.PRINCIPLES OF ELECTRICAL ENGINEERING 15. 0. The equivalent circuit constants. 50Hz transformer are O. UNIT-VIII: SINGLE PHASE INDUCTION MOTORS 1.C. (b) The primary and secondary winding resistances of a 30 KVA. (a) What is transformer regulation? How it can be obtained from equivalent circuit parameters? (b) The primary and secondary resistance of a 1100/220 V transformer are 0. ESSAY Questions (a) What is regulation? How can it be obtained from equivalent circuit parameters? (b) The readings obtained from tests on 10 KVA. If iron loss amounts to 260 W. Describe the working of shaded pole motors 5.Tech 2nd Semester Page 241 .C. Test (HV Side): 9.120W Compute: i.02 ohm respectively. Unity ii.2A. 17.4. Explain the operation of a single phase induction motor according to cross field revolving theory Vignan Institute of Technology & Science II B. Explain the following: a) Hybrid motors b) Permanent magnet stepper motor 10. The efficiency at half load and 80% lagging power factor. Explain the torque-slip characteristics of a single phase induction motor along with the relevant equivalent circuit 3.015 ohm respectively. Explain the characteristics of ac servo motor along with its transfer function 6. Test (LV Side) : 120V. 80W S. 16. Discuss why single phase induction motor is not self starting? Explain different techniques for starting of 1-phase induction motor.Tech 2nd Semester Page 242 . 12. Explain the concept of split-phase induction motor along with its characteristics. Vignan Institute of Technology & Science II B.PRINCIPLES OF ELECTRICAL ENGINEERING ESSAY Questions 11. ASSIGNMENT QUESTIONS . 3. For the below circuit (Figure. when the switch is opened at t = 0. 2.PRINCIPLES OF ELECTRICAL ENGINEERING Assignment Questions ASSIGNMENT QUESTIONS UNIT I: Transient Analysis 1.Tech 2nd Semester Page 244 . find the current equation i(t). For the circuit shown below Figure. Vignan Institute of Technology & Science II B. 1). find the current equation when switch S is opened at t = 0.2) in to ‘S’ domain and determine the laplace impedance. Transform the below circuit (Figure. 1. Determine the current i for t ≥ 0 if initial current i(0) = 1 for the below circuit 4. 2. Express Z parameters in terms of Y parameters? 4. Two identical sections of the network shown in figure below are connected in cascaded Vignan Institute of Technology & Science II B. Find Y parameters and hence find h parameters for the network a. Determine the transmission parameter and hence determine the short circuit admittance parameters for the below circuit a.Tech 2nd Semester Page 245 . 3. Express ABCD parameters in terms of h parameters? 5.PRINCIPLES OF ELECTRICAL ENGINEERING Assignment Questions UNIT II: Two port networks 1. Explain the lattice attenuator and also design a lattice attenuator to have a characteristic impedance of 800Ω and attenuation of 20 dB. It runs at Vignan Institute of Technology & Science II B. 3.25 KHz and f = 6 KHZ.Tech 2nd Semester Page 246 . Explain Bridged – T attenuator and also design it with an attenuation of 20 dB and terminated in a load of 500Ω. 3. 2.PRINCIPLES OF ELECTRICAL ENGINEERING Assignment Questions Obtain the ABCD parameters of the combination? UNIT III: Filters 1. Design a band elimination filter having a design impedance of 500Ω and cut – off frequencies f = 1. A 6 – pole dc shunt generator with a wave – wound armature has 960 conductors. Explain T – type attenuator and also design a T – type attenuator to give an attenuation of 60dB and to work in a line of 500Ω impedance. Explain π – type attenuator and also design it to give 20db attenuation and to have characteristic impedance of 100Ω. 4. Classify pass band and stop band when the impedances are of opposite type 4. 3. Unit V: DC Machines 1. 2. What are the different types of dc generators? Show the connection diagrams and load characteristics of each type. Derive the design parameters of a high pass filter. UNIT IV:Attenuators 1. 1 2 2. Derive the resonant frequency of a m derived high pass filter. State the principle of operation of a dc generator and derive the expression for the emf generated. 8 power factor. If 6. the induced emf and flux per pole. ii. Calculate the full load speed if the motor armature resistance is 0.Tech 2nd Semester Page 247 . a Estimate efficiency of motor when working under full load. Running light: Armature current of 6. UNIT VI: DC Motors 1. 7. unity power factor. 500V dc shunt motor has 700 wave connected armature conductors. A 10 KVA 2500/250 Volts single phase transformer gave the following test results Open circuit test : 250 V. Find the armature current.2Ω and brush drop is 1V per brush.5 A and field current = 2. 100 KVA transformer has full load copper loss of 1200W and its iron loss is 960W.8 A. 0. 50 W Short circuit test: 60V 3A 45 W 2.8 power factor lag 3. A load of 20Ω is connected to the generator at a terminal voltage of 240V. Explain why a dc series motor should never run unloaded. Vignan Institute of Technology & Science II B. Calculate the efficiency and voltage regulation at full load 0. The full load armature current is 60 A and the flux per pole is 30mWb. A 50Hz. The efficiency at full load. find the new current and terminal voltage.2A With armature locked: I =70A when potential difference of 3V was applied to the brusher.PRINCIPLES OF ELECTRICAL ENGINEERING Assignment Questions a speed of 500 rpm. 0. 1Ø.92kW. The useful flux per pole is 30mWb and speed is 800 rpm. 2. UNIT.4 is 5. 4. The armature and field resistances are 0. 3. The efficiency at half load. Derive the torque equation of a dc motor.3Ω and 240Ω respectively. A 200V. A 4 pole. running at 1000 rpm and delivering 5. A Series generator having combined armature and field resistance of 0. Calculate: i. 14. A 4 pole generator has 48 slots and 8 conductors per slot.VII: Transformers 1. the speed is raised to 1500 rpm and load is adjusted to 10kW. 4. Find the generated emf.5kW at a terminal voltage of 110V. if the machine is wave connected. dc shunt motor when tested by Swinburne’s method gave the following test results. 50 Hz.C Test (LV Side): 250V 1.m. 9. A 20 kVA transformer has its maximum efficiency of 0. is 1. calculate: i) The full load primary and secondary currents. 220/400V. 17. 2A.98 at 15 kVA at upf. 2500/250V.Side 11. 0. 50Hz. The iron loss is 350W. 16. single phase transformer gave the following results: OC Test: 220V. ii) The no-load secondary induced emf.Side 12. Assignment Questions The efficiency at 7.7 power factor. Open circuit and short circuit tests on a 5 KVA. 1. A 200/400V.φ transformer 14.φ transformer has 500 turns and is supplied from 3300V supply. 15.φ transformer gave the following test figures: i) O. 1. 8.The maximum flux density in the core of 240/2400V.C Test (HV Side): 105V 8A 320W Vignan Institute of Technology & Science II B. If the EMF per turn is 16 volts.V. determine: i.V. 1.9 power factor lagging. for 0.7A 70 W -on L. Derive the expression for the induced emf of a transformer.C Test: 15V 10A 85 W -on H. V1=200V. Calculate the efficiency at full load. Find the peak value of the flux in the core and the secondary voltage. A 25 kVA. 5. iii) Maximum flux in the core.Tech 2nd Semester Page 248 . Calculate the secondary voltage when delivering 5kW at 0. Draw the phasor diagram of a single phase transformer under load conditions for lagging.f lag and upf.4A. 50Hz. Neglecting losses.5% of full load. A 125 KVA transformer having primary voltage of 2000V at 50 Hz has 182 primary and 40 secondary turns.4A 105W ii) S. O. The secondary winding has 50 turns.8lag. 7. 8.C. 1. The primary winding of a 50Hz. 0.φ transformer has the following test data 10. leading and unity power factors. 13.8 p. the primary & secondary turns and ii. S. 200W ( hv side) 6. Test: 200V 0. Determine the efficiency and approximate regulation at full load. 100W (lv side) SC Test: 40V. 11.PRINCIPLES OF ELECTRICAL ENGINEERING iii. 4. area of the core.0Wb/sq. UNIT-VIII: Single phase induction motors 1. 3. Draw the circuit diagram of capacitor – start. Where this type of motor is commonly used? 2.8 p. b) AC tachometers. Also obtain percentage regulation at full load with 0.Tech 2nd Semester Page 249 . Write a short note on the following: a) Stepper motor. capacitor – run single phase induction motor and explain its working.PRINCIPLES OF ELECTRICAL ENGINEERING Assignment Questions iii) Compute the equivalent circuit parameters referred to LV side and HV side. Explain the principle of operation of a single phase induction motor based on double field revolving theory ****THE END*** Vignan Institute of Technology & Science II B.f lagging. Professor & mrs.padmaja asst.professor Lab Schedule Department of ELECTRONICS AND COMMUNICATION ENGINEERING VIGNAN INSTITUTE OF TECHNOLOGY AND SCIENCE VIGNAN HILLS. Hyderabad) .b. DESHMUKHI VILLAGE.p. POCHAMPALLY (MANDAL) NALGONDA (DISTRICT) .Pulse & digital circuit laboratory Ms.508284 Sponsored by Lavu Educational Society (Approved by AICTE and Affiliated to JNT University. vijaya laxmi Assoc. Tech 2nd Semester Page 251 .NO Name Of The Experiment LABORATORY SHEDULE 1 Linear Wave shaping Regular Experiment*/ Additional Experiment+ Regular Experiment 2 Non Linear Wave shaping .PULSE &DIGITAL CIRCUITS LAB S.Clippers Regular Experiment 3 Non Linear Wave shaping .Clampers Regular Experiment 4 Transistor as a switch Regular Experiment 5 Bistable Multivibrator Regular Experiment 6 Monostable Multivibrator Regular Experiment 7 Astable Multivibrator Regular Experiment 8 Schmitt Trigger Regular Experiment 9 UJT Relaxation Oscillator Regular Experiment 10 Bootstrap sweep circuit Regular Experiment 11 Study of Logic Gates and some Applications Regular Experiment 12 Study of Flip-Flops and some application Regular Experiment Vignan Institute of Technology & Science Remarks II B. 508284 Sponsored by Lavu Educational Society (Approved by AICTE and Affiliated to JNT University.Harshavardini AssT.professor Lab Schedule Department of ELECTRONICS AND COMMUNICATION ENGINEERING VIGNAN INSTITUTE OF TECHNOLOGY AND SCIENCE VIGNAN HILLS.A. DESHMUKHI VILLAGE. Professor & mr.P.n.hathiram asst.ELECTRONIC CIRCUIT ANALYSIS labaratory Mrs. POCHAMPALLY (MANDAL) NALGONDA (DISTRICT) . Hyderabad) . Simulation of Cascode Amplifier Regular Experiment 12.Tech 2nd Semester Page 253 . Simulation of Common Source Regular Experiment amplifier 4. Simulation of High Frequency Vignan Institute of Technology & Science Additional Experiment II B. Two Stage RC Coupled Amplifier Regular Experiment 7. Simulation of Two Stage RC Coupled Regular Experiment Amplifier 6. Simulation of Single Tuned Voltage Regular Experiment Amplifier 8. Common Source amplifier Regular Experiment 5. Simulation of Wien Bridge Oscillator Regular Experiment using Transistors 10. Hartley & Colpitt’s Oscillators Regular Experiment 11. RC Phase Shift Oscillator using Regular Experiment Transistors 9. MOSFET amplifier Regular Experiment 13. Common Emitter amplifier Regular Experiment 3. Simulation of Common Emitter Regular Experiment amplifier 2.ELECTRONIC CIRCUIT ANALYSIS LAB S.NO Name Of The Experiment LABORATORY SHEDULE Regular Experiment*/ Remarks Additional Experiment+ 1. ELECTRONIC CIRCUIT ANALYSIS LAB LABORATORY SHEDULE Common Base (Bjt)/Common Gate (JFET) Amplifier 14. High Frequency Common Base Additional Experiment (Bjt)/Common Gate (Jfet) Amplifier Vignan Institute of Technology & Science II B.Tech 2nd Semester Page 254 . sravanthi AssT. DESHMUKHI VILLAGE. Hyderabad) .ELECTRICAL ENGINEERING laboratory Mrs. Professor Lab Schedule Department of ELECTRONICS AND COMMUNICATION ENGINEERING VIGNAN INSTITUTE OF TECHNOLOGY AND SCIENCE VIGNAN HILLS.508284 Sponsored by Lavu Educational Society (Approved by AICTE and Affiliated to JNT University. G. POCHAMPALLY (MANDAL) NALGONDA (DISTRICT) . ELECTRICAL ENGINEERING LAB LABAROTARY SHEDULE S.NO Name Of The Experiment 1 2 3 4 5 6 7 8 9 10 11 12 VERIFICATION OF KVL AND KCL SERIES AND PARALLEL RESONANCE TIME RESPONSE OF RC SERIES CIRCUIT TWO PORT NETWORK PARAMETERS-Z.Y TWO PORT NETWORK PARAMETERS-ABCD AND H VERIFICATION OF SUPERPOSITION AND RECIPROCITY THEOREMS VERIFICATION OF MAXIMUM POWER TRANSFER THEOREMS THEVININ’S AND NORTON’S THEOREM MAGNETISATION CHARACTRISTICS OF DC SHUNT GENERATOR SWINBURNE’S TEST ON DC SHUNT MOTOR BRAKE TEST ON DC SHUNT MOTOR OC & SC TEST ON SINGLE PHASE TRANSFORMER *Regular experiment ----according to the syllabus/ Vignan Institute of Technology & Science Regular Experiment*/ Additional Experiment+ Remarks REGULAR REGULAR REGULAR REGULAR REGULAR REGULAR REGULAR REGULAR REGULAR REGULAR REGULAR REGULAR + Additional Experiments – Experiments other than syllabus II B.Tech 2nd Semester Page 256 . ***The End*** .
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