VerilogHDL

Verilog HDLCompiled from the Web Bil 361 Computer Architecture and Organization Introduction • • • • Hardware Description Language (HDL) Verilog is a useful and popular language Parallel not serial (Not like C language) Meaningful declaration – parameter, port name, module name, … • Case-sensitive Identifies – “Even” and “even” are different • Top-Down • Bottom-up Methodology Target Module 1 Module 2 Module 3 Basic Comp. Basic Comp. Basic Comp. Basic Comp. Basic Comp. Basic Comp. Design Flow • What functions are you want to program ? – Input and output • Specify the Input/Output signals • Separate the whole circuit into smaller ones – Each block has its own function / purpose • Connect all blocks/modules B1 B2 B3 . Verification Scenario • Use test bench file to verify your design Stimulus & Control Signal Response & Verification Test-Bench Module Monitor Signals . mux. or. adder. shifter… • Most important – Input and Output Module .What is a Module • Module is a block of circuit – Special function – and. Verilog .Module . input2. c). output1. endmodule . …. output2. y. b. endmodule – module adder(x.Module Declaration • module module_name (input1. …). … endmodule • Example – module mux2(a. z). • Nests – wire [k-1:0] B. • Integers − 4’d3.b} • Registers − reg [n-1:0] A. • Parameter − parameter size = 16. Data types [0:k-1]B C[1:0] = {a. • Preprocessor Directive − `define BEQ 4’b0100 No “=” . 6’h20 • Array − reg [8:0] ram [0:9]. 4’b0100. − wire [size-1:0] bus. Synthesizable Description • Can be used in your RTL codes `define parameter wire always if/else `include input reg assign case/casex module/endmodule output begin/end posedge/negedge . Un-synthesizable Description • Can not be used in your RTL codes! • Can be used in test bench Delay forever join deassign primitive initial wait event force Repeat Foke Time Relace . then a && b = 0 a || b = 1 . ^a = 1’b1.) − !A not A − A&&B A and B − A || B A or B • Example − assign a= 1. then &a = 1’b0. − assign b= 0.Synthesizable Operator • Binary (2 operands) – – – – – – & ~& | ~| ^ ~^ AND NAND OR NOR XOR XNOR • Logic (1 or 2 op. • Example – a = 4’b0010. assign a=b | c b = 4’b0011 c = 4’b0101 a = 4’b0111 . always @() begin a=b & c.Examples reg [3:0] a. end wire [3:0] a = b | c. • wire [3:0] a. assign a=b & c b = 4’b0011 c = 4’b0101 a = 4’b0001 • wire [3:0] a. B} = 5’b10110 . • Concatenate − A=2’b10. • Conditional − A = (condition) ? B : C.) • Shift ~inverse & and | or ^ XOR ~^ XNOR − << − >> shift left shift right • Example − a= 4’b0010. B=3’b110. a <<2 = 4’b1000.• Binary Bitwise – – – – – Synthesizable Operator (cont. a >>1 = 4’b0001. then {A. if b = 4’b0010. then a = 4’b1101. • Example – assign a= ~b. .Numbers • (size) ’ (base)(number) a = 1’b0. a = 20’b00001_11011_01011_01010. 5’d-4 (error) • Underscore (_) a = 20’b00001110110101101010. 4’b0001. 10’d700 • Negative number -8’d34 = (-34)10. 8’hFF. x. x y 0 1 z 1 0 y or g(z.Logic Gates Level • AND. x y x 0 0 1 1 y 0 1 0 1 z 0 0 0 1 z not g(y. y). x. y). x y x 0 0 1 1 y 0 1 0 1 z 0 1 1 1 z . Inverter. and OR gates and g(z. x). • Purpose Program 1 – A circuit can calculate the addition and subtraction of two 8 bits numbers – Three inputs and one output 8 a + Mux 8 If op = 1 then s=a+b s If op = 0 then s=a-b b 8 1 op . assign add = a+b. input [SIZE-1:0] a. op. parameter SIZE = 8. sub. sub b assign s = (op==ADD)? add : sub. endmodule op . Mux s assign sub = a-b. a + wire add. input op. add output [SIZE-1:0] s. b. s).b. Model declaration parameter ADD = 1’b1.) comment • /* A first program in Verilog */ module adder_or_subtract( a.Program 1 (cont. aendmodule . add sub input op. output [SIZE-1:0] s. parameter SIZE = 8. assign s = (op==ADD)? a+b : a-b. s). b.Program 1 (cont. input [SIZE-1:0] a.) module adder_or_subtract( a.b. op. parameter ADD = 1’b1. Program 2 • 1-to-2 De-multiplexer Select y0 0 D DMUX 1 D y0 y1 y1 Select 0 1 y0 D 0 y1 0 D Select . ) • // A deMux program in Verilog Single Col.y1. y1). comment module demux ( D.Program 2 (cont. wire y0. select. endmodule Select . y0. D y0 output y0. y1 assign y1 = select & D. input select. assign y0 = (~select) & D.y1. Model declaration input D. endmodule comment Model declaration g1 N g0 g2 y0 y1 Select . Select). and g2(y1. D. Select). not g0(N.y1.Program 2 (cont. D output y0.N. and g1(y0. N). input select. select.) • /* A deMux program in Verilog */ module demux ( D. input D.y1. y1). y0. wire y0. D. sub-module.Sub Module • Complex circuit • Many modules in a circuit • Module. sub-sub-module. … B1 B2 B3 . endmodule B1 B3 B2 . z). endmodule • module B2(a. d). ……………….. ………………. b. ………………. c).Example of Call Module • module B1(a. endmodule • module B3(x.. c. y.. b. w. f). …… • endmodule Example of Call Module (cont. b. ………………. f)... B1 b1(q. b. ………………. c. a.• module function(q.. b. d). B2 b2(a. e). • B3 b3(c. e. d. endmodule module B2(a. b. endmodule module B3(x. endmodule .) module B1(a. c). y. z). ………………. d. • ……. c). w. b.. B1 b1(w..Port Mapping Between Modules • # of ports • Width of each port • module function(a.. ……. e. ……………….. a. w. f). input q.d). output [1:0] f. q.. input [3:0] e. w. endmodule w q a q w e • module B1(q.c.. c). endmodule B1 f c .. . ) .) • Port name should match the name in sub_module • Prot connection – module_name( .port3_m1(w3_or_r3). .port1_m1(w1_or_r1).port1_m1(w1_or_r1).port4_m1(w4_or_r4).port4_m1(w4_or_r4). . .port2_m1(w2_or_r2). . . ) – module_name( . .port2_m1(w2_or_r2).port3_m1(w3_or_r3).Port Mapping Between Modules (cont. .. input q... . a.. input [3:0] e... endmodule q w a q w e B1 f c .d).b..Connection Between Modules (cont... .f(c))...q(q)... f).. .. ……………….. e.. B1 b1(.e(a)... B1 b1(q... w.e(a).. B1 b1(...........c..w(w)..... endmodule • module B1(q. w.. .. w.... . .... output [1:0] f. .... ...) • Port connection • module function(a...f(c))..w(w).q(q). c). Reuse Module • Using the same module many times • Example – Constructing 4-bits adder with four 1-bit adder b3 a3 b2 a2 b1 a1 b0 a0 a [3:0] b [3:0] A c3 A c2 A c1 A 0 Adder s4 s3 s2 s1 s0 S [4:0] . cout). y. y. cout cin A output sum. sum assign sum = x ^ y ^ cin. sum} = x + y + cin. wire x. assign cout = (x & y) | (x & cin) | (y & cin). y.4-bits Adder • module Adder(x. endmodule y x . c. assign {cout. input x. cout. c. cin. sum. sum. cout. y[1]. Adder A4(x[3].) • module Adder4(x. sum[1]. y[2]. cin. s1 s0 endmodule . c3). c3.4-bists Adder (cont. sum[4]). wire [3:0] x. sum). c3. Adder A2(x[1]. output [4:0]sum. c1. c2. sum[0]. y. input [3:0]x. c1). y. input cin. wire [4:0] sum. Adder A3(x[2]. cin. y. sum[2]. c2. c2). wire cin. y[3]. y[0]. b3 a3 b2 a2 b1 a1 b0 a0 A c3 A c2 A c1 cin A s2 s4 s3 wire c1. Adder A1(x[0]. sum[3]. • Miss “ . ” symbol for the end of every statement • Mismatch between the number of port or the number of pins of some buses .Mistake • module and endmodule • begin and end • module(). not Module(). • Syntax – always @(event-expression) assignment or block Always Block • Level type – always @(a or b or c) • Edge type – always @(posedge clock) – always @(negedge clock) • if-else and case statement are only in always block • wire and reg . Example • wire a; reg b; always @(x or y or z) begin a <= x & y; error b <= x | z; correct end Program 2 Select • 1-to-2 De-multiplexer 0 y0 D DMUX 1 D y0 y1 y1 Select 0 1 y0 D 0 y1 0 D Select Program 2 (cont.) D Select • module demux ( D, select, y0, y1); input D, select; output y0,y1; y0 reg y0,y1; always @( D or select ) begin if( select == 1’b0) begin y0 = D; y1 = 1’b0; y1 end else begin y0 = 1’b0; y1 = D; end end endmodule Blocking and Non-blocking . ....... endcase .......... case (state) 2’b00: ...................... end • reg [1:0] state...... default: ....... 2’b10: ................. end else if (condition 2) begin .. end else begin ... 2’b01: .............If-else and case • If (condition 1) begin . 2’b11: ............. end wire out. assign out = (sel)? a : b. always @(sel or a or b) begin if(sel == 1’b1) out = a.if statement • Like C language • Only in always block reg out. else out = b. . 2’b10 : out <= c. 2’b01 : out <= b. endcase end .Using of case and casex • Multiplexer or selection • Inside always block • All possible condition a b c d Sel [1:0] out always @(sel or a or b or c or d) begin case (sel[1:0] ) 2’b00 : out <= a. 2’b11 : out <= d. 3’b100 : out <= c. endcase end always @(sel or a or b or c or d) begin casex (sel[2:0] ) 3’b011 : out <= a. 3’b00x : out <= b. endcasex end All others Sel [1:0] a b c d Sel [2:0] out .) a b c out always @(sel or a or b or c or d) begin case (sel[1:0] ) 2’b00.Using of case and casex (cont. 2’b01 : out <= b. default : out <= d. 2’b10 : out <= c. 2’b11 : out <= a. Delay and Critical Path • Each gate and wire may cause delay of circuit • Longest path of the circuit is the critical path – Speed of whole circuit • Shorten the critical path can speedup the circuit • Input data rate higher than the speed of circuit may cause some problems . • 5 inputs adder a b Critical Path Example Z = (a + b) + (c + d) + e a b + c + Three adders e e + + Z Z d –Z=a+b+c+d+e + c + d + Four adders + . Test-bench • Input data of the circuit • All inputs of original circuit are assigned “reg” – Store data • All outputs of original circuit are assigned “wire” • Assign inputs in different time • Define time scale . y. wire [4:0] sum. cin. . Initialization adder4 add(. y = 4’d5. sum=13. . In 10ns x=3. end In 15ns x=3. y=5. y=10. y. endmodule module Adder4(x.Test-bench Example • `timescale 1ns/10ps module Adder_testbench. . sum=3. cin=1’b0. y = 4’d0. sum). #10 x = 4’d3. reg cin. In 25ns x=1. #10 x = 4’d1. sum=6. reg [3:0] x. #5 y = 4’d10. .sum(sum)). initial begin #0 x = 4’d0.x(x).y(y).cin(cin). y=0. d. end 46 wire c. d. for reg c. . assign d = c |b.Structural Vs Procedural Structural • textual description of circuit • • order does not matter • • Starts with assign statements • • Harder to code • Need to work out logic Procedural Think like C code Order of statements are important Starts with initial or always statement • Easy to code • Can use case. assign d = c |b. assign c =a & b. if. always@ (a or b or c) begin assign c =a & b. Q[0] Q[1] Q[2] y[0] y[1] Q[3] 47 . assign Q[0]=(~y[1])&(~y[0]). 2’b10: Q[2]=1. case(y) begin 2’b00: Q[0]=1. endcase end Structural wire [3:0]Q.Structural Vs Procedural Procedural reg [3:0] Q. wire [1:0] y. Q[1]=(~y[1])&y[0]. Q[2]=y[1]&(~y[0]). wire [1:0]y. always@(y) begin Q=4’b0000. Q[3]=y[1]&y[0]. 2’b01: Q[1]=1. 2’b11: Q[3]=1. latches and registers Do not mix both assignments in one procedure 48 .Blocking Vs Non-Blocking Blocking <variable> = <statement> Similar to C code The next assignment waits until the present one is finished Used for combinational logic Non-blocking <variable> <= <statement> The inputs are stored once the procedure is triggered Statements are executed in parallel Used for flip-flops. #1 b<=0. did not wait e<=b 49 . // grabbed the old b f=e. e<=b.Blocking Vs Non-Blocking Initial begin #1 e=2. #1 b=1. // used old e=2. Component Inference . a<=b&c. end B D Q clk CLK A 51 .Flip-Flops always@(posedge clk) begin a<=b. D Flip-Flop with Asynchronous Reset always@(posedge clk or negedge rst) begin if (!rst) a<=0. end rst B D clr Q clk CLK A 52 . else a<=b. D Flip-flop with Synchronous reset and Enable always@(posedge clk) begin if (rst) a<=0. else if (enable) a<=b. end 53 . else begin Q <=Q << 1. always@(posedge clk or posedge rset ) begin if (rset) Q<=0. Q[0]<=Q[3]. end 54 .Shift Registers reg[3:0] Q. Method 2 always@(select or b or c) begin if(select) a=b. 1’b0: a=c.Multiplexers Method 1 assign a = (select ? b : c). endcase 55 0 1 SL select . end Method 2b case(select) 1’b1: a=b. else a=c. wire enable. else if (enable) count<=count+1.Counters reg [7:0] count. end 56 . always@(posedge clk or negedge rst) begin if (rst) count<=0. Avoiding Unwanted Latches Latches are BAD . z=0.y=0.Rule #1 If the procedure has several paths. always @(. end end 58 .. y=0. y=3. else z=4. begin if (a) begin x=2. z=0.. elseif (b) y=3. Later on different values can overwrite those values.. if (a) x=2. y=0. End • Method2: Be sure every branch of every if and case generate every output always @(.. end else begin x=0. begin x=0. end elseif (b) begin x=0. every path must evaluate all outputs • Method1: Set all outputs to some value at the start of the procedure. z=0. z=4. end • Branch controlling variables: Be sure every branch of every if and case generate every output always @(a or b) begin if (a) begin x=2. y=0. y=3. z=0. end else begin x=0. always @(a or b or c or x or y) begin x=a.Rule #2 All inputs used in the procedure must appear in the trigger list • Right-hand side variables: Except variables both calculated and used in the procedure. w=x+y. y=b. z=0. end end 59 . z=c. end elseif (b) begin x=0. z=4. y=0. else next_state=reset.Rule #3 All possible inputs used control statements must be covered • End all case statements with the default case whether you need it or not. 60 .. default: next_state = reset. endcase • Do not forget the self loops in your state graph if(a|b&c) next_state=S1. elseif(c&d) next_state=S2.. case(state) . Finite State Machines . nxt_st. // NEXT STATE CALCULATIONS always@(state or inputs or .... end // OUTPUT CALCULATIONS output= f(state.S2=2.S1=1... inputs) 62 .. // state definitions parameter reset=0. … end // REGISTER DEFINITION always@(posedge clk) begin state<=next_state.) begin … next_state= .S3=3.Standard Form for a Verilog FSM // state flip-flops reg [2:0] state. endcase end endmodule 63 . S7: nxt_st=S0.S1=1. else nxt_st=S2. S1: if(x) nxt_st=S3. else nxt_st=S7.S3=3. // NEXT STATE CALCULATIONS always @(state or x) begin case (state) S0: if(x) nxt_st=S1. S2: if(x) nxt_st=S0.S7=7 // REGISTER DEFINITION always @(posedge clk) begin state<=nxt_st. // state definition parameter S0=0. output z. S3: if(x) nxt_st=S2. x. // state flip-flops reg [2:0] state. z) input clk. x. else nxt_st=S7.Example module myFSM (clk.S2=2. end // OUTPUTCALCULATIONS assign z = (state==S7). default: nxt_st = S0. else nxt_st=S0. nxt_st. Test Benches . .par_2. • Writing to a File: $fopen.par_1..).par_2...System tasks • Used to generate input and output during simulation.).par_1. z). $monitor(“format_string”.. $fmonitor and $fwrite • Random number generator: $random (seed) • Query current simulation time: $time 65 . $fdisplay.. • Display Selected Variables: $display (“format_string”. Start with $ sign. Example: $display(“Output z: %b”. Implement the system tasks to view the results 4. Specify when to end the simulation. Send test vectors 3. Approach 1.Test Benches Overview 1. Simulate input vectors 3. Initialize all inputs 2. Set the clk signal 66 . Invoke the verilog under design 2. #1000 $finish. x. z). rst. module my_fsm_tb. reg clk. z). x. rst=0. wire z. rst.Example ‘timescale1 ns /100 ps // timeunit =1ns. $display(“Output z: %b”. /* 10MHz clock (50*1ns*2) with 50% duty-cycle */ /****SPECIFY THE INPUT WAVEFORM x ****/ Initial begin #1 x=0. /**** DESIGN TO SIMULATE (my_fsm) INSTANTIATION ****/ myfsm dut1(clk.*/ #200 rst=0. @(posedge clk) x=1. it will not stop end endmodule 67 . /****RESET AND CLOCK SECTION****/ Initial begin clk=0. #100 x=0. #1rst=1. #400 x=1. /*The delay gives rst a posedge for sure. //Deactivate reset after two clock cycles +1ns*/ end always #50clk=~clk. precision=1/10ns. //stop simulation //without this. Synthesizable Description • Can be used in your RTL codes `define parameter wire always if/else `include input reg assign case/casex module/endmodule output begin/end posedge/negedge 68 . Un-synthesizable Description • Can not be used in your RTL codes! • Can be used in test bench Delay (#) forever join deassign primitive initial wait event force Repeat Foke Time Relace 69 . • Default value is “X” (unknown) 70 . • Registers are used extensively in behavior modeling and in applying test patterns.Register • Registers represent abstract storage elements. • A register holds its value until a new value is assigned to it. end A = 3. C = 3. B = 3. C = B.Blocking and Non-blocking • Blocking assignments are executed sequentially. B = 4. much like a program in C language • Non-blocking assignments evaluate the right-hand side. begin B <= A. C <= B. end A = 3. B = 3. and make the assignments when all righthand have been evaluated Initial values: begin B = A. Blocking assignments “ = “ Non-Blocking assignments “ <= “ 71 . C = 4. C = 5. A = 3. 72 . clock. end end endmodule “<=” non-blocking assignment Use non-blocking assignments in sequential circuits. reset. else begin Reg[0] <= in. reg [3:0] R. out). R[1] R[2] R[3] out always @(posedge clock) begin if (!reset) Reg[3:0] <= 4’d0. Reg[2] <= Reg[1].4-bits Shift Register Codes module shifter (in. assign out = R[3]. reset. Reg[3] <= Reg[2]. in R[0] output out. input in. Reg[1] <= Reg[0]. clock. else begin if (enable) begin if (out == 4’d15) out[3:0] <= 4’d0. end end end Synchronous Reset 73 . else out <= out. enable. reg [3:0] out. else out <= out + 1’b1. clock.4-bit Up Counter input reset. output [3:0] out. always @(posedge clock) begin if (reset) out[3:0] <= 4’d0. else out <= out . end end end end 74 .1’b1.4-bit Up-Down Counter always @(posedge clk) begin if (reset) out[2:0] = 3’d0. end else begin if (out == 4’d0) out[3:0]<=4’d15. else begin if (enable) begin if (select) begin if (out == 4’d15) out[3:0]<=4’d0. else out <= out + 1’b1. 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