FIR FILTER DESIGN USING VERILOGFIR filters are is widely used in different applications such as biomedical, communication and control due to its easily implementation, stability and best performance. Its simplicity makes it attractive for many applications where it is need to minimize computational requirements. Filters play an important role for removal of unwanted signal or noise from original input signal by removing the selected frequencies from incoming signal. They became much popular due to the increase of the digital signal processing. Comparison between FIR and IIR Filters The non recursive (FIR) and recursive (IIR) filters have different characteristics for numbers of applications. The non recursive filters are chosen due to its best performance of numerical operations, differentiation and integration. The table 2.1 below shows the comparison between FIR and IIR filters. IIR More Efficient Analog Equivalent FIR Less Efficient No Analog Equivalent assign m4=d13>>h3.d13).d2. input [7:0]x.m2. wire [7:0]d1.dataout).May Be Unstable Always Stable Non-Linear Phase Response Linear Phase Response No Efficiency Gained by Decimation Decimation Increases Efficiency VERILOG CODE FOR FIR FILTER // main module FIR module filterfir(clk.d11. dff u2(clk. parameter h4=3'b001. input clk. assign d2=d1+m3. assign m3=d12>>h2.rst.m4.d12. parameter h0=3'b101. dff u4(clk.rst.d11).rst. parameter h3=3'b010. wire [7:0]d11.rst. assign m2=d11>>h1. wire [7:0]m1. assign m5=d14>>h4.rst. parameter h1=3'b100. dff u8(clk. dff u6(clk. .d3.d14). assign d1=m1+m2.d13.m3.x.m5.d14.d13. output [9:0]dataout. assign m1=x>>h0.rst.x. parameter h2=3'b011.d12.d12). assign d3=d2+m4. rst. reg [7:0]q. end end endmodule //////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 22:07:00 01/29/2014 // Design Name: filterfir // Module Name: D:/fft/floating_mul/tst.// sub module d flipflop input clk.rst. output [7:0]q.assign dataout=d3+m5.q).d. always@(posedge clk) begin if(rst==1) begin q=0. end else begin q=d.v // Project Name: floating_mul // Target Device: // Tool versions: // Description: // // Verilog Test Fixture created by ISE for module: filterfir // // Dependencies: // // Revision: . input [7:0]d. endmodule module dff(clk. // Revision 0. . reg [7:0] x. x = 8'd16. #100.dataout(dataout) ). x = 8'd15.File Created // Additional Comments: // //////////////////////////////////////////////////////////////////////////////// module tst. #100.rst(rst). #100. // Instantiate the Unit Under Test (UUT) filterfir uut ( .01 . reg rst.x(x). initial begin // Initialize Inputs clk = 0. #100. x = 8'd12. . rst = 1. x = 8'd5. x = 8'd10. // Outputs wire [9:0] dataout. // Inputs reg clk. x = 0. rst = 0. rst = 0. #100. #100. . .clk(clk). coeffs[11]=1.result(toAdd[i])). coeffs[10]=-3656. coeffs[7]=4. end endgenerate . generate for (i=0. input wire[15:0] input_sample.dataa(coeffs[i]). . coeffs[3]=3. output reg[15:0] output_sample). reg [15:0] holderBefore[12:0]. end endmodule module fir_filter( input clock. end genvar i. input reset. coeffs[12]=6375. i=i+1) begin: mult multiplier mult1( . end always begin #50 clk=~clk. coeffs[8]=4171. i<N. parameter N = 13. reg signed[15:0] coeffs[12:0]. . coeffs[4]=4171. coeffs[6]=28404. wire [15:0] toAdd[12:0]. coeffs[2]=-3656. coeffs[9]=3.datab(holderBefore[i]). always @(*) begin coeffs[0]=6375. coeffs[5]=4. coeffs[1]=1.#100. holderBefore[4] <= 0. holderBefore[6] <= 0. holderBefore[0] <= 0. holderBefore[11] <= 0. holderBefore[3] <= holderBefore[2]. holderBefore[0] <= input_sample. holderBefore[7] <= 0. end else begin holderBefore[12] <= holderBefore[11]. output_sample <= (input_sample + toAdd[0] + toAdd[1] + toAdd[2] + toAdd[3] + toAdd[4] + toAdd[5] + toAdd[6] + toAdd[7] + toAdd[8] + toAdd[9] + toAdd[10] + toAdd[11] + toAdd[12]). holderBefore[3] <= 0. holderBefore[1] <= holderBefore[0].always @(posedge clock or posedge reset) begin if(reset) begin holderBefore[12] <= 0. holderBefore[4] <= holderBefore[3]. holderBefore[8] <= holderBefore[7]. holderBefore[11] <= holderBefore[10]. holderBefore[5] <= 0. holderBefore[2] <= 0. holderBefore[9] <= holderBefore[8]. holderBefore[10] <= holderBefore[9]. holderBefore[2] <= holderBefore[1]. holderBefore[5] <= holderBefore[4]. holderBefore[9] <= 0. end end endmodule . output_sample <= 0. holderBefore[8] <= 0. holderBefore[6] <= holderBefore[5]. holderBefore[10] <= 0. holderBefore[1] <= 0. holderBefore[7] <= holderBefore[6].