UVMRegisters

UVM UpdateRegister Package Agenda • • • • Introduction to UVM UVM Register Model Our experience with using Register Model Register Model Generator 2 Verification Methodologies • History – February 2011 Accellera releases UVM 1.0 – Recently, June 2011 UVM 1.1 is released 3 proven industry foundations – Engineers worldwide can write thorough and reusable test environments 4 .Introduction to UVM • Universal Verification Methodology – A methodology and a class library for building Advanced Reusable Verification Components • Relies on strong. • Test Class • Contains Testbench • Reusable components with different config Source: Accellera DAC Presentation 5 .UVM Environment • Module top () as top level element. What’s in UVM ? • • • • • • • • Base Classes Factory Classes Phasing Configuration TLM Sequences & Sequencers Message Reporting Register Model 6 . Base Classes • Facilitate the design of modular. run. connect. etc. transactions 7 . scalable.build. reusable verification environments • The basic building blocks for all environments are components and the transactions they use to communicate establish structal hierarchy phase-. – Only one instance of the factory is present in a given simulation class uvm_component_registry #( type T = uvm_component.Factory Classes • Manufacture (create) UVM objects and components. string Tname = "<unknown>" ) extends uvm_object_wrapper 8 . Phasing Several new runtime phases in parallel with run_phase() By default. all components must allow all other components to complete a phase before all components move to next phase Source: Accellera DAC Presentation 9 . • uvm_resource_db • uvm_config_db – Configuration mechanism advantages: • Wild cards and regular expressions allow configuration of multiple attributes with a single command target Initiator • Run-time configuration support • TLM – Unidirectional put/get interfaces – TLM 2. access to store or receive from database.0 • Well-defined completion semantics put Initiator target get 10 .Configuration & TLM • Configuration – The configuration & resource classes. randomized.Sequencers & Sequences • Sequences – User-defined procedures that generate multiple uvm_sequence_item-based transactions – Reused. extended. and combined sequentially and hierarchically • Sequencers – Arbiter for controlling transaction flow – pull or push semantic between Driver 11 . 12 . and time `uvm_info("PKT".Message Reporting • Messages print trace information with advantages over $display: – Aware of its hierarchy/scope in testbench – Allows filtering based on hierarchy. verbosity. "Packet Sent“. UVM_LOW). Agenda • • • • Introduction to UVM UVM Register Model Our experience with using Register Model Register Model Generator 13 . Register Model • Object oriented Shadow Model for Registers and Memories in DUT • Components – Field – Register – Register File – Memory – Block 14 . . F10 F11 F6 F8 F7 F9 F5 F6 F7 F8 F9 F5 F6 F7 F8 F9 . . F5 F6 F7 F8 F9 ARR[n] RF0 [0] RF1 [0] RF0 [1] RF1 [1] RF0 [m] RF1 [m] MEM0 15 uvm_reg_block MEM_0 BLOCK F1 F2 .Register Model BLK_1 R0 F1 F2 F3 F4 F10 F11 F10 F11 Registers uvm_reg R0 F1 F2 F10 F10 F3 F11 F11 . . . F5 F6 F7 uvm_mem F8 F9 MEM_0 Memory MEM_0 . . . F7 F9 F4 R0 R1 ARR[0] ARR[1] . . . F10 F5 F6 F8 F11 F7 F9 F6 F8 . . . R0 BLK_n F3 F4 F11 uvm_reg_file F5 Register File Array F5 F10 F10 F11 . F10 F11 F5 F6 F7 F8 F9 F5 F6 F7 Register Arrays F8 F9 . . Register Package Usage Read-Write Generator Adapter Bus Specific R/W Backdoor Bus Agent 16 . Mirroring • Register model mirrors content of registers in DUT – Updated on read() and write() – “Scoreboard” for checking – Memories : • uvm_mem::peek() • uvm_mem::poke() R0 R1 Monitor Monitor Scoreboard DUT R0.).. . .read (.). . R1. Sequence R0 Sequencer Driver APB R1 17 .write (. .. . ..write (. R1. Back-door • Front Door: Normal bus access • Back Door – Access RTL directly in zero-time • Load memory – Hardware writable • Counter. status flags Scoreboard Monitor R0 R1 Monitor – Must define “hdl_path” • Generator-specific DUT R0..read (.).). . . .Front-door vs. . Sequence R0 Sequencer Driver APB R1 18 . Agenda • • • • Introduction to UVM UVM Register Model Our experience with using Register Model Register Model Generator 19 . clear_hdl_path().HDL Path HDL path components are specified using the following methods: a) uvm_reg_block::configure() and uvm_reg_block::add_hdl_path() b) uvm_reg_file::configure() and uvm_reg_file::add_hdl_path() c) uvm_reg::configure() and uvm_reg::add_hdl_path_slice() d) uvm_mem::configure() and uvm_mem::add_hdl_path_slice() CODE: R0.add_hdl_path_slice("dut. Clear HDL paths if mentioned above in configure() R0 R1 Monitor array name And For Register Arrays: DUT Sequence R0 R1 Sequencer Driver foreach (reg_array[i]) begin APB reg[i].clear_hdl_path(). reg[i]. end 20 . R1. R1. R0. 0.R0". 32). 0. 0.add_hdl_path_slice($sformatf(“DUT_ARRAY[%0x]". 64). i).R1". 32).add_hdl_path_slice("dut.clear_hdl_path(). 4. APB_map.Mapping in Block byte-width of the bus Base Address APB_map = create_map("APB".add_reg (R1. ‘h0).add_reg (R1. 8. ‘h0. UVM_LITTLE_ENDIAN. R0 Byte addressing: consecutive addresses refer are 1 byte apart R0 . ‘h4).add_reg (R0.32 bit R1 . endianess APB_map = create_map("APB". APB_map. 1). ‘h0. ‘h4).add_reg (R0.64 bit Monitor If (Byte addressing == 0) then Bus width = Max size of Register in Register Model Sequence R1 DUT R0 Sequencer Driver APB R1 21 . APB_map_map. UVM_LITTLE_ENDIAN. 0). ‘h0). APB_map_map. UVM_CVR_ADDR_MAP Coverage models for bits read or written UVM_CVR_ALL in registers. – To enable: MEM_0 22 . )). R1 7 6 5 4 . – Can be large. F1 F2 Coverage models for addresses read or written in an address map.0x030 3 2 1 0 0x008 F4 0x000 • Not instantiated by default uvm_reg::include_coverage (”*”. Instantiate only when needed. R2 R3 F5 F8 F6 F7 F9 0x014 0x015 0x020 . . UVM_CVR_FIELD_VALS Coverage models for UVM_CVR_REG_BITS values of fields. . Block R0 F3 . (UVM_CVR_REG_BITS + .Coverage • For all elements except in Register File • Pre-defined Functional Coverage Type Identifiers – – – – – UVM_NO_COVERAGE No coverage models. All coverage models. bins { ['h18 : endgroup} } endgroupblock_reg1 : coverpoint m_offset { function new(string name = "my_reg_R1").sample().m_offset { block_MEM0 : coverpoint{[6:8]}. .value[13:0]. F10 F5 F8 F5 F6 F8 . end cg_vals. localuvm_reg_field F1. bins F2: coverpoint F2. uvm_reg_map map). . bit is_read. .value[6:0]. endfunction super. `uvm_object_utils(block_MEM0) if (has_coverage(UVM_CVR_FIELD_VALS)) virtual function void sample(uvm_reg_addr_t cg_vals. local uvm_reg_addr_t m_offset. bins hit = { ‘h4 }. m_offset. cg_addr = void if (has_coverage(UVM_CVR_ADDR_MAP)) uvm_reg_data_t byte_en.sample(uvm_reg_data_t data. build_coverage( UVM_CVR_FIELD_VALS)). bins FIRST = {[0:2]}. virtual functionnew(). covergroup cg_addr. function}new(string name = "block_mem_reg"). function new(string name = "block_block"). . cg_addr. m_offset = offset. uvm_reg_map map).sample(). . bins THIRD = F3: coverpointhit = FOURTH = {[9:11]}. 32. virtual functionoffset. ifm_offset = void sample_values(). uvm_reg_addr_t randblock_R1 R1. .(get_coverage(UVM_CVR_ADDR_MAP)) begin if bit is_read. endfunction = new().value[19:0]. if (has_coverage(UVM_CVR_ADDR_MAP)) build_coverage(UVM_CVR_ADDR_MAP)). block_MEM0 extends uvm_mem. endfunction . . SECOND = F1: coverpoint F1. offset. rand uvm_reg_field F3. endclass : block_block endclass Register R0 F1 F2 F10 F10 F3 F11 F11 . block_block extends uvm_reg_block.sample(). uvm_reg_field F2. build_coverage(UVM_CVR_ADDR_MAP)). F6 F11 F7 F9 F7 F9 R0 R1 ARR[0] ARR[1] Register Arrays ARR[n] RF0 [0] RF1 [0] RF0 [1] RF1 [1] RF0 [m] RF1 [m] MEM0 23 Register File F5 F6 F8 F7 F9 Memory MEM_0 .Coverage class my_reg_R1 extends uvm_reg.sample().sample_values(). QUADRANTS : coverpoint m_offset { covergroup cg_vals. 32.new(name. virtual function void sample(uvm_reg_addr_t endfunction offset. end(get_coverage(UVM_CVR_FIELD_VALS)) ifcg_addr. "RW". cg_addr bit is_read. super.begin (get_coverage(UVM_CVR_ADDR_MAP)) super. covergroup cg_addr.new(name.new(name. bins F3. .{[3:5]}. endgroup super. endfunction uvm_reg_map map). 'h47] }. 'h30. randblock_MEM0 MEM0. regmodel. "NO_REG_TESTS". 1. Sequence ignores this Register SEQUENCES uvm_reg_hw_reset_seq uvm_reg_bit_bash_seq uvm_reg_access_seq uvm_mem_walk_seq uvm_mem_access_seq uvm_reg_mem_built_in_seq uvm_reg_mem_hdl_paths_seq ATTRIBUTES NO_REG_TESTS NO_MEM_TESTS NO_REG_HW_RESET_TEST NO_REG_BIT_BASH_TEST NO_REG_ACCESS_TEST NO_MEM_WALK_TEST NO_MEM_ACCESS_TEST 24 .Pre-Defined Sequences • Factory given Sequences • hdl_path Access needed uvm_resource_db#(bit)::set({"REG::". this).blk.r0.get_full_name()}. configure(IND_IDX. null). Not in the Register Map . null). virtual function build(). 4). . endclass data 25 . Indirect Register Array (External) INDIRECT_REG[0] INDIRECT_REG[1] INDIRECT_REG[2] IND_IDX [0:7] 0x00 IND_DATA 0x04 . 0). default_map. ind_reg INDIRECT_REG[256]. default_map. `ifdef INCA begin uvm_reg r[256]. .add_reg(IND_IDX. default_map = create_map(““. . this. UVM_BIG_ENDIAN). INDIRECT_REG[255] INDIRECT_REG[256] IND_DATA. end `else IND_DATA. 4. ind_idx_reg IND_IDX.add_reg(IND_DATA. INDIRECT_REG . `endif . . r. ind_data_reg IND_DATA.Special Registers • Pre-Defined Registers – Indirect Indexed Registers class my_blk extends uvm_reg_block. my_blk foreach(INDIRECT_REG[i]) r[i]=INDIRECT_REG [i]. . this. 0.configure(IND_IDX. 0. F1. "RO". – Fields in aliased registers will have different behavior depending on the address used to access them. alias_RaRb RaRb. . . . endclass begin class my_reg_Rb extends uvm_reg. . . RaRb = . . uvm_reg_field F1. endfunction end endclass endfunction endclass R0 F1 F2 F3 F4 Ra F10 F10 ‘h100 F11 F11 Rb F10 Aliased Registers ‘h200 F11 26 . alias_RaRb::type_id::create("RaRb".configure(this. . rand my_reg_Ra Ra. . . . 0. "RW". class my_blk extends uvm_reg_block. F1. . endfunction default_map. . RaRb.configure(Ra.. – Accessible from multiple addresses in the same address map. .configure(this. . default_map.Special Registers • Aliased Registers cont.get_full_name()). ‘h0200). ‘h0100). function build(). virtual rand uvm_reg_field F1. rand class my_reg_Ra extends uvm_reg. Rb).add_reg(Rb. ..).add_reg(Ra. 8. .). my_reg_Rb Rb. 8. . endfunction: new `uvm_object_utils(fifo_reg) endclass • RO and WO Sharing the Same Address default_map. super.UVM_NO_COVERAGE).8. 'h100.add_reg(R1. function new(string name = "fifo_reg"). endfunction : build 27 .add_reg(W1.32. default_map.Special Registers • FIFO class fifo_reg extends uvm_reg_fifo.new(name. 'h100. "RO"). "WO"). Agenda • • • • Introduction to UVM UVM Register Model Our experience with using Register Model Register Model Generator 28 . Generation of Register Model GENERATOR EDA Vendors 29 . Why use a Generated Register Model • Create correct-by-construction models – Coverage types – Constraints – Backdoor access – Special register • Sync with specification • Ease of use 30 . Free UVM Register tools • Cadence : RGM – IP-XACT to UVM • Synopsys : Ralgen – RALF to UVM • Agnisys : IDSExcel – Excel to UVM 31 . Summary • UVM register package must be used for any serious SoC verification • Not using a register model is painful • Not using a generated register model is very painful • Any questions? 32 . 33 . 34 . • Three basic operations for creating components: 1. Designing components to use the factory to create objects or components 3. both within and outside components 35 . . Configuring the factory with type and instance overrides. Registering objects and components types with the factory 2.UVM: Factory Classes cont. Write • Checking Monitor Register Model Monitor Scoreboard DUT R0.). Sequence R0 Sequencer Driver APB R1 36 .read (. . . R1..Register Model Usage • Physical Interface • Read. .write (.. .). . Introspection 37 . endclass . rand my_reg_Ra Ra. endfunction Rb = reg_Rb::type_id::create("Rb".get_full_name()). class write_also_to_F extends uvm_reg_cbs.predict(value. Ra ‘h100 protected reg_Rb m_Rb. .Special Registers • Aliased Registers cont. UVM_PREDICT_WRITE. endclass F2F = new(Rb. RaRb.get_full_name()). . alias_RaRb RaRb. m_toF = toF. -1. endfunction: new RaRb = alias_RaRb::type_id::create("RaRb". . 4. . Rb). function new(uvm_reg_field toF).. endfunction m_Rb = Rb. void'(m_toF. . uvm_path_e path.F1. virtual function void post_predict(uvm_reg_field fld. endfunction class my_blk extends uvm_reg_block. uvm_reg_map map). ‘h0200). uvm_reg_data_t value.. default_map = create_map("". begin Rb ‘h200 super. if (kind != UVM_PREDICT_WRITE) return.add_reg(Rb. ‘h0100).configure(Ra. write_also_to_F F2F. rand my_reg_Rb Rb. local uvm_reg_field m_toF. map)).F1). UVM_BIG_ENDIAN). function void configure(reg_Ra Ra. protected reg_Ra m_Ra. class alias_RaRb extends uvm_object.add_reg(Ra. reg_Rb Rb). end m_Ra = Ra. path. endfunction : configure endclass : alias_RaRb R0 F1 F2 F3 F4 F10 F11 F10 F11 F10 F11 38 .get_full_name()). virtual function build().new(name). uvm_reg_field_cb::add(Ra. default_map. default_map. 0.. . uvm_predict_e kind. Aliased `uvm_object_utils(alias_RaRb) Registers function new(string name = "alias_RaRb"). F2F). Ra = reg_Ra::type_id::create("Ra".