Types of Operating System Schedulers

Types of operating system schedulers Operating systems may feature up to 3 distinct types of schedulers: a long-term scheduler (alsoknown as an admission scheduler or high-level scheduler), a mid-term or medium-term scheduler and a short-term scheduler . The names suggest the relative frequency with which these functions are performed. [edit] Long-term scheduler The long-term, or admission, scheduler decides which jobs or processes are to be admitted to the ready queue; that is, when an attempt is made to execute a program, its admission to the set of currently executing processes is either authorized or delayed by the long-term scheduler. Thus, this scheduler dictates what processes are to run on a system, and the degree of concurrency to be supported at any one time - ie: whether a high or low amount of processes are to be executed concurrently, and how the split between IO intensive and CPU intensive processes is to be handled. In modern OS's, this is used to make sure that real time processes get enough CPU time to finish their tasks. Without proper real time scheduling, modern GUI interfaces would seem sluggish. [Stallings, 399]. Long-term scheduling is also important in large-scale systems such as batch processing systems, computer clusters, supercomputers and render farms. In these cases, special purpose job scheduler software is typically used to assist these functions, in addition to any underlying admission scheduling support in the operating system. [edit] Mid-term scheduler The mid-term scheduler temporarily removes processes from main memory and places them on secondary memory (such as a disk drive) or vice versa. This is commonly referred to as "swapping out" or "swapping in" (also incorrectly as "paging out" or "paging in"). The mid-term scheduler may decide to swap out a process which has not been active for some time, or a process which has a low priority, or a process which is page faulting frequently, or a process which is taking up a large amount of memory in order to free up main memory for other processes, swapping the process back in later when more memory is available, or when the process has been unblocked and is no longer waiting for a resource. [Stallings, 396] [Stallings, 370] In many systems today (those that support mapping virtual address space to secondary storage other than the swap file), the mid-term scheduler may actually perform the role of the long-term scheduler, by treating binaries as "swapped out processes" upon their execution. In this way, when a segment of the binary is required it can be swapped in on demand, or "lazy loaded". [Stallings, 394] [edit] Short-term scheduler The short-term scheduler (also known as the CPU scheduler) decides which of the ready, in-memory processes are to be executed (allocated a CPU) next following a clock interrupt, an IO interrupt, an operating system call or another form of signal. Thus the short-term scheduler makes scheduling decisions much more frequently than the long-term or mid-term schedulers - a scheduling decision will at a minimum have to be made after every time slice, and these are very short. This scheduler can be preemptive, implying that it is capable of forcibly removing processes from a CPU when it decides to allocate that CPU to another process, or non-preemptive (also known as "voluntary" or "cooperative"), in which case the scheduler is unable to "force" processes off the CPU. [Stallings, 396]. Q. 1. Briefly explain instruction format. Ans. An instruction contain number of bits in the so that it is being to perform specific operation. Generally an instruction is divided into three fields Addreg mode: It specifies that how the operands are accessed in an instruction. Operation code (O):This field specifies the operation that is performed in the operand. Operand : It specifies the data on which operation is performed. Q. 2.What is instruction pipelining? Ans. An instruction pipeline reads Consecutive instruction from memory previous instructions are being executed in other segments Pipeline processing can occur not only in data stream but in the instruction stream as well. This causes the instruction fetch and execute phases to overlap and perform simultaneous.The pipeline must be It uses wide range of instruction.emptied and all instructions that have been read from memory after the branch instruction must be discarded. It uses the micro programmed control unit when RISC machines mostly uses hardwired control unit. RISC machine use the simple addressing mode. Logic for implementation of these instructions is simple because instruction set is small in RISC machine. It uses high level statent.It uses hardwired control unit. It is easy to understand for human being. Difference between RISC and CISC are given below: 1.RISC : It means Reduced instruction set computing. 2. Q. These instructions produce more efficient result.RISC requires fewer and limited instructions . Q.4 Differentiate between RISC and CISC. CISC: It means complex instruction set computing. Ans. 3. 3 What is RISC and CISC? Ans.It means Reduced Instruction set computing. SPARC from SO p-ticrosoft ycm.Example of RISC processors are BM2PO. The concept of pipeline can be same as the water tab. CISC: It means complex instruction set computing. ClSC requires wide range of instructions. Pipelining is the concept of overlapping of multiple instructions during execution time.RISC. . Further assume that each task can be divided into four subtasks so that each of these subtasks are executed by one state of hardware. These instructions produce more efficient results.. What is super pipelining? Ans. —. These subtasks of two or more different tasks are executed parallel by hardware unit. Q. power PC and PA. Suppose there are five tasks to be executed. It uses micro programmed control unit. The example of CISC processor are IBM Z and gital equipment corporation VAX computer. Pipeline splits one task into multiple subtasks.4. The execution of these five tasks is super pipe thing. The amount of water coming out of tab in equal to amount of water enters at pipe of tab.5. Ans. RISC processor or systems are more popular than CISC due to better performance. RISC machines uses load and store. Micro programming is the concept for generating control signals using programs. These programs are called micro programs which are designed in control unit.6 Explain about RISC processors. . Explain micro programmed control.7. Ans. It has fewer and limited number instruction Earlier RISC processors do not have port for floating-point data But the current technology processors suit the pU poiniata type. Q. It consume less power and are having high performance. That means only load and store instruction can access the memory. This is the concept controlling the sequence of micro operation computer. Micro programming is the latest software concept used in designing the control Unit. It mostly use the hardwired control unit.This instructions operate on registers. The operations are performed on data to redin side the registers are called micro operations.Q.RISC means Reduced instruction computing. Q 9 Write any six characteristics of RISC. . Explain pipelining in CPU design? Ans.Q. or Explain the important features of RISC based system architecture. The result obtained from the computation in each segment is transferred to next segment in the pipeline. with each subprocess being executed in a special dedicated segment that operates concurrently with all other segments A pipeline is a collection of processing segments through which binary information which is meporms partial processing dictated by the way the task is partitioned. Pipelining is a technique of decomposing a sequential process into sub-operations. The final result is obtained after the data ave passed through all segments. 8. Q. 11. 5. The current technology RISC processors support the floating point data type. 10. 2. 1. What is SIMD Array processor? Ans. . 4. RISC processor consume less power and haypnce. Q.Ans. RISC machines require lesser time for its design implementation. There are following characteristics of RISC. L. The processing unit are synchronised to perform the same operation under the control of common control unit. 6. RISC system are more popular. 3. How pipelining would improve the performance of CPU justify. while most of CISC requires more than one clock cycle. A SIMD array processor is a computer with multiple processing units operating in parallel. RISC machines mostly uses hardwired control unit. multiple data stream (SIMD) organization. RISC instructions are executed in single clock cycle. thus providing a single instruction stream. Non-pipeline unit that performs the same operation and takes a time equal to (time taken to complete each task). Under this condition. To clarify the meaning of improving the performance of C. Assume that the pipeline k 4 segments and . n becomes much larger than k — 1. The total time required for n tasks is n t.U. consider the following numerical example.U. where K is segments of pipeline and Ip is time used to execute n tasks.P. through speed up ratio. and K + n — I approaches the value of n.P.Ans. where K is number of segments in pipeline. The time it takes to process a task is the same in the pipeline and non pipeline circuits. The speed up of a pipeline processing over an equivalent non-pipeline processing is defined by the ratio As the number of tasks increases. the speed up becomes. Speed of pipeline process is improved the performance of C. Let the time it takes to process sub operation in each segment be equal to 20 ns. There if t = kt speed reduces to Maximum speed that a pipeline can provide is K. As the number of tasks increase. It overlaps the multiple instructions in execution. Execute the instruction (LI). Super of pipelining splits one tasks into multiple subtasks. Compare and contrast super pipelined machine and super scaler machines. a non-pipelne system requires nktp = 100 x 80 8080 ns to complete tice 100 tasks. which is equal to the number of segment in pipeline. 12. 2. then speed up become=60/3. Q. Decode the instruction (DI). 1. Calculate the effective address (EA). It we assume that = 60ns. The pipeline system will take (k + n — 1) t = (4 + 99) 20 = 2060 ns to complete. Super pipelined machine : Pipelining is the concept overlapping of multiple instruction during execution time. . The speed up ratio is equal to 8000/2060 88. the speed up will approach 4. Ans. Assuming that t = kt = 4 x 20 = 80ns. The instruction goes through the four stages during execution phase. 3.executes n 100 tesks in square. Fetch an instruction from memory (Fl). These subtasks of two or more different tasks are executed parallel by different hardware units. 4. Pipeline is also implemented in each processing elements.Fig. at the same time in different pipeline. Q. decode and execute will determine the overall performance of system. The super scalar architecture allows on the execution of multiple instruction. The instruction fetching units fetch multiple instructions at a time from cache. . The instruction decoding units check the independence of those instructions at a time from cache. The slowest stage among fetch. There should be multiple execution units so that multiple instruction can be executed at the same time. Ideally these three stages should be equal fast.13 Give the comparison between and examples of hardwired control unit and micro programmed control unit. Space time diagram Super scalar processor/Machine : The scalar machine executes one instruction one set of operands at a time. Here multiple processing elements are used for different instruction at the same time. Ans. any required changes or modifications can be done by updating the microprogram in control memory. decociptherdiitirçits. In Hardwired organisation. It has the advantage that it can be optimised to produce a fast mode of operation In microprogrammed organisation. A hardwired control for the basic computer is presented here. (b) Microprogrammed control. Difference between hardwired control and microprogrammed control are given below: . In the micro programmed control.flip-flops. The control memory is programmed to initiate the required sequence of micro operations. as the name implies. A hardwired control. the control logic implemented with .gates. There are two major types of control organisation (a) Hardwired control. the control information is stored in a control. requires changes in the wiring among the various components if the design has to be modified or changed. The program counter (PC) contains the address the first instruction of a program under execution. The address of first instruction from PC is loaded into the address register (AR) during first clock cycle (To). instruction cycle. Then instruction from memory location given by address register is loaded into the instruction register (IR) and the program counter is incremented to the address of next instruction in . What do you understand by Fetch cycle. machine cycle. Fetch cycle : The sequence counter is initialized to 0.Q 14. inter put acknowledgment. Ans. A memory unit with 4096 words of 16 bits each.second clock cycle (TL). First of all an instruction in fetched (accessed) from memory. read the effective address from the memory. 3. Seven flip-flops. Executing these instructions runs the program in computer. Moreover each instruction is further divided into sequence of phases. 2. Decision is made for memory or register or I/O reference instruction. Then decode that instruction. The concept of execution of an instruction through different phases is called instruction cycle. In case of memory indirect address. These micro-operations using register transfer is shown as Instruction cycle: A program in computer consists of sequence of instructions. Finally execute the instruction. Machine cycle: Machine includes following Hardware components. 1. 3. The instruction is divided into sub phases as specified ahead— 1. 2. 4. Nine registers. . 7. 6. This is way of interrupt acknowledge to C. The memory unit is a standard component that can be obtained readily from a commercial source. Adder and logic circuit connected to the input of AC. The . This type of transfer uses interrupt facility. and memory. the computer can be interrupted. The interrupt enable flip-flop can be set and cleared with two instructions.4. 5. 16-bit common bus. Control logic gates. When flip-flop is cleared with two instruction.What is meant by super scalar processor? Explain the concept of pipelining in uperscalar processor? Ans. Q 15. The scalar processor executes one instruction on one set of operands at a time. Two decoders : a 3 x 8 operation recorder and a 4 x 16 timing decoder. When flip-flop is cleared to 0. In the meantime the computer can be busy with other tasks.U.P. the flags cannot interrupts computer when flip-flop is set to 1. Interrupt Acknowledgment : The programmed controlled procedure is to external device inform the computer when it is ready for transfer. decode and execute will determine the performance of the system. Fetch an instruction from memory (Fl) 2. 1. Execute the Instruction (El). The instruction goes through the four stages during the execution phase. The instruction fetching units fetch microinstruction at a time from cache. The instruction decoding unit checks the independence of these instructions so that they can be executed in paraiit There should be multiple execution units so the multiple instructions . .can be executed at the same time. Decode the instruction (DI) 3.super scalar architecture allows the execution of multiple instructions at the same time in different pipelines. Ideally these three stages should be equally fast. Pipeline overlaps the multiple instructions in execution. Practically execution stage in slowest and drastically affect the performance of system. Here multiple processing elements are used for different instruction at same time. Pipeline is also implemented in each processing elements. The slowest stage among fetch. Calculate the effective address (EA) 4. Single Cycle instruction execution. Q. Hardwired rather than micro programmed control. Fixed length. The major characteristics of a RISC processor are: 1. 6. (CPI) Ans. Although the various stages may not be of equal duration in each instruction. All operations done with in registers of the CPU. These five instructions are executed in eight clock cycles. . Relatively few addressing modes. 7. Memory access limited to load and store instructions. Each instruction had been through four stages. five instructions are executed using instruction pipeline.In space-time diagram above. Relatively few instructions. easily decoded instruction format. 4. 5. RISC Architecture involves an attempt to reduce execution time by simplifying the instruction set of the computer. 2. addressing modes and cycle per instruction. 3. That ma result in waiting at certain stages. 16 Compare the instruction set Architecture is RISC and CISC processor in the instruction formats. There are three basic addressing modes register addressing.The small set of instructions of a typical RISC processor consists mostly of register to register operations.typically from 5 to 20 different modes. 3. 5. -16. with only simple load and store operations for memory access. immediate operand and relative to PC addressing for branch instructions. or 32-bit data. A large member of instructions-typically from 100 to 250 instructions. CISC Processor : The major characteristics of CISC architecture are: 1. 2. A large variety of addressing nodes . Variable-Length instruction formats. It supports 32-bit addresses and either 8-. Some instructions that perform specialised tasks and are used in frequently. 4. Instruction that manipulate operands in memory. It has a 32-bit instruction format and a total of 31 instructions. The Berkely RISC is a 82-bit integrated circuit CPU. . SIMD computer executes one instruction on multiple data items at a time. The processor may have more than one functional unit. Here all processor receives the same instruction from control unit and implement it on different data items. This means it is implemented in multiprocessor system. 17. It involves multiple control unit. All these functional unit works under same control unit. This concept is for theoretical interest and is not feasible practically. What cause of processor pipeline to be under pipelined? Ans. SISD computer executes one instruction on single data item at a time. There is a single control and single execution unit. Multiple control units receive multiple instructions from centralized memory.Q. multiple processing units and single execution unit. Here the instructions are executed sequentially but can be overlapped during execution stages using pipelines. Hence attention has not been paid to implement this architecture. This means its implementation is only for uniprocessor systems. There is single control unit that handle multiple execution units MISD computer manipulates the same data stream with different instruction at a time. Each instruction from centralized unit is passed to its corresponding . This concept is implemented in vector or array processing and multimedia extension (MMX) in pentium. Hence it involves multiple processor. The term is used to refer to two different types of processors. Then all these instructions operate on the same data provided by contralised common memory. It achieves high performance by means of parallel processing with multiple functional units. Array processor is a processor that performs computations on large array of data underpipeline. It includes an arithmetic unit containing one or more pipelined. An attached array processor is n auxiliary processor attached to a general purpose. The array processor can be programmed by the user to accommodate a variety of complex arithmetic problems. When the different tasks are executed by different hardware unit is called pipeline. It manipulates vector instructions by means of multiple functional units responding to a common instruction. These types of computer provide the high level of parallelism by having multiple processors. An SIMD array processor is a processor that has a single instruction multiple data organisation. An attached array processor is designed as peripheral for a conventional host computer. MIMD computer involves the execution of multiple instruction on multiple data stream.processing unit. and its purpose is to enhance the performance of the computer by providing vector processing for complex scientific applications. . The Simplest way of viewing the pipeline structure is that each segment consists of an input register followed by a Combination circuit. Ans. Each segment performs partial processing. . Explain instruction set of SPARC with description.Q. The result obtained from computation in each segment is transferred to next segment in pipeline. Write short note on Hazards of pipelining. A clock is applied to all registers after enough time has elapsed to perform all segment activity. The register holds the data and the combinations circuit performs the sub operations in the particular segment. Q. 18. The output of Combination CK is applied to input register of the next segment. with each subprocess being executed in special dedicated segment that operates Concurrently with all other segments. Pipelining is a techniques of decomposing a sequential process into suboperations. Pipeline can be visualized as a collection of processing segments through which binary information flows. 19. It implies a flow of information to an assembly line. and for jump instruction (f-format and format & instructions). The layout of SPARC instruction is Format Two Instructions (branch) The SPARC Call Instruction. SPARC machine use instruction that thirtytwo bits long. the cond is the Branch condition and the .Ans. The machine has an instruction type for algebric instruction. for branch instruction. the first two bits specify the instruction type. used to transfer control to anywhere in 32 bit address looks date As usual. 20. Data dependency conflict : It arise when an instruction depends on the result of a previous instruction. Branch difficulties: It arise from branch and other instructions that change the value of PC. What are reasons of pipeline conflicts in pipelined processor ? How are they resolved? Ans. They are either algebric instruction to load/store instruction.op2 is the operand to compare against. but this result is not yet available. Q. Resource conflicts : It caused by access to memory by two segments at the same time. Non-branch format two instruction is Format three: (Algebric Instructions) These instruction are the most common instructions. 3. Most of these conflicts can be resolved by using separate instruction and data memories. It met the machine transfers control to location specified by the 22 bit constant. There are following reasons which create the conflicts in pipelined processor and way by which it is resolved: 1. . 2. An interlock is a circuit that detects instructions whose source operands are destinations of instructions farther up in pipeline. Similarly. This approach maintains the program sequences by using hardware to insert the required delays.A difficulty that may cause a degradation of performance in an instruction in pipeline is due to possible collision of data or address. A collision occurs when an instruction cannot proceed because previous instructions did not complete certain operations. For example. the second instruction must wait for data to become available by the first instruction. an instruction with register indirect mode cannot proceed to fetch the operand if the previous instruction is loading the address into the register. the operand access to memory must be delayed until the required address is available. an address dependency needed by address mode is not available. Pipelined computers deal with such conflicts between data dependencies in a variety of ways. Therefore. . A data depending occurs when an instruction needs data that are not yet available. For example. The most straight forward method is to insert Hardware inter locks. Therefore. an instruction in the Fetch operand segment may need to fetch an operand that is being generated at the same time by the previous instruction in segment EX (Execute). Q. Such an interrupt is called a software interrupt. The normal operation of a micro processor can also be interrupted by abnormal internal conditions or special instruction. Hardware and software interrupts : Interrupts caused by I/O devices are called Hardware interrupt. This method requires additional hardware paths through multiplexers as well as the circuit that detects the conflict. RST is instruction of processor are used for software interrupt. 21. instead of transforming an ALU result into a destination register. hardware checks the destination operand and if it is needed as a source in the next instruction. When RST n . W1at do you mean by software and Hardware interrupts ? How these are used in microprocessor.Another technique called operand forwarding uses special hardware to detect a conflict and then avoid it by routing the data through special paths between pipeline segments. A procedure employed in some computers is to give the responsibility for solving data conflicts problems to the compiler that translates the high-level programming language into a machine language program. it passes the result directly into ALU input.’tor example. Ans. by passing the register file. If it is set to 0. Bit 3 is set to 1 to make bits 0 . . corresponding interrupt is enabled. The external Hardware circuits generate RSTn codes to implement the multiple interrupt scheme.5. 6.5 mask.5 is reset.5.5.7 and 7. Bit 0 for RST 5.ST 7. the program is executed upto the point where RST n has been inserted. bit I for RSI 6.5 and RST 5.instruction is inserted in a program. RST 6. This is used in debugging of a program. These interrupts are enabled by software using instructions El and SIM (Set interrupt mask). Bit 4 is an additional control for RSI 7. Intel literature do not use the form exception. Where Motorola literature use the term exception. For example.5 mask and bit 2 for RST 7.5 is 0 or 1.5 are maskable interrupts. These RST 7. Bit — 0 to 2 rest/ set the mask bits of interrupt mask for RST 5. The excretion of instruction SIM enables/disables interrupts according to hit pattern of accemable. P. The internal abnormal or unusual conditions which prevent processing sequence of a microprocessor are also called exceptions. If it is set to I the flip.flop for RST 7.2 effective.5 mask.5.5 is disabled regardless of whether bit 2 for RST 7. Intel includes exception in software interrupt when several I/O devices are connected to INR interrupt line. divide by zero will cause an exception. If a bit is set of the corresponding interrupt is masked off (disable). an external Hardware is used to interface I/O devices.