UG Diploma in Analog VLSI DesignCourse: Mini Project Course Code: 10UGVL06 Nature of Project: Analog VLSI Layout Design Project Title: Design of a Static CMOS Tri-state Inverter Defined Specification: Minimum Achievable Delay Conclusion. Layout plan 9. SPICE Simulations 8. Theoretical estimated parameters 6.References . Device sizing details 4. Delay versus load estimate 7. Architecture analysis and comparisons 3. 11. DRC and LVS report 10. Introduction 2. Switching potential estimate 5.Project By: Manasa S Upadhyaya CONTENTS: 1. The mode of operation of tri state logic circuit is determined by the state of enable input.. the digital value interpreted by the input depends on the type of technology used. This is commonly used to connect banks of computer memory and other similar devices to a common data bus. Variation of load versus delay is plotted. out of these the best architecture is chosen. where all but one are put into the high impedance state. When the enable input is ‘high’. The tri-state inverter forms the basis for various types of clocked logic. On the other hand CMOS technology will temporarily hold the previous state seen on that input (due to the capacitance of the gate input). This provides an effective way to connect several logic outputs to a single input.ABSTRACT: This project report comprises design of a static CMOS tri state inverter for minimum achievable delay. When the enable is ‘low’ the circuit is in the high impedance state. The symbol and truth table of a tri state inverter is as shown below: . and I/O structures. when it is given a high impedance signal). The device sizing. 1. TTL technology will reliably default to a "1" state. When a digital input is left disconnected (i. latches. allowing the remaining output to operate in the normal binary sense. multiplexers. bus drivers. switching potential estimation is carried out through hand calculations and verified through SPICE simulations.e. with a third high impedance state (or 'off-state') which effectively disconnects the logic output. Finally the layout of the inverter is captured using standard cell layout technique along with DRC and LVS reports. INTRODUCTION: A tri state logic comprises the usual true (0) and false (1) states. driving 10 identical copies of it. a large number of devices can communicate over the same channel simply by ensuring only one is enabled at a time. 3 possible architectures for realising the inverter are discussed. the device is enabled for normal logic operation. The disadvantages of the above topology can be avoided by putting a transmission gate inside the inverter.1 Circuit topologies: .1 provides tri state capability. A A 0 1 0 1 Y Z Z 1 0 ARCHITECTURE ANALYSIS AND COMPARISONS: Following are the architectures that can be used for realising a tri state inverter: Using Transmission gate: A transmission gate connected to the output of an inverter as shown in Fig2.. It is also a non restoring circuit. This topology contributes to dynamic power each time that the input and output (Y’) are switched. The possibilities fig are as follows: 2. i.En Symbol: Y En Truth table: En/ En 0/1 0/1 1/0 1/0 2. but also consumes unnecessary power. even when gate is disabled in the tri state mode.e. the output will receive same noise. if the input is a noisy or degraded signal. 3. For the circuit of fig2. the charges from the internal nodes disturbs the floating output node. When the output is tri-stated. the effect of charge sharing is not seen in its tri-state condition as the output node Y is completely disconnected from the input and internal nodes. the voltage level of the floating output node will not remain same as its previous value. This effect may switch the next gate driven by this gate. Hence it can cause erroneous output of the circuit. Due to this. Nomenclature: Subscripts: p – PMOS .3 In general.fig2. Load: 10 copies. the two topologies shown above are logically equivalent. Method used: RC Delay model. DEVICE SIZING : Specification: To size the device for minimum achievable delay.2 fig2.2. Hence this circuit topology is best suited for realising a simple tri-state inverter. if the input A toggles.3. but the effect of charge sharing comes into picture for the circuit of fig2. so channel length. Lp = Ln = 180nm. 2.n – NMOS d – Drain terminal of MOSFET s – Source terminal of MOSFET g – Gate terminal of MOSFET b – Body/Substrate of MOSFET Parameters: Vdd – Supply terminal Vss – Ground terminal R–Drain to Source resistance C – Gate Capacitance µ – mobility of electrons (n) /holes (p) W – Width of MOSFET L – Chanel length Tpdr – Rise time of output Y Tpdf – Fall time of output Y Tpd – Propagation delay time 1. Consider a unit inverter which has been designed minimum propagation delay. Let Wn and Wp be the widths of NMOS and PMOS of the inverter as shown fig3. Since TSMC 180nm technology is used for design of the inverter.1. . 8. 6. The gate capacitance: Cg∝W*L⟹ Cg-pCg-n= 2*Wp2*Wn=WpWn ∵ Lp=Ln 4.1 fig3.2 3. 7. Let the mobility ratio be μ=μnμp.3.fig3. Cgs1=Cdb1=Csb2=Cg-n Cgs4=Cdb4=Csb3=Cg-p Cdb4=12*Cg-n Cdb3=12*Cg-p .2. as shown in fig3. 5. The design calculations are carried out by considering En (En) as high (low). let the width of NMOS be 2 times that of unit inverter so that the effective resistance of the 2 NMOSs’ together is equal to that of the unit inverter. From fig3. Considering Cdb=Cgs=Csb=Cg for contacted diffusion and Cdb=Cgs=Csb≅Cg/2 for uncontacted shared diffusion. 9. So the transistors M2 and M3 are on. The same holds good for the PMOSs’ as well. The resistance of a transistor: R∝ 1μ * W ⇒ RpRn= μnμp*2*Wn2*Wp=μnμp*WnWp. Now for the tri-state inverter. e..e. the rise time is determined. Tpdf=Rn*Cg-n+Rn*Cpar+Cload= n+Cpar+Cload Tpdf=Rn*Cg-n*(232+212*WpWn) Rn*Cg- 13. The fall time is again determined by equivalent RC network (fig3. i. A = 1(high). Which implies that.4 12. the load Cload=Cout=10*Cin=10*Cg-n*(1+WpWn) 10.4.5).Propagation delay: The average propagation delay is given by. both PMOSs’ must be turned on. Determination of Rise time (Tpdr): 11. we get Tpdr=212*Rn*Cg-n*μnμp*WnWp fig3 . it must be connected to Vdd. 5 .3 The parasitic capacitance is given by: Cpar=Cdb3+Cdb4=12*(Cg-n+Cg-p)=12*Cg-n*(1+WpWn) Since the inverter capacitance is given by: drives 10 copies of itself. Using the equivalent second order RC network as shown in fig3. it has to be connected to Vss. A = 0 (low). Determination of Fall time (Tpdf): For the output Y to fall from Vdd (high) to Vss (low).The effective input capacitance is given by: Cin=Cgs1+Cgs4=Cg-n+Cg-p=Cg-n*(1+WpWn) (From step 2) fig3 . i. Hence both NMOSs’ must be on.. Tpdr=Rp*Cg-p+Rp*Cpar+Cload=Rp*Cg-p+Cpar+Cload On substituting equations of step 9 in above equation. For the output Y to rise from Vss (low) to Vdd (high). fig3. β(=μ*Cox*WL)of the single N MOS is given by βn1+βn2=βn2. And the trans conductance parameter. To do this. first consider the NMOSs’. SWITCHING POTENTIAL ESTIMATE: The switching point of an inverter is a point on its voltage transfer characteristic at which the input voltage is equal to the output voltage. At the switching point. Similarly the equal sized PMOSs’ can be approximated as a single PMOS of channel length 2*Lp and β=βp2 . it is configured as a simple inverter. To find minimum value of Tpd.Tpd=12*(Tpdr+Tpdf) ⟹Tpd=12*Rn*Cg-n*(212*μnμp*WnWp+232+212*WpWn) To determine Wn and Wp for defined specification: Let w=WpWn. dTpddw=0 ⟹12*Rn*Cg-n*212*μnμp+212*-1w2=0 ⟹w2=μnμp ⟹WpWn=μnμp 1. This potential is termed as the switching potential. the MOSFETs are operating in saturation region. The 2 NMOSs’ of equal sizes connected in series can be approximated to be a single NMOS with channel length equal to sum of the individual lengths. To determine the switching potential of the tri-state inverter. . hence the drain current of NMOS and PMOS must be equal. differentiating equation with respect to w and equating to zero. Ln1+Ln2=2*Ln . 86 volts µA/V^2 cm^2/V *s From the above derived equations and details. therefore for the tri-state inverter.07 – 0.0 87.0 406. the devices sizes are: . THEORETICAL ESTIMATED PARAMETERS: The parameters of the MOSFETs are taken from the measurements of MOSIS test structures obtained by MOSIS. Vsp – Switching potential Vthn – Threshold voltage of NMOS Vthp – Threshold voltage of PMOS Vdd – Supply voltage On solving the above equation for Vsp .5µm.50 171.49 –37. choosing Wn of the unit inverter as 0.∴ βn22*Vsp-Vthn2=βp22*Vdd-Vsp-Vthp2. Where. we get Vsp=βpβn*Vdd-Vthp+Vthn(1+βpβn). 2.18 microns TRANSISTO NP-CHANNEL UNITS R CHANNEL PARAMETE RS Vth K' (µ*Cox/2) Low-field Mobility (µ) 0. VENDOR: TSMC TECHNOLOGY: SCN018 FEATURE SIZE: 0. The logical effort of the gate is given by g=Cin-gateCin-inv where Cin-gate input capacitance of the gate and Cin-inv input capacitance of an inverter delivering the same output current as that of the gate.5(1+888.1620.821900*1.00µm 2. Hence the value of ‘h’ varies from 1 to 10.8289V.Transistor NMOS PMOS Channel Width 1.80. . Hence for the tri-state inverter. f=g*h. Cin-inv=Cg-n*(1+μ) Cin-gate=2*Cg-n*(1+μ) ⟹g=2 The fanout of the tri-state inverter is equal to number of identical copies drawn by the gate.162µm Channel Length 0. where Cpar-gate – parasitic capacitance at the output node of the gate and Cin-inv – capacitance at the input node of the unit inverter.18µm Switching potential value: βn=2*(μ0*Cox2*WL)n=2*171*10. Hence d=g*h+p. The parasitic delay of the gate is given by p=Cpar-gateCin-inv. Consider a unit transistor designed to achieve minimum delay.49+0.18=888. DELAY VERSUS LOAD ESTIMATE: From the linear delay model.821900)=0.18=1900 βp=2*(μ0*Cox2*WL)p=2*37*2. we have the normalised delay of the gate as d=f+p Where p –normalised parasitic delay of the gate under zero load. 3.18µm 0. f – Stage effort. Vsp=βpβn*Vdd-Vthp+Vthn(1+βpβn)=888. where g – logical effort and h – fanout of the gate.82 Switching potential. Wn=2*0. Consider En/En =1/0.5μ=1μm. To verify the device size.p=2. 4. d=2*h+2. Hence the normalised delay. therefore for the tri-state inverter.5µm. . SPICE SIMULATIONS: Tool used: LT SPICE IV Schematic: 1. Choosing Wn for inverter as 0. Analysis: transient analysis is carried out to determine the propagation delay. we get minimum delay at Wp = 2. 2. Consider En/En =1/0. Keeping Wn = 1 µm and Wp = 2. Analysis: dc sweep to determine the switching potential. To determine the switching potential. .Propagation delay v/s width of the PMOS transistors: From the transient analysis.132 µm.132µm. Vsp = 0.From the dc sweep analysis. The gate is made to drive 0 to 10 copies of it and the corresponding delay values are plotted. .833V 3. To plot the average propagation delay-versus load. 1. LAYOUT PLAN: Tool used: The Electric VLSI Design System. Stick diagram: Layout Plan: . DRC AND LVS REPORT: DRC report: .2. Layout v/s Schematic (Network Consistency Checking (NCC) in the tool): 3. CONCLUSION: . John P Uyemura.mosis. In the load versus delay plots.com . the delay at zero load is not same as estimated but for higher loads the 2 plots match. David Haris. Third edition. 1. REFERENCES: Neil H. 4.The tri-state inverter with a simple architecture has been analysed and designed to achieve the defined specification. Website: www. This is so because. The theoretically estimated values are approximately equal to the simulated values. Prentice Hall. 3. ‘Digital Integrated Circuits’. while determining the theoretical values. ‘Introduction to VLSI CIRCUITS AND SYSTEMS’. 2. Wiely-India.E Weste. 2nd. Ayan Banerjee-‘CMOS VLSI Design A Circuit and systems Perspective’. Pearson Education. Rabeay. 4.Edition. approximate RC delay models have been used.