1. What is callback ?Callback is one of the major confusing point for a System Verilog learner. Many people have asked the same question in many forums, but the answer doesn't seems to satisfy fully the quest of the person who has raised the querry. I too had the same issue, but I learned it slowly in a hard way. I am presenting here a way in which if I had an answer, I would have learned faster. We can pass data member to any function. Now consider a case where you are passing a function (say func1) as a data member to another function (say func2) and you get what is called callback. The reason why it is called callback is that the function func2 now can call anywhere in its code function func1. From wikipedia In computer programming, a callback is executable code that is passed as an argument to other code. It allows a lower-level software layer to call a subroutine (or function) defined in a higher-level layer. Note that SV doesn't give a straight-forward way of passing a function as argument for another function. But we can get the same result (almost we can say!) by using OOP. The idea is to describe all the functions (both func1 type and func2 type) in a base class (don't implement the funct2 kind of function and make them virtual for polymorphism), and then extend the class to a derived class where you implement the func2 type of function. Example:- class abc_transactor; virtual task pre_send(); endtask virtual task post_send(); endtask task xyz(); // Some code here this.pre_send(); // Some more code here this.post_send(); // And some more code here endtask : xyz endclass : abc_transactor class my_abc_transactor extend abc_transactor; virtual task pre_send(); ... // This function is implemented here endtask virtual task post_send(); ... // This function is implemented here endtask endclass : my_abc_transactor Now let me explain how it is going to work. The base class abc_transactor has 3 tasks, 2 of which are declared virtual and are not implemented. But they are being called from another task xyz() which is fully implemented. The unimplemented virtual task are called callback class. The child class, which extends from the base class, implements the previous unimplemented tasks. It inherits the xyz() task from the base class and hence doesn't need to change it. By this we can inject executable code to a function without modifying it. Now the next question is why is done. There are many reasons for it. 1. 2. The biggest advantage is that you can modify the behavior of task xyz() without modifying it in the base or child class. It is a big advantage as no one wants to fiddle with known good functioning code. Consider a case where you are writing a base class which is going to be used by multiple test environment, and for each test environment a known part of the code, or a known function/task is going to change. The natural choice is to implement those change-in-every-case functions/tasks as callback method and let the user extend your base class with specifying only that part of the code which need to be changed in his case. Simple callback using the above approach does have some known limitations, which can be solved using design patterns (from OOP land), the details of which can be found at Janik's article of vmm_callback. Suppose if you are doing transmitting data using mailboxes, Once you are send ing data to design from genetarator . The same data you need to put back in score board for latter comparison. This is called callbacks 2. What is factory pattern ? Factory pattern as the name suggest, is aimed at solving the issue of creation of object. (Factory pattern is not the only pattern to deal with creation of objects, there are a bunch of more patterns for handling different kind of cases, and collectively they are known a creational patterns) Let me give an example of case where we might need to use creational pattern and how to do so it in SV. Suppose you want to create a "Toy Factory" class which needs to create multiple types of toys (say toy aeroplane, toy tank, toy bus) depending upon the string input to it. To create these different types of toys we need to have class defined for them. And there will be common method and data interface for these classes, hence it make sense to put all the common data member/task/functions in a class called toy class and then extend it. class TOY; // Common data memeber string type; my_toy = new TOY_Bus(). Wire:Wires are used for connecting different elements They can be treated as a physical wire They can be read or assigned No values get stored in them They need to be driven by either continuous assign statement or from a port of a module Reg:- . return this. Explain the difference between data types logic and reg and wire 1. 2.string = "Toy Bus". let's consider the case where we will want to pass 1 to get an instance of tank class and 2 for getting an instance of bus class from the factory. endfunction : get_toy endclass : TOY_factory Note that we are using virtual function for bringing polymorphism in action and save us from having an individual instance of the toy type in the factory class. endfunction : new string function string get_type(). this. endclass : TOY class TOY_Tank extends TOY. function new(). if(type == 1) this. class TOY_factory. 5. 3. endfunction : get_type endclass : TOY_Tank class TOY_Bus extends TOY. Toy my_toy // Common methods function toy get_toy(int type). if(type == 2) this.my_toy = new TOY_Tank(). this.string = "Toy Tank". 4.// Common methods virtual function string get_type(). function new().string. return this. return this. endfunction : get_type endclass : TOY_Bus Now we are done with the bothering about the objects to be created.string. The next problem that we need to solve is to write the toy factory class itself.my_toy. endfunction : new string function string get_type(). 3. Now the factory class will look like this. For simplicity. Contrary to their name. As we have seen. Thus. There are quite a few links on clocking block in the internet. So the next question is what is this logic data type and how it is different from our good old wire/reg. which enables users to write testbenches at a higher level of abstraction. the timing for sampling and driving clocking block signals is implicit and relative to the clocking block’s clock. The clocking block is a key element in a cycle-based methodology. These operations are as follows: — Synchronous events — Input sampling — Synchronous drives Clocking block in SystemVerilog are used for specifying the clock signal. and synchronization requirements of various blocks. . timing. The clocking block separates the timing and synchronization details from the structural. Logic:- 1. It has a last assignment wins behavior in case of multiple assignment (which implies it has no hardware equivalence). 3. // reg style MyModule module(. A clocking block assembles signals that are synchronous to a particular clock and makes their timing explicit.out(a). The idea behind having a new data type called logic which at least doesn't give an impression that it is hardware synthesizable Logic data type doesn't permit multiple driver. 4. functional. // wire style always (c or d) a = c + d. synchronization requirements. However.1. . the test can be defined in terms of cycles and transactions. an interface does not explicitly specify any timing disciplines. This enables a set of key operations to be written very succinctly. reg data type is bit mis-leading in Verilog. 3. Reg/Wire data type give X if multiple driver try to drive them with different value. 2. the communication between blocks is specified using module ports. 2. latch or combinational circuit (They might not be synthesizable !!!) Wires and Regs are present from Verilog timeframe. SystemVerilog added a new data type called logic to them. without explicitly using clocks or specifying timing. // wire style 4. Rather than focusing on signals and transitions in time. a testbench can contain one or more clocking blocks. These are links to learn about SV clocking blocks. regs doesn't necessarily corresponds to physical registers They represents data storage elements in Verilog/SystemVerilog They retain their value till next value is assigned to them (not through assign statement) They can be synthesized to FF. Depending on the environment. SystemVerilog's logic data type addition is to remove the above confusion. each containing its own clock plus an arbitrary number of signals. SystemVerilog adds the clocking block that identifies clock signals and captures the timing and synchronization requirements of the blocks being modeled. Logic data type simply assign the last assignment value. What is the need of clocking blocks ? In Verilog.in(xyz)). output of a port and inside a procedural block like this logic a. a key construct that encapsulates the communication between blocks. functional and procedural element of the TB. thereby enabling users to easily change the level of abstraction at which the intermodule communication is to be modeled. or clocking paradigms. assign a = b ^ c. The next difference between reg/wire and logic is that logic can be both driven by assign block. An interface can specify the signals or nets through which a testbench communicates with a device under test (DUT). It separates the timing related information from structural. SystemVerilog adds the interface. and procedural elements of a testbench. 03.output #3ns enout. enout.output [31:0] dout .input ck.sab = sd.din[7:0].din . The primary task of a testbench is to generate valid input stimulus for the design under test and to verify that the device operates correctly.Provides race-free operation if input skew > 0 . 04. 02.Specify synchronization characteristics of the design .initial begin 14.input [31:0] din .Helps in testbench driving the signals at the right time . enin. dout. 09. testbenches that use cycle abstractions are only concerned with the stable or steady state of the system for both checking the current outputs and for computing stimuli for the next cycle.module or program Example : 01.Can be declared inside interface.output enout . 07. 05. dout).Cycle delay (##) .clocking sd @(posedge ck). these effects are all unimportant details. din.input #2ns ein. 10. 12. The second one is that statements without time control constructs in behavioral blocks do not execute as one event. from the testbench perspective.Clock specification .enin. What are the ways to avoid race condition between testbench and RTL using SystemVerilog? There are two major sources of nondeterminism in Verilog. 08.end 16.. 13. Furthermore.Offer a clean way to drive and sample signals . 15.output skew .Input skew.endmodule:M1 5. However. The first one is that active events are processed in an arbitrary order.endclocking:sd 11.Module M1(ck.Features . 06. .reg [7:0] sab . Formal tools also work in this fashion. in time order. This procedure guarantees that the simulator never goes backwards in time. Proper input sampling only addresses a single clocking block. With this behavior. correct cycle semantics can be modeled without races. in contrast. not program blocks) are scheduled in the Reactive region. Simulation proceeds by executing and removing all events in the current simulation time slot before moving on to the next nonempty time slot.Statements within a program block that are sensitive to changes (e. The program construct addresses this issue by scheduling its execution in the Reactive region. Because the program schedules events in the Reactive region. In addition. where clk is a design signal in some module.. which at any given point during simulation can be the current time or some future time. All scheduled events at a specific time define a time slot. . design signals driven from within the program must be assigned using nonblocking assignments and are updated in the NBA region. thereby making program-based testbenches compatible with clocked assertions and formal tools. Every transition of signal clk will cause the statement S1 to be scheduled into the Reactive region. update events) in design signals (declared in modules. With multiple clocks. the clocking block construct is very useful to automatically sample the steady-state values of previous time steps or clock cycles. Consider a program block that contains the statement @(clk) S1. the arbitrary order in which overlapping or simultaneous clocks are processed is still a potential source for races. including clocks driven by nonblocking assignments. even signals driven with no delay are propagated into the design as one event. Programs that read design values exclusively through clocking blocks with #0 input skews are insensitive to read-write races. initial blocks in modules are scheduled in the Active region. after all design events have been processed. initial blocks within program blocks are scheduled in the Reactive region. Every event has one and only one simulation execution time. The first division is by time. Likewise. 6. A time slot is divided into a set of ordered regions: a) Preponed b) Pre-active c) Active d) Inactive e) Pre-NBA f) NBA g) Post-NBA h) Observed i) Post-observed j) Reactive k) Re-inactive l) Pre-postponed m) Postponed The purpose of dividing a time slot into these ordered regions is to provide predictable interactions between the design and testbench code. Thus. Explain Event regions in SV.g. It is important to understand that simply sampling input signals (or setting nonzero skews on clocking block inputs) does not eliminate the potential for races. and other similar events. and Re-inactive regions and the Post-observed PLI region. The Pre-NBA region provides for a PLI callback control point that allows PLI application routines to read and write values and create events before the events in the NBA region are evaluated (see 9. In other words. Conceptually.4). The Pre-active region provides for a PLI callback control point that allows PLI application routines to read and write values and create events before events in the Active region are evaluated (see 9. This #1step construct is a conceptual mechanism that provides a method for defining when sampling takes place and does not require that an event be created in this previous time slot. The Pre-active. The Observed. with exactly the same level of determinism. The new #1step sampling delay provides the ability to sample data immediately before entering the current time slot and is a preferred construct over other equivalent constructs because it allows the 1step time delay to be parameterized. and Re-inactive regions are new in this standard. The Postponed region is where the monitoring of signals. PLI callbacks are not allowed in the Observed region. Reactive.4). A criterion for this determinism is that the property evaluations must only occur once in any clock triggering time slot. takes place. The Post-observed region provides for a PLI callback control point that allows PLI application routines to read values after properties are evaluated (in Observed or earlier region). The Post-observed region is new in this standard and has been added for PLI support. legacy Verilog code shall continue to run correctly without modification within the new mechanism. During the property evaluation. and Post-NBA regions are new in this standard but support existing PLI callbacks. and events are only scheduled into these new regions from new language constructs. these regions essentially encompass IEEE 1364 reference model for simulation. NOTE—The PLI currently does not schedule callbacks in the Post-observed region. this #1step sampling is identical to taking the data samples in the Preponed region of the current time slot. . Pre-NBA.Except for the Observed. No new value changes are allowed to happen in the time slot once the Postponed region is reached. The Re-inactive region is the program block dual of the Inactive region (see below). The Post-NBA region provides for a PLI callback control point that allows PLI application routines to read and write values and create events after the events in the NBA region are evaluated (see 9.4). pass/fail code shall be scheduled in the Reactive region of the current time slot. The code specified in the program block and the pass/fail code from property expressions are scheduled in the Reactive region. The Observed region is for the evaluation of the property expressions when they are triggered. Reactive. A #0 control delay specified in a program block schedules the process for resumption in the Re-inactive region. Reactive. schedule all initialization events into time 0 slot. Observed. The Inactive region holds the events to be evaluated after all the active events are processed. and Prepostponed regions are known as the iterative regions. Post-observed. NBA. The flow of execution of the event regions is specified in Figure 9-1.The Pre-postponed region provides a PLI callback control point that allows PLI application routines to read and write values and create events after processing all other regions except the Postponed region. it is illegal to write values to any net or variable or to schedule an event in any other region within the current time slot. The Active region holds current events being evaluated and can be processed in any order. it is illegal to write values to any net or variable or to schedule an event in any previous region within the current time slot. Re-inactive. Within this region. The Postponed region provides for a PLI callback control point that allows PLI application routines to be suspended until after all the Active. while (some time slot is nonempty) { move to the next future nonempty time slot and set T. 9. initialize the values of all nets and variables. Inactive. and Re-inactive regions have completed. Post-NBA. preponed pre-active active inactive pre-NBA NBA post-NBA observed post-observed reactive postponed time slot . NBA. The Preponed region provides for a PLI callback control point that allows PLI application routines to access data at the current time slot before any net or variable has changed state. NOTE—The PLI currently does not schedule callbacks in the Preponed region. Inactive. scheduled for the current or a later simulation time.3. Reactive. Pre-NBA. An explicit #0 delay control requires that the process be suspended and an event scheduled into the Inactive region (or Re-inactive for program blocks) of the current time slot so that the process can be resumed in the next inactive to active iteration. The Active.1 The SystemVerilog simulation reference algorithm execute_simulation { T = 0. Within this region. Observed. A nonblocking assignment creates an event in the NBA region. abstraction. Objects are key to understanding object-oriented technology. and identity. What are the types of coverages available in SV ? Using Cover Groups: Variables. What is OOPS? Brief Introduction To Oop Unlike procedural programming.switch off). encapsulation. In SystemVerilog OOPS . method. we first need to understand several fundamentals related to objects. expressions and their cross Using Cover Properties 8. Real-world objects share two characteristics: They all have state and behavior. The class definition describes all the properties. color) and behavior (playing music. Object . and identity of objects present within that class. Class It is the central point of OOP and that contains data and codes with behavior. here in the OOP programming model programs are organized around objects and data rather than actions and logic. In OOP based language the principal aim is to find out the objects to manipulate and their relation between each other. properties. Look around right now and you'll find many examples of real-world objects: your system. everything happens within class and it describes a set of objects with common behavior. your desk. OOP offers greater flexibility and compatibility then procedural language like verilog. Objects represent some concepts or things and like any other objects in the real Objects in programming language have certain behavior. SystemVerilog is a object oriented programming and to understand the functionality of OOP in SystemVerilog.from previous time slot to next time slot region PLI region Legend: re-inactive pre-postponed 7. inheritance. polymorphism etc. your chair. System have state (name. behavior. Identifying the state and behavior for real-world objects is a great way to begin thinking in terms of object-oriented programming. type. These include class. Though objects are distinguished from each other by some additional features but there are objects that share certain things common. Again these variables and methods are distinguished from each other as instant variables. accurate coding and reduces development time. Methods We know that a class can define both attributes and behaviors. Inheritance This is the mechanism of organizing and structuring program. Abstraction The process of abstraction in SystemVerilog is used to hide certain details and only show the essential features of the object. to write a new definition using the exesisting definitioan is done inserting `ifdef conpilation controls into the exesisting code. An object is expressed by the variable and methods within the objects. private and protected . This helps in hiding an object's data describing its state from any further modification by external component. In other words. Encapsulation This is an important programming concept that assists in separating an object's state from its behavior. these are part of a class but are not the same. identity. As we know an object can associated with data with predefined classes and in any application an object can know about the data it needs to know about.Objects are the basic unit of object orientation with behavior. This helps in a better data analysis. This saves work as the special class inherits all the properties of the old general class and as a programmer you only require the new features. In SystemVerilog there are three different terms used for hiding data constructs and these are public. In object oriented programming classes can inherit some common behavior and state from others. In other words. Inheritance in OOP allows to define a general class and later to organize some other classes simply adding some details with the old class definition. In Verilog . As we mentioned above. it deals with the outside view of an object. It can also be termed as information hiding that prohibits outsiders in seeing the inside of an object in which abstraction is . instant methods and class variable and class methods. methods define the abilities of an object. So any unnecessary data are not required by an object can be hidden by this process. Again attributes are defined by variables and behaviors are represented by methods. Each of these packets might look very similar. A base class sets out the prototype for the subclasses. and satellite packets. along with their directions (via modports) and synchronization details (via clocking block). 9. One way to view this is that there is only one implementation of a virtual method per class hierarchy. a common base class of type BasePacket that sets out the structure of packets but is incomplete would never be instantiated. and it is always the one in the latest derived class. Virtual interface is a data type (that implies it can be instantiated in a class) which hold reference to an interface (that implies the class can drive the interface using the virtual interface). Because the base class is not intended to be instantiated. But they needed to be driven from verification environment like class. such as Ethernet packets. To solve this issue virtual interface concept was introduced in SV. but they could vary significantly in terms of their internal details. A virtual method overrides a method in all the base classes. Polymorphism It describes the ability of the object in belonging to different types with specific behavior of each type. But Interface can't be instantiated inside program block. one object can be treated like another and in this way it can create and define multiple level of interface. For example. and the return type if it is needed. virtual function integer send(bit[31:0] data). The major usage of interface is to simplify the connection between modules. What is the need of virtual interfaces ? An interface encapsulate a group of inter-related wires.. From this base class. class (or similar non-module entity in SystemVerilog).implemented. Abstract classes can also have virtual methods. a number of useful subclasses could be derived. 10. Another big advantage of virtual interface is that class can dynamically connect to different physical interfaces in run time. // body of the function . whereas a normal method only overrides a method in that class and its descendants. i. GPSS packets.e. function integer send(bit[31:0] data). It provides a mechanism for separating abstract models and test programs from the actual signals that make up the design. Here the programmers need not have to know the exact type of object in advance and this is being implemented at runtime. the type and number of arguments. Later. it can be made abstract by specifying the class to be virtual: virtual class BasePacket. A set of classes can be created that can be viewed as all being derived from a common base class. Virtual methods provide prototypes for subroutines. Thus. token ring packets. Explain Abstract classes and virtual methods. they must follow the prototype exactly. all needing the same set of methods. all versions of the virtual method look identical in all subclasses: virtual class BasePacket. when subclasses override virtual methods. So by using this. all of the information generally found on the first line of a method declaration: the encapsulation criteria. Virtual methods are a basic polymorphic construct. endfunction endclass class EtherPacket extends BasePacket. however. If any virtual methods have no implementation. endfunction endclass EtherPacket is now a class that can be instantiated.. if an abstract class has any virtual methods.. even though the compiler did not know—at compile time—what was going to be loaded into it. as virtual functions. it can still be used to declare a variable: BasePacket packets[100]. // extends BasePacket TokenPacket tp = new. Such methods include send. Now. it can be done. the method must have a body. // extends EtherPacket packets[0] = ep. an incomplete class).e. At run time. because the methods were declared as virtual. packets[1] packets[1]. In this case. the subclass needs to be abstract. bits. An abstract class can contain methods for which there is only a prototype and no implementation (i. and print. the system correctly binds the method from the appropriate class. Sometimes it make sense to only describe the properties of a set of objects without knowing the actual behaviour beforehand Abstract classes are those which can be used for creation of handles. Polymorphism: dynamic method lookup Polymorphism allows the use of a variable in the superclass to hold subclass objects and to reference the methods of those subclasses directly from the superclass variable. Even though BasePacket is abstract. Methods of normal classes can also be declared virtual. 11. In general. // extends BasePacket GPSSPacket gp = new. defines. BasePacket. EXAMPLE: useing abstract class . and strings. Consequently. An abstract class cannot be instantiated. instances of various packet objects can be created and put into the array: EtherPacket ep = new. In this example.. but with polymorphism. then the class can be instantiated. If the method does have a body. the appropriate subclass methods can be accessed from the superclass variable. If the data types were. it can only be derived. However their methods and constructors can be used by the child or extended class. all of these types could not be stored into a single array. all of the public methods that are to be generally used by its subclasses. for example. receive. As an example. packets[2] = gp. The need for abstract classes is that you can generalize the super class from which child classes can share its methods. assume the base class for the Packet objects. integers.. as can its subclasses. all of the methods must be overridden (and provided with a method body) for the subclass to be instantiated. The subclass of an abstract class which can create an object is called as "concrete class". For example. providing capabilities that are far more powerful than what is found in a nonobjectoriented framework. shall invoke the send method associated with the TokenPacket class. packets[1] = tp. This is a typical example of polymorphism at work. objects of a subclass behave like objects of their superclasses.send(). What is the use of the abstract class? With inheritance we are able to force a subclass to offer the same properties like their superclasses. endtask endclass program main . virtual task disp (). initial begin my_ea = new().disp(). virtual task disp (). A my_a. EA my_ea. my_ea. $display(" This is Extended class A "). my_a = my_ea. A my_a. end endprogram RESULT This is Extended class A This is Extended class A EXAMPLE: creating object of virtual class virtual class A . initial begin my_a = new(). end .disp(). endtask endclass program main . task disp (). my_a. endtask endclass class EA extends A . $display(" This is class A ").virtual class A . $display(" This is class A "). my_a.disp(). Thus from the abstract class point of view. The full definition including the semantics of the properties must be provided by derived classes. the properties are only specified but not fully defined. What data structure you used to build scoreboard Queue 14. 12. What are the advantages of linkedlist over the queue ? 15. Definition (Abstract Class) A class A is called abstract class if it is only used as a superclass for other classes. What is the difference between $random and $urandom? $random system function returns a 32-bit signed random number each time it is called . Derived classes must define the properties of A. What is the difference between pure function and cordinary function ? 17. Class A only specifies properties. How parallel case and full cases problems are avoided in SV 16. It is not used to create objects.endprogram RESULT Abstract class A cannot be instantiated Virtual keyword is used to express the fact that derived classes must redefine the properties to fulfill the desired functionality. What is the difference between mailbox and queue? 13. GREEN. Agreed. How to call the task which is defined in parent object into derived class ? 25. They can't be shared between two modules. What is $root? $root refers to the top level instance in SystemVerilog 1.before constraint ? . What is scope randomization 19. // Some typedef typedef enum {RED. What are bi-directional constraints? 29. It allows having global data/task/function declaration which can be used across modules. (newly added in SV.$urandom system function returns a 32-bit unsigned random number each time it is called. 3.2 of SV LRM 3. not present in verilog) 18.A. or using import (with option of referencing particular or all content of the package). // Some function void function do_nothing() endfunction : do_nothing // You can have many different declarations here endpackage : ABC // How to use them import ABC::Color. The package construct of SystemVerilog aims in solving the above issue. What is the difference between rand and randc? 26. 20.$root.. What is solve. // Import everything inside the package 23. What is the use of packages? 22. we can achieve the same via cross module referencing or by including the files.A. In Verilog declaration of data/task/function within modules are specific to the module only. package ABC. List the predefined randomization methods.1a ) The content inside the package can be accessed using either scope resolution operator (::). What is the dfference between always_combo and always@(*)? 21.C. It can contain module/class/function/task/constraints/covergroup and many more declarations (for complete list please refer section 18. YELLOW} Color.package ABC. What is $unit? 28. What is the use of $cast? 24. both of which are known to be not a great solution. 2.$root.B. // Just import Color import ABC::*.. A // top level instance A // item C within instance B within top level instance 27. printf(" i is changed to %d at %d\n". . Modules don't have any such restrictions. i = 2. and byte sig_2...i. the changes do not affect the caller. program variable can only be assigned using blocking assignment and non-program variables can only be assigned using non-blocking assignments. Inside a program block.int UniqVal[10]. 33..generate an array of unique values? ... Each subroutine retains a local copy of the argument.get_time(LO) ).30. modules. example: task pass(int i) // task pass(var int i) pass by reference { delay(10). endprogram) that specifies scheduling in the Reactive Region. 4. It separates testbench from DUT It helps in ensuring that testbench doesn't have any race condition with DUT It provides an entry point for execution of testbench It provides syntactic context (via program . printf(" i is changed to %d at %d\n". delay(10).UniqVal. What is the difference between program block and module ? Program block is newly added in SystemVerilog. It serves these purposes 1. In pass by reference functions and tasks directly access the specified variables passed as arguments. Program blocks can't contain UDP. or other instance of program block inside them. Without using randomize method or rand. 2. } 32.. 4. If the arguments are changed within the subroutine declaration.i. Explain about pass by ref and pass by value? Pass by value is the default method through which arguments are passed into functions and tasks. modules can have.foreach(UniqVal[i]) UniqVal[i] = i. 3. What is the difference between bit[7:0] sig_1.. i = 1.shuffle(). 5. 3. 31. Having said this the major difference between module and program blocks are Program blocks can't have always block inside them. 2.get_time(LO) ). byte is signed whereas bit [7:0] is unsigned. 2.Its like passing pointer of the variable. 3. No such restrictions on module 1. end end // Using forever : slightly complex but doable forever begin fork begin : reset_logic @ (negedge reset_). What is final block ? 35. 5. why not have a real useful post on fork/join{x} of SystemVerilog and its associated disable/wait command. SV substantially improved fork/join construct to have much more controllability in process creation. It is used for forking out parallel processes in test bench. destruction. and waiting for end of the process. end : reset_logic begin : clk_logic @ (posedge clk). Hence I thought. How to implement always block logic in program block ? Use of forever begin end. But a module can not call a task or function in a program. One interesting I am observing is that quite a few hit to my site is coming for fork/join interview questions in Google. Fork-join statement has come from Verilog. The basic syntax of fork join block looks like this: . fork/join_none fork/join_any ? I have added histstat hit counter for my blog to have an idea about traffic/visitor/search engine trends. 34. data <= '0. If it is a complex always block statement like always (@ posedge clk or negedge reset_) always @(posedge clk or negedge reset_) begin if(!reset_) begin data <= '0.4. What is the difference between fork/joins. end : clk_logic join_any disable fork end 36. else data <= data_next. end else begin data <= data_next. module blocks get executed in the active region A program can call a task or function in modules or other programs. Program blocks get executed in the re-active region of scheduling queue. if(!reset_) data <= '0. (For example. 37.// Code for 1st thread 04.join // Can be join_any. output z).// Code for 2nd thread 07.. in the last example if you want to kill only the 2nd thread after exiting the loop via join_any/join_none. you want to wait till completion of all the threads spanned by the previous fork loop. y.. 6. you want to kill just one thread (out of many). Now.endinterface Please refer section 19.interface my_intf.. What is the use of modports ? Modports are part of Interface.begin : Second_thread 06. y. have named begin end block and call "disable ".wire x. What is forward referencing and how to avoid this problem? 40.modport slave (output x.01.begin : First_thread 03.end 08. but lets the other process/thread execute as usual join_none : doesn't wait for completion of any thread. 2. 4. What is circular dependency and how to avoid this problem ? . Now. o o o join : waits for completion of all of the threads join_any : waits for the completion of the 1st thread. y. 3. 12." at the point where you want to disable the second thread. SV has "disable fork" for the same.4 of SV LRM for more details 38.end 11. Hope that will help understand this in a much better way. suppose you have exited the fork loop by join_none or join_any and after some steps.. 39. Modports are used for specifing the direction of the signals with respect to various modules the interface connects to. SV has "wait fork" for the same.// Code for 3rd branch 10. 1. each specifying a different way of waiting for completion of the threads/process created by the fork. just starts then and immediately exits fork loop. you want to killall the threads spanned by the previous fork loop. join_none in SV There are 3 different kind of join keyword in SV.modport master (input x. suppose you have exited the fork loop by join_none or join_any and after some steps. Write a clock generator without using always block.begin : Third thread 09. 5. input z).. The solution.end 05. then comes out of fork loop. Next interesting scenario: you have exited fork loop by join_none or join_any and after some steps.. I have created a image to pictorially depict fork/join in SV. then add "disable Second_thread.fork 02. z. What is cross coverage ? 42. Difference b/w Procedural and Concurrent Assertions? 46. Describe the difference between Code Coverage and Functional Coverage Which is more important and Why we need them Code Coverage indicates the how much of RTL has been exercised. // Constraining individual entry data[0] > 5. e. 47. e. it may not present the real features coverage. the functional coverage may miss some unused RTL coverage. On the other hand.41. With only Code Coverage. and efficient way to connect SystemVerilog and foreign language code unlike PLI or VPI. The Functional Coverage indicates which features or functions has been executed. 43. // Dynamic array rand bit [7:0] data []. In associative array. } endclass : ABC . 45. When the size of the collection is unknown or the data space is sparse. // All elements foreach(data[i]) if(i > 0) data[i] > data[i-1]. What are the advantages of SystemVerilog DPI? SystemVerilog introduces a new foreign language interface called the Direct Programming Interface (DPI). Both of them are very important. it uses the transaction names as the keys in associative array. an associative array is a better option. straightforward.g. // Constraints constraint cc { // Constraining size data.g. How to kill a process in fork/join? 44. The DPI provides a very simple.size inside {[1:10]}. How to randomize dynamic arrays of objects? class ABC. int array[string]. Difference between Associative array and Dynamic array ? 1) Difference between Associative array and Dynamic array ? Answer: Dynamic arrays are useful for dealing with contiguous collections of variables whose number changes dynamically. int array[]. What is the need to implement explicitly a copy() method inside a transaction . when we can simple assign one object to other ? 57. bit [0:2] y. Which is best to use to model transaction? Struct or class ? 52. Difference between assert and expect statements? 54. If the bin designates a sequence of value transitions. What is the difference between view source print? 1. covergroup cg. . program main. e. bit [0:2] values[$]= '{3. end endprogram 50. What is the need of alias in SV? 56. the count is incremented every time the coverage point matches one of the values in the set. cg_inst. What is tagged union ? 60. } endgroup cg cg_inst = new().6}. What is the difference between Verilog Parameterized Macros and SystemVerilog Parameterized Macros? 62. What is "this"? 59. What is randsequence and what is its use? 49. How SV is more random stable then Verilog? 53. the count is incremented every time the coverage point matches the entire sequence of value transitions.auto_bin_max = 4 . initial foreach(values[i]) begin y = values[i].sample(). cover_point_y : coverpoint y { option.logic data_1.5. How different is the implementation of a struct and union in SV. Why always block is not allowed in program block? 51.g. How to add a new processs with out disturbing the random number generator state ? 55. What is bin? A coverage-point bin associates a name and a count with a set of values or a sequence of value transitions. What is "scope resolution operator"? 61. 58.48. If the bin designates a set of values. 4. 5. How to check weather a handles is holding object or not ? . and Thanks for all the fishes"). which implies it can't have any delay. How to import all the items declared inside a package ? 76. What are void functions ? 79. 75. What is the difference between initial block and final block? There are many difference between initial and final block. What are the simulation phases in your verification environment? 72. 3.var bit data_5.bit data_4. or nonblocking assignments. Explain how the timescale unit and precision are taken when a module does not have any timescalerdeclaration in RTL? 77. 3.wire logic data_3j.end 82. 63. 4. 1.$display("Final value of xyz = %h". What is streaming operator and what is its use? 78. What is the use of "extern"? 81. The most obvious one : Initial blocks get executed at the beginning of the simulation. What is the difference between $rose and posedge? 66. final block at the end of simulation Final block has to be executed in zero time. wait. How to avoid the race condition between programblock ? 68. Write a Statemechine in SV styles. What is advantage of program block over clockcblock w.$display("Bye :: So long. I am listing the few differences that is coming to mind now.final begin 2. What data structure is used to store data in your environment and why ? 74.r.t race condition? 67. Initial block doesn't have any such restrictions of execution in zero time (and can have delay. What is coverage driven verification? 70.$display("Simulation Passed"). What is layered architecture ? 71. 65. What is casting? Explain about the various types of casting available in SV. What is the difference between assumes and assert? 69. 2.var logic data_2.2.xyz). wait and non-blocking statements) Final block can be used to display statistical/genaral information regarding the status of the execution like this:- 1. What is the difference between bits and logic? 64. How to pick a element which is in queue from random index? 73. 5. How to make sure that a function argument passed has ref is not changed by the function? 80. ..83. How to disable multiple threads which are spawned by fork.join .