STM32F103 Datasheet

September 2009 Doc ID 15060 Rev 3 1/801 STM32F103x4 STM32F103x6 Low-density performance line, ARM-based 32-bit MCU with 16 or 32 KB Flash, USB, CAN, 6 timers, 2 ADCs, 6 communication interfaces Features ■ Core: ARM 32-bit Cortex™-M3 CPU – 72 MHz maximum frequency, 1.25 DMIPS/MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division ■ Memories – 16 or 32 Kbytes of Flash memory – 6 or 10 Kbytes of SRAM ■ Clock, reset and supply management – 2.0 to 3.6 V application supply and I/Os – POR, PDR, and programmable voltage detector (PVD) – 4-to-16 MHz crystal oscillator – Internal 8 MHz factory-trimmed RC – Internal 40 kHz RC – PLL for CPU clock – 32 kHz oscillator for RTC with calibration ■ Low power – Sleep, Stop and Standby modes – V BAT supply for RTC and backup registers ■ 2 x 12-bit, 1 µs A/D converters (up to 16 channels) – Conversion range: 0 to 3.6 V – Dual-sample and hold capability – Temperature sensor ■ DMA – 7-channel DMA controller – Peripherals supported: timers, ADC, SPIs, I 2 Cs and USARTs ■ Up to 51 fast I/O ports – 26/37/51 I/Os, all mappable on 16 external interrupt vectors and almost all 5 V-tolerant ■ Debug mode – Serial wire debug (SWD) & JTAG interfaces ■ 6 timers – Two 16-bit timers, each with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input – 16-bit, motor control PWM timer with dead- time generation and emergency stop – 2 watchdog timers (Independent and Window) – SysTick timer: a 24-bit downcounter ■ 6 communication interfaces – 1 x I 2 C interface (SMBus/PMBus) – 2 × USARTs (ISO 7816 interface, LIN, IrDA capability, modem control) – 1 × SPI (18 Mbit/s) – CAN interface (2.0B Active) – USB 2.0 full-speed interface ■ CRC calculation unit, 96-bit unique ID ■ Packages are ECOPACK ® Table 1. Device summary Reference Part number STM32F103x4 STM32F103C4, STM32F103R4, STM32F103T4 STM32F103x6 STM32F103C6, STM32F103R6, STM32F103T6 LQFP64 (10 × 10 mm) LQFP48 (7 × 7 mm) TFBGA64 (5 × 5 mm VFQFPN36 (6 × 6 mm) www.st.com Contents STM32F103x4, STM32F103x6 2/80 Doc ID 15060 Rev 3 Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.1 ARM ® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 13 2.3.2 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.3 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 13 2.3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.5 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 13 2.3.6 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.7 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.8 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.9 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.10 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.11 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.12 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3.13 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.14 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 16 2.3.15 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.16 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.17 Universal synchronous/asynchronous receiver transmitter (USART) . . 18 2.3.18 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.19 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.20 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.21 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.22 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.23 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.24 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 STM32F103x4, STM32F103x6 Contents Doc ID 15060 Rev 3 3/80 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 31 5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 31 5.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 5.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.3.11 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 51 5.3.12 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.3.13 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.3.14 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3.15 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.3.16 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 5.3.18 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.2.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.2.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 75 7 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Contents STM32F103x4, STM32F103x6 4/80 Doc ID 15060 Rev 3 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 STM32F103x4, STM32F103x6 List of tables Doc ID 15060 Rev 3 5/80 List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. STM32F103xx low-density device features and peripheral counts. . . . . . . . . . . . . . . . . . . . 9 Table 3. STM32F103xx family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 4. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5. Low-density STM32F103xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 6. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 7. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 8. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 9. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 10. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 11. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 12. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 13. Maximum current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 14. Maximum current consumption in Run mode, code with data processing running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 15. Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 36 Table 16. Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 37 Table 17. Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 18. Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 19. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 20. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 21. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 22. HSE 4-16 MHz oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 23. LSE oscillator characteristics (f LSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 24. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 25. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 26. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 27. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 28. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 29. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 30. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 31. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 32. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 33. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Table 34. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 35. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 36. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 37. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 38. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 39. I 2 C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 40. SCL frequency (f PCLK1 = 36 MHz.,V DD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 41. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 42. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 43. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 44. USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 List of tables STM32F103x4, STM32F103x6 6/80 Doc ID 15060 Rev 3 Table 45. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 46. R AIN max for f ADC = 14 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 47. ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 48. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 49. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 50. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 69 Table 51. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . . 70 Table 52. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data. . . 71 Table 53. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . . 73 Table 54. Package thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 55. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 STM32F103x4, STM32F103x6 List of figures Doc ID 15060 Rev 3 7/80 List of figures Figure 1. STM32F103xx performance line block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 3. STM32F103xx performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 4. STM32F103xx performance line TFBGA64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 5. STM32F103xx performance line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 6. STM32F101xx Medium-density access line VFQFPN36 pinout . . . . . . . . . . . . . . . . . . . . . 22 Figure 7. Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 8. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 9. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 10. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 11. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 35 Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 35 Figure 14. Typical current consumption on V BAT with RTC on versus temperature at different V BAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 15. Typical current consumption in Stop mode with regulator in Run mode versus temperature at V DD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 16. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at V DD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 17. Typical current consumption in Standby mode versus temperature at V DD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 18. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 19. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 20. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 21. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 22. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 23. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Figure 24. I 2 C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 25. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 26. SPI timing diagram - slave mode and CPHA = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figure 27. SPI timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 28. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 29. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 30. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 31. Power supply and reference decoupling (V REF+ not connected to V DDA ). . . . . . . . . . . . . . 66 Figure 32. Power supply and reference decoupling(V REF+ connected to V DDA ) . . . . . . . . . . . . . . . . . 67 Figure 33. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 34. Recommended footprint (dimensions in mm) (1)(2)(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 35. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 70 Figure 36. Recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 37. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline . . . . . . . . . . 71 Figure 38. Recommended PCB design rules for pads (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . . 72 Figure 39. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . 73 Figure 40. Recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 41. LQFP64 P D max vs. T A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Introduction STM32F103x4, STM32F103x6 8/80 Doc ID 15060 Rev 3 1 Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F103x4 and STM32F103x6 low-density performance line microcontrollers. For more details on the whole STMicroelectronics STM32F103xx family, please refer to Section 2.2: Full compatibility throughout the family. The low-density STM32F103xx datasheet should be read in conjunction with the low-, medium- and high-density STM32F10xxx reference manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.st.com. For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical Reference Manual, available from the www.arm.com website at the following address: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/. 2 Description The STM32F103x4 and STM32F103x6 performance line family incorporates the high- performance ARM Cortex™-M3 32-bit RISC core operating at a 72 MHz frequency, high- speed embedded memories (Flash memory up to 32 Kbytes and SRAM up to 6 Kbytes), and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All devices offer two 12-bit ADCs, three general purpose 16-bit timers plus one PWM timer, as well as standard and advanced communication interfaces: up to two I 2 Cs and SPIs, three USARTs, an USB and a CAN. The STM32F103xx low-density performance line family operates from a 2.0 to 3.6 V power supply. It is available in both the –40 to +85 °C temperature range and the –40 to +105 °C extended temperature range. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F103xx low-density performance line family includes devices in four different package types: from 36 pins to 64 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the STM32F103xx low-density performance line microcontroller family suitable for a wide range of applications: ● Motor drive and application control ● Medical and handheld equipment ● PC peripherals gaming and GPS platforms ● Industrial applications: PLC, inverters, printers, and scanners ● Alarm systems, Video intercom, and HVAC STM32F103x4, STM32F103x6 Description Doc ID 15060 Rev 3 9/80 2.1 Device overview Table 2. STM32F103xx low-density device features and peripheral counts Peripheral STM32F103Tx STM32F103Cx STM32F103Rx Flash - Kbytes 16 32 16 32 16 32 SRAM - Kbytes 6 10 6 10 6 10 T i m e r s General-purpose 2 2 2 2 2 2 Advanced-control 1 1 1 C o m m u n i c a t i o n SPI 1 1 1 1 1 1 I 2 C 1 1 1 1 1 1 USART 2 2 2 2 2 2 USB 1 1 1 1 1 1 CAN 1 1 1 1 1 1 GPIOs 26 37 51 12-bit synchronized ADC Number of channels 2 10 channels 2 10 channels 2 16 channels CPU frequency 72 MHz Operating voltage 2.0 to 3.6 V Operating temperatures Ambient temperatures: –40 to +85 °C /–40 to +105 °C (see Table 9) Junction temperature: –40 to + 125 °C (see Table 9) Packages VFQFPN36 LQFP48 LQFP64, TFBGA64 Description STM32F103x4, STM32F103x6 10/80 Doc ID 15060 Rev 3 Figure 1. STM32F103xx performance line block diagram 1. T A = –40 °C to +105 °C (junction temperature up to 125 °C). 2. AF = alternate function on I/O port pin. PA[ 15:0] EXTI WWD G 12bit ADC1 16 AF V REF+ JTDI JTCK/SWCLK JTMS/SWDIO NJTRST JTDO NRST V DD = 2 to 3.6V 51AF PB[ 15:0] PC[15:0] AHB2 SRAM WAKEUP GPIOA GPIOB GPIOC F max : 7 2 MHz V SS GP DMA TIM2 TIM3 XTAL OSC 4-16 MHz XTAL 32 kHz OSC_IN OSC_OUT OSC32_OUT OSC32_IN PLL & A P B 1 : F m a x = 2 4 / 3 6 M H z PCLK1 HCLK CLOCK MANAGT PCLK2 Flash 32 KB VOLT. REG. 3.3V TO 1.8V POWER Backup i nterf ace as AF B u s M a t r i x 64 bit 10KB RTC RC 8 MHz Cortex-M3 CPU Ibus Dbus pbus o b l F l a s h i n t e r f a c e SRAM 512B Trace Controlle r USART1 USART2 7 channels Backup reg 4 Channels TIM1 3 compl. channels SCL,SDA,SMBA I2C as AF Temp sensor PD[2:0] GPIOD A H B : F m a x = 4 8 / 7 2 M H z ETR and BKIN 4 Channels 4 Channels FCLK RC 40 kHz Stand by IWDG @VBAT POR / PDR SUPPLY @VDDA VDDA VSSA @VDDA V BAT RX,TX, CTS, RTS, Smart Card as AF RX,TX, CTS, RTS, CK, SmartCard as AF A P B 2 : F m a x = 4 8 / 7 2 M H z NVIC SPI MOSI,MISO, SCK,NSS as AF 12bi t ADC2 IF IF IF interface @VDDA SUPERVISION PVD Rst Int @VDD AHB2 APB2 APB1 AWU TAMPER-RTC @VDD Syst em ai15175c TRACECLK TRACED[0:3] as AS SW/JTAG TPIU Trace/trig USBDP/CAN_TX bxCAN USB 2.0 FS USBDM/CAN_RX STM32F103x4, STM32F103x6 Description Doc ID 15060 Rev 3 11/80 Figure 2. Clock tree 1. When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz. 2. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either 48 MHz or 72 MHz. 3. To have an ADC conversion time of 1 µs, APB2 must be at 14 MHz, 28 MHz or 56 MHz. HSE OSC 4-16 MHz OSC_IN OSC_OUT OSC32_IN OSC32_OUT LSE OSC 32.768 kHz HSI RC 8 MHz LSI RC 40 kHz to Independent Watchdog (IWDG) PLL x2, x3, x4 PLLMUL Legend: MCO Clock Output Main PLLXTPRE /2 ..., x16 AHB Prescaler /1, 2..512 /2 PLLCLK HSI HSE APB1 Prescaler /1, 2, 4, 8, 16 ADC Prescaler /2, 4, 6, 8 ADCCLK PCLK1 HCLK PLLCLK to AHB bus, core, memory and DMA USBCLK to USB interface to TIM2, TIM3 USB Prescaler /1, 1.5 to ADC LSE LSI HSI /128 /2 HSI HSE peripherals to APB1 Peripheral Clock Enable (13 bits) Enable (3 bits) Peripheral Clock APB2 Prescaler /1, 2, 4, 8, 16 PCLK2 to TIM1 peripherals to APB2 Peripheral Clock Enable (11 bits) Enable (1 bit) Peripheral Clock 48 MHz 72 MHz max 72 MHz 72 MHz max 36 MHz max to RTC PLLSRC SW MCO CSS to Cortex System timer /8 Clock Enable (3 bits) SYSCLK max RTCCLK RTCSEL[1:0] TIM1CLK TIMXCLK IWDGCLK SYSCLK FCLK Cortex free running clock TIM2, TIM3 If (APB1 prescaler =1) x1 else x2 TIM1 timer If (APB2 prescaler =1) x1 else x2 HSE = high-speed external clock signal HSI = high-speed internal clock signal LSI = low-speed internal clock signal LSE = low-speed external clock signal ai15176 Description STM32F103x4, STM32F103x6 12/80 Doc ID 15060 Rev 3 2.2 Full compatibility throughout the family The STM32F103xx is a complete family whose members are fully pin-to-pin, software and feature compatible. In the reference manual, the STM32F103x4 and STM32F103x6 are identified as low-density devices, the STM32F103x8 and STM32F103xB are referred to as medium-density devices, and the STM32F103xC, STM32F103xD and STM32F103xE are referred to as high-density devices. Low- and high-density devices are an extension of the STM32F103x8/B devices, they are specified in the STM32F103x4/6 and STM32F103xC/D/E datasheets, respectively. Low- density devices feature lower Flash memory and RAM capacities, less timers and peripherals. High-density devices have higher Flash memory and RAM capacities, and additional peripherals like SDIO, FSMC, I 2 S and DAC, while remaining fully compatible with the other members of the STM32F103xx family. The STM32F103x4, STM32F103x6, STM32F103xC, STM32F103xD and STM32F103xE are a drop-in replacement for STM32F103x8/B medium-density devices, allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. Moreover, the STM32F103xx performance line family is fully compatible with all existing STM32F101xx access line and STM32F102xx USB access line devices. Table 3. STM32F103xx family Pinout Low-density devices Medium-density devices High-density devices 16 KB Flash 32 KB Flash (1) 1. For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7), the reference datasheet for electrical characteristics is that of the STM32F103x8/B medium-density devices. 64 KB Flash 128 KB Flash 256 KB Flash 384 KB Flash 512 KB Flash 6 KB RAM 10 KB RAM 20 KB RAM 20 KB RAM 48 KB RAM 64 KB RAM 64 KB RAM 144 5 × USARTs 4 × 16-bit timers, 2 × basic timers 3 × SPIs, 2 × I 2 Ss, 2 × I2Cs USB, CAN, 2 × PWM timers 3 × ADCs, 2 × DACs, 1 × SDIO FSMC (100 and 144 pins) 100 3 × USARTs 3 × 16-bit timers 2 × SPIs, 2 × I 2 Cs, USB, CAN, 1 × PWM timer 2 × ADCs 64 2 × USARTs 2 × 16-bit timers 1 × SPI, 1 × I 2 C, USB, CAN, 1 × PWM timer 2 × ADCs 48 36 STM32F103x4, STM32F103x6 Description Doc ID 15060 Rev 3 13/80 2.3 Overview 2.3.1 ARM ® Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The STM32F103xx performance line family having an embedded ARM core, is therefore compatible with all ARM tools and software. Figure 1 shows the general block diagram of the device family. 2.3.2 Embedded Flash memory 16 or 32 Kbytes of embedded Flash is available for storing programs and data. 2.3.3 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location. 2.3.4 Embedded SRAM Six or ten Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. 2.3.5 Nested vectored interrupt controller (NVIC) The STM32F103xx performance line embeds a nested vectored interrupt controller able to handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) and 16 priority levels. ● Closely coupled NVIC gives low-latency interrupt processing ● Interrupt entry vector table address passed directly to the core ● Closely coupled NVIC core interface ● Allows early processing of interrupts ● Processing of late arriving higher priority interrupts ● Support for tail-chaining ● Processor state automatically saved ● Interrupt entry restored on interrupt exit with no instruction overhead Description STM32F103x4, STM32F103x6 14/80 Doc ID 15060 Rev 3 This hardware block provides flexible interrupt management features with minimal interrupt latency. 2.3.6 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. Each line can be independently configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 51 GPIOs can be connected to the 16 external interrupt lines. 2.3.7 Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal, resonator or oscillator). Several prescalers allow the configuration of the AHB frequency, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the high-speed APB domains is 72 MHz. The maximum allowed frequency of the low-speed APB domain is 36 MHz. See Figure 2 for details on the clock tree. 2.3.8 Boot modes At startup, boot pins are used to select one of three boot options: ● Boot from User Flash ● Boot from System Memory ● Boot from embedded SRAM The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1. For further details please refer to AN2606. 2.3.9 Power supply schemes ● V DD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through V DD pins. ● V SSA , V DDA = 2.0 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs and PLL (minimum voltage to be applied to V DDA is 2.4 V when the ADC is used). V DDA and V SSA must be connected to V DD and V SS , respectively. ● V BAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when V DD is not present. For more details on how to connect power pins, refer to Figure 10: Power supply scheme. 2.3.10 Power supply supervisor The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is always active, and ensures proper operation starting from/down to 2 V. The device remains STM32F103x4, STM32F103x6 Description Doc ID 15060 Rev 3 15/80 in reset mode when V DD is below a specified threshold, V POR/PDR , without the need for an external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the V DD /V DDA power supply and compares it to the V PVD threshold. An interrupt can be generated when V DD /V DDA drops below the V PVD threshold and/or when V DD /V DDA is higher than the V PVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. Refer to Table 11: Embedded reset and power control block characteristics for the values of V POR/PDR and V PVD . 2.3.11 Voltage regulator The regulator has three operation modes: main (MR), low power (LPR) and power down. ● MR is used in the nominal regulation mode (Run) ● LPR is used in the Stop mode ● Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset. It is disabled in Standby mode, providing high impedance output. 2.3.12 Low-power modes The STM32F103xx performance line supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ● Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. ● Stop mode The Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the RTC alarm or the USB wakeup. ● Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin, or an RTC alarm occurs. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop or Standby mode. Description STM32F103x4, STM32F103x6 16/80 Doc ID 15060 Rev 3 2.3.13 DMA The flexible 7-channel general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with support for software trigger on each channel. Configuration is made by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I 2 C, USART, general-purpose and advanced-control timers TIMx and ADC. 2.3.14 RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on V DD supply when present or through the V BAT pin. The backup registers are ten 16-bit registers used to store 20 bytes of user application data when V DD power is not present. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function, and provides an alarm interrupt and a periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power RC oscillator or the high-speed external clock divided by 128. The internal low-power RC has a typical frequency of 40 kHz. The RTC can be calibrated using an external 512 Hz output to compensate for any natural crystal deviation. The RTC features a 32-bit programmable counter for long-term measurement using the Compare register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32.768 kHz. 2.3.15 Timers and watchdogs The low-density STM32F101xx performance line devices include an advanced-control timer, two general-purpose timers, two watchdog timers and a SysTick timer. Table 4 compares the features of the advanced-control and general-purpose timers. Table 4. Timer feature comparison Timer Counter resolution Counter type Prescaler factor DMA request generation Capture/compare channels Complementary outputs TIM1 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 Yes TIM2, TIM3 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 No STM32F103x4, STM32F103x6 Description Doc ID 15060 Rev 3 17/80 Advanced-control timer (TIM1) The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels. It has complementary PWM outputs with programmable inserted dead-times. It can also be seen as a complete general-purpose timer. The 4 independent channels can be used for ● Input capture ● Output compare ● PWM generation (edge- or center-aligned modes) ● One-pulse mode output If configured as a general-purpose 16-bit timer, it has the same features as the TIMx timer. If configured as the 16-bit PWM generator, it has full modulation capability (0-100%). In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switch driven by these outputs. Many features are shared with those of the general-purpose TIM timers which have the same architecture. The advanced-control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining. General-purpose timers (TIMx) There are up to two synchronizable general-purpose timers embedded in the STM32F103xx performance line devices. These timers are based on a 16-bit auto-reload up/down counter, a 16-bit prescaler and feature 4 independent channels each for input capture/output compare, PWM or one-pulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages. The general-purpose timers can work together with the advanced-control timer via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. They all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. The counter can be frozen in debug mode. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. Description STM32F103x4, STM32F103x6 18/80 Doc ID 15060 Rev 3 SysTick timer This timer is dedicated for OS, but could also be used as a standard downcounter. It features: ● A 24-bit downcounter ● Autoreload capability ● Maskable system interrupt generation when the counter reaches 0 ● Programmable clock source 2.3.16 I²C bus The I²C bus interface can operate in multimaster and slave modes. It can support standard and fast modes. It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. A hardware CRC generation/verification is embedded. It can be served by DMA and they support SM Bus 2.0/PM Bus. 2.3.17 Universal synchronous/asynchronous receiver transmitter (USART) One of the USART interfaces is able to communicate at speeds of up to 4.5 Mbit/s. The other available interface communicates at up to 2.25 Mbit/s. They provide hardware management of the CTS and RTS signals, IrDA SIR ENDEC support, are ISO 7816 compliant and have LIN Master/Slave capability. All USART interfaces can be served by the DMA controller. 2.3.18 Serial peripheral interface (SPI) The SPI interface is able to communicate up to 18 Mbits/s in slave and master modes in full- duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. The SPI interface can be served by the DMA controller. 2.3.19 Controller area network (CAN) The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks. 2.3.20 Universal serial bus (USB) The STM32F103xx performance line embeds a USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). STM32F103x4, STM32F103x6 Description Doc ID 15060 Rev 3 19/80 2.3.21 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high-current- capable except for analog inputs. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. I/Os on APB2 with up to 18 MHz toggling speed 2.3.22 ADC (analog-to-digital converter) Two 12-bit analog-to-digital converters are embedded into STM32F103xx performance line devices and each ADC shares up to 16 external channels, performing conversions in single- shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. Additional logic functions embedded in the ADC interface allow: ● Simultaneous sample and hold ● Interleaved sample and hold ● Single shunt The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers (TIMx) and the advanced-control timer (TIM1) can be internally connected to the ADC start trigger, injection trigger, and DMA trigger respectively, to allow the application to synchronize A/D conversion and timers. 2.3.23 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. The conversion range is between 2 V < V DDA < 3.6 V. The temperature sensor is internally connected to the ADC12_IN16 input channel which is used to convert the sensor output voltage into a digital value. 2.3.24 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared with SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. Pinouts and pin description STM32F103x4, STM32F103x6 20/80 Doc ID 15060 Rev 3 3 Pinouts and pin description Figure 3. STM32F103xx performance line LQFP64 pinout 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 29 30 31 32 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0 OSC_IN PD1 OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2 V D D _ 3 V S S _ 3 P B 9 P B 8 B O O T 0 P B 7 P B 6 P B 5 P B 4 P B 3 P D 2 P C 1 2 P C 1 1 P C 1 0 P A 1 5 P A 1 4 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 P A 3 V S S _ 4 V D D _ 4 P A 4 P A 5 P A 6 P A 7 P C 4 P C 5 P B 0 P B 1 P B 2 P B 1 0 P B 1 1 V S S _ 1 V D D _ 1 LQFP64 ai14392 STM32F103x4, STM32F103x6 Pinouts and pin description Doc ID 15060 Rev 3 21/80 Figure 4. STM32F103xx performance line TFBGA64 ballout AI15494 PB2 PC14- OSC32_IN PA7 PA4 PA2 PA15 PB11 PB1 PA6 PA3 H PB10 PC5 PC4 D PA8 PA9 BOOT0 PB8 C PC9 PA11 PB6 PC12 V DDA PB9 B PA12 PC10 PC15- OSC32_OUT PB3 PD2 A 8 7 6 5 4 3 2 1 V SS_4 OSC_IN OSC_OUT V DD_4 G F E PC2 V REF+ PC13- TAMPER-RTC PB4 PA13 PA14 PB7 PB5 V SS_3 PC7 PC8 PC0 NRST PC1 PB0 PA5 PB14 V DD_2 V DD_3 PB13 V BAT PC11 PA10 V SS_2 V SS_1 PC6 V SSA PA1 V DD_1 PB15 PB12 PA0-WKUP Pinouts and pin description STM32F103x4, STM32F103x6 22/80 Doc ID 15060 Rev 3 Figure 5. STM32F103xx performance line LQFP48 pinout Figure 6. STM32F101xx Medium-density access line VFQFPN36 pinout 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 48 47 46 45 P A 3 P A 4 P A 5 P A 6 P A 7 P B 0 P B 1 P B 2 P B 1 0 P B 1 1 V S S _ 1 V D D _ 1 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0-OSC_IN PD1-OSC_OUT NRST VSSA VDDA PA0-WKUP PA1 PA2 V D D _ 3 V S S _ 3 P B 9 P B 8 B O O T 0 P B 7 P B 6 P B 5 P B 4 P B 3 P A 1 5 P A 1 4 LQFP48 ai14393b V S S _ 3 B O O T 0 P B 7 P B 6 P B 5 P B 4 P B 3 P A 1 5 P A 1 4 36 35 34 33 32 31 30 29 28 V DD_3 1 27 V DD_2 OSC_IN/PD0 2 26 V SS_2 OSC_OUT/PD1 3 25 PA13 NRST 4 QFN36 24 PA12 V SSA 5 23 PA11 V DDA 6 22 PA10 PA0-WKUP 7 21 PA9 PA1 8 20 PA8 PA2 9 19 V DD_1 10 11 12 13 14 15 16 17 18 P A 3 P A 4 P A 5 P A 6 P A 7 P B 0 P B 1 P B 2 V S S _ 1 ai14654 STM32F103x4, STM32F103x6 Pinouts and pin description Doc ID 15060 Rev 3 23/80 Table 5. Low-density STM32F103xx pin definitions Pins Pin name T y p e ( 1 ) I / O L e v e l ( 2 ) Main function (3) (after reset) Alternate functions (4) L Q F P 4 8 L Q F P 6 4 T F B G A 6 4 V F Q F P N 3 6 Default Remap 1 1 B2 - V BAT S V BAT 2 2 A2 - PC13-TAMPER- RTC (5) I/O PC13 (6) TAMPER-RTC 3 3 A1 - PC14-OSC32_IN (5) I/O PC14 (6) OSC32_IN 4 4 B1 - PC15- OSC32_OUT (5) I/O PC15 (6) OSC32_OUT 5 5 C1 2 OSC_IN I OSC_IN 6 6 D1 3 OSC_OUT O OSC_OUT 7 7 E1 4 NRST I/O NRST - 8 E3 - PC0 I/O PC0 ADC12_IN10 - 9 E2 - PC1 I/O PC1 ADC12_IN11 - 10 F2 - PC2 I/O PC2 ADC12_IN12 - 11 - - PC3 I/O PC3 ADC12_IN13 - - G1 - V REF+ (7) S V REF+ 8 12 F1 5 V SSA S V SSA 9 13 H1 6 V DDA S V DDA 10 14 G2 7 PA0-WKUP I/O PA0 WKUP/USART2_CTS/ ADC12_IN0/ TIM2_CH1_ETR (8) 11 15 H2 8 PA1 I/O PA1 USART2_RTS/ ADC12_IN1/ TIM2_CH2 (8) 12 16 F3 9 PA2 I/O PA2 USART2_TX/ ADC12_IN2/ TIM2_CH3 (8) 13 17 G3 10 PA3 I/O PA3 USART2_RX/ ADC12_IN3/TIM2_CH4 (8) - 18 C2 - V SS_4 S V SS_4 - 19 D2 - V DD_4 S V DD_4 14 20 H3 11 PA4 I/O PA4 SPI1_NSS (8) / USART2_CK/ADC12_IN4 15 21 F4 12 PA5 I/O PA5 SPI1_SCK (8) / ADC12_IN5 16 22 G4 13 PA6 I/O PA6 SPI1_MISO (8) / ADC12_IN6/TIM3_CH1 (8) TIM1_BKIN 17 23 H4 14 PA7 I/O PA7 SPI1_MOSI (8) / ADC12_IN7/TIM3_CH2 (8) TIM1_CH1N - 24 H5 PC4 I/O PC4 ADC12_IN14 Pinouts and pin description STM32F103x4, STM32F103x6 24/80 Doc ID 15060 Rev 3 - 25 H6 PC5 I/O PC5 ADC12_IN15 18 26 F5 15 PB0 I/O PB0 ADC12_IN8/TIM3_CH3 (8) TIM1_CH2N 19 27 G5 16 PB1 I/O PB1 ADC12_IN9/TIM3_CH4 (8) TIM1_CH3N 20 28 G6 17 PB2 I/O FT PB2/BOOT1 21 29 G7 - PB10 I/O FT PB10 TIM2_CH3 22 30 H7 - PB11 I/O FT PB11 TIM2_CH4 23 31 D6 18 V SS_1 S V SS_1 24 32 E6 19 V DD_1 S V DD_1 25 33 H8 - PB12 I/O FT PB12 TIM1_BKIN (8) 26 34 G8 - PB13 I/O FT PB13 TIM1_CH1N (8) 27 35 F8 - PB14 I/O FT PB14 TIM1_CH2N (8) 28 36 F7 - PB15 I/O FT PB15 TIM1_CH3N (8) - 37 F6 - PC6 I/O FT PC6 TIM3_CH1 38 E7 - PC7 I/O FT PC7 TIM3_CH2 39 E8 - PC8 I/O FT PC8 TIM3_CH3 - 40 D8 - PC9 I/O FT PC9 TIM3_CH4 29 41 D7 20 PA8 I/O FT PA8 USART1_CK/ TIM1_CH1/MCO 30 42 C7 21 PA9 I/O FT PA9 USART1_TX (8) / TIM1_CH2 (8) 31 43 C6 22 PA10 I/O FT PA10 USART1_RX (8) / TIM1_CH3 32 44 C8 23 PA11 I/O FT PA11 USART1_CTS/ CAN_RX (8) / TIM1_CH4 / USBDM 33 45 B8 24 PA12 I/O FT PA12 USART1_RTS/ CAN_TX (8) / TIM1_ETR / USBDP 34 46 A8 25 PA13 I/O FT JTMS/SWDIO PA13 35 47 D5 26 V SS_2 S V SS_2 36 48 E5 27 V DD_2 S V DD_2 37 49 A7 28 PA14 I/O FT JTCK/SWCLK PA14 38 50 A6 29 PA15 I/O FT JTDI TIM2_CH1_ETR/ PA15 / SPI1_NSS - 51 B7 PC10 I/O FT PC10 - 52 B6 PC11 I/O FT PC11 - 53 C5 PC12 I/O FT PC12 Table 5. Low-density STM32F103xx pin definitions (continued) Pins Pin name T y p e ( 1 ) I / O L e v e l ( 2 ) Main function (3) (after reset) Alternate functions (4) L Q F P 4 8 L Q F P 6 4 T F B G A 6 4 V F Q F P N 3 6 Default Remap STM32F103x4, STM32F103x6 Pinouts and pin description Doc ID 15060 Rev 3 25/80 5 5 C1 2 PD0 I/O FT OSC_IN (9) 6 6 D1 3 PD1 I/O FT OSC_OUT (9) 54 B5 - PD2 I/O FT PD2 TIM3_ETR 39 55 A5 30 PB3 I/O FT JTDO TIM2_CH2 / PB3/ TRACESWO SPI1_SCK 40 56 A4 31 PB4 I/O FT NJTRST TIM3_CH1 /PB4 SPI1_MISO 41 57 C4 32 PB5 I/O PB5 I2C1_SMBA TIM3_CH2 / SPI1_MOSI 42 58 D3 33 PB6 I/O FT PB6 I2C1_SCL (8) / USART1_TX 43 59 C3 34 PB7 I/O FT PB7 I2C1_SDA (8) USART1_RX 44 60 B4 35 BOOT0 I BOOT0 45 61 B3 - PB8 I/O FT PB8 I2C1_SCL /CAN_RX 46 62 A3 - PB9 I/O FT PB9 I2C1_SDA / CAN_TX 47 63 D4 36 V SS_3 S V SS_3 48 64 E4 1 V DD_3 S V DD_3 1. I = input, O = output, S = supply. 2. FT = 5 V tolerant. 3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1 and USART1 & USART2, respectively. Refer to Table 2 on page 9. 4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). 5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED). 6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 7. Unlike in the LQFP64 package, there is no PC3 in the TFBGA64 package. The V REF+ functionality is provided instead. 8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual, available from the STMicroelectronics website: www.st.com. 9. The pins number 2 and 3 in the VFQFPN36 package, 5 and 6 in the LQFP48 and LQFP64 packages and C1 and C2 in the TFBGA64 package are configured as OSC_IN/OSC_OUT after reset, however the functionality of PD0 and PD1 can be remapped by software on these pins. For more details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. Table 5. Low-density STM32F103xx pin definitions (continued) Pins Pin name T y p e ( 1 ) I / O L e v e l ( 2 ) Main function (3) (after reset) Alternate functions (4) L Q F P 4 8 L Q F P 6 4 T F B G A 6 4 V F Q F P N 3 6 Default Remap Memory mapping STM32F103x4, STM32F103x6 26/80 Doc ID 15060 Rev 3 4 Memory mapping The memory map is shown in Figure 7. Figure 7. Memory map reserved 0x4000 0000 0x4000 0400 0x4000 0800 0x4000 2800 0x4000 2C00 0x4000 3000 0x4000 3400 0x4000 4400 0x4000 4800 0x4001 0C00 0x4001 1000 0x4001 1400 0x4001 1800 0x4002 1400 APB memory space DMA 0x4002 1000 TIM2 Reserved 0x4001 0800 0x4001 2400 0x4001 2800 0x4001 2C00 0x4001 3000 0x4001 3400 0x4001 3800 TIM3 RTC WWDG IWDG USART2 AFIO Port A Port C Port D reserved ADC1 reserved USART1 reserved 0x4002 0400 0x4002 0000 0x4001 3C00 0x4000 5400 0x4000 5800 ADC2 TIM1 SPI reserved I2C BKP 0x4000 6000 0x4000 5C00 PWR Port B reserved bxCAN EXTI reserved RCC reserved Flash Interface reserved 0x4000 6400 0x4000 6800 0x4000 6C00 0x4000 7000 0x4000 7400 0x4001 0000 0x4001 0400 0x4002 2000 0x4002 2400 0x4002 3000 0x4002 3400 0xFFFF FFFF USB Registers CRC 0 1 2 3 4 5 6 7 0x2000 0000 0x4000 0000 0x6000 0000 0x8000 0000 0xA000 0000 0xC000 0000 0xE000 0000 0xFFFF FFFF 0x0000 0000 Peripherals SRAM Flash memory reserved reserved 0x0800 0000 0x0801 FFFF 0x1FFF F000 0x1FFF FFFF System memory Option Bytes 0x1FFF F800 0x1FFF F80F Cortex-M3 Internal Peripherals 0xE010 0000 ai15177c shared 512 byte USB/CAN SRAM Aliased to Flash or system memory depending on BOOT pins 0x0000 0000 reserved reserved reserved reserved STM32F103x4, STM32F103x6 Electrical characteristics Doc ID 15060 Rev 3 27/80 5 Electrical characteristics 5.1 Parameter conditions Unless otherwise specified, all voltages are referenced to V SS . 5.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T A = 25 °C and T A = T A max (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3E). 5.1.2 Typical values Unless otherwise specified, typical data are based on T A = 25 °C, V DD = 3.3 V (for the 2 V s V DD s 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2E). 5.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 5.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 8. 5.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 9. Electrical characteristics STM32F103x4, STM32F103x6 28/80 Doc ID 15060 Rev 3 5.1.6 Power supply scheme Figure 10. Power supply scheme Caution: In Figure 10, the 4.7 µF capacitor must be connected to V DD3 . Figure 8. Pin loading conditions Figure 9. Pin input voltage ai14141 C = 50 pF STM32F103xx pin ai14142 STM32F103xx pin V IN ai15496 V DD 1/2/3/4/5 Analog: RCs, PLL, ... Power swi tch V BAT GP I/Os OUT IN Kernel logic (CPU, Digital & Memories) Backup circuitry (OSC32K,RTC, Backup registers) Wakeup logic 5 × 100 nF + 1 × 4.7 µF 1.8-3.6V Regulator V SS 1/2/3/4/5 V DDA V SSA ADC L e v e l s h i f t e r IO Logic V DD 10 nF + 1 µF V DD V REF+ V REF- 10 nF + 1 µF V REF STM32F103x4, STM32F103x6 Electrical characteristics Doc ID 15060 Rev 3 29/80 5.1.7 Current consumption measurement Figure 11. Current consumption measurement scheme 5.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 6: Voltage characteristics, Table 7: Current characteristics, and Table 8: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ai14126 V BAT V DD V DDA I DD _V BAT I DD Table 6. Voltage characteristics Symbol Ratings Min Max Unit V DD –V SS External main supply voltage (including V DDA and V DD ) (1) 1. All main power (V DD , V DDA ) and ground (V SS , V SSA ) pins must always be connected to the external power supply, in the permitted range. –0.3 4.0 V V IN Input voltage on five volt tolerant pin (2) 2. I INJ(PIN) must never be exceeded (see Table 7: Current characteristics). This is implicitly insured if V IN maximum is respected. If V IN maximum cannot be respected, the injection current must be limited externally to the I INJ(PIN) value. A positive injection is induced by V IN > V IN max while a negative injection is induced by V IN < V SS . V SS ÷ 0.3 +5.5 Input voltage on any other pin (2) V SS ÷ 0.3 V DD +0.3 |AV DDx | Variations between different V DD power pins 50 mV |V SSX ÷ V SS | Variations between all the different ground pins 50 V ESD(HBM) Electrostatic discharge voltage (human body model) see Section 5.3.11: Absolute maximum ratings (electrical sensitivity) Electrical characteristics STM32F103x4, STM32F103x6 30/80 Doc ID 15060 Rev 3 5.3 Operating conditions 5.3.1 General operating conditions Table 7. Current characteristics Symbol Ratings Max. Unit I VDD Total current into V DD /V DDA power lines (source) (1) 1. All main power (V DD , V DDA ) and ground (V SS , V SSA ) pins must always be connected to the external power supply, in the permitted range. 150 mA I VSS Total current out of V SS ground lines (sink) (1) 150 I IO Output current sunk by any I/O and control pin 25 Output current source by any I/Os and control pin ÷ 25 I INJ(PIN) (2)(3) 2. I INJ(PIN) must never be exceeded. This is implicitly insured if V IN maximum is respected. If V IN maximum cannot be respected, the injection current must be limited externally to the I INJ(PIN) value. A positive injection is induced by V IN > V DD while a negative injection is induced by V IN < V SS . 3. Negative injection disturbs the analog performance of the device. See note in Section 5.3.17: 12-bit ADC characteristics. Injected current on NRST pin ± 5 Injected current on HSE OSC_IN and LSE OSC_IN pins ± 5 Injected current on any other pin (4) 4. When several inputs are submitted to a current injection, the maximum EI INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with EI INJ(PIN) maximum current injection on four I/O port pins of the device. ± 5 EI INJ(PIN) (2) Total injected current (sum of all I/O and control pins) (4) ± 25 Table 8. Thermal characteristics Symbol Ratings Value Unit T STG Storage temperature range –65 to +150 °C T J Maximum junction temperature 150 °C Table 9. General operating conditions Symbol Parameter Conditions Min Max Unit f HCLK Internal AHB clock frequency 0 72 MHz f PCLK1 Internal APB1 clock frequency 0 36 f PCLK2 Internal APB2 clock frequency 0 72 V DD Standard operating voltage 2 3.6 V V DDA (1) Analog operating voltage (ADC not used) Must be the same potential as V DD (2) 2 3.6 V Analog operating voltage (ADC used) 2.4 3.6 V BAT Backup operating voltage 1.8 3.6 V STM32F103x4, STM32F103x6 Electrical characteristics Doc ID 15060 Rev 3 31/80 5.3.2 Operating conditions at power-up / power-down Subject to general operating conditions for T A . Table 10. Operating conditions at power-up / power-down 5.3.3 Embedded reset and power control block characteristics The parameters given in Table 11 are derived from tests performed under ambient temperature and V DD supply voltage conditions summarized in Table 9. P D Power dissipation at T A = 85 °C for suffix 6 or T A = 105 °C for suffix 7 (3) TFBGA64 308 mW LQFP64 444 LQFP48 363 VFQFPN36 1110 TA Ambient temperature for 6 suffix version Maximum power dissipation –40 85 °C Low power dissipation (4) –40 105 Ambient temperature for 7 suffix version Maximum power dissipation –40 105 °C Low power dissipation (4) –40 125 TJ Junction temperature range 6 suffix version –40 105 °C 7 suffix version –40 125 1. When the ADC is used, refer to Table 45: ADC characteristics. 2. It is recommended to power V DD and V DDA from the same source. A maximum difference of 300 mV between V DD and V DDA can be tolerated during power-up and operation. 3. If T A is lower, higher P D values are allowed as long as T J does not exceed T J max (see Table 6.2: Thermal characteristics on page 74). 4. In low power dissipation state, T A can be extended to this range as long as T J does not exceed T J max (see Table 6.2: Thermal characteristics on page 74). Table 9. General operating conditions (continued) Symbol Parameter Conditions Min Max Unit Symbol Parameter Conditions Min Max Unit t VDD V DD rise time rate 0 · µs/V V DD fall time rate 20 · Electrical characteristics STM32F103x4, STM32F103x6 32/80 Doc ID 15060 Rev 3 Table 11. Embedded reset and power control block characteristics Symbol Parameter Conditions Min Typ Max Unit V PVD Programmable voltage detector level selection PLS[2:0]=000 (rising edge) 2.1 2.18 2.26 V PLS[2:0]=000 (falling edge) 2 2.08 2.16 V PLS[2:0]=001 (rising edge) 2.19 2.28 2.37 V PLS[2:0]=001 (falling edge) 2.09 2.18 2.27 V PLS[2:0]=010 (rising edge) 2.28 2.38 2.48 V PLS[2:0]=010 (falling edge) 2.18 2.28 2.38 V PLS[2:0]=011 (rising edge) 2.38 2.48 2.58 V PLS[2:0]=011 (falling edge) 2.28 2.38 2.48 V PLS[2:0]=100 (rising edge) 2.47 2.58 2.69 V PLS[2:0]=100 (falling edge) 2.37 2.48 2.59 V PLS[2:0]=101 (rising edge) 2.57 2.68 2.79 V PLS[2:0]=101 (falling edge) 2.47 2.58 2.69 V PLS[2:0]=110 (rising edge) 2.66 2.78 2.9 V PLS[2:0]=110 (falling edge) 2.56 2.68 2.8 V PLS[2:0]=111 (rising edge) 2.76 2.88 3 V PLS[2:0]=111 (falling edge) 2.66 2.78 2.9 V V PVDhyst (2) PVD hysteresis 100 mV V POR/PDR Power on/power down reset threshold Falling edge 1.8 (1) 1. The product behavior is guaranteed by design down to the minimum V POR/PDR value. 1.88 1.96 V Rising edge 1.84 1.92 2.0 V V PDRhyst (2) PDR hysteresis 40 mV T RSTTEMPO (2) 2. Guaranteed by design, not tested in production. Reset temporization 1 2.5 4.5 ms STM32F103x4, STM32F103x6 Electrical characteristics Doc ID 15060 Rev 3 33/80 5.3.4 Embedded reference voltage The parameters given in Table 12 are derived from tests performed under ambient temperature and V DD supply voltage conditions summarized in Table 9. 5.3.5 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 11: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code. Maximum current consumption The MCU is placed under the following conditions: ● All I/O pins are in input mode with a static value at V DD or V SS (no load) ● All peripherals are disabled except when explicitly mentioned ● The Flash memory access time is adjusted to the f HCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above) ● Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling) ● When the peripherals are enabled f PCLK1 = f HCLK /2, f PCLK2 = f HCLK The parameters given in Table 13, Table 14 and Table 15 are derived from tests performed under ambient temperature and V DD supply voltage conditions summarized in Table 9. Table 12. Embedded internal reference voltage Symbol Parameter Conditions Min Typ Max Unit V REFINT Internal reference voltage –40 °C < T A < +105 °C 1.16 1.20 1.26 V –40 °C < T A < +85 °C 1.16 1.20 1.24 V T S_vrefint (1) 1. Shortest sampling time can be determined in the application by multiple iterations. ADC sampling time when reading the internal reference voltage 5.1 17.1 (2) 2. Guaranteed by design, not tested in production. µs V RERINT (2) Internal reference voltage spread over the temperature range V DD = 3 V ±10 mV 10 mV T Coeff (2) Temperature coefficient 100 ppm/°C Electrical characteristics STM32F103x4, STM32F103x6 34/80 Doc ID 15060 Rev 3 Table 13. Maximum current consumption in Run mode, code with data processing running from Flash Symbol Parameter Conditions f HCLK Max (1) 1. Based on characterization, not tested in production. Unit T A = 85 °C T A = 105 °C I DD Supply current in Run mode External clock (2) , all peripherals enabled 2. External clock is 8 MHz and PLL is on when f HCLK > 8 MHz. 72 MHz 45 46 mA 48 MHz 32 33 36 MHz 26 27 24 MHz 18 19 16 MHz 13 14 8 MHz 7 8 External clock (2) , all peripherals disabled 72 MHz 30 31 48 MHz 23 24 36 MHz 19 20 24 MHz 13 14 16 MHz 10 11 8 MHz 6 7 Table 14. Maximum current consumption in Run mode, code with data processing running from RAM Symbol Parameter Conditions f HCLK Max (1) 1. Based on characterization, tested in production at V DD max, f HCLK max. Unit T A = 85 °C T A = 105 °C I DD Supply current in Run mode External clock (2) , all peripherals enabled 2. External clock is 8 MHz and PLL is on when f HCLK > 8 MHz. 72 MHz 41 42 mA 48 MHz 27 28 36 MHz 20 21 24 MHz 14 15 16 MHz 10 11 8 MHz 6 7 External clock (2) , all peripherals disabled 72 MHz 27 28 48 MHz 19 20 36 MHz 15 16 24 MHz 10 11 16 MHz 7 8 8 MHz 5 6 STM32F103x4, STM32F103x6 Electrical characteristics Doc ID 15060 Rev 3 35/80 Figure 12. Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals enabled Figure 13. Typical current consumption in Run mode versus frequency (at 3.6 V) - code with data processing running from RAM, peripherals disabled 0 5 10 15 20 25 30 35 40 45 – 45°C 25 °C 70 °C 85 °C 105 °C Temperature (°C) C o n s u m p t i o n ( m A ) 72 MHz 36 MHz 16 MHz 8 MHz 0 5 10 15 20 25 30 – 45°C 25 °C 70 °C 85 °C 105 °C Temperature (°C) C o n s u m p t i o n ( m A ) 72 MHz 36 MHz 16 MHz 8 MHz Electrical characteristics STM32F103x4, STM32F103x6 36/80 Doc ID 15060 Rev 3 Table 15. Maximum current consumption in Sleep mode, code running from Flash or RAM Symbol Parameter Conditions f HCLK Max (1) 1. based on characterization, tested in production at V DD max , f HCLK max with peripherals enabled. Unit T A = 85 °C T A = 105 °C I DD Supply current in Sleep mode External clock (2) , all peripherals enabled 2. External clock is 8 MHz and PLL is on when f HCLK > 8 MHz. 72 MHz 26 27 mA 48 MHz 17 18 36 MHz 14 15 24 MHz 10 11 16 MHz 7 8 8 MHz 4 5 External clock (2) , all peripherals disabled 72 MHz 7.5 8 48 MHz 6 6.5 36 MHz 5 5.5 24 MHz 4.5 5 16 MHz 4 4.5 8 MHz 3 4 STM32F103x4, STM32F103x6 Electrical characteristics Doc ID 15060 Rev 3 37/80 Figure 14. Typical current consumption on V BAT with RTC on versus temperature at different V BAT values Table 16. Typical and maximum current consumptions in Stop and Standby modes Symbol Parameter Conditions Typ (1) Max Unit V DD /V BAT = 2.0 V V DD /V BAT = 2.4 V V DD /V BAT = 3.3 V T A = 85 °C T A = 105 °C I DD Supply current in Stop mode Regulator in Run mode, low-speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) - 21.3 21.7 160 200 µA Regulator in Low Power mode, low- speed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) - 11.3 11.7 145 185 Supply current in Standby mode Low-speed internal RC oscillator and independent watchdog ON - 2.75 3.4 - - Low-speed internal RC oscillator ON, independent watchdog OFF - 2.55 3.2 - - Low-speed internal RC oscillator and independent watchdog OFF, low- speed oscillator and RTC OFF - 1.55 1.9 3.2 4.5 I DD_VBAT Backup domain supply current Low-speed oscillator and RTC ON 0.9 1.1 1.4 1.9 (2) 2.2 1. Typical values are measured at T A = 25 °C. 2. Based on characterization, not tested in production. 0 0.5 1 1.5 2 2.5 –40 °C 25 °C 70 °C 85 °C 105 °C Temperature (°C) C o n s u m p t i o n ( µ A ) 2 V 2.4 V 3 V 3.6 V ai17351 Electrical characteristics STM32F103x4, STM32F103x6 38/80 Doc ID 15060 Rev 3 Figure 15. Typical current consumption in Stop mode with regulator in Run mode versus temperature at V DD = 3.3 V and 3.6 V Figure 16. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at V DD = 3.3 V and 3.6 V 0 20 40 60 80 100 120 –45 °C 25 °C 85 °C 105 °C Temperature (°C) C o n s u m p t i o n ( µ A ) 3.3 V 3.6 V 0 10 20 30 40 50 60 70 80 90 –45 °C 25 °C 85 °C 105 °C Temperature (°C) C o n s u m p t i o n ( µ A ) 3.3 V 3.6 V STM32F103x4, STM32F103x6 Electrical characteristics Doc ID 15060 Rev 3 39/80 Figure 17. Typical current consumption in Standby mode versus temperature at V DD = 3.3 V and 3.6 V Typical current consumption The MCU is placed under the following conditions: ● All I/O pins are in input mode with a static value at V DD or V SS (no load). ● All peripherals are disabled except if it is explicitly mentioned. ● The Flash access time is adjusted to f HCLK frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above). ● Ambient temperature and V DD supply voltage conditions summarized in Table 9. ● Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling) ● When the peripherals are enabled f PCLK1 = f HCLK /4, f PCLK 2 = f HCLK /2, f ADCCLK = f PCLK2 /4 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 –45 °C 25 °C 85 °C 105 °C Temperature (°C) C o n s u m p t i o n ( µ A ) 3.3 V 3.6 V Electrical characteristics STM32F103x4, STM32F103x6 40/80 Doc ID 15060 Rev 3 Table 17. Typical current consumption in Run mode, code with data processing running from Flash Symbol Parameter Conditions f HCLK Typ (1) 1. Typical values are measures at T A = 25 °C, V DD = 3.3 V. Unit All peripherals enabled (2) 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). All peripherals disabled I DD Supply current in Run mode External clock (3) 3. External clock is 8 MHz and PLL is on when f HCLK > 8 MHz. 72 MHz 31.3 24.5 mA 48 MHz 21.9 17.4 36 MHz 17.2 13.8 24 MHz 11.2 8.9 16 MHz 8.1 6.6 8 MHz 5 4.2 4 MHz 3 2.6 2 MHz 2 1.8 1 MHz 1.5 1.4 500 kHz 1.2 1.2 125 kHz 1.05 1 Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency 64 MHz 27.6 21.6 mA 48 MHz 21.2 16.7 36 MHz 16.5 13.1 24 MHz 10.5 8.2 16 MHz 7.4 5.9 8 MHz 4.3 3.6 4 MHz 2.4 2 2 MHz 1.5 1.3 1 MHz 1 0.9 500 kHz 0.7 0.65 125 kHz 0.5 0.45 STM32F103x4, STM32F103x6 Electrical characteristics Doc ID 15060 Rev 3 41/80 Table 18. Typical current consumption in Sleep mode, code running from Flash or RAM Symbol Parameter Conditions f HCLK Typ (1) 1. Typical values are measures at T A = 25 °C, V DD = 3.3 V. Unit All peripherals enabled (2) 2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register). All peripherals disabled I DD Supply current in Sleep mode External clock (3) 3. External clock is 8 MHz and PLL is on when f HCLK > 8 MHz. 72 MHz 12.6 5.3 mA 48 MHz 8.7 3.8 36 MHz 6.7 3.1 24 MHz 4.8 2.3 16 MHz 3.4 1.8 8 MHz 2 1.2 4 MHz 1.5 1.1 2 MHz 1.25 1 1 MHz 1.1 0.98 500 kHz 1.05 0.96 125 kHz 1 0.95 Running on high speed internal RC (HSI), AHB prescaler used to reduce the frequency 64 MHz 10.6 4.2 48 MHz 8.1 3.2 36 MHz 6.1 2.5 24 MHz 4.2 1.7 16 MHz 2.8 1.2 8 MHz 1.4 0.55 4 MHz 0.9 0.5 2 MHz 0.7 0.45 1 MHz 0.55 0.42 500 kHz 0.48 0.4 125 kHz 0.4 0.38 Electrical characteristics STM32F103x4, STM32F103x6 42/80 Doc ID 15060 Rev 3 On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 19. The MCU is placed under the following conditions: ● all I/O pins are in input mode with a static value at V DD or V SS (no load) ● all peripherals are disabled unless otherwise mentioned ● the given value is calculated by measuring the current consumption – with all peripherals clocked off – with only one peripheral clocked on ● ambient operating temperature and V DD supply voltage conditions summarized in Table 6 5.3.6 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 20 result from tests performed using an high-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 9. Table 19. Peripheral current consumption (1) 1. f HCLK = 72 MHz, f APB1 = f HCLK /2, f APB2 = f HCLK , default prescaler value for each peripheral. Peripheral Typical consumption at 25 °C Unit APB1 TIM2 1.2 mA TIM3 1.2 USART2 0.35 I2C 0.39 USB 0.65 CAN 0.72 APB2 GPIO A 0.47 mA GPIO B 0.47 GPIO C 0.47 GPIO D 0.47 ADC1 (2) 2. Specific conditions for ADC: f HCLK = 56 MHz, f APB1 = f HCLK /2, f APB2 = f HCLK , f ADCCLK = f APB2/4 , ADON bit in the ADC_CR2 register is set to 1. 1.81 ADC2 1.78 TIM1 1.6 SPI 0.43 USART1 0.85 STM32F103x4, STM32F103x6 Electrical characteristics Doc ID 15060 Rev 3 43/80 Low-speed external user clock generated from an external source The characteristics given in Table 21 result from tests performed using an low-speed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 9. Table 20. High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit f HSE_ext User external clock source frequency (1) 1 8 25 MHz V HSEH OSC_IN input pin high level voltage 0.7V DD V DD V V HSEL OSC_IN input pin low level voltage V SS 0.3V DD t w(HSE) t w(HSE) OSC_IN high or low time (1) 1. Guaranteed by design, not tested in production. 16 ns t r(HSE) t f(HSE) OSC_IN rise or fall time (1) 20 C in(HSE) OSC_IN input capacitance (1) 5 pF DuCy (HSE) Duty cycle 45 55 % I L OSC_IN Input leakage current V SS s V IN s V DD ±1 µA Table 21. Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit f LSE_ext User External clock source frequency (1) 1. Guaranteed by design, not tested in production. 32.768 1000 kHz V LSEH OSC32_IN input pin high level voltage 0.7V DD V DD V V LSEL OSC32_IN input pin low level voltage V SS 0.3V DD t w(LSE) t w(LSE) OSC32_IN high or low time (1) 450 ns t r(LSE) t f(LSE) OSC32_IN rise or fall time (1) 50 C in(LSE) OSC32_IN input capacitance (1) 5 pF DuCy (LSE) Duty cycle 30 70 % I L OSC32_IN Input leakage current V SS s V IN s V DD ±1 µA Electrical characteristics STM32F103x4, STM32F103x6 44/80 Doc ID 15060 Rev 3 Figure 18. High-speed external clock source AC timing diagram Figure 19. Low-speed external clock source AC timing diagram High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 22. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). ai14143 OSC_IN EXTERNAL STM32F103xx CLOCK SOURCE V HSEH t f(HSE) t W(HSE) I L 90% 10% T HSE t t r(HSE) t W(HSE) f HSE_ext V HSEL ai14144b OSC32_IN EXTERNAL STM32F103xx CLOCK SOURCE V LSEH t f(LSE) t W(LSE) I L 90% 10% T LSE t t r(LSE) t W(LSE) f LSE_ext V LSEL STM32F103x4, STM32F103x6 Electrical characteristics Doc ID 15060 Rev 3 45/80 For C L1 and C L2 , it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 20). C L1 and C L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C L1 and C L2 . PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing C L1 and C L2 . Refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com. Figure 20. Typical application with an 8 MHz crystal 1. R EXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 23. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 22. HSE 4-16 MHz oscillator characteristics (1) (2) 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Based on characterization, not tested in production. Symbol Parameter Conditions Min Typ Max Unit f OSC_IN Oscillator frequency 4 8 16 MHz R F Feedback resistor 200 kO C Recommended load capacitance versus equivalent serial resistance of the crystal (R S ) (3) 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. R S = 30 O 30 pF i 2 HSE driving current V DD = 3.3 V, V IN = V SS with 30 pF load 1 mA g m Oscillator transconductance Startup 25 mA/V t SU(HSE (4) 4. t SU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer startup time V DD is stabilized 2 ms ai14145 OSC_OUT OSC_IN f HSE C L1 R F STM32F103xx 8 MHz resonator R EXT (1) C L2 Resonator with integrated capacitors Bias controlled gain Electrical characteristics STM32F103x4, STM32F103x6 46/80 Doc ID 15060 Rev 3 Note: For C L1 and C L2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator. C L1 and C L2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C L1 and C L2 . Load capacitance C L has the following formula: C L = C L1 x C L2 / (C L1 + C L2 ) + C stray where C stray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. Caution: To avoid exceeding the maximum value of C L1 and C L2 (15 pF) it is strongly recommended to use a resonator with a load capacitance C L s 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if you choose a resonator with a load capacitance of C L = 6 pF, and C stray = 2 pF, then C L1 = C L2 = 8 pF. Figure 21. Typical application with a 32.768 kHz crystal 5.3.7 Internal clock source characteristics The parameters given in Table 24 are derived from tests performed under ambient temperature and V DD supply voltage conditions summarized in Table 9. Table 23. LSE oscillator characteristics (f LSE = 32.768 kHz) (1) 1. Based on characterization, not tested in production. Symbol Parameter Conditions Min Typ Max Unit R F Feedback resistor 5 MO C (2) 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for ST microcontrollers. Recommended load capacitance versus equivalent serial resistance of the crystal (R S ) (3) 3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R S value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details R S = 30 kO 15 pF I 2 LSE driving current V DD = 3.3 V, V IN = V SS 1.4 µA g m Oscillator Transconductance 5 µA/V t SU(LSE) (4) 4. t SU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer startup time V DD is stabilized 3 s ai14146 OSC32_OUT OSC32_IN f LSE C L1 R F STM32F103xx 32.768 kHz resonator C L2 Resonator with integrated capacitors Bias controlled gain STM32F103x4, STM32F103x6 Electrical characteristics Doc ID 15060 Rev 3 47/80 High-speed internal (HSI) RC oscillator Low-speed internal (LSI) RC oscillator Wakeup time from low-power mode The wakeup times given in Table 26 is measured on a wakeup phase with a 8-MHz HSI RC oscillator. The clock source used to wake up the device depends from the current operating mode: ● Stop or Standby mode: the clock source is the RC oscillator ● Sleep mode: the clock source is the clock that was set before entering Sleep mode. All timings are derived from tests performed under ambient temperature and V DD supply voltage conditions summarized in Table 9. Table 24. HSI oscillator characteristics (1) 1. V DD = 3.3 V, T A = –40 to 105 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit f HSI Frequency 8 MHz ACC HSI Accuracy of the HSI oscillator User-trimmed with the RCC_CR register (2) 2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from the ST website www.st.com. 1 (3) 3. Guaranteed by design, not tested in production. % Factory- calibrated (4) 4. Based on characterization, not tested in production. T A = –40 to 105 °C –2 2.5 % T A = –10 to 85 °C –1.5 2.2 % T A = 0 to 70 °C –1.3 2 % T A = 25 °C –1.1 1.8 % t su(HSI) (4) HSI oscillator startup time 1 2 µs I DD(HSI) (4) HSI oscillator power consumption 80 100 µA Table 25. LSI oscillator characteristics (1) 1. V DD = 3 V, T A = –40 to 105 °C unless otherwise specified. Symbol Parameter Min Typ Max Unit f LSI (2) 2. Based on characterization, not tested in production. Frequency 30 40 60 kHz t su(LSI) (3) 3. Guaranteed by design, not tested in production. LSI oscillator startup time 85 µs I DD(LSI) (3) LSI oscillator power consumption 0.65 1.2 µA Electrical characteristics STM32F103x4, STM32F103x6 48/80 Doc ID 15060 Rev 3 5.3.8 PLL characteristics The parameters given in Table 27 are derived from tests performed under ambient temperature and V DD supply voltage conditions summarized in Table 9. 5.3.9 Memory characteristics Flash memory The characteristics are given at T A = –40 to 105 °C unless otherwise specified. Table 26. Low-power mode wakeup timings Symbol Parameter Typ Unit t WUSLEEP (1) 1. The wakeup times are measured from the wakeup event to the point in which the user application code reads the first instruction. Wakeup from Sleep mode 1.8 µs t WUSTOP (1) Wakeup from Stop mode (regulator in run mode) 3.6 µs Wakeup from Stop mode (regulator in low power mode) 5.4 t WUSTDBY (1) Wakeup from Standby mode 50 µs Table 27. PLL characteristics Symbol Parameter Value Unit Min (1) 1. Based on characterization, not tested in production. Typ Max (1) f PLL_IN PLL input clock (2) 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by f PLL_OUT . 1 8.0 25 MHz PLL input clock duty cycle 40 60 % f PLL_OUT PLL multiplier output clock 16 72 MHz t LOCK PLL lock time 200 µs Jitter Cycle-to-cycle jitter 300 ps Table 28. Flash memory characteristics Symbol Parameter Conditions Min (1) Typ Max (1) Unit t prog 16-bit programming time T A = –40 to +105 °C 40 52.5 70 µs t ERASE Page (1 KB) erase time T A = –40 to +105 °C 20 40 ms t ME Mass erase time T A = –40 to +105 °C 20 40 ms STM32F103x4, STM32F103x6 Electrical characteristics Doc ID 15060 Rev 3 49/80 Table 29. Flash memory endurance and data retention 5.3.10 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: ● Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. ● FTB: A Burst of Fast Transient voltage (positive and negative) is applied to V DD and V SS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 30. They are based on the EMS levels and classes defined in application note AN1709. I DD Supply current Read mode f HCLK = 72 MHz with 2 wait states, V DD = 3.3 V 20 mA Write / Erase modes f HCLK = 72 MHz, V DD = 3.3 V 5 mA Power-down mode / Halt, V DD = 3.0 to 3.6 V 50 µA V prog Programming voltage 2 3.6 V 1. Guaranteed by design, not tested in production. Symbol Parameter Conditions Value Unit Min (1) 1. Based on characterization, not tested in production. Typ Max N END Endurance T A = –40 to +85 °C (6 suffix versions) T A = –40 to +105 °C (7 suffix versions) 10 kcycles t RET Data retention 1 kcycle (2) at T A = 85 °C 2. Cycling performed over the whole temperature range. 30 Years 1 kcycle (2) at T A = 105 °C 10 10 kcycles (2) at T A = 55 °C 20 Table 28. Flash memory characteristics (continued) Symbol Parameter Conditions Min (1) Typ Max (1) Unit Electrical characteristics STM32F103x4, STM32F103x6 50/80 Doc ID 15060 Rev 3 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: ● Corrupted program counter ● Unexpected reset ● Critical Data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 30. EMS characteristics Symbol Parameter Conditions Level/ Class V FESD Voltage limits to be applied on any I/O pin to induce a functional disturbance V DD = 3.3 V, T A = +25 °C, f HCLK = 72 MHz conforms to IEC 61000-4-2 2B V EFTB Fast transient voltage burst limits to be applied through 100 pF on V DD and V SS pins to induce a functional disturbance V DD = 3.3 V, T A = +25 °C, f HCLK = 72 MHz conforms to IEC 61000-4-4 4A Table 31. EMI characteristics Symbol Parameter Conditions Monitored frequency band Max vs. [f HSE /f HCLK ] Unit 8/48 MHz 8/72 MHz S EMI Peak level V DD = 3.3 V, T A = 25 °C 0.1 to 30 MHz 12 12 dBµV 30 to 130 MHz 22 19 130 MHz to 1GHz 23 29 SAE EMI Level 4 4 - STM32F103x4, STM32F103x6 Electrical characteristics Doc ID 15060 Rev 3 51/80 5.3.11 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the JESD22-A114/C101 standard. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: ● A supply overvoltage is applied to each power supply pin ● A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 32. ESD absolute maximum ratings Symbol Ratings Conditions Class Maximum value (1) 1. Based on characterization results, not tested in production. Unit V ESD(HBM) Electrostatic discharge voltage (human body model) T A = +25 °C conforming to JESD22-A114 2 2000 V V ESD(CDM) Electrostatic discharge voltage (charge device model) T A = +25 °C conforming to JESD22-C101 II 500 Table 33. Electrical sensitivities Symbol Parameter Conditions Class LU Static latch-up class T A = +105 °C conforming to JESD78A II level A Electrical characteristics STM32F103x4, STM32F103x6 52/80 Doc ID 15060 Rev 3 5.3.12 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 34 are derived from tests performed under the conditions summarized in Table 9. All I/Os are CMOS and TTL compliant. All I/Os are CMOS and TTL compliant (no software configuration required), their characteristics consider the most strict CMOS-technology or TTL parameters: ● For V IH : – if V DD is in the [2.00 V - 3.08 V] range: CMOS characteristics but TTL included – if V DD is in the [3.08 V - 3.60 V] range: TTL characteristics but CMOS included ● For V IL : – if V DD is in the [2.00 V - 2.28 V] range: TTL characteristics but CMOS included – if V DD is in the [2.28 V - 3.60 V] range: CMOS characteristics but TTL included Table 34. I/O static characteristics Symbol Parameter Conditions Min Typ Max Unit V IL Input low level voltage TTL ports –0.5 0.8 V V IH Standard IO input high level voltage 2 V DD +0.5 IO FT (1) input high level voltage 1. FT = Five-volt tolerant. 2 5.5V V IL Input low level voltage CMOS ports –0.5 0.35 V DD V V IH Input high level voltage 0.65 V DD V DD +0.5 V hys Standard IO Schmitt trigger voltage hysteresis (2) 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. 200 mV IO FT Schmitt trigger voltage hysteresis (2) 5% V DD (3) 3. With a minimum of 100 mV. mV I lkg Input leakage current (4) 4. Leakage could be higher than max. if negative current is injected on adjacent pins. V SS s V IN s V DD Standard I/Os ±1 µA V IN = 5 V I/O FT 3 R PU Weak pull-up equivalent resistor (5) 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order). V IN = V SS 30 40 50 kO R PD Weak pull-down equivalent resistor (5) V IN = V DD 30 40 50 kO C IO I/O pin capacitance 5 pF STM32F103x4, STM32F103x6 Electrical characteristics Doc ID 15060 Rev 3 53/80 Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink +20 mA (with a relaxed V OL ). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2: ● The sum of the currents sourced by all the I/Os on V DD, plus the maximum Run consumption of the MCU sourced on V DD, cannot exceed the absolute maximum rating I VDD (see Table 7). ● The sum of the currents sunk by all the I/Os on V SS plus the maximum Run consumption of the MCU sunk on V SS cannot exceed the absolute maximum rating I VSS (see Table 7). Output voltage levels Unless otherwise specified, the parameters given in Table 35 are derived from tests performed under ambient temperature and V DD supply voltage conditions summarized in Table 9. All I/Os are CMOS and TTL compliant. Table 35. Output voltage characteristics Symbol Parameter Conditions Min Max Unit V OL (1) 1. The I IO current sunk by the device must always respect the absolute maximum rating specified in Table 7 and the sum of I IO (I/O ports and control pins) must not exceed I VSS . Output low level voltage for an I/O pin when 8 pins are sunk at same time TTL port I IO = +8 mA 2.7 V < V DD < 3.6 V 0.4 V V OH (2) 2. The I IO current sourced by the device must always respect the absolute maximum rating specified in Table 7 and the sum of I IO (I/O ports and control pins) must not exceed I VDD . Output high level voltage for an I/O pin when 8 pins are sourced at same time V DD –0.4 V OL (1) Output low level voltage for an I/O pin when 8 pins are sunk at same time CMOS port I IO =+ 8mA 2.7 V < V DD < 3.6 V 0.4 V V OH (2) Output high level voltage for an I/O pin when 8 pins are sourced at same time 2.4 V OL (1)(3) 3. Based on characterization data, not tested in production. Output low level voltage for an I/O pin when 8 pins are sunk at same time I IO = +20 mA 2.7 V < V DD < 3.6 V 1.3 V V OH (2)(3) Output high level voltage for an I/O pin when 8 pins are sourced at same time V DD –1.3 V OL (1)(3) Output low level voltage for an I/O pin when 8 pins are sunk at same time I IO = +6 mA 2 V < V DD < 2.7 V 0.4 V V OH (2)(3) Output high level voltage for an I/O pin when 8 pins are sourced at same time V DD –0.4 Electrical characteristics STM32F103x4, STM32F103x6 54/80 Doc ID 15060 Rev 3 Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 22 and Table 36, respectively. Unless otherwise specified, the parameters given in Table 36 are derived from tests performed under the ambient temperature and V DD supply voltage conditions summarized in Table 9. Table 36. I/O AC characteristics (1) 1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register. MODEx[1:0] bit value (1) Symbol Parameter Conditions Min Max Unit 10 f max(IO)out Maximum frequency (2) 2. The maximum frequency is defined in Figure 22. C L = 50 pF, V DD = 2 V to 3.6 V 2 MHz t f(IO)out Output high to low level fall time C L = 50 pF, V DD = 2 V to 3.6 V 125 (3) 3. Guaranteed by design, not tested in production. ns t r(IO)out Output low to high level rise time 125 (3) 01 f max(IO)out Maximum frequency (2) C L = 50 pF, V DD = 2 V to 3.6 V 10 MHz t f(IO)out Output high to low level fall time C L = 50 pF, V DD = 2 V to 3.6 V 25 (3) ns t r(IO)out Output low to high level rise time 25 (3) 11 F max(IO)out Maximum frequency (2) C L = 30 pF, V DD = 2.7 V to 3.6 V 50 MHz C L = 50 pF, V DD = 2.7 V to 3.6 V 30 MHz C L = 50 pF, V DD = 2 V to 2.7 V 20 MHz t f(IO)out Output high to low level fall time C L = 30 pF, V DD = 2.7 V to 3.6 V 5 (3) ns C L = 50 pF, V DD = 2.7 V to 3.6 V 8 (3) C L = 50 pF, V DD = 2 V to 2.7 V 12 (3) t r(IO)out Output low to high level rise time C L = 30 pF, V DD = 2.7 V to 3.6 V 5 (3) C L = 50 pF, V DD = 2.7 V to 3.6 V 8 (3) C L = 50 pF, V DD = 2 V to 2.7 V 12 (3) - t EXTIpw Pulse width of external signals detected by the EXTI controller 10 ns STM32F103x4, STM32F103x6 Electrical characteristics Doc ID 15060 Rev 3 55/80 Figure 22. I/O AC characteristics definition 5.3.13 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R PU (see Table 34). Unless otherwise specified, the parameters given in Table 37 are derived from tests performed under the ambient temperature and V DD supply voltage conditions summarized in Table 9. ai14131 10% 90% 50% t r(I O)out OUTPUT EXTERNAL ON 50pF Maximum frequency is achieved if (t r + t f ) s 2/3)T and if the duty cycle is (45-55%) 10% 50% 90% when loaded by 50pF T t r(I O)out Table 37. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit V IL(NRST) (1) 1. Guaranteed by design, not tested in production. NRST Input low level voltage –0.5 0.8 V V IH(NRST) (1) NRST Input high level voltage 2 V DD +0.5 V hys(NRST) NRST Schmitt trigger voltage hysteresis 200 mV R PU Weak pull-up equivalent resistor (2) 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). V IN = V SS 30 40 50 kO V F(NRST) (1) NRST Input filtered pulse 100 ns V NF(NRST) (1) NRST Input not filtered pulse 300 ns Electrical characteristics STM32F103x4, STM32F103x6 56/80 Doc ID 15060 Rev 3 Figure 23. Recommended NRST pin protection 2. The reset network protects the device against parasitic resets. 3. The user must ensure that the level on the NRST pin can go below the V IL(NRST) max level specified in Table 37. Otherwise the reset will not be taken into account by the device. 5.3.14 TIM timer characteristics The parameters given in Table 38 are guaranteed by design. Refer to Section 5.3.12: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). ai14132c STM32F10xxx R PU NRST (2) V DD Filter Internal Reset 0.1 µF External reset circuit (1) Table 38. TIMx (1) characteristics 1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3 and TIM4 timers. Symbol Parameter Conditions Min Max Unit t res(TIM) Timer resolution time 1 t TIMxCLK f TIMxCLK = 72 MHz 13.9 ns f EXT Timer external clock frequency on CH1 to CH4 0 f TIMxCLK /2 MHz f TIMxCLK = 72 MHz 0 36 MHz Res TIM Timer resolution 16 bit t COUNTER 16-bit counter clock period when internal clock is selected 1 65536 t TIMxCLK f TIMxCLK = 72 MHz 0.0139 910 µs t MAX_COUNT Maximum possible count 65536 × 65536 t TIMxCLK f TIMxCLK = 72 MHz 59.6 s STM32F103x4, STM32F103x6 Electrical characteristics Doc ID 15060 Rev 3 57/80 5.3.15 Communications interfaces I 2 C interface characteristics Unless otherwise specified, the parameters given in Table 39 are derived from tests performed under the ambient temperature, f PCLK1 frequency and V DD supply voltage conditions summarized in Table 9. The STM32F103xx performance line I 2 C interface meets the requirements of the standard I 2 C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V DD is disabled, but is still present. The I 2 C characteristics are described in Table 39. Refer also to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 39. I 2 C characteristics Symbol Parameter Standard mode I 2 C (1) 1. Guaranteed by design, not tested in production. Fast mode I 2 C (1)(2) 2. f PCLK1 must be higher than 2 MHz to achieve the maximum standard mode I 2 C frequency. It must be higher than 4 MHz to achieve the maximum fast mode I 2 C frequency. Unit Min Max Min Max t w(SCLL) SCL clock low time 4.7 1.3 µs t w(SCLH) SCL clock high time 4.0 0.6 t su(SDA) SDA setup time 250 100 ns t h(SDA) SDA data hold time 0 (3) 3. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. 0 (4) 4. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 900 (3) t r(SDA) t r(SCL) SDA and SCL rise time 1000 20 + 0.1C b 300 t f(SDA) t f(SCL) SDA and SCL fall time 300 300 t h(STA) Start condition hold time 4.0 0.6 µs t su(STA) Repeated Start condition setup time 4.7 0.6 t su(STO) Stop condition setup time 4.0 0.6 µs t w(STO:STA) Stop to Start condition time (bus free) 4.7 1.3 µs C b Capacitive load for each bus line 400 400 pF Electrical characteristics STM32F103x4, STM32F103x6 58/80 Doc ID 15060 Rev 3 Figure 24. I 2 C bus AC waveforms and measurement circuit 1. Measurement points are done at CMOS levels: 0.3V DD and 0.7V DD . Table 40. SCL frequency (f PCLK1 = 36 MHz.,V DD = 3.3 V) (1)(2) 1. R P = External pull-up resistance, f SCL = I 2 C speed, 2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external components used to design the application. f SCL (kHz) I2C_CCR value R P = 4.7 kO 400 0x801E 300 0x8028 200 0x803C 100 0x00B4 50 0x0168 20 0x0384 ai14149b START SDA 100Ω 4.7kΩ I 2 C bus 4.7kΩ 100Ω V DD V DD STM32F103xx SDA SCL t f(SDA) t r(SDA) SCL t h(STA) t w(SCKH) t w(SCKL) t su(SDA) t r(SCK) t f(SCK) t h(SDA) START REPEATED START t su(STA) t su(STO) STOP t su(STA:STO) STM32F103x4, STM32F103x6 Electrical characteristics Doc ID 15060 Rev 3 59/80 SPI interface characteristics Unless otherwise specified, the parameters given in Table 41 are derived from tests performed under the ambient temperature, f PCLKx frequency and V DD supply voltage conditions summarized in Table 9. Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 41. SPI characteristics (1) 1. Remapped SPI1 characteristics to be determined. Symbol Parameter Conditions Min Max Unit f SCK 1/t c(SCK) SPI clock frequency Master mode 18 MHz Slave mode 18 t r(SCK) t f(SCK) SPI clock rise and fall time Capacitive load: C = 30 pF 8 ns DuCy(SCK) SPI slave input clock duty cycle Slave mode 30 70 % t su(NSS) (2) 2. Based on characterization, not tested in production. NSS setup time Slave mode 4t PCLK ns t h(NSS) (2) NSS hold time Slave mode 2t PCLK t w(SCKH) (2) t w(SCKL) (2) SCK high and low time Master mode, f PCLK = 36 MHz, presc = 4 50 60 t su(MI) (2) t su(SI) (2) Data input setup time Master mode 5 Slave mode 5 t h(MI) (2) Data input hold time Master mode 5 t h(SI) (2) Slave mode 4 t a(SO) (2)(3) 3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. Data output access time Slave mode, f PCLK = 20 MHz 0 3t PCLK t dis(SO) (2)(4) 4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z Data output disable time Slave mode 2 10 t v(SO) (2)(1) Data output valid time Slave mode (after enable edge) 25 t v(MO) (2)(1) Data output valid time Master mode (after enable edge) 5 t h(SO) (2) Data output hold time Slave mode (after enable edge) 15 t h(MO) (2) Master mode (after enable edge) 2 Electrical characteristics STM32F103x4, STM32F103x6 60/80 Doc ID 15060 Rev 3 Figure 25. SPI timing diagram - slave mode and CPHA = 0 Figure 26. SPI timing diagram - slave mode and CPHA = 1 (1) 1. Measurement points are done at CMOS levels: 0.3V DD and 0.7V DD . ai14134c S C K I n p u t CPHA=0 MOSI I NPUT MISO OUT PUT CPHA=0 MSB OUT MSB IN BI T6 OUT LSB IN LSB OUT CPOL=0 CPOL=1 BI T1 IN NSS input t SU(NSS) t c(SCK) t h(NSS) t a(SO) t w(SCKH) t w(SCKL) t v(SO) t h(SO) t r(SCK) t f(SCK) t dis(SO) t su(SI) t h(SI) ai14135 S C K I n p u t CPHA=1 MOSI I NPUT MISO OUT PUT CPHA=1 MSB OUT MSB IN BI T6 OUT LSB IN LSB OUT CPOL=0 CPOL=1 BI T1 IN t SU(NSS) t c(SCK) t h(NSS) t a(SO) t w(SCKH) t w(SCKL) t v(SO) t h(SO) t r(SCK) t f(SCK) t dis(SO) t su(SI) t h(SI) NSS input STM32F103x4, STM32F103x6 Electrical characteristics Doc ID 15060 Rev 3 61/80 Figure 27. SPI timing diagram - master mode (1) 1. Measurement points are done at CMOS levels: 0.3V DD and 0.7V DD . USB characteristics The USB interface is USB-IF certified (Full Speed). Table 42. USB startup time Symbol Parameter Max Unit t STARTUP (1) 1. Guaranteed by design, not tested in production. USB transceiver startup time 1 µs ai14136 S C K I n p u t CPHA=0 MOSI OUTUT MISO INPUT CPHA=0 MSBIN MSB OUT BI T6 IN LSB OUT LSB IN CPOL=0 CPOL=1 BI T1 OUT NSS input t c(SCK) t w(SCKH) t w(SCKL) t r(SCK) t f(SCK) t h(MI) High S C K I n p u t CPHA=1 CPHA=1 CPOL=0 CPOL=1 t su(MI) t v(MO) t h(MO) Electrical characteristics STM32F103x4, STM32F103x6 62/80 Doc ID 15060 Rev 3 Figure 28. USB timings: definition of data signal rise and fall time 5.3.16 CAN (controller area network) interface Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate function characteristics (CAN_TX and CAN_RX). Table 43. USB DC electrical characteristics Symbol Parameter Conditions Min. (1) 1. All the voltages are measured from the local ground potential. Max. (1) Unit Input levels V DD USB operating voltage (2) 2. To be compliant with the USB 2.0 full-speed electrical specification, the USBDP (D+) pin should be pulled up with a 1.5 kO resistor to a 3.0-to-3.6 V voltage range. 3.0 (3) 3. The STM32F103xx USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V V DD voltage range. 3.6 V V DI (4) 4. Guaranteed by design, not tested in production. Differential input sensitivity I(USBDP, USBDM) 0.2 V V CM (4) Differential common mode range Includes V DI range 0.8 2.5 V SE (4) Single ended receiver threshold 1.3 2.0 Output levels V OL Static output level low R L of 1.5 kO to 3.6 V (5) 5. R L is the load connected on the USB drivers 0.3 V V OH Static output level high R L of 15 kO to V SS (5) 2.8 3.6 Table 44. USB: Full-speed electrical characteristics (1) 1. Guaranteed by design, not tested in production. Symbol Parameter Conditions Min Max Unit Driver characteristics t r Rise time (2) 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification - Chapter 7 (version 2.0). C L = 50 pF 4 20 ns t f Fall time (2) C L = 50 pF 4 20 ns t rfm Rise/ fall time matching t r /t f 90 110 % V CRS Output signal crossover voltage 1.3 2.0 V ai14137 t f Differential data lines V SS V CRS t r Crossover points STM32F103x4, STM32F103x6 Electrical characteristics Doc ID 15060 Rev 3 63/80 5.3.17 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 45 are derived from tests performed under the ambient temperature, f PCLK2 frequency and V DDA supply voltage conditions summarized in Table 9. Note: It is recommended to perform a calibration after each power-up. Table 45. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit V DDA Power supply 2.4 3.6 V V REF+ (3) Positive reference voltage 2.4 V DDA V I VREF (3) Current on the V REF input pin 160 (1) 220 (1) µA f ADC ADC clock frequency 0.6 14 MHz f S (2) Sampling rate 0.05 1 MHz f TRIG (2) External trigger frequency f ADC = 14 MHz 823 kHz 17 1/f ADC V AIN (3) Conversion voltage range 0 (V SSA tied to ground) V REF+ V R AIN (2) External input impedance See Equation 1 and Table 46 for details 50 kO R ADC (2) Sampling switch resistance 1 kO C ADC (2) Internal sample and hold capacitor 8 pF t CAL (2) Calibration time f ADC = 14 MHz 5.9 µs 83 1/f ADC t lat (2) Injection trigger conversion latency f ADC = 14 MHz 0.214 µs 3 (4) 1/f ADC t latr (2) Regular trigger conversion latency f ADC = 14 MHz 0.143 µs 2 (4) 1/f ADC t S (2) Sampling time f ADC = 14 MHz 0.107 17.1 µs 1.5 239.5 1/f ADC t STAB (2) Power-up time 0 0 1 µs t CONV (2) Total conversion time (including sampling time) f ADC = 14 MHz 1 18 µs 14 to 252 (t S for sampling +12.5 for successive approximation) 1/f ADC 1. Based on characterization, not tested in production. 2. Guaranteed by design, not tested in production. 3. In devices delivered in VFQFPN and LQFP packages, V REF+ is internally connected to V DDA and V REF- is internally connected to V SSA . Devices that come in the TFBGA64 package have a V REF+ pin but no V REF- pin (V REF- is internally connected to V SSA ), see Table 5 and Figure 4. 4. For external triggers, a delay of 1/f PCLK2 must be added to the latency specified in Table 45. Electrical characteristics STM32F103x4, STM32F103x6 64/80 Doc ID 15060 Rev 3 Equation 1: R AIN max formula: The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution). Table 46. R AIN max for f ADC = 14 MHz (1) 1. Based on characterization, not tested in production. T s (cycles) t S (µs) R AIN max (kO) 1.5 0.11 0.4 7.5 0.54 5.9 13.5 0.96 11.4 28.5 2.04 25.2 41.5 2.96 37.2 55.5 3.96 50 71.5 5.11 NA 239.5 17.1 NA Table 47. ADC accuracy - limited test conditions (1) (2) 1. ADC DC accuracy values are measured after internal calibration. 2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non- robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I INJ(PIN) and EI INJ(PIN) in Section 5.3.12 does not affect the ADC accuracy. Symbol Parameter Test conditions Typ Max (3) 3. Based on characterization, not tested in production. Unit ET Total unadjusted error f PCLK2 = 56 MHz, f ADC = 14 MHz, R AIN < 10 kO, V DDA = 3 V to 3.6 V T A = 25 °C Measurements made after ADC calibration ±1.3 ±2 LSB EO Offset error ±1 ±1.5 EG Gain error ±0.5 ±1.5 ED Differential linearity error ±0.7 ±1 EL Integral linearity error ±0.8 ±1.5 R AIN T S f ADC C ADC 2 N 2 + ( ) ln × × -------------------------------------------------------------- R ADC – < STM32F103x4, STM32F103x6 Electrical characteristics Doc ID 15060 Rev 3 65/80 Figure 29. ADC accuracy characteristics Table 48. ADC accuracy (1) (2) (3) 1. ADC DC accuracy values are measured after internal calibration. 2. Better performance could be achieved in restricted V DD , frequency and temperature ranges. 3. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non- robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. Any positive injection current within the limits specified for I INJ(PIN) and EI INJ(PIN) in Section 5.3.12 does not affect the ADC accuracy. Symbol Parameter Test conditions Typ Max (4) 4. Based on characterization, not tested in production. Unit ET Total unadjusted error f PCLK2 = 56 MHz, f ADC = 14 MHz, R AIN < 10 kO, V DDA = 2.4 V to 3.6 V Measurements made after ADC calibration ±2 ±5 LSB EO Offset error ±1.5 ±2.5 EG Gain error ±1.5 ±3 ED Differential linearity error ±1 ±2 EL Integral linearity error ±1.5 ±3 E O E G 1 LSB IDEAL (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line E T =Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. E O =Offset Error: deviation between the first actual transition and the first ideal one. E G =Gain Error: deviation between the last ideal transition and the last actual one. E D =Differential Linearity Error: maximum deviation between actual steps and the ideal one. E L =Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. 4095 4094 4093 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 4093 4094 4095 4096 (1) (2) E T E D E L (3) V DDA V SSA ai14395b V REF+ 4096 (or depending on package)] V DDA 4096 [1LSB IDEAL = Electrical characteristics STM32F103x4, STM32F103x6 66/80 Doc ID 15060 Rev 3 Figure 30. Typical connection diagram using the ADC 1. Refer to Table 45 for the values of R AIN , R ADC and C ADC . 2. C parasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high C parasitic value will downgrade conversion accuracy. To remedy this, f ADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown inFigure 31 or Figure 32, depending on whether V REF+ is connected to V DDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 31. Power supply and reference decoupling (V REF+ not connected to V DDA ) 1. The V REF+ input is available only on the TFBGA64 package. ai14150c STM32F103xx V DD AINx I L ±1 µA 0.6 V V T R AIN (1) C parasitic V AIN 0.6 V V T R ADC (1) 12-bit converter C ADC (1) Sample and hold ADC converter V REF+ (see note 1) STM32F103xx V DDA V SSA 1 µF // 10 nF 1 µF // 10 nF ai15887 STM32F103x4, STM32F103x6 Electrical characteristics Doc ID 15060 Rev 3 67/80 Figure 32. Power supply and reference decoupling(V REF+ connected to V DDA ) 1. The V REF+ input is available only on the TFBGA64 package. 5.3.18 Temperature sensor characteristics V DDA /V REF+ (see note 1) STM32F103x4/6 1 µF // 10 nF V SSA ai15888 Table 49. TS characteristics Symbol Parameter Min Typ Max Unit T L (1) 1. Based on characterization, not tested in production. V SENSE linearity with temperature ±1 ±2 °C Avg_Slope (1) Average slope 4.0 4.3 4.6 mV/°C V 25 (1) Voltage at 25 °C 1.34 1.43 1.52 V t START (2) 2. Guaranteed by design, not tested in production. Startup time 4 10 µs T S_temp (3)(2) 3. Shortest sampling time can be determined in the application by multiple iterations. ADC sampling time when reading the temperature 17.1 µs Package characteristics STM32F103x4, STM32F103x6 68/80 Doc ID 15060 Rev 3 6 Package characteristics 6.1 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK ® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK ® is an ST trademark. STM32F103x4, STM32F103x6 Package characteristics Doc ID 15060 Rev 3 69/80 1. Drawing is not to scale. 2. The back-side pad is not internally connected to the V SS or V DD power pads. 3. There is an exposed die pad on the underside of the VFQFPN package. It should be soldered to the PCB. All leads should also be soldered to the PCB. It is recommended to connect it to V SS . Figure 33. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package outline (1) Figure 34. Recommended footprint (dimensions in mm) (1)(2)(3) Seating plane ddd C C A3 A1 A A2 Pin # 1 ID R = 0.20 ZR_ME E2 b 1 9 10 18 27 28 36 19 D2 E D e L 0.30 6.30 0.50 1.00 4.30 4.30 4.80 4.80 4.10 4.10 1 28 9 19 ai14870b 36 27 18 10 0.75 Table 50. VFQFPN36 6 x 6 mm, 0.5 mm pitch, package mechanical data Symbol millimeters inches (1) Min Typ Max Min Typ Max A 0.800 0.900 1.000 0.0315 0.0354 0.0394 A1 0.020 0.050 0.0008 0.0020 A2 0.650 1.000 0.0256 0.0394 A3 0.250 0.0098 b 0.180 0.230 0.300 0.0071 0.0091 0.0118 D 5.875 6.000 6.125 0.2313 0.2362 0.2411 D2 1.750 3.700 4.250 0.0689 0.1457 0.1673 E 5.875 6.000 6.125 0.2313 0.2362 0.2411 E2 1.750 3.700 4.250 0.0689 0.1457 0.1673 e 0.450 0.500 0.550 0.0177 0.0197 0.0217 L 0.350 0.550 0.750 0.0138 0.0217 0.0295 ddd 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Package characteristics STM32F103x4, STM32F103x6 70/80 Doc ID 15060 Rev 3 Figure 35. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline (1) Figure 36. Recommended footprint (1)(2) 1. Drawing is not to scale. 2. Dimensions are in millimeters. A A2 A1 c L1 L E E1 D D1 e b ai14398b 48 32 49 64 17 1 16 1.2 0.3 33 10.3 12.7 10.3 0.5 7.8 12.7 ai14909 Table 51. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package mechanical data Symbol millimeters inches (1) Min Typ Max Min Typ Max A 1.60 0.0630 A1 0.05 0.15 0.0020 0.0059 A2 1.35 1.40 1.45 0.0531 0.0551 0.0571 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 0.20 0.0035 0.0079 D 12.00 0.4724 D1 10.00 0.3937 E 12.00 0.4724 E1 10.00 0.3937 e 0.50 0.0197 u 0° 3.5° 7° 0° 3.5° 7° L 0.45 0.60 0.75 0.0177 0.0236 0.0295 L1 1.00 0.0394 N Number of pins 64 1. Values in inches are converted from mm and rounded to 4 decimal digits. STM32F103x4, STM32F103x6 Package characteristics Doc ID 15060 Rev 3 71/80 Figure 37. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package outline 1. Drawing is not to scale. Table 52. TFBGA64 - 8 x 8 active ball array, 5 x 5 mm, 0.5 mm pitch, package mechanical data Symbol millimeters inches (1) 1. Values in inches are converted from mm and rounded to 4 decimal digits. Min Typ Max Min Typ Max A 1.200 0.0472 A1 0.150 0.0059 A2 0.785 0.0309 A3 0.200 0.0079 A4 0.600 0.0236 b 0.250 0.300 0.350 0.0098 0.0118 0.0138 D 4.850 5.000 5.150 0.1909 0.1969 0.2028 D1 3.500 0.1378 E 4.850 5.000 5.150 0.1909 0.1969 0.2028 E1 3.500 0.1378 e 0.500 0.0197 F 0.750 0.0295 ddd 0.080 0.0031 eee 0.150 0.0059 fff 0.050 0.0020 A3 A4 A2 A1 A Seating plane B A D D1 e F F E1 E e H G F E D C B A 1 2 3 4 5 6 7 8 A1 ball pad corner Øb (64 balls) Bottom view C ME_R8 Package characteristics STM32F103x4, STM32F103x6 72/80 Doc ID 15060 Rev 3 Figure 38. Recommended PCB design rules for pads (0.5 mm pitch BGA) 1. Non solder mask defined (NSMD) pads are recommended 2. 4 to 6 mils solder paste screen printing process Pitch 0.5 mm D pad 0.27 mm Dsm 0.35 mm typ (depends on the soldermask registration tolerance) Solder paste 0.27 mm aperture diameter Dpad Dsm ai15495 STM32F103x4, STM32F103x6 Package characteristics Doc ID 15060 Rev 3 73/80 Figure 39. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package outline (1) Figure 40. Recommended footprint (1)(2) 1. Drawing is not to scale. 2. Dimensions are in millimeters. D D1 D3 A1 L1 L k c b ccc C A1 A2 A C Seating plane 0.25 mm Gage plane E3 E1 E 12 13 24 25 48 1 36 37 Pin 1 identification 5B_ME 9.70 5.80 7.30 12 24 0.20 7.30 1 37 36 1.20 5.80 9.70 0.30 25 1.20 0.50 ai14911b 13 48 Table 53. LQFP48, 7 x 7 mm, 48-pin low-profile quad flat package mechanical data Symbol millimeters inches (1) Min Typ Max Min Typ Max A 1.600 0.0630 A1 0.050 0.150 0.0020 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 D 8.800 9.000 9.200 0.3465 0.3543 0.3622 D1 6.800 7.000 7.200 0.2677 0.2756 0.2835 D3 5.500 0.2165 E 8.800 9.000 9.200 0.3465 0.3543 0.3622 E1 6.800 7.000 7.200 0.2677 0.2756 0.2835 E3 5.500 0.2165 e 0.500 0.0197 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 1.000 0.0394 k 0° 3.5° 7° 0° 3.5° 7° ccc 0.080 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Package characteristics STM32F103x4, STM32F103x6 74/80 Doc ID 15060 Rev 3 6.2 Thermal characteristics The maximum chip junction temperature (T J max) must never exceed the values given in Table 9: General operating conditions on page 30. The maximum chip-junction temperature, T J max, in degrees Celsius, may be calculated using the following equation: T J max = T A max + (P D max × O JA ) Where: ● T A max is the maximum ambient temperature in °C, ● O JA is the package junction-to-ambient thermal resistance, in °C/W, ● P D max is the sum of P INT max and P I/O max (P D max = P INT max + P I/O max), ● P INT max is the product of I DD and V DD , expressed in Watts. This is the maximum chip internal power. P I/O max represents the maximum power dissipation on output pins where: P I/O max = E (V OL × I OL ) + E((V DD – V OH ) × I OH ), taking into account the actual V OL / I OL and V OH / I OH of the I/Os at low and high level in the application. 6.2.1 Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. Table 54. Package thermal characteristics Symbol Parameter Value Unit O JA Thermal resistance junction-ambient TFBGA64 - 5 × 5 mm / 0.5 mm pitch 65 °C/W Thermal resistance junction-ambient LQFP64 - 10 × 10 mm / 0.5 mm pitch 45 Thermal resistance junction-ambient LQFP48 - 7 × 7 mm / 0.5 mm pitch 55 Thermal resistance junction-ambient VFQFPN 36 - 6 × 6 mm / 0.5 mm pitch 18 STM32F103x4, STM32F103x6 Package characteristics Doc ID 15060 Rev 3 75/80 6.2.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Table 55: Ordering information scheme. Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and, to a specific maximum junction temperature. As applications do not commonly use the STM32F103xx at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application. The following examples show how to calculate the temperature range needed for a given application. Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature T Amax = 82 °C (measured according to JESD51-2), I DDmax = 50 mA, V DD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with I OL = 8 mA, V OL = 0.4 V and maximum 8 I/Os used at the same time in output at low level with I OL = 20 mA, V OL = 1.3 V P INTmax = 50 mA × 3.5 V= 175 mW P IOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW This gives: P INTmax = 175 mW and P IOmax = 272 mW: P Dmax = 175 + 272 = 447 mW Thus: P Dmax = 447 mW Using the values obtained in Table 54 T Jmax is calculated as follows: – For LQFP64, 45 °C/W T Jmax = 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.115 °C = 102.115 °C This is within the range of the suffix 6 version parts (–40 < T J < 105 °C). In this case, parts must be ordered at least with the temperature range suffix 6 (see Table 55: Ordering information scheme). Example 2: High-temperature application Using the same rules, it is possible to address applications that run at high ambient temperatures with a low dissipation, as long as junction temperature T J remains within the specified range. Assuming the following application conditions: Maximum ambient temperature T Amax = 115 °C (measured according to JESD51-2), I DDmax = 20 mA, V DD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with I OL = 8 mA, V OL = 0.4 V P INTmax = 20 mA × 3.5 V= 70 mW P IOmax = 20 × 8 mA × 0.4 V = 64 mW This gives: P INTmax = 70 mW and P IOmax = 64 mW: P Dmax = 70 + 64 = 134 mW Thus: P Dmax = 134 mW Package characteristics STM32F103x4, STM32F103x6 76/80 Doc ID 15060 Rev 3 Using the values obtained in Table 54 T Jmax is calculated as follows: – For LQFP64, 45 °C/W T Jmax = 115 °C + (45 °C/W × 134 mW) = 115 °C + 6.03 °C = 121.03 °C This is within the range of the suffix 7 version parts (–40 < T J < 125 °C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Table 55: Ordering information scheme). Figure 41. LQFP64 P D max vs. T A 0 100 200 300 400 500 600 700 65 75 85 95 105 115 125 135 T A (°C) P D ( m W ) Suffix 6 Suffix 7 STM32F103x4, STM32F103x6 Ordering information scheme Doc ID 15060 Rev 3 77/80 7 Ordering information scheme For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. Table 55. Ordering information scheme Example: STM32 F 103 C 4 T 7 A xxx Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 103 = performance line Pin count T = 36 pins C = 48 pins R = 64 pins Flash memory size 4 = 16 Kbytes of Flash memory 6 = 32 Kbytes of Flash memory Package H = BGA T = LQFP U = VFQFPN Temperature range 6 = Industrial temperature range, –40 to 85 °C. 7 = Industrial temperature range, –40 to 105 °C. Internal code “A” or blank (1) 1. For STM32F103x6 devices with a blank Internal code, please refer to the STM32F103x8/B datasheet available from the ST website: www.st.com. Options xxx = programmed parts TR = tape and real Revision history STM32F103x4, STM32F103x6 78/80 Doc ID 15060 Rev 3 8 Revision history Table 56. Document revision history Date Revision Changes 22-Sep-2008 1 Initial release. 30-Mar-2009 2 “96-bit unique ID” feature added and I/O information clarified on page 1. Timers specified on page 1 (Motor control capability mentioned). Table 4: Timer feature comparison added. PB4, PB13, PB14, PB15, PB3/TRACESWO moved from Default column to Remap column, plus small additional changes in Table 5: Low-density STM32F103xx pin definitions. Figure 7: Memory map modified. References to V REF- removed: – Figure 1: STM32F103xx performance line block diagram modified, – Figure 10: Power supply scheme modified – Figure 29: ADC accuracy characteristics modified – Note modified in Table 48: ADC accuracy. Table 20: High-speed external user clock characteristics and Table 21: Low-speed external user clock characteristics modified. Note modified in Table 13: Maximum current consumption in Run mode, code with data processing running from Flash and Table 15: Maximum current consumption in Sleep mode, code running from Flash or RAM. Figure 16 shows a typical curve (title modified). ACC HSI max values modified in Table 24: HSI oscillator characteristics. TFBGA64 package added (see Table 52 and Table 37). Small text changes. STM32F103x4, STM32F103x6 Revision history Doc ID 15060 Rev 3 79/80 24-Sep-2009 3 Note 5 updated and Note 4 added in Table 5: Low-density STM32F103xx pin definitions. V RERINT and T Coeff added to Table 12: Embedded internal reference voltage. Typical I DD_VBAT value added in Table 16: Typical and maximum current consumptions in Stop and Standby modes. Figure 14: Typical current consumption on VBAT with RTC on versus temperature at different VBAT values added. f HSE_ext min modified in Table 20: High-speed external user clock characteristics. C L1 and C L2 replaced by C in Table 22: HSE 4-16 MHz oscillator characteristics and Table 23: LSE oscillator characteristics (fLSE = 32.768 kHz), notes modified and moved below the tables. Table 24: HSI oscillator characteristics modified. Conditions removed from Table 26: Low-power mode wakeup timings. Note 1 modified below Figure 20: Typical application with an 8 MHz crystal. Figure 23: Recommended NRST pin protection modified. Jitter added to Table 27: PLL characteristics on page 48. IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to IEC 61967-2 in Section 5.3.10: EMC characteristics on page 49. C ADC and R AIN parameters modified in Table 45: ADC characteristics. R AIN max values modified in Table 46: RAIN max for fADC = 14 MHz. Small text changes. Table 56. Document revision history (continued) Date Revision Changes STM32F103x4, STM32F103x6 80/80 Doc ID 15060 Rev 3 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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All other names are the property of their respective owners. © 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Contents STM32F103x4, STM32F103x6 Contents 1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 2.2 2.3 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.3.8 2.3.9 2.3.10 2.3.11 2.3.12 2.3.13 2.3.14 2.3.15 2.3.16 2.3.17 2.3.18 2.3.19 2.3.20 2.3.21 2.3.22 2.3.23 2.3.24 ARM® Cortex™-M3 core with embedded Flash and SRAM . . . . . . . . . 13 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . 13 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 13 External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . 14 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 RTC (real-time clock) and backup registers . . . . . . . . . . . . . . . . . . . . . . 16 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Universal synchronous/asynchronous receiver transmitter (USART) . . 18 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . 19 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2/80 Doc ID 15060 Rev 3 STM32F103x4, STM32F103x6 Contents 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2 5.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.9 5.3.10 5.3.11 5.3.12 5.3.13 5.3.14 5.3.15 5.3.16 5.3.17 5.3.18 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 31 Embedded reset and power control block characteristics . . . . . . . . . . . 31 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 51 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 CAN (controller area network) interface . . . . . . . . . . . . . . . . . . . . . . . . . 62 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1 6.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.2.1 6.2.2 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 75 7 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Doc ID 15060 Rev 3 3/80 Contents STM32F103x4, STM32F103x6 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 4/80 Doc ID 15060 Rev 3 . . 29 Current characteristics . . . 43 Low-speed external user clock characteristics . . . 48 Flash memory endurance and data retention . . . . . . . . . . . . . . . . 49 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 15. . . . . . . . 16 Low-density STM32F103xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 SCL frequency (fPCLK1= 36 MHz. . . code with data processing running from Flash . . . . . . . 55 TIMx characteristics . . . . . . . . . . . . . . . . Table 17. . . . . . . . . . . Table 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4. . . . . . . . . . . . 45 LSE oscillator characteristics (fLSE = 32. 30 General operating conditions . . . . . . . . . . . . Device summary . . . 32 Embedded internal reference voltage . . . . . . . . . . . . . . . . 42 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Maximum current consumption in Run mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 32. . . . . . . . . . . . . . . . . . . . . . . . . . . code running from Flash or RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 33. . . . Table 2. . . . . . . . . . . . . . . . . . Table 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 28. . . . . . 34 Maximum current consumption in Sleep mode. . . . . . . . 36 Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . . . . . . Table 24. . . . 23 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . code with data processing running from RAM. . . . . . . . . . . . . . . STM32F103x6 List of tables List of tables Table 1. . . . . . . . . . . . . . . . . . . . . . . 50 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . 43 HSE 4-16 MHz oscillator characteristics . . . . . 12 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . 47 LSI oscillator characteristics . . 34 Maximum current consumption in Run mode. . . . . . . . . . . . 56 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 31. . . . . . . . . . . . . . . . 50 EMI characteristics . . . . . . . . 62 Doc ID 15060 Rev 3 5/80 . . . . . . . . . . . . . . . . . Table 13. . . . . . . . . . . . . . . . . . Table 8. . . . . . . . . . . . . . . 59 USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 NRST pin characteristics . . . . . . . . . . . .VDD = 3. . . . . . . . 37 Typical current consumption in Run mode. . . Table 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 35. . . . . . . . Table 37. . . . Table 5. . . . . . . . . . . . . . . . . . . . . . . Table 39. . . . . . . . . . . . . . . . . . . . . . . . . Table 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6. . . . . . . . . . . . .3 V) . . . . . . . . . . . . . . Table 34. . . . . . . . . . . . . . . . . . . . . Table 42. 1 STM32F103xx low-density device features and peripheral counts. 58 SPI characteristics . . . . . . . . . . 47 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . Table 29. . . . 30 Operating conditions at power-up / power-down . . . . . . . . 62 USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 41. . . . . . . . . . . . Table 19. . . . . . . . . . . . . . . . . . . . . . Table 27. . . . . . . . . . 51 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 30. . . . . . . . . . . . . . . . . . . . . code with data processing running from Flash . Table 38. . . . . . . . . . . . . . . . . . . . . Table 18. . . . . . . . Table 25. Table 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Peripheral current consumption . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 36. . . . . . . . . . . . . . . 61 USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . Table 44. . . . 9 STM32F103xx family . . . . . . . . . . 46 HSI oscillator characteristics. . . . . . . Table 9. . . Table 14. . Table 10. . . . . . . . . . .768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 40. . . . . . . . . 51 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . code running from Flash or RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Thermal characteristics. . . . . . . . . . . . . . . .STM32F103x4. . . . . . 53 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Typical current consumption in Sleep mode. . . . . 52 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . Table 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Embedded reset and power control block characteristics. . . . . . . . . . . . . . 0. .8 x 8 active ball array. . . . . . Table 50. . . Table 55. . . . . . . . . . . . . . . . package mechanical data . . . . 71 LQFP48. . . . . . . . 64 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STM32F103x4. . . . . . . . .limited test conditions . . . . . . . . . . STM32F103x6 ADC characteristics . . . . . . . Table 48. . . . . . . . . . . . 5 x 5 mm. . . . package mechanical data. . . . . 0. . . . 64-pin low-profile quad flat package mechanical data . 10 x 10 mm. . . . . . . . 67 VFQFPN36 6 x 6 mm. . . . . . . . . . . . . . .5 mm pitch. . . . . . . . . . . . . . . . . 64 ADC accuracy . . . . . . . . . . . . . . . . . . Table 53. . . . . . . . 7 x 7 mm. . . . . . . Table 49. . . . . . . 70 TFBGA64 . . . . . . . . . . . 74 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . Table 46. 73 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . 48-pin low-profile quad flat package mechanical data . . Table 52. . . . 69 LQFP64. . . . . . . . . . . . .List of tables Table 45. . . . . . . . . . .5 mm pitch. . . . 65 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 51. 77 6/80 Doc ID 15060 Rev 3 . . . . . . . . . . . . . . . . . . . Table 47. . . . . . . . . . . . . . Table 54. . . . . . . . . . . . . . . . . . . . . . 63 RAIN max for fADC = 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 18. . Figure 32. . . . . . . . . . . . . . . . . . . . . . . . . . Figure 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6. . . . . . . . . . . . . . . Figure 3. . . . . . . . . . . . . . . . . . . . . . Figure 16. . . . . . 62 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 37. . . . . . . . . . . . . . . Figure 8. . . . . . . . . . . . . . . . . 0. . . . .slave mode and CPHA = 1(1) . . . . . . 58 SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 V . . . . . . . . . . . . . . . . 76 Doc ID 15060 Rev 3 7/80 . . . . . . . . . Figure 13. . . . . . . . . . . . . . . . . . 10 x 10 mm. . . . . 44 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Pin input voltage . . . . . . 11 STM32F103xx performance line LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . 7 x 7 mm. . . . 38 Typical current consumption in Standby mode versus temperature at VDD = 3. . . . . . . . . . . Figure 14. . . . . . . . . . . . Figure 11. . . . . . . . . . . . . 69 LQFP64. . . . . . . . . . . . 26 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 33. . . . . . . . . . . . Figure 19. . . . . . Figure 24. . 29 Typical current consumption in Run mode versus frequency (at 3. . . . . . . . . . . . . . . . . . . . package outline . . . . . . . . . . . . . . . . . . . . . . . . Figure 40. . . .6 V) code with data processing running from RAM. . . . . . . . . . . . Figure 10. . . .5 mm pitch. . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 34. .5 mm pitch BGA) . . . . . . . . . . . . . . . . . . . Figure 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 26. . . . . . 70 Recommended footprint(1) . . . . . . . 73 Recommended footprint(1) . . . 45 Typical application with a 32. . . . . .slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . 72 LQFP48. .3 V and 3. . . . 44 Low-speed external clock source AC timing diagram . . . . . . 69 Recommended footprint (dimensions in mm)(1)(2)(3) . .master mode(1) . . . . . 67 VFQFPN36 6 x 6 mm. . 28 Current consumption measurement scheme . Figure 7. 61 USB timings: definition of data signal rise and fall time . . . . . . . . 66 Power supply and reference decoupling(VREF+ connected to VDDA) . . . . . . . 60 SPI timing diagram . . . . . . . . . . . . . . 38 Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3. . . . . . . . . . . . 20 STM32F103xx performance line TFBGA64 ballout . . . . . . . . . . Figure 9. . . . . . Figure 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Typical current consumption on VBAT with RTC on versus temperature at different VBAT values . . . . . . . . . . . . . . . 0. . . . . . . . . . 10 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 LQFP64 PD max vs. . . Figure 2. . . . . . .5 mm pitch. . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 27. . . 22 STM32F101xx Medium-density access line VFQFPN36 pinout . . . . . . . . . . . . . Figure 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Recommended PCB design rules for pads (0. . . . . . .8 x 8 active ball array. .6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Recommended NRST pin protection . . . . . . . . Figure 25. . . . . STM32F103xx performance line block diagram . . . . Figure 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 x 5 mm. . . . . Figure 17. . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4. . . . . STM32F103x6 List of figures List of figures Figure 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 21. . . . . . . . . . . . . . . . 37 Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3. . . . . . . 28 Power supply scheme. . . . . . Figure 38. . Figure 35. . . . . . . . . . . 65 Typical connection diagram using the ADC . . . . . . . . . . . . . Figure 36. .3 V and 3. . . 56 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . 46 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . peripherals enabled. . . . . .3 V and 3. . . . peripherals disabled . . . . . . . . TA . . . . . . . . . . . . . . . Figure 39. . package outline(1) . . . . .STM32F103x4. . . . . . . . . . . . . . . . . . . . Figure 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 High-speed external clock source AC timing diagram . . . . . . . . . Figure 30. . . . .6 V . . . 35 Typical current consumption in Run mode versus frequency (at 3. . . .768 kHz crystal . . . . . 21 STM32F103xx performance line LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . 60 SPI timing diagram . . . . . . . . . . Figure 22. . . . . . . . . . . . . . . . . . . . .6 V) code with data processing running from RAM. . . . . . . Figure 12. . . . . . . . . . . . . . 22 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 28. . 70 TFBGA64 . . . . . . . 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . printers. 2 Description The STM32F103x4 and STM32F103x6 performance line family incorporates the highperformance ARM Cortex™-M3 32-bit RISC core operating at a 72 MHz frequency.Introduction STM32F103x4. For more details on the whole STMicroelectronics STM32F103xx family.com. and HVAC 8/80 Doc ID 15060 Rev 3 . All devices offer two 12-bit ADCs.and high-density STM32F10xxx reference manual. The STM32F103xx low-density performance line family includes devices in four different package types: from 36 pins to 64 pins. medium. STM32F103x6 1 Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F103x4 and STM32F103x6 low-density performance line microcontrollers. three USARTs.arm.com/help/index. Video intercom.st. please refer to Section 2.0 to 3.jsp?topic=/com. The low-density STM32F103xx datasheet should be read in conjunction with the low-. inverters. an USB and a CAN. available from the www. three general purpose 16-bit timers plus one PWM timer. as well as standard and advanced communication interfaces: up to two I2Cs and SPIs. different sets of peripherals are included. A comprehensive set of power-saving mode allows the design of low-power applications.arm. highspeed embedded memories (Flash memory up to 32 Kbytes and SRAM up to 6 Kbytes). The STM32F103xx low-density performance line family operates from a 2. These features make the STM32F103xx low-density performance line microcontroller family suitable for a wide range of applications: ● ● ● ● ● Motor drive and application control Medical and handheld equipment PC peripherals gaming and GPS platforms Industrial applications: PLC.ddi0337e/. and scanners Alarm systems.6 V power supply. Depending on the device chosen.2: Full compatibility throughout the family. the description below gives an overview of the complete range of peripherals proposed in this family.com website at the following address: http://infocenter.doc. For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical Reference Manual. The reference and Flash programming manuals are both available from the STMicroelectronics website www.arm. It is available in both the –40 to +85 °C temperature range and the –40 to +105 °C extended temperature range. and an extensive range of enhanced I/Os and peripherals connected to two APB buses. STM32F103x4.1 Device overview Table 2.0 to 3. TFBGA64 32 10 2 STM32F103Cx 16 6 2 1 1 1 2 1 1 1 1 2 1 1 51 2 16 channels 32 10 2 STM32F103Rx 16 6 2 1 1 1 2 1 1 32 10 2 Peripheral Flash .Kbytes Timers Communication General-purpose Advanced-control SPI I2C USART USB CAN GPIOs 12-bit synchronized ADC Number of channels CPU frequency Operating voltage Operating temperatures Packages Doc ID 15060 Rev 3 9/80 . STM32F103x6 Description 2.Kbytes SRAM .6 V Ambient temperatures: –40 to +85 °C /–40 to +105 °C (see Table 9) Junction temperature: –40 to + 125 °C (see Table 9) VFQFPN36 LQFP48 LQFP64. STM32F103xx low-density device features and peripheral counts STM32F103Tx 16 6 2 1 1 1 2 1 1 26 2 10 channels 1 1 2 1 1 1 1 2 1 1 37 2 10 channels 72 MHz 2. 10/80 Doc ID 15060 Rev 3 .SMBA as AF USBDP/CAN_TX USBDM/CAN_RX WWDG 16 AF VREF+ Temp sensor ai15175c 1.3V TO 1.SDA. SmartCard as AF SCL. CTS. TA = –40 °C to +105 °C (junction temperature up to 125 °C).TX. 3.TX.Description Figure 1. AF = alternate function on I/O port pin.8V @VDD NJTRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as AF VDD = 2 to 3. RTS.6V VSS Cortex-M3 CPU Fmax : 7 2M Hz Dbus Flash obl interface Flash 32 KB 64 bit BusM atrix NVIC Syst em SRAM 10 KB PCLK1 PCLK2 HCLK FCLK RC 8 MHz RC 40 kHz @VDDA @VBAT PLL & CLOCK MANAGT @VDD XTAL OSC 4-16 MHz OSC_IN OSC_OUT GP DMA AHB:F max =48/72 MHz 7 ch annels IWDG Stand by in terface @VDDA SUPPLY SUPERVISION POR / PDR PVD 51AF PA[ 15:0] PB[ 15:0] PC[15:0] PD[2:0] 4 Chann els 3 co mpl. Smart Card as AF EXTI WAKEUP GPIOA GPIOB GPIOC GPIOD TIM1 SPI USART1 @VDDA 12bit ADC1 IF 12bi t ADC2 IF APB2 : F max =48 / 72 MHz Rst Int VBAT OSC32_IN OSC32_OUT TAMPER-RTC NRST VDDA VSSA XTAL 32 kHz AHB2 APB2 AHB2 APB 1 RTC AWU Back up reg Backu p i nterf ace TIM2 TIM3 APB1 : Fmax =24 / 36 MHz USART2 I2C bx CAN USB 2. RTS.0 FS SRAM 512B 4 Chann els 4 Chann els RX. CTS. REG. CK. 2. TRACECLK TRACED[0:3] as AS STM32F103x4.MISO. STM32F103x6 STM32F103xx performance line block diagram TPIU SW/JTAG Trace/trig pbu s Ibus Trace Controlle r POWER VOLT. channels ETR and BKIN MOSI.NSS as AF RX. SCK. STM32F103x6 Figure 2. TIM3 If (APB1 prescaler =1) x1 TIMXCLK else x2 Peripheral Clock Enable (3 bits) PLLXTPRE OSC_OUT OSC_IN 4-16 MHz HSE OSC /2 APB2 Prescaler /1. 2. both HSE and PLL must be enabled.STM32F103x4. TIM3 to TIM2. with the CPU running at either 48 MHz or 72 MHz. x16 x2. To have an ADC conversion time of 1 µs. 16 36 MHz max CSS TIM2.512 max AHB Prescaler APB1 Prescaler /1. Doc ID 15060 Rev 3 11/80 . core. x3. 8. 3. 1. the maximum system clock frequency that can be achieved is 64 MHz. Clock tree 8 MHz HSI RC Description HSI /2 USB Prescaler /1. 16 72 MHz max Peripheral Clock Enable (11 bits) PCLK2 to APB2 peripherals TIM1 timer to TIM1 If (APB2 prescaler =1) x1 TIM1CLK else x2 Peripheral Clock LSE to RTC /128 OSC32_IN OSC32_OUT LSE OSC 32. 28 MHz or 56 MHz. 2. 6. For the USB function to be available. When the HSI is used as a PLL clock input. 4.768 kHz ADC Prescaler /2. 4. 2.5 48 MHz USBCLK to USB interface HCLK to AHB bus.. 4. 2.... 8 Enable (1 bit) to ADC RTCCLK RTCSEL[1:0] ADCCLK LSI RC 40 kHz LSI to Independent Watchdog (IWDG) IWDGCLK Legend: Main Clock Output /2 PLLCLK HSI HSE SYSCLK MCO HSE = high-speed external clock signal HSI = high-speed internal clock signal LSI = low-speed internal clock signal LSE = low-speed external clock signal MCO ai15176 1. 8. memory and DMA to Cortex System timer FCLK Cortex free running clock PCLK1 to APB1 peripherals Peripheral Clock Enable (13 bits) 72 MHz max Clock Enable (3 bits) PLLSRC PLLMUL . x4 PLL HSI PLLCLK HSE SW SYSCLK /8 72 MHz /1. APB2 must be at 14 MHz. the reference datasheet for electrical characteristics is that of the STM32F103x8/B medium-density devices. the STM32F103x8 and STM32F103xB are referred to as medium-density devices. 2 × I2Ss. respectively.Description STM32F103x4. the STM32F103x4 and STM32F103x6 are identified as low-density devices. 2 × basic timers 3 × SPIs. CAN. 1 × PWM timer 2 × ADCs 5 × USARTs 4 × 16-bit timers. they are specified in the STM32F103x4/6 and STM32F103xC/D/E datasheets. For orderable part numbers that do not show the A internal code after the temperature range code (6 or 7). the STM32F103xx performance line family is fully compatible with all existing STM32F101xx access line and STM32F102xx USB access line devices. software and feature compatible. High-density devices have higher Flash memory and RAM capacities. Moreover. 12/80 Doc ID 15060 Rev 3 . The STM32F103x4. USB. and additional peripherals like SDIO. STM32F103xC. CAN. and the STM32F103xC. 1 × SDIO FSMC (100 and 144 pins) 1. 2 × PWM timers 3 × ADCs. I2S and DAC. 2 × I2Cs USB. allowing the user to try different memory densities and providing a greater degree of freedom during the development cycle. 1 × I2C. STM32F103xx family Low-density devices Pinout 16 KB Flash 32 KB Flash(1) Medium-density devices 64 KB Flash 128 KB Flash High-density devices 256 KB Flash 384 KB Flash 512 KB Flash 6 KB RAM 10 KB RAM 20 KB RAM 20 KB RAM 48 KB RAM 64 KB RAM 64 KB RAM 144 100 64 48 36 2 × USARTs 2 × 16-bit timers 1 × SPI. 2 × I2Cs.2 Full compatibility throughout the family The STM32F103xx is a complete family whose members are fully pin-to-pin. 2 × DACs. STM32F103xD and STM32F103xE are a drop-in replacement for STM32F103x8/B medium-density devices. USB. STM32F103x6 2. In the reference manual. CAN. Lowdensity devices feature lower Flash memory and RAM capacities. less timers and peripherals. while remaining fully compatible with the other members of the STM32F103xx family. Table 3. Low. STM32F103xD and STM32F103xE are referred to as high-density devices. STM32F103x6. FSMC.and high-density devices are an extension of the STM32F103x8/B devices. 1 × PWM timer 2 × ADCs 3 × USARTs 3 × 16-bit timers 2 × SPIs. while delivering outstanding computational performance and an advanced system response to interrupts. 2.3 CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. with a reduced pin count and low-power consumption. delivering the high-performance expected from an ARM core in the memory size usually associated with 8. CRC-based techniques are used to verify data transmission or storage integrity. is therefore compatible with all ARM tools and software. The STM32F103xx performance line family having an embedded ARM core. The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency. to be compared with a reference signature generated at linktime and stored at a given memory location. In the scope of the EN/IEC 60335-1 standard.1 Overview ARM® Cortex™-M3 core with embedded Flash and SRAM The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation.and 16-bit devices.3 2.3. ● ● ● ● ● ● ● ● Closely coupled NVIC gives low-latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Support for tail-chaining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead Doc ID 15060 Rev 3 13/80 .2 Embedded Flash memory 16 or 32 Kbytes of embedded Flash is available for storing programs and data.3. Figure 1 shows the general block diagram of the device family.3.3. 2.5 Nested vectored interrupt controller (NVIC) The STM32F103xx performance line embeds a nested vectored interrupt controller able to handle up to 43 maskable interrupt channels (not including the 16 interrupt lines of Cortex™-M3) and 16 priority levels. 2.STM32F103x4. STM32F103x6 Description 2. 2. The CRC calculation unit helps compute a signature of the software during runtime.3. they offer a means of verifying the Flash memory integrity.4 Embedded SRAM Six or ten Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. Among other applications. external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.10 Power supply supervisor The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. both) and can be masked independently. respectively. Provided externally through VDD pins. A pending register maintains the status of the interrupt requests. and ensures proper operation starting from/down to 2 V. boot pins are used to select one of three boot options: ● ● ● Boot from User Flash Boot from System Memory Boot from embedded SRAM The boot loader is located in System Memory. the system automatically switches back to the internal RC oscillator. It is used to reprogram the Flash memory by using USART1. VSSA. VDDA and VSSA must be connected to VDD and VSS. 2.8 Boot modes At startup. Similarly. For further details please refer to AN2606. in which case it is monitored for failure.3.6 V: power supply for RTC.Description STM32F103x4.3.7 Clocks and startup System clock selection is performed on startup.0 to 3. An external 4-16 MHz clock can be selected. 2. VDDA = 2. STM32F103x6 This hardware block provides flexible interrupt management features with minimal interrupt latency.9 Power supply schemes ● ● VDD = 2. VBAT = 1. Each line can be independently configured to select the trigger event (rising edge. however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. See Figure 2 for details on the clock tree.6 V: external power supply for I/Os and the internal regulator. The device remains 14/80 Doc ID 15060 Rev 3 . reset blocks. falling edge. If failure is detected. full interrupt management of the PLL clock entry is available when necessary (for example on failure of an indirectly used external crystal. Several prescalers allow the configuration of the AHB frequency. 2. The maximum allowed frequency of the low-speed APB domain is 36 MHz. 2.3. refer to Figure 10: Power supply scheme.3. 2.3. the high-speed APB (APB2) and the low-speed APB (APB1) domains. A software interrupt is generated if enabled. The maximum frequency of the AHB and the high-speed APB domains is 72 MHz.8 to 3.4 V when the ADC is used). It is always active. resonator or oscillator). ● For more details on how to connect power pins. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period.6 External interrupt/event controller (EXTI) The external interrupt/event controller consists of 19 edge detector lines used to generate interrupt/event requests. RCs and PLL (minimum voltage to be applied to VDDA is 2.0 to 3.6 V: external analog power supplies for ADC. Up to 51 GPIOs can be connected to the 16 external interrupt lines. the PVD output. Note: The RTC. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. Refer to Table 11: Embedded reset and power control block characteristics for the values of VPOR/PDR and VPVD.8 V domain are stopped. The device can be woken up from Stop mode by any of the EXTI line. or an RTC alarm occurs. the IWDG. The internal voltage regulator is switched off so that the entire 1. ● ● ● MR is used in the nominal regulation mode (Run) LPR is used in the Stop mode Power down is used in Standby mode: the regulator output is in high impedance: the kernel circuitry is powered down. the PLL. ● Standby mode The Standby mode is used to achieve the lowest power consumption.11 Voltage regulator The regulator has three operation modes: main (MR). the HSI RC and the HSE crystal oscillators are also switched off.3. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold.8 V domain is powered off. All clocks in the 1. an IWDG reset. It is disabled in Standby mode. STM32F103x6 Description in reset mode when VDD is below a specified threshold.12 Low-power modes The STM32F103xx performance line supports three low-power modes to achieve the best compromise between low power consumption. The device exits Standby mode when an external reset (NRST pin). 2. The EXTI line source can be one of the 16 external lines. and the corresponding clock sources are not stopped by entering Stop or Standby mode. low power (LPR) and power down. SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. the HSI RC and the HSE crystal oscillators are disabled. the RTC alarm or the USB wakeup. ● Stop mode The Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. The PLL. The PVD is enabled by software. short startup time and available wakeup sources: ● Sleep mode In Sleep mode. inducing zero consumption (but the contents of the registers and SRAM are lost) This regulator is always enabled after reset. Doc ID 15060 Rev 3 15/80 .STM32F103x4. only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. without the need for an external reset circuit. After entering Standby mode.3. a rising edge on the WKUP pin. VPOR/PDR. 2. providing high impedance output. The voltage regulator can also be put either in normal or in low power mode. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. peripheral-to-memory and memory-to-peripheral transfers. It is clocked by a 32.768 kHz. USART. Timer Timer feature comparison Counter resolution 16-bit Counter type Up.13 DMA The flexible 7-channel general-purpose DMA is able to manage memory-to-memory. The RTC can be calibrated using an external 512 Hz output to compensate for any natural crystal deviation.768 kHz external crystal. The real-time clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function. down. the internal low-power RC oscillator or the high-speed external clock divided by 128.15 Timers and watchdogs The low-density STM32F101xx performance line devices include an advanced-control timer. up/down Prescaler factor Any integer between 1 and 65536 Any integer between 1 and 65536 DMA request Capture/compare Complementary generation channels outputs Yes 4 Yes TIM1 TIM2. general-purpose and advanced-control timers TIMx and ADC. The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer.3. and provides an alarm interrupt and a periodic interrupt.3. The backup registers are ten 16-bit registers used to store 20 bytes of user application data when VDD power is not present. TIM3 16-bit Yes 4 No 16/80 Doc ID 15060 Rev 3 .Description STM32F103x4. up/down Up. two watchdog timers and a SysTick timer. with support for software trigger on each channel.14 RTC (real-time clock) and backup registers The RTC and the backup registers are supplied through a switch that takes power either on VDD supply when present or through the VBAT pin. Table 4 compares the features of the advanced-control and general-purpose timers. STM32F103x6 2. Table 4. Each channel is connected to dedicated hardware DMA requests. A 20-bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32. two general-purpose timers. The DMA can be used with the main peripherals: SPI. I2C. 2. The RTC features a 32-bit programmable counter for long-term measurement using the Compare register to generate an alarm. resonator or oscillator. 2. Configuration is made by software and transfer sizes between source and destination are independent. The internal low-power RC has a typical frequency of 40 kHz.3. down. Independent watchdog The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. The advanced-control timer can therefore work together with the TIM timers via the Timer Link feature for synchronization or event chaining. It can be used either as a watchdog to reset the device when a problem occurs. it has the same features as the TIMx timer. It is clocked from the main clock. It can be used as a watchdog to reset the device when a problem occurs. This gives up to 12 input captures/output compares/PWMs on the largest packages. it has full modulation capability (0-100%). It can also be seen as a complete general-purpose timer. STM32F103x6 Description Advanced-control timer (TIM1) The advanced-control timer (TIM1) can be seen as a three-phase PWM multiplexed on 6 channels.or center-aligned modes) One-pulse mode output If configured as a general-purpose 16-bit timer. It has an early warning interrupt capability and the counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. The 4 independent channels can be used for ● ● ● ● Input capture Output compare PWM generation (edge. or as a free-running timer for application timeout management. It is hardware.STM32F103x4. It has complementary PWM outputs with programmable inserted dead-times.or software-configurable through the option bytes. In debug mode. PWM or one-pulse mode output. Doc ID 15060 Rev 3 17/80 . it can operate in Stop and Standby modes. Many features are shared with those of the general-purpose TIM timers which have the same architecture. They all have independent DMA request generation. These timers are based on a 16-bit auto-reload up/down counter. The general-purpose timers can work together with the advanced-control timer via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. It is clocked from an independent 40 kHz internal RC and as it operates independently of the main clock. Window watchdog The window watchdog is based on a 7-bit downcounter that can be set as free-running. General-purpose timers (TIMx) There are up to two synchronizable general-purpose timers embedded in the STM32F103xx performance line devices. If configured as the 16-bit PWM generator. The counter can be frozen in debug mode. the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switch driven by these outputs. a 16-bit prescaler and feature 4 independent channels each for input capture/output compare. 2.3. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. The USB interface implements a full-speed (12 Mbit/s) function interface. 2. The SPI interface can be served by the DMA controller. It supports dual slave addressing (7-bit only) and both 7/10-bit addressing in master mode. 2.Description STM32F103x4. 18/80 Doc ID 15060 Rev 3 .3.3.19 Controller area network (CAN) The CAN is compliant with specifications 2. The other available interface communicates at up to 2. It can support standard and fast modes.20 Universal serial bus (USB) The STM32F103xx performance line embeds a USB device peripheral compatible with the USB full-speed 12 Mbs. It features: ● ● ● ● A 24-bit downcounter Autoreload capability Maskable system interrupt generation when the counter reaches 0 Programmable clock source 2.5 Mbit/s. but could also be used as a standard downcounter. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits.25 Mbit/s. are ISO 7816 compliant and have LIN Master/Slave capability. two receive FIFOs with 3 stages and 14 scalable filter banks. A hardware CRC generation/verification is embedded.18 Serial peripheral interface (SPI) The SPI interface is able to communicate up to 18 Mbits/s in slave and master modes in fullduplex and simplex communication modes.0A and B (active) with a bit rate up to 1 Mbit/s. It has three transmit mailboxes. IrDA SIR ENDEC support.17 Universal synchronous/asynchronous receiver transmitter (USART) One of the USART interfaces is able to communicate at speeds of up to 4. All USART interfaces can be served by the DMA controller. They provide hardware management of the CTS and RTS signals. 2. It has software-configurable endpoint setting and suspend/resume support. The hardware CRC generation/verification supports basic SD Card/MMC modes.3.3. STM32F103x6 SysTick timer This timer is dedicated for OS.16 I²C bus The I²C bus interface can operate in multimaster and slave modes.0/PM Bus. It can be served by DMA and they support SM Bus 2. 2.3. In scan mode. and DMA trigger respectively. Additional logic functions embedded in the ADC interface allow: ● ● ● Simultaneous sample and hold Interleaved sample and hold Single shunt The ADC can be served by the DMA controller. 2.22 ADC (analog-to-digital converter) Two 12-bit analog-to-digital converters are embedded into STM32F103xx performance line devices and each ADC shares up to 16 external channels. Most of the GPIO pins are shared with digital or analog alternate functions. An interrupt is generated when the converted voltage is outside the programmed thresholds.6 V. The conversion range is between 2 V < VDDA < 3. as input (with or without pull-up or pull-down) or as peripheral alternate function. automatic conversion is performed on a selected group of analog inputs.23 Temperature sensor The temperature sensor has to generate a voltage that varies linearly with temperature. and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. performing conversions in singleshot or scan modes.24 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP Interface is embedded. respectively.STM32F103x4. STM32F103x6 Description 2. some or all selected channels. to allow the application to synchronize A/D conversion and timers.3. I/Os on APB2 with up to 18 MHz toggling speed 2. The JTAG TMS and TCK pins are shared with SWDIO and SWCLK.3. Doc ID 15060 Rev 3 19/80 . All GPIOs are high-currentcapable except for analog inputs. The temperature sensor is internally connected to the ADC12_IN16 input channel which is used to convert the sensor output voltage into a digital value.3. An analog watchdog feature allows very precise monitoring of the converted voltage of one.21 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain). injection trigger. The events generated by the general-purpose timers (TIMx) and the advanced-control timer (TIM1) can be internally connected to the ADC start trigger. and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers. Pinouts and pin description STM32F103x4. STM32F103xx performance line LQFP64 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PD2 PC12 PC11 PC10 PA15 PA14 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0 OSC_IN PD1 OSC_OUT NRST PC0 PC1 PC2 PC3 VSSA VDDA PA0-WKUP PA1 PA2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 LQFP64 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PB15 PB14 PB13 PB12 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 ai14392 20/80 Doc ID 15060 Rev 3 . STM32F103x6 3 Pinouts and pin description Figure 3. STM32F103x6 Figure 4. Pinouts and pin description STM32F103xx performance line TFBGA64 ballout 1 2 3 4 5 6 7 8 A PC14PC13OSC32_IN TAMPER-RTC PB9 PB4 PB3 PA15 PA14 PA13 B PC15OSC32_OUT VBAT PB8 BOOT0 PD2 PC11 PC10 PA12 C OSC_IN VSS_4 PB7 PB5 PC12 PA10 PA9 PA11 D OSC_OUT VDD_4 PB6 VSS_3 VSS_2 VSS_1 PA8 PC9 E NRST PC1 PC0 VDD_3 VDD_2 VDD_1 PC7 PC8 F VSSA PC2 PA2 PA5 PB0 PC6 PB15 PB14 G VREF+ PA0-WKUP PA3 PA6 PB1 PB2 PB10 PB13 H VDDA PA1 PA4 PA7 PC4 PC5 PB11 PB12 AI15494 Doc ID 15060 Rev 3 21/80 .STM32F103x4. Pinouts and pin description Figure 5. STM32F103x4. STM32F101xx Medium-density access line VFQFPN36 pinout BOOT0 VSS_3 PA15 PA14 PB7 PB6 PB5 PB4 PB3 36 VDD_3 OSC_IN/PD0 OSC_OUT/PD1 NRST VSSA VDDA PA0-WKUP PA1 PA2 1 2 3 4 5 6 7 8 9 10 35 34 33 32 31 30 29 28 27 26 25 24 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 VDD_1 QFN36 23 22 21 20 19 18 11 12 13 14 15 16 17 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 VSS_1 ai14654 22/80 Doc ID 15060 Rev 3 . STM32F103x6 STM32F103xx performance line LQFP48 pinout VDD_3 VSS_3 PB9 PB8 BOOT0 PB7 PB6 PB5 PB4 PB3 PA15 PA14 VBAT PC13-TAMPER-RTC PC14-OSC32_IN PC15-OSC32_OUT PD0-OSC_IN PD1-OSC_OUT NRST VSSA VDDA PA0-WKUP PA1 PA2 48 47 46 45 44 43 42 41 40 39 38 37 36 1 2 35 3 34 33 4 32 5 31 6 LQFP48 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 VDD_2 VSS_2 PA13 PA12 PA11 PA10 PA9 PA8 PB15 PB14 PB13 PB12 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 ai14393b Figure 6. STM32F103x6 Table 5.STM32F103x4. Pins VFQFPN36 TFBGA64 LQFP48 LQFP64 Pin name Type(1) Pinouts and pin description Low-density STM32F103xx pin definitions I / O Level(2) Alternate functions(4) Main function(3) (after reset) Default Remap 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 B2 A2 A1 B1 C1 D1 E1 E3 E2 F2 G1 F1 H1 G2 2 3 4 5 6 7 VBAT PC13-TAMPERRTC(5) S I/O VBAT PC13(6) PC14(6) PC15(6) OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VREF+ VSSA VDDA PA0 WKUP/USART2_CTS/ ADC12_IN0/ TIM2_CH1_ETR(8) USART2_RTS/ ADC12_IN1/ TIM2_CH2(8) USART2_TX/ ADC12_IN2/ TIM2_CH3(8) USART2_RX/ ADC12_IN3/TIM2_CH4(8) ADC12_IN10 ADC12_IN11 ADC12_IN12 ADC12_IN13 TAMPER-RTC OSC32_IN OSC32_OUT PC14-OSC32_IN(5) I/O PC15OSC32_OUT(5) OSC_IN OSC_OUT NRST PC0 PC1 PC2 PC3 VREF+(7) VSSA VDDA PA0-WKUP I/O I O I/O I/O I/O I/O I/O S S S I/O 11 12 13 14 15 16 17 - 15 16 17 18 19 20 21 22 23 24 H2 F3 G3 C2 D2 H3 F4 G4 H4 H5 8 9 10 11 12 13 14 PA1 PA2 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 I/O I/O I/O S S I/O I/O I/O I/O I/O PA1 PA2 PA3 VSS_4 VDD_4 PA4 PA5 PA6 PA7 PC4 SPI1_NSS(8)/ USART2_CK/ADC12_IN4 SPI1_SCK(8)/ ADC12_IN5 SPI1_MISO(8)/ ADC12_IN6/TIM3_CH1(8) SPI1_MOSI(8)/ ADC12_IN7/TIM3_CH2(8) ADC12_IN14 TIM1_BKIN TIM1_CH1N Doc ID 15060 Rev 3 23/80 . Pins VFQFPN36 TFBGA64 LQFP48 LQFP64 Pin name Type(1) STM32F103x4.Pinouts and pin description Table 5. STM32F103x6 Low-density STM32F103xx pin definitions (continued) I / O Level(2) Alternate functions(4) Main function(3) (after reset) Default Remap 18 19 20 21 22 23 24 25 26 27 28 - 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 H6 F5 G5 G6 G7 H7 D6 E6 H8 G8 F8 F7 F6 E7 E8 D8 D7 C7 C6 C8 B8 A8 D5 E5 A7 A6 B7 B6 C5 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 PC5 PB0 PB1 PB2 PB10 PB11 VSS_1 VDD_1 PB12 PB13 PB14 PB15 PC6 PC7 PC8 PC9 PA8 PA9 PA10 PA11 PA12 PA13 VSS_2 VDD_2 PA14 PA15 PC10 PC11 PC12 I/O I/O I/O PC5 PB0 PB1 ADC12_IN15 ADC12_IN8/TIM3_CH3(8) ADC12_IN9/TIM3_CH4 (8) TIM1_CH2N TIM1_CH3N I/O FT PB2/BOOT1 I/O FT I/O FT S S I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT I/O FT PB10 PB11 VSS_1 VDD_1 PB12 PB13 PB14 PB15 PC6 PC7 PC8 PC9 PA8 PA9 PA10 PA11 PA12 USART1_CK/ TIM1_CH1/MCO USART1_TX(8)/ TIM1_CH2(8) USART1_RX(8)/ TIM1_CH3 USART1_CTS/ CAN_RX(8)/ TIM1_CH4 / USBDM USART1_RTS/ CAN_TX(8) / TIM1_ETR / USBDP PA13 TIM1_BKIN(8) TIM1_CH1N (8) TIM1_CH2N (8) TIM1_CH3N(8) TIM3_CH1 TIM3_CH2 TIM3_CH3 TIM3_CH4 TIM2_CH3 TIM2_CH4 29 30 31 32 33 34 35 36 37 38 - 40 41 42 43 44 45 46 47 48 49 50 51 52 53 I/O FT JTMS/SWDIO S S VSS_2 VDD_2 I/O FT JTCK/SWCLK I/O FT I/O FT I/O FT I/O FT JTDI PC10 PC11 PC12 PA14 TIM2_CH1_ETR/ PA15 / SPI1_NSS 24/80 Doc ID 15060 Rev 3 . For devices having reduced peripheral counts. FT = 5 V tolerant. Pins VFQFPN36 TFBGA64 LQFP48 LQFP64 Pin name Type(1) Pinouts and pin description Low-density STM32F103xx pin definitions (continued) I / O Level(2) Alternate functions(4) Main function(3) (after reset) OSC_IN(9) Default Remap 5 6 5 6 54 C1 D1 B5 A5 2 3 30 PD0 PD1 PD2 PB3 I/O FT I/O FT OSC_OUT(9) I/O FT I/O FT PD2 JTDO TIM3_ETR TIM2_CH2 / PB3/ TRACESWO SPI1_SCK TIM3_CH1 /PB4 SPI1_MISO I2C1_SMBA I2C1_SCL(8)/ I2C1_SDA(8) TIM3_CH2 / SPI1_MOSI USART1_TX USART1_RX 39 55 40 41 42 43 44 45 46 47 48 56 57 58 59 60 61 62 63 64 A4 C4 D3 C3 B4 B3 A3 D4 E4 31 32 33 34 35 36 1 PB4 PB5 PB6 PB7 BOOT0 PB8 PB9 VSS_3 VDD_3 I/O FT I/O I/O FT I/O FT I I/O FT I/O FT S S NJTRST PB5 PB6 PB7 BOOT0 PB8 PB9 VSS_3 VDD_3 I2C1_SCL /CAN_RX I2C1_SDA / CAN_TX 1. I = input. PC13.st. For more details. available from the STMicroelectronics website: www. The pins number 2 and 3 in the VFQFPN36 package. Since the switch only sinks a limited amount of current (3 mA). the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these IOs must not be used as a current source (e. refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual. respectively. however the functionality of PD0 and PD1 can be remapped by software on these pins. Refer to Table 2 on page 9. 3. they will be called SPI1 and USART1 & USART2. there is no PC3 in the TFBGA64 package. to avoid conflict between these alternate functions only one peripheral should be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register). This alternate function can be remapped by software to some other port pins (if available on the used package). Function availability depends on the chosen device. For details on how to manage these IOs. Main function after the first backup domain power-up. If several peripherals share the same I/O pin. S = supply. Unlike in the LQFP64 package. 8. 5. it depends on the contents of the Backup registers even after reset (because these registers are not reset by the main reset). refer to the Battery backup domain and BKP register description sections in the STM32F10xxx reference manual.com.st. Doc ID 15060 Rev 3 25/80 . 5 and 6 in the LQFP48 and LQFP64 packages and C1 and C2 in the TFBGA64 package are configured as OSC_IN/OSC_OUT after reset. 6. if a device has only one SPI and two USARTs. 2. PC14 and PC15 are supplied through the power switch.g. The VREF+ functionality is provided instead. available from the STMicroelectronics website: www. For more details.STM32F103x4. O = output. 7. it is always the lower number of peripheral that is included. Later on. refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual.com. 4. STM32F103x6 Table 5. to drive an LED). For example. 9. Memory mapping STM32F103x4. 0xFFFF FFFF Memory map APB memory space 0xFFFF FFFF 0x4002 3400 reserved 7 0xE010 0000 0xE000 0000 Cortex-M3 Internal Peripherals CRC 0x4002 3000 reserved 0x4002 2400 Flash Interface 0x4002 2000 reserved 0x4002 1400 0x4002 1000 RCC reserved 6 0xC000 0000 0x4002 0400 DMA 0x4002 0000 reserved 0x4001 3C00 0x4001 3800 USART1 reserved SPI 5 0xA000 0000 0x4001 3400 0x4001 3000 TIM1 0x4001 2C00 ADC2 0x4001 2800 ADC1 0x4001 2400 4 0x8000 0000 reserved 0x1FFF FFFF 0x4001 1800 reserved 0x1FFF F80F Option Bytes 0x1FFF F800 Port D 0x4001 1400 Port C 0x4001 1000 Port B 0x4001 0C00 Port A 0x4001 0800 3 0x1FFF F000 0x6000 0000 EXTI System memory 0x4001 0400 AFIO 0x4001 0000 reserved 0x4000 7400 PWR 0x4000 7000 BKP 2 reserved 0x4000 0000 Peripherals 0x4000 6C00 reserved 0x4000 6800 bxCAN 0x4000 6400 0x4000 6000 0x4000 5C00 shared 512 byte USB/CAN SRAM USB Registers reserved 0x4000 5800 0x4000 5400 0x2000 0000 SRAM 0x0801 FFFF 1 I2C reserved 0x4000 4800 0x4000 4400 0x4000 3400 USART2 reserved 0 0x0000 0000 0x0800 0000 IWDG Flash memory 0x4000 3000 WWDG 0x4000 2C00 RTC Aliased to Flash or system memory depending on 0x0000 0000 BOOT pins 0x4000 2800 0x4000 0800 0x4000 0400 0x4000 0000 reserved TIM3 TIM2 Reserved ai15177c 26/80 Doc ID 15060 Rev 3 . STM32F103x6 4 Memory mapping The memory map is shown in Figure 7. Figure 7. the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3). Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range.6 V voltage range). 5. all typical curves are given only as design guidelines and are not tested. design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. 5.1. typical data are based on TA = 25 °C.2 Typical values Unless otherwise specified. STM32F103x6 Electrical characteristics 5 5. where 95% of the devices have an error less than or equal to the value indicated (mean±2).3 Typical curves Unless otherwise specified.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 8. 5.3 V (for the 2 V  VDD  3. 5.1. They are given only as design guidelines and are not tested.1. Data based on characterization results.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 9.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature.STM32F103x4. Based on characterization. Doc ID 15060 Rev 3 27/80 . supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by the selected temperature range).1 Electrical characteristics Parameter conditions Unless otherwise specified. all voltages are referenced to VSS. VDD = 3.1. 5. 1..6V Po wer swi tch Backup circuitry (OSC32K.RTC. Pin input voltage STM32F103xx pin C = 50 pF VIN STM32F103xx pin ai14141 ai14142 5.8-3..6 Power supply scheme Figure 10. . the 4.7 µF capacitor must be connected to VDD3. Wakeup logic Backup registers) OUT Level shifter GP I/Os IN IO Logic Kernel logic (CPU. Pin loading conditions Figure 9. 28/80 Doc ID 15060 Rev 3 .Electrical characteristics STM32F103x4. Power supply scheme VBAT 1. PLL.7 µF VDD VDDA VREF VREF+ 10 nF + 1 µF 10 nF + 1 µF VSSA ADC VREF- Analog: RCs. STM32F103x6 Figure 8. Digital & Memories) VDD VDD 1/2/3/4/5 VSS 1/2/3/4/5 Regulator 5 × 100 nF + 1 × 4. ai15496 Caution: In Figure 10. A positive injection is induced by VIN> VINmax while a negative injection is induced by VIN < VSS.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 6: Voltage characteristics.11: Absolute maximum ratings (electrical sensitivity) V Unit 1.5 VDD+0. These are stress ratings only and functional operation of the device at these conditions is not implied. This is implicitly insured if VIN maximum is respected. VSSA) pins must always be connected to the external power supply. If VIN maximum cannot be respected.3. Symbol VDD–VSS VIN |VDDx| |VSSX VSS| VESD(HBM) Voltage characteristics Ratings External main supply voltage (including VDDA and VDD)(1) Input voltage on five volt tolerant pin(2) Input voltage on any other pin(2) Variations between different VDD power pins Variations between all the different ground pins Electrostatic discharge voltage (human body model) Min –0.3 VSS  0. Table 6.STM32F103x4. IINJ(PIN) must never be exceeded (see Table 7: Current characteristics). Exposure to maximum rating conditions for extended periods may affect device reliability.3 50 mV 50 see Section 5.7 Current consumption measurement Figure 11.3 Max 4.3 VSS 0. Current consumption measurement scheme IDD_VBAT VBAT IDD VDD VDDA ai14126 5. in the permitted range. Table 7: Current characteristics.0 +5. VDDA) and ground (VSS. 2. STM32F103x6 Electrical characteristics 5. the injection current must be limited externally to the IINJ(PIN) value.1. Doc ID 15060 Rev 3 29/80 . All main power (VDD. and Table 8: Thermal characteristics may cause permanent damage to the device. VDDA) and ground (VSS. 2. Thermal characteristics Ratings Storage temperature range Maximum junction temperature Value –65 to +150 150 Unit °C °C Symbol TSTG TJ 5. in the permitted range.1 Operating conditions General operating conditions Table 9. These results are based on characterization with IINJ(PIN) maximum current injection on four I/O port pins of the device. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS.3 5.Electrical characteristics Table 7. All main power (VDD. 3. the injection current must be limited externally to the IINJ(PIN) value.4 1. When several inputs are submitted to a current injection. If VIN maximum cannot be respected.6 V 3. This is implicitly insured if VIN maximum is respected.6 3. 150 150 25  25 Unit Output current sunk by any I/O and control pin Output current source by any I/Os and control pin Injected current on NRST pin IINJ(PIN) (2)(3) IINJ(PIN) (2) mA ±5 ±5 ±5 (4) Injected current on HSE OSC_IN and LSE OSC_IN pins Injected current on any other pin (4) Total injected current (sum of all I/O and control pins) ± 25 1.3.6 3.17: 12-bit ADC characteristics. 4. See note in Section 5.6 V V MHz Unit VDDA(1) VBAT 30/80 Doc ID 15060 Rev 3 . Symbol fHCLK fPCLK1 fPCLK2 VDD General operating conditions Parameter Internal AHB clock frequency Internal APB1 clock frequency Internal APB2 clock frequency Standard operating voltage Analog operating voltage (ADC not used) Analog operating voltage (ADC used) Backup operating voltage Conditions Min 0 0 0 2 2 Must be the same potential as VDD(2) 2. Symbol IVDD IVSS IIO STM32F103x4. STM32F103x6 Current characteristics Ratings Total current into VDD/VDDA power lines (source)(1) Total current out of VSS ground lines (sink) (1) Max. IINJ(PIN) must never be exceeded.3. Negative injection disturbs the analog performance of the device. Table 8.8 Max 72 36 72 3. VSSA) pins must always be connected to the external power supply. the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 10.2 Operating conditions at power-up / power-down Subject to general operating conditions for TA.3. 2.3 Embedded reset and power control block characteristics The parameters given in Table 11 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. It is recommended to power VDD and VDDA from the same source. Symbol tVDD Operating conditions at power-up / power-down Parameter VDD rise time rate VDD fall time rate Conditions Min 0 20 Max Unit µs/V   5. refer to Table 45: ADC characteristics.STM32F103x4. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and operation. TA can be extended to this range as long as TJ does not exceed TJmax (see Table 6. 3. In low power dissipation state. 4.2: Thermal characteristics on page 74). Doc ID 15060 Rev 3 31/80 . higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6. Symbol Electrical characteristics General operating conditions (continued) Parameter Conditions TFBGA64 Min Max 308 444 mW 363 1110 –40 –40 –40 –40 –40 –40 85 °C 105 105 °C 125 105 °C 7 suffix version 125 Unit PD Power dissipation at TA = 85 °C LQFP64 for suffix 6 or TA = 105 °C for LQFP48 suffix 7(3) VFQFPN36 Ambient temperature for 6 suffix version Maximum power dissipation Low power dissipation (4) TA Ambient temperature for 7 suffix version TJ Junction temperature range Maximum power dissipation Low power dissipation 6 suffix version (4) 1. When the ADC is used.3. If TA is lower.2: Thermal characteristics on page 74). 5. STM32F103x6 Table 9. 66 2.38 2.96 2.19 2.28 2.28 2.57 2.26 2.9 2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.8(1) 1.38 2.37 2.78 100 Falling edge Rising edge 1. Guaranteed by design.37 2.92 40 1 2.58 2.27 2.68 2.18 2.69 2.5 1.5 4.28 2.18 2.28 2.88 1.66 Typ 2.38 2.47 2.79 2.48 2.48 2.08 2.48 2. 32/80 Doc ID 15060 Rev 3 .18 2.56 2. not tested in production.1 2 2.59 2.88 2.47 2.38 2.78 2.9 Unit V V V V V V V V V V V V V V V V mV V V mV ms VPVD Programmable voltage detector level selection PLS[2:0]=011 (falling edge) PLS[2:0]=100 (rising edge) PLS[2:0]=100 (falling edge) PLS[2:0]=101 (rising edge) PLS[2:0]=101 (falling edge) PLS[2:0]=110 (rising edge) PLS[2:0]=110 (falling edge) PLS[2:0]=111 (rising edge) PLS[2:0]=111 (falling edge) VPVDhyst(2) VPOR/PDR VPDRhyst (2) (2) PVD hysteresis Power on/power down reset threshold PDR hysteresis Reset temporization TRSTTEMPO 1.Electrical characteristics Table 11.8 3 2. Symbol STM32F103x4.48 2.58 2. STM32F103x6 Embedded reset and power control block characteristics Parameter Conditions PLS[2:0]=000 (rising edge) PLS[2:0]=000 (falling edge) PLS[2:0]=001 (rising edge) PLS[2:0]=001 (falling edge) PLS[2:0]=010 (rising edge) PLS[2:0]=010 (falling edge) PLS[2:0]=011 (rising edge) Min 2.16 2.0 Max 2.58 2.09 2.76 2.84 1.69 2.68 2. 2. Doc ID 15060 Rev 3 33/80 . All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.STM32F103x4.1(2) Unit V V µs ADC sampling time when TS_vrefint(1) reading the internal reference voltage Internal reference voltage VRERINT(2) spread over the temperature range TCoeff(2) Temperature coefficient VDD = 3 V ±10 mV 10 100 mV ppm/°C 1. Symbol VREFINT Embedded internal reference voltage Parameter Internal reference voltage Conditions –40 °C < TA < +105 °C –40 °C < TA < +85 °C Min 1. 5. Maximum current consumption The MCU is placed under the following conditions: ● ● ● ● ● All I/O pins are in input mode with a static value at VDD or VSS (no load) All peripherals are disabled except when explicitly mentioned The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0 to 24 MHz. Table 14 and Table 15 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. STM32F103x6 Electrical characteristics 5. not tested in production.20 1. Guaranteed by design.3.16 1. I/O pin switching rate.20 5. 2.1 code. device software configuration. Shortest sampling time can be determined in the application by multiple iterations. program location in memory and executed binary code.3. operating frequencies.16 Typ 1. The current consumption is measured as described in Figure 11: Current consumption measurement scheme.24 17.4 Embedded reference voltage The parameters given in Table 12 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. I/O pin loading. 1 wait state from 24 to 48 MHz and 2 wait states above) Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/2. Table 12. fPCLK2 = fHCLK The parameters given in Table 13.5 Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage.1 Max 1. ambient temperature.26 1. 2. all 36 MHz peripherals disabled 24 MHz 16 MHz 8 MHz 1.Electrical characteristics Table 13. Based on characterization. not tested in production. Table 14. STM32F103x4. code with data processing running from Flash Max(1) Parameter Conditions fHCLK TA = 85 °C 72 MHz 48 MHz External clock(2). Maximum current consumption in Run mode. 2. all 36 MHz peripherals disabled 24 MHz 16 MHz 8 MHz 31 24 20 14 11 7 Unit Symbol IDD Supply current in Run mode 8 MHz 1. 34/80 Doc ID 15060 Rev 3 . tested in production at VDD max. Based on characterization. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. all peripherals enabled 36 MHz 24 MHz 16 MHz Unit TA = 85 °C 41 27 20 14 10 6 27 19 15 10 7 5 TA = 105 °C 42 28 21 15 11 7 28 20 16 11 8 6 mA Symbol IDD Supply current in Run mode 8 MHz 72 MHz 48 MHz External clock(2). External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. code with data processing running from RAM Max(1) Parameter Conditions fHCLK 72 MHz 48 MHz External clock(2). all peripherals enabled 36 MHz 24 MHz 16 MHz 45 32 26 18 13 7 30 23 19 13 10 6 TA = 105 °C 46 33 27 19 14 8 mA 72 MHz 48 MHz External clock(2). STM32F103x6 Maximum current consumption in Run mode. fHCLK max. 6 V) code with data processing running from RAM. Typical current consumption in Run mode versus frequency (at 3. Typical current consumption in Run mode versus frequency (at 3. peripherals enabled 45 40 35 Consumption (mA) 30 72 MHz 25 20 15 10 5 0 – 45°C 25 °C 70 °C Temperature (°C) 85 °C 105 °C 36 MHz 16 MHz 8 MHz Figure 13.6 V) code with data processing running from RAM. STM32F103x6 Electrical characteristics Figure 12.STM32F103x4. peripherals disabled 30 25 Consumption (mA) 20 72 MHz 15 36 MHz 16 MHz 8 MHz 10 5 0 – 45°C 25 °C 70 °C Temperature (°C) 85 °C 105 °C Doc ID 15060 Rev 3 35/80 . 5 4 mA Symbol IDD Supply current in Sleep mode 8 MHz 72 MHz 48 MHz External clock(2). code running from Flash or RAM Max(1) Parameter Conditions fHCLK 72 MHz 48 MHz External clock(2).5 5 4. all peripherals enabled 36 MHz 24 MHz 16 MHz Unit TA = 85 °C 26 17 14 10 7 4 7.Electrical characteristics Table 15.5 5.5 4 3 TA = 105 °C 27 18 15 11 8 5 8 6.5 6 5 4. tested in production at VDD max. STM32F103x4. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. 2. 36/80 Doc ID 15060 Rev 3 . all peripherals disabled 36 MHz 24 MHz 16 MHz 8 MHz 1. STM32F103x6 Maximum current consumption in Sleep mode. fHCLK max with peripherals enabled. based on characterization. 2 - - µA - 1.3 11. 2.75 2.9(2) 2.1 1.7 145 185 IDD - 2.0 V = 2.5 0 –40 °C 25 °C 70 °C Temperature (°C) ai17351 2V 2.5 Consumption ( µA ) 2 1.4 V 3V 3.STM32F103x4.9 1. Typical current consumption on VBAT with RTC on versus temperature at different VBAT values 2.5 1 0.3 V 85 °C 105 °C Regulator in Run mode. independent watchdog OFF mode Low-speed internal RC oscillator and independent watchdog OFF. not tested in production.9 3. lowspeed oscillator and RTC OFF Backup IDD_VBAT domain supply Low-speed oscillator and RTC ON current 1.7 160 200 - 11. Typical values are measured at TA = 25 °C.3 21.2 4.55 1.4 V = 3. Based on characterization.5 0.4 1. low-speed and high-speed internal RC oscillators and high-speed oscillator Supply current OFF (no independent watchdog) in Stop mode Regulator in Low Power mode. Symbol Electrical characteristics Typical and maximum current consumptions in Stop and Standby modes Typ(1) Parameter Conditions Max VDD/VBAT VDD/VBAT VDD/VBAT TA = TA = Unit = 2. lowspeed and high-speed internal RC oscillators and high-speed oscillator OFF (no independent watchdog) Low-speed internal RC oscillator and independent watchdog ON Supply current Low-speed internal RC oscillator in Standby ON.6 V 85 °C 105 °C Doc ID 15060 Rev 3 37/80 . - 21.2 Figure 14.4 3. STM32F103x6 Table 16.55 3. 6 V 120 100 Consumption (µA) 80 3. Typical current consumption in Stop mode with regulator in Run mode versus temperature at VDD = 3. STM32F103x6 Figure 15.3 V 3. Typical current consumption in Stop mode with regulator in Low-power mode versus temperature at VDD = 3.6 V 60 40 20 0 –45 °C 25 °C 85 °C 105 °C Temperature (°C) Figure 16.6 V 38/80 Doc ID 15060 Rev 3 .6 V 90 80 70 Consumption (µA) 60 50 40 30 20 10 0 –45 °C 25 °C 85 °C 105 °C Temperature (°C) 3.3 V and 3.Electrical characteristics STM32F103x4.3 V 3.3 V and 3. 5 Consumption (µA) 3 2.6 V Typical current consumption The MCU is placed under the following conditions: ● ● ● ● ● ● All I/O pins are in input mode with a static value at VDD or VSS (no load).5 1 0.STM32F103x4.5 4 3. All peripherals are disabled except if it is explicitly mentioned.5 2 1. 1 wait state from 24 to 48 MHz and 2 wait states above). STM32F103x6 Electrical characteristics Figure 17.3 V 3.6 V 4.5 0 –45 °C 25 °C 85 °C 105 °C Temperature (°C) 3. Typical current consumption in Standby mode versus temperature at VDD = 3. fADCCLK = fPCLK2/4 Doc ID 15060 Rev 3 39/80 . fPCLK2 = fHCLK/2.3 V and 3. The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz. Ambient temperature and VDD supply voltage conditions summarized in Table 9. Prefetch is ON (Reminder: this bit must be set before clock setting and bus prescaling) When the peripherals are enabled fPCLK1 = fHCLK/4. Typical values are measures at TA = 25 °C.5 1.8 8.9 0.2 11.65 0. STM32F103x6 Typical current consumption in Run mode.4 1. Add an additional power consumption of 0.3 21.5 17. 40/80 Doc ID 15060 Rev 3 .3 2.4 1.6 4. VDD = 3. 2.5 24. STM32F103x4.7 13.45 72 MHz 48 MHz 36 MHz 24 MHz 16 MHz External clock (3) 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz mA IDD Supply current in Run mode 125 kHz 64 MHz 48 MHz 36 MHz Running on high speed internal RC (HSI). this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).4 4.3 V.6 21.2 5.6 1. 3.5 7.6 16.2 2.2 16. AHB prescaler used to reduce the frequency 24 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 125 kHz mA 1.1 8.8 mA per ADC for the analog part.4 13. In applications.7 0.9 17.5 10.8 1.2 1 21.Electrical characteristics Table 17.9 3.5 1 0.2 1.6 2 1.9 6. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz. code with data processing running from Flash Typ(1) Parameter Conditions fHCLK Unit Symbol All peripherals All peripherals disabled enabled(2) 31.05 27.1 5 3 2 1.2 8.3 0. 2 0. this consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).8 mA per ADC for the analog part.2 2.2 3.5 0.1 2.48 0. Electrical characteristics Typical current consumption in Sleep mode.8 1.8 1.42 0.6 8. Typical values are measures at TA = 25 °C.4 5. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.9 0. code running from Flash or RAM Typ(1) Conditions fHCLK Unit Symbol Parameter All peripherals All peripherals enabled(2) disabled 12.3 V. Add an additional power consumption of 0.2 2.8 3.3 3.4 2 1.7 0.98 0.1 6. Doc ID 15060 Rev 3 41/80 .1 1 0.38 1.7 6.6 8.8 3.95 72 MHz 48 MHz 36 MHz 24 MHz 16 MHz External clock (3) 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz IDD Supply current in Sleep mode 125 kHz 64 MHz 48 MHz 36 MHz 24 MHz Running on high 16 MHz speed internal RC (HSI).05 1 10.1 1.55 0.7 1. In applications. 2.5 1.55 0. AHB prescaler 8 MHz used to reduce the 4 MHz frequency 2 MHz 1 MHz 500 kHz 125 kHz mA 4.7 4.4 0.45 0.2 1.4 0. STM32F103x6 Table 18.25 1. 3.96 0.STM32F103x4.3 1. VDD = 3.1 4.5 1. Specific conditions for ADC: fHCLK = 56 MHz.Electrical characteristics STM32F103x4.72 0.2 1.35 Unit APB1 I2C USB CAN GPIO A GPIO B GPIO C GPIO D APB2 ADC1 ADC2 TIM1 SPI USART1 (2) mA 0.6 0.47 0.3.47 0. 2. 5. fAPB2 = fHCLK.2 0.6 External clock source characteristics High-speed external user clock generated from an external source The characteristics given in Table 20 result from tests performed using an high-speed external clock source. Typical consumption at 25 °C 1.85 mA 1. fAPB2 = fHCLK. The MCU is placed under the following conditions: ● ● ● all I/O pins are in input mode with a static value at VDD or VSS (no load) all peripherals are disabled unless otherwise mentioned the given value is calculated by measuring the current consumption – – with all peripherals clocked off with only one peripheral clocked on ● ambient operating temperature and VDD supply voltage conditions summarized in Table 6 Peripheral current consumption(1) Peripheral TIM2 TIM3 USART2 Table 19.43 0. ADON bit in the ADC_CR2 register is set to 1.81 1. and under ambient temperature and supply voltage conditions summarized in Table 9.39 0. fHCLK = 72 MHz.47 0. 42/80 Doc ID 15060 Rev 3 .78 1. default prescaler value for each peripheral.47 1. fADCCLK = fAPB2/4. fAPB1 = fHCLK/2.65 0. fAPB1 = fHCLK/2. STM32F103x6 On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in Table 19. and under ambient temperature and supply voltage conditions summarized in Table 9.768 Max 1000 VDD V 0. Guaranteed by design. Symbol fLSE_ext VLSEH VLSEL tw(LSE) tw(LSE) tr(LSE) tf(LSE) Cin(LSE) Low-speed external user clock characteristics Parameter User External clock source frequency(1) OSC32_IN input pin high level voltage OSC32_IN input pin low level voltage OSC32_IN high or low time(1) OSC32_IN rise or fall time(1) 5 30 VSS  VIN  VDD 70 ±1 0.7VDD VSS 450 ns 50 pF % µA Conditions Min Typ 32. Doc ID 15060 Rev 3 43/80 . Table 21.7VDD VSS 16 ns 20 pF % µA Typ 8 Max 25 VDD 0. STM32F103x6 Table 20. Symbol fHSE_ext VHSEH VHSEL tw(HSE) tw(HSE) tr(HSE) tf(HSE) Cin(HSE) Electrical characteristics High-speed external user clock characteristics Parameter User external clock source frequency(1) OSC_IN input pin high level voltage OSC_IN input pin low level voltage OSC_IN high or low time(1) OSC_IN rise or fall time(1) OSC_IN input capacitance(1) 45 VSS  VIN  VDD 5 55 ±1 Conditions Min 1 0.STM32F103x4.3VDD Unit MHz V DuCy(HSE) Duty cycle IL OSC_IN Input leakage current 1. Low-speed external user clock generated from an external source The characteristics given in Table 21 result from tests performed using an low-speed external clock source.3VDD Unit kHz OSC32_IN input capacitance(1) DuCy(LSE) Duty cycle IL OSC32_IN Input leakage current 1. Guaranteed by design. not tested in production. not tested in production. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 22. STM32F103x6 Figure 18. In the application. 44/80 Doc ID 15060 Rev 3 . Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency. High-speed external clock source AC timing diagram VHSEH 90% VHSEL 10% tr(HSE) THSE tf(HSE) tW(HSE) tW(HSE) t EXTER NAL CLOCK SOURC E fHSE_ext OSC _IN IL STM32F103xx ai14143 Figure 19. the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. accuracy). Low-speed external clock source AC timing diagram VLSEH 90% VLSEL 10% tr(LSE) TLSE tf(LSE) tW(LSE) tW(LSE) t EXTER NAL CLOCK SOURC E fLSE_ext OSC32_IN IL STM32F103xx ai14144b High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic resonator oscillator. package.Electrical characteristics STM32F103x4. and selected to match the requirements of the crystal or resonator (see Figure 20). the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Resonator characteristics given by the crystal/ceramic resonator manufacturer. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency.3 V.com. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32. due to the induced leakage and the bias condition change. accuracy). 2. However. Doc ID 15060 Rev 3 45/80 . This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer For CL1 and CL2. CL1 and CL2 are usually the same size.). All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 23.768 kHz crystal/ceramic resonator oscillator. Refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st. not tested in production. Figure 20. In the application. 4. Symbol fOSC_IN RF C Electrical characteristics HSE 4-16 MHz oscillator characteristics(1) (2) Parameter Oscillator frequency Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) HSE driving current Oscillator transconductance RS = 30 VDD = 3. Typical application with an 8 MHz crystal Resonator with integrated capacitors CL1 OSC_IN 8 MH z resonator REXT(1) OSC_OU T RF Bias controlled gain STM32F103xx fHSE CL2 ai14145 1. REXT value depends on the crystal characteristics. it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ. STM32F103x6 Table 22. VIN = VSS with 30 pF load Startup VDD is stabilized 25 2 Conditions Min 4 Typ 8 200 30 Max 16 Unit MHz k pF i2 gm tSU(HSE (4) 1 mA mA/V ms startup time 1. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. Based on characterization. 3. it is recommended to take this point into account if the MCU is used in tough humidity conditions. designed for high-frequency applications. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2.STM32F103x4. package. 46/80 Doc ID 15060 Rev 3 . To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL  7 pF. Based on characterization. Symbol RF C(2) I2 gm tSU(LSE)(4) STM32F103x4.768 kHz crystal Caution: Resonator with integrated capacitors CL1 OSC32_IN 32. CL1 and CL2.7 Internal clock source characteristics The parameters given in Table 24 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. Refer to the note and caution paragraphs below the table.768 kHz) (1) Parameter Feedback resistor Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) LSE driving current Oscillator Transconductance startup time VDD is stabilized RS = 30 k VDD = 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32. 3.Electrical characteristics Table 23.4 Max Unit M pF µA µA/V s 1. STM32F103x6 LSE oscillator characteristics (fLSE = 32. Typically. are usually the same size. 2. and Cstray = 2 pF.3 V. it is between 2 pF and 7 pF. Refer to crystal manufacturer for more details 4. Never use a resonator with a load capacitance of 12.5 pF. not tested in production. and to the application note AN2867 “Oscillator design guide for ST microcontrollers.768 kHz oscillation is reached. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. VIN = VSS 5 3 Conditions Min Typ 5 15 1. then CL1 = CL2 = 8 pF. Typical application with a 32.768 kH z resonator CL2 RF OSC32_OU T Bias controlled gain STM32F103xx fLSE ai14146 5.3. Figure 21. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Note: For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator.768kHz. Example: if you choose a resonator with a load capacitance of CL = 6 pF. com.3 V. not tested in production. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. STM32F103x6 Electrical characteristics High-speed internal (HSI) RC oscillator Table 24. TA = –40 to 105 °C unless otherwise specified. Based on characterization.1 1 80 2. Wakeup time from low-power mode The wakeup times given in Table 26 is measured on a wakeup phase with a 8-MHz HSI RC oscillator.8 2 100 Max Unit MHz % % % % % µs µA ACCHSI Accuracy of the HSI oscillator Factorycalibrated(4) TA = –40 to 105 °C TA = –10 to 85 °C TA = 0 to 70 °C TA = 25 °C tsu(HSI)(4) IDD(HSI)(4) HSI oscillator startup time HSI oscillator power consumption 1. Guaranteed by design. 2.STM32F103x4. TA = –40 to 105 °C unless otherwise specified. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from the ST website www.3 –1. Low-speed internal (LSI) RC oscillator Table 25. Doc ID 15060 Rev 3 47/80 . Guaranteed by design. Symbol fHSI HSI oscillator characteristics(1) Parameter Frequency User-trimmed with the RCC_CR register(2) Conditions Min Typ 8 1(3) –2 –1. Based on characterization. not tested in production. 4. VDD = 3.5 –1. 3.5 2.2 2 1. The clock source used to wake up the device depends from the current operating mode: ● ● Stop or Standby mode: the clock source is the RC oscillator Sleep mode: the clock source is the clock that was set before entering Sleep mode.2 Unit kHz µs µA IDD(LSI)(3) 1. not tested in production. VDD = 3 V.65 Min 30 Typ 40 Max 60 85 1. Symbol fLSI(2) tsu(LSI) (3) LSI oscillator characteristics (1) Parameter Frequency LSI oscillator startup time LSI oscillator power consumption 0.st. 3. not tested in production. 2. Based on characterization. Symbol tprog tERASE tME Flash memory characteristics Parameter Conditions Min(1) 40 20 20 Typ 52. Table 28.5 Max(1) 70 40 40 Unit µs ms ms 16-bit programming time TA–40 to +105 °C Page (1 KB) erase time Mass erase time TA –40 to +105 °C TA –40 to +105 °C 48/80 Doc ID 15060 Rev 3 . Low-power mode wakeup timings Parameter Wakeup from Sleep mode STM32F103x4.3.0 Max(1) 25 60 72 200 300 Unit MHz % MHz µs ps fPLL_IN fPLL_OUT tLOCK Jitter PLL input clock duty cycle PLL multiplier output clock PLL lock time Cycle-to-cycle jitter 1.8 3.6 Unit µs Wakeup from Stop mode (regulator in run mode) Wakeup from Stop mode (regulator in low power mode) Wakeup from Standby mode µs 5.3.9 Memory characteristics Flash memory The characteristics are given at TA = –40 to 105 °C unless otherwise specified.8 PLL characteristics The parameters given in Table 27 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. 5. not tested in production.4 50 µs 1. STM32F103x6 Symbol tWUSLEEP(1) tWUSTOP(1) tWUSTDBY(1) Typ 1. 2. 5. Table 27.Electrical characteristics Table 26. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. Symbol PLL characteristics Value Parameter PLL input clock(2) Min(1) 1 40 16 Typ 8. The wakeup times are measured from the wakeup event to the point in which the user application code reads the first instruction. 6 V 5 50 2 3. 2. the device is stressed by two electromagnetic events until a failure occurs. until a functional disturbance occurs. Table 29. They are based on the EMS levels and classes defined in application note AN1709.10 EMC characteristics Susceptibility tests are performed on a sample basis during device characterization.3. Doc ID 15060 Rev 3 49/80 . VDD = 3.STM32F103x4. not tested in production. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor. 5. VDD = 3. This test is compliant with the IEC 61000-4-2 standard.0 to 3. The test results are given in Table 30. Cycling performed over the whole temperature range. VDD = 3.3 V Min(1) Typ Max(1) 20 Unit mA IDD Supply current Write / Erase modes fHCLK = 72 MHz.6 mA µA V Vprog Programming voltage 1. Symbol Flash memory endurance and data retention Value Parameter Conditions TA = –40 to +85 °C (6 suffix versions) TA = –40 to +105 °C (7 suffix versions) 1 kcycle(2) at TA = 85 °C kcycle(2) Min(1) 10 30 10 20 Years Unit Typ Max kcycles NEND Endurance tRET Data retention 1 at TA = 105 °C 10 kcycles(2) at TA = 55 °C 1. A device reset allows normal operations to be resumed. STM32F103x6 Table 28.3 V Power-down mode / Halt. Based on characterization. The failure is indicated by the LEDs: ● ● Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. Symbol Electrical characteristics Flash memory characteristics (continued) Parameter Conditions Read mode fHCLK = 72 MHz with 2 wait states. Guaranteed by design. not tested in production. This test is compliant with the IEC 61000-4-4 standard. Voltage limits to be applied on any I/O pin to fHCLK 72 MHz induce a functional disturbance conforms to IEC 61000-4-2 Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD3. [fHSE/fHCLK] Unit 8/48 MHz 8/72 MHz 12 22 23 4 12 19 29 4 dBµV SEMI Peak level VDD 3. Symbol STM32F103x4. STM32F103x6 EMS characteristics Parameter Conditions Level/ Class 2B VFESD VDD 3. Software recommendations The software flowchart must include the management of runaway conditions such as: ● ● ● Corrupted program counter Unexpected reset Critical Data corruption (control registers. To complete these trials. ESD stress can be applied directly on the device.3 V.3 V. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.Electrical characteristics Table 30. TA 25 °C 30 to 130 MHz 130 MHz to 1GHz SAE EMI Level 50/80 Doc ID 15060 Rev 3 . over the range of specification values. This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Table 31. Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports).) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.1 to 30 MHz Max vs. TA +25 °C. TA +25 °C. When unexpected behavior is detected. fHCLK 72 MHz conforms to IEC 61000-4-4 VEFTB 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. Symbol EMI characteristics Parameter Conditions Monitored frequency band 0..3 V.. Table 33. Table 32. LU) using specific measurement methods. Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: ● ● A supply overvoltage is applied to each power supply pin A current injection is applied to each input.STM32F103x4. Based on characterization results. the device is stressed in order to determine its performance in terms of electrical sensitivity. Symbol LU Electrical sensitivities Parameter Static latch-up class Conditions TA +105 °C conforming to JESD78A Class II level A Doc ID 15060 Rev 3 51/80 . output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard.3. not tested in production. STM32F103x6 Electrical characteristics 5.11 Absolute maximum ratings (electrical sensitivity) Based on three different tests (ESD. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. This test conforms to the JESD22-A114/C101 standard. Symbol VESD(HBM) ESD absolute maximum ratings Ratings Electrostatic discharge voltage (human body model) Conditions TA +25 °C conforming to JESD22-A114 TA +25 °C conforming to JESD22-C101 Class 2 Maximum value(1) 2000 V II 500 Unit Electrostatic discharge VESD(CDM) voltage (charge device model) 1. Electrical characteristics STM32F103x4, STM32F103x6 5.3.12 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 34 are derived from tests performed under the conditions summarized in Table 9. All I/Os are CMOS and TTL compliant. Table 34. Symbol VIL VIH VIL VIH I/O static characteristics Parameter Input low level voltage Standard IO input high level voltage IO FT(1) input high level voltage Input low level voltage CMOS ports Input high level voltage Standard IO Schmitt trigger voltage hysteresis(2) 0.65 VDD 200 5% VDD(3) VSS  VIN  VDD Standard I/Os VIN= 5 V I/O FT Weak pull-up equivalent resistor(5) Weak pull-down equivalent resistor(5) I/O pin capacitance VIN VSS VIN VDD 30 30 40 40 5 1 µA 3 50 50 k k pF TTL ports Conditions Min –0.5 2 2 –0.5 Typ Max 0.8 V VDD+0.5 5.5V 0.35 VDD VDD+0.5 mV mV V Unit Vhys IO FT Schmitt trigger voltage hysteresis(2) Ilkg Input leakage current (4) RPU RPD CIO 1. FT = Five-volt tolerant. 2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production. 3. With a minimum of 100 mV. 4. Leakage could be higher than max. if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This MOS/NMOS contribution to the series resistance is minimum (~10% order). All I/Os are CMOS and TTL compliant (no software configuration required), their characteristics consider the most strict CMOS-technology or TTL parameters: ● For VIH: – – if VDD is in the [2.00 V - 3.08 V] range: CMOS characteristics but TTL included if VDD is in the [3.08 V - 3.60 V] range: TTL characteristics but CMOS included if VDD is in the [2.00 V - 2.28 V] range: TTL characteristics but CMOS included if VDD is in the [2.28 V - 3.60 V] range: CMOS characteristics but TTL included ● For VIL: – – 52/80 Doc ID 15060 Rev 3 STM32F103x4, STM32F103x6 Electrical characteristics Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink +20 mA (with a relaxed VOL). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2: ● The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 7). The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 7). ● Output voltage levels Unless otherwise specified, the parameters given in Table 35 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 9. All I/Os are CMOS and TTL compliant. Table 35. Symbol VOL(1) VOH (2) Output voltage characteristics Parameter Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time Output low level voltage for an I/O pin when 8 pins are sunk at same time Output high level voltage for an I/O pin when 8 pins are sourced at same time Conditions TTL port IIO = +8 mA 2.7 V < VDD < 3.6 V CMOS port IIO =+ 8mA 2.7 V < VDD < 3.6 V Min Max 0.4 V VDD–0.4 0.4 V 2.4 1.3 V VDD–1.3 0.4 V VDD–0.4 Unit VOL (1) VOH (2) VOL(1)(3) VOH(2)(3) VOL(1)(3) VOH(2)(3) IIO = +20 mA 2.7 V < VDD < 3.6 V IIO = +6 mA 2 V < VDD < 2.7 V 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 7 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 3. Based on characterization data, not tested in production. Doc ID 15060 Rev 3 53/80 Electrical characteristics STM32F103x4, STM32F103x6 Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 22 and Table 36, respectively. Unless otherwise specified, the parameters given in Table 36 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 36. I/O AC characteristics(1) Parameter Conditions Min Max 2 125(3) CL = 50 pF, VDD = 2 V to 3.6 V 125 (3) MODEx[1:0] Symbol bit value(1) Unit MHz fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 10 tf(IO)out tr(IO)out Output high to low level fall time Output low to high level rise time ns fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2 V to 3.6 V 01 tf(IO)out tr(IO)out Output high to low level fall time Output low to high level rise time CL = 50 pF, VDD = 2 V to 3.6 V 10 25(3) MHz ns 25(3) CL = 30 pF, VDD = 2.7 V to 3.6 V Fmax(IO)out Maximum frequency(2) CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V CL = 30 pF, VDD = 2.7 V to 3.6 V 11 tf(IO)out Output high to low level fall time CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V CL = 30 pF, VDD = 2.7 V to 3.6 V tr(IO)out Output low to high level rise time Pulse width of external signals detected by the EXTI controller CL = 50 pF, VDD = 2.7 V to 3.6 V CL = 50 pF, VDD = 2 V to 2.7 V 50 30 20 5(3) 8(3) 12(3) 5(3) 8(3) 12(3) MHz MHz MHz ns - tEXTIpw 10 ns 1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure 22. 3. Guaranteed by design, not tested in production. 54/80 Doc ID 15060 Rev 3 STM32F103x4, STM32F103x6 Figure 22. I/O AC characteristics definition Electrical characteristics 90% 50% 10% EXT ERNAL OUTPUT ON 50pF tr(I O)out 10% 50% 90% tr(I O)out T Maximum frequency is achieved if (tr + tf) 2/3)T and if the duty cycle is (45-55%) when loaded by 50pF ai14131 5.3.13 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 34). Unless otherwise specified, the parameters given in Table 37 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 9. Table 37. Symbol VIL(NRST)(1) NRST pin characteristics Parameter NRST Input low level voltage Conditions Min –0.5 2 200 VIN VSS 30 40 50 100 300 Typ Max 0.8 V VDD+0.5 mV k ns ns Unit VIH(NRST)(1) NRST Input high level voltage Vhys(NRST) RPU VF(NRST) (1) NRST Schmitt trigger voltage hysteresis Weak pull-up equivalent resistor(2) NRST Input filtered pulse NRST Input not filtered pulse VNF(NRST)(1) 1. Guaranteed by design, not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). Doc ID 15060 Rev 3 55/80 3.1 µF STM32F10xxx ai14132c 2. external clock. STM32F103x6 External reset circuit(1) NRST(2) VDD RPU Filter Internal Reset 0. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 37.3. TIMx is used as a general term to refer to the TIM1. The reset network protects the device against parasitic resets.9 0 0 fTIMxCLK/2 36 16 65536 910 65536 × 65536 Conditions Min 1 Max Unit tTIMxCLK ns MHz MHz bit tTIMxCLK µs tTIMxCLK s fEXT ResTIM tCOUNTER tMAX_COUNT Maximum possible count fTIMxCLK = 72 MHz 59. Symbol tres(TIM) TIMx(1) characteristics Parameter Timer resolution time fTIMxCLK = 72 MHz Timer external clock frequency on CH1 to CH4 f TIMxCLK = 72 MHz Timer resolution 16-bit counter clock period 1 when internal clock is fTIMxCLK = 72 MHz 0.12: I/O port characteristics for details on the input/output alternate function characteristics (output compare. TIM3 and TIM4 timers. 56/80 Doc ID 15060 Rev 3 . Recommended NRST pin protection STM32F103x4. 3.6 1. Otherwise the reset will not be taken into account by the device.0139 selected 13. PWM output). Refer to Section 5. input capture. Table 38.14 TIM timer characteristics The parameters given in Table 38 are guaranteed by design.Electrical characteristics Figure 23. TIM2. 5. 3. not tested in production. Table 39.7 400 4.15 Communications interfaces I2C interface characteristics Unless otherwise specified. STM32F103x6 Electrical characteristics 5. Guaranteed by design.1Cb 900(3) 300 300 ns Max Fast mode I2C(1)(2) Unit 1.0 4. the parameters given in Table 39 are derived from tests performed under the ambient temperature.12: I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL).6 0. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. Doc ID 15060 Rev 3 57/80 .3 400 s s pF Max Min 1.6 1. the PMOS connected between the I/O pin and VDD is disabled.6 100 0(4) 20 + 0.0 250 0(3) 1000 300 0. fPCLK1 frequency and VDD supply voltage conditions summarized in Table 9.7 4. 3.0 4. The I2C characteristics are described in Table 39. Refer also to Section 5. 2.6 µs 0. fPCLK1 must be higher than 2 MHz to achieve the maximum standard mode I2C frequency. but is still present.7 4. Symbol tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) tsu(STO) tw(STO:STA) Cb I2C characteristics Standard mode I2C(1) Parameter Min SCL clock low time SCL clock high time SDA setup time SDA data hold time SDA and SCL rise time SDA and SCL fall time Start condition hold time Repeated Start condition setup time Stop condition setup time Stop to Start condition time (bus free) Capacitive load for each bus line 4. It must be higher than 4 MHz to achieve the maximum fast mode I2C frequency. 4.STM32F103x4. When configured as open-drain. The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.3 µs 0. The STM32F103xx performance line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-drain.3. 7 kΩ I2C bus VDD 4 . STM32F103x6 Figure 24.7 kΩ STM32F103xx SDA 100Ω SCL 100Ω S TART REPEATED S TART tsu(STA) SDA tf(SDA) th(STA) SCL tw(SCKH) S TART tr(SDA) tw(SCKL) tsu(SDA) th(SDA) S TOP tsu(STA:STO) tr(SCK) tf(SCK) tsu(STO) ai14149b 1.Electrical characteristics STM32F103x4. For other speed ranges. I2C bus AC waveforms and measurement circuit VDD 4 . fSCL = I2C speed. SCL frequency (fPCLK1= 36 MHz.7 k 400 300 200 100 50 20 0x801E 0x8028 0x803C 0x00B4 0x0168 0x0384 1.VDD = 3. 58/80 Doc ID 15060 Rev 3 .3VDD and 0. RP = External pull-up resistance. For speeds around 200 kHz. These variations depend on the accuracy of the external components used to design the application.7VDD. 2. the tolerance on the achieved speed is of 5%. Table 40.. the tolerance on the achieved speed 2%. Measurement points are done at CMOS levels: 0.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4. SCK high and low time tw(SCKL)(2) presc = 4 tsu(MI) (2) tsu(SI)(2) th(MI) (2) Master mode Data input setup time Slave mode Master mode Data input hold time Slave mode Data output access time Data output disable time Slave mode. fPCLK = 20 MHz Slave mode Slave mode (after enable edge) Master mode (after enable edge) Slave mode (after enable edge) Data output hold time Master mode (after enable edge) th(SI)(2) ta(SO)(2)(3) tdis(SO)(2)(4) tv(SO) (2)(1) Data output valid time tv(MO) (2)(1) Data output valid time th(SO)(2) th(MO) (2) 1. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. Table 41. the parameters given in Table 41 are derived from tests performed under the ambient temperature. fPCLKx frequency and VDD supply voltage conditions summarized in Table 9. not tested in production. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z Doc ID 15060 Rev 3 59/80 . MOSI.12: I/O port characteristics for more details on the input/output alternate function characteristics (NSS. MISO). Remapped SPI1 characteristics to be determined. 2. 3. Based on characterization. Refer to Section 5. 4. fPCLK = 36 MHz. Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) DuCy(SCK) SPI characteristics(1) Parameter SPI clock frequency Slave mode SPI clock rise and fall time SPI slave input clock duty cycle Capacitive load: C = 30 pF Slave mode Slave mode Slave mode 30 4tPCLK 2tPCLK 50 5 5 5 4 0 2 3tPCLK 10 25 5 15 2 ns 60 18 8 70 ns % Conditions Master mode Min Max 18 MHz Unit tsu(NSS)(2) NSS setup time th(NSS) (2) NSS hold time tw(SCKH)(2) Master mode.3. SCK. STM32F103x6 Electrical characteristics SPI interface characteristics Unless otherwise specified.STM32F103x4. 7VDD. SPI timing diagram . STM32F103x6 NSS input tc(SCK) tSU(NSS) SCK Input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 ta(SO) MISO OUT P UT tsu(SI) MOSI I NPUT M SB IN th(SI) ai14134c th(NSS) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) LSB OUT tv(SO) MS B O UT th(SO) BI T6 OUT tdis(SO) B I T1 IN LSB IN Figure 26. SPI timing diagram .3VDD and 0.Electrical characteristics Figure 25.slave mode and CPHA = 1(1) NSS input tSU(NSS) SCK Input tc(SCK) th(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) ta(SO) MISO OUT P UT tsu(SI) MOSI I NPUT M SB IN tv(SO) MS B O UT th(SI) th(SO) BI T6 OUT tdis(SO) LSB OUT B I T1 IN LSB IN ai14135 1.slave mode and CPHA = 0 STM32F103x4. Measurement points are done at CMOS levels: 0. 60/80 Doc ID 15060 Rev 3 . USB characteristics The USB interface is USB-IF certified (Full Speed). SPI timing diagram . USB startup time Parameter USB transceiver startup time Max 1 Unit µs Symbol tSTARTUP(1) 1. STM32F103x6 Figure 27. Table 42. Measurement points are done at CMOS levels: 0.master mode(1) High NSS input tc(SCK) SCK Input Electrical characteristics CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 SCK Input CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INP UT MOSI OUTUT tw(SCKH) tw(SCKL) MS BIN th(MI) M SB OUT tv(MO) B I T1 OUT th(MO) ai14136 tr(SCK) tf(SCK) BI T6 IN LSB IN LSB OUT 1. Doc ID 15060 Rev 3 61/80 .3VDD and 0. Guaranteed by design.STM32F103x4.7VDD. not tested in production. 5 k resistor to a 3. Symbol USB: Full-speed electrical characteristics(1) Parameter Conditions Min Max Unit Driver characteristics tr tf trfm VCRS Rise time(2) Fall time(2) CL = 50 pF CL = 50 pF tr/tf 4 4 90 1.16 CAN (controller area network) interface Refer to Section 5. Guaranteed by design. not tested in production. 2. 2.0).0 V Output levels VOL VOH Static output level low Static output level high RL of 1.0(3) I(USBDP.3. To be compliant with the USB 2. The STM32F103xx USB functionality is ensured down to 2.5 2. 4. 5.6 V voltage range.0 ns ns % V Rise/ fall time matching Output signal crossover voltage 1. USB timings: definition of data signal rise and fall time Crossover points Differen tial data lines V CRS VS S tf tr ai14137 Table 44.12: I/O port characteristics for more details on the input/output alternate function characteristics (CAN_TX and CAN_RX).0 V VDD voltage range. Guaranteed by design.3 20 20 110 2.8 0. not tested in production.3 3. For more detailed informations.6 V 2. RL is the load connected on the USB drivers Figure 28.7 V but not the full USB electrical characteristics which are degraded in the 2. STM32F103x6 USB DC electrical characteristics Parameter Conditions Min.(1) Max.0-to-3. please refer to USB Specification . Symbol Input levels VDD VDI(4) VCM(4) VSE(4) USB operating voltage(2) Differential input sensitivity Differential common mode range Single ended receiver threshold STM32F103x4. 5.Chapter 7 (version 2.(1) Unit 3. Measured from 10% to 90% of the data signal. 3.3 V 3. USBDM) Includes VDI range 0. All the voltages are measured from the local ground potential.0 full-speed electrical specification.7-to-3. the USBDP (D+) pin should be pulled up with a 1.6 1.Electrical characteristics Table 43.2 0.6 V(5) RL of 15 k to VSS(5) 2.3. 62/80 Doc ID 15060 Rev 3 .5 k to 3.8 1. 4. STM32F103x6 Electrical characteristics 5. the parameters given in Table 45 are derived from tests performed under the ambient temperature. not tested in production. In devices delivered in VFQFPN and LQFP packages. Symbol VDDA VREF+(3) IVREF (3) It is recommended to perform a calibration after each power-up. Based on characterization.pin (VREF.STM32F103x4.17 12-bit ADC characteristics Unless otherwise specified.143 2 (4) fADC = 14 MHz 0.4 160 (1) Typ Max 3. ADC characteristics Parameter Power supply Positive reference voltage Current on the VREF input pin ADC clock frequency Sampling rate External trigger frequency fADC = 14 MHz 0. 3. see Table 5 and Figure 4.is internally connected to VSSA.214 3(4) µs 1/fADC µs 1/fADC µs 1/fADC µs µs 1/fADC fADC = 14 MHz 0. 2.4 2. not tested in production. Note: Table 45. Doc ID 15060 Rev 3 63/80 .9 83 fADC = 14 MHz 0. fPCLK2 frequency and VDDA supply voltage conditions summarized in Table 9. Devices that come in the TFBGA64 package have a VREF+ pin but no VREF.05 Conditions Min 2.107 1. Guaranteed by design. a delay of 1/fPCLK2 must be added to the latency specified in Table 45.3.is internally connected to VSSA).1 239.6 0. For external triggers.5 0 1 0 17.5 1 18 14 to 252 (tS for sampling +12. VREF+ is internally connected to VDDA and VREF.6 VDDA 220 (1) Unit V V µA MHz MHz kHz 1/fADC V k k pF µs 1/fADC fADC fS(2) fTRIG(2) VAIN(3) RAIN(2) RADC(2) CADC(2) tCAL(2) tlat(2) tlatr(2) tS(2) tSTAB(2) tCONV(2) 14 1 823 17 Conversion voltage range External input impedance Sampling switch resistance Internal sample and hold capacitor Calibration time Injection trigger conversion latency Regular trigger conversion latency Sampling time Power-up time Total conversion time (including sampling time) fADC = 14 MHz fADC = 14 MHz See Equation 1 and Table 46 for details 0 (VSSA tied to ground) VREF+ 50 1 8 5.5 for successive approximation) 1. 5 55.5 7.96 2.6 V TA = 25 °C Measurements made after ADC calibration Typ ±1.5 LSB Unit 1.1 0. Here N = 12 (from 12-bit resolution). RAIN < 10 k.3.9 11.54 0.5 1. RAIN max for fADC = 14 MHz(1) Ts (cycles) tS (µs) 0. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. not tested in production.8 Max(3) ±2 ±1. Based on characterization.2 50 NA NA RAIN max (k) 1. Table 46. 2.96 5.5 ±0.5 71.2 37.4 25. VDDA = 3 V to 3. Symbol ET EO EG ED EL ADC accuracy .5 ±1.Electrical characteristics Equation 1: RAIN max formula: TS R AIN  ------------------------------------------------------------.limited test conditions(1) (2) Parameter Total unadjusted error Offset error Gain error Differential linearity error Integral linearity error Test conditions fPCLK2 = 56 MHz.– R ADC N+2 f ADC  C ADC  ln  2  STM32F103x4. ADC Accuracy vs.3 ±1 ±0.7 ±0.04 2. Table 47. 64/80 Doc ID 15060 Rev 3 .96 3. 3.11 17.5 ±1 ±1.5 239. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.12 does not affect the ADC accuracy.11 0.4 5.5 28.5 13. ADC DC accuracy values are measured after internal calibration. Based on characterization. STM32F103x6 The formula above (Equation 1) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. fADC = 14 MHz. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. not tested in production.5 41. 5 Max(4) ±5 ±2. VDDA = 2. Figure 29. not tested in production.6 V Measurements made after ADC calibration Test conditions Typ ±2 ±1. ADC accuracy characteristics V V [1LSBIDEAL = REF+ (or DDA depending on package)] 4096 4096 EG 4095 4094 4093 (2) ET 7 6 5 4 3 2 1 0 1 VSSA 2 3 4 1 LSBIDEAL EO EL ED (3) (1) ET=Total Unadjusted Error: maximum deviation between the actual and the ideal transfer curves. Better performance could be achieved in restricted VDD. EL=Integral Linearity Error: maximum deviation between any actual transition and the end point correlation line. fADC = 14 MHz. (1) Example of an actual transfer curve (2) The ideal transfer curve (3) End point correlation line 5 6 7 4093 4094 4095 4096 VDDA ai14395b Doc ID 15060 Rev 3 65/80 . Based on characterization. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.5 ±1 ±1. ED=Differential Linearity Error: maximum deviation between actual steps and the ideal one. 2. ADC Accuracy vs.12 does not affect the ADC accuracy. STM32F103x6 Table 48.4 V to 3. EG=Gain Error: deviation between the last ideal transition and the last actual one. RAIN < 10 k.5 ±3 ±2 ±3 LSB Unit 1. Symbol ET EO EG ED EL Electrical characteristics ADC accuracy(1) (2) (3) Parameter Total unadjusted error Offset error Gain error Differential linearity error Integral linearity error fPCLK2 = 56 MHz. ADC DC accuracy values are measured after internal calibration.3. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current. EO=Offset Error: deviation between the first actual transition and the first ideal one.STM32F103x4.5 ±1. 4. Negative Injection Current: Injecting negative current on any of the standard (nonrobust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. 3. frequency and temperature ranges. Typical connection diagram using the ADC VDD VT 0. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). Power supply and reference decoupling (VREF+ not connected to VDDA) 1. Figure 31.6 V AINx Cparasitic VT 0. The VREF+ input is available only on the TFBGA64 package. The 10 nF capacitors should be ceramic (good quality). depending on whether VREF+ is connected to VDDA or not. A high Cparasitic value will downgrade conversion accuracy. 2. 66/80 Doc ID 15060 Rev 3 . General PCB design guidelines Power supply decoupling should be performed as shown inFigure 31 or Figure 32. Refer to Table 45 for the values of RAIN. fADC should be reduced. STM32F103x6 RAIN(1) STM32F103xx Sample and hold ADC converter RADC(1) 12-bit converter CADC(1) VAIN ai14150c 1. They should be placed them as close as possible to the chip.6 V IL±1 µA STM32F103x4. RADC and CADC.Electrical characteristics Figure 30. To remedy this. 18 Temperature sensor characteristics Table 49.43 2 4. 5. Doc ID 15060 Rev 3 67/80 . STM32F103x6 Electrical characteristics Figure 32. 3. 2.52 10 17.STM32F103x4. not tested in production. Power supply and reference decoupling(VREF+ connected to VDDA) 1.3 1.3. Symbol TL(1) Avg_Slope(1) V25(1) tSTART(2) TS_temp(3)(2) TS characteristics Parameter VSENSE linearity with temperature Average slope Voltage at 25 °C Startup time ADC sampling time when reading the temperature 4.1 1.0 1. not tested in production. Guaranteed by design.34 4 Min Typ Max Unit °C mV/°C V µs µs 1 4. Shortest sampling time can be determined in the application by multiple iterations. The VREF+ input is available only on the TFBGA64 package.6 1. Based on characterization. ECOPACK® specifications.com. ST offers these devices in different grades of ECOPACK® packages. depending on their level of environmental compliance. ECOPACK® is an ST trademark. STM32F103x6 6 6.1 Package characteristics Package mechanical data In order to meet environmental requirements.Package characteristics STM32F103x4. 68/80 Doc ID 15060 Rev 3 .st. grade definitions and product status are available at: www. 30 ai14870b Pin # 1 ID R = 0. Table 50.550 0.80 e D D2 36 10 0.875 1.650 0.000 3.0031 0.750 0.20 1.0197 0. It should be soldered to the PCB.450 0.750 5. VFQFPN36 6 x 6 mm. It is recommended to connect it to VSS.0177 0.875 1. 0.2313 0.900 0.0138 Max 1.0020 0.0256 0.5 mm pitch.0394 0.10 0. package mechanical data millimeters Min Typ 0.700 6. Values in inches are converted from mm and rounded to 4 decimal digits.30 10 1 E 9 L ZR_ME 6.700 0.30 4.750 0. Doc ID 15060 Rev 3 69/80 .0008 0. 3.50 28 18 4.125 4.0217 0.250 6.0071 0.250 0. 2.0217 0.300 6.000 0.30 1.0295 Max 0.75 1 9 36 0.2313 0.050 1.180 5.1457 0.STM32F103x4.0689 0. package outline(1) Seating plane C A2 A ddd C Figure 34. There is an exposed die pad on the underside of the VFQFPN package.800 1. Recommended footprint (dimensions in mm)(1)(2)(3) 4.500 0.1457 0.80 4.2362 0.350 0. All leads should also be soldered to the PCB.2411 0. Symbol VFQFPN36 6 x 6 mm.5 mm pitch.10 4.020 0.000 Min 0.0118 0.1673 0.0394 A A1 A2 A3 b D D2 E E2 e L ddd 0.2411 0.230 6.080 0.2362 0.0689 0.125 4.0315 inches(1) Typ 0.0091 0. 0. STM32F103x6 Package characteristics Figure 33.1673 0.00 27 19 A3 E2 b 27 19 A1 28 18 4.250 0. Drawing is not to scale.550 0. The back-side pad is not internally connected to the VSS or VDD power pads.0354 0.000 3.0098 0. STM32F103x6 Figure 35.00 10.05 1.00 Number of pins 7° 0.2 1 7.0106 0.0059 0. Dimensions are in millimeters.75 0° 0.27 0.15 1.5° 0.5° 0.0295 0. 64-pin low-profile quad flat package mechanical data millimeters Min Typ Max 1.5 32 E E1 b 12.00 10.60 1.20 0.17 0.0020 0.0394 7° 0.0177 1. 10 x 10 mm.0531 0.0197 3. Table 51.3937 0. Values in inches are converted from mm and rounded to 4 decimal digits.Package characteristics STM32F103x4. 10 x 10 mm.00 0.0035 0.00 12.0630 0.09 12.8 16 D1 D L1 c 12.45 3.3937 0.0236 0.3 e 10.7 ai14909 L ai14398b 1.3 A1 49 0.0551 0. 2.7 10. Drawing is not to scale.0079 A A1 A2 b c D D1 E E1 e  L L1 N 64 1.0571 0.35 0.40 0.4724 0.50 0° 0.3 64 17 1.4724 0. 70/80 Doc ID 15060 Rev 3 . LQFP64. 64-pin low-profile quad flat package outline(1) A A2 Figure 36.22 0.0067 0. Recommended footprint(1)(2) 48 33 0.60 0.45 0.0087 Min inches(1) Typ Max 0. Symbol LQFP64. 750 0.150 0. 5 x 5 mm. STM32F103x6 Package characteristics Figure 37.200 0.350 5.0295 0.150 0.2028 Min Typ Max 0.500 4.150 0.8 x 8 active ball array.5 mm pitch.080 0.1969 0.0197 0. 0.050 5. Doc ID 15060 Rev 3 71/80 .2028 0.0472 Symbol Min A A1 A2 A3 A4 b D D1 E E1 e F ddd eee fff Typ 1.1378 0.0118 0.0098 0.1909 0.1378 0. TFBGA64 .5 mm pitch.000 3.0236 0. Drawing is not to scale.0309 0.STM32F103x4.250 4.300 5.0079 0.0059 0.850 5.200 0.850 0. package outline B A A1 e D D1 A F H G F E E1 D C B A e 1 A3 A4 A2 Seating C plane Bottom view ME_R8 F E 2 3 4 5 6 7 8 A1 ball pad corner Øb (64 balls) 1.000 3.785 0. Values in inches are converted from mm and rounded to 4 decimal digits. TFBGA64 .500 0.8 x 8 active ball array. 5 x 5 mm.500 0.0138 0.600 0.0059 0. 0.0031 0.150 0.1969 0. package mechanical data millimeters inches(1) Max 1.0020 0. Table 52.1909 0. STM32F103x6 Figure 38.Package characteristics STM32F103x4.35 mm typ (depends on the soldermask registration tolerance) 0.27 mm aperture diameter Solder paste Dpad Dsm ai15495 1.5 mm 0.5 mm pitch BGA) Pitch D pad Dsm 0. 4 to 6 mils solder paste screen printing process 72/80 Doc ID 15060 Rev 3 .27 mm 0. Recommended PCB design rules for pads (0. Non solder mask defined (NSMD) pads are recommended 2. 200 7. 48-pin low-profile quad flat package outline(1) Seating plane C Figure 40. STM32F103x6 Package characteristics Figure 39.0236 0.0035 0.5° 0. 7 x 7 mm.0531 0.0059 0.200 0. 7 x 7 mm.400 0.2165 0.0551 0.0020 0. 2.80 E3 E1 E 9. Drawing is not to scale.800 6.50 1.000 7.000 5.000 7.2835 0.090 8.800 9.750 0.000 0° 3.2756 0.STM32F103x4.3543 0.450 0. 48-pin low-profile quad flat package mechanical data millimeters Min Typ Max 1.220 0.80 7.200 9. Symbol LQFP48.450 0.70 ai14911b 48 Pin 1 identification 1 12 13 5B_ME 1.0295 0.3543 0.000 5. Doc ID 15060 Rev 3 73/80 .0087 Min inches(1) Typ Max 0. Table 53.70 5.20 25 24 0.2835 A A1 A2 b c D D1 D3 E E1 E3 e L L1 k ccc 1.500 0.3465 0.600 1.0177 9.0079 0.800 9.500 8.3465 0.0031 7° 0.270 0.0106 0.150 1.3622 0.2756 0.30 A1 L 9.2165 0.500 0.2677 1.050 1. Dimensions are in millimeters. Values in inches are converted from mm and rounded to 4 decimal digits.0197 0.350 0.20 37 24 48 1 13 12 1.600 0.800 6. Recommended footprint(1)(2) A A2 A1 ccc b C D D1 k D3 36 25 L1 7.20 5.200 0. LQFP48.25 mm Gage plane 36 0.0394 3.0630 0.0571 0.0067 0.30 0.200 7.170 0.3622 0.5° 0.2677 0.30 37 c 0.080 7° 0° 0. 5 mm pitch Thermal resistance junction-ambient LQFP48 . Available from www.1 Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions .jedec.5 × 5 mm / 0. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. may be calculated using the following equation: TJ max = TA max + (PD max × JA) Where: ● ● ● ● TA max is the maximum ambient temperature in C.5 mm pitch Value 65 45 °C/W 55 18 Unit JA 6. JA is the package junction-to-ambient thermal resistance.2.Natural Convection (Still Air). PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax).Package characteristics STM32F103x4. 74/80 Doc ID 15060 Rev 3 .6 × 6 mm / 0. STM32F103x6 6. in C/W.2 Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 9: General operating conditions on page 30.5 mm pitch Thermal resistance junction-ambient VFQFPN 36 . Symbol Package thermal characteristics Parameter Thermal resistance junction-ambient TFBGA64 . PI/O max = (VOL × IOL) + ((VDD – VOH) × IOH). Table 54.org.5 mm pitch Thermal resistance junction-ambient LQFP64 . PINT max is the product of IDD and VDD. The maximum chip-junction temperature.7 × 7 mm / 0.10 × 10 mm / 0. expressed in Watts. TJ max. in degrees Celsius. it is possible to address applications that run at high ambient temperatures with a low dissipation.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW: PDmax = 175 + 272 = 447 mW Thus: PDmax = 447 mW Using the values obtained in Table 54 TJmax is calculated as follows: – For LQFP64. VOL= 0.4 V PINTmax = 20 mA × 3. IDDmax = 50 mA. parts must be ordered at least with the temperature range suffix 6 (see Table 55: Ordering information scheme). STM32F103x6 Package characteristics 6. maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA. 45 °C/W TJmax = 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.5 V= 175 mW PIOmax = 20 × 8 mA × 0. The following examples show how to calculate the temperature range needed for a given application.5 V= 70 mW PIOmax = 20 × 8 mA × 0.2 Selecting the product temperature range When ordering the microcontroller. the temperature range is specified in the ordering information scheme shown in Table 55: Ordering information scheme. In this case. it is useful to calculate the exact power consumption and junction temperature to determine which temperature range will be best suited to the application.4 V = 64 mW This gives: PINTmax = 70 mW and PIOmax = 64 mW: PDmax = 70 + 64 = 134 mW Thus: PDmax = 134 mW Doc ID 15060 Rev 3 75/80 . Each temperature range suffix corresponds to a specific guaranteed ambient temperature at maximum dissipation and. Assuming the following application conditions: Maximum ambient temperature TAmax = 115 °C (measured according to JESD51-2). Example 1: High-performance application Assuming the following application conditions: Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2). As applications do not commonly use the STM32F103xx at maximum dissipation. IDDmax = 20 mA.4 V and maximum 8 I/Os used at the same time in output at low level with IOL = 20 mA.115 °C This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C).2.5 V.STM32F103x4. to a specific maximum junction temperature.3 V PINTmax = 50 mA × 3. as long as junction temperature TJ remains within the specified range.5 V. VDD = 3.115 °C = 102. VOL= 0.4 V + 8 × 20 mA × 1. VOL= 1. Example 2: High-temperature application Using the same rules. maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA. VDD = 3. TA 700 600 PD (mW) 500 400 300 200 100 0 65 75 85 95 105 115 125 135 Suffix 6 Suffix 7 TA (°C) 76/80 Doc ID 15060 Rev 3 .03 °C This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C). STM32F103x6 Using the values obtained in Table 54 TJmax is calculated as follows: – For LQFP64.03 °C = 121. parts must be ordered at least with the temperature range suffix 7 (see Table 55: Ordering information scheme). In this case. 45 °C/W TJmax = 115 °C + (45 °C/W × 134 mW) = 115 °C + 6.Package characteristics STM32F103x4. LQFP64 PD max vs. Figure 41. Example: Device family STM32 = ARM-based 32-bit microcontroller Product type F = general-purpose Device subfamily 103 = performance line Pin count T = 36 pins C = 48 pins R = 64 pins Flash memory size 4 = 16 Kbytes of Flash memory 6 = 32 Kbytes of Flash memory Package H = BGA T = LQFP U = VFQFPN Temperature range 6 = Industrial temperature range. –40 to 105 °C. etc. Internal code “A” or blank(1) Options xxx = programmed parts TR = tape and real 1. please contact your nearest ST sales office. Ordering information scheme STM32 F 103 C 4 T 7 A xxx For a list of available options (speed.com.STM32F103x4.) or for further information on any aspect of this device.st. package. please refer to the STM32F103x8/B datasheet available from the ST website: www. STM32F103x6 Ordering information scheme 7 Ordering information scheme Table 55. –40 to 85 °C. 7 = Industrial temperature range. For STM32F103x6 devices with a blank Internal code. Doc ID 15060 Rev 3 77/80 . References to VREF. PB15. “96-bit unique ID” feature added and I/O information clarified on page 1. code running from Flash or RAM. PB13. Figure 16 shows a typical curve (title modified). TFBGA64 package added (see Table 52 and Table 37). Figure 7: Memory map modified. Note modified in Table 13: Maximum current consumption in Run mode. Timers specified on page 1 (Motor control capability mentioned). Date 22-Sep-2008 Document revision history Revision 1 Initial release. STM32F103x6 8 Revision history Table 56. – Figure 10: Power supply scheme modified – Figure 29: ADC accuracy characteristics modified – Note modified in Table 48: ADC accuracy. Table 20: High-speed external user clock characteristics and Table 21: Low-speed external user clock characteristics modified. ACCHSI max values modified in Table 24: HSI oscillator characteristics. code with data processing running from Flash and Table 15: Maximum current consumption in Sleep mode. plus small additional changes in Table 5: Low-density STM32F103xx pin definitions. PB14. Changes 30-Mar-2009 2 78/80 Doc ID 15060 Rev 3 . Small text changes.removed: – Figure 1: STM32F103xx performance line block diagram modified.Revision history STM32F103x4. PB3/TRACESWO moved from Default column to Remap column. Table 4: Timer feature comparison added. PB4. RAIN max values modified in Table 46: RAIN max for fADC = 14 MHz. fHSE_ext min modified in Table 20: High-speed external user clock characteristics. CADC and RAIN parameters modified in Table 45: ADC characteristics. Note 1 modified below Figure 20: Typical application with an 8 MHz crystal.3. CL1 and CL2 replaced by C in Table 22: HSE 4-16 MHz oscillator characteristics and Table 23: LSE oscillator characteristics (fLSE = 32. Table 24: HSI oscillator characteristics modified. notes modified and moved below the tables.10: EMC characteristics on page 49.768 kHz). 24-Sep-2009 3 Doc ID 15060 Rev 3 79/80 . Typical IDD_VBAT value added in Table 16: Typical and maximum current consumptions in Stop and Standby modes. Small text changes. Figure 23: Recommended NRST pin protection modified. Date Revision history Document revision history (continued) Revision Changes Note 5 updated and Note 4 added in Table 5: Low-density STM32F103xx pin definitions.STM32F103x4. Figure 14: Typical current consumption on VBAT with RTC on versus temperature at different VBAT values added. Jitter added to Table 27: PLL characteristics on page 48. STM32F103x6 Table 56. IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to IEC 61967-2 in Section 5. VRERINT and TCoeff added to Table 12: Embedded internal reference voltage. Conditions removed from Table 26: Low-power mode wakeup timings. Finland . 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