March 29, 2005SPWG Notebook Panel Specification Version 3.5 Purpose: SPWG (Standard Panel Working Group) was formed to establish a set of standard LCD panels with dimensions and interface characteristics that allow both notebook and LCD supplier industries to manage the volatile LCD supply and demand in an easier fashion. This effort enables panels from multiple LCD suppliers to be used in most notebooks (or other products utilizing these standard panels) that are designed around these Standard Panels without changing either the notebook/product or the LCD panel module tooling. Summary: To date, the notebook and panel industry has been plagued by an overabundance of unique/custom designs from the many LCD suppliers in the industry. This has in turn, forced the notebook OEM’s and other end-product users to change their packaging, interface design and tooling literally every time a new panel supplier or module has been used. This leads to schedule slippages, missed market opportunities, and logistic and product obsolescence problems. Similarly, many times this problem has blocked some LCD manufacturers from being considered as a potential supplier due to the magnitude of changes that their design would force on the notebook end product. As more panel suppliers come on line in the near future, this style of independent designs would only increase this problem for both the notebook OEM’s as well as the LCD suppliers. In an attempt to lessen this problem, these requirements are being established with the aid of PC makers, notebook OEMs, LCD panel suppliers, and other parties related to the development of notebook displays. Version 3.5 adds a new panel size 14.1”W and incorporates its option for an integrated inverter. Backward compatibility with existing SPWG panels is maintained. As in earlier versions no limits are placed on the LCD panel feature sets. A typo found in the 3.0 version of the 14.1” was also corrected. The JST connector part number was updated on all drawings. The Panel Power Sequence, section 5.9, was modified so that the “T” value definitions matched those of versions 1.0 and 2.0 of the SPWG spec. Warranty: The contributors acknowledge that this document is provided “AS IS” WITH NO WARRANTIES WHATSOEVER, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO ANY WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION, OR SAMPLE. March 29, 2005 Intellectual Property: The contributors to this document acknowledge that each may have patent rights. Except for the rights expressly provided by this agreement, no promoter grants or receives, by implication, estoppels or otherwise, any rights under any patents or other intellectual property. This document is developed without regard to whether its adoption may involve any patents, articles, materials, or processes. The adoption of this document does not assume any liability to any patent owner, nor does it assume any obligation to parties adopting to use this standard. Trademarks: All trademarks used within this document are the property of their respective owners; VESA, DDC/CI, EEDID are trademarks of Video Electronics Standard Association, LVDS is a trademark of National Semiconductor, HRS is a trade mark of Hirose Electric Company Ltd., Honda is a trademark of Honda Connectors, Inc., I2C is a trademark of Philips, JAE is a trademark of Japan Aviation Electronics Industry, Ltd., JST is a trademark of JST Manufacturing Co, Ltd., PC99 is a trademark of Microsoft Corporation. Support: The Standard Panel Working Group, which consists of many of the major notebook suppliers, in conjunction with many of the leading LCD suppliers, and other parties related to the development of notebook displays, have established these mechanical and electrical standards defined herein. This document has been refined through a number of proposal/feedback review cycles with these suppliers. This document is intended as a reference document only for both notebook OEMs and panel suppliers and other parties related to the development of notebook displays. Users of this document should not base final end-product designs (notebook or other) on this document, but instead should utilize the display supplier’s detailed drawings and specifications for full documentation. 2 March 29, 2005 What is New in SPWG Version 3.5 Item Description 14.1” Panel dimension from datum line to top of panel. 14.1”W Panel defined 14.1”W Panel with Inverter defined JAE Inverter I/O Connector introduced on 14.1”W panel with inverter drawing. 14.1”W JAE Inverter I/O Connector pin-out defined. JST CCFL connector (N) suffix added to denote lead free version. Panel Power Sequence “T” value definitions were changed to be consistent with those SPWG version 2.0 14.1”W Inverter, PWM input voltage brightness control pin. SPWG Ver. 3.0 Section 4.4 15.5mm+0.0,-2.5 N/A N/A N/A N/A N/A Section 5.9. N/A SPWG Ver. 3.5 Section 4.4 15.3mm+0.0,-2.5 Section 4.5. Section 8.5. Section 8.5. Section 8.1.2. All panel drawings and Section 8.1.1. Section 5.9. Section 8.1.2. pin 11 3 March 29, 2005 Table of Contents 1.0 Introduction & Overview: 2.0 Reference Documents: 3.0 Panel Resolution & Aspect Ratio: 4.0 Mechanical Properties: 5.0 Electrical Interface: 6.0 Optical Measurement: 7.0 Power Measurement: 8.0 Inverter Integration: 9.0 Screen Cosmetic Evaluation: 10.0 Panel Reliability: 4 March 29, 2005 1.0 Introduction and Overview: This document defines selected electrical interface requirements and mechanical dimensions for a series of industry compatible panels for XGA (1024x768), WXGA (1280x800, 1440x900), SXGA+ (1400x1050), WSXGA+ (1680x1050), UXGA (1600x1200), WUXGA (1920x1200), and QXGA (2048x1536) resolution LCD panels. These standard panels are defined as having 12.1”12.1”W, 13.3”, 14.1”, 14.1”W, 15.0”, 15.4”W, and 17.0”W display screens. Through the DDC/EEDID interface, graphics controller BIOS and driver support is provided as well as support for Microsoft PC99 and future PCxxxx requirements. With most panels used in portable computer designs today, the notebook OEM may have different interface cables, plastic or magnesium enclosures, bezels, bracket assemblies, and EMI shields for every panel used. For each of these parts, there are associated tooling changes required and schedule impacts relative to these tooling changes, to support the use of the different panels. Additionally, the associated documentation and logistics impacts for these different configurations are staggering. Many times these changes and schedule impacts, caused by these changes, eliminate many panel suppliers from being considered as potential 2nd sources. This document establishes common panels for the multiple display sizes/aspect ratios. This enables a Standard Panel to be mounted in any system that has been designed to accept the maximum size Standard Panel of any size defined. The Standard Panel design has been developed to allow LCD panel suppliers the opportunity for product differentiation and still meet the intent of transparent usage across different platforms. LCD manufacturers that have endorsed the SPWG standard include: AU Optronics, BOE/Hydis, Chi Mei, CPT, HannStar, Hitachi, IDTech, InnoLux, LG.Philips LCD, Mitsubishi, Quanta Display, Samsung, Sharp, Toppoly, Tottori Sanyo, and TMDisplay Additionally, with the various requirements of PC00 and future PCxxxx versions, the incorporation of EEDID information will allow transparent usage with minimum changes to system BIOS or drivers. The end objective is to specify the panel-timing requirement so that no BIOS or driver changes are required with the use of a new panel 2.0 Reference Documents: The following documents form a part of this specification to the extent specified herein. The user of this document is advised to ensure they have the latest versions of these reference standards and documents. • • • • • VESA Display Data Channel Standard, DDC2B VESA Enhanced Extended Display Identification Data VESA Flat Panel Display Measurement Standard, version 2.0 Philips I2C Bus Specification – Data Handbook I2C Peripherals for Microcontrollers TIA/EIA-644 Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits 5 revision 1. 2002.3” XGA 1024 x 768 4:3 0. version 1.217 117 15.0”W WUXGA 1920 x 1200 16:10 15. resolutions.259 98 15.0” QXGA 2048 x 1536 4:3 Panel Size Resolution Pixels Aspect Ratio Pixel Pitch Pixels/Inch* 12.1”W WXGA 16:10 1440 x 900 0. FPDMSU.158 161 15.0”W WSXGA+ 1680 x 1050 16:10 14.0”W WXGA 16:10 1440 x 900 12. April 9.1”. Nov. 17.3”.4”W.0”W WUXGA 1920 x 1200 16:10 0.230 110 15. 2003 3. 14. Resolution Pixels Aspect Ratio XGA 1024 x 768 4:3 SXGA+ 1400 x 1050 4:3 UXGA 1600 x 1200 4:3 1280 x 800 12.3”.1.237 107 14.240 106 12.1”W.193 132 14. 17.210 121 14.0” UXGA 1600 x 1200 4:3 0.0” 14.1”W. 15.4”W.org . 17. 14.255 100 17.1”W WSXGA+ 1680 x 1050 16:10 0.190 134 15.4”W. 15. and pixels per inch covered by this specification are shown in the charts below.0”W WSXGA+ 1680 x 1050 16:10 0.0” SXGA+ 1400 x 1050 4:3 0.1”W.0” 12.0 Panel Sizes.1”W.March 29.204 125 14.1”.148 172 1280 x 800 0. VESA file at www. & Aspect Ratio: The notebook display panel sizes.1”W WSXGA+ 1680 x 1050 16:10 0.1” SXGA+ 1400 x 1050 4:3 0.287 89 17.1”.296 86 15.191 133 Approx values which may vary slightly by LCD supplier.219 116 17.1” XGA 1024 x 768 4:3 0.0” . 6 Panel Size 12.0” QXGA 2048 x 1536 4:3 0.1”. 15.180 141 14.15.5.1” SXGA+ 1400 x 1050 4:3 0. 15.ppt VESA Coordinated Video Timing Generator.1” XGA 1024 x 768 4:3 0.4”W WXGA 16:10 1440 x 900 0.1”W WXGA 16:10 1440 x 900 0.264 96 13.176 144 1280 x 800 0.181 140 12.204 125 12.155 164 13.179 142 1280 x 800 0. 14.0” XGA 1024 x 768 4:3 0.1”.279 91 14. Resolutions. 15.1” UXGA 1600 x 1200 4:3 0.3” SXGA+ 1400 x 1050 4:3 0.197 129 15.173 147 1280 x 800 0.4”W WUXGA 1920 x 1200 16:10 0.1”W.0”W WXGA 16:10 1440 x 900 0. 14.1”W WUXGA 1920 x 1200 16:10 0.vesa. aspect ratios.4”W WSXGA+ 1680 x 1050 16:10 0. 13. pixel pitch. 13. 2005 • • • Intel Common Panel Interface Specification. These drawings cover the display panel module only and do not include an integrated inverter. FCI.0±0. STM. JST. FCI.0” style B panels. 15. STM. JAE. Starconn. 10. 5. 2. to expand the LCD supplier base and make inverter integration easier. Notebook display panels have similar mechanical dimensions regardless of their screen resolution. To support the development of both newer display technologies and ultra thin panels.1W. 12. KEL. 8. 14.3mm minimum. These changes are minor and should have minimal impact on backwards compatibility of existing panels. The 20-pin I/O connector is listed as a HRS DF19L-20P-1H or equivalent. Panel dimensioning should be referenced from the center of this location hole. 2. Starconn.1mm diameter reference locator hole. No minimum dimension was previously specified. version 2. 0 point for dimensioning the panel 7 . Hirose. and 17. however. 14.1”. 3. There may. 2. The “units” for all drawings are millimeters. and 15. These small variations will not impact the active area center or the dimension of the system cover bezel. 15. I-PEX.0”. If an inverter is added to the module the display panel’s basic mechanical properties do not change. 13.4”W. 2005 4.3mm from the face of the panel.1”W. KEL. Some changes have been made to the existing SPWG. Sunridge. JAE. Connector manufacturers that have endorsed the SPWG standard include: DDK. the upper left mounting hole should be replaced with a 0.5 maximum.March 29. Sunridge.1”. Changes include CCFL wire length updates to eliminate inverter pigtails and a change in the mounting hole depth to 2. which allows all LCD suppliers to participate. Connector manufacturers that have endorsed the SPWG standard include: DDK. 9.1”. LG Cable. JST. The I/O connector is located on the rear of the panel and is shown as viewed from the panel’s front surface. and Uju.0”W display panels are included in this section. 7.3”. 4.0. drawings for the 13. 14. be a small variation in active area from one resolution to another caused by variations in pattern stepping capability during TFT fabrication. For these applications. The 30-pin I/O connector is listed as a JAE FI-Xx30Sx-HFxx or equivalent (locking design preferred).5±0. Hirose. Notes: 1. display panels that are too thin to reliably utilize mounting screws may be developed without incorporating the mounting holes.3”. As such this reference locating hole center becomes the 0. and Uju. LG Cable. The first and last pin numbers are labeled on the I/O connector.0 Mechanical Properties: Drawings for 12. 6. Locking I/O connectors are backwards compatible with non-locking system cables. I-PEX. 5 max 8 184.5±0.3 Connector Keep-out Area 35mm x 45mm centered about the connector centerline.5 20 1 23. -1.6 ref 12.5. -1.6 ref 6.5mm 2.8 typ 261.5 12. 2005 . PO.0±0.2 170.5 I/O Connector (Hirose) DF19L-20P-1H or equivalent 91. 8.0±01.2 6.5 units = mm 15.5±0.0±5.76±0.5mm minimum 30.8±0.5 Pin 1 Centerline 100.1” Standard Notebook Panel: 170.4 +0.1" Standard Notebook Panel Active Area 245.1 +0.5 max 7.3 199.0±0.0.1" 131.0mm dia (4-M2.4 Tapping) Mounting screw hole Minimum depth 2.3 Black Matrix Border 1.3mm Maximum depth 2.0 typ 199.5 85.3 Active Area 184.1 12.32±0.15±0.9±0.0 11.0 (JST) BHSR-02VS-1 (N) or equivalent March 29.0±0.0.9 typ 4 .2.0±0.3 Active Area Center Point 4. 3 7.0+0. PO.3 5.2 Active Area Center 138.8±0.1"W Active Area 261.4 Tapping) Minimum depth 2.5mm 50.1"W Standard Notebook Panel 2.0±5.2 12.8±0.1 ref 147.0.3±0.0.0±0.1”W Standard Notebook Panel 9 12.2 147.6 typ 163.3mm Maximum depth 2.0±1.0 typ 178.0 (JST) BHSR-02VS-1 (N) or equivalent March 29.6 ref Connector Keep-out Area 35mm x 45mm centered about the connector centerline.3 Active Area 163. 2005 .2±0.2±0.-1.2 typ Units = mm Pin 1 Centerline 32.6+0.-1.3 12.3±0.5 20 7.4±0.5±0.5 107.5mm minimum 15.6 max 4.12±0.275.5 1 116.3 7.0 30.3 178.1±0.5 Black Matrix Border 1.5 max 7.3 4 .2mm dia Mounting screw holes (8-M2. I/O Connector (HRS) DF19L-20P-1H or equivalent 73. 3 4.3 Active Area Center Point 142.3 1 30 24.7 typ 11.1 8 .3 203.6 ref 6.3±0.6 +0.3mm 6.3 13.5 68.0±0.3 Active Area 202.1 ref 121.5mm minimum (JST) BHSR-02VS-1 (N) or equivalent March 29.3 190.4 Tapping) Mounting screw hole Minimum depth 2.8±0.units = mm 284.0±1.3" Standard Notebook Panel Active Area 270.0±0.3” Standard Notebook Panel 10 13.8±0. PO.4±0.5 68.0 2.5 216.3 Connector Keep-out Area 45mm x 45mm centered about the connector centerline.0 60.5 I/O Connector JAE FI-X30S-HF or equivalent 95.1 190.0±0. 2005 .0mm dia (8-M2.1 max 13. -2.3 Black Matrix Border 1.2.5 max 13.8±0. -2. 117.5 typ 217.0 typ 6.0±5.5±0.3 7.0.4±0.8±0.5±0.3±0.3 121.5 7.1±0.5 +0.5 Pin 1 Centerline 103.3±0.0. 1 30 28.3 ref 6.0 typ Units = mm 15.5mm 2.15±0.0 65.0±0.4 Tapping) Mounting screw hole Minimum depth 2.7 typ 11.0 8 .0±0.1" 228.0 typ 228.0.5 14.3±0.5 Connector Keep-out Area 35mm x 45mm centered about the connector centerline.3+0.3 125.5 max 299.3±0.0±0.1” Standard Notebook Panel 198. -2.3 11 213.0±0.5 54.7±0.3±0.6.3 144.3mm Maximum depth 2.3 Black Matrix Border 1.0±1.0±5.2 14.5mm minimum (JST) BHSR-02VS-1 (N) or equivalent March 29.2 198.5 Pin 1 Centerline 110.2.0mm dia (8-M2.0±0.1±0.5 7.3 Active Area Center Point 150.15±0.6±0.4 14.0±0.3 7.1" Standard Notebook Panel Active Area 285. PO.8±0.3 Active Area 214.3 4.0.8 max 6.3 99.5 I/O Connector (JAE) FI-Xx30Sx-HFxx or equivalent (locking design preferred) 54.3 +0. -2. 2005 .0 ref 144. 1±0.5±0.5 Units = mm 8.2 typ 108.3 Active Area 189.5±0.4 typ Black Matrix Border >=1.5±0. 2005 .5 typ (JST) BHSR-02VS-1 (N) or equivalent 187.0±5.3 Active Area Center 168.4±0.0±0.0±0.0±1.3 61. I/O Connector (JAE) FI-Xx30Sx-HFxx or equivalent.1"W Active Area 303.3 85.3 205.3 160.9 typ 108.5±0.0±0.3±0.6±0.0 30.5 108.1”W Standard Notebook Panel 12 14.5mm 30.3 6.5 1 30 18. PO.5mm 70.5±0.6±0.9±0.5mm <=2.3 4.1"W Standard Notebook Panel 3.3 14.3 Connector Keep-out Area 35mm x 45mm centered about the connector centerline.2mm dia Mounting screw holes (8-M2.6±0.1±0.5 9.5 14.3 168.3 5.5±0.3 8 .4 Tapping) Minimum depth 2.0 March 29.319.5 94.3mm Maximum depth 2.5 max 7. locking design preferred 61.5±0. 3 15.0" Active Area Center Point 242.4±0.9±0.0 (JST) BHSR-02VS-1 (N) or equivalent March 29.8 typ 11.0±1.5 56.2±0.5 15.9 ref 160.5 7.3 Black Matrix Border 1.5 mm 3.9±0.5mm minimum 6. 2005 .5 317.9±0.0” Standard Notebook Panel 13 15.3 7.3 5.5 Connector Keep-out Area 35mm x 45mm centered about the connector centerline.0 max 12. 160.2±0.3 159.3 1 30 30.3 I/O Connector (JAE) FI-Xx30Sx-HFxx or equivalent (locking design preferred) 134.35±0.0mm dia (8-M2.5 56.0" Standard Notebook Panel Active Area 304.8 +0. -2.0 typ 242.0.0±5.0.65±0.3 ref 108.0 80.4.3mm Maximum depth 2. -2.1±0.2 8 .2 217.6 max 229.1±0.4±0.4 Tapping) Mounting screw holes Minimum depth 2.8+0.2.6 7.1 typ Units = mm Pin 1 Centerline 119.3 Active Area 228.1±0. PO.3±0.4±0.3 217.5±0. 5 1 30 28.7 11.4”W Standard Notebook Panel 14 15.6±0.0±0.4.1±0.3 6. 2005 .5 Active Area 331.5 344.5 Connector Keep-out Area 45mm x 45mm centered about the connector centerline. 54.5mm minimum Pin 1 Centerline 110.5 typ Black Matrix Border 1.8±0.6 ref 144.2 ref 99.0 30.0±0.3 7.0±0.5 max 7.0 March 29.4"W Standard Notebook Panel 3.3±0.0±0.5mm 101.3 222.5 typ (JST) BHSR-02VS-1 (N) or equivalent 209.0±0.3 125.3mm Maximum depth 2.3 198.4"W Active Area Center Active Area 207.0±1.3 5.2±0. PO.5 54.2±0.0±5.6 max 8 .0±0.2mm dia Mounting screw holes (8-M2.0±0.3 172.3 I/O Connector (JAE) FI-Xx30Sx-HFxx or equivalent (locking design preferred) 144.3 15.5 Units = mm 7.4 Tapping) Minimum depth 2.3 198.75±0.3 15.7±0.0 typ 222.3±0.85±0. 5 typ (JST) BHSR-02VS-1 (N) or equivalent 228.5 typ Black Matrix Border 1.3 17.8±0.8 382.3 244.5±0.3 155.2±0.25±0.25±0.3 7.5 8 . PO.5 Pin 1 Centerline 58.0 81±5. 108.3 191. 2005 .3 7.5 1 30 27.5±0.3 212.25±0.5 Connector Keep-out Area 45mm x 45mm centered about the connector centerline.0±1.5±0.3mm Maximum depth 2.5mm minimum 16.0"W Standard Notebook Panel 3.5mm 30.25±0.0”W Standard Notebook Panel 15 17.0"W Active Area 367.3 Active Area Center 7.3 123.5±0.5 I/O Connector (JAE) FI-Xx30Sx-HFxx or equivalent (locking design preferred) 58.0±0.5±0.4.5 max 212.4 Tapping) Minimum depth 2.5 ref 155.2mm dia Mounting screw holes (8-M2.5 ref 106.3 17.3±0.5 Units = mm 7.5 typ 245.3±0.1±0.2±0.25±0.0 March 29.0 max 7.3 Active Area 229. G0 Ground . G0 + LVDS differential data input.1”. HS/VS/DE (NC on XGA resolution) + LVDS differential data input.LVDS differential data input.LVDS differential data input.LVDS differential data input.3 V (typical) DDC 3. R0 – R5.3”. G0 (odd pixels on SXGA+ & higher resolutions) Ground . HS/VS/DE + LVDS differential data input.3 V power Reserved for LCD supplier test point DDC Clock DDC Data .4”W. G1 – G5.3 V power Reserved for LCD supplier test point DDC Clock DDC Data .LVDS differential clock input (odd pixels on SXGA+ & higher resolutions) LVDS differential clock input (odd pixels on SXGA+ & higher resolutions) Ground . B0 – B1 (NC on XGA resolution) Ground .0 5. B0 – B1 (odd pixels on SXGA+ & higher resolutions) + LVDS differential data input.0”W Display Interface Cable Pin Assignments I/O Connector: (JAE) FI-Xx30Sx-HFxx or equivalent (2 Channel LVDS) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symbol VSS VDD VDD V EEDID Tp Clk EEDID Data EEDID Odd RIN 0 Odd RIN 0 + VSS Odd RIN 1 Odd RIN 1+ VSS Odd RIN 2 Odd RIN 2+ VSS Odd Clk IN Odd Clk IN + VSS Even RIN 0 Even RIN 0 + VSS Even RIN 1 Even RIN 1 + VSS Even RIN 2 Even RIN 2 + VSS Even Clk IN Even Clk IN + Pin Function Ground Power Supply.1” & 12. HS/VS/DE (odd pixels on SXGA+ & higher resolutions) Ground . R0 – R5. R0 – R5. B2 – B5. and 17.LVDS differential data input.3 V (typical) Power Supply. even pixels.LVDS differential data input. HS/VS/DE Ground . HS/VS/DE (odd pixels on SXGA+ & higher resolutions) + LVDS differential data input.3 V (typical) DDC 3.LVDS differential data input.March 29.LVDS differential clock input + LVDS differential clock input Ground Ground 13. even pixels.LVDS differential data input. B2 – B5. G0 (odd pixels on SXGA+ & higher resolutions) + LVDS differential data input. even pixels.0”. G0 (NC on XGA resolution) + LVDS differential data input. even pixels (NC on XGA resolution) + LVDS differential clock input. R0 – R5. HS/VS/DE (NC on XGA resolution) Ground . B0 – B1 Ground . 2005 5. 3. B0 – B1 + LVDS differential data input. even pixels (NC on XGA resolution) 16 . 3. even pixels. B2 – B5.LVDS differential clock input.LVDS differential data input. B0 – B1 (NC on XGA resolution) + LVDS differential data input. B2 – B5. 14. R0 – R5. G1 – G5.3 V (typical) Power Supply. G1 – G5. even pixels.LVDS differential data input. 14. G0 (NC on XGA resolution) Ground . 15. even pixels.1”W Display Interface Cable Pin Assignments I/O Connector: (HRS) DF19L-20P-1H or equivalent (1 Channel LVDS) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Symbol VSS VDD VDD V EEDID Tp Clk EEDID Data EEDID Odd RIN 0 Odd RIN 0 + VSS Odd RIN 1 Odd RIN 1+ VSS Odd RIN 2 Odd RIN 2+ VSS Odd Clk IN Odd Clk IN + VSS VSS Pin Function Ground Power Supply.1”W. 3. B0 – B1 (odd pixels on SXGA+ & higher resolutions) Ground . B2 – B5. B2 – B5.1 Electrical Interface: Connectors & Pin-Outs 12. 15. R0 – R5. G1 – G5. 3. G1 – G5. G1 – G5. 51 74.95 Typ Units 1536 3 4 37 1580 59.901 0.678 0.47 Typ 1680 48 32 80 1840 15.55 94. Sync PW Vertical Bk Porch Vertical Period Vertical Frequency Typ 768 3 4 15 790 59. Back Porch Horizontal Period Horizontal Period Horizontal Freq. Single LVDS Channel Primary Timing Values at a 60 Hz Frame Rate Resolution Overall Dot Clock XGA SXGA+ UXGA WXGA(I) WXGA(II) WSXGA+ WUXGA QXGA 1024x768 1400x1050 1600x1200 1280x800 1440x900 1680x1050 1920x1200 2048x1536 Typ 56.000 6.March 29. 2005 5.00% Typ 71.14 47.50 74. Typ 1024 48 32 80 1184 21. revision 1.31 Typ 1440 48 32 80 1600 18.779 nsec 0.92 Typ 800 3 6 14 823 59.000 8.28 49.403 0.00% % of Dot FFPD LFPDP DCSS Dot Clock Freq.494 0.04 Typ Units 2048 48 32 80 2208 10. Sync PW Horiz.46 64.77 Pixels Pixels Pixels Pixels Pixels µsec KHz Vertical Parameters Name VA VFP VSPW VBP VP VFP Definition Vertical Active Vertical Front Porch Vert.00% Typ 101.268 0.00% Typ 130.87 Typ 1050 3 4 23 1080 59.085 0.1.44 64.250 7.90 Typ 1050 3 6 21 1080 59. Front Porch Horiz.98 Typ 1200 3 6 26 1235 59. 2003.2 Signal Timing Notebook signal timing is 18 bit as defined VESA Coordinated Video Timing Generator.000 9.857 0.98 Lines Lines Lines Lines Lines Hz 17 .00% Typ 154.000 14.30 Typ 1400 48 32 80 1560 15.00% Typ Units 209.74 Typ 1600 48 32 80 1760 13. Dot Clock Period Clock Spread Horizontal Parameters Name HA HFP HSPW HBP HP HP HF Definition Horizontal Active Horiz.01 Typ 1280 48 32 80 1440 20.750 11.67 Typ 1920 48 32 80 2080 13. with reduced blanking.250 MHz 4.95 Typ 1200 3 4 28 1235 59. April 9.91 Typ 900 3 6 17 926 59.000 17.00% Typ 119.00% Typ 88.03 55. 3 Signal Timing Waveforms Parameters 18 .March 29. 2005 5. 18bpp. 2005 5. Single Channel LVDS Data Mapping (18bpp) 20-Pin Connector 5.5 Single Channel LVDS Data Mapping (18bpp) 30-Pin Connector Clk +/Rin0 +/Rin1 +/Rin2 +/E Clk +/E Rin0 +/E Rin1+/E Rin2+/- 19 . These diagrams define the current 6 bit.4 LVDS Data and Control Signal Interface The panel LVDS signals interface should meet the requirements of TAI/EAI-644. The figures below show mapping diagrams of each LVDS channel. notebook panel LVDS addressing scheme.March 29. 1024 1. 1 1200.March 29. 2005 5. 1440 1. 1920 1. 1280 1. 1 900. 1600 1. 1 800. 1 1050. 1 1536. 1400 1. 1 20 .6 Dual Channel LVDS Data Mapping (18bpp) 30-Pin Connector 5. 1680 1. 2048 768.7 Active Area Pixel Layout 1. Header Byte Byte (dec) (hex) 0 00 Header 1 01 Header 2 02 Header 3 03 Header 4 04 Header 5 05 Header 6 06 Header 7 07 Header Field Name and Comments Value (hex) 00 FF FF FF FF FF FF 00 Value (binary) 00000000 11111111 11111111 11111111 11111111 11111111 11111111 00000000 Vendor / Product ID / EDID Version Byte (dec) 8 9 10 11 12 13 14 15 16 17 18 19 Byte (hex) Field Name and Comments 08 EISA manufacture code = 3 Character ID 09 EISA manufacture code (Compressed ASCII) 0A Panel Supplier Reserved – Product Code 0B Panel Supplier Reserved – Product Code 0C LCD module Serial No – Preferred but Optional (“0” if not used) 0D LCD module Serial No – Preferred but Optional (“0” if not used) 0E LCD module Serial No – Preferred but Optional (“0” if not used) 0F LCD module Serial No – Preferred but Optional (“0” if not used) 10 Week of manufacture 11 Year of manufacture 12 EDID structure version # = 1 (EDID V1. Rev 1.March 29.2×100 ) – 100 = 17 120 18 Feature support ( no DPMS. 2/9/2000) Value Value (hex) (binary) 00 00 00 00 00000000 00000000 00000000 00000000 01 03 00000001 00000011 Display Parameters Byte Byte (dec) (hex) 20 21 22 23 24 Field Name and Comments 14 Video I/P definition = Digital I/P (80h) 15 Max H image size = (Rounded to cm) 16 Max V image size = (Rounded to cm) Display gamma = (gamma ×100)-100 = Example: ( 2. RGB. 2005 5. timing BLK 1) Value Value (hex) (binary) 80 10000000 0A 00001010 21 . Active off.8 This is the EDID (Enhanced Extended Display Identification Data) data format to support displays as defined in the VESA Plug & Display.3) 13 EDID revision # = 3 (Release A. xxx 1C Red Y Ry = 0.xxx 22 White Y Wy = 0. 2005 Panel Color Coordinates Byte (dec) 25 26 27 28 29 30 31 32 33 34 Byte (hex) Field Name and Comments 19 Red/Green Low bit (RxRy/GxGy) 1A Blue/White Low bit (BxBy/WxWy) 1B Red X Rx = 0.xxx Value (hex) Value (binary) Established Timings Byte Byte (dec) (hex) Field Name and Comments 35 23 Established timings 1 (00h if not used) 36 24 Established timings 2 (00h if not used) 37 25 Manufacturer’s timings (00h if not used) Value Value (hex) (binary) 00 00000000 00 00000000 00 00000000 Standard Timing ID Byte (dec) 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Byte (hex) 26 Standard timing ID1 27 Standard timing ID1 28 Standard timing ID2 29 Standard timing ID2 2A Standard timing ID3 2B Standard timing ID3 2C Standard timing ID4 2D Standard timing ID4 2E Standard timing ID5 2F Standard timing ID5 30 Standard timing ID6 31 Standard timing ID6 32 Standard timing ID7 33 Standard timing ID7 34 Standard timing ID8 35 Standard timing ID8 Field Name and Comments (01h if not used) (01h if not used) (01h if not used) (01h if not used) (01h if not used) (01h if not used) (01h if not used) (01h if not used) (01h if not used) (01h if not used) (01h if not used) (01h if not used) (01h if not used) (01h if not used) (01h if not used) (01h if not used) Value (hex) 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 Value (binary) 00000001 00000001 00000001 00000001 00000001 00000001 00000001 00000001 00000001 00000001 00000001 00000001 00000001 00000001 00000001 00000001 22 .xxx 1D Green X Gx = 0.xxx 1E Green Y Gy = 0.March 29.xxx 1F Blue X Bx = 0.xxx 21 White X Wx = 0.xxx 20 Blue Y By = 0. 02.000 (MSB) Horizontal Active = xxxx pixels (lower 8 bits) Note 2 Horizontal Blanking (Thbp) = xxxx pixels (lower 8 bits) Horizontal Active/Horizontal blanking (Thbp) (upper4:4 bits) Vertical Active = xxxx lines Vertical Blanking (Tvbp) = xxxx lines (DE Blanking typ.000 (MSB) Horizontal Active = xxxx pixels (lower 8 bits) Note 2 Horizontal Blanking (Thbp) = xxxx pixels (lower 8 bits) Horizontal Active/Horizontal blanking (Thbp) (upper4:4 bits) Vertical Active = xxxx lines Vertical Blanking (Tvbp) = xxxx lines (DE Blanking typ. H/V pol Negatives.000 (LSB) Pixel Clock/10. Offset (Thfp) = xxxx pixels Horizontal Sync. 03. For DE only panels) Vertical Active : Vertical Blanking (Tvbp) (upper4:4 bits) Horizontal Sync. DE 18 only note: LSB is set to “1” if panel is DE-timing only. Normal. 01. H/V can be (19) ignored. Offset (Tvfp) = xx lines Sync Width = xx lines Horizontal Vertical Sync Offset/Width upper 2 bits Horizontal Image Size =xxx mm Vertical image Size = xxx mm Horizontal Image Size / Vertical image size Horizontal Border = 0 (Zero for Notebook LCD) Vertical Border = 0 (Zero for Notebook LCD) Module “A” Revision = Example: 00. 2005 Timing Descriptor #1 Byte (dec) 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 Byte (hex) 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 Value Field Name and Comments (hex) Pixel Clock/10. Value (hex) Value (binary) 00 00 00000000 00000000 23 . Offset (Thfp) = xxxx pixels Horizontal Sync.000 (LSB) Pixel Clock/10. no stereo. Value (binary) 00000000 00000000 00011000 00011001 Timing Descriptor #2 Alternative Panel Timing Byte (dec) 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 Byte (hex) 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 Field Name and Comments Pixel Clock/10. etc. For DE only panels) Vertical Active : Vertical Blanking (Tvbp) (upper4:4 bits) Horizontal Sync. Separate sync.March 29. Offset (Tvfp) = xx lines Sync Width = xx lines Horizontal Vertical Sync Offset/Width upper 2 bits Horizontal Image Size =xxx mm Vertical image Size = xxx mm Horizontal Image Size / Vertical image size Horizontal Border = 0 (Zero for Notebook LCD) 00 Vertical Border = 0 (Zero for Notebook LCD) 00 Non-interlaced. Pulse Width = xxxx pixels Vertical Sync. Pulse Width = xxxx pixels Vertical Sync. 2005 Timing Descriptor #3 Byte (dec) 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 Byte (hex) Field Name and Comments 5A Flag 5B Flag 5C Flag 5D Dummy Descriptor 5E Flag 5F PC Maker P/N 1st Character 60 PC maker P/N 2nd Character 61 PC maker P/N 3rd Character 62 PC maker P/N 4th Character 63 PC maker P/N 5th Character 64 LCD Supplier EEDID Revision # 65 Manufacturer P/N 66 Manufacturer P/N 67 Manufacturer P/N 68 Manufacturer P/N 69 Manufacturer P/N 6A Manufacturer P/N Manufacturer P/N (If <13 char. set remaining char = 20h) 0A 20 20 Byte Value Value (hex) Field Name and Comments (hex) (binary) 7E Extension flag (# of optional 128 EDID extension blocks to follow.March 29. 01 – Present) (If <13 char. then terminate with ASCII code 0Ah. XXX nits) 79 7A 7B 7C 7D Number of LVDS channels = 1 or 2 Panel Self Test (00 – Not Present. set remaining char = 20h) (If <13 char. set remaining char = 20h) (If <13 char. then terminate with ASCII code 0Ah. then terminate with ASCII code 0Ah. then terminate with ASCII code 0Ah. Typ = 0) 00 00000000 7F Checksum (The 1-byte sum of all 128 bytes in this EDID block shall = 0) 24 . set 107 6B remaining char = 20h) Value (hex) 00 00 00 FE 00 Value (binary) 00000000 00000000 00000000 11111110 00000000 Timing Descriptor #4 Byte (dec) 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 Byte (dec) 126 127 Byte (hex) 6C Flag 6D Flag 6E Flag 6F Data Type Tag: 70 Flag Field Name and Comments Value (hex) 00 00 00 FE 00 Value (binary) 00000000 00000000 00000000 11111110 00000000 Value Value Value Value Value Value Value Value 00000000 00001010 00100000 00100000 71 SMBUS Value = XX nits 72 SMBUS Value = XX nits 73 SMBUS Value = XX nits 74 SMBUS Value = XX nits 75 SMBUS Value = XX nits 76 SMBUS Value = XXX nits 77 SMBUS Value = XXX nits 78 SMBUS Value = max nits (Typically = 00h. 2005 EEDID Notes: 1. is HA for XGA and HA/2 for WSXGA+ and above resolutions. Horizontal Active (HA).9 Panel Power Sequence 90% Power Supply For LCD VCC 10% 0V T1 Interface Data Signal. 10 50 50 10 (ms) (ms) (ms) (ms) (ms) (ms) (ms) (ms) 25 . 0. 3. bytes 55 & 56. Timing Descriptor #2 may used for timings other than 60Hz 5. Vi (LVDS Signal of Transmitter) 90% 10% T 3 T7 Valid Data T4 T2 0V T5 T6 BLamp On FPVEE Backlight on/off OFF OFF T8 Power for Inverter VIN Power Sequence Timing Parameter T1 T2 T3 T4 T5 T6 T7 T8 Min.March 29. See page 16 for “Timing Waveform Parameters” definitions. Units Max. HA pixel clks value. 2.5 0 0 200 200 200 0 10 Value Typ. byte 38h. is true active pixels. or equivalent.10 Panel Backlight Interface The panel CCFL cable should be terminated with a JST BHSR-02VS-1 connector. 2005 5. Backlight Electrical Interface Pin No. The lamp wires exiting the panel should be sufficiently protected so that normal movement of these wires during cover assembly will not cause them to be damaged.March 29. Signal Level Function 1 VCCFL AC Power supply for CCFL 2 Gnd Return ~GND Power return for CCFL 26 . or color tolerance >+/-0. Temperature: 23°C±4°C Humidity: 25% . > +/-2%. 2005 6.3 CCFL (Cold Cathode Fluorescent Lamp) warm-up time. 27 . The standard office conditions are. all measurements should be performed in a darkroom.1.1. The procedure for measuring each of the following optical/FOS (Front Of Screen) properties are defined in this section.). 6.1.) that could corrupt the measurements. will show approximate properties but should not be used to accurately compare measurements of one panel with another. Display FOS properties are measured with a photometer equivalent to a. 6. Luminance Contrast Ratio Uniformity Color Gamut Color Gamma Viewing Angle Response Time Residual Image 6. Measurements made outside these conditions may not be valid for comparison of one panel to another.2 Measurement environment. The CCFL requires time to achieve its set brightness after turn on. however. Photo Research PR-650/880 or a TOPCON BM5A. The darkroom definition assumes that all light comes from the display and that there are no reflective surfaces (white clothing. To eliminate variation in screen reflection.I. Other measurement equipment with a larger luminance measurement tolerance.1 Measurement equipment. non-condensing Atmospheric pressure: 25 inHg to 31inHg 6.0 Optical/FOS Measurement: This spec generally employees the VESA Flat Panel Display Measurements Standard.1. To insure accurate optical measurements the CCFL should be turned on and be allowed to warm-up for a minimum of 20 minutes.4 Darkroom measurement conditions. etc. Version 2 for its panel optical measurement procedures.1 General Measurement Requirements: 6.0015 (1931 C. have been modified slightly to make them more meaningful to the end user. light colored objects. computer displays.85% RH. ≤1 lux. Measurements are made in normal office condition environment.March 29.E. Some measurement procedures. contrast ratio. Luminance. Display Screen 500mm 2° Aperture Photometer Display Screen 1000mm 1° Aperture Photometer 28 .6 Measurement viewing direction. “Normal” measurements are performed perpendicular to the display screen surface.5 Display luminance control during measurement.3°.March 29. ±0.1. See the drawings below. A 2o aperture is used when the photometer is positioned 500mm from the screen to be measured and a 1o aperture when the distance is 1000mm.1. 6. to the display screen. Changing the luminance to optimize measurement is not allowed. color gamut. During a set of optical measurements the screen luminance should not be changed. and response time measurements should be performed with a viewing direction which is perpendicular.1. Viewing angle measurements should be performed at angles that reference the screen center. 2005 6. The fixed distance is determined by the photometer measurement aperture used. uniformity. 6.7 Measurement equipment setup: The photometer is placed at a fixed distance from the display screen to be measured. Changes in luminance require that the entire FOS measurement suite be repeated. color gamma. 2005 Example of a Typical Optical FOS Measurement System 29 .March 29. 1+2+3+4+5 Display Luminance = 5 100% 1 5 3 4 2 75% 50% 25% 0 0 25% 50% 75% 100% Screen Luminance Measurement Points (5) 30 . To eliminate variations in environmental lighting conditions that can affect display luminance. all measurements are performed in a dark ambient. Display luminance is defined as the average value of five (5) white screen measurements. The location of these 5 measurement points is shown in the drawing below.2 Luminance Measurement: Luminance is a cd/m2 (nits) measurement of the display’s white color (white screen). 2005 6.March 29. 3 Contrast Ratio Measurement: Contras Ratio (CR) is the comparison of the display screen’s maximum white luminance (white screen) to its minimum luminance (black screen). 0o). Contrast Ratio is measured perpendicular to the display at the screen center (“Normal Line”. 2005 6. θ =0o θL o θ L =90 x θR φL φH 12 O’clock direction o y φ H = 90 6 O’clock direction φ L = 90o y’ x’ θR =90o 31 .March 29. Although other screen patterns (various black and white checkerboard patterns) could be used these can add variation to the CR value. A full white screen and a full black screen are used when measuring luminance for contrast ratio. CR is expressed as a ratio of white luminance value to black. 0o. Luminance of all white screen CR = __________________________ Luminance of all black screen Normal Line φ = 0o. Example: 150:1 (white luminance is 150 times greater than black luminance). 1-13) Max Luminance (13 Pts. All measurements are performed with the photometer perpendicular to the display screen surface. Luminance % Uniformity = Max Luminance (13 Pts. 2005 6. This measurement describes the uniformity of the LCD lighting system. The location of these 13 measurement points is shown in the drawing below.March 29. 1-13) – Min Luminance (13 Pts. Display luminance uniformity is defined as the percent (%) of luminance value variation over thirteen (13) white screen measurements. 1-13) 10mm 6 10mm 1 7 10mm 8 2 5 10 4 12 13 100% 75% 50% 25% 0 9 3 11 10mm 0 25% 50% 75% 100% Screen Uniformity Measurement Points (13) 32 . To eliminate variations in environmental lighting conditions that can affect display luminance.4 White Uniformity Measurement: White luminance uniformity is a cd/m2 (nits) measurement of the display’s white color across the display screen. all measurements are performed in a dark ambient.. A 100% blue screen (r=0. A 100% green screen (r=0. and blue. green. This percentage is commonly referred to as the color gamut for the display. The measurements are taken at the screen center (Normal Line) perpendicular to the display. referenced to the 1931/1976 CIE color standard. Notebook panels are 6 bit and actually produce only 64 shades of gray for each color. Note: Graphic adapters typically define 8 bit color settings with 256 shades of gray for each color as shown above. & b=255) is used to measure the color blue. g=255.5 Color Gamut Measurement: Color Gamut is the measurement of the display color chromaticity coordinates. g=0. by the R G B coordinates. This comparison is typically made as the measured display’s percentage of the NTSC standard. g=0. red. & b=0) is used to measure the color red. 33 . for its primary colors. can be compared with the area of the NTSC color coordinate triangle. A 100% red screen (r=255. & b=0) is used to measure the color green.March 29. The area of the triangle formed on the CIE color chart. These charts are shown below for reference only. 2005 6. March 29. 2005 34 . L21 40%. L59 100%. L30 Measured Luminance Gray Shade 9 10 11 12 13 14 15 16 Transmission or Gray Scale 53%. A windows standard 2. L42 73%. Green.2 gamma should be used.6 Color Gamma Measurement: Color gamma is the measurement of Red. L34 60%. & White) Gamma Measurement 100% 90% 80% % Color Transmission 70% Luminance Value Min nits 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Gray Scale Color Level 60% 50% 40% 30% 20% 10% 0% Max nits 35 . Gray Scale Measurement Levels Gray Shade 1 2 3 4 5 6 7 8 Transmission or Gray Level 0%. A sample chart format is shown below. The measurement units are nits (cd/m2) and are converted to percent (%) transmission and recorded in chart form. L9 20%.March 29. L0 7%. Blue and White over their gray scale range (luminance transmission 0 – 100%). L50 87%. 2005 6. L63 Measured Luminance Color (R. L13 27%. L26 47%. L38 67%. L47 80%. R G B & White.G. L55 93%. L17 33%. Note: Notebook display panels have a range of 64 shades of gray for each color.B. A minimum of 16 measurements for each color should be made. The color gamma measurements are taken at the screen center (Normal Line) perpendicular to the display. L5 13%. high (up) and low (down). Normal Line φ = 0o. at the screen center. The 180° viewing angle range is broken down as follows. 2005 6.March 29.7 Viewing Angle Measurement: Viewing angle is the measurement of contrast ratio. The measurement direction is typically perpendicular to the display surface with the screen rotated about its center to develop the desired measurement viewing angle. 90° (θ) horizontal left and right and 90° (Φ) vertical. θ =0o θL o θ L =90 x θR φL φH 12 O’clock direction o y φ H = 90 6 O’clock direction φ L = 90o y’ x’ θR =90o Vertical Viewing Angle Measurement Photometer Horizontal Viewing Angle Measurement Photometer 36 . over a 180° horizontal and 180° vertical range (off-normal viewing angles). Contrast Ratios are calculated and plotted per the graph below. 2005 Display Screen 1000mm 1° Aperture Photometer Horizontal Viewing Angle Measurement Display Screen 1000mm 1° Aperture Photometer Vertical Viewing Angle Measurement Setup Luminance measurements are made at a minimum of 20 viewing angles in both horizontal and vertical axis. Viewing angles below ±20° are measured at 4° increments. The measurements are made on both white and black screens.March 29. Viewing angles above ±20° are measured in 10° increments. 37 . 38 . 2005 Viewing angles are typically specified as a maximum ± angle with a Contrast Ratio greater (≥) than 10:1. Plotting the horizontal and vertical viewing angles in the chart format above provides an easy to understand process for evaluating and comparing display panels.March 29. expect useable viewing angles to have a Contrast Ratio’s greater (≥) than 100:1. Consumers. however. LCD Tesponse Time LCD Response Time 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% Ton Pixel On .1 the total response time. 39 .White Pixel Off . A pixel is determined to be “On” when its drive voltage reaches 90% of maximum and “Off” when the voltage level drops to 10%.March 29. The leading and trailing edge of the box will appear blurred if the speed of its movement is faster than display can update its pixels. a fast moving screen image can appear blurred if it moves faster than the screen can update the pixels. While this is not an accurate measurement of screen response time it can be used to generally compare the speed of one panel with another. “On” and “Off” are also referred to as “Rise” and “Fall” times.White Time Response Time = Ton + Toff Black and White screen patterns are switched and the resulting electro-optical step response function is measured. Measurements are made at the screen center perpendicular to the display surface (Normal Line). TOn + TOff.Black Toff Pixel Drive voltage On/Off Pixel Off . The photometer must have a response time and sample rate ≤ 0. Updates to pixel drive technology can improve the apparent response time without changing the display’s physical internal design/technology. The photometer is connected to a computer or storage oscilloscope which collects the sample data and processes it to display the “Total LCD Response Time. 2005 6.8 Response Time Measurement: Response time is the measurement of the total time takes to turn a pixel “On” and “Off”. See the chart below. A black box moving across the screen at different speeds can be an indicator of the display screen’s response time. In LCD display screens with slower response times. This residual image should dissipate after a short time.ppt. measure the white screen luminance in the same locations as on the original checkerboard pattern. 40 . Notebook displays are “normally white” screens so this turns off all the TFT pixels. white screen post burn in.9 Residual Image Measurement: A residual or retained screen image may occur if a fixed screen pattern is displayed for a long period of time. Residule Image Checkerboard Screen WL BC WR The checkerboard pattern is allowed to remain on the screen (burn in) for 16 hours. should be a specified percentage (%) of the initial checkerboard CR. slide #90 from the VESA file “Flat Panel Display Monitor Setup Patterns”. as described above. A 5 x 5 black and white checkerboard pattern should be used for the measurement (FPDMSU. After the burn in period (16 hours) the screen pattern is changed to all white. (WL+WR)/2 Initial checkerboard CR = BC (WL+WR)/2 White screen post burn in CR = BC The second CR measurement. can also be used to develop a test limit for a residual image specification. A 2 minute post burn in (white screen) CR measurement. This percentage value is determined by individual panel specifications but will typically be ≤ 1%. FPDMSU. 2005 6.March 29. Initial luminance measurements are made on the checkerboard screen center squares per the drawing below. Compare the original checkerboard contrast ratio (CR) with the 2 minute post burn in measurement. The white screen is allowed to remain on for 2 minutes.).ppt. After the 2 minutes has elapsed. Pin 1 is a 14.eblwg.1 LCD Cell Power Measurement: The panel’s luminance. has no impact on the LCD cell power measurement. LCD Cell Power Measurement Setup 1 2 3 I/O Connector 13. The procedures defined here basically mirror those established by the EBL WG (Extended Battery Life Working Group).3V) in”.0” panel ground.March 29. The LCD cell is powered by a 3. & 17. 14. For 12.0"W LCD Panels Video Source System Graphics Chip Voltage Meter (VOM) 3. Fluke 87 III multimeter. LCD and cell and Backlamp measurements can be performed using a Fluke NetDaq Data Acquisition (Model 2645A). P=VI.3V ± 10% supply from the notebook system. The basic panel power test setups are shown below. 14. Measurements for the LCD cell and the backlamp/inverter are measured separately and the results are totaled to define the display module’s power. The power unit is Watts. Power measurement assumes that the panel is powered from a power source separate from the LCD panel.0". The power supply connections are made directly to the display’s I/O connector pins or to the equivalent location at a system cable termination.1” single channel LVDS panels. 2005 7. www.0” 2 channel LVDS panels have pin 2 and 3 designated as “power (3.3".1” panel ground.3V Power Supply to Display Screen Current Meter (VOM) 41 .1” – 17.3V) is supplied through pins 1 and 2. power (3.org. produced by the backlight.1” – 17. Display power(P) for both the LCD cell and backlight is defined as the product of the input voltage (V) and its current (I) draw.4"W. 7. 15.0 Power Measurement: Display panel power is the summation of the LCD cell + the backlamp.1". The backlamp CCFL (Cold Cathode Fluorescent Lamp) is driven by a high voltage inverter which is powered by a 5V supply from the notebook system. Pin 3 is a 12. or the equivalent. 15. vesa. the screen pattern is fixed as a checkerboard.March 29. This pattern provides a typical screen for power measurement. This file is available at the VESA website. 2005 LCD Cell Power Measurement Setup I/O Connector 3 2 1 12.ppt.1" & 12.org.1"W LCD Panel Video Source System Graphics Chip Voltage Meter (VOM) 3. slide #100 from the VESA file “Flat Panel Display Monitor Setup Patterns”. FPDMSU. 32 32 x 36 Black & White Checkerboard Pattern 42 . www. The pattern used is a black and white 32 x 36 checkerboard.3V Power Supply to Display Screen Current Meter (VOM) The display cell power varies according to the pattern being displayed on the screen. To eliminate variables in measurement. The power is again the product of the voltage and current. Backlamp measurements can performed using with a Fluke 87 III digital multimeter or the equivalent. See the setup drawing below. Second. First. Since the notebook user can set the panel luminance manually. set the LCD panel to “Luminance Level 2” and measure the inverter input voltage and current draw. The efficiency of the inverter and total backlighting system will greatly affect the backlamp power usage. Backlamp power usage is in direct proportion to the panel luminance. For this reason it is necessary that a standard luminance levels be defined for measurement. In either case the true power required to drive the backlamp is a measurement of the inverter input. As panel luminance increases power also increases. The backlamp power can be measured without the inverter as shown below. Level one (1) is the maximum LCD panel luminance. The backlamp measurement procedure requires that the panel luminance be measured and manually set. set the LCD panel to “Luminance Level 1” and measure the inverter input voltage and current draw. The second (2) luminance level for backlamp power measurement is therefore set manually at ~ 60nits. The power is again the product of the voltage and current.2 Backlamp Power Measurement: The backlamp is driven by an inverter which can be either notebook system supplied or part of a LCD panel module. Two (2) luminance levels are defined for backlamp power measurement. P=VI 43 . In notebook products this luminance level is typically used with AC system power input.March 29. 2005 7. Under battery operation most notebook systems are initially set to optimize battery life and at the same time provide an adequate level of panel luminance. The backlamp power measurement process is the same for all LCD panel sizes. This battery luminance level is typically ~ 60nits (cd/m2). power measurement at this level is required. P=VI. 60nits will typically be an approximate preset luminance level in the notebook system. These standard luminance levels allow backlamp power comparisons of one panel to another. 2005 LCD Backlamp (CCFL) with Inverter Power Measurement Setup Backlamp (CCFL) CCFL Inverter Voltage Meter (VOM) 7. Power supply to CCFL Current Meter (VOM) 44 .March 29.5V-21V Power to Backlamp Inverter Current Meter (VOM) LCD Backlamp Only (CCFL) Power Measurement Setup Backlamp (CCFL) Hi-Voltage Meter CCFL Inverter Wire to Pin #2. Power return from CCFL Wire to connector pin #1. 5V to 21V to drive the backlight DC-AC converter This power rail should be used as a power rail 7.5V to 21V to drive the backlight DC-AC converter No Connection 0V Ground No Connection This should be used as power source for the control circuitry on the inverter and stores the 5V brightness/contrast values & the circuit that interfaces with SMB_CLK & SMB_DAT 0V Ground SMBus interface for sending brightness & contrast information to the inverter/panel SMBus interface for sending brightness & contrast information to the inverter/panel 0V Ground Control signal input into the inverter to turn the backlight ON & OFF (1 .1. 13.3”. 13. Input connector Honda LVC-D20SFYG or equivalent Pin Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ~ 20 INV_SRC INV_SRC INV_SRC NC GND NC 5VALW GND SMB_DAT SMB_CLK GND FPBACK GND LAMP_STAT NC This power rail should be used as a power rail to drive the backlight DC-AC converter This power rail should be used as a power rail 7.4”W. from control chip No Connection 7. 14.March 29. Lamp On = 5v. 15.0 Inverter Integration: This section is optional but is highly recommended. The inverter locations and the input pin-outs are shown in the charts and drawings below.0”W use a 20-pin inverter input connector.3”. and 17.0” 15. and 17. 12.4’W. 15. Lamp Off 0v). 2005 8.1”.1 Inverter Input Connectors 12. Backlamp inverters can be integrated to the LCD panel module.1”W.1. 8. The 14.ON. 0 – OFF) 0V Ground Lamp status (Feedback.1W panel uses a 12-pin inverter input connector. and I/O pin-outs be defined for all size panels. location.1”. connector type and location. This provides for true panel interchangeability from one LCD supplier to another. 14. Inverter integration to the LCD panel requires that the inverter dimensions.0”. 15. This also insures optimized compatibility between the inverter and the LCD panel.1”W.0W” Inverter Input Connector Pin-Out Voltage Comments 8.5V to 21V 45 . 2005 8. 7. 0 – OFF) PWM FPBACK Enable GND 0V Ground Pin used for PWM voltage input brightness PWM Variable V control. 14. LAMP_STAT 0V/5V Lamp On = 5v. used for panel diags.0V to 21V 46 .ON. Lamp status. (Feedback.2.0V to 21V to drive the backlight DC-AC converter This should be used as power source for the control circuitry on the inverter and stores the 5VALW 5V brightness/contrast values & the circuit that interfaces with SMB_CLK & SMB_DAT GND 0V Ground SMBus interface for sending brightness & SMB_DAT contrast information to the inverter/panel SMBus interface for sending brightness & SMB_CLK contrast information to the inverter/panel GND 0V Ground Control signal input into the inverter to turn the backlight ON & OFF (1 .0V to 21V to drive the backlight DC-AC converter This power rail should be used as a power rail INV_SRC 7.March 29. Lamp Off 0v).1. from control chip.1”W Inverter Input Connector Pin-Out Input connector JAE FI-K12SL-VF or equivalent Pin Function 1 2 3 INV_SRC Voltage Comments 4 5 6 7 8 9 10 11 12 This power rail should be used as a power rail to drive the backlight DC-AC converter This power rail should be used as a power rail INV_SRC 7. 5 145.3 163.D205FYG or Equivalent 175. 2) 2. 2005 .6 typ 178.3 20-Pin Connector Type Honda LVC .5±0.5 2.3 178.8±0.275.2 12. -1.0 47 12.5 max (wire routing area) 70.1W" Standard Notebook Panel with CCFL Inverter Integration (Panel Front View) 84.5±1.5 60.6 max 8.2±0.5 Notes: 1) When LCD panel is viewed from the front.0mm typical clearence between bottom of LCD panel and inverter.0±0.5 Units = mm 73.1”W Integrated Inverter Placement 171. the Inverter connectors are rear facing.0±0.0±0.0+0. March 29.5±0.0±0.0.3 Active Area Center 138. 0±0.1±0. March 29.5±0.8. 2005 .0±0.3 216.5 145.0±1. -2. 20-Pin Connector Type: HondaLVC-D205FYG or Equivalent 2) 2.0.0mm typical clearence between bottom of LCD panel and inverter.3" Standard Notebook Panel with CCFL Inverter Integration (Panel Front View) 88. the Inverter connectors are rear facing.5 95.5 typ 217.1 max 48 13.0±0.0±0.5 +0.3 142.5 203.5 2.0 Active Area Center Point 13.5 64±0.3” Integrated Inverter Placement 216.5 max (wire routing area) Notes: 1) When LCD panel is viewed from the front.3 units = mm 284.3 212. 2005 2) 2.5 99.5 84.0mm typical clearence between bottom of LCD panel and inverter.-2.5 8.5 max (wire routing area) 108.3 150.0. . 20-Pin Connector Type Honda LVC .15±0. the Inverter connectors are rear facing.1" Standard Notebook Panel with CCFL Inverter Integration (Panel Front View) 2.3 59.0±0.8±1.4 14.15±0.0 typ 228.0 225.5 49 14.8 max 213.Units = mm 299.0 Wire Routing Area Notes: 1) When LCD panel is viewed from the front.D205FYG or Equivalent March 29.5±0.3+0.5±0.5 145.0±0.3 Active Area Center Point 228.6±0.1” Integrated Inverter Placement 221. 4±0. 2) 1.1"W Standard Notebook Panel with CCFL Inverter Integration (Panel Front View) 117.8.5 194.3 187.5 145.5±0.2±0.3 160.5 Units = mm 85.5 50 14. the Inverter connectors are rear facing. 2005 .0±0. March 29.5±0.5mm minimum clearence between bottom of LCD panel and inverter.3 Active Area Center 205.0±0.5±0.5 14.5 319.6±0.9±0.5 93.3±0.5 max (wire routing area) 82.1”W Integrated Inverter Placement 199.8 max Notes: 1) When LCD panel is viewed from the front.F1-K12SL-VF or Equivalent 2.5 12-Pin Connector Type: JAE . 5 max (wire routing area) 79.-2.0.0±0.0 Notes: 1) When LCD panel is viewed from the front.0±0.6 max 229.5 93.6 317.5 108.2±5.0” Integrated Inverter Placement 241.7 15. the Inverter connectors are rear facing.8.7±0.3 15.35±0.7 51 117.5 237.3 Units = mm 159. 2005 .0 145.1±1. March 29.2±0. 20-Pin Connector Type Honda LVC .3 Active Area Center Point 242.0mm typical clearence between bottom of LCD panel and inverter.65±0.3±0.0" Standard Notebook Panel with CCFL Inverter Integration (Panel Front View) 2.0 typ 242.8+0.D205FYG or Equivalent 2) 2. 2±0.3 232.5 255.D205FYG or Equivalent Notes: 1) When LCD panel is viewed from the front.0±0.5 209.5±0.5 124.5±0.7 246.5 221.3 Units = mm 15.75±0. 2) 2.5 10.5 240. 2005 .7±0.4±0. the Inverter connectors are rear facing.0mm typical clearence between bottom of LCD panel and inverter.0 max 99.3 234.0±0.2±0.2 20-Pin Connector Type Honda LVC .4"W Standard Notebook Panel with Inverter Integration (Panel Front View) 2.15±0.3 22.6 max 227.Diameter 3.0±0.8±0.5 Active Area Center 172.65±0.0±0.6±0.5 136.2±0.6±0.0±0.5 344.5 216.0 min CCFL Wire Routing Area (Hatch) 113.4” W Integrated Inverter Placement 52 2 .0 max 15.8.5 336.5 221.5 118.5 max 1 20 CCFL Inverter 8. March 29.5 220. 8 382.0mm typical clearence between bottom of LCD panel and inverter.0 17. March 29.3 240.2±0.2±0.5 2.1±0.5 typ 245.5 137.0±0.3 Active Area Center 244.2±0.25±0. 2005 . the Inverter connectors are rear facing.0±1.8±0.5 Units = mm 106.0 +0.0"W Standard Notebook Panel with CCFL Inverter Integration (Panel Front View) 161.0” W Integrated Inverter Placement 53 17.0 191.5 145.0±0.5 max (wire routing area) 90.D205FYG or Equivalent Notes: 1) When LCD panel is viewed from the front.5 Wire Routing Area 20-Pin Connector Type Honda LVC .0.8.3 229.5 max 237. 2) 2. -1. 1.1.5 Nap – Minor Defect (Contamination in front or rear polarizer layers) This refers to fibrous material such as lint/hair within the display. 9. 9. in some cases.1.11 Line (Row / Column) Out – Major Defect During operation the unit displays one or more horizontal or vertical lines in black. 9.8 Rub – Minor Defect This is an unevenness. Those screen cosmetics for evaluation are defined below. red. 9. Defects are typically visible with the panel turned off but may.4 White Lines – Minor Defect (Contamination in front polarizer layer) Lines that appear light in the display pattern and vary/remain unchanged in terms of size and shade regardless of the adjustment of brightness or viewing angle. or shiny spot.1.1. green. on the display surface where the anti-glare coating has been damaged or removed.1. Defects are typically visible with the panel turned off but may. it is most often bright and will be a particular color.1.6 Polarizer Scratches – Minor Defect Polarizer (outside) surface.12 Glass Crack – Major Defect Refers to a fracture in a glass layer of the display 54 .9 Pixel Failure (Stuck On) – Minor Defect within spec.0 Screen Cosmetic Evaluation: 9. Defects are typically visible with the panel turned off but may. Defects are typically visible with the panel turned off but may. 9.3 White Spots – Minor Defect (Contamination in front polarizer layer) . be noticeable in black or 32 gray screens. in some cases. Defects are typically visible with the panel turned off but may.10 Pixel Failure (Stuck Off) – Minor Defect within spec. 9.1 Black Spots – Minor Defect (Contamination in front polarizer layer) Spots that appear dark in the display pattern and vary/remain unchanged in terms of size and shade regardless of the adjustment of brightness or viewing angle.Spots that appear light in the display pattern and vary/remain unchanged in terms of size and shade regardless of the adjustment of brightness or viewing angle. Major Defect outside of spec limits This is a failure of the pixel on a TFT display. in some cases.1.1.1 Display screen cosmetic evaluation limits are established by the PC maker and the LCD supplier. 9. be noticeable in black or 32 gray screens. 9. 9.1. in some cases. be noticeable in white or 32 gray screens 9.1. This refers to an actual scratch on the 9. Major Defect outside of spec limits This is a failure of the pixel on a TFT display.1. be noticeable in white or 32 gray screens.7 Polarizer Dents – Minor Defect Dents are small indentations or impressions on the Polarizer (outside) surface. it is most often black and will be seen only on 32 gray or colored backgrounds.March 29. be noticeable in white or 32 gray screens. in some cases. or blue patterns.2 Black Lines – Minor Defect (Contamination in front polarizer layer) Lines that appear dark in the display pattern and vary/remain unchanged in terms of size and shade with the adjustment of brightness or viewing angle. 9. 2005 9. 13 White or black spots – Minor Defect within spec. 9. or a column only visible during panel operation. red. black.2 Display screen cosmetic defects may be weighted by their location. 55 . black. green. or other irregularities in the display pattern. green.1. Major Defect outside of spec limits This caused by the displacement of spacers and liquid crystal (LC) material that result in a visible discoloration in the shape of wavy lines. or blue screen patterns 9. 9. or blue screen patterns. white. and no light is visible along the edges of the LCD.March 29. Major Defect outside of spec limits Refers to white or black spots visible within the glass cell only visible during panel operation.4” 17. Typically caused by a crack in the plastic LGP portion of the backlight assembly. ½ moons.1.1. Major Defect when CCFL light leak occurs within the CR10:1 viewing angle. red. The drawings below define these screen locations (quadrants).14 Etch / TFT – Major Defect Usually reflected as a failure of a part of a single row.0” Note: A clear plastic sheet with the display quadrants outlined can be used as a reference for checking defect location.1.Minor Defect within spec.1. Display Quadrants 1 2 Graphics Region 5 LCD Size 4 Graphics Region Dimensions 6” x 4” 7” x 5” 8” x 6” 3 12” – 13. 9.1.15 Backlight – Major Defect Backlight does not operate.9” 14” – 15.16 LGP (Light Guide Pipe) – Major Defect Panel operates but white scratch like lines are visible seen from an angle. 32 gray. 2005 9. or black spots that show up in all color display patterns. spots. 9. 9.18 Light Leak – Minor Defect CCFL light leak at the edges of the screen outside of CR 10:1 viewing angles.17 Pooling / Ripple . circles (Newton Rings). Videotext is barely perceptible on the screen. 4 mm L > 5. Defect Type White / Black Spots (Contamination in/on front polarizer layer) White / Dark Lines & Nap (Contamination in/on front polarizer layer) Polarizer Scratch Polarizer Scratch Polarizer Dent Polarizer Dent Newton Ring (Cell Internal) Newton Ring (Cell Internal) Rub Defect Rub Defect Glass Crack Polarizer delamination (Bubble) Total number for all major & minor defects Panel Type New panel or post reliability stress test New panel or post reliability stress test New panel Post reliability stress test New panel Post reliability stress test New panel or post reliability stress test New panel or post reliability stress test New panel Post reliability stress test New panel or post reliability stress test New panel or post reliability stress test New panel or post reliability stress test Reject Size (mm) Reject Count (n) Dia > 0.4 mm L > 5. 3 2 2 2.March 29.0 mm n => D > 0. 3 2.10 mm n> Notes 1.5 mm n> D > 0.7 mm L > 1.0 mm n => W > 0.7 mm n => W > 0.5 mm n> Dia > 20 mm n => Dia > 20 mm n => Not Allowed Not Allowed Not Allowed >0. 56 . 3 2. 2005 9. 3 2 2 2 2 2. Note 3: Inspected with both a white and 32 level gray screen pattern. 3 2 Defect Severity Minor Defect Minor Defect Minor Defect Minor Defect Minor Defect Minor Defect Major Defect Major Defect Minor Defect Minor Defect Major Defect Minor Defect n => All Defect Note 1: White/black spots are inspected within the panel viewing angles only Note 2: Inspected with the panel turned off.0 mm n => W > 0.3 Cosmetic Visual Defects: NOTE: Functional defects take precedence over visual. 2005 9.60.30 < Dia ≤ 0. n > 0.30. NOTE: Functional defects take precedence over visual defects Defect Type Bright Pixels – Random Bright Pixels – Green Bright Pixels – 2 Adjacent Bright Pixels – 2 Adjacent Green Dark Pixels – Random Dark Pixels 2 Adjacent Total Bright and Dark Pixels Distance between Dark Pixels Bright Pixel (Green sub-pixel) Distance between bright pixel defects: Dark Pixel Distance between Dark Pixels Bright adjacent pixels Dark adjacent pixels Etch / TFT Light leak Static Pooling/ Ripple Dynamic Pooling/Ripple < 2 sec after cover movement stops No pooling/ripple during system operation Total number of all Major and Minor Defects Panel Type New panel New panel New panel New panel New panel New panel New panel New panel Post reliability stress test Reject Size (mm) Reject Count (n) n> n> n> n> n> n> n> < 5mm. n > < 15 mm >15 mm n> n> Notes All Quadrants All Quadrants All Quadrants All Quadrants All Quadrants All Quadrants Defect Severity Major Defect Major Defect Major Defect Major Defect Minor Defect Minor Defect All Major Defect Quadrants Minor Defect Major Defect Post reliability stress test Major Defect Post reliability stress test Post reliability stress test Post reliability stress test Post reliability stress test New panel or post reliability stress test New panel or post reliability stress test New panel or post reliability stress test New panel or post reliability stress test Dia > 0.March 29.60. n > > 5 mm. n> n> n> Not Allowed Not Allowed None allowed All Quadrants All Quadrants All Quadrants Minor Defect Minor Defect Major Defect Minor Defect All Major Defect Quadrants Major Defect Major Defect Major Defect n> New panel or post reliability stress test n> All Defects 57 . n > 0.60. n > Dia > 0. n> 0.4 Screen Functional Defects: Evaluated in Black.10 < Dia ≤ 0. n> 0. and 32 Gray screens. n > < 5 mm. Red. Green.10 < Dia ≤ 0. n> > 5 mm.60.30. Blue. White.30 < Dia ≤ 0. 50 Hz G2/Hz=0. = 30min. = 30min.Non-Operating Vibration . 80 durometer plunger. Test Cycles = 160 58 .5 Grms. 30 min/side.High Temp. The Limits for testing will be dependent on the system or fixture used in the tests. Dynamic. This testing may be performed in a notebook system or on stand alone panels. Ramp ≤20°C/min. Cycle . Stand alone LCD panel testing requires that test fixtures be designed and correlated with system test results. Non-Operating.March 29. +Z.= 0°C. Storage Life . 2005 10. +Y.Low Temp.007. Storage Life Torsion Test High Temp & High Humidity Operating Life RCF (Repetitive Compressive Force) Shock . -Z) 3 Shocks per Direction 1. 500Hz G2/Hz=0. -Y.0 Panel Reliability: LCD panel must be qualified thru environmental and reliability testing. The reliability tests shown below are typical of those necessary for panel qualification/approval. PSD Spectrum Break Points. 2. 222 Hz G2/Hz=0. Duration at Temp. Non-Operating. 250 Hours Temp. Test Cycles = 160 -25°C to +65°C. Half Sine Wave ± 3 Axis ( +X. Humidity 95% ( Non-Condensing).NonOperating Temp.Non-Operating Low Temp. Dynamic. Operating Life .= +50°C.0018. Duration at Temp.= +65°C.1 Sample LCD Panel Stand Alone Environmental and Reliability Test Plan Environmental Test Operating Life . Dynamic. Cycle Operating Temp. 10. The sample plan shown below is an example only and is not meant to define a standard test plan. -X.= +40°C.0 ms.NonOperating Test Conditions Temp. 250 Hours 20mm. 250 Hours Panel Twisted to defined limits Temp. 250 Hours Temp.= -25°C. 5000 cycles 220g’s.316. 250 Hours Temp. High Temp. 26 Hz G2/Hz=0.0001 0°C to+40°C. Ramp ≤20°C/min.