Solutions C5

120CHAPTER 5 5.1 (a) D CP C Q' S = DC R = D'C Q (b) D C Q' s = (D' + C')' =D C R = (D + C')' =D' C Q (c) D CP C Q' R = ((DC)' C)' =DC + C' = (D + C') = (D'C)' S = (DC)' =D' + C' Q 5.2 J K 0 1 s C 2x1 mux D = JQ' + K'Q Q Y D Q 5.3 For T – Flip-Flop Q (t + 1) = TQ′ + T′Q = T ⊕ Q Q′ (t + 1) = [T ⊕ Q]′ = T′Q′ + TQ 5.4 (a) PN 0 0 1 Q(t + 1) 0 Q(t) 1 0 0 1 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 121 1 1 Q′(t) (b) Q(t + 1) = PN′ + PQ(t)′ + N′Q(t) (c) Q(t) 0 0 1 1 (d) Q(t + 1) 0 1 0 1 P 0 1 N 1 0 5.5 State table is also called as transition table. The truth table describes a combinational circuit. The state table describes a sequential circuit. The characteristic table describes the operation of a flip-flop. The excitation table gives the values of flip-flop inputs for a given state transition. The four equations correspond to the algebraic expression of the four tables. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 122 5.6 x y xy' + xA D Q A, z C B D Q CP (b) A(t+1) = xy' + xB B(t+1) = xA + xB' z=A (c) 00, 01 00, 01 Present state Output Inputs Next state 00 0 11 01 0 A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x y 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 A 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 B 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 1 z 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 00, 01 10 00, 01 10,11 10 1 10, 11 11 1 10, 11 5.7 State Table: Q(t) x y Q(t + 1) Diff. 0 0 0 0 State Diagram: 0 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 123 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 1 0 0 1 1 0 1 1 1 0 1 0 0 1 Diff. = Q(t)′(x ⊕ y) + Q(t)(x ⊕ y)′ = Q(t) ⊕ x ⊕ y 5.8 A counter with a repeated sequence of 00, 01, 10. Present state Next state FF Inputs T A TB 0 1 1 1 1 1 0 1 00 01 A B A B 0 0 1 1 0 1 0 1 0 1 0 0 0 0 0 0 TA = A + B TB = A' + B Repeated sequence: 01 10 00 11 10 5.9 (a) A(t) B(t) x A(t + 1) B(t + 1) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. 124 0 0 0 0 1 1 1 1 A(t + 1): 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 0 1 0 0 0 1 0 1 1 A(t + 1) = A′x + AB′ B(t + 1): B(t + 1) = B′x′ + AB (b) 5.10 (a) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. Mano. M.D. Ciletti, Copyright 2012, All rights reserved. Copyright 2012. Ciletti. 8. 4. 14) = A x′y′ + Bxy′ + A′Bx + A′B′y′ B(t + 1): Σ(2. 7. 3. 12. 6.125 (b) State Table: A(t) B(t) x 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 y 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A(t + 1) 0 1 1 0 0 1 1 0 0 0 1 0 0 1 1 1 0 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0 B(t + 1) 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 z 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 (c) A(t + 1): Σ(0. All rights reserved. . 2. Mano. M. 7) Digital Design With An Introduction to the Verilog HDL – Solution Manual. M.D. 5. Copyright 2012. .D. 10 → c. Mano. 11 → d State Input Output (b) Present A (t ) 0 0 0 0 1 1 1 1 OR Present 00 01 01 10 x=0 00 00 00 00 Next x=1 01 01 10 10 O/p x=0 0 1 1 1 a b d a b d c a d 1 1 0 1 1 1 0 0 1 0 0 1 0 0 0 1 0 0 State Input Next B(t) x A(t + 1) 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 State Output B(t + 1) z 0 0 0 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 x=1 0 0 0 0 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M.126 = A′Bx′ + Axy + A′B′x /. 01 → b. M.00 (a) 00 → a. Ciletti. All rights reserved. M.127 (c) Present State Input A(t) B(t) x 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 JA = A JB = KA = 1 Next State A(t + 1) B(t + 1) 0 0 1 0 0 0 1 0 0 1 0 1 - z 0 1 0 KA JB 0 0 0 0 1 0 1 0 0 .JA KB 0 1 1 0 =x KB: KB = x′ z: = Bx′ 5. All rights reserved. Mano. . Copyright 2012.. M. Ciletti..D..12 Present state a Next state 0 1 f b Output 0 1 0 0 Digital Design With An Introduction to the Verilog HDL – Solution Manual. 14 State a b c d e Assignment3 00001 00010 00100 01000 10000 Next State Output x=1 x=0 x=1 00001 00010 0 00100 01000 0 00001 01000 0 10000 01000 0 00001 01000 0 Present State ABCDE x=0 a 0 00 01 b 0 00 10 c 0 01 00 d 0 10 00 e 1 00 00 5.D. Copyright 2012. M.128 b D F G d a g a f b g d 0 1 1 0 0 0 1 1 5. All rights reserved.15 0 0 0 1 1 Present State (Q) Input (T) 0 0 0 1 1 0 1 1 Q(t + 1) = T ⊕ Q(t) Next State (Q) 0 1 1 0 5.13 (a) State Input Output a f a f a f g b g b a 0 1 0 1 0 0 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 0 (b) State a b a b a b g b g b a Input 0 1 0 1 0 0 1 0 1 1 1 Output 0 0 0 0 0 1 0 1 0 0 0 5. Ciletti. . Mano.16 (a) DA = Ax′ + Bx DB = A′x + Bx′ Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. M. Thereafter. the output is the complement of the input. at which time the output is 1. All rights reserved. Ciletti.D. Copyright 2012. Mano. . in state 1: output = input'. The state diagram has two states.12 Present state A B 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Input x 0 1 0 1 0 1 0 1 Next state A B 0 0 0 1 1 0 1 1 0 1 1 1 0 0 1 0 A Bx A 0 m4 m5 m7 B 00 m0 01 m1 11 m3 10 m2 1 m6 1 1 x 1 1 DA = Ax' + Bx Bx A 0 m4 m5 B 00 m0 01 m1 11 m3 10 m2 1 m7 1 m6 1 1 A 1 x DB = A'x + Bx' (b) DA = A'x + Ax' DB = AB + Bx' Present state A B 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Input x 0 1 0 1 0 1 0 1 Next state A B 0 1 0 1 1 0 1 0 0 1 1 0 0 0 1 1 A Bx A 0 m4 m5 B 00 m0 01 m1 11 m3 10 m2 1 m7 1 m6 1 1 x 1 DA = A'x + Ax' Bx A 0 m4 m5 B 00 m0 01 m1 11 m3 10 m2 1 m7 m6 1 1 x 1 A 1 DB = AB + Bx' 5. In state 0: output = input.17 The output is 0 for all 0 inputs until the first 1 occurs. M. Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. . Mano. Ciletti.130 x clk D Q y Present state Next state Output reset_b Input 0/0 A 0 0 1 1 x 0 1 0 1 A 0 1 1 1 y 0 1 1 0 reset_b 1 1/1 0/1 1/0 0 DA = A + x y = Ax' + A'x 5.18 Binary up-down counter with enable E. Copyright 2012.D. All rights reserved. M. Present Next state Input state AB x AB 00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11 01 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 00 11 01 01 01 01 10 10 10 01 11 11 11 11 11 Flip-flop inputs JA KA JB KB 0 x 0 x 1 x 0 x 0 x 0 x 0 x 1 x x 0 x 0 x 1 x 0 x 0 x 0 1 0 x1 0 0 1 1 x x x x 1 1 x x x x x x x x x x 0 0 1 1 0 0 1 1 0 0 1 1 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. 11. C. 13. 111. P5. All rights reserved. Ciletti. M. 12. 14. x) = Σ (10. Present Next Input Output state state y ABC x ABC 000 0 011 0 000 1 100 1 001 0 001 0 001 1 100 1 010 0 010 0 010 1 000 1 011 0 001 0 011 1 010 1 0 100 010 0 1 100 011 1 d(A. 15) Digital Design With An Introduction to the Verilog HDL – Solution Manual. B.131 Ex AB 00 m4 m5 m7 E 00 m0 Cx 10 m2 C 00 m0 01 m1 11 m3 AB 00 01 m1 11 m3 10 m2 1 m6 x m4 m5 x m7 x m6 x 01 m12 m13 1 m15 m14 01 B 11 A 10 m8 x m12 x m13 x m15 m14 B 11 A 10 m8 x m9 x x x m11 x m10 1 m9 m11 m10 x x x 1 x KA = (Bx + B'x')E x JA = (Bx + B'x')E Ex AB 00 m4 m5 m7 E 00 m0 Ex 10 m2 E 00 m0 01 m1 11 m3 AB 00 01 m1 11 m3 10 m2 1 m6 1 x m14 x m4 m5 x m7 x m6 x 1 m14 01 11 A 10 m8 x m12 x m13 x m15 01 E 11 A 10 m8 m9 m12 m13 1 m15 E x m9 x x m11 x m10 1 m11 1 m10 1 x JB = E 1 x x x KB = E x x 5.D. Copyright 2012. Mano. .19): 101.19 (a) Unused states (see Fig. 110. D.132 Cx AB 00 m4 m5 C 00 m0 Cx 10 m2 C 00 m0 01 m1 11 m3 AB 00 01 m1 11 m3 10 m2 1 m7 1 m6 1 m4 m5 m7 m6 01 m12 m13 m15 m14 01 B 11 A 10 m8 1 m12 m13 1 m15 m14 B 11 A 10 m8 x m9 x x m11 x m10 x m9 x 1 x m11 x m10 x x DA = A'B'x x 1 x x x DB = A + C'x' + BCx C Cx 10 m2 Cx AB 00 m4 C 00 m0 00 m0 01 m1 11 m3 AB 00 01 m1 11 m3 10 m2 1 m5 m7 m6 1 1 1 m4 m5 m7 1 m6 01 m12 m13 m15 01 B 11 A 10 m8 m12 1 m13 1 m15 m14 m14 B 11 A 10 m8 x m9 x 1 x m11 x m10 x m9 x x m11 x m10 x x x x y = A'x x x DC = Cx'+ Ax +A'B'x' The machine is self-correcting.. 111 0/0 1/0 101 0/0 1/0 1/0 011 010 110 0/0 Digital Design With An Introduction to the Verilog HDL – Solution Manual. i. M. M. the unused states transition to known states.e. All rights reserved. Ciletti. . Mano. Copyright 2012. Mano.D. All rights reserved. 5. Ciletti.133 (b) With JK flip=flops. Copyright 2012. Flip-flop inputs JA KA JB KB JC KC 0 1 0 1 0 0 0 0 x x x x x x x x x x 1 1 1 0 0 0 x x x x 1 1 x x x x 0 1 1 0 x x 1 0 x x 0 0 x x 0 1 x x 0 1 x x 0 1 x x JA = B'x KA = 1 JB = A + C'x' KB = C' x+ Cx' JC = Ax + A'B'x' KC = x y = A'x The machine is self-correcting because KA = 1. M. . the state table is the same as in (a). M.20 DA = (A ⊕ B) + Bx DB = (x ⊕ A ⊕ B) Digital Design With An Introduction to the Verilog HDL – Solution Manual. 5. All rights reserved. 3. M. . Copyright 2012. 7) = AB′ + Bx + A′B Digital Design With An Introduction to the Verilog HDL – Solution Manual.134 Present State A(t) B(t) 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Input Next State x A(t + 1) B(t + 1) 0 0 1 0 0 1 1 1 0 1 1 1 0 0 1 1 DA 1 0 1 0 1 0 0 1 DB 0 0 1 1 1 1 0 1 1 0 1 0 1 0 0 1 DA = Σ(2. Ciletti. 4.D. Mano. M. always @ (posedge clk. clear). #10). the statements assocated with the always keyword execute repeatedly. 7) = B′x′ + A′x′ + ABx =x⊕A⊕B 5. subject to timing control (e. reg clk. preset. clear. Copyright 2012. endmodule module t_DFF (). negedge clear ) if (preset == 0) Q <= 1'b1. 2. M. 5. RegB = 125 (b) RegA = 125.21 The statements associated with an initial keyword execute once. 5. Mano. input D. in sequence. RegB = 50 Note: Text has error. M. negedge preset. All rights reserved. reg D.24 (a) module DFF (output reg Q.135 = (A ⊕ B) + Bx DB = Σ(0. preset. Ciletti.23 20 40 60 80 100 120 140 160 (a) RegA = 125.D. with the activity expiring after the last statment competes execution. with RegB = 30 at page 526).g. else if (clear == 0) Q <= 1'b0. else Q <= D. . Digital Design With An Introduction to the Verilog HDL – Solution Manual. clk. 4.22 (a) (b) t 0 5. wire Q. M. preset. 2'b01: Q <= D2. in(!t D. D.D.25 module Quad_Input_DFF (output reg Q. wire Q. initial begin clk = 0. #100 D = 0. always @ (posedge clk. Copyright 2012. s0}) 2'b00: Q <= D1. M. $lA. else case ({s1. else Q <= D. clk. D3. negedge reset_b) if (reset_b == 1'b0) Q <= 0. 2'b11: Q <= D4. s0. #200 D = 1. $lear+2 always @ (posedge clk) if (preset == 0) Q <= 1'b1. Digital Design With An Introduction to the Verilog HDL – Solution Manual. #80 clear = 1. . clear). Ciletti. clk. endcase endmodule module t_Quad_Input_DFF (). initial #160 $finish. D2. s1. else if (clear == 0) Q <= 1'b0. #10 D = 1. Mano. input D1. reset_b).136 DFF M0 (Q. All rights reserved. end initial fork #10 preset = 0. join endmodule Name clk preset clear D Q 0 60 120 (b) od!#e D?? 'o!t(!t re' @. 2'b10: Q <= D3. preset. forever #5 clk = ~clk. D4. #20 preset = 1. endmodule Name 0 60 120 clk preset clear D Q 5. #50 clear = 0. s1. s0 = 1. D3. D2. end #160 begin s1 = 1. forever #20 D4 = ~D4.26 (a) Q(t + 1) = JQ′ + K′Q When Q = 0. D4. s0. #4 reset_b = 1. s0 = 0. forever #5 clk = ~clk. end #120 begin s1 = 1. end join initial fork #2 reset_b = 1. clk. Q(t + 1) = K′ module JK_Behavior_a (output reg Q. D2. end #80 begin s1 =1. Q(t + 1) = J When Q = 1. end begin D4 = 0. s1. s0 = 0. forever #10 D3 = ~D3. forever #20 D2 = ~D2. clk. Quad_Input_DFF M0 (Q. K. CLK. All rights reserved. initial #350 $finish.137 reg D1. end begin D2 = 1. end #40 begin s1 = 0. D1. endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. join endmodule 5. reset_b).<< 0+ @ C< 02 e#se if (Q == 0) Q <= J.D. Mano. initial begin clk = 0. D3. always @ (posedge CLK. D4. Copyright 2012. #3 reset_b = 0. end initial fork begin s1 = 0. s0 = 1. input J. reset_b). M. Ciletti. negedge reset_b) if 'resetB. M. s0 = 0. reset_b. . end begin D3 = 0. end join initial fork begin D1 = 0. forever #10 D1 = ~D1. else Q <= ~K. s0. // Initialize to s0 #4 reset_b = 1. always @ (posedge CLK. clk. clk. J. initial #100 $finish. wire Q_a. K. end initial fork #2 reset_b = 1.16) module Mealy_Zero_Detector ( output reg y_out. #3 reset_b = 0. K = 0. JK_Behavior_b M1 (Q_b.27 // Mealy FSM zero detector (See Fig. endcase endmodule module t_Prob_5_26 (). reg [1: 0] state. next_state. reset_b). clk. K. input J. Copyright 2012. K. 5. J =0. K = 1. reg J. M. 2'b11: Q <= ~Q.138 (b) module JK_Behavior_b (output reg Q. parameter S0 = 2'b00. end #50 begin J = 1. end #30 begin J = 1. K = 1. reset_b.<< 0+ @ C< 02 e#se case ({J. Q_b. forever #5 clk = ~clk. J. input x_in. S2 = 2'b10. K = 1. negedge reset_b) if 'resetB. .D. Mano. reset_b). M. initial begin clk = 0. reset_b). All rights reserved. end #40 begin J = 0. reset ). end join endmodule Name clk reset_b J K Q_a Q_b 0 40 80 5. S3 = 2'b11. clock. #20 begin J= 1. 2'b10: Q <= 1. CLK. Ciletti. JK_Behavior_a M0 (Q_a. 2'b01: Q <= 0. K. S1 = 2'b01. K}) 2'b00: Q <= Q. Digital Design With An Introduction to the Verilog HDL – Solution Manual. K = 0. #10 t_x_in = 1. #30 t_x_in = 0. initial begin t_clock = 0. t_reset. if (x_in) next_state = S2. else next_state = S0. #100 t_x_in = 0. #160 t_x_in = 0. #70 t_x_in = 0. #54 t_x_in = 0. always @ (state. else next_state = S2. Mano. #52 t_x_in = 1. wire t_y_out. if (x_in) next_state = S1. else next_state = S0. t_x_in.D. forever #5 t_clock = ~t_clock. #70 t_x_in = 1. #50 t_x_in = 0. Mealy_Zero_Detector M0 (t_y_out. t_clock. #89 t_reset = 1.22. end S1: begin y_out = ~x_in. 5. reg t_x_in. #87 t_reset = 0. end initial fork t_reset = 0. Name t_clock t_reset state[1:0] t_x_in t_y_out 0 1 3 0 1 0 0 1 0 1 3 2 0 1 6 46 86 126 166 Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. else next_state = S0. x_in) // Form the next state case (state) S0: begin y_out = 0. t_clock. initial #200 $finish. Copyright 2012. end endcase endmodule module t_Mealy_Zero_Detector. t_reset).13 always @ (posedge clock. Ciletti. #40 t_x_in = 1. negedge reset) // state transition if (reset == 0) state <= S0. All rights reserved. if (~x_in) next_state = S0. join endmodule Note: Simulation results match Fig. #2 t_reset = 1. if (x_in) next_state = S3. end S3: begin y_out = ~x_in. else state <= next_state. #80 t_x_in = 1. #120 t_x_in = 1. #90 t_x_in = 1. M. end S2: begin y_out = ~x_in. . #170 t_x_in = 1. A). DFF M0 (A. end join endmodule 0 N ame 80 160 clk reset_ b x y A (b) module Prob_5_28b (output A. M. end #40 begin x = 1. w1. Copyright 2012. 2'b11: next_state = s1. y. clk. All rights reserved. y). x. end #60 begin x = 1. y = 1. endcase s1: case ({x. #3 reset_b = 0. reset_b). xor (w1. case (state) s0: case ({x. input x. endcase endcase end endmodule module t_Prob_5_28a (). x. M. always @ (state. else state <= next_state. #20 begin x= 1. y. 2'b01. clk. reset_b). parameter s0 = 0. // Initialize to s0 #4 reset_b = 1. next_state. y = 0. y = 1. negedge reset_b) if (reset_b == 0) state <= s0. clk. x. Prob_5_28a M0 (A. 2'b10: next_state = s1. end #70 begin x = 1. end #50 begin x = 0. xor (w2. always @ (posedge clk. Digital Design With An Introduction to the Verilog HDL – Solution Manual. Clock. 2'b10: next_state = s0. initial begin clk = 0. y = 1. Ciletti. reg x. end initial fork #2 reset_b = 1. input x. w2. . 2'b01. forever #5 clk = ~clk. assign A = state. y = 0. y}) 2'b00. reset_b. y. initial #350 $finish. reset_b). y = 0. reset_b). wire A. y = 0.D. y) begin next_state = s0.28 (a) module Prob_5_28a (output A. end #30 begin x = 0. Mano. y = 0. y. Clock. 2'b11: next_state = s0. s1 = 1. x =0. reg state.140 5. y}) 2'b00. end #80 begin x = 0. A_b. wire A_a. y = 1. M. // Initialize to s0 #4 reset_b = 1. reset_b. y = 0. All rights reserved. #20 begin x= 1. end #50 begin x = 0. clk. end #40 begin x = 1. #3 reset_b = 0. // Initialize to s0 #4 reset_b = 1. y = 0. end #30 begin x = 0. x =0. Mano. y. clk. clk. y. y = 1. reg x. Prob_5_28b M1 (A_b. initial #350 $finish. clk. reset_b). else Q <= D. y = 1. initial begin clk = 0. Prob_5_28b M0 (A. x. reg x. y. Prob_5_28a M0 (A_a. y = 0. initial #350 $finish. y = 0. always @ (posedge Clock. x =0. #3 reset_b = 0. end #70 begin x = 1.141 endmodule module DFF (output reg Q. reset_b). y. y = 0. module t_Prob_5_28c (). y = 0. end #80 begin x = 0. #20 begin x= 1. end initial fork #2 reset_b = 1. reset_b. . wire A. end #30 begin x = 0. y = 0. negedge reset_b) if (reset_b == 0) Q <= 0. Ciletti. end #40 begin x = 1. Copyright 2012. x. end Digital Design With An Introduction to the Verilog HDL – Solution Manual. initial begin clk = 0. Clock. y = 1. input D.D. M. reset_b). forever #5 clk = ~clk. end initial fork #2 reset_b = 1. clk. endmodule module t_Prob_5_28b (). x. end #60 begin x = 1. y = 0. y. reset_b). forever #5 clk = ~clk. end join endmodule Name Clock reset_b x y A 0 60 120 180 (c) See results of (b) and (c). parameter s0 = 3'b000. s2 = 3'b010. y = 1. y_out = 0. s3 = 3'b011. always @ (posedge clock. y = 1. x_in. y_out = 0. end #80 begin x = 0. s4 = 3'b100. y = 0. s1 = 3'b001. clk. M. y_out = 0. // Initialize to s0 #4 reset_b = 1. . y_out = 1. initial begin clk = 0. end s1: if (x_in) begin next_state = s4. Prob_5_29 M0 (y_out. end s2: if (x_in) begin next_state = s0. endcase end endmodule module t_Prob_5_29 (). end default: next_state = 3'bxxx. end else begin next_state = s1. next_state. end else begin next_state = s1. clk. case (state) s0: if (x_in) begin next_state = s4. end else begin next_state = s3. y_out = 0. M. y_out = 1. Copyright 2012. y_out = 1. negedge reset_b) if (reset_b == 0) state <= s0. end #70 begin x = 1. forever #5 clk = ~clk. reg [2: 0] state. reg x_in. wire y_out. end #60 begin x = 1. Mano.29 module Prob_5_29 (output reg y_out. next_state = s0. end s3: if (x_in) begin next_state = s2. reset_b). y_out = 0. y_out = 0. end else begin next_state = s2. x_in) begin y_out = 0. end join endmodule Name clk reset_b x y A_a A_b 0 60 120 180 5. clock. else state <= next_state. #3 reset_b = 0. input x_in. end else begin next_state = s2. All rights reserved. y_out = 1.142 #50 begin x = 0. end s4: if (x_in) begin next_state = s3. // Trace the state diagram and monitor y_out Digital Design With An Introduction to the Verilog HDL – Solution Manual. initial #350$finish. y = 0. always @ (state. reset_b). end initial fork #2 reset_b = 1. reset_b. Ciletti.D. Mano. M. // Drive s0 to s4 etc join endmodule 0 40 80 Name clk reset_b x_in state[2:0] y_out 3 1 4 3 2 0 4 2 120 0 4 Digital Design With An Introduction to the Verilog HDL – Solution Manual. All rights reserved. // Drive to s4 to s3 to s2 to s0 to s4 and loop #90 x_in = 0. Ciletti. M. Copyright 2012. // Drive from s0 to s3 to s2 and part #110 x_in = 1.D.143 x_in = 0. . // Drive from s0 to s3 to S1 and park #40 x_in = 1. B. with predictable outputs of the flip-flops that are affected by the inputs. F = 0. D = 1. D = 1.31 module Seq_Ckt (input A. M.30 A D B CLK C CLK E D Q CLK 5.D. B = 0. E = A || B. C = 0. end #40 begin B = 0. 5. end #20 begin A = 1. #10 B = 0. D= 0. Copyright 2012. F = 1. B = 1. #10 A = 0. F = 0. end #70 begin B = 1.144 5. #10 A = 1. E = 0. D = 1. E = 1. B = 0. C = 0. .32 initial begin enable = 0.33 Signal transitions that are caused by input signals that change on the active edge of the clock race with the clock itself to reach the affected flip-flops. F = 1. end initial fork enable = 0. #10 begin A = 0. end endmodule Note: The statements must be written in an order than produces the effect of concurrent assignments. Ciletti. C. D = 0. D = 1. always @ (posedge CLK) begin Q = E && C. #10 enable = 1. reg E. end join 5. F =1. B = 1. All rights reserved. end #50 begin B = 1. Conversely. E = 1. end #30 begin B = 1. C = 1. A = 1. B = 0. M. output reg Q). and the outcome is indeterminate (unpredictable). D = 1. end #60 begin B = 0. #10 B = 1. E = 0. E = 1. CLK. D = 1. #10 B = 1. Digital Design With An Introduction to the Verilog HDL – Solution Manual. B = 0. A = 1. Mano. changes caused by inputs that are synchronized to the inactive edge of the clock reach stability before the active edge. E = 1. #10 B = 1. B = 0. F = 1. initial begin clock = 0. endmodule module t_JK_flop_Prob_5_34 (). J. Inverter M2 (K_bar. K = 0. assign y = select ? a: b. clk). clk). clk). J. input D.34 Note: Problem statement should refer to Problem 5. end initial fork #10 begin J = 0. clock). always @ (posedge clk) Q <= D. endmodule module Mux (output y. reg J. M. M. initial #500 $finish. end // toggle Q join endmodule Name 0 30 60 90 clock J K Q Digital Design With An Introduction to the Verilog HDL – Solution Manual. input J. K. wire K_bar. end // set q to 1 #40 begin J = 1. input y). forever #5 clock = ~clock. K = 1. end // toggle Q unknown #20 begin J = 0. K). All rights reserved. Mux M1 (D. Ciletti. endmodule module D_flop (output reg Q. assign y_bar = ~y. clock. K_bar.D. Mano. module JK_flop_Prob_5_34 (output Q. K. K = 0.145 5. . K. select). K = 0. D. JK_flop_Prob_5_34 M0 (Q. input a. end // no change #60 begin J = 0. b. Copyright 2012.5.2 instead of Fig 5. endmodule module Inverter (output y_bar. K = 1. end // set Q to 0 #30 begin J = 1. D_flop M0 (Q. Q). wire Q. in_y} == 2'b00) || ({in_x. in_y} == 2'b01)) next_state = 2'b00. M. in_y} == 2'b01)) next_state = 2'b00. in_y} == 2'b11)) next_state = 2'b11. in. in_y} == 2'b10) || ({in_x. 2'b01: if (({in_x. assign out_z = ((state == 2'b10) || (state == 2'b11)). reg [1:0] state.146 5. else if (({in_x. Ciletti. 2'b11: if (({in_x. in_y} == 2'b11)) next_state = 2'b10. in_y} == 2'b10) next_state = 2'b11. else if ({in_x. else next_state = 2'b01. next_state. clk. reset_b). in_y) case (state) 2'b00: if (({in_x. in_y} == 2'b00) || ({in_x. in_y} == 2'b10) || ({in_x. else if (({in_x. All rights reserved. in_y} == 2'b00) || ({in_x. 01 10. .11 10 1 10. in_y} == 2'b10) || ({in_x. else if (({in_x. z C B D Q CP (b) A(t+1) = xy' + xB B(t+1) = xA + xB' z=A (c) 00. endcase endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual.6: x y xy' + xA D Q A. else state <= next_state. always @ (posedge clk) if (reset_b == 1'b0) state <= 2'b00. 01 Present state Output Inputs Next state 00 0 11 01 0 A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 x y 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 A 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 B 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1 1 z 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 00. input in_x. 11 module Prob_5_35 (output out_z. in_y} == 2'b01)) next_state = 2'b00. in_y.35 From Problem 5. Mano.D. 11 11 1 10. 01 10 00. M. in_y} == 2'b11)) next_state = 2'b11. 01 00. Copyright 2012. 2'b10: if (({in_x. in_x. always @ (state. in_y} == 2'b01)) next_state = 2'b00. in_y} == 2'b00) || ({in_x. #160 {in_x. #20 reset_b = 1. clk. in_y} = 2'b11. in_y} = 2'b00. Prob_5_35 M0 (out_z. join endmodule // Remain in 2'b00 // Remain in 2'b00 // Transition to 2'b01 // Transition to 2'b00 // Transition to 2'b01 // Transition to 2'b00 // Transition to 2'b01 // Transition to 2'b10 // Transition to 2'b00 // Transition to 2'b01 // Transition to 2'b10 // Transition to 2'b00 // Transition to 2'b01 // Transition to 2'b10 // Transition to 2'b11 // Remain in 2'b11 // Remain in 2'b11 Digital Design With An Introduction to the Verilog HDL – Solution Manual. in_y} = 2'b11. in_y. #50 {in_x. M. in_y} = 2'b01. in_y} = 2'b11. end initial fork reset_b = 0. #190 {in_x. in. in_y} = 2'b00. in_y} = 2'b11. reset_b. #230 {in_x. in_y} = 2'b01. All rights reserved. reset_b). in. in_y} = 2'b01. in_y} = 2'b11. in_x. initial begin clk = 0. in_y} = 2'b11. #180 {in_x. #170 {in_x. clk. M. #110 {in_x. #130 {in_x. wire out_z. . #220 {in_x. #120 {in_x. forever #5 clk = ~clk.147 module t_Prob_5_35 (). in_y} = 2'b11. in_y} = 2'b11. Ciletti. in_y} = 2'b11. #140 {in_x. in_y. #150 {in_x. in_y} = 2'b10. #60 {in_x. #200 {in_x. in_y} = 2'b10.D. #90 {in_x. in_y} = 2'b00. reg in_x. #210 {in_x. Mano. #70 {in_x. initial #250 $finish. Copyright 2012. or (T_A. B. B_b. Copyright 2012. reset_b). reset_b). always @ (posedge Clock.. Clock. e = 3'b100. always @ (state. reset_b). reset_b. B). next_state = a. B. P5. M.36 Note: See Problem 5. input T. g = 3'b110.148 5. A. reset_b).. #4 reset_b = 1. always @ (posedge clock. parameter a = 3'b000. f = 3'b101. A_b.37 module Problem_5_37_Fig_5_25 (output reg y. T_flop M0 (A. initial begin Clock = 0. join endmodule Name Clock reset_b A B 0 30 60 90 5. output QB. next_state. wire A.8 module Problem_5_36 (output A.8 (counter with repeated sequence: (A.D. negedge reset_b) if (reset_b == 0) Q <= 0. 00 . input Clock. T_A. else state <= next_state. d = 3'b011. 01. b = 3'b001. x_in) begin y = 0. end initial fork #2 reset_b = 1. #3 reset_b = 0. // See Fig. Mano. or (T_B. reg [2: 0] state. Clock. Problem_5_36 M0 (A. reset_b). reset_b). Digital Design With An Introduction to the Verilog HDL – Solution Manual. reg Clock. M. clock. T_flop M1 (B. 10. All rights reserved.. . else if (T) Q <= ~Q. Clock. B). input x_in. initial #350$finish. B. A_b. endmodule module T_flop (output reg Q. forever #5 Clock = ~Clock. B) = 00. Clock. endmodule module t_Problem_5_36 (). c = 3'b010. assign QB = ~ Q. T_B. Ciletti. negedge reset_b) if (reset_b == 0) state <= a. e = 3'b100. end else begin y = 1. Digital Design With An Introduction to the Verilog HDL – Solution Manual. negedge reset_b) if (reset_b == 0) state <= a. else next_state = d. b = 3'b001. next_state = f. c = 3'b010. if (x_in == 0) next_state = a. Ciletti. if (x_in == 0) next_state = c. endcase end endmodule module Problem_5_37_Fig_5_26 (output reg y. next_state = e. end else begin y = 1. next_state. next_state = f. . Mano.14 case (state) a: begin y = 0. always @ (posedge clock. end e: f: g: default: next_state = a. next_state = f. end if (x_in == 0) begin y = 0. reset_b). reg [2: 0] state. end else begin y = 1. else next_state = b. input x_in. end if (x_in == 0) begin y = 0. else state <= next_state. end if (x_in == 0) begin y = 0. else next_state = d. M. next_state = f. Copyright 2012. parameter a = 3'b000. end if (x_in == 0) begin y = 0. end b: c: d: begin y = 0. end begin y = 0. if (x_in == 0) next_state = a. next_state = a. end else begin y = 1. All rights reserved. d = 3'b011. next_state = a. clock. M. next_state = g.D. .. M. reset_b). end else begin y = 1.... #170 x_in = 1.. wire [2: 0] state_25 = M0. Digital Design With An Introduction to the Verilog HDL – Solution Manual. reg x_in. Mano. #4 reset_b = 1. next_state = a. reset_b). end if (x_in == 0) begin y = 0. forever #5 clock = ~clock. end if (x_in == 0) begin y = 0. end else begin y = 1. #20 x_in = 1.. #160 x_in = 0. y_Fig_5_26. All rights reserved. dea #120 x_in = 1.. #2 reset_b = 1.. clock. x_in. Ciletti. initial #350 $finish. x_in. reset_b. #250 x_in = 1. #240 x_in = 0.. . Copyright 2012. clock. // abdf. e: default: endcase end endmodule module t_Problem_5_37 ().state. next_state = d. wire [2: 0] state_26 = M1. Problem_5_37_Fig_5_26 M1 (y_Fig_5_26. end begin y = 0. else next_state = d. Problem_5_37_Fig_5_25 M0 (y_Fig_5_25.. clock. // abded.. M. end initial fork x_in = 0..ea #220 x_in = 1. case (state) a: begin y = 0..fgf. end next_state = a. initial begin clock = 0. // abdf. end b: c: d: begin y = 0. if (x_in == 0) next_state = a. #200 x_in = 0. else next_state = d. x_in) begin y = 0.D. if (x_in == 0) next_state = c. abd . #3 reset_b = 0. join endmodule // abdef. next_state = a.. if (x_in == 0) next_state = a. else next_state = b. // abdea.. #100 x_in = 0.fga.. abd . next_state = e. #40 x_in = 0.. wire y_Fig_5_25. abdea #60 x_in = 1.state.ded.150 always @ (state. next_state = d.fga. s1 = 2'b01. #20 x_in = 1. s2 = 2'b10.38 (a) module Prob_5_38a (input x_in. reg x_in. initial #350$finish. #90 x_in = 0. else if (x_in == 1) next_state = s1. // Initialize to s0 #4 reset_b = 1. default: next_state = s0. initial begin clk = 0. end initial fork #2 reset_b = 1. Digital Design With An Introduction to the Verilog HDL – Solution Manual. forever #5 clk = ~clk. #2 x_in = 0. reg [1: 0] state. else if (x_in == 1) next_state = s0. always @ (posedge clock. parameter s0 = 2'b00. s1: if (x_in == 0) next_state = s1. reset_b). reset_b). else if (x_in == 1) next_state = s3. s2: if (x_in == 0) next_state = s3. Prob_5_38a M0 ( x_in. else if (x_in == 1) next_state = s2.D. clk. M. if (x_in == 0) next_state = s2. #80 x_in = 1. s3 = 2'b11. M.151 Name clock reset_b x_in state_25[2:0] state_26[2:0] y_Fig_5_25 y_Fig_5_26 0 110 220 0 0 1 3 4 1 3 4 1 3 1 3 5 6 0 4 0 3 3 5 5 3 6 0 1 4 0 1 4 4 5 3 5. clock. Ciletti. Copyright 2012. always @ (state. negedge reset_b) if (reset_b == 0) state <= s0. All rights reserved. s3: . x_in) begin next_state = s0. clk. else state <= next_state. case (state) s0: if (x_in == 0) next_state = s0. #60 x_in = 0. next_state. Mano. endcase end endmodule module t_Prob_5_38a (). reset_b. #3 reset_b = 0. reset_b). x_in) begin next_state = s0. Ciletti. else if (x_in == 1) next_state = s1. s1: if (x_in == 0) next_state = s1. next_state. initial begin clk = 0. always @ (state. join endmodule Name clk reset_b x_in state[1:0] 0 60 120 180 0 3 1 2 0 3 1 2 0 3 (b) module Prob_5_38b (input x_in. // Initialize to s0 #4 reset_b = 1. #3 reset_b = 0.152 #110 x_in = 1. default: next_state = s0. Copyright 2012. forever #5 clk = ~clk. #140 x_in = 1. . else if (x_in == 1) next_state = s0. M.D. case (state) s0: if (x_in == 0) next_state = s0. Mano. Prob_5_38b M0 ( x_in. end initial fork #2 reset_b = 1. reg [1: 0] state. clk. #170 x_in= 1. #150 x_in = 0. clk. M. s3 = 2'b11. parameter s0 = 2'b00. reg x_in. negedge reset_b) if (reset_b == 0) state <= s0. else if (x_in == 1) next_state = s3. s2 = 2'b10. else state <= next_state. always @ (posedge clock. endcase end endmodule module t_Prob_5_38b (). reset_b). if (x_in == 0) next_state = s2. s3: Digital Design With An Introduction to the Verilog HDL – Solution Manual. s1 = 2'b01. initial #350$finish. s2: if (x_in == 0) next_state = s3. else if (x_in == 1) next_state = s2. reset_b. #2 x_in = 0. #20 x_in = 1. clock. #120 x_in = 0. All rights reserved. negedge reset_b) begin if (reset_b == 0) state <= S_0. M. B_out = ~B_in. Serial_2s_Comp M0 (B_out. input B_in. negedge reset_b) if (reset_b == 0) data <= 16'ha5ac. B_out = 0.153 #60 x_in = 0. always @ (posedge clk. clk. reset_b. end else if (B_in == 1) begin next_state = S_1. M. initial #150 $finish. else data <= data >> 1. case (state) S_0: if (B_in == 0) begin next_state = S_0. #170 x_in= 1. B_in) begin B_out = 0. Mano. endcase end endmodule module t_Serial_2s_Comp (). // See problem 5. reg [15: 0] data. forever #5 clk = ~clk. else state <= next_state. reg clk. clk. // Sample bit stream Digital Design With An Introduction to the Verilog HDL – Solution Manual. B_out = 1.39 module Serial_2s_Comp (output reg B_out. Copyright 2012. next_state. B_in. end default: next_state = S_0. #90 x_in = 0. end S_1: begin next_state = S_1. wire B_in. Ciletti. All rights reserved. S_1 = 1'b1. reg state. always @ (negedge clk. #120 x_in = 0.D. assign B_in = data[0]. . end initial fork #10 reset_b = 0. initial begin clk = 0. reset_b). #80 x_in = 1. B_out. #140 x_in = 1. #150 x_in = 0. join endmodule Name clk reset_b x_in state[1:0] 0 60 120 180 0 3 1 2 0 3 1 2 0 3 1 2 0 5. #110 x_in = 1.17 parameter S_0 = 1'b0. reset_b). end always @ (state. parameter s0 = 2'b00. if (E == 0) next_state = s2. s2 = 2'b10. reg [1: 0] state. else next_state = s2. E. s3 = 2'b11.D. M. s1: if (E == 0) next_state = s1. join endmodule Name 0 60 120 clk reset_b B_in state B_out 5. F. reset_b). s2: s3: Digital Design With An Introduction to the Verilog HDL – Solution Manual. All rights reserved. if (E == 0) next_state = s3. clock. s1 = 2'b01. else next_state = s1. Ciletti. next_state. . else if (F == 1) next_state = s0. else next_state = s0. Mano. else if (F == 1) next_state = s2. else next_state = s3. else if (F == 1) next_state = s1. case (state) s0: if (E == 0) next_state = s0.154 #12 reset_b = 1. Copyright 2012.40 EF = 0x s0 10 10 11 0x s3 11 10 11 s1 11 0x 10 s2 0x module Prob_5_40 (input E. M. always @ (posedge clock. F) begin next_state = s0. else if (F == 1) next_state = s3. always @ (state. negedge reset_b) if (reset_b == 0) state <= s0. else state <= next_state. reg [2: 0] state. input x_in. reset_b). reset_b). y_out = 0.D. #140 E = 1. else state <= next_state. module t_Prob_5_40 (). F. next_state. F. #120 E = 0. M. F = 1. #150 E = 0. #2 E = 0. #170 F = 0. #170 E= 1. All rights reserved. #110 E = 1. end Digital Design With An Introduction to the Verilog HDL – Solution Manual. forever #5 clk = ~clk. M. y_out = 1. always @ (posedge clock.155 default: endcase end endmodule next_state = s0. #20 begin E = 1. clock. Ciletti. reset_b. always @ (state. parameter s0 = 3'b000. #3 reset_b = 0. end initial fork #2 reset_b = 1. negedge reset_b) if (reset_b == 0) state <= s0. reg E. Prob_5_40 M0 ( E. case (state) s0: if (x_in) begin next_state = s4. end else begin next_state = s3. #90 E = 0. // Initialize to s0 #4 reset_b = 1. s3 = 3'b011. s1 = 3'b001. s4 = 3'b100. Copyright 2012. end #60 E = 0. next_state = s0. clk. initial begin clk = 0.41 module Prob_5_41 (output reg y_out. clk. . #80 E = 1. s2 = 3'b010. x_in) begin y_out = 0. Mano. initial #350$finish. join endmodule Name clk reset_b E F state[1:0] 0 100 200 0 1 2 3 0 1 2 3 2 1 0 3 2 1 5. w3). endmodule module DFF (output reg Q. and (w3. Prob_5_41 M0 (y_out. #3 reset_b = 0. not (B_bar. B). initial begin clk = 0. 5. w1. and (y. wire y_out. x_in. x). // Drive from s0 to s3 to S1 and park #40 x_in = 1. Ciletti. w3. A. or (D_A. clk. D_A. y_out = 0. and (w2.29 wire w1. reset_b). Mano. end else begin next_state = s1. B_bar.D. M. clk. next_state = 3'bxxx. y. A. reset_b). y_out = 0. D1. B_bar. D2. end else begin next_state = s2. reset_b. clk. B.156 s1: end s2: end s3: end s4: end if (x_in) begin next_state = s4. DFF M0_A (A. if (x_in) begin next_state = s0. // Drive to s4 to s3 to s2 to s0 to s4 and loop #90 x_in = 0. input x. // See Fig. end else begin next_state = s2. DFF M0_B (B. and (w1. B). // Drive from s0 to s3 to s2 and part #110 x_in = 1. input data. clk. M. or (D_B. initial #350$finish. B. D_B. end else begin next_state = s1. if (x_in) begin next_state = s3. // Trace the state diagram and monitor y_out x_in = 0. if (x_in) begin next_state = s2. y_out = 0. Copyright 2012. All rights reserved. reg x_in. y_out = 0. . reset_b). x). reset_b). // Initialize to s0 #4 reset_b = 1. y_out = 1. forever #5 clk = ~clk. w2. reset_b). clk. Digital Design With An Introduction to the Verilog HDL – Solution Manual. y_out = 0. x). default: endcase end endmodule module t_Prob_5_41 (). y_out = 1. clk. y_out = 1. w2).42 module Prob_5_42 (output A. // Drive s0 to s4 etc join endmodule 0 40 80 Name clk reset_b x_in state[2:0] y_out 3 1 4 3 2 0 4 2 0 4 120 5. w1. end initial fork #2 reset_b = 1. 3'b011: count = 3'b100.157 always @ (posedge clk.D. 3'b100: count = 3'b001. B. 3'b101: count = 3'b010. Prob_5_42 M0 (A.45. Mano. #70 bit_in = 0. // Drive to S0 #30 bit_in = 0. Ciletti. . reset_b). 3'b001: count = 3'b010. #3 reset_b = 0. M. wire A. // Trace the state diagram and monitor detect (assert in S3) bit_in = 0. B_bar. B. #130 bit_in = 0. clk. endmodule module t_Prob_5_42 (). always @ (count) begin case (state) 3'b000: count = 3'b001. else count <= next_count. B}. All rights reserved. M. else Q <= data. wire [1:0] state. initial #350$finish. // Drive to S1 and back to S0 (2 clocks) #50 bit_in = 1. end initial fork #2 reset_b = 1. forever #5 clk = ~clk. bit_in. B_bar. Copyright 2012. 3'b110: count = 3'b011. 3'b111: count = 3'b100. then and back to S0 join endmodule Name 0 50 100 150 reset_b clk A B B_bar y state[1:0] detect x 0 1 0 1 2 0 1 2 3 0 5. #4reset_b = 1. y. reset_b. clk. assign state = {A. wire detect = y. input clk. y. initial begin clk = 0. // Drive to S2 and back to S0 (3 clocks) #80 bit_in = 1. 3'b010: count = 3'b011. Digital Design With An Introduction to the Verilog HDL – Solution Manual. reset_b) always @ (posedge clk) if (reset_b == 0) count <= 0. // Park in S0 #20 bit_in = 1. reg bit_in. // Drive to S3. park. // Patterns from Problem 5. negedge reset_b) if (reset_b == 0) Q <= 0.43 module Binary_Counter_3_bit (output [2: 0] count. T_flop M2 (A2. always @ (posedge clk. Prob_5_41 M0 (A2. forever #5 clk = ~clk. input T. endmodule module t_Prob_5_41. wire [2: 0] count = {A2. . A0. reset_bar). wire A2. initial #200 $finish. negedge reset_bar) if (!reset_bar) Q <= 0. clk. toggle_A2. All rights reserved. A0. T_flop M1 (A1. reset_bar). clk. endmodule Name 0 50 100 150 reset_b clk count[2:0] x 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 Alternative: structural model. M. clk. A0. endcase end endmodule module t_Binary_Counter_3_bit () wire [2: 0] count. T. initial begin clk = 0. reset_bar). forever #5 clk = ~clk. join initial fork T = 0. Binary_Counter_3_bit M0 ( count. initial begin clk = 0. reset_b) initial #150 $finish. Ciletti. reg T. else if (T) Q <= ~Q. clk. #70 T = 0. #40 reset_bar = 0. #12 reset = 1. reset_b. A0. It resumes a correct counting sequence when T is changed back to 1. join endmodule If the input to A0 is changed to 0 the counter counts incorrectly. clk. clk. reset_bar). reset_bar). T_flop M0 (A0. end initial fork reset_bar = 0. M. A0. A1).158 default: count = 3'b000. A1. Mano. A1. reset_bar. else Q <= Q. module Prob_5_41 (output A2. #10 reset = 0. clk. A0}. A1. Copyright 2012. end initial fork reset = 1.D. clk. #2 reset_bar = 1. wire toggle_A2. #20 T = 1. #110 T = 1. and (toggle_A2. reg clk. endmodule module T_flop (output reg Q. reset_bar). input T. A1. #42 reset_bar = 1. T. Digital Design With An Introduction to the Verilog HDL – Solution Manual. input data. clk. Mano.45 module Seq_Detector_Prob_5_45 (output detect. #110 data = 0. reset). #50 data = 0. Copyright 2012. #82 reset = 1. reset_b). #12 data = 1. M. Ciletti. #97 reset = 0. initial #150 $finish.15 5. #41 reset = 0. end initial fork reset = 0. DFF_asynch_reset M0 (Q. clk. parameter S0 = 0. reset. forever #5 clk = ~clk. clk. Digital Design With An Introduction to the Verilog HDL – Solution Manual. input bit_in. #90 data = 1.D. always @ (posedge clk. #80 data = 0. M. clk. . initial begin clk = 0. S1 = 1. data. reset). S3 = 3. reg data. #60 data = 1. All rights reserved. wire Q. #7 reset = 1. endmodule module t_DFF_asynch_reset (). else Q <= data.44 module DFF_asynch_reset (output reg Q. join endmodule Name reset clk 0 50 100 150 data Q 5. posedge reset) // Asynchronous reset if (reset) Q <= 0. S2 = 2. reg bit_in. // Drive to S3. All rights reserved. . default: next_state = S0.D. M. else next_state = S0.160 reg [1: 0] state. Mano. 2: if (bit_in) next_state = S3. Ciletti. reset_b).46 Pending simulation results Digital Design With An Introduction to the Verilog HDL – Solution Manual. else state = S0. else state = S0. initial #350$finish. else next_state = S0. // Trace the state diagram and monitor detect (assert in S3) bit_in = 0. 3: if (bit_in) next_state = S3. // Drive to S0 #30 bit_in = 0. always @ (state. Seq_Detector_Prob_5_45 M0 (detect. case (state) 0: if (bit_in) next_state = S1. 1: if (bit_in) next_state = S2. endcase end endmodule module t_Seq_Detector_Prob_5_45 (). bit_in. clk. park. Copyright 2012. else state <= next_state. negedge reset_b) if (reset_b == 0) state <= S0. bit_in) begin next_state = S0. end initial fork #2 reset_b = 1. reset_b. forever #5 clk = ~clk. initial begin clk = 0. #70 bit_in = 0. always @ (posedge clk. // Drive to S1 and back to S0 (2 clocks) #50 bit_in = 1. clk. #4reset_b = 1. wire detect. // Drive to S2 and back to S0 (3 clocks) #80 bit_in = 1. then and back to S0 join endmodule Name 0 40 80 120 reset_b clk bit_in state[1:0] detect x 0 1 0 1 2 0 1 2 3 0 5. #3 reset_b = 0. assign detect = (state == S3). M. // Park in S0 #20 bit_in = 1. #130 bit_in = 0. next_state. . end initial fork reset_b = 0. #90 reset_b = 1. 00. x_in 01. else next_state = 3'b000. clk. always @ (posedge clk) if (reset_b == 1'b0) state <= 3'b000. always @ (x_in. initial begin clk = 0. 3'b001: next_state = 3'b010. Mano.161 Assumption: Synchronous active-low reset Moore machine reset_b. reset_b. Copyright 2012. next_state. assign y_out = (state == 3'b001)||(state == 3'b010) || (state == 3'b011). All rights reserved. x_in = 0. endcase end endmodule module t_Prob_5_46 (). clk. M. 3'b101: next_state = 3'b000. x_in. reset_b). case (state) 3'b000: if (x_in) next_state = 3'b001. reset_b). #10 reset_b = 1. #30 x_in = 1. 10 000 0 y_out 11 0x 001 1 0x 1x 010 1 1x 011 1 1x 100 0 1x 101 0 xx 0x 0x Verify that machine remains in state 000 while reset_b is asserted. clk. forever #5 clk = !clk. else state <= next_state. 3'b010: next_state = 3'b011. #40 x_in = 1. module Prob_5_46 (output y_out. Verify that state transitions from 000 through 101 are correct. wire y_out. Verify reset_b "on the fly.D. state) begin next_state = 3'b000. 3'b011: next_state = 3'b100. Verify that machine makes transition from 000 to 001 if not reset_b and if x_in is asserted. M. 3'b100: next_state = 3'b101. Digital Design With An Introduction to the Verilog HDL – Solution Manual. initial #200 $finish. reg [2:0] state." Verify that y_out is asserted correctly. Ciletti. default: next_state = 3'b000. independently of x_in. input x_in. #80 reset_b = 0. reg x_in. Prob_5_46 M0 (y_out. reg Run. #60 x_in = 1. // Initiate counting #70 Run = 0. join endmodule 5. clk. // redundant statement and may be omitted endmodule // Verify that counting is prevented while reset_b is asserted. Mano. else if (Run && (y_out == 4'b1110)) y_out <= 4'b0000. // reset on-the-fly #120 reset_b = 1. independently of Run // Verify that counting is initiated by Run if reset_b is de-asserted // Verify reset on-the-fly // Verify that deasserting Run suspends counting // Verify wrap-around of counter. Ciletti. input Run. #30 reset_b = 1. initial begin clk = 0. forever #5 clk = !clk.D. end initial fork reset_b = 0. reset_b). Prob_5_47 M0 (y_out. module t_Prob_5_47 (). reset_b. Run. #130 x_in = 0. // Pause #90 reset_b = 0. #70 x_in = 0. M. // Resume counting join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. M. module Prob_5_47 (output reg [3:0] y_out. else if (Run && (y_out < 4'b1110)) y_out <= y_out + 2'b10. always @ (posedge clk) if (reset_b == 1'b0) y_out <= 4'b000. Run = 1. . #50 Run = 1. else y_out <= y_out. initial #300 $finish. clk. #120 x_in = 1. All rights reserved. reset_b). // Attempt to run is overridden by reset_b #30 Run = 0. // Pause counting #200 Run = 1. wire [3:0] y_out.47 Assume synchronous active-low reset.162 #50 x_in = 0. clk. // De-assert reset_b #150 Run = 1. Copyright 2012. // Resume counting #180 Run = 0. y_out = 1. end s_c: if (x_in == 1'b0) begin next_state = s_b. y_out = 1.163 5. y_out = 0. initial begin clk = 0. reset_b. end s_d: if (x_in == 1'b0) begin next_state = s_c.D. hold x_in = 1 and get loop bdacd… Transition to d. end else begin next_state = s_c. M. Digital Design With An Introduction to the Verilog HDL – Solution Manual. module Prob_5_48 (output reg y_out. reg [1: 0] state. y_out = 0. Ciletti. y_out = 1. y_out = 0. All rights reserved. end endcase end endmodule Verify reset action. parameter s_c = 2'd2. end else begin next_state = s_d. end else begin next_state = s_d. y_out = 0. Mano. end default: begin next_state = s_a. wire y_out. hold x_in = 0 and get loop bc… Transition to a. M. Transition to a. clk. always @ (posedge clk) if (reset_b == 1'b0) state <= s_a. x_in) begin next_state = s_a. parameter s_a = 2'd0. y_out = 0. input x_in.48 Assume "a" is the reset state. next_state. y_out = 0. module t_Prob_5_48 (). clk. reg x_in. x_in. reset_b). . end else begin next_state = s_a. hold x_in = 1 and get loop acda… Transitons to b. Prob_5_48 M0 (y_out. y_out = 1. forever #5 clk = !clk. initial #400 $finish. parameter s_b = 2'd1. case (state) s_a: if (x_in == 1'b0) begin next_state = s_b. else state <= next_state. Verify state transitions. Copyright 2012. parameter s_d = 2'd3. reset_b). clk. always @ (state. hold x_in = 0 and get loop dcbc… Confirm Mealy outputs at each state/input pair Verify reset on-the-fly. end s_b: if (x_in == 1'b0) begin next_state = s_c. end initial fork reset_b = 0. Copyright 2012. always @ (state. default: next_state = s_a. #310 reset_b = 1. else next_state = s_a. M. else next_state = s_c. parameter s_c = 2'd2. else state <= next_state. join endmodule // loop abcbcbc… // loop acdacda… // loop bdacdacd… // loop acdcbcbc…. #300 reset_b = 0. Ciletti. reg [1: 0] state. if (x_in == 1'b0) next_state = s_b. #330 x_in = 0. #310 x_in = 1.164 #30 reset_b = 1. Mano. #210 x_in = 0. next_state. parameter s_ =d 2'd3. .D. case (state) s_a: if (x_in == 1'b0) next_state = s_b. #100 reset_b = 0. M. #110 reset_b = 1. reset_b). else next_state = s_d. #220 x_in = 1. end s_c: begin y_out = 1'b1. if (x_in == 1'b0) next_state = s_c. #110 x_in = 1. y_out = 1'b0. #30 x_in = 0. #210 reset_b = 1. x_in) begin next_state = s_a. clk. endcase end endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. input x_in. always @ (posedge clk) if (reset_b == 1'b0) state <= s_a. #200 reset_b = 0. end s_d: if (x_in == 1'b0) next_state = s_c. parameter s_a = 2'd0. 5. module Prob_5_49 (output reg y_out. parameter s_b = 2'd1. else next_state = s_d. s_b: begin y_out = 1'b1. All rights reserved.49 Assume "a" is the reset state. D. join endmodule // loop acdacda… // loop bdacdacd… // loop acdcbcbc…. // Verify state transitions. initial #400 $finish. hold x_in = 0 and get loop dcbc… // Confirm Moore outputs at each state // Verify reset on-the-fly. #30 reset_b = 1. Prob_5_49 M0 (y_out. reset_b. #310 reset_b = 1. x_in. #210 x_in = 0. forever #5 clk = !clk. // Transition to a. #310 x_in = 1. wire y_out. hold x_in = 1 and get loop acda… // Transitons to b. // loop abcbcbc… #100 reset_b = 0. #200 reset_b = 0.165 // Verify reset action. #300 reset_b = 0. #330 x_in = 0. . Digital Design With An Introduction to the Verilog HDL – Solution Manual. #30 x_in = 0. All rights reserved. #110 reset_b = 1. module t_Prob_5_49 (). M. hold x_in = 0 and get loop abcbc… // Transition to a. initial begin clk = 0. #220 x_in = 1. reset_b). clk. Run. reg x_in. hold x_in = 1 and get loop bdacd… // Transition to d. #110 x_in = 1. #210 reset_b = 1. Ciletti. clk. Copyright 2012. end initial fork reset_b = 0. Mano. M. Mano. Set_flag = 1. Set_flag = 0. links for reset on-the-fly are implicit and not shown Set_flag reset_b && x_in && !flag !reset_b || !x_in a 0 reset_b && x_in && flag b 1 0 c 1 0 Clr_flag Note: the output signal y_out is a Moore-type output. The machine is to assert its output upon detection of the second sample and to continue asserting the output until the fourth sample is detected. parameter s_a = 2'd0. x_in. Set_flag = 0. case (state) s_a: if ((x_in == 1'b1) && (flag == 1'b0)) begin next_state = s_a. end s_c: if (x_in == 1'b0) next_state = s_c. clk. reg [1:0] state. reg Set_flag. parameter s_b = 2'd1. M. Clr_flag = 0. This will enable the machine to detect the presence of the second sample while being in the initial state. The control signals Set_flag and Clr_flag are not. reg Clr_flag. All rights reserved. Assumption: Synchronous active-low reset Moore machine. Ciletti.50 The machine is to remain in its initial state until a second sample of the input is detected to be 1. end else if (x_in == 1'b0) next_state = s_a. input x_in. else if (Set_flag) flag <= 1'b1. assign y_out = (state == s_b) || (state == s_c) .D. default: begin next_state = s_a. always @ (state. else next_state = s_a. reset_b). always @ (posedge clk) if (reset_b == 1'b0) state <= s_a. else begin next_state = s_c.166 5. endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. Clr_flag = 1. end endcase end always @ (posedge clk) if (reset_b == 1'b0) flag <= 0. Copyright 2012. else if (Clr_flag) flag <= 1'b0. module Prob_5_50 (output y_out. end else if ((x_in == 1'b1) && (flag == 1'b1)) begin next_state = s_b. s_b: if (x_in == 1'b0) next_state = s_b. M. next_state. Set_flag = 1'b0. else state <= next_state. A flag will be set when the first sample is obtained. . flag) begin next_state = s_a. Clr_flag = 1'b0. parameter s_c = 2'd2. #20 x_in = 1'b0. end initial fork reset_b = 1'b0. #20 reset_b = 1. join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. #100 x_in = 0.D.167 // Verify reset action // Verify detection of first input // Verify wait for second input // Verify transition at detection of second input // Verify with between detection of input // Verify transition to s_d at fourth detection of input // Verify return to s_a and clearing of flag after fourth input // Verify reset on-the-fly module t_Prob_5_50 (). forever #5 clk = !clk. #50 x_in = 1'b0. M. M. reset_b. #250 reset_b = 1'b1. Prob_5_50 M0 (y_out. initial #500 $finish. reg x_in. #160 x_in = 1'b0. Copyright 2012. initial begin clk = 0. clk. reset_b). All rights reserved. #150 x_in = 1'b1. #80 x_in = 1'b1. #230 reset_b = 1'b0. #300 x_in = 1'b0. wire y_out. #200 x_in = 1'b1. Mano. . clk. Ciletti. x_in. #40 x_in = 1'b1. links for reset on-the-fly are implicit and not shown reset_b s0 0 01. Ciletti.51 Assumption: Synchronous active-low reset Moore machine.55 Assumption: Synchronous active-low reset Mealy machine.53 Assumption: Synchronous active-low reset Moore machine.52 Assumption: Synchronous active-low reset Moore/Mealy machine. 11 01. links for reset on-the-fly are implicit and not shown 0/1 0/0 0/0 reset_b s0 0/0 1/0 s1 1/0 s2 1/0 s3 1/1 Digital Design With An Introduction to the Verilog HDL – Solution Manual. links for reset on-the-fly are implicit and not shown Mealy output reset_b 0 0/1 0 0 s0 0 1 s1 0 1 s2 1/0 s3 1 1 5. links for reset on-the-fly are implicit and not shown reset_b s0 0 0 1 s1 0 0 1 s2 0 0 1 s3 1 1 0 5. 11 5. 11 s2 1 00. .D. Mano. M. All rights reserved. M. Copyright 2012. links for reset on-the-fly are implicit and not shown reset_b 0 s0 0 1 s1 0 0 1 s2 1 0 1 s3 1 0 1 5.54 Assumption: Synchronous active-low reset Moore machine. 10 s1 0 00.168 5. 10 01. 10 00. All rights reserved. Mano. Copyright 2012. M. . M.16 5.D.56 reset_b x_in 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 D2 D1 D0 x 0 0 x 0 0 x 0 1 x 0 1 x 1 0 x 1 0 x 1 1 x 1 1 0 1 x 0 1 x 0 1 x 0 1 x 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 nD2 0 1 0 1 0 1 0 1 0 0 1 0 0 1 0 0 1 0 0 1 nD1 nD0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 For reset_b = 1: nD2 = (x_in D2'D1D0') || (x_in' D2 D1' D0') || (x_in D2 D1' D0') || (x_in D2 D1 D0') nD1 = (x_in D2' D1' D0') || (x_in' D2' D1 D0') || (x_in D2 D1' D0') || (x_in' D2 D1 D0') Digital Design With An Introduction to the Verilog HDL – Solution Manual. Ciletti. D. reg Run. reset_b. Copyright 2012. else if (Run && (y_out == 3'b110)) y_out <= 3'b000.57 Assume synchronous active-low reset.170 x_in D2 D1 D0 00 m0 D1 01 m1 D1 D0 10 x_in D2 00 00 m0 D1 01 m1 11 m3 m2 11 m3 10 m2 00 m4 m5 m7 m6 1 m4 m5 m7 m6 01 11 x_in 10 m8 1 m12 m13 m15 m14 01 D2 m12 m13 m15 1 m14 D2 1 m9 m11 1 m10 11 x_in m8 1 m9 m11 m10 1 D0 10 1 D0 nD2 = D2 D1'D0' + x_in D1 D0' x_in D2 D1 D0 Reset_b Clk nD1 = x_inD1' D0' + x_in' D1 D0' D D2 Clr D2' D D1 Clr D1' 5. module t_Prob_5_57 (). Digital Design With An Introduction to the Verilog HDL – Solution Manual. clk. wire [2:0] y_out. always @ (posedge clk) if (reset_b == 1'b0) y_out <= 3'b000. clk. clk. All rights reserved. // redundant statement and may be omitted endmodule // Verify that counting is prevented while reset_b is asserted. Assume that the counter is controlled by assertion of Run. . else if (Run && (y_out < 3'b110)) y_out <= y_out + 3'b010. input Run. else y_out <= y_out. M. reset_b). Ciletti. independently of Run // Verify that counting is initiated by Run if reset_b is de-asserted // Verify reset on-the-fly // Verify that deasserting Run suspends counting // Verify wrap-around of counter. module Prob_5_57 (output reg [2:0] y_out. M. reset_b). Mano. Prob_5_57 M0 (y_out. Run. Ciletti. initial begin clk = 0.171 initial #300 $finish. All rights reserved. end initial fork reset_b = 0. x_in. next_state = s0. reset_b) Digital Design With An Introduction to the Verilog HDL – Solution Manual. reset_b. // De-assert reset_b #150 Run = 1. Prob_5_58 M0 (y_out.D. reg [1:0] state. Run = 1. else if (x_in = 1'b1) next_state = s1. clk. // Resume counting #180 Run = 0. clk.58 module Prob_5_58 (output reg y_out. #30 reset_b = 1. parameter s3 = 2'b11. x_in) begin y_out = 0. reset_b) parameter s0 = 2'b00. always @ (posedge clk. . else state <= next_state. else if (x_in = 1'b1) next_state = s2. input x_in. end default: begin next_state = s0. next_state. reg x_in. Mano. // Initiate counting #70 Run = 0. // Pause #90 reset_b = 0. s1: if (x_in == 1'b0) next_state = s0. parameter s2= 2'b10. // Attempt to run is overridden by reset_b #30 Run = 0. // reset on-the-fly #120 reset_b = 1. // Resume counting join endmodule 5. y_out = 1. y_out = 0. forever #5 clk = !clk. s2: if (x_in == 1'b0) next_state = s0. negedge reset_b) if (reset_b == 1'b0) state <= s0. M. else if (x_in = 1'b1) next_state = s3. clk. parameter s1 = 2'b01. case(state) s0: if (x_in == 1'b0) next_state = s0. #50 Run = 1. // Pause counting #200 Run = 1. Copyright 2012. M. else if (x_in = 1'b1) begin next_state = s3. end endcase end endmodule module t_Prob_5_58 (). wire y_out. always @(state. s3: if (x_in == 1'b0) next_state = s0. M. end initial fork reset_b = 0. clk. join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual. #150 x_in = 0. #90 x+in = 0. forever #5 clk = ~clk. #100 reset_b = 0. enable. Copyright 2012. . 3'b100: count <= 3'b110. else if (enable) case (count) 3'b000: count <= 3'b010. 3'b110: count <= 3'b000. join endmodule 5. initial #200 $finish. reg enable. clk.59 module Prob_5_59 (output reg [2: 0] count. reset_b). always @ (posedge clk) if (reset_b == 1'b0) count <= 3'b000. wire [2:0] count. #80 x_in = 1. reset_b). end initial fork reset_b = 0. #110 x_in = 1. #130 reset_b = 1.D. x_in = 0. // Use for error detection endcase endmodule module t_Prob_5_59 ().172 initial begin clk = 0. #120 x_in = 1. #90 enable = 1. Ciletti. enable = 0. #200 x_in = 1. reset_b. M. #210 reset_b = 0. initial begin clk = 0. #60 x_in = 0. #30 enable = 1. 3'b010: count <= 3'b100. #10 reset_b = 1. input enable. forever #5 clk = !clk. Mano. #50 x_in = 1. #40 reset_b = 1. clk. #60 enable = 0. Prob_5_59 M0 (count. #20 reset_b = 1. All rights reserved. default: count <= 3'b111. #240 reset_b = 1. 173 5. Assume that counting is controlled by Run. . forever #5 clk = !clk. initial begin clk = 0. // reset on-the-fly #120 reset_b = 1. Mano. input Run. Run = 1.500 else y_out <= y_out. wire [3:0] y_out. always @ (posedge clk) if (reset_b == 1'b0) y_out <= 4'b000. reset_b). else if (Run && (y_out < 4'b1001)) y_out <= y_out + 4'b0001. // Pause #90 reset_b = 0. // Resume counting #180 Run = 0. // Pause counting #200 Run = 1. reg Run. Ciletti. end initial fork reset_b = 0. // De-assert reset_b #150 Run = 1.D. reset_b. Run. #50 Run = 1. reset_b). All rights reserved. module t_Prob_5_60 (). module Prob_5_60 (output reg [3:0] y_out. M. #30 reset_b = 1. clk. clk. Prob_5_60 M0 (y_out. independently of Run // Verify that counting is initiated by Run if reset_b is de-asserted // Verify reset on-the-fly // Verify that deasserting Run suspends counting // Verify wrap-around of counter. else if (Run && (y_out == 4'b1001)) y_out <= 4'b0000. Copyright 2012. initial #500 $finish. clk. M. // redundant statement and may be omitted endmodule // Verify that counting is prevented while reset_b is asserted. // Attempt to run is overridden by reset_b #30 Run = 0. // Resume counting join endmodule Digital Design With An Introduction to the Verilog HDL – Solution Manual.60 Assume synchronous active-low reset. // Initiate counting #70 Run = 0.