Solution Manual Advanced Digital Design With the Verilog HDL 2nd Edition Michael D. Ciletti

Solution Manual Advanced Digital Design With TheVerilog HDL 2nd edition Michael D. Ciletti Download full at: https://testbankdata.com/download/solution-manual-advanced- digital-design-verilog-hdl-2nd-edition-michael-d-ciletti/ Problem 3-1 Problem 3-2 clk rst Bit_in Parity Par_Detect Assumption: asynchronous reset Bit_in clocked on rising edge. Interpretation: Even parity will be asserted unless an odd number of rst 1 1s have been received. s0 s1 1 0 0 0 1 SET D Q Bit_in Q parity CLR clock rst Problem 3-3 q2 q1 q0 q2+ q1+ q0+ s0 0 0 0 0 1 0 s2 0 1 0 1 0 0 s4 1 0 0 1 1 0 s6 1 1 0 0 0 0 q2+ = q2'q1q0' + q2q1'q0' = (q2 ^ q1)q0' q1+ = q2'q1'q0' + q2q1'q0' = q1'q0' Note that QB could be used to eliminate the inverter. Advanced Digital Design with the Verilog HDL, Second Edition Michael D. Ciletti Prentice Hall, Pearson Education, 2011 Problem 3-4 State transition graph - Mealy Machine 1/1 reset 0 1/0 1/0 1/1 s0 s1 s2 s3 0/0 0/0 0/0 Advanced Digital Design with the Verilog HDL, Second Edition Michael D. Ciletti Prentice Hall, Pearson Education, 2011 Problem 3 – 5 Advanced Digital Design with the Verilog HDL, Second Edition Michael D. Ciletti Prentice Hall, Pearson Education, 2011 Problem 3-6 No static-0 or static-1 hazards. Advanced Digital Design with the Verilog HDL, Second Edition Michael D. Ciletti Prentice Hall, Pearson Education, 2011 Problem 3-7 B_in = 1 B_in = 0 reset S_00 B_in = 0 S_10 B_in = 1 S_11 B_in = 1 S_21 B_in = 1 S_31 0 0 0 0 1 B_in = 0 B_in = 1 B_in = 0 B_in = 0 Advanced Digital Design with the Verilog HDL, Second Edition Michael D. Ciletti Prentice Hall, Pearson Education, 2011 Problem 3-8 Tie the machines together to complete the solution: bit, done rst 1,x s_0 0 incr 0,x 0,x Control Counter Unit s_1 done 0 0,x 1,x incr is asserted as the output of the FSM n s_4 and S_5. 1,x s_2 done is asserted by the counter when the 0 counter is 5. 0,x 1,x s_3 1, done s_5 s_6 0 1 0 0,x 1,0 s_4 1 Assumption: asynchronous reset. Bit_in clocked on rising edge. MSB (0) of 0111 arrives first. Transitions for reset condition are omitted for simplicity. Bit_in 0 1 rst s0 0 s1 1 s2 1 s3 1 s4 0 0 0 0 1 0 Detect 0 0 0 Detect 0 rst s0 1 s1 1 s2 1 s3 1 s4 1 s5 1 s6 0 0 0 0 0 0 1 0 0 0 0 0 Done Advanced Digital Design with the Verilog HDL, Second Edition Michael D. Ciletti Prentice Hall, Pearson Education, 2011 Problem 3-9 Sample at the midpoint of the bit time. module NRZ_NRZI ( output reg B_out, input B_in, input clk, rst ); parameter s0 = 0; parameter s1 = 1; reg state, next_state; always @ (negedge clk, posedge rst) if (rst == 1) state <= s0; else state <= next_state; always @ (state, B_in) begin next_state = state; B_out = 0; case(state) s0: if (B_in == 1) begin next_state = s1; B_out = 0; end s1: if (B_in == 1) begin next_state = s0; B_out = 1; end endcase end endmodule module t_NRZ_NRZI (); // problem 3.9 wire B_out; reg B_in; reg clk, rst; reg clk_NRZ; NRZ_NRZI M1 (B_out, B_in, clk, rst); initial #400 $finish; initial begin rst = 0; #10 rst = 1; #20 rst = 0; #147 rst = 1; // reset on-the-fly #5 rst = 0; end initial begin clk = 1; forever #5 clk = ~clk; end initial begin clk_NRZ = 1; forever #10 clk_NRZ = ~clk_NRZ; end initial begin // Data waveform B_in = 1; #40 B_in = 0; #40 B_in = 1; #40 B_in = 0; #40 B_in = 1; #100 B_in = 0; #100 B_in = 1; end endmodule Advanced Digital Design with the Verilog HDL, Second Edition Michael D. Ciletti Prentice Hall, Pearson Education, 2011 Problem 3-10 NRZI Line encoder Advanced Digital Design with the Verilog HDL, Second Edition Michael D. Ciletti Prentice Hall, Pearson Education, 2011 Problem 3-11 Advanced Digital Design with the Verilog HDL, Second Edition Michael D. Ciletti Prentice Hall, Pearson Education, 2011 Problem 3-12 Advanced Digital Design with the Verilog HDL, Second Edition Michael D. Ciletti Prentice Hall, Pearson Education, 2011 Problem 3-13