sn74ls04

SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004SN5404, SN54LS04, SN54S04, SN7404, SN74LS04, SN74S04 HEX INVERTERS D Dependable Texas Instruments Quality and Reliability description/ordering information These devices contain six independent inverters. SN5404 . . . J PACKAGE SN54LS04, SN54S04 . . . J OR W PACKAGE SN7404, SN74S04 . . . D, N, OR NS PACKAGE SN74LS04 . . . D, DB, N, OR NS PACKAGE (TOP VIEW) 1A 1Y 2A 2Y 3A 3Y GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC 6A 6Y 5A 5Y 4A 4Y SN5404 . . . W PACKAGE (TOP VIEW) 1A 2Y 2A VCC 3A 3Y 4A 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1Y 6A 6Y GND 5Y 5A 4Y SN54LS04, SN54S04 . . . FK PACKAGE (TOP VIEW) 2A NC 2Y NC 3A 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 1Y 1A NC VCC 6A 6Y NC 5A NC 5Y NC − No internal connection Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL PRF 38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. Copyright  2004, Texas Instruments Incorporated POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3Y GND NC 4Y 4A 1 SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 SN5404, SN54LS04, SN54S04, SN7404, SN74LS04, SN74S04 HEX INVERTERS ORDERING INFORMATION TA PACKAGE† Tube PDIP − N Tube Tube Tube Tape and reel Tube 0 C 70 C 0°C to 70°C SOIC − D Tape and reel Tube Tape and reel Tape and reel SOP − NS SSOP − DB Tape and reel Tape and reel Tape and reel Tube Tube Tube CDIP − J Tube Tube −55 C 125°C −55°C to 125 C CFP − W Tube Tube Tube Tube Tube LCCC − FK Tube ORDERABLE PART NUMBER SN7404N SN74LS04N SN74S04N SN7404D SN7404DR SN74LS04D SN74LS04DR SN74S04D SN74S04DR SN7404NSR SN74LS04NSR SN74S04NSR SN74LS04DBR SN5404J SNJ5404J SN54LS04J SN54S04J SNJ54LS04J SNJ54S04J SNJ5404W SNJ54LS04W SNJ54S04W SNJ54LS04FK SNJ54S04FK S04 SN7404 74LS04 74S04 LS04 SN5404J SNJ5404J SN54LS04J SN54S04J SNJ54LS04J SNJ54S04J SNJ5404W SNJ54LS04W SNJ54S04W SNJ54LS04FK SNJ54S04FK LS04 7404 TOP-SIDE MARKING SN7404N SN74LS04N SN74S04N † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each inverter) INPUT A H L OUTPUT Y L H 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54S04.SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 SN5404. TEXAS 75265 3 . SN74S04 HEX INVERTERS logic diagram (positive logic) 1A 1Y 2A 2Y 3A 3Y 4A 4Y 5A 5Y 6A Y=A 6Y POST OFFICE BOX 655303 • DALLAS. SN74LS04. SN54LS04. SN7404. SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 SN5404. 4 POST OFFICE BOX 655303 • DALLAS.5 kΩ 250 Ω GND GND Resistor values shown are nominal. SN7404. TEXAS 75265 .6 kΩ Input A Output Y 1 kΩ GND ’LS04 VCC 20 kΩ 8 kΩ 120 Ω 2.8 kΩ ’S04 VCC 900 Ω 50 Ω Input A 12 kΩ 4 kΩ Output Y Input A 3. SN74S04 HEX INVERTERS schematics (each gate) ’04 VCC 130 Ω 4 kΩ 1. SN74LS04. SN54S04.5 kΩ Output Y 500 Ω 3 kΩ 1. SN54LS04. . . . . . . . . . . . VIH = 2 V. . . 5. . . VCC = MAX VCC = MAX. . . . . 96°C/W N package . .5 V TEST CONDITIONS‡ II = − 12 mA VIL = 0. . . . . . . . . . . . . . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. . . VCC = MIN. . . . . . . . . . . . . . . . . . . . This are stress ratings only. . . . . . . . .8 V. . .5 IOH = −0. . . . . .6 −55 12 33 MIN SN7404 TYP§ MAX −1. .4 0. . . . . . . . . . . 76°C/W Storage temperature range. . . . . . . . .25 UNIT V V V mA mA °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. . . . . . . . . . . . . recommended operating conditions (see Note 3) SN5404 MIN VCC VIH VIL IOH IOL TA Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Operating free-air temperature −55 4. . . . . . . . . . . . . . . .5 V VI = 2. . . . Tstg . . .4 1 40 −1. SN7404. . . . . 86°C/W DB package .4 16 70 SN7404 NOM 5 MAX 5. . . . VCC = MAX.2 0. . . VI = 5. . . . . Implications of Slow or Floating CMOS Inputs. . . . . . . . .4 3. . . .75 2 0.2 0. . .5 V ’LS04 . . . . VI: ’04. . . . . . . . . . . . . . . . . . . . . SN54LS04.6 −55 12 33 −18 6 18 MAX −1. . . . . . . . .4 V VI = 0. 80°C/W NS package . .4 1 40 −1. . .4 V −20 6 18 MIN 2. . SN74LS04. . . . . .5 MIN 4. § All typical values are at VCC = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . .SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 SN5404. . . . . .4 mA IOL = 16 mA 2. . VI = 0 V VI = 4. . . . . .5 2 0. . . . . . VCC = MAX. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL II IIH IIL IOS¶ ICCH ICCL VCC = MIN. . . and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. 2. . . Refer to the TI application report. . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. . . . . . . . . . . TEXAS 75265 5 . . . . NOTES: 1. . .4 0. . VCC (see Note 1) . . . . 7 V Package thermal impedance. . . . . . . . . . . . . . . . . Voltage values are with respect to network ground terminal. . ’S04 . 7 V Input voltage. . . . θJA (see Note 2): D package . . .4 16 125 0 NOM 5 MAX 5. . . . . . . . . . . . . VCC = MAX. . SN54S04. .5 UNIT V V V mA µA mA mA mA mA ‡ For conditions shown as MIN or MAX. TA = 25°C. . . . . literature number SCBA004. . . . . . . . . .8 −0. . POST OFFICE BOX 655303 • DALLAS. . . . . . . . use the appropriate value specified under recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . .4 SN5404 TYP§ 3. . . . . . . . . . . . . VCC = MIN. . . . .8 −0. . . . . . . . . . . SN74S04 HEX INVERTERS absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage. The package thermal impedance is calculated in accordance with JESD 51-7. . . . . . ¶ Not more than one output should be shorted at a time. . VCC = MAX. . . . 2 3. VCC = MAX VCC = MAX.25 2.1 20 −0.4 6. ‡ All typical values are at VCC = 5 V.4 0. TA = 25°C (see Figure 2) PARAMETER tPLH tPHL FROM (INPUT) A TO (OUTPUT) Y TEST CONDITIONS SN54LS04 SN74LS04 MIN RL = 2 kΩ.4 8 70 NOM 5 MAX 5. literature number SCBA004.6 2.5 SN74LS04 MIN 4. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL II IIH IIL IOS§ ICCH ICCL VCC = MIN. VCC = MIN.8 −0.4 −100 2. SN74S04 HEX INVERTERS switching characteristics.5 2 0. VCC = 5 V.2 3.5 V 1. use the appropriate value specified under recommended operating conditions. TA = 25°C. switching characteristics.5 UNIT V V V mA µA mA mA mA mA † For conditions shown as MIN or MAX. CL = 15 pF SN5404 SN7404 TYP 12 8 MAX 22 15 ns UNIT recommended operating conditions (see Note 3) SN54LS04 MIN VCC VIH VIL IOH IOL TA Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Operating free-air temperature −55 4.5 0. SN74LS04.7 3.4 6. SN54LS04.5 3. SN54S04. VCC = MAX.4 4 125 0 NOM 5 MAX 5. VCC = MAX.5 IOH = −0.SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 SN5404. CL = 15 pF TYP 9 10 MAX 15 15 ns UNIT 6 POST OFFICE BOX 655303 • DALLAS.6 SN74LS04 MIN TYP‡ MAX −1.1 20 −0.75 2 0. and the duration of the short-circuit should not exceed one second.7 −0. VCC = MIN. VIH = 2 V VI = 7 V VI = 2.7 V VI = 0.4 0. SN7404.4 V −20 VI = 0 V VI = 4.25 0. TA = 25°C (see Figure 1) PARAMETER tPLH tPHL FROM (INPUT) A TO (OUTPUT) Y TEST CONDITIONS MIN RL = 400 Ω.25 UNIT V V V mA mA °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation.4 −100 2. Refer to the TI application report. TEST CONDITIONS† II = − 18 mA VIL = MAX.6 −20 1. VCC = MAX. Implications of Slow or Floating CMOS Inputs.4 0. VCC = 5 V. VCC = MAX.6 SN54LS04 MIN TYP‡ MAX −1. TEXAS 75265 . § Not more than one output should be shorted at a time.4 mA IOL = 4 mA IOL = 8 mA 0.4 0. VI = 0 V VI = 4.7 V VI = 0.8 −1 20 70 SN74S04 NOM 5 MAX 5. SN54S04. SN7404. TEXAS 75265 7 .7 3.5 5 ns ns UNIT POST OFFICE BOX 655303 • DALLAS.5 MIN 4.4 0. SN54LS04.5 V TEST CONDITIONS† II = − 18 mA VIL = 0.5 1 50 −2 −100 24 54 −40 15 30 2.SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 SN5404. SN74LS04. and the duration of the short-circuit should not exceed one second. use the appropriate value specified under recommended operating conditions.5 V VI = 2. VCC = MAX. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL II IIH IIL IOS§ ICCH ICCL VCC = MIN. VCC = MIN.5 5 MAX 4.5 SN54S04 TYP‡ MAX −1. VCC = MIN.8 V. TA = 25°C.25 UNIT V V V mA mA °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation.5 V −40 15 30 MIN 2.2 IOH = −1 mA IOL = 20 mA 3.5 2 0. RL = 280 Ω. ‡ All typical values are at VCC = 5 V. VCC = MAX VCC = MAX.75 2 0. literature number SCBA004. VCC = 5 V. § Not more than one output should be shorted at a time. switching characteristics.8 −1 20 125 0 NOM 5 MAX 5. VI = 5. VCC = MAX.5 1 50 −2 −100 24 54 MIN SN74S04 TYP‡ MAX −1. TA = 25°C (see Figure 1) PARAMETER tPLH tPHL tPLH tPHL FROM (INPUT) A A TO (OUTPUT) Y Y TEST CONDITIONS MIN RL = 280 Ω. Implications of Slow or Floating CMOS Inputs. VCC = MAX. CL = 15 pF CL = 50 pF SN54S04 SN74S04 TYP 3 3 4.4 0. VCC = MAX. VIH = 2 V. Refer to the TI application report. SN74S04 HEX INVERTERS recommended operating conditions (see Note 3) SN54S04 MIN VCC VIH VIL IOH IOL TA Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Operating free-air temperature −55 4.2 UNIT V V V mA µA mA mA mA mA † For conditions shown as MIN or MAX. tr and tf ≤ 7 ns for Series 54/74 devices and tr and tf ≤ 2.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES Waveform 2 (see Notes C and D) 3V 1. tPHZ.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V tPHL VOH 1. and tPLZ. Waveform 1 is for an output with internal conditions such that the output is low. S1 and S2 are closed for tPLH.5 V VOL tPHZ VOH 1. tPHL.5 ns for Series 54S/74S devices. S1 is closed and S2 is open for tPZL. All diodes are 1N3064 or equivalent.5 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES. ZO ≈ 50 Ω. Load Circuits and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS. E.5 V 0V tPLH In-Phase Output (see Note D) tPHL Out-of-Phase Output (see Note D) 1. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz.5 V 0V tPLZ ≈1. D.5 V 1. F. S1 is open and S2 is closed for tPZH.5 V LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V 1.5 V VOL tPLH 1. 3-STATE OUTPUTS NOTES: A. except when disabled by the output control. Figure 1.SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 SN5404. SN74S04 HEX INVERTERS PARAMETER MEASUREMENT INFORMATION SERIES 54/74 AND 54S/74S DEVICES VCC Test Point VCC VCC RL From Output Under Test CL (see Note A) RL (see Note B) From Output Under Test CL (see Note A) Test Point S2 Test Point RL S1 (see Note B) 1 kΩ From Output Under Test CL (see Note A) LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS High-Level Pulse LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS Timing Input tsu 1. C.5 V Low-Level Pulse 1. except when disabled by the output control.5 V 1. CL includes probe and jig capacitance. SN7404.5 V 0V th 3V 1. Waveform 2 is for an output with internal conditions such that the output is high. with one input transition per measurement. SN54LS04.5 V VOLTAGE WAVEFORMS PULSE DURATIONS Output Control (low-level enabling) tPZL Waveform 1 (see Notes C and D) tPZH VOH 1.5 V ≈1. SN54S04. TEXAS 75265 .5 V 1. SN74LS04.5 V 3V Input 1.5 V Data Input 1. B.5 V tw 1.5 V VOL + 0. The outputs are measured one at a time.5 V VOH − 0. 3 V 0V th 3V 1.3 V Data Input 1. F. SN74S04 HEX INVERTERS PARAMETER MEASUREMENT INFORMATION SERIES 54LS/74LS DEVICES VCC Test Point VCC VCC RL From Output Under Test CL (see Note A) RL (see Note B) From Output Under Test CL (see Note A) Test Point S2 Test Point RL S1 (see Note B) 5 kΩ From Output Under Test CL (see Note A) LOAD CIRCUIT FOR 2-STATE TOTEM-POLE OUTPUTS High-Level Pulse LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS Timing Input tsu 1. Figure 2.3 V Low-Level Pulse 1. D. tPHZ. Waveform 1 is for an output with internal conditions such that the output is low. 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. G. tr ≤ 1. SN54LS04.5 V 3V Input 1. SN7404. The outputs are measured one at a time.3 V 0V tPLH In-Phase Output (see Note D) tPHL Out-of-Phase Output (see Note D) 1. S1 and S2 are closed for tPLH.3 V tPHL VOH 1.SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004 SN5404.5 V VOL + 0.5 ns.3 V 0V tPLZ ≈1. tPHL. SN54S04.3 V VOLTAGE WAVEFORMS PULSE DURATIONS Output Control (low-level enabling) tPZL Waveform 1 (see Notes C and D) tPZH VOH 1.5 V VOL tPHZ VOH 1.6 ns. C. SN74LS04. B. Waveform 2 is for an output with internal conditions such that the output is high. ZO ≈ 50 Ω.3 V 1.3 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1. E. S1 is open and S2 is closed for tPZH.3 V 1. except when disabled by the output control.5 V ≈1. with one input transition per measurement. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz.3 V VOH − 0. tf ≤ 2.3 V LOAD CIRCUIT FOR 3-STATE OUTPUTS 3V 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS. S1 is closed and S2 is open for tPZL. except when disabled by the output control. and tPLZ.3 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES.3 V VOL tPLH 1. TEXAS 75265 9 .3 V 1.3 V tw 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES Waveform 2 (see Notes C and D) 3V 1. All diodes are 1N3064 or equivalent. ti.PACKAGE OPTION ADDENDUM www.com 15-Oct-2009 PACKAGING INFORMATION Orderable Device JM38510/00105BCA JM38510/00105BDA JM38510/07003BCA JM38510/30003B2A JM38510/30003BCA JM38510/30003BDA JM38510/30003SCA JM38510/30003SDA SN5404J SN54LS04J SN54S04J SN7404D SN7404DE4 SN7404DG4 SN7404DR SN7404DRE4 SN7404DRG4 SN7404N SN7404N3 SN7404NE4 SN7404NSR SN7404NSRE4 SN7404NSRG4 SN74LS04D SN74LS04DE4 SN74LS04DG4 SN74LS04DR SN74LS04DRE4 SN74LS04DRG4 SN74LS04J Status (1) ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE Package Type CDIP CFP CDIP LCCC CDIP CFP CDIP CFP CDIP CDIP CDIP SOIC SOIC SOIC SOIC SOIC SOIC PDIP PDIP PDIP SO SO SO SOIC SOIC SOIC SOIC SOIC SOIC CDIP Package Drawing J W J FK J W J W J J J D D D D D D N N N NS NS NS D D D D D D J Pins Package Eco Plan (2) Qty 14 14 14 20 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 25 1 1 1 1 1 1 1 1 1 1 1 50 50 50 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Lead/Ball Finish A42 A42 A42 A42 A42 A42 A42 A42 A42 A42 CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI MSL Peak Temp (3) N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type Call TI N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Call TI POST-PLATE N / A for Pkg Type 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 25 Pb-Free (RoHS) TBD Pb-Free (RoHS) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 50 50 50 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) TBD Addendum-Page 1 . ti. Samples may or may not be available. LIFEBUY: TI has announced that the device will be discontinued. and a lifetime-buy period is in effect. Pb-Free (RoHS Exempt).PACKAGE OPTION ADDENDUM www.please check http://www.The planned eco-friendly classification: Pb-Free (RoHS).ti. PREVIEW: Device has been announced but is not in production. Addendum-Page 2 . but TI does not recommend using this part in a new design. OBSOLETE: TI has discontinued the production of the device. NRND: Not recommended for new designs. (2) Eco Plan . Device is in production to support existing customers.com/productcontent for the latest availability information and additional product content details.com 15-Oct-2009 Orderable Device SN74LS04N SN74LS04N3 SN74LS04NE4 SN74LS04NSR SN74LS04NSRG4 SN74S04D SN74S04DE4 SN74S04DG4 SN74S04DR SN74S04DRE4 SN74S04DRG4 SN74S04N SN74S04N3 SN74S04NE4 SN74S04NSR SN74S04NSRE4 SN74S04NSRG4 SNJ5404J SNJ5404W SNJ54LS04FK SNJ54LS04J SNJ54LS04W SNJ54S04FK SNJ54S04J SNJ54S04W (1) Status (1) ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type PDIP PDIP PDIP SO SO SOIC SOIC SOIC SOIC SOIC SOIC PDIP PDIP PDIP SO SO SO CDIP CFP LCCC CDIP CFP LCCC CDIP CFP Package Drawing N N N NS NS D D D D D D N N N NS NS NS J W FK J W FK J W Pins Package Eco Plan (2) Qty 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 20 14 14 20 14 14 25 25 25 Pb-Free (RoHS) TBD Pb-Free (RoHS) Lead/Ball Finish CU NIPDAU Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU Call TI CU NIPDAU CU NIPDAU CU NIPDAU CU NIPDAU A42 A42 A42 A42 A42 A42 MSL Peak Temp (3) N / A for Pkg Type Call TI N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type Call TI N / A for Pkg Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type N / A for Pkg Type 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 50 50 50 Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 2500 Green (RoHS & no Sb/Br) 25 Pb-Free (RoHS) TBD Pb-Free (RoHS) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 2000 Green (RoHS & no Sb/Br) 1 1 1 1 1 1 1 1 TBD TBD TBD TBD TBD TBD TBD TBD POST-PLATE N / A for Pkg Type POST-PLATE N / A for Pkg Type The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. or Green (RoHS & no Sb/Br) . TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package.1% by weight in homogeneous materials.ti. and peak solder temperature. including the requirement that lead not exceed 0. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible). Where designed to be soldered at high temperatures.com 15-Oct-2009 TBD: The Pb-Free/Green conversion plan has not been defined. and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0. TI and TI suppliers consider certain information to be proprietary. and thus CAS numbers and other limited information may not be available for release. Peak Temp. TI bases its knowledge and belief on information provided by third parties. -. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 3 . Efforts are underway to better integrate information from third parties. or 2) lead-based die adhesive used between the die and leadframe. and makes no representation or warranty as to the accuracy of such information. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances.PACKAGE OPTION ADDENDUM www.The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.1% by weight in homogeneous material) (3) MSL. 0 10.ti.5 2.0 16.5 8.1 2.0 16.0 330.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SOIC SO SOIC SO SOIC SO D NS D NS D NS 14 14 14 14 14 14 SPQ Reel Reel Diameter Width (mm) W1 (mm) 330.0 330.5 2.0 330.1 2.4 16.0 12.5 8.2 6.4 16.0 330.0 12.0 8.0 8.PACKAGE MATERIALS INFORMATION www.0 Q1 Q1 Q1 Q1 Q1 Q1 SN7404DR SN7404NSR SN74LS04DR SN74LS04NSR SN74S04DR SN74S04NSR 2500 2000 2500 2000 2500 2000 6.0 330.5 2.4 16.4 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 8.5 9.4 16.0 16.0 10.0 12.5 Pack Materials-Page 1 .1 2.5 8.0 16.5 9.0 W Pin1 (mm) Quadrant 16.4 16.2 9.0 10.0 16.0 16.2 6. 0 346.0 346.0 346.0 346.0 Height (mm) 33.ti.0 33.0 Width (mm) 346.0 346.0 33.PACKAGE MATERIALS INFORMATION www.0 33.com 11-Mar-2008 *All dimensions are nominal Device SN7404DR SN7404NSR SN74LS04DR SN74LS04NSR SN74S04DR SN74S04NSR Package Type SOIC SO SOIC SO SOIC SO Package Drawing D NS D NS D NS Pins 14 14 14 14 14 14 SPQ 2500 2000 2500 2000 2500 2000 Length (mm) 346.0 346.0 Pack Materials-Page 2 .0 346.0 346.0 33.0 346.0 33.0 346. . . 442 (11.14) 0.25) 0.010 (0.63) 0.047 (26.83) 1.59) MIN 0.89) 4040140 / D 10/96 NOTES: A.045 (1.6) 1.69) 0.58) 0.25) 0. B.458 (11.23) 0.6) B MAX 0. This drawing is subject to change without notice.43) 1.080 (2.51) 0.035 (0.09) 0.660 (16.055 (1. D.09) 0.14) 0.63) 0.76) 0.020 (0.14) 0.063 (27.358 (9.8) 1.035 (0.045 (1.89) 0.560 (14. This package can be hermetically sealed with a metal lid. E.560 (14. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS.165 (29.99) MAX 0.022 (0.27) 0.141 (28.51) 0.028 (0.045 (1.22) 0.020 (0.850 (21.58) 0.938 (23.26) 0.54) 0.307 (7.40) 0. OF TERMINALS ** 11 10 28 9 8 7 6 68 5 84 44 52 20 A MIN 0.03) 0.31) 0.342 (8.71) 0.739 (18.495 (12. All linear dimensions are in inches (millimeters).78) 0.22) 0.050 (1.63) 0. The terminals are gold plated.495 (12.MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) 28 TERMINAL SHOWN LEADLESS CERAMIC CHIP CARRIER 18 17 16 15 14 13 12 NO.858 (21.010 (0.761 (19.32) 0.358 (9. C.458 (11.0) 19 20 21 B SQ 22 A SQ 23 24 25 26 27 28 1 2 3 4 0. TEXAS 75265 .80) 0.640 (16.406 (10.962 (24.064 (1. . . . . ti. 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