4/29/2014More "Setup and Hold Time Violation" : Static Timing Analysis (STA) basic (Part 3b) | VLSI Concepts Next Blog» VLSI Concepts You will find the basics of VLSI design in this place. Home Content VLSI BASIC STA & SI Extraction & DFM Vlsi Interview Questions VLSI Glossary VLSI Forum Recommended Book About Us Friday, April 8, 2011 Translate page "Setup and Hold Time Violation" : Static Timing Analysis (STA) basic (Part 3b) Index Chapter1 Introduction Part2 Part6a Chapter2 Static Timing Analysis Part3a Part6b Part3b Part6c Part3c Part7a Chapter3 Signal Integrity Part4a Part7b Part4b Part7c Part4c Part 8 Part5a Search This Blog Loading... Am azon Search Part1 Part5b Static Timing analysis is divided into several parts: Part1 -> Timing Paths Part2 -> Time Borrowing Part3a -> Basic Concept Of Setup and Hold Part3b -> Basic Concept of Setup and Hold Violation Part3c -> Practical Examples for Setup and Hold Time / Violation Part4a -> Delay - Timing Path Delay Part4b -> Delay - Interconnect Delay Models Part4c -> Delay - Wire Load Model Part5a -> Maximum Clock Frequency Part5b -> Examples to calculate the “Maximum Clock Frequency” for different circuits. Part 6a -> How to solve Setup and Hold Violation (basic example) Part 6b -> Continue of How to solve Setup and Hold Violation (Advance examples) Part 6c -> Continue of How to solve Setup and Hold Violation (more advance examples) Part 7a -> Methods for Increase/Decrease the Delay of Circuit (Effect of Wire Length On the Slew) Part 7b -> Methods for Increase/Decrease the Delay of Circuit (Effect of Size of the Transistor On the Slew) Part 7c -> Methods for Increase/Decrease the Delay of Circuit (Effect of Threshold voltage On the Slew) Part 8 -> 10 ways to fix Setup and Hold Violation. Popular Posts Subscribe To VLSI EXPERT Total Pageview s 825,266 Posts Comments Here we will discuss how to calculate the Setup and Hold Violation for a design. Till now we have discussed setup and hold violation with respect to the single flipflop, now lets extend this to 2 flip flop. In the following fig there are 2 flipflops (FF1 and FF2). "Timing Paths" : Static Timing Analysis (STA) basic (Part 1) "Examples Of Setup and Hold time" : Static Timing Analysis (STA) basic (Part 3c) "Setup and Hold Time Violation" : Static Timing Analysis (STA) basic (Part 3b) "Setup and Hold Time" : Static Timing Analysis (STA) basic (Part 3a) "Time Borrowing" : Static Timing Analysis (STA) basic (Part 2) http://www.vlsi-expert.com/2011/04/static-timing-analysis-sta-basic-part3b.html#.U1-UU1WSwkw Synopsys Design 1/7 Data should be stable "Ts" time before the positive edge at FF2/C. then we can say that the data launched from FF1 at time 10ns does not get propagated so soon that it reaches at FF2 before time (10+0. From the Fig its clear that if Slack= Required Time . Setup is check ed at next clock edge.5ns after the clock edge at FF2). Data should be stable "Th" time after the positive edge at FF2/C. Means there should not be any change in the Input data at FF2/D between positive edge of clock at FF2 at Time=10ns and Time=10ns+Th. basic (Part 1) |VLSI Maharashtra arrived from Concepts" 7 mins ago google.Arrival time < 0 (-ive) . For Hold Analysis at FF2.yahoo. Means if data is launched at time=0ns from FF1 then it should be captured at time=10ns by FF2. its reported Hold violation.U1-UU1WSwkw 2/7 . So I can say that Launching Flip-Flop is FF1 and Capturing Flip-Flop is FF2. Hold is check ed at same clock edge. then. If Th=0.Signal has to be propagate through Data path in one clock cycle. With the above explanation I can say 2 important points: 1."Interconnect Delay Models" : Static Timing Analysis (STA) basic (Part 4b) "Delay .5ns.Timing path Delay" : Static Timing Analysis (STA) basic (Part 4a) Single-Cycle Setup and Hold For Flip-Flops Recent Visitors Few important things to note down hereData is launching from FF1/D to FF1/Q at the positive clock edge at FF1/C. data can't be stable at FF2 for time=0. it is reported as Setup Violation. data launched from FF1 at time=0ns should arrive at D of FF2 before or at time=(10ns-1ns)=9ns. input data is coming from FF1/Q through a combinational logic.co. Where "Ts" is the Setup time of FF2.vlsi-expert.5ns from FF1 to FF2. 3c) |VLSI Concepts" Karnataka left ""Time 1 min ago Borrowing" : Static Timing Analysis (STA) basic (Part 2) |VLSI Concepts" via A visitor from Indore. 2. So for Setup analysis at FF2.4/29/2014 "Setup and Hold Time Violation" : Static Timing Analysis (STA) basic (Part 3b) | VLSI Concepts Synopsys Design Constraints (SDC) Basics Antenna Effects Basic of Timing Analysis in Physical Design Delay . If data arrive so soon (means with in 0.com and viewed ""Timing Paths" : Static Timing Analysis (STA) A visitor from Mumbai. Where "Th" is the Hold time of FF2. at the positive clock edge at FF2/C. At FF2/D . then . 1 vlsi-expert. then there is a Setup violation at FF2. If Ts=1ns. Karnataka arrived from google. So Data path is FF1/C --> FF1/Q --> FF2/D For a single cycle circuit. Pessimism (CRP) basic |VLSI Concepts" 22 Dun. Hold Check timing can be more clear with the help of following circuit and explanation. Live Traffic Feed A visitor from Bangalore.5ns ( Or say it should reach from FF1 to FF2 with in 0.search.5ns).in and viewed ""Examples Of Setup and Hold time" : Static Timing Analysis basic (Part A visitor (STA) from Bangalore. If Ts=0ns. mins A visitor from Dehra ago Blog Archive Uttaranchal viewed ""Examples Of Setup and ► 2014 Hold time" : Static Timing ► 2013 Analysis (STA) basic (Part ► 2012 A visitor from Bangalore. 3c) |VLSI Concepts" 23 Karnataka mins ago viewed "VLSI ▼ 2011 Concepts: Content" 24 mins ► September ago A visitor from Chennai. it is reported as Setup Violation. Setup Check timing can be more clear for the above Flip-flop combination with the help of following explanation.com Madhya min ago Pradesh arrived from in.yhs4.in and viewed ""Setup and Hold Time Violation" : Static Timing Analysis basic (Part A visitor (STA) from Hyderabad.com and viewed "CMOS A visitor BASIC from Bangalore. To satisfy the Hold Condition at FF2 for the Data launched by FF1 at 0ns. If data takes too long ( greater then 10ns) to arrive (means it is not stable before clock edge at FF2) .blogspot.5)=10. 3b) |VLSI Concepts" 10 Andhra Pradesh viewed mins ago "Clock Reconvergence Setup Check Timing In the above fig you can see that the data launched by FF1/D ( at launch edge) reaches at FF2/D after a specific delay ( CLK-to-Q delay + Conminational Logic Delay) well before the setup time requirement of Flip-Flop FF2.com/2011/04/static-timing-analysis-sta-basic-part3b. data launched from FF1 at time=0ns should arrive at D of FF2 before or at time=10ns. the data launched by FF1 at 10ns should not reach at FF2/D before 10ns+Th time. LOGIC |VLSI Karnataka arrived from Concepts" 2 mins ago vlsi-expert. If data takes too long (greater then 9ns) to arrive (means it is not stable before 1ns of clock edge at FF2). ► August Tamil Nadu viewed "Fixing ► May Setup and Hold Violation : ▼ April Static Timing Analysis "Setup and H (STA) Basic ( Part 6a) A visitor from United |VLSI Concepts" 25 mins Kingdom left ""Setup and ago Hold Time Violation" : "Setup and H Static Timing Analysis (STA) basic (Part 3b) Real-time view · Menu ► March ► February ► 2010 ► 2008 http://www. so there is no setup violation.html#.co. Data is capturing at FF2/D. .U1-UU1WSwkw 3/7 .. We will discuss all these later sometime. at the end sir has written that to avoid it. But the complexity increases in case of multi-cycle path .. the change in the FF1/Q propagates very soon. You can see that desired data which suppose to capture by CLKB at FF2. since hold checks are done for the same clock cycle? Reply Replies your VLSI Hi. I didn't get you question very clearly. just to show the http://www.D should be at Zero (0) logic state and be constant long enough after the CLKB capture edge to meet hold requirement but because of very short logic delay between FF1/Q and FF1/D. 2012 at 10:18 AM Anonymous May 19.c <<< Previous Next >>> Posted by your VLSI at 12:45 AM Reactions: VLSI Design+Digital+ Project 4Weeks Course+Certific forRs9900 Need M ore (1) Excellent (2) Good (2) Interesting (0) 25 comments: Anonymous February 2. February 7. 2012 at 2:57 AM should not the launch edge be the second rising edge of CLK. either decrease the buffers in the clock path or increase the delay in the data so that the data arrives at or before the capturing edge of the clock b.com/2011/04/static-timing-analysis-sta-basic-part3b. Setup and Hold violation calculation for the single clock cycle path is very easy to understand.which is a hold violation and we l loose data.vlsi-expert. Flip-flop using different clocks.Gated clock.4/29/2014 "Setup and Hold Time Violation" : Static Timing Analysis (STA) basic (Part 3b) | VLSI Concepts Am azon Deal Hold Check Timing In the above fig you can see that there is a delay in the CLK and CLKB because of the delay introduced by the series of buffer in the clock path. As a result of that there occurs a Hold violation.. Now Flip-flop FF2 has a hold requirement and as per that data should be constant after the capture edge of CLKB at Flip-flop FF2. Please elaborate it. Latches in place of Flip-Flop. Maven O Summer se vlsitraining. but sir has written and shown in the diagram that the data is arriving at the ff2 d before the clock b and it is in the transition region.html#. 2012 at 9:20 AM dear clock checks ideally should be done at the rising or capturing edge of clock b only.. This type of violation (Hold Violation) can be fixed by shortening the delay in the clock line or by increasing the delay in the data path. U1-UU1WSwkw 4/7 . It should be FF2/D. It has" because of very short logic delay between FF1/Q and FF1/D" Its FF2/D your VLSI May 2.. 2012 at 12:00 PM jigs January 15. 2013 at 5:00 PM sir i don't understand. 2013 at 3:20 PM thank you Reply Anonymous March 14.. do u have nay idea about datapulse violations Reply jigs October 26. setup check at next clock edge and hold check at same clock edge. 2012 at 11:53 AM Thank you very much. For a particular FF.4/29/2014 "Setup and Hold Time Violation" : Static Timing Analysis (STA) basic (Part 3b) | VLSI Concepts hold violation sir has made the same in the diagram Reply Anonymous February 15. 2012 at 11:44 AM thanks man . sir! Can you please correct the misprint in the original post just in case readers do not see the comment? Thanks again! Reply hairol March 3. 2012 at 12:38 AM hi . You are right.com/2011/04/static-timing-analysis-sta-basic-part3b. while launching and capturing edge are different. 2012 at 10:20 AM is setup and hold time for given input slew is constant? Reply jigs October 26. Reply Sravan Tekuru July 13. 2012 at 4:42 PM I think there is misprint in hold time analysis Reply Replies your VLSI February 16. 2012 at 12:46 PM 3rd Paragraph from last.. 2012 at 10:21 AM i:e Ts+Th=constant Reply Replies your VLSI Hi Jigs. 2012 at 12:10 AM can you please let me know what's that misprint? Anonymous April 29.. plz explain http://www.html#. power PufF! June 13.vlsi-expert. 2013 at 7:10 AM plz can u explain me ? Reply Anonymous March 7.. October 26. these numbers are always constant. 2012 at 10:38 PM Thank you so much for the excellent tutorial.. I hope you got my point. 2013 at 9:18 AM In the Hold Check Timing diagram. 2014 at 11:46 PM Data can arrive at the following flip flop only at the next clock edge. As for the figures posted above. even before we get to the second rising edge of CLKB.com/2011/04/static-timing-analysis-sta-basic-part3b. We check both at next clock edge and calculate also like that but why we say diffrently? Please elaborate Reply Replies Anonymous February 23.considered as launching edge but when this edge reaches capturing FF. 2014 at 5:21 PM Can you please elaborate why setup check at next clock edge and hold check at same clock edge ? from CLK1 . is correct. which though. Reply Anonymous March 26. T2 = T1 + T(clk). Could you please clarify me if you are talking about reducing the CLKB clock width? Reply Anonymous August 30. FF1 generated its output to data D1. I would say .html#. Reply Anonymous May 14. 2013 at 7:56 PM Thank you sir. 2013 at 3:51 PM yyyy Reply Anonymous October 4. At T1. Reply mrmittal January 21. 2013 at 8:30 PM Hi VLSI Expert. Reply Replies your VLSI February 24. and so naturally for the same clock cycle. You have mentioned that we need to reduce the delay of the clock to avoid the hold time violation right. highlighting the same. means every thing is related to Capturing edge. I've already posted a comment below. since T(launch) and T(capture) must be at the same clock cycle.check the pic more closely and you will crack this figure also. But for analysis purpose of Hold . FF2 will be able to process FF1's output to D1 only at the next clock edge. 2014 at 11:40 PM In the Hold Time diagram. I think the one for Hold Time is perhaps erroneous.. The Set-up Time diagram. whereas it should be at the same clock edge (delayed by buffers). Reply http://www. 2014 at 1:51 PM For the same data Capture and launch edges are always one clock cycle. Still If some confusion. the Capture edge has been shown one clock cycle after Launch edge. 2013 at 11:26 PM Clock edge at Launching FF . So this will result in setup violation (and maybe hold violation too). it become Capturing Edge. Hold analysis is done only after the data has already arrived.U1-UU1WSwkw 5/7 . Awaiting yourVLSI's reply! Reply Anonymous February 23. it looks like the first transition of FF2/D (1 > 0) happens at about the same time as the first rising edge of CLKB. Now in setup and hold we are talking every thing on the Capturing FF. I got your point. whereas FF2 was processing FF1's output to data D0. please write in detail about your confusion.vlsi-expert. too uses the same clock edges.4/29/2014 Reply Replies your VLSI "Setup and Hold Time Violation" : Static Timing Analysis (STA) basic (Part 3b) | VLSI Concepts March 14..you analysis the whole concept at the same edge. .html#. by Simon Monk Follow ers http://www. by Paul Scherz Programming Arduino Getting Started with Sk..U1-UU1WSwkw 6/7 . Third ..com/2011/04/static-timing-analysis-sta-basic-part3b.com VLSI Design+Digital+Verilog+Project 4Weeks Course+Certificate forRs9900 ebooks and Referance eBooks and Reference Material Electrical & Electronics Shopping Cart Make: Electronics: Learning Through Discovery by Charles Platt Practical Electronics for Inventors.vlsi-expert..4/29/2014 "Setup and Hold Time Violation" : Static Timing Analysis (STA) basic (Part 3b) | VLSI Concepts Links to this post Create a Link Newer Post Subscribe to: Post Comments (Atom) Home Older Post Maven Online SummerCourse vlsitraining. http://www.html#. Simple template.com/2011/04/static-timing-analysis-sta-basic-part3b. Powered by Blogger. Vlsi expert group.4/29/2014 "Setup and Hold Time Violation" : Static Timing Analysis (STA) basic (Part 3b) | VLSI Concepts Follow by Em ail Email address..vlsi-expert..U1-UU1WSwkw 7/7 .
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