A Project report onPOWER FACTOR CORRECTION WITH A NEW MODIFIED SEPIC CONVERTER Project report submitted to Shanmugha Arts, Science, Technology & Research Academy SASTRA UNIVERISTY in partial fulfillment of the requirements for the award of the Degree of B.Tech (Part-time) in ELECTRICAL & ELECTRONICS ENGINEERING Submitted by BALAMURUGAN P MUSARRAF HOSSIAN SEKH SATHIYA SEELAN S 010983003 010983009 010983017 GUIDED BY Mr. S.Mohamed Ghouse, Assistant Professor-II, EEE/ SEEE, SASTRA University, Thanjavur Department of Electrical & Electronics Engineering School of Electrical & Electronics Engineering Shanmugha Arts, Science, Technology & Research Academy SASTRA UNIVERSITY Thirumalaisamudram, Thanjavur - 613 403 SCHOOL OF ELECTRICAL & ELECTRONICS ENGINEERING SASTRA UNIVERSITY BONAFIDE CERTIFICATE This is to certify that the project work entitled “POWER FACTOR CORRECTION WITH A NEW MODIFIED SEPIC CONVERTER” is the bonafide work done by Balamurugan P (010983003), Musarraf Hossain Sekh (010983009), Sathiya Seelan S (010983017) Students of VII Semester, B.Tech (Part-time) in Electrical & Electronics Engineering during the academic year 2008-2009 in partial fulfillment of the requirement for the award of Degree of Bachelor of Technology in Electrical and Electronics (Part-time) at SASTRA University. __________________ Project Guide __________________ Dean, SEEE Submitted for the University Exam held on _ _ _ _ _ _ _ _ _ _ __________________ Internal Examiner __________________ External Examiner SCHOOL OF ELECTRICAL & ELECTRONICS ENGINEERING SASTRA UNIVERSITY DECLARATION We submit this project entitled “POWER FACTOR CORRECTION WITH A NEW MODIFIED SEPIC CONVERTER” to SASTRA University, Tirumalaisamudram-613401, in partial fulfillment of the award of B.Tech., Degree in ELECTRICAL & ELECTRONICS ENGINEERING and we in full consciousness, declare this dissertation as our original and independent work carried out under the guidance of Mr. S.Mohamed Ghouse, Assistant Professor II, School of Electrical & Electronics Engineering, SASTRA University. Date : _ _ _ _ _ _ _ _ _ Place : _ _ _ _ _ _ _ _ _ Signature : 1. 2. 3. ______________ ______________ ______________ ACKNOWLEDGEMENT We would like to thank the management, our honorable Vice-Chancellor, Prof. Dr. R.SETHURAMAN, Dean, Planning and our and esteemed Development, Registrar, S.VAIDHYASUBRAMANIAM Dr.S.N.SRIVASTAVA, for giving us this opportunity to develop our knowledge and sharpen our technical skills. We are also grateful to the Dean, School of Electrical & Electronics Engineering, Prof. P.S. SRINIVASAN, for giving us an invaluable support on how to proceed with the project. We are extremely thankful to our Project coordinator Prof. R. MURALI SACHITHANANDAM, Senior Assistant Professor, School of Electrical & Electronics Engineering for lending us support in completing the project. We would like to convey our heartfelt thanks to our internal guide Mr. S.MOHAMED GHOUSE, Assistant Professor II, School of Electrical & Electronics Engineering, for guiding us in the best possible manner all through the project. Lastly, we are thankful to our parents and other family members for the encouragement and moral support which they have been giving us in abundance. CONTENTS 1. OVERVIEW 1.1 1.2 1.3 1.4 1.5 Abstract Goal Objective Project plan Main components used 1 2 2 2 3 4 5 7 8 9 9 10 10 10 11 11 11 12 13 15 15 22 23 23 23 25 26 26 27 27 27 28 28 28 28 2. INTRODUCTION 3. NEED FOR THIS PROJECT AND ITS ADVANTAGES 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 What is power factor? Need for power factor correction Various methods for power factor correction What is a SEPIC? Why SEPIC converter for power factor correction? Problems of conventional SEPIC PFC Proposed modified SEPIC PFC Soft switching Soft switching benefits 4. CIRCUIT DIAGRAM AND WORKING PRINCIPLE 4.1 4.2 4.3 Power circuit configuration Conceptual waveforms Working principle of the proposed PFC 5. DESIGNE OF THE PROPOSED PFC 5.1 DESIGN OF MODIFED SEPIC PFC 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 5.2 Selection of duty cycle Selection of inductor Selection of MOSFET Selection of diodes Selection of tank inductor Selection of tank capacitor Selection of load DESIGN OF GATE CONTROL CIRCUIT 5.2.1 5.2.2 5.2.3 5.2.4 Selection of control voltage Selection of Op-Amp Selection of NOT gate Selection of MOSFET gate driver circuit 6. SOFTWARE SIMULATION 6.1 6.2 Simulation software Simulation results 29 31 32 35 37 40 40 41 43 44 52 64 72 78 92 93 7. HARDWARE PROTO TYPE IMPLEMENTATION AND TESTINGS 7.1 7.2 7.3 Measurements of key waveforms Measurements of power factor Measurements of efficiency 8. CONCLUSION 9. APPENDIX 9.1 9.2 9.3 9.4 9.5 9.6 10. Datasheet for LM 7812 Datasheet for LM 347 Datasheet for IRFP 460 Datasheet for CD4049 Datasheet for MIC 6a4 Datasheet for IR 2110 REFERENCES OVERVIEW Page 1 . 1. which generate current harmonics. analyzed and implemented along with required software simulations to establish the thought. 1. Implementing a prototype the hardware model of the same to establish the thought Page 2 . 1. 1. Analyze and compare the characteristic of a conventional SEPIC PFC versus our modified SEPIC based PFC. produce power pollution and result in low power factor. 3. Hence in this project.e. A prototype will be designed.1 ABSTRACT: Power electronic devices with front-end rectifier are widely used in industry. The switching loss is reduced by applying soft switching topology i. But the conventional SEPIC converters suffer from high switching losses.3 OBJECTIVE: 1. Software Modelling and Simulation of the modified SEPIC based PFC to achieve unity power factor with lower switching losses using soft switching topology. zero voltage switching (ZVS). 2. SEPIC converter was the most successful one. a new modified SEPIC converter is proposed to achieve unity power factor at the mains side with greater efficiency.2 GOAL: Design and Implementation of a modified SEPIC based PFC to achieve unity power factor with higher efficiency. commerce and transportation. Though there are several proposed solutions to this. 4 PROJECT PLAN: Phase 1: Description of Activity: 1. Study and analysis of proposed modified SEPIC based PFC 6. Presentation on second review meet Phase 3: Description of Activity: 1. Study of Soft switching Topologies 5. Boost. Implementation and performance analysis of the hardware prototype 3. Observation and Inferences 4. Study of Buck. Submission of final report Page 3 . Literature Survey – IEEE . Reference Books and International conference papers 2. Designing the hardware prototype of the proposed modified SEPIC based PFC 2. Presentation on final review meet 5. Presentation on first review meet Phase 2: Description of Activity: 1. Designing the model of proposed modified SEPIC based PFC 2.1. Study and analysis of conventional SEPIC based PFC 4. Simulation and performance analysis of the proposed model 3. Buck-Boost and SEPIC converters 3. Comparison of conventional SEPIC based PFC vs proposed modified SEPIC based PFC 4. 5 MAIN COMPONENTS USED: 1.5. LM 7812 – A linear Voltage regulator 2.2 SEPIC PFC CIRCUIT: 1. COUPLING CAPACITOR 5. INDUCTOR–20mH 3.1 GATE CONTROL CIRCUIT: 1. IRFP 460 – POWER MOSFET 2. LM 347 – An OP-AMP 3. 230/12V Step down transformer 1. MIC 6A4 – POWER DIODE Page 4 . INDUCTOR–22µH 4.1. CD 4049U – A CMOS INVERTER 4. 1A . IR 2110 – A High Frequency MOSFET GATE DRIVER 5.5. FILTER CAPACITOR 6. 2. INTRODUCTION Page 5 . there are international harmonic standards (such as: IEC-1000 and IEC-555) to confine power pollution. Boost. is proposed for low output-voltage applications. Page 6 . The Buck-type PFC can obtain an output voltage smaller than ac input voltage. In addition. a modified SEPIC-type PFC. the SEPIC type possesses better performance in total harmonics distortion (THD). One is passive PFC. ZETA. ZETA. which is feasible to operate in discontinuous conduction mode.8. or continuous conduction mode. Low efficiency. SEPIC and Fly back. commerce and transportation. In order to meet the requirements of the standards. Passive-type PFC is mainly constructed by inductors and capacitors. Among the Cuk. Therefore. a soft-switching cell is embedded into the converter to achieve ZVS for efficiency improvement. For active type. SEPIC and Fly back PFC topologies. produce power pollution and result in low power factor. only a power factor of 0. the other is active one. of which topologies have Buck. active switch. Nevertheless. The Boost structure attains better power factor correction feature but its output voltage is higher than acside voltage and power components withstand high voltage stresses. However. which generate current harmonics. boundary conduction mode. Besides. heavy weight and large volume are its major disadvantages. Buck-Boost. The PFCs can be briefly classified into two types. efficiency and power factor correction. the input current waveforms of a device have to be shaped by a PFC to eliminate current harmonics and improve power factor. Cuk. there is a polarity reversal on the output and an isolation driver for active switch is required. power factor merely is improved to around 0.Power electronic devices with front-end rectifier are widely used in industry. Therefore. diode and energy-stored component are used to achieve near unity power factor.95 is met. The Buck-Boost PFC can obtain an output voltage magnitude either larger or smaller than the input. 3. NEED FOR THIS PROJECT AND ITS ADVANTAGES Page 7 . It is also the ratio of the real power or true power to the apparent power of the load.1 WHAT IS POWER FACTOR? There are several ways to define power factor of a load. It is the cosine of the phase angel (Φ) between the load voltage and load current. APPARENT POWER (S) in KVA Φ POWER FACTOR OR IMPEDANCE ANGLE TRUE POWER (P) in KW Fig2: Power Triangle of an Inductive load Page 8 . 3. Fig1: The voltage and current wave form of an Inductive load with Phase angle (Φ) 2. Such as 1. Page 9 . Cuk. Low efficiency. diode and energy-stored component are used to achieve near unity power factor. W=VICosΦ Where. V I = Mains Voltage across the load =Load current between the load Voltage and the load current CosΦ = Power factor of the load i. 3.2 NEED FOR POWER FACTOR CORRECTION: There are The power drawn by a load from AC Mains depends not only on Mains Voltage and Current but also on the Power Factor of the load. SEPIC and Fly back. active switch.e. the Cosine of the phase angle (Φ) As our supply mains voltage is maintained constant.3 VARIOUS METHODS FOR POWER FACTOR CORRECTION: There are two types of power factor correction (PFC) circuits. For active type. Besides. Passive-type PFC is mainly constructed by inductors and capacitors. heavy weight and large volume are its major disadvantages.3. This causes line pollution and reduces the power factor. power drawn by the load only depends on the load current and power factor from the above equation . Higher line loss reduces the transmission efficiency. it is clear that for a particular load if the power falls. Power drawn by a single phase load. ZETA. Hence in order to meet the international standards we must prevent the line harmonics and improve the power factor. of which topologies have Buck. Power electronic devices with front end rectifier which is widely used in industry takes high pulsating current from mains and produces severe current harmonics. That is why there always a need of power factor correction and power factor correction circuit. Buck-Boost. Boost.8. One is passive power factor correction circuit and the other is active power factor correction circuit. power factor merely is improved to around 0. the load current increases which results in higher current from supply mains and higher line loss. efficiency and power factor correction. The Boost structure attains better power factor correction feature but its output voltage is higher than ac-side voltage and power components withstand high voltage stresses.6 PROBLEMS OF CONVENTIONAL SEPIC PFC: The conventional SEPIC suffers from high switching losses as in the normal switching method (i. ZETA. the SEPIC type possesses better performance in total harmonics distortion (THD). only a power factor of 0. The voltage can be controlled by adjusting the duty cycle of the switch. The output voltage can be lesser.5 WHY SEPIC AS POWER FACTOR CORRECTION? The Buck-type PFC can obtain an output voltage smaller than ac input voltage. Nevertheless. discontinuous.95 is met. However. SEPIC and Fly back PFC topologies. hard switching).e. equal or higher than the input voltage. The output voltage is also non-inverted with respect to the input voltage. Page 10 . The Buck-Boost PFC can obtain an output voltage magnitude either larger or smaller than the input. there is a polarity reversal on the output and an isolation driver for active switch is required. power switches (MOSFETs) has to cut off the current within turn off period while the full DC rail voltage applied across it. 3.4 WHAT IS A SEPIC? A single ended primary inductance converter or SEPIC is basically a DC-DC converter which can operate in continuous. or boundary conduction mode. 3. Therefore the switch has to withstand high voltage as well as current stresses resulting in high switching losses and limiting the switching frequency. 3. Among the Cuk. Such as 1. 3. By this zero voltage or zero current conditions are created and the switching is performed at either zero voltage or zero current.3. The switching losses are reduced. The soft switching will reduce the switching losses thereby improving the efficiency. or boundary conduction mode for low output voltage applications. Magnetic components (such as inductor and its core) sizes are reduced. 3. 4. In 1980s the concept of resonant tank circuit was developed for switching.8 SOFT SWITCHING: In soft switching. The switching frequency can be increased to hundreds of Kilo Hertz 3. it is ensured that the voltage across the switch or current through the switch is zero or very low when they receive turns on signal or gate signal. continuous. 2. In addition to this a soft switching cell is embedded into the circuit to achieve Zero Voltage Switching.9 SOFT SWITCHING BENEFITS: There are several benefits of soft switching as compared to the conventional hard switching. By suitable introducing a resonant tank circuit along with the switch the oscillatory voltage or current waves are created across the switch.7 PROPOSED MODIFIED SEPIC PFC: Therefore in this project we propose a modified SEPIC PFC which is feasible to work in discontinuous. The power density of converters are increased Page 11 . CIRCUITS AND WORKING PRINCIPLE Page 12 . 4. 3. 4. an inductor Lr and a capacitor Cr is embedded into the PFC stage for ZVS. Page 13 . lowering overall efficiency and increasing cost. in which the PFC stage performs power factor correcting and steps down its input voltage to a desired level. a PFC and a dc/dc converter. a modified SEPIC configuration shown in Fig. as shown in Fig. 5. A soft-switching cell including an active switch Q2. as shown in Fig. it is required that a dc/dc converter is added to drop voltage for dc load.1 POWER CIRCUIT CONFIGURATION: For high line voltage or low output voltage applications. both diodes D5 and D6 prevent opposite current from flowing through inductor L1 and L2. the input voltage also is boosted. The PFC stage shapes a high-crest-factor current caused by the full-wave rectifier into a purely sinusoidal waveform to being in phase with line voltage. a PFC stage is cascaded with a full-wave rectifier in input and a step-down dc/dc converter in output. In this paper. Power is processed by two stages. However.5 is presented to serve as stepdown PFC stage. To release the aforementioned drawbacks. Therefore. respectively. a single-stage stepdown PFC is adopted. In Fig. 4. as illustrated in Fig6. Page 14 . over a switching cycle the operation of the PFC can be divided into eight modes. The eight operation modes during a switching period are discussed as following. Page 15 . which leads to unity power factor. a high power factor can readily be achieved.3 WORKING PRINCIPLE OF THE PROPOSED PFC While the modified soft-switching SEPIC PFC operates in boundary conduction mode (BCM) and with constant turn-on control. When the resonant frequency of the soft-switching cell is much higher than switching frequency of main power circuit. 7.2 CONCEPTUAL WAVEFORMS: 4. As a result. Fig.4. the envelope of the input current will follow the shape of line voltage to be sinusoidal. 8 is the corresponding circuits and the related conceptual key waveforms are shown in Fig. Meanwhile. the voltage vDS1 reaches vC2+vo and this mode is terminated. the capacitor C3 supplies power for dc load. The time constant determined by capacitance of C3 and dc-load resistance is much larger than switching period so that output voltage vo can be regarded as an constant. switch Q1 is turned on and Q2 off. Mode 2 [t1 ≤ t < t2. this mode is ended and Q2 is turned off. the capacitor C2 still dumps energy to L2 and dc load draws power from C3. Page 16 . Q1and D6.Mode 1 [t0 ≤ t < t1. the voltage vDS1 across Cb1 increases rapidly. The inductor currents of iL1 and iLr are linearly built and the capacitor C2 dumps energy to inductor L2 by the way of Lr. At t=t2. At time t=t1. Since typical value of Cb1 is far smaller than capacitance of C2. resonant inductor Lr and parasitical capacitor Cb1. At the same time. Fig8 (a)]: During this time interval. Fig8 (b)]: The inductor L1 discharges through the path of D5. Fig8 (c)]: During this time interval. inductors L1 and Lr still discharge energy and voltage vDS1 increases. the voltage vDS1 attains to vCr+vC1-vL1 and this mode is ended. At t=t3. Page 17 . Therefore. L2 dumps energy to output.Mode 3 [t2 ≤ t < t3. The diode D7 starts conducting and the voltage across L2 is equal to output voltage vo. The parasitical capacitor of switch Q2 starts dumping energy by the way of Cr and Lr until vDS2 drops to zero. Fig8 (d)]: Inductors L1 and L2 releases energy continuously but capacitor C2 charges.Mode 4 [t3 ≤ t < t4. Fig8 (e)]: The body diode of Q2 is on and inductor Lr resonates with Cr. switch Q2 is tuned on with ZVS. Page 18 . Mode 5 [t4≤ t < t5. During this time interval. Operation of the PFC enters to next mode as the current iLr decreases to zero. Q2 is turned off and this mode is terminated.Mode 6 [t5 ≤ t < t6. Fig (f)]: The energy stored in resonant capacitor Cr is dumped to Lr via Q2. At t=t6. the current iLr increases negatively. Page 19 . inductors L1 and L2 release energy but C2 charges. In this time period. As a result. at which switch Q1 is turned on again. Mode 8 [t7 ≤ t < t8]: The energy stored in Lr is discharges by the way of C2. switch Q1 is triggered. The stored energy in the parasitical capacitor Cb1 is drawn by inductor Lr and vDS1 decreases. C3 and Db1. Fig (g)]: Switches Q1 and Q2 are off. A complete switching cycle is ended at t=t8. In this time interval. D7.Mode 7 [t6 ≤ t < t7. Page 20 . This mode ends when vDS1 drops to zero. This mode is terminated while iLr equals zero. TON stands for on time of switch Q1 and fl presents line frequency. Peak (t)dt e = f V Ton2 Sin( 2πi t ) s P L1 In addition the input power can be found by P= = 1 2π ∫ V (t)i (t)dt 2π 0 S S V P 2 f T on 2 s 2 L1 Page 21 . Peak (t) = V T sin P on ( 2 π i et ) L1 Where Vp is the amplitude of line voltage. av 0 L1 . the peak value of the inductor current iL1 can be expressed as follows: i L1 .During each switching period. The average input current in each line period can be expressed as follows: i (t) = 1 ∫ i 2π 2π L1 . DESIGNE OF THE PROPOSED MODIFIED PFC Page 22 . 5. 2 SELECTION OF INDUCTOR: A good rule for determining the inductance is to allow the peak-to-peak ripple current to be approximately 40% of the maximum input current at the Page 23 .e.1 SELCTION OF DUTY CYCLE: For a SEPIC converter operating in a continuous conduction mode (CCM) or Boundary conduction mode. The maximum duty cycle is: D max = V out + V D V in (min) + V out + V D For our application .476.1.5.45 50 + 40 + 1 And the maximum duty cycle can be found as D max = 40 + 1 = (41/86) = 0. the forward voltage drop across the output diode as 1V. the duty cycle is given by: D = V out + V D V in + V out + V D VD is the forward voltage drop of the output diode. Hence the duty cycle can be found as. D= 40 + 1 = (41/91) = 0. Vin (min)=(50-50*10%) = 45V 5. we have chosen the input voltage is 60V and the output voltage is 40V. 45 + 40 + 1 considering the fall in input voltage @ 10 %.1.1 DESIGN OF MODIFIED PFC: 5. i. The ripple current flowing in equal value inductors L1 and L2 is given by: ∆ iL = i in × 40 % = i out × V in (min) V out × 40 % In our application.2 = 2 .minimum input voltage. Hence. Peak = i out × V out + V D 40 % ) × (1 + 2 V in (min) = i out × (1 + 40 % ) 2 iL 2 . we have chosen the total output is 80Watt and as the output voltage has been selected as 40V. to ensure the inductor does not saturate. 476 = 0. 71 45 × 100 The inductor value is calculated by : L1 = L 2 = L = V in (min) × D max ∆ i × fs Where. Peak = i out × (1 + Page 24 . ∆ iL = i in × 40 % = i out × V in (min) V out × 40 % = 2 × 40 × 40 = 0 . is given by: iL1. 71 × 50000 × . iout = 80/40= 2 Amp. Peak i Vout + V D 40 +1 40 % ) = 2× × (1 + ×1. (The switching frequency has been chosen as 50 KHz) ∴ L1 = L 2 = L = 45 0 . The peak current in the inductor.186 A 2 Vin (min) 45 40 % ) = 2 ×1 .6 mH As the standard nearest size is 1 miliHenry therefore L = 1 mH is chosen.2 = 2. i = iout × L1.4A 2 L 2. therefore. output current . Peak Hence. fs is the switching frequency and Dmax is the duty cycle at the minimum Vin. the on-resistance Rds(on).64 A ( 40 + 45 + 1) × ( 40 + 1) 45 2 For our application. 586 A iQ . VGS = ±20V Gate threshold Voltage. 4 = 4 . and the maximum drain to source voltage. Logic level or sub logic level threshold MOSFETs should be used based on the gate drive voltage.1. ID = 12 A at 100o C temperature Gate to Source Voltage.3 SELECTION OF MOSFET : The parameters governing the selection of MOSFET are the minimum threshold voltage Vth(min). The peak switch current is given by: iL1.24Ω Gate to Drain “Miller” Charge. Peak + i L 2 . VDGR = 500V Continuous Drain Current. VGS(TH) = 2V Drain to Source On Resistance. The peak switch voltage is equal to Vin+Vout. Peak = i out × V out + V D 40 +1 40 % × (1 + ) = 2× × 1 . Drain to source Voltage. RDS(ON) = 0. 186 + 2 . Page 25 . gate-drain charge QGD. VDS = 500V Drain to Gate Voltage.5. 186 A 2 V in (min) 45 = i L 1. Peak = 2 . 2 = 2 . RMS = iout (Vout +Vin (min) +VD )×(Vout +VD ) = 2 × Vin (min) 2 = 2. VDS(max). Peak The RMS current through the switch is given by: iQ1. QGD = 62 nC. ID = 20 A at normal temperature Continuous Drain Current. we have chosen IRFP460 as it has the following parameters which suits our requirement. In our application.47micro Farad/ 250 V.5.1.Peak. Page 26 . The minimum peak reverse voltage the diode must withstand is: V RD 1 = V in (max) + V out (max) = 50 + 40 = 90 V Similar to boost converter. The voltage ratting of the coupling capacitor must be greater than the maximum input voltage.4 SELECTION OF DIODES: The output diode must be selected to handle the peak current and the reverse voltage. The power dissipation of the diode is equal to the output current multiplied by the forward voltage drop of the diode. the average output diode current is equal to the output current.5 SELECTION OF TANK INDUCTOR: The selection of SEPIC coupling capacitor Cs depends on the RMS current which is given by: 40 +1 = 1 . the diode peak current is the same as the switch peak current IQ. we have chosen the 6A4 MIC diode which is having a current ratting of 6A and the forward voltage drop is less than 1 V. Electrolytic capacitors work well for through-hole applications where the size is not limited and they can accommodate the required RMS current rating. Tantalum and ceramic capacitors are the best choice. This is not a Schottky diode. In our application. For very high frequency operation Schottky diodes are recommended in order to minimize the efficiency loss. In a SEPIC.1. 90 A iQ1. Due to unavailability of Schottky diode. we have chosen a 0. we have used this diode. RMS = i out (V out +V D ) = 2 × V in (min) 45 The SEPIC coupling capacitor must be rated for large RMS current relative to the output power. 5. Page 27 . 5. The comparator output is the required PWM signal whose duty cycle is controlled by the comparator base value i. The output of the driver is in phase with the input voltage. Two comparators have been used to create two independent PWM signal with different duty cycle but having same frequency. 01 µ = 1073 KHz 5. the resonance frequency of the tank circuit can be found as: fr = 2π 1 LrCr = 1 2π 22 µ × 0 . the analog voltage. It is done by a simple voltage divider circuit. In the second stage.Phase of one PWM signal is inverted also in the buffer stage. Cr = 0. The MOSFETs are finally driven by the gate driver IC IR2110.1.2 DESIGN OF GATE CONTROL CIRCUIT: The gate control circuit has two PWM generators with same frequency.001 µF.e. we have chosen the following components. In fact a 60W incandescent filament lamp is chosen for simplicity. the triangular wave is compared with a variable voltage in an Op-amp comparator. fS = 50KHz.7 SELECTION OF LOAD: The load has been chosen as 60W resistive. Therefore. Lr = 22µH.1. It is a very high frequency two channel gate driver.5. In fact analog PWM generation technique has been used using Operational amplifier (LF347). The upper channel output is with respect to a floating point which is helpful for our circuit.6 SELECTION OF TANK CAPACITOR: As the resonance frequency of the tank circuit must be much higher than switching frequency. The first stage generates a rectangular wave which is integrated and a triangular wave is achieved. The PWM generation has two stages. The generated PWM signal is buffered with the help of a CMOS NOT gate (CD 4049). And we need 5 Op-amp. IR2110 suits best for our application. A virtual ground has been created with the help of Op-amp and used to make the circuit with single power supply operated instead of using two equal and opposite power supply for the Op-amp.e. The other specification can be found from its datasheet which is available in the appendix at the end of this document. It is an industrial standard. It also has enable and automatic shutdown inputs.2.2.2. very reliable high frequency gate driver DIP package. IR 2110 is made by International rectifier. Hence CMOS NOT gate was required for our application which logic levels are suitable. Page 28 . Therefore LF347 has been chosen. The output is filtered with an electrolytic capacitor 220µF.4 SELCTION OF MOSFET GATE DRIVER CIRCUIT The gate driver required for our application must be very fast and should have two channels. Therefore. 5. The shutdown input can be configured as overload protection also. the control voltage is selected as 12V.1 SELCTION OF CONTROL VOLTAGE : As the VGS of the MOSFETs IRFP460 is 20V and the threshold voltage VTH is 4V.2 SELECTION OF OP-AMP: To generate the PWM of frequency 50 KHz.2. the Op-amp response must be very first i. 5. It is a quad Op-amp and very fast acting.3 SELECTION OF NOT GATE: The NOT gate required here must have the Vcc = 12V to 15V. The power supply stage contains a rectifier with output voltage 15V which is regulated to 12V with the linear voltage regulator LM7812. the time to reach the output from zero to saturation has to be extremely low.5. The normal digital NOT gates are having the Vcc as 5V which is incompatible with our logic level. CD4049 has been chosen which a versatile CMOS Hex NOT gate. 5. 6. SOFTWARE SIMULATION Page 29 . Software Simulation is based on the process of imitating a real phenomenon with a set of mathematical formulas. digital and mixed A/D circuits for exceptional power and accuracy. they are not essential for design and testing of circuits. it is a software program that converts a computer into a fully functioning electronics laboratory. Essentially. Simulation software is used widely to design equipment so that the final product will be as close to design specs as possible without expensive in process modification. essentially. While these simulators typically have printed circuit board (PCB) export capabilities. Most simulators use a SPICE engine that simulates analog. Electronics simulators such as Circuit Logix integrate a schematic editor SPICE simulator and on-screen waveforms and make “what-if” scenarios easy and instant. The software simulation of the proposed PFC was one of the objective our project and we have tried our level best to achieve the correct simulation result. Page 30 . which is the primary application of electronic circuit simulation. By simulating a circuit’s behavior before actually building it greatly improves efficiency and provides insights into the behavior and stability of electronics circuit designs. They also typically contain extensive model and device libraries. It is. a program that allows the user to observe an operation through simulation without actually performing that operation. For this purpose we have used PSPICE software which is very helpful and convenient for power electronic simulation. Electronics simulation software utilizes mathematical models to replicate the behavior of an actual electronic device or circuit. having been released in January 1984 to run on the original IBM PC. support of parameterized models. It also supports many additional features. encryption. Subsequent versions improved in performance and moved to DEC/VAX minicomputers. Today it has evolved into an analog mixed signal simulator. 6. and the Microsoft Windows platform.1 SIMULATION SOFTWARE: PSPICE is a SPICE analog circuit and digital logic simulation software that runs on personal computers. the Apple Macintosh. Sun workstations. a Model Editor. The name is an acronym for Personal Simulation Program with Integrated Circuit Emphasis. which were not available in the original Berkeley code like Advanced Analysis with automatic optimization of a circuit. This initial version ran from two 360KB floppy disks and later included a waveform viewer and analyzer program called Probe. magnetic part editor and Tabrizi core model for non-linear cores. is integrated in the complete systems design flow from OrCAD and Cadence Allegro. MicroSim was bought by OrCAD which was subsequently purchased by Cadence Design Systems. has several internal solvers. It was developed by MicroSim and is used in electronic design automation. PSPICE. Page 31 . hence the first letter "P" in its name. now developed towards more complex industry requirements. auto-convergence and checkpoint restart. PSPICE was the first version of UC Berkeley SPICE available on a PC. 6. Fig9: Modified SEPIC PFC with Gate driver Page 32 .2 SIMULATION RESULTS: The following figure shows the schematic arrangement of the modified SEPIC PFC which is drawn by OrCAD schematic capture for simulation. Fig10: Simulated output of Gate control voltage Fig11: Simulated output of drain to source current and voltage of main MOSFET Page 33 . they are in same phase Page 34 . MOSFET Fig13:Simulated output of input line voltage and current.Fig12: Simulated output of drain to source current and voltage of aux. 7. HARDWARE PROTO TYPE IMPLEMENTATION AND TESTINGS Page 35 . Fig14: The Gate Driver Circuit Fig15: The Modified SEPIC PFC Page 36 . 7.1 MEASUREMENTS OF KEY WAVEFORMS: Fig16: The Gate voltage without load Fig17: The Gate voltage with load Page 37 . Fig18: The drain to source voltage of main MOSFET Fig19: The drain to source voltage of auxiliary MOSFET Page 38 . Fig20: The line voltage and line current Fig21: The line voltage and line current Page 39 . 67 A Hence. we can comment the concept can be used for the real world rectifier driven loads to improve the power factor. 7 % 33 . Hence as whole.2 MEASUREMENTS OF POWER FACTOR: As from the waveforms of input line voltage and current it is evident that they are exactly in same phase .3 MEASUREMENTS OF EFFICIENCY: In the test condition the following parameters are measured as follows.76 A . the Output power = 40×0. Iout = 0. Vout= 40 V. 4 = 90 . Vin= 50 V.7. The Input power = VICosΦ = 50×0.5 Watt Therefore efficiency. 7.4 Watt.76=30. Iin= 0. the power factor is unity. η = Output Input = 30 .67×1= 33. 5 Page 40 . 8. CONCLUSION Page 41 . BCM. This paper has proposed a modified SEPIC-type soft-switching converter. As a result. The output voltage of the PFC can be smaller than ac-side voltage. The PFC configuration can be applied to DCM. Page 42 . which can perform power factor correcting and achieve zero-voltage switching feature. Therefore. a unity power factor is obtained and efficiency is improved significantly. reducing component stresses. A prototype of the designed PFC for 40W 135V dc load has been successfully implemented. or CCM operation for power factor correction and ZVS. The simulations and practical measurements have verified the feasibility of the PFC. the PFC is suitable for the applications of high line voltage and/or low output voltage. 9. APPENDIX Page 43 . the thermal shutdown circuit takes over preventing the IC from overheating.national. instrumentation. If internal power dissipation becomes too high for the heat sinking provided. although this does improve transient response. The LM78XX series is available in an aluminum TO-3 package which will allow over 1. The voltages available allow these regulators to be used in logic systems. HiFi. LM7812CK or LM7815CK See NS Package Number KC02A Top View Order Number LM7805CT. eliminating the distribution problems associated with single point regulation. LM7812CT or LM7815CT See NS Package Number T03B © 2000 National Semiconductor Corporation DS007746 www. Features n n n n n n Output current in excess of 1A Internal thermal overload protection No external components required Output transistor safe area protection Internal short circuit current limit Available in the aluminum TO-3 package Voltage Range LM7805C LM7812C LM7815C 5V 12V 15V Connection Diagrams Metal Can Package TO-3 (K) Aluminum Plastic Package TO-220 (T) DS007746-3 DS007746-2 Bottom View Order Number LM7805CK. Input bypassing is needed only if the regulator is located far from the filter capacitor of the power supply. 12V and 15V the LM117 series provides an output voltage range from 1.LM78XX Series Voltage Regulators May 2000 LM78XX Series Voltage Regulators General Description The LM78XX series of three terminal regulators is available with several fixed output voltages making them useful in a wide range of applications. Although designed primarily as fixed voltage regulators these devices can be used with external components to obtain adjustable voltages and currents.com . Current limiting is included to limit the peak output current to a safe value. One of these is local on card regulation. Safe area protection for the output transistor is provided to limit internal power dissipation. Considerable effort was expanded to make the LM78XX series of regulators easy to use and minimize the number of external components. For output voltage other than 5V. It is not necessary to bypass the output.0A load current if adequate heat sinking is provided.2V to 57V. and other solid state electronic equipment. LM78XX Schematic DS007746-1 www.com 2 .national. 5 ≤ VIN ≤ 20) 25 (8 ≤ VIN ≤ 12) 10 50 25 50 8 8. 10 sec.5 ≤ VIN ≤ 27) 4 120 (17.5 1.com .0 (14.) TO-3 Package K TO-220 Package T 150˚C 150˚C −65˚C to +150˚C 300˚C 230˚C Electrical Characteristics LM78XXC 0˚C ≤ TJ ≤ 125˚C unless otherwise noted. 5 mA ≤ IO ≤ 1A PD ≤ 15W.0 8 80 14.LM78XX Absolute Maximum Ratings (Note 3) If Military/Aerospace specified devices are required.25 11. Output Voltage Input Voltage (unless otherwise noted) Symbol VO Parameter Output Voltage Conditions Tj = 25˚C.75 V V V mV V mV V mV V mV V mV mV mV mA mA mA mA V mA V µV dB dB V V mΩ Units 5.5 ≤ VIN ≤ 30) 90 54 54 (18.5 12V 19V Typ Max 12 Min 12.5 ≤ VIN ≤ 30) 4 150 (7 ≤ VIN ≤ 25) 50 (8 ≤ VIN ≤ 20) 50 (7.0 18 72 (17.6 14. IOUT = 1A f = 1 kHz 3 www.5A 250 mA ≤ IO ≤ 750 mA 5 mA ≤ IO ≤ 1A.6 15.2 Min 11.5 ≤ VIN ≤ 30) 150 (17. IO ≤ 1A VMIN ≤ VIN ≤ VMAX IO ≤ 500 mA. 12V and 15V) Internal Power Dissipation (Note 1) Operating Temperature Range (TA) 35V Internally Limited 0˚C to +70˚C Maximum Junction Temperature (K Package) (T Package) Storage Temperature Range Lead Temperature (Soldering.0 (17. 5 mA ≤ IO ≤ 1A VMIN ≤ VIN ≤ VMAX ∆VO Line Regulation IO = 500 mA Tj = 25˚C ∆VIN (Note 2) 5V 10V Min 4.25 15V 23V Typ Max 15 15. Input Voltage (VO = 5V.0 (7 ≤ VIN ≤ 25) 40 62 62 (8 ≤ VIN ≤ 18) 2. 10 Hz ≤ f ≤ 100 kHz IO ≤ 1A.4 12.5 14.4 (7.5 ≤ VIN≤ 30) 75 55 55 (15 ≤ VIN ≤ 25) 2.5 ≤ VIN ≤ 30) 150 (18.5 ≤ VIN ≤ 30) 120 (15 ≤ VIN ≤ 27) 120 (14.8 ≤ VIN≤ 27) 1.5 ≤ VIN ≤ 28. please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.5 ≤ VIN ≤ 20) 1. 0˚C ≤ Tj ≤ +125˚C VMIN ≤ VIN ≤ VMAX VN Output Noise Voltage Ripple Rejection f = 120 Hz TA =25˚C.0 19 70 0˚C ≤ Tj ≤ +125˚C ∆VIN IO ≤ 1A Tj = 25˚C ∆VIN 0˚C ≤ Tj ≤ +125˚C ∆VIN ∆VO Load Regulation Tj = 25˚C 5 mA ≤ IO ≤ 1.national.0 (17.0 (7. Tj = 25˚C or IO ≤ 500 mA 0˚C ≤ Tj ≤ +125˚C VMIN ≤ VIN ≤ VMAX RO Dropout Voltage Output Resistance Tj = 25˚C.5 1.8 4.0 (14.5 1.7 ≤ VIN ≤ 30) 75 (20 ≤ VIN ≤ 26) 12 150 75 150 8 8.75 Typ Max 5 5.5) 2.5 0. 0˚C ≤ Tj ≤ +125˚C IQ ∆IQ Quiescent Current Quiescent Current Change IO ≤ 1A Tj = 25˚C 0˚C ≤ Tj ≤ +125˚C 5 mA ≤ IO ≤ 1A Tj = 25˚C.5 ≤ VIN ≤ 20) 3 50 (14.9 ≤ VIN ≤ 30) 1.5 0.5 0.6 ≤ VIN ≤ 27) 60 (16 ≤ VIN ≤ 22) 12 120 60 120 8 8. see Electrical Characteristics.1µF. duty cycle ≤ 5%).com 4 .5 Min 15V 23V Typ Max 1. For guaranteed specifications and the test conditions.4 0.1 2.6 Min 12V 19V Typ Max 1.4 1. IO = 5 mA Conditions (Note 2) (Continued) 5V 10V Min Typ Max 2. Note 2: All characteristics are measured with capacitor across the input of 0.8 A A mV/˚C Units 7. Thermal resistance of the TO-220 package (T) is typically 4˚C/W junction to case and 50˚C/W case to ambient.5 2. IO ≤ 1A Tj = 25˚C Tj = 25˚C 0˚C ≤ Tj ≤ +125˚C.5 14. www. Note 3: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.22 µF.LM78XX Electrical Characteristics LM78XXC 0˚C ≤ TJ ≤ 125˚C unless otherwise noted.national.4 1. KC) is typically 4˚C/W junction to case and 35˚C/W case to ambient.2 2. All characteristics except noise voltage and ripple rejection ratio are measured using pulse techniques (tw ≤ 10 ms. and a capacitor across the output of 0.6 17. Output Voltage Input Voltage (unless otherwise noted) Symbol Parameter Short-Circuit Current Peak Output Current Average TC of VOUT VIN Input Voltage Required to Maintain Line Regulation Tj = 25˚C. Output voltage changes due to changes in internal temperature must be taken into account separately.7 V Note 1: Thermal resistance of the TO-3 package (K. national.com .LM78XX Typical Performance Characteristics Maximum Average Power Dissipation Maximum Average Power Dissipation DS007746-5 DS007746-6 Peak Output Current Output Voltage (Normalized to 1V at TJ = 25˚C) DS007746-7 DS007746-8 Ripple Rejection Ripple Rejection DS007746-9 DS007746-10 5 www. LM78XX Typical Performance Characteristics Output Impedance (Continued) Dropout Voltage DS007746-11 DS007746-12 Dropout Characteristics Quiescent Current DS007746-13 DS007746-14 Quiescent Current DS007746-15 www.com 6 .national. LM78XX Physical Dimensions inches (millimeters) unless otherwise noted Aluminum Metal Can Package (KC) Order Number LM7805CK. LM7812CK or LM7815CK NS Package Number KC02A 7 www.national.com . As used herein: 1.com National Semiconductor Europe Fax: +49 (0) 180-530 85 86 Email: europe. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email:
[email protected] Deutsch Tel: +49 (0) 69 9508 6208 English Tel: +44 (0) 870 24 0 2171 Français Tel: +33 (0) 1 41 91 8790 2. or (b) support or sustain life.support@nsc. . National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: ap. or to affect its safety or effectiveness.national. Life support devices or systems are devices or systems which. LM7812CT or LM7815CT NS Package Number T03B LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. (a) are intended for surgical implant into the body. can be reasonably expected to result in a significant injury to the user.com www. and whose failure to perform when properly used in accordance with instructions for use provided in the labeling. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system.LM78XX Series Voltage Regulators Physical Dimensions inches (millimeters) unless otherwise noted (Continued) TO-220 Package (T) Order Number LM7805CT. Tel: 81-3-5639-7560 Fax: 81-3-5639-7507 National does not assume any responsibility for use of any circuitry described. no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and
[email protected] National Semiconductor Japan Ltd. LF147 LF347 Wide Bandwidth Quad JFET Input Operational Amplifiers December 1994 LF147 LF347 Wide Bandwidth Quad JFET Input Operational Amplifiers General Description The LF147 is a low cost high speed quad JFET input operational amplifier with an internally trimmed input offset voltage (BI-FET IITM technology) The device requires a low supply current and yet maintains a large gain bandwidth product and a fast slew rate In addition well matched high voltage JFET input devices provide very low input bias and offset currents The LF147 is pin compatible with the standard LM148 This feature allows designers to immediately upgrade the overall performance of existing LF148 and LM124 designs The LF147 may be used in applications such as high speed integrators fast D A converters sample-and-hold circuits and many other circuits requiring low input offset voltage low input bias current high input impedance high slew rate and wide bandwidth The device has low noise and offset voltage drift Features Y Y Y Y Y Y Y Y Y Y Internally trimmed offset voltage 5 mV max Low input bias current 50 pA Low input noise current 0 01 pA 0Hz Wide gain bandwidth 4 MHz High slew rate 13 V ms Low supply current 7 2 mA High input impedance 1012X k 0 02% Low total harmonic distortion AV e 10 RL e 10k VO e 20 Vp-p BW e 20 Hzb20 kHz Low 1 f noise corner 50 Hz Fast settling time to 0 01% 2 ms Simplified Schematic Quad Connection Diagram Dual-In-Line Package TL H 5647 – 1 TL H 5647 – 13 Top View Order Number LF147J LF347M LF347BN LF347N LF147D 883 or LF147J 883 See NS Package Number D14E J14A M14A or N14A Available per SMD 8102306 JM38510 11906 BI-FET IITM is a trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL H 5647 RRD-B30M115 Printed in U S A . Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications LF147 LF347B LF347 g 22V g 18V Supply Voltage g 38V g 30V Differential Input Voltage g 19V g 15V Input Voltage Range (Note 1) Output Short Circuit Continuous Continuous Duration (Note 2) Power Dissipation 900 mW 1000 mW (Notes 3 and 9) Tj max 150 C 150 C ijA Cavity DIP (D) Package 80 C W Ceramic DIP (J) Package 70 C W Plastic DIP (N) Package 75 C W Surface Mount Narrow (M) 100 C W Surface Mount Wide (WM) 85 C W Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering 10 sec ) Soldering Information Dual-In-Line Package Soldering (10 seconds) Small Outline Package Vapor Phase (60 seconds) Infrared (15 seconds) See AN-450 ‘‘Surface Mounting on Product Reliability’’ for other face mount devices ESD Tolerance (Note 10) LF147 (Note 4) LF347B LF347 (Note 4) b 65 C s TA s 150 C 260 C 260 C 260 C 215 C 220 C Methods and Their Effect methods of soldering sur900V DC Electrical Characteristics Symbol VOS Parameter Input Offset Voltage (Note 5) LF147 Min Typ 1 10 25 50 1012 50 25 100 50 25 g 12 g 13 5 g 11 Conditions RS e 10 kX TA e 25 C Over Temperature RS e 10 kX Tj e 25 C (Notes 5 6) Over Temperature Tj e 25 C (Notes 5 6) Over Temperature Tj e 25 C VS e g 15V TA e 25 C VO e g 10V RL e 2 kX Over Temperature LF347B Max Min 5 8 Typ 3 10 100 25 200 50 25 50 1012 100 25 15 100 4 200 8 Max Min 5 7 LF347 Typ 5 10 25 50 1012 100 100 4 200 8 Max 10 13 Units mV mV mV C pA nA pA nA X V mV V mV V V V dB dB 11 mA DVOS DT Average TC of Input Offset Voltage IOS IB RIN AVOL Input Offset Current Input Bias Current Input Resistance Large Signal Voltage Gain VO VCM CMRR PSRR IS Output Voltage Swing Input Common-Mode Voltage Range VS e g 15V RL e 10 kX g 12 g 13 5 VS e g 15V g 11 g 12 g 13 5 g 11 a 15 b 12 a 15 b 12 a 15 b 12 Common-Mode Rejection Ratio RSs10 kX Supply Voltage Rejection Ratio (Note 7) Supply Current 80 80 100 100 72 11 80 80 100 100 72 11 70 70 100 100 72 2 . AC Electrical Characteristics (Note 5) Symbol Parameter Amplifier to Amplifier Coupling Conditions Min TA e 25 C f e 1 Hzb20 kHz (Input Referred) VS e g 15V TA e 25 C 8 LF147 Typ b 120 LF347B Max Min Typ b 120 LF347 Max Min Typ b 120 Units Max dB SR GBW en in Slew Rate Gain-Bandwidth Product 13 4 20 0 01 8 22 13 4 20 0 01 8 22 13 4 20 0 01 V ms MHz nV 0Hz pA 0Hz VS e g 15V TA e 25 C 2 2 Equivalent Input Noise Voltage TA e 25 C RS e 100X f e 1000 Hz Equivalent Input Noise Current Tj e 25 C f e 1000 Hz Note 1 Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage Note 2 Any of the amplifier outputs can be shorted to ground indefinitely however more than one should not be simultaneously shorted as the maximum junction temperature will be exceeded Note 3 For operating at elevated temperature these devices must be derated based on a thermal resistance of ijA Note 4 The LF147 is available In the military temperature range b 55 C s TA s 125 C while the LF347B and the LF347 are available in the commercial temperature range 0 C s TA s 70 C Junction temperature can rise to Tj max e 150 C Note 5 Unless otherwise specified the specifications apply over the full temperature range and for VS e g 20V for the LF147 and for VS e g 15V for the LF347B LF347 VOS IB and IOS are measured at VCM e 0 Note 6 The input bias currents are junction leakage currents which approximately double for every 10 C increase in the junction temperature Tj Due to limited production test time the input bias currents measured are correlated to junction temperature In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation PD Tj e TA a ijA PD where ijA is the thermal resistance from junction to ambient Use of a heat sink is recommended if input bias current is to be kept to a minimum Note 7 Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice from VS e g 5V to g 15V for the LF347 and LF347B and from VS e g 20V to g 5V for the LF147 Note 8 Refer to RETS147X for LF147D and LF147J military specifications Note 9 Max Power Dissipation is defined by the package characteristics Operating the part near the Max Power Dissipation may cause the part to operate outside guaranteed limits Note 10 Human body model 1 5 kX in series with 100 pF 3 . Typical Performance Characteristics Input Bias Current Input Bias Current Supply Current Positive Common-Mode Input Voltage Limit Negative Common-Mode Input Voltage Limit Positive Current Limit Negative Current Limit Output Voltage Swing Output Voltage Swing Gain Bandwidth Bode Plot Slew Rate TL H 5647 – 2 4 . Typical Performance Characteristics Distortion vs Frequency (Continued) Open Loop Frequency Response Undistorted Output Voltage Swing Common-Mode Rejection Ratio Power Supply Rejection Ratio Equivalent Input Noise Voltage Open Loop Voltage Gain Output Impedance Inverter Settling Time TL H 5647 – 3 5 . Pulse Response RL e 2 kX CL e 10 pF Small Signal Non-Inverting Small Signal Inverting TL H 5647–4 TL H 5647 – 5 Large Signal Inverting Large Signal Non-Inverting TL H 5647–6 TL H 5647 – 7 Current Limit (RL e 100X) TL H 5647 – 8 Application Hints The LF147 is an op amp with an internally trimmed input offset voltage and JFET input devices (BI-FET IITM) These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs Therefore large differential input voltages can easily be accommodated without a large increase in input current The maximum differential input voltage is independent of the supply voltages However neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit Exceeding the negative common-mode limit on either input will force the output to a high state potentially causing a reversal of phase to the output Exceeding the negative common-mode limit on both inputs will force the amplifier 6 . Application Hints (Continued) output to a high state In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode Exceeding the positive common-mode limit on a single input will not change the phase of the output however if both inputs exceed the limit the output of the amplifier will be forced to a high state The amplifiers will operate with a common-mode input voltage equal to the positive supply however the gain bandwidth and slew rate may be decreased in this condition When the negative common-mode voltage swings to within 3V of the negative supply an increase in input offset voltage may occur Each amplifier is individually biased by a zener reference which allows normal circuit operation on g 4 5V power supplies Supply voltages less than these may result in lower gain bandwidth and slew rate The LF147 will drive a 2 kX load resistance to g 10V over the full temperature range If the amplifier is forced to drive heavier load currents however an increase in input offset voltage may occur on the negative voltage swing and finally reach an active current limit on both positive and negative swings Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit As with most amplifiers care should be taken with lead dress component placement and supply decoupling in order to ensure stability For example resistors from the output to an input should be placed with the body close to the input to minimize ‘‘pick-up’’ and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground A feedback pole is created when the feedback around any amplifier is resistive The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin However if the feedback pole is less than approximately 6 times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant Detailed Schematic TL H 5647 – 9 7 . Typical Applications Digitally Selectable Precision Attenuator All resistors 1% tolerance A1 A2 A3 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 VO Attenuation 0 b 1 dB b 2 dB b 3 dB b 4 dB b 5 dB b 6 dB b 7 dB Accuracy of better than 0 4% with standard 1% value resistors No offset adjustment necessary Expandable to any number of stages Very high input impedance TL H 5647 – 10 Long Time Integrator with Reset Hold and Starting Threshold Adjustment TL H 5647 – 11 VOUT starts from zero and is equal to the integral of the input voltage with respect to the threshold voltage VOUT e 1 t (VIN b VTH)dt RC 0 Output starts when VIN t VTH Switch S1 permits stopping and holding any output value Switch S2 resets system to zero 8 . Typical Applications (Continued) Universal State Variable Filter TL H 5647 – 12 For circuit shown fo e 3 kHz fNOTCH e 9 5 kHz Qe3 4 Passband gain Highpass Bandpass Lowpass Notch 10 01 1 1 fo c Q s 200 kHz 10V peak sinusoidal output swing without slew limiting to 200 kHz See LM148 data sheet for design equations 9 . Physical Dimensions inches (millimeters) Hermetic Dual-In-Line Package (D) Order Number LF147D 883 NS Package Number D14E 10 . Physical Dimensions inches (millimeters) (Continued) Ceramic Dual-In-Line Package (J) Order Number LF147J or LF147J 883 NS Package Number J14A S O Package (M) Order Number LF347M NS Package Number M14A 11 . LF147 LF347 Wide Bandwidth Quad JFET Input Operational Amplifiers Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number LF347BN or LF347N NS Package Number N14A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications . com Datasheets for electronics components.datasheetcatalog.This datasheet has been download from: www. . d.IRFP460.) (nC) Qgs (nC) Qgd (nC) Configuration VGS = 10 V 210 29 110 Single D FEATURES 500 0. ORDERING INFORMATION Package Lead (Pb)-free SnPb TO-247 IRFP460PbF SiHFP460-E3 IRFP460 SiHFP460 ABSOLUTE MAXIMUM RATINGS TC = 25 °C. The TO-247 package is preferred for commercial-industrial applications where higher power levels preclude the use of TO-220 devices. Repetitive rating. exemptions may apply Document Number: 91237 S-81360-Rev. IAS = 20 A (see fig. L = 4. starting TJ = 25 °C. pulse width limited by maximum junction temperature (see fig.com 1 .27 • Dynamic dV/dt Rating • Repetitive Avalanche Rated • Isolated Central Mounting Hole • Fast Switching • Ease of Paralleling • Simple Drive Requirements • Lead (Pb)-free Available Available RoHS* COMPLIANT TO-247 DESCRIPTION G S D G S N-Channel MOSFET Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching. TJ ≤ 150 °C.6 mm from case. RG = 25 Ω. ruggedized device design. 28-Jul-08 www. VDD = 50 V. A.vishay.3 mH. c.55 to + 150 300d 10 1. low on-resistance and cost-effectiveness. * Pb containing terminations are not RoHS compliant. ISD ≤ 20 A. Tstg LIMIT 500 ± 20 20 13 80 2. VDD ≤ VDS. 1. unless otherwise noted PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Currenta Linear Derating Factor Single Pulse Avalanche Energyb Repetitive Avalanche Currenta Repetitive Avalanche Energya Maximum Power Dissipation Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) Mounting Torque VGS at 10 V TC = 25 °C TC = 100 °C SYMBOL VDS VGS ID IDM EAS IAR EAR PD dV/dt TJ. 11). The TO-247 is similar but superior to the earlier TO-218 package because its isolated mounting hole.2 960 20 28 280 3. SiHFP460 Vishay Siliconix Power MOSFET PRODUCT SUMMARY VDS (V) RDS(on) (Ω) Qg (Max. b.1 UNIT V A W/°C mJ A mJ W V/ns °C lbf · in N·m TC = 25 °C for 10 s 6-32 or M3 screw Notes a.5 . dI/dt ≤ 160 A/µs. It also provides greater creepage distances between pins to meet the requirements of most safety specifications. 12). 27 - V V/°C V nA µA Ω S VDS = 50 V. b. f = 1.com 2 Document Number: 91237 S-81360-Rev. Repetitive rating. VDS = 25 V. TYP. ID = 12 VGS = 0 V. 0. MAX. A.IRFP460. 5 - 4200 870 350 18 59 110 58 5. UNIT VDS ΔVDS/TJ VGS(th) IGSS IDSS RDS(on) gfs Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf LD LS VGS = 0 V. ID = 1 mA VDS = VGS.6 V ns µC G S TJ = 25 °C. 40 0. VGS = 0 V.3 Ω.63 - 4. RG = 4. www. IS = 20 A. ID = 250 µA Reference to 25 °C.0 13 0. Flat.7 20 A 80 1. ID = 20 A . Greased Surface Maximum Junction-to-Case (Drain) SYMBOL RthJA RthCS RthJC TYP. 11). dI/dt = 100 A/µsb Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a.45 °C/W UNIT SPECIFICATIONS TJ = 25 °C. SiHFP460 Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER Maximum Junction-to-Ambient Case-to-Sink. see fig.25") from package and center of die contact D - G S - 570 5. RD = 13 Ω.vishay. ID = 250 µA VGS = ± 20 V VDS = 500 V. VDS = 400 V see fig. Pulse width ≤ 300 µs.24 MAX. TJ = 125 °C VGS = 10 V ID = 12 Ab Ab 500 2.8 860 8. duty cycle ≤ 2 %. 28-Jul-08 . VGS = 0 V VDS = 400 V.0 13 210 29 110 nH ns nC pF VGS = 10 V ID = 20 A.n junction diode D SYMBOL TEST CONDITIONS MIN. unless otherwise noted PARAMETER Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance Dynamic Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage Body Diode Reverse Recovery Time Body Diode Reverse Recovery Charge Forward Turn-On Time IS ISM VSD trr Qrr ton MOSFET symbol showing the integral reverse p . pulse width limited by maximum junction temperature (see fig. VGS = 0 Vb TJ = 25 °C. 10b - Between lead.0 MHz. 6 mm (0. 6 and 13b - VDD = 250 V. IF = 20A. see fig.0 ± 100 25 250 0. 5 V 5.0 V 7.0 V Bottom 4.0 2.5 V 101 25 °C 100 91237_01 20 µs Pulse Width TC = 25 °C 100 101 100 4 91237_03 20 µs Pulse Width VDS = 50 V 5 6 7 8 9 10 VDS.5 V Top VGS 150 °C 101 4.0 V 5.0 V 6.5 2.0 V 7.Typical Output Characteristics. A. Drain Current (A) 15 V 10 V 8.0 V 6.IRFP460.60 .5 3. 2 . Drain Current (A) 101 VGS 15 V 10 V 8. TC = 150 °C Fig.5 ID = 20 A VGS = 10 V 4.40 .com 3 .5 V 100 100 91237_02 20 µs Pulse Width TC = 150 °C 101 0. unless otherwise noted ID. 1 .Normalized On-Resistance vs. Drain-to-Source Voltage (V) 91237_04 TJ.Typical Transfer Characteristics ID. TC = 25 °C VGS. 28-Jul-08 www. 3 .vishay. Drain-to-Source Voltage (V) Fig. 4 . Junction Temperature (°C) Fig.Typical Output Characteristics. Drain Current (A) ID.0 V 5.5 V Top RDS(on).0 .0 1.5 1.20 0 20 40 60 80 100 120 140 160 VDS.5 V 5. Drain-to-Source On Resistance (Normalized) 3. Temperature Document Number: 91237 S-81360-Rev.0 V Bottom 4. Gate-to-Source Voltage (V) Fig. SiHFP460 Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C.0 0. 28-Jul-08 .6 91237_07 VDS. 5 .Typical Gate Charge vs. Drain-to-Source Voltage (V) Fig.8 1. Drain Current (A) 16 2 102 5 12 VDS = 100 V 8 10 µs 100 µs 2 10 5 4 For test circuit see figure 13 2 1 ms TC = 25 °C TJ = 150 °C Single Pulse 1 2 5 10 ms 102 2 5 0 0 91237_06 1 40 80 120 160 200 91237_08 10 2 5 103 QG.Typical Source-Drain Diode Forward Voltage 20 VGS. Reverse Drain Current (A) Capacitance (pF) VGS = 0 V. Drain-to-Source Voltage Fig.vishay.com 4 Document Number: 91237 S-81360-Rev. Gate-to-Source Voltage (V) ID = 20 A VDS = 400 V VDS = 250 V 103 5 Operation in this area limited by RDS(on) ID. Drain-to-Source Voltage (V) VSD. Cds Shorted Crss = Cgd Coss = Cds + Cgd 102 150 °C 25 °C VGS = 0 V 0. 8 .0 1. SiHFP460 Vishay Siliconix 10 000 8000 6000 Ciss 4000 Coss ISD.8 2.6 1. A.IRFP460. Total Gate Charge (nC) VDS.4 1. 6 . 7 . f = 1 MHz Ciss = Cgs + Cgd.Typical Capacitance vs. Gate-to-Source Voltage Fig.Maximum Safe Operating Area www. Source-to-Drain Voltage (V) Fig.0 2000 Crss 0 100 91237_05 101 101 0.2 1. vishay. Peak Tj = PDM x ZthJC + TC 10-5 10-4 10-3 10-2 0. SiHFP460 Vishay Siliconix RD VDS VGS D.5 0.2 0.05 0.0.com 5 . Duty Factor.Maximum Drain Current vs. 11a .Switching Time Test Circuit 8 VDS 4 90 % 0 25 91237_09 50 75 100 125 150 10 % VGS td(on) tr td(off) tf TC. 9 . Junction-to-Case L Vary tp to obtain required IAS RG VDS tp VDD D.U.Maximum Effective Transient Thermal Impedance. A.Unclamped Inductive Test Circuit Document Number: 91237 S-81360-Rev.1 1 10 10-2 10-3 91237_11 t1.T IAS 10 V tp 0. 12a . Drain Current (A) 16 12 Fig. Rectangular Pulse Duration (S) Fig.VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.IRFP460. 12b .1 % 20 RG ID. 10b .U.01 Ω IAS Fig.Unclamped Inductive Waveforms VDS + - V DD A VDS Fig. Case Temperature (°C) Fig. 10a .Switching Time Waveforms 1 Thermal Response (ZthJC) 0 .02 0. + . 28-Jul-08 www.T.01 PDM Single Pulse (Thermal Response) t1 t2 Notes: 1.1 0.1 0. Case Temperature Fig. D = t1/t2 2. Junction Temperature (°C) Fig.vishay.9 A 13 A Bottom 20 A Top 125 150 91237_12c Starting TJ.com 6 Document Number: 91237 S-81360-Rev. Single Pulse Energy (mJ) 2000 1600 1200 800 400 0 VDD = 50 V 25 50 75 100 ID 8.Maximum Avalanche Energy vs.T. 13b .U.Gate Charge Test Circuit www.3 µF + D.IRFP460. 50 kΩ 12 V 0. 13a . 28-Jul-08 . Drain Current 10 V QGS QG QGD VG Charge Fig.U. A.2 µF 0. 12c . VGS 3 mA - VDS IG ID Current sampling resistors Fig.T. SiHFP460 Vishay Siliconix 2400 EAS.Basic Gate Charge Waveform Current regulator Same type as D. 14 .T. and reliability data. For related documents such as package/tape drawings.U. A.com 7 . + Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + + - RG • • • • dV/dt controlled by RG Driver same type as D. Document Number: 91237 S-81360-Rev.W. part marking.T.com/ppg?91237. VDS waveform Diode recovery dV/dt VDD Re-applied voltage Inductor current Body diode forward drop Ripple ≤ 5 % ISD * VGS = 5 V for logic level devices Fig.T.T.U. 28-Jul-08 www.For N-Channel Vishay Siliconix maintains worldwide manufacturing capability.T.device under test + VDD Driver gate drive P.U. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. Period D= P.W. ISD controlled by duty factor "D" D. ISD waveform Reverse recovery current Body diode forward current dI/dt D. SiHFP460 Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit D.vishay.IRFP460.U. Products may be manufactured at one of several qualified locations.U.vishay. Period VGS = 10 V* D. . see http://www. vishay. Product names and markings noted herein may be trademarks of their respective owners. disclaim any and all liability for any errors. No license.com 1 . by estoppel or otherwise. which apply to these products. life-saving. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. express or implied. Vishay Intertechnology. its affiliates. or life-sustaining applications unless otherwise expressly indicated. “Vishay”). Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.Legal Disclaimer Notice Vishay Disclaimer All product specifications and data are subject to change without notice. to any intellectual property rights is granted by this document or by any conduct of Vishay. and all persons acting on its or their behalf (collectively. including but not limited to the warranty expressed therein. agents. Inc. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase. and employees. Document Number: 91000 Revision: 18-Jul-08 www.. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. The products shown herein are not designed for use in medical. and P-channel enhancement mode transistors These devices feature logic level conversion using only one supply voltage (VDD) The input signal high level (VIH) can exceed the VDD supply voltage when these devices are used for logic level conversions These devices are intended for use as hex buffers CMOS to DTL TTL converters or as CMOS current drivers and at VDD e 5 0V they can drive directly two DTL TTL loads over the full operating temperature range Features Y Y Y Y Wide supply voltage range 3 0V to 15V Direct drive to 2 TTL loads at 5 0V over full temperature range High source and sink current capability Special input protection permits input voltages greater than VDD Applications Y Y Y Y CMOS CMOS CMOS CMOS hex inverter buffer to DTL TTL hex converter current ‘‘sink’’ or ‘‘source’’ driver high-to-low logic level converter Connection Diagrams CD4049UBM CD4049UBC Dual-In-Line Package CD4050BM CD4050BC Dual-In-Line Package TL F 5971 – 1 TL F 5971 – 2 Top View Order Number CD4049UB or CD4049B Top View Order Number CD4050UB or CD4050B C1995 National Semiconductor Corporation TL F 5971 RRD-B30M105 Printed in U S A .CD4049UBM CD4049UBC Hex Inverting Buffer CD4050BM CD4050BC Hex Non-Inverting Buffer March 1988 CD4049UBM CD4049UBC Hex Inverting Buffer CD4050BM CD4050BC Hex Non-Inverting Buffer General Description These hex buffers are monolithic complementary MOS (CMOS) integrated circuits constructed with N. Absolute Maximum Ratings (Notes 1 2) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VDD) Input Voltage (VIN) Voltage at Any Output Pin (VOUT) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering 10 seconds) b 0 5V to a 18V b 0 5V to a 18V b 0 5V to VDD a 0 5V b 65 C to a 150 C Recommended Operating Conditions (Note 2) Supply Voltage (VDD) Input Voltage (VIN) Voltage at Any Output Pin (VOUT) Operating Temperature Range (TA) CD4049UBM CD4050BM CD4049UBC CD4050BC 3V to 15V 0V to 15V 0 to VDD b 55 C to a 125 C b 40 C to a 85 C 700 mW 500 mW 260 C DC Electrical Characteristics CD4049M Symbol IDD Parameter Quiescent Device Current Conditions VDD e 5V VDD e 10V VDD e 15V CD4050BM (Note 2) b 55 C a 25 C a 125 C Units mA mA mA Min Max 10 20 40 Min Typ 0 01 0 01 0 03 Max 10 20 40 Min Max 30 60 120 VOL Low Level Output Voltage VIH e VDD VIL e 0V lIOl k 1 mA VDD e 5V VDD e 10V VDD e 15V VIH e VDD VIL e 0V lIOl k 1 mA VDD e 5V VDD e 10V VDD e 15V 0 05 0 05 0 05 0 0 0 0 05 0 05 0 05 0 05 0 05 0 05 V V V VOH High Level Output Voltage 4 95 9 95 14 95 15 30 40 10 20 30 35 70 11 0 40 80 12 0 56 12 35 4 95 9 95 14 95 5 10 15 2 25 45 6 75 15 25 35 15 30 40 10 20 30 4 95 9 95 14 95 15 30 40 10 20 30 35 70 11 0 40 80 12 0 32 68 20 V V V V V V V V V V V V V V V mA mA mA VIL Low Level Input Voltage (CD4050BM Only) lIOl k 1 mA VDD e 5V VO e 0 5V VDD e 10V VO e 1V VDD e 15V VO e 1 5V lIOl k 1 mA VDD e 5V VO e 4 5V VDD e 10V VO e 9V VDD e 15V VO e 13 5V lIOl k 1 mA VDD e 5V VO e 4 5V VDD e 10V VO e 9V VDD e 15V VO e 13 5V lIOl k 1 mA VDD e 5V VO e 0 5V VDD e 10V VO e 1V VDD e 15V VO e 1 5V VIH e VDD VIL e 0V VDD e 5V VO e 0 4V VDD e 10V VO e 0 5V VDD e 15V VO e 1 5V VIL Low Level Input Voltage (CD4049UBM Only) VIH High Level Input Voltage (CD4050BM Only) 35 70 11 0 40 80 12 0 46 98 29 2 75 55 8 25 35 75 11 5 5 12 40 VIH High Level Input Voltage (CD4049UBM Only) IOL Low Level Output Current (Note 3) Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices should be operated at these limits The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device operation Note 2 VSS e 0V unless otherwise specified Note 3 These are peak output current capabilities Continuous output current is rated at 12 mA maximum The output current should not be allowed to exceed this value for extended periods of time IOL and IOH are tested one output at a time 2 . DC Electrical Characteristics CD4049M Symbol IOH Parameter High Level Output Current (Note 3) Conditions CD4050BM (Note 2) (Continued) b 55 C a 25 C a 125 C Units Min VIH e VDD VIL e 0V VDD e 5V VO e 4 6V VDD e 10V VO e 9 5V VDD e 15V VO e 13 5V VDD e 15V VIN e 0V VDD e 15V VIN e 15V b1 3 b2 6 b8 0 Max Min b1 1 b2 2 b7 2 Typ b1 6 b3 6 b 12 b 10 b 5 Max Min b 0 72 b1 5 b5 0 Max mA mA mA b1 0 IIN Input Current b0 1 b0 1 01 10b5 01 10 mA mA Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices should be operated at these limits The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device operation Note 2 VSS e 0V unless otherwise specified Note 3 These are peak output current capabilities Continuous output current is rated at 12 mA maximum The output current should not be allowed to exceed this value for extended periods of time IOL and IOH are tested one output at a time DC Electrical Characteristics CD4049UBC Symbol IDD Parameter Quiescent Device Current Conditions VDD e 5V VDD e 10V VDD e 15V VIH e VDD VIL e 0V lIOl k 1 mA VDD e 5V VDD e 10V VDD e 15V VIH e VDD VIL e 0V lIOl k 1 mA VDD e 5V VDD e 10V VDD e 15V CD4050BC (Note 2) b 40 C a 25 C a 85 C Units mA mA mA Min Max 4 8 16 Min Typ 0 03 0 05 0 07 Max 40 80 16 0 Min Max 30 60 120 VOL Low Level Output Voltage 0 05 0 05 0 05 0 0 0 0 05 0 05 0 05 0 05 0 05 0 05 V V V VOH High Level Output Voltage 4 95 9 95 14 95 15 30 40 10 20 30 35 70 11 0 40 80 12 0 4 95 9 95 14 95 5 10 15 2 25 45 6 75 15 25 35 15 30 40 10 20 30 4 95 9 95 14 95 15 30 40 10 20 30 35 70 11 0 40 80 12 0 V V V V V V V V V V V V V V V VIL Low Level Input Voltage (CD4050BC Only) lIOl k 1 mA VDD e 5V VO e 0 5V VDD e 10V VO e 1V VDD e 15V VO e 1 5V lIOl k 1 mA VDD e 5V VO e 4 5V VDD e 10V VO e 9V VDD e 15V VO e 13 5V lIOl k 1 mA VDD e 5V VO e 4 5V VDD e 10V VO e 9V VDD e 15V VO e 13 5V lIOl k 1 mA VDD e 5V VO e 0 5V VDD e 10V VO e 1V VDD e 15V VO e 1 5V VIL Low Level Input Voltage (CD4049UBC Only) VIH High Level Input Voltage (CD4050BC Only) 35 70 11 0 40 80 12 0 2 75 55 8 25 35 75 11 5 VIH High Level Input Voltage (CD4049UBC Only) Note 1 ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices should be operated at these limits The table of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteristics’’ provides conditions for actual device operation Note 2 VSS e 0V unless otherwise specified Note 3 These are peak output current capabilities Continuous output current is rated at 12 mA maximum The output current should not be allowed to exceed this value for extended periods of time IOL and IOH are tested one output at a time 3 . DC Electrical Characteristics CD4049UBC Symbol IOL Parameter Low Level Output Current (Note 3) Conditions VIH e VDD VIL e 0V VDD e 5V VO e 0 4V VDD e 10V VO e 0 5V VDD e 15V VO e 1 5V CD4050BC (Note 2) (Continued) b 40 C a 25 C a 85 C Units Min 46 98 29 Max Min 40 85 25 b0 9 b1 9 b6 2 Typ 5 12 40 b1 6 b3 6 b 12 Max Min 32 68 20 b 0 72 b1 5 b5 Max mA mA mA mA mA mA b1 0 IOH High Level Output Current VIH e VDD VIL e 0V b1 0 (Note 3) VDD e 5V VO e 4 6V VDD e 10V VO e 9 5V b2 1 VDD e 15V VO e 13 5V b7 1 Input Current VDD e 15V VIN e 0V VDD e 15V VIN e 15V b0 3 IIN b 0 3 b 10 b 5 03 03 10b5 10 mA mA AC Electrical Characteristics CD4049UBM CD4049UBC TA e 25 C CL e 50 pF RL e 200k tr e tf e 20 ns unless otherwise specified Symbol tPHL Parameter Propagation Delay Time High-to-Low Level Propagation Delay Time Low-to-High Level Transition Time High-to-Low Level Transition Time Low-to-High Level Input Capacitance Conditions VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V Any Input Min Typ 30 20 15 45 25 20 30 20 15 60 30 25 15 Max 65 40 30 85 45 35 60 40 30 120 55 45 22 5 Units ns ns ns ns ns ns ns ns ns ns ns ns pF tPLH tTHL tTLH CIN AC Parameters are guaranteed by DC correlated testing AC Electrical Characteristics CD4050BM CD4050BC TA e 25 C CL e 50 pF RL e 200k tr e tf e 20 ns unless otherwise specified Symbol tPHL Parameter Propagation Delay Time High-to-Low Level Propagation Delay Time Low-to-High Level Transition Time High-to-Low Level Transition Time Low-to-High Level Input Capacitance Conditions VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V VDD e 5V VDD e 10V VDD e 15V Any Input Min Typ 60 25 20 60 30 25 30 20 15 60 30 25 5 Max 110 55 30 120 55 45 60 40 30 120 55 45 75 Units ns ns ns ns ns ns ns ns ns ns ns ns pF tPLH tTHL tTLH CIN AC Parameters are guaranteed by DC correlated testing 4 Schematic Diagrams CD4049UBM CD4049UBC 1 of 6 Identical Units CD4050BM CD4050BC 1 of 6 Identical Units TL F 5971 – 3 TL F 5971 – 4 Switching Time Waveforms TL F 5971 – 5 Typical Applications CMOS to TTL or CMOS at a Lower VDD Note VDD1 t VDD2 Note In the case of the CD4049UBM CD4049UBC the output drive capability increases with increasing input voltage E g If VDD1 e 10V the CD4049UBM CD4049UBC could drive 4 TTL loads TL F 5971 – 6 5 CD4049UBM CD4049UBC Hex Inverting Buffer CD4050BM CD4050BC Hex Non-Inverting Buffer Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number CD4049UBMJ CD4049UBCJ CD4049BMJ or CD4049BCJ NS Package Number J16A Molded Dual-In-Line Package (N) Order Number CD4050BMN CD4050BCN CD4050BMN or CD4050BCN NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1(800) 272-9959 Fax 1(800) 737-7018 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Europe Fax (a49) 0-180-530 85 86 Email cnjwge tevm2 nsc com Deutsch Tel (a49) 0-180-530 85 85 English Tel (a49) 0-180-532 78 32 Fran ais Tel (a49) 0-180-532 93 58 Italiano Tel (a49) 0-180-534 16 80 National Semiconductor Hong Kong Ltd 13th Floor Straight Block Ocean Centre 5 Canton Rd Tsimshatsui Kowloon Hong Kong Tel (852) 2737-1600 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications 95 10 1.0 1.C.3mS single half sine wave superimposed on rated load (JEDEC method) Maximum Instantaneous Forward Voltage @ 6.375”(9.1) . P. Measured at 1.3kg) tension . .375”(9.board mounted with 1.1”× 1.2) 1.1) DIA . resistive or inductive load For capacitive load derate current by 20% SYMBOLS Maximum Repetitive Peak Reverse Voltage Maximum RMS Voltage Maximum DC Blocking Voltage Maximum Average Forward Rectified Current 0. MECHANICAL DATA • • • • • • Case: Transfer molded plastic Epoxy: UL94V-O rate flame retardant Polarity: Color band denotes cathode end Lead: Plated axial lead.5mm)lead length.0 Ampere Low coat construction Low forward voltage drop Low reverse leakage High forward surge current capability High temperature soldering guaranteed: 260℃/10 secods/. solderable per MIL-STD-202E method 208C Mounting position: Any Weight: 0. 60Hz.0A Maximum DC Reverse Current at Rated DC Blocking Voltage per element TA = 25℃ TA = 100℃ VRRM VRMS VDC I(AV) IFSM VF IR IR(AV) CJ RθJA TJ，TSTG 6A05 50 35 50 6A1 100 70 100 6A2 200 140 200 6A4 400 280 400 6.048(1. 2.0V Volts. full cycle average 0.07 ounce. E-mail: sales@cnmic. 2.6) 1.5mm) lead length at T A= 60℃ Peak Forward Surge Current 8.0(25.5mm)lead length at TL=105℃ Typical Junction Capacitance (Note 1) Typical Thermal Resistance (Note 2) Operating Junction Temperature Range -55 to +150 Notes: 1.AXIAL SILASTIC GUARD JUNCTION STANDARD RECTIFIER 6A05 THRU 6A10 FEATURES • • • • • VOLTAGE RANGE CURRENT 50 to 1000 Volts 6.3) DIA . Thermal Resistance from junction to Ambient at .375”(9.com Web Site: www.0 300 0.052(1.360(9.0MHz and Applied Reverse Voltage of 4.4) MIN.340(8.360(9.6) .cnmic. half wave.com .0 150 10 6A6 600 420 600 6A8 800 560 800 6A10 1000 700 1000 UNITS Volts Volts Volts Amps Amps Volts µAmps mAmps mAmps pF ℃/W ℃ Maximum Full Load Reverse Current.1”(30× 30mm)copper heatsink .340(8.0(25.0 grams MAXIMUM RATINGS AND ELECTRICAL CHARACTERISTICS • • • Dimensions in inches and (millimeters) Ratings at 25OC ambient temperature unless otherwise specified Single Phase.4) MIN.375”(9.5mm)lead length at 5 lbs(2. 0 CURRENT.0 10 (A) 0.0 FIG.8 1.1 0. (A) 200 8.6 1.1 1. Board Mounting 4.C.0 100 1. Board Mounting 0 0 25 50 60 75 100 125 150 175 0 1 2 5 8 10 20 50 100 AMBIENT TEMPERATURE.com .cnmic.AXIAL SILASTIC GUARD JUNCTION STANDARD RECTIFIER 6A05 THRU 6A10 VOLTAGE RANGE CURRENT 50 to 1000 Volts 6.3-TYPICAL INSTANTANEOUS FORWARD CHARACTERISTICS 1000 FIG. 1.3ms Single Half Sine-Wave (JEDEC Method) =T T j jmax (A) 3.com Web Site: www.C. (° C) NUMBER OF CYCLES AT 60 Hz FIG.0 Ampere RATING AND CHRACTERISTIC CURVES 6A05 Thur 6A10 FIG. (mA) Tj =100° C 100 INSTANTANEOUS FORWARD CURRENT.4 1.(%) INSTANTANEOUS FORWARD VOLTAGE.(V) FIG.C.0 PERCENT OF RATED PEAK REVERSE VOLTAGE.0 2.6 0.0 100 REVERSE VOLTAGE.01 0 20 40 60 80 100 120 140 0.0 P.0 4.4-TYPICAL REVERSE CHARACTERISTICS 20 10 INSTANTANEOUS REVERSE CURRENT. 60 Hz Resistive or Inductive loads Group Plane 1" X 1" Copper Surface Area Recommended P.(VOLTS) E-mail:
[email protected] PEAK FORWARD SURGE 5.0 1.2-MAXIMUM NON-REPETITIVE PEAK FORWARD SURGE CURRENT 300 AVERAGE FORWARD CURRENT.0 10.1-TYPICAL FORWARD CURRENT DERATING CURVE 6.(pF) 100 TJ=25° C F=1MHz 10 0.1 1 Tj =25° C Pulse Width=300us 1% Duty Cycle Tj =25° C 0. Board Standard P.2 1.8 2.5-TYPICAL JUNCTION CAPACITANCE 1000 CAPACITANCE. Data Sheet No.20V 120 & 94 ns 10 ns Packages Description The IR2110 is a high voltage. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 500 volts. Logic inputs are compatible with standard CMOS or LSTTL outputs.) Delay Matching 500V max. Typical Connection up to 500V HO VDD HIN SD LIN VSS VCC V DD HIN SD LIN V SS VCC COM LO VB VS TO LOAD CONTROL INTEGRATED CIRCUIT DESIGNERS MANUAL B-25 . PD-6. 2A / 2A 10 . Propagation delays are matched to simplify use in high frequency applications. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction.011E IR2110 HIGH AND LOW SIDE DRIVER Features n Floating channel designed for bootstrap operation Fully operational to +500V Tolerant to negative transient voltage dV/dt immune n Gate drive supply range from 10 to 20V n Undervoltage lockout for both channels n Separate logic supply range from 5 to 20V Logic and power ground ±5V offset n CMOS Schmitt-triggered inputs with pull-down n Cycle by cycle edge-triggered shutdown logic n Matched propagation delay for both channels n Outputs in phase with inputs Product Summary VOFFSET IO+/VOUT ton/off (typ. Proprietary HVIC and latch immune CMOS technologies enable ruggedized monolithic construction. high speed power MOSFET and IGBT driver with independent high and low side referenced output channels. 3 VCC .IR2110 Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur.3 50 1.6 1.3 -0. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions. Logic state held for VS of -4V to -VBS.3 VSS + 25 VCC + 0.3 25 VCC + 0. Additional information is shown in Figures 28 through 35.6 1.0. LIN & SD) Allowable Offset SupplyVoltage Transient (Figure 2) Package Power Dissipation @ TA ≤ +25°C (14 Lead DIP) (14 Lead DIP w/o Lead 4) (16 Lead DIP w/o Leads 5 & 6) (16 Lead SOIC) Value Min. For proper operation the device should be used within the recommended conditions. LIN & SD) AmbientTemperature Value Min.3 VB + 0. The VS and VSS offset ratings are tested with all supplies biased at 15V differential.3 -0. Symbol VB VS VHO VCC VLO VDD VSS VIN dV s/dt PD Parameter Definition High Side Floating SupplyVoltage High Side Floating Supply Offset Voltage High Side Floating OutputVoltage Low Side Fixed Supply Voltage Low Side Output Voltage Logic SupplyVoltage Logic Supply OffsetVoltage Logic InputVoltage (HIN. Junction to Ambient (14 Lead DIP) (14 Lead DIP w/o Lead 4) (16 Lead DIP w/o Leads 5 & 6) (16 Lead SOIC) TJ TS TL JunctionTemperature Storage Temperature LeadTemperature (Soldering.25 VS . Symbol VB VS VHO VCC VLO VDD VSS VIN TA Parameter Definition High Side Floating Supply AbsoluteVoltage High Side Floating Supply Offset Voltage High Side Floating OutputVoltage Low Side Fixed Supply Voltage Low Side Output Voltage Logic SupplyVoltage Logic Supply OffsetVoltage Logic InputVoltage (HIN. 525 VB + 0. 10 seconds) °C/W °C Recommended Operating Conditions The Input/Output logic timing diagram is shown in Figure 1.3 -0. All voltage parameters are absolute voltages referenced to COM.3 — — — — — — — — — — -55 — Max.3 VB .25 75 85 75 100 150 150 300 Units V V/ns W RθJA Thermal Resistance. Typical ratings at other bias conditions are shown in Figures 36 and 37.3 VDD + 0. B-26 CONTROL INTEGRATED C IRCUIT DESIGNERS MANUAL .25 VSS . -0.5 1. VS + 10 Note 1 VS 10 0 VSS + 5 -5 VSS -40 Max. VS + 20 500 VB 20 VCC VSS + 20 5 VDD 125 Units V °C Note 1: Logic operational for VS of -4 to +500V.0. Typ. VBIAS . VDD) = 15V. The V O and IO parameters are referenced to COM and are applicable to the respective output leads: HO or LO. VO Offset Supply Leakage Current Quiescent VBS Supply Current Quiescent VCC Supply Current Quiescent VDD Supply Current Logic “1” Input Bias Current Logic “0” Input Bias Current VBS Supply Undervoltage Positive Going Threshold VBS Supply Undervoltage Negative Going Threshold VCC Supply Undervoltage Positive Going Threshold VCC Supply Undervoltage Negative Going Threshold Output High Short Circuit Pulsed Current Output Low Short Circuit Pulsed Current Figure Min. The VIN. Max. HS & LS Turn-On/Off Value Figure Min. The dynamic electrical characteristics are measured using the test circuit shown in Figure 3.VO Low Level Output Voltage.0 7.5 7. 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 9.0 2. CL = 1000 pF.2 8.0 1.5 2.4 7. VIN = 0V PW ≤ 10 µs V µA V IO = 0A IO = 0A VB = VS = 500V VIN = 0V or VDD VIN = 0V or VDD VIN = 0V or VDD VIN = VDD VIN = 0V CONTROL I NTEGRATED CIRCUIT DESIGNERS MANUAL B-27 .7 9. TA = 25°C and VSS = COM unless otherwise specified.4 9.0 2. VDD) = 15V. Units Test Conditions 7 8 9 10 11 — — — — — — — 120 94 110 25 17 — 150 125 140 35 25 10 Figure 5 VS = 0V VS = 500V VS = 500V ns Static Electrical Characteristics VBIAS (VCC . TA = 25°C and VSS = COM unless otherwise specified. LIN and SD.6 9.2 2. VIN = VDD PW ≤ 10 µs VO = 15V. VBS.0 9.5 — — — — — — — — — 7. Symbol VIH VIL VOH VOL I LK I QBS I QCC I QDD IIN+ IINVBSUV+ VBSUVVCCUV+ VCCUVI O+ I O- Parameter Definition Logic “1” Input Voltage Logic “0” Input Voltage High Level Output Voltage.6 8. Units Test Conditions — — — — — 125 180 15 20 — 8. Symbol t on t off t sd tr tf MT Parameter Definition Turn-On Propagation Delay Turn-Off Propagation Delay Shutdown Propagation Delay Turn-On Rise Time Turn-Off Fall Time Delay Matching.5 8.IR2110 Dynamic Electrical Characteristics VBIAS (VCC .5 — 6.0 Value Typ.4 — — A VO = 0V. Max.2 0. VBS. VTH and I IN parameters are referenced to VSS and are applicable to all three logic input leads: HIN.1 50 230 340 30 40 1. IR2110 Functional Block Diagram VB VDD R Q S HIN HV LEVEL SHIFT UV DETECT PULSE FILTER R R S Q HO VDD /VCC LEVEL SHIFT PULSE GEN VS SD UV DETECT VCC VDD /VCC LEVEL SHIFT LIN R Q VSS S LO DELAY COM Lead Definitions Lead Symbol Description VDD HIN SD LIN V SS VB HO VS VCC LO COM Logic supply Logic input for high side gate driver output (HO). in phase Logic ground High side floating supply High side gate drive output High side floating supply return Low side supply Low side gate drive output Low side return Lead Assignments 14 Lead DIP 14 Lead DIP w/o Lead 4 16 Lead DIP w/o Leads 4 & 5 16 Lead SOIC (Wide Body) IR2110 B-28 IR2110-1 Part Number IR2110-2 IR2110S CONTROL INTEGRATED C IRCUIT DESIGNERS MANUAL . in phase Logic input for shutdown Logic input for low side gate driver output (LO). 5 µm PSG (SiO2) 1.IR2110 Device Information Process & Design Rule Transistor Count Die Size Die Outline HVDCMOS 4.000Å 8 µm X 8 µm PSG (SiO2) 1.1%) 6 µm 9 µm 20.1 Thermo Sonic Au (1.5 µm Proprietary* Proprietary* Full Cut Ablebond 84 .0 mil / 1.3 mil) Cu Ag Pb : Sn (37 : 63) 14 & 16 Lead PDIP / 16 Lead SOIC EME6300 / MP150 / MP190 CONTROL I NTEGRATED CIRCUIT DESIGNERS MANUAL B-29 .0 µm 220 100 X 117 X 26 (mil) Thickness of Gate Oxide Connections First Layer Second Layer Contact Hole Dimension Insulation Layer Passivation (1) Passivation (2) Method of Saw Method of Die Bond Wire Bond Leadframe Material Width Spacing Thickness Material Width Spacing Thickness Material Thickness Material Thickness Material Thickness Package Remarks: * Patent Pending Method Material Material Die Area Lead Plating Types Materials 800Å Poly Silicon 4 µm 6 µm 5000Å Al .Si (Si: 1.0% ±0. IR2110 Figure 1. Switching Time Waveform Definition HIN LIN 50% 50% SD 50% LO HO 10% t sd MT MT 90% HO LO 90% LO Figure 3. Switching Time Test Circuit 10% 10% Figure 4. Delay Matching Waveform Definitions B-30 CONTROL INTEGRATED C IRCUIT DESIGNERS MANUAL . Input/Output Timing Diagram Figure 2. Floating Supply Voltage Transient Test Circuit HIN LIN ton 50% 50% tr 90% t off 90% tf HO LO Figure 3. Shutdown Waveform Definitions HO Figure 6. 150 Typ. 100 Typ. 150 Typ. Turn-Off Time vs. 100 Typ. 100 50 50 0 -50 -25 0 25 50 75 100 125 Temperature (°C) 0 10 12 14 16 18 20 VBIAS Supply Voltage (V) Figure 8A. Turn-On Time vs. Shutdown Time vs.IR2110 250 250 200 Turn-On Delay Time (ns) Turn-On Delay Time (ns) 200 Max. 100 Typ. 150 150 Typ. 100 50 50 0 -50 -25 0 25 50 75 100 125 Temperature (°C) 0 10 12 14 16 18 20 VBIAS Supply Voltage (V) Figure 9A. 150 Max. 100 50 50 0 -50 -25 0 25 50 75 100 125 Temperature (°C) 0 10 12 14 16 18 20 VBIAS Supply Voltage (V) Figure 7A. Voltage 250 250 200 Turn-Off Delay Time (ns) Turn-Off Delay Time (ns) 200 Max. Shutdown Time vs. Voltage CONTROL I NTEGRATED CIRCUIT DESIGNERS MANUAL B-31 . Temperature Figure 9B. Turn-On Time vs. 150 Max. Voltage 250 250 200 Shutdown Delay Time (ns) Shutdown Delay time (ns) 200 Max. Turn-Off Time vs. Temperature Figure 8B. Temperature Figure 7B. Max. 10 10 0 -50 -25 0 25 50 75 100 125 Temperature (°C) 0 10 12 14 16 18 20 VBIAS Supply Voltage (V) Figure 11A. Typ.IR2110 100 100 80 Turn-On Rise Time (ns) Turn-On Rise Time (ns) 80 60 60 Max. Logic “1” Input Threshold vs. Logic “1” Input Threshold vs.0 15. Typ.0 Min.5 15 17. 12. Turn-On Rise Time vs.0 5 7. Temperature Figure 12B.0 6.0 -50 -25 0 25 50 75 100 125 Temperature (°C) 0. Voltage B-32 CONTROL INTEGRATED C IRCUIT DESIGNERS MANUAL . 30 20 Typ.0 12. 20 20 0 -50 -25 0 25 50 75 100 125 Temperature (°C) 0 10 12 14 16 18 20 VBIAS Supply Voltage (V) Figure 10A. 3.5 20 V DD Logic Supply Voltage (V) Figure 12A.0 Logic "1" Input Threshold (V) Min. Voltage 15. Turn-Off Fall Time vs.0 0. 40 Typ.0 3.0 Logic "1" Input Threshold (V) 9.5 10 12.0 6. Turn-Off Fall Time vs. 40 Max. Temperature Figure 11B. Turn-On Rise Time vs. 20 Max.0 9. Voltage 50 50 40 Turn-Off Fall Time (ns) Turn-Off Fall Time (ns) 40 30 Max. Temperature Figure 10B. 00 Max.0 Max. 3. 0.5 20 V DD Logic Supply Voltage (V) Figure 15A.0 9.0 0.00 4.20 Max.0 12.5 15 17.00 High Level Output Voltage (V) High Level Output Voltage (V) 4.00 0. Temperature Figure 13B. Temperature Figure 15B.0 0.0 3.0 9.00 -50 0.5 10 12. Logic “0” Input Threshold vs.0 5 7.00 5.00 Max.5 15 17. Voltage CONTROL I NTEGRATED CIRCUIT DESIGNERS MANUAL B-33 . Logic “0” Input Threshold vs. 6.00 15. High Level Output vs. 1. Low Level Output vs.0 Max.00 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (°C) VBIAS Supply Voltage (V) Figure 14A. Voltage 1.0 5 7. Temperature Figure 14B.60 9.0 Min.00 3. Low Level Output vs.0 6. 0.00 2. High Level Output vs.0 0.40 6.00 1.80 Low Level Output Voltage (V) Logic "1" Input Threshold (V) 12.5 20 V DD Logic Supply Voltage (V) Figure 13A.IR2110 15. 2.00 -50 -25 0 25 50 75 100 125 Temperature (°C) 0.0 0.0 15.0 Logic "0" Input Threshold (V) Logic "0" Input Threshold (V) 12.5 10 12.0 3.0 -50 -25 0 25 50 75 100 125 Temperature (°C) 0. Voltage 5.00 3. 0 -50 -25 0 25 50 75 100 125 Temperature (°C) 0 10 12 14 16 18 20 V BS Floating Supply Voltage (V) Figure 17A. 0 -50 -25 0 25 50 75 100 125 Temperature (°C) 0 10 12 14 16 18 20 VCC Fixed Supply Voltage (V) Figure 18A. Voltage 500 500 400 V BS Supply Current (µA) V BS Supply Current (µA) 400 300 Max. VBS Supply Current vs. V CC Supply Current vs. 300 200 Typ. Voltage 625 625 500 VCC Supply Current (µA) VCC Supply Current (µA) 500 375 Max. 100 Max. 375 250 Typ. 250 Max. Voltage B-34 CONTROL INTEGRATED C IRCUIT DESIGNERS MANUAL . VCC Supply Current vs. 0 -50 -25 0 25 50 75 100 125 Temperature (°C) 0 0 100 200 300 400 500 V B Boost Voltage (V) Figure 16A. VBS Supply Current vs. 200 Max. 125 125 Typ. Offset Supply Current vs. Offset Supply Current vs. 100 100 Typ. Temperature Figure 17B. Temperature Figure 16B. Temperature Figure 18B.IR2110 500 500 Offset Supply Leakage Current (µA) Offset Supply Leakage Current (µA) 400 400 300 300 200 200 100 Max. 00 2. 0 -50 -25 0 25 50 75 100 125 Temperature (°C) 0 5 7.00 -50 -25 0 25 50 75 100 125 Temperature (°C) 0. Logic “1” Input Current vs. 0 -50 -25 0 25 50 75 100 125 Temperature (°C) 0 5 7. Voltage 100 100 Logic "1" Input Bias Current (µA) Logic "1" Input Bias Current (µA) 80 80 60 60 40 Max.00 Max. Voltage CONTROL I NTEGRATED CIRCUIT DESIGNERS MANUAL B-35 . VDD Supply Current vs.5 20 VDD Logic Supply Voltage (V) Figure 20A. Voltage 5. Temperature Figure 21B. Temperature Figure 19B.5 20 V DD Logic Supply Voltage (V) Figure 19A.00 5. Temperature Figure 20B. T yp. 40 20 Typ. Max.5 10 12.5 10 12.5 20 V DD Logic Supply Voltage (V) Figure 21A. 80 60 60 40 40 20 20 Typ. Typ.5 10 12.00 4.5 15 17.00 3. VDD Supply Current vs.00 Logic "0" Input Bias Current (µA) 3.00 Logic "0" Input Bias Current (µA) 4.IR2110 100 100 80 VDD Supply Current (µA) VDD Supply Current (µA) Max. 20 Max. Max. Logic “0” Input Current vs.00 0.5 15 17. Logic “0” Input Current vs.00 2. Logic “1” Input Current vs.5 15 17.00 5 7.00 1. 1. Output Source Current vs. 3.0 7.0 Min.00 1.0 -50 -25 0 25 50 75 100 125 Temperature (°C) Figure 22. 1.0 VCC Undervoltage Lockout + (V) Max.0 Typ.00 -50 0. 9. Min. Temperature Figure 26B.(V) 10. 6. 0.00 2. 8.0 -50 -25 0 25 50 75 100 125 Temperature (°C) Figure 24.0 11.0 Min.0 Min. 8.0 Typ.0 Max. Voltage B-36 CONTROL INTEGRATED C IRCUIT DESIGNERS MANUAL .0 Max.00 Typ.0 Min.0 7.IR2110 11. Temperature 11.0 11. 8.0 7.00 5.0 Typ. 9. 9. Temperature Figure 23.00 Typ.00 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (°C) V BIAS Supply Voltage (V) Figure 26A.00 2. 9. VBS Undervoltage (-) vs.00 3. VCC Undervoltage (-) vs.00 Min. Temperature Figure 25. Temperature 5. Output Source Current vs. VBS Undervoltage (+) vs.0 -50 -25 0 25 50 75 100 125 Temperature (°C) 6.0 Max.0 8.0 10.(V) 10. V CC Undervoltage Lockout . VBS Undervoltage Lockout . 6.0 VBS Undervoltage Lockout + (V) 10.0 -50 -25 0 25 50 75 100 125 Temperature (°C) 6. Typ.0 7.00 4. VCC Undervoltage (+) vs.00 Output Source Current (A) Output Source Current (A) 4. 00 -50 0. Frequency (IRFBC20) RGATE = 33Ω.00 3.00 Output Sink Current (A) Output Sink Current (A) 4. IR2110 TJ vs. Voltage 150 320V 150 320V 125 Junction Temperature (°C) 140V 125 140V 100 Junction Temperature (°C) 100 75 10V 75 10V 50 50 25 25 0 1E+2 1E+3 1E+4 Frequency (Hz) 1E+5 1E+6 0 1E+2 1E+3 1E+4 Frequency (Hz) 1E+5 1E+6 Figure 28. VCC = 15V Ω 150 320V 140V 150 320V 140V 125 Junction Temperature (°C) Junction Temperature (°C) 125 10V 100 10V 100 75 75 50 50 25 25 0 1E+2 1E+3 1E+4 Frequency (Hz) 1E+5 1E+6 0 1E+2 1E+3 1E+4 Frequency (Hz) 1E+5 1E+6 Figure 30.00 -25 0 25 50 75 100 125 10 12 14 16 18 20 Temperature (°C) V BIAS Supply Voltage (V) Figure 27A. Min. Output Sink Current vs.00 Min. VCC = 15V Ω Figure 29. 1. VCC = 15V Ω CONTROL I NTEGRATED CIRCUIT DESIGNERS MANUAL B-37 . 3. Frequency (IRFBC30) RGATE = 22Ω . Frequency (IRFPE50) RGATE = 10Ω .00 2.00 2. 0.00 Typ. VCC = 15V Ω Figure 31. IR2110 TJ vs. IR2110 TJ vs.IR2110 5.00 Typ. Temperature Figure 27B. Frequency (IRFBC40) RGATE = 15Ω. IR2110 TJ vs. Output Sink Current vs.00 4.00 1.00 5. 0 10 12 14 16 18 20 V BS Floating Supply Voltage (V) 0. VCC = 15V Ω 0. Maximum VS Negative Offset vs. -8.0 -10. IR2110S TJ vs.0 4.0 VSS Logic Supply Offset Voltage (V) -2. -4. Frequency (IRFPE50) RGATE = 10Ω.0 10 12 14 16 18 20 V CC Fixed Supply Voltage (V) Figure 36. Frequency (IRFBC40) RGATE = 15Ω.0 Typ. Maximum VSS Positive Offset vs.0 -6. VCC = 15V Ω 150 320V 140V 150 320V 140V 10V 125 Junction Temperature (°C) 10V 125 Junction Temperature (°C) 100 100 75 75 50 50 25 25 0 1E+2 1E+3 1E+4 Frequency (Hz) 1E+5 1E+6 0 1E+2 1E+3 1E+4 Frequency (Hz) 1E+5 1E+6 Figure 34.0 20. VCC = 15V Ω Figure 33. Frequency (IRFBC30) RGATE = 22Ω.0 Typ.IR2110 150 320V 140V 150 320V 140V 125 Junction Temperature (°C) Junction Temperature (°C) 125 100 100 10V 75 10V 75 50 50 25 25 0 1E+2 1E+3 1E+4 Frequency (Hz) 1E+5 1E+6 0 1E+2 1E+3 1E+4 Frequency (Hz) 1E+5 1E+6 Figure 32.0 8. IR2110S TJ vs. VCC = 15V Ω Figure 35. VCC Supply Voltage B-38 CONTROL INTEGRATED C IRCUIT DESIGNERS MANUAL . IR2110S TJ vs. VBS Supply Voltage Figure 37. IR2110S TJ vs.0 12. Frequency (IRFBC20) RGATE = 33Ω.0 VS Offset Supply Voltage (V) 16. REFERENCES Page 93 . 10. 153. 2008 Page 94 . “Continuous- conduction-mode SEPIC converter with low reverse-recovery loss for power factor correction”.-M.-H.-Electr. IEEE TRANSACTIONS ON POWER ELECTRONICS. Roberto Prieto. Member. Kwon. IEEE. 2005. Wu and M. Dubrovnik. IEEE ISIE 2005. E.-E. May 5-9. No. Vol. IEEE. MAY 2003 [ 5 ] Alenka Hren. Shen and Y. José A. Primoz Slibar. Kim and B.[ 1 ] C. W. Calimanesti-Caciulata.-H. 5. National Semiconductor Application Note 1484. [ 4 ] Oscar García.. Chen. NO. IEEE/978-1-4244-1706-3/08. Power Appl. “Full order Dynamic Model of SEPIC Converter”. Alin Grama. and Javier Uceda. Lee. Choi. 3. June 20-23. IEEE. Member. “A Modified Sepic Converter with Soft Switching Technology”. Senior Member. 18. IEE Proc. Romania. Croatia [ 6 ] Wei Gu. “Designing A SEPIC Converter”. “Single Phase Power Factor Correction: A Survey”. J. IEEE. VOL. Florin Hurgoi.-L.2001. Member. April 30. Pedro Alou. Cobos. September 2006 [ 3 ] Ovidiu Pop. Dongbing Zhang. [ 2 ] J.-H. Kwon. Gabriel Chindris. “Power Factor Correction Circuit with a New Modified SEPIC Converter”.-Y.-J. 24th International Spring Seminar on Electronics Technology.