11001101011010101010101010 1010101010111 0100101001110 11010 SAR ADC’s vs Delta Sigma ADC’s: Different Architectures for Different Applications Needs October, 2015 Agenda • Introduction • SAR ADC Architecture • Delta Sigma ADC Architecture • SAR and Delta Sigma Comparison • Typical Application Examples • Featured TI Designs 2 The Signal Chain Analog to Digital Converter Types The three most common ADC architectures include the Successive Approximation Register (SAR), Delta Sigma (ΔΣ), and Pipeline. Reference Reference Amplifier ADC SAR, ΔΣ & Pipeline MCU DSP FPGA Processor DAC Amplifier 3 SAR Architecture ADC Technologies Advantages Converter Resolution (bits) 32 24 • Low Latency-time • High Accuracy • Typically Low Power • Easy to Use ~ Disadvantages 20 • Max FSAMP of 2-5Mhz Delta Sigma 16 Pipeline SAR 12 8 10 100 1K 10K 100K 1M 10M 100M 1G Conversion Rate (SPS) 4 . Delta-Sigma Architecture ADC Technologies Advantages Converter Resolution (bits) 32 24 • High Resolution • Low Noise • High Stability • Low Power ~ Disadvantages • Cycle-Latency 20 Delta Sigma 16 Pipeline SAR 12 8 10 100 1K 10K 100K Conversion Rate (SPS) 1M 10M 100M 1G 5 . Pipeline Architecture ADC Technologies Advantages • Higher Speeds • Higher Bandwidth Converter Resolution (bits) 32 24 ~ Disadvantages • Lower Resolution • Pipeline Delay/Latency • Higher Power 20 Delta Sigma 16 Pipeline SAR 12 8 10 100 1K 10K 100K 1M 10M 100M 1G Conversion Rate (SPS) 6 . ADC Topology Comparison ADC Topology SAR ADS7xxx ADS8xxx Delta-Sigma ADS10xx/11xx ADS12xxx ADS13xxx ADS16xx Pipeline Sampling Frequency Resolution Comments ≤ 4 Msps ≤ 1.25 Msps ≤ 16-bit ≤ 18-bit • Easy to Use • Zero Latency • Low Power ≤ 4 Ksps ≤ 4 Msps ≤ 10 Msps > 24-bit ≤ 24-bit ≤ 16-bit • High Resolution • Moderate Cost • High Integration ≤ 200 Msps ≤ 250 Msps ≤ 1000 Msps ≤ 16-bit ≤ 14-bit ≤ 12-bit • High Speed • Expensive • Higher Power 7 . SAR ADC Architecture Successive Approximation Register ADC SAR ADC . How Does a SAR ADC Work? • Similar to a balance scale the MSB LSB is is determined determined last first ? ? ? ? 11 1 MSB 1 ? 1 ½¼ mid LSB 0 ½ 1 ¼ 9 . Typical Topology of a SAR ADC Data Output Register S1 S2 VIN SAR C N-bit Search DAC 10 . switch S2 is open • Sample capacitor is charged to Vin N-bit Search DAC • Switch S1 is open. switch S2 is closed • The digital result is determined 11 .SAR ADC: Acquisition & Conversion Phases Conversion Phase Acquisition Phase Data Register S1 S2 VIN Data Register S1 SAR C S2 VIN SAR C N-bit Search DAC • Switch S1 is closed. SAR ADC Acquisition Phase Acquisition Phase VIN Input Signal DAC SAMPLE & HOLD VIN Data Register S1 RS1 S2 VCSH SAR CSH N-bit Search DAC COMPARATOR VIN 1/2 LSB • It is important that at the end of the acquisition phase that the voltage difference on the sample capacitor and the input voltage is less than ½ of an LSB VCSH(t) VSH0 t0 • The sample capacitor CSH needs to change from the initial voltage to the final value of VIN tAQ Time 12 . CSH • VCSH(t0) is voltage across the CSH.SAR ADC Acquisition Phase Settling Time Acquisition Phase VIN 1/2 LSB Input Signal VIN Data Register S1 RS1 S2 VCSH SAR VCSH(t) CSH VSH0 N-bit Search DAC t0 tAQ Time • VCSH(t) is voltage in time across the sampling capacitor. at start of acquisition • VIN is the input voltage to the ADC • τ is the acquisition time constant and equal to RS1 × CSH RS1 CSH VCSH (t ) VCSH (t0 ) [VIN VCSH (t0 )] (1 e t ) • t is a time variable in seconds 13 . SAR ADC Conversion Phase Conversion Phase Full Scale (FS) Bit = 0 VDAC 3/4FS 1/2FS Bit = 1 Bit = 0 Bit = 0 Analog Input Bit = 1 TEST MSB TEST MSB -1 TEST MSB -2 TEST MSB -3 TEST LSB 1/4FS 0 • S1 is opened and S2 is closed Time DAC Output Digital Output Code = 10100 • The voltage of the sample capacitor is used in the successive approximation process • The MSB is determined first followed by the other bits 14 . Delta Sigma Architecture ΔΣ ADC ΔΣ ADC . Delta Sigma Topology Delta-Sigma Delta Sigma Modulator Modulator Analog Input SAMPLE RATE (Fs) DATA RATE (Fd) Digital Filter Digital Output Decimator Decimator Digital Decimating Filter (usually implemented as a single unit) Fs / Fd = DR (DR = Decimation Ratio) 16 . Modulator Output Delta Sigma Modulator Digital Filter Decimator 17 . 1st Order Delta-Sigma Modulator Frequency Domain e(n) Sigma Σ A(f) 1-bit ADC DOUT Magnitude Magnitude VIN Delta Signal Frequency Signal Quantization Noise Noise Transfer Function Signal Transfer Function 18 . Modulator Output Signal Analog Signal Modulator Output: TIME DOMAIN Believe it or not. the sine wave is in there! Modulator Output: FREQUENCY DOMAIN SIGNAL 1 0 Fs (drawing is approximate) QUANTIZATION NOISE 19 . Higher Order Delta-Sigma Modulators Third Order DS Modulator Second Order DS Modulator First Order DS Modulator Frequency FS 20 . Delta-Sigma A/D Signal Path Delta Sigma Modulator Digital Filter Decimator 21 . ΔΣ Principal DS Modulator Noise Shaping Filter set by Oversampling Ratio Frequency FS 22 . • Common filters: “Sinc” and “Flat Passband” Sinc Filter Flat Passband Filter 23 .Digital Filter • Needed to remove higher frequency noise from modulator output a “low-pass” function • Digital filter architecture determines overall ADC response. Sinc Digital Filter Advantages Sinc filter response • Economical silicon area. easy to implement 0 – Low cost – Low power Low latency • Filter notches can target specific frequencies (ex. 50/60 Hz) Disadvantages • Pass band signal droop • Weak Stop band attenuation for low order Sinc filters -20 Attentuation. dB • Sinc 1 Sinc 3 Sinc 5 -40 -60 -80 Fdata -100 0 1 2 3 4 5 6 Frequency (x Fdata) 24 . Flat Pass Band Filter Advantages • Frequency Response • Very low ripple pass band • Sharp Nyquist transition band Low Ripple Passband • Large stopband attenuation: lower than 100dB (simplify aliasing requirement) • Frequency response scalable with master clock Disadvantages 100dB stop band • Large area – Costly • Multiorder / high tap filter – Large latency 25 . SAR ADC SAR and Delta Sigma Comparison ΔΣ ADC . Delta-Sigma What is the ADC actually converting? DS SAR SAR ADC takes “snapshots” Each conversion command captures the signal level.SAR vs. onto the sample/hold DS ADC calculates an average The signal is sampled continuously 27 . at that point in time. Delta-Sigma How does the ADC control happen? • SAR conversions have Start Conversion Signal • Delta-Sigma is always sampling/converting SAR Converter Start Conversion Conversion Done Delta-Sigma Converter Input Sampling Conversion Done 28 .SAR vs. A SAR converter has zero cycle latency. – Latency is also often specified as cycle latency: number of complete data cycles between the start of conversion and the settled conversion data. This time is usually very short (typically equal to the conversion time). Some Delta-Sigma incorporate filters optimized for fast settling. typically measured from the beginning of the sample period to the time a settled conversion result can be retrieved. or successive approximation process to complete.Latency Comparison SAR ADC ΔΣ ADC ADC Latency – SAR Converter Latency: Amount of time needed for the conversion process. often referred as single-cycle settling filters or Zero Cycle Latency. – Delta-Sigma Converter Latency: Often called settling time. The latency on the delta sigma depends on the characteristics of the digital filter. 29 . so power scales with speed 30 .SAR ADC – Data Output Latency Current ADC Data Out with No Latency tCYCLE Sample N Acquisition Acquisition Conversion Conversion Sample (N+1) Acquisition Acquisition Conversion Conversion CS DOUT Sample (N-1) Data Sample N Data • Output bits are pushed out after the conversion is over but before acquisition of the next sample • No limitation on min value of SCLK as conversion happens on INTCLK • Reduce SCLK frequency for slower operation ADC spends more time in Acquisition phase which is low or zero power. resolution and power • Speed: DC to 5 MSPS • Resolution: 8 to 18 bits • TI Part Numbers: – ADS7xxx – ADS8xxx 31 .SAR ADCs SAR ADC • Very Popular Topology • Attractive in “Point in Time” or Multiplexed Measurements • Advantages – “no latency” • input is sampled once • “balancing” done internally – good tradeoff between speed. PGA. Buffer. Vref) • Very Low Power • Simple Anti-Aliasing Filter • Higher Latency • Typically Requires Configuration of Registers • TI Part Numbers: – ADS10xx/11xx – ADS12xxx/13xxx – ADS16xx 32 .Delta Sigma Considerations • Useful for Lower Bandwidth Signals ΔΣ ADC • Very High Resolution • Very High Linearity • Typically Highly Integrated (Calibration. MUX. SAR ADC SAR and Delta Sigma Typical Application Examples ΔΣ ADC . Precision SAR ADC Applications Motor Control Test & Measurement Motion Control Encoders Bench Equipment Medical Manufacturing / Robotics Measurement Data Acquisition Cards Servo Drives Industrial 3 Phase BLDC Automated Test Equipment Wearables Distributed Control Systems MRI Machines Programmable Logic Controllers Pulse Oximeter Automation & Sensors Diagnostic Equipment Industrial Drives Electrocardiogram Infotainment Advanced Driver Assistance (ADAS) Protection Relays Substation Automation Battery Management Power Grid ABS & Stability Control Intelligent Electronic Devices Circuit Breakers Automotive Motor Control Sensors Smart Grid & Power Automation 34 . Small Packages/Cost PLC / DCS Systems Seismic Data Acquisition Test & Measurement Medical 35 .5ppm • Best-in class SNR/THD • Simple Anti-alias filter • Integrated Digital Filters o Single cycle settling w/ 50/60Hz rejection o Brick-wall implementations • High level of integration o PGA | IDACs | MUX | Buffer | REF o Diagnostics | Sinc/Brick-wall filters • Low Power.Precision ΔΣ ADC Applications Temperature Measurement Pressure Measurement Vibration / Flow Measurement Power / Harmonics Measurement • High Resolution o 16-32 bits o Scalable: speed ↔ resolution • High linearity 0. tricks and techniques from TI precision analog experts TI Designs .com/blogs_/b/precisionhub Tips.ti.More Precision ADC Information Precision ADC Web Page: www.ti.com/precisonadc • Data Sheets & Technical Reference Manuals • Application Notes • Software.ti.Precision: www. Tools & SPICE Model Downloads • Order Evaluation & Performance Demonstration Kits PA SAR ADC E2E™ Support Forum: www.com/precisionadcsupport • Ask Technical Questions • Search for Technical Content Precision HUB Blog Series: e2e.com/precisiondesigns • Reference Designs • Board Schematics & Verification Results 36 .ti. 6V Digital Interface 16 MHz SPI (SCLK) -80 dB THD 3 wire SPI 80dB SFDR JESD8-7A Digital I/O ADS704x Family Input Options: Single Ended | Pseudo Differential | Differential http://www.com/tool/tipd168 TI Designs – Precision Overview Video Link 37 .40°C + 125°C Reference & Supply Reference: AVDD AVdd & DVdd: 1.Featured TI Designs Functional Diagram ADS7042 Temperature Range SAR ADC Core 12-bit Input Range 1-MSPS Single-Ended Input ±1 LSB INL (max) Vin: 0V to AVDD ±1 LSB DNL (max) 70 dB SNR Amal Kundu Matthew W Hann Rafael Ordonez .ti.65V – 3.
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