File hosted by educationobserver.com/forum 1) a. Who is the brain of computer: ALU b. CPU d. None of these c. 2) a. MU Which technology using the microprocessor is fabricated on a single chip: POS b. MOS d. ABM c. 3) a. b. c. d. 4) a. ALU MOS stands for: Metal oxide semiconductor Memory oxide semiconductor Metal oxide select None of these In which form CPU provide output: Computer signals b. Digital signals d. None of these c. 5) a. b. c. d. 6) a. Metal signals How many types of microprocessor comprises: 3 6 9 4 Which is the microprocessor comprises: Register section b. One or more ALU d. All of these c. 7) a. Control unit The register section is related to______ of the computer: Processing b. ALU d. None of these c. 8) a. b. Main memory What is the store by register: data operands File hosted by educationobserver.com/forum c. d. 9) a. memory None of these How many types of classification of processor based on register section: 1 b. 2 d. 4 a. Calculator c. 3 10) In Microprocessor one of the operands holds a special register called: b. Dedicated d. None of these a. Intel 8085 c. Accumulator 11) Accumulator based microprocessor example are: b. Motorola 6809 d. None of these a. data c. A and B 12) A set of register which contain are: b. memory addresses d. all of these a. 1 c. result 13) How many types are primarily register: b. 2 d. 4 a. general purpose register c. 3 14) There are primarily two types of register: b. dedicated register d. none of these a. general purpose register c. A and B 15) Which register is a temporary storage location: b. dedicated register d. none of these a. 2 c. A and B 16) How many parts of dedicated register: File hosted by educationobserver.com/forum b. 4 d. 6 a. PC c. 5 17) Name of typical dedicated register is: b. IR d. All of these a. Program counter c. Paragraph counter c. SP 18) PC stands for: b. Points counter d. Paint counter a. Intel register 19) IR stands for: b. In counter register d. Instruction register a. Status pointer c. Index register 20) SP stands for: b. Stack pointer d. None of these c. a and b 21) The act of acquiring an instruction is referred as the____ the instruction: a. Fetching c. Both a and b b. Fetch cycle d. None of these a. 2-bit 22) How many bit of instruction on our simple computer consist of one____: b. 6-bit d. None of these a. 1 c. 12-bit 23) How many parts of single address computer instruction : b. 2 d. 4 c. 3 24) Single address computer instruction has two parts: File hosted by educationobserver.com/forum a. The operation code b. The operand d. None of these c. A and B 25) LA stands for: a. b. c. Load accumulator Least accumulator Last accumulator d. None of these a. Enable MRD 26) ED stands for: b. Enable MDR d. None of these a. Least MAR c. Both a and b 27) LM stands for: b. Load MAR d. Load MRA a. Clearing a flag c. Both a and b c. Least MRA 28) Causing a flag to became 0 is called: b. d. Case a flag None of these 29) Which are the flags of status register: a. Over flow flag b. Carry flag d. Zero flag f. Negative flag c. e. Half carry flag Interrupt flag g. All of these a. C a. S a. Z 30) The carry is operand by: 31) The sign is operand by: 32) The zero is operand by: 33) The overflow is operand by: File hosted by educationobserver.com/forum a. O a. CD c. Both a and b 34) _____ is the condition: b. IR d. None of these a. CRJA 35) ____ causes the address of the next microprocessor to be obtained from the memory: b. ROM d. HLT a. Instruction register c. Both a and b c. MAP 36) _________ Stores the instruction currently being executed: b. Current register d. None of these a. Instruction register 37) In which register instruction is decoded prepared and ultimately executed: b. Current register d. None of these a. Condition code register c. Both a and b 38) The status register is also called the____: b. c. Flag register A and B d. None of these a. Binary coded decimal c. Both a & b 39) BCD stands for: b. Binary coded decoded d. none of these a. Stack c. Accumulator 40) Which is used to store critical pieces of data during subroutines and interrupts: b. Queue d. Data register a. High memory 41) The area of memory with addresses near zero are called: b. Mid memory File hosted by educationobserver. Memory Low memory .com/forum c. d. 4 bit . None of these a. Queue pointer register d. None of these a. Return address c. Stack d. Both a & b b. None of these a. Stack pointer c. Main Address d. Stack pop d.com/forum 42) The point where control returns after a subprogram is completed is known as the : a. TOP c. Pointer c. Program counter 44) The processor uses the stack to keep track of where the items are stored on it this by using the: a. Stack push c. Queue 43) The subprogram finish the return instruction recovers the return address from the: b. LIFO FIFO d. None of these a. Program Address b. POP d. c. PUSH 47) Which is the basic stack operation: b. START d. MID 45) Which point to the ___ of the stack: b. BOTH A and B 48) SP stand for: b. Current Address a. Stack pointer register c. 1 bit 49) How many bit stored by status register: b. LILO 46) Stack words on: b.File hosted by educationobserver. None of these a. None of these a. ALL OF THESE a. None of these c. None of these a. MICROPROGRAMING d. First in last out c. 6 bit d. Both a & b 51) The structure of the stack is _______ type structure: a. NANOPROGRAMING 54) The 16 bit register is separated into groups of 4 bit where each groups is called: b.com/forum c. Barrel shifter d. Most significant digit d. Both a & b b. Index register 50) Which is the important part of a combinational logic block: b. Hexadecimal 56) The left side of any binary number is called: b. Octal digit c. Pushed d. None of these a. Decimal d. Pushing data 52) The data in the stack is called: b.File hosted by educationobserver. None of these a. 8 bit a. Pulling 53) The CU is designed by using which techniques: b. BCD c. Last in last out d. Half byte 55) A nibble can be represented in the from of: b. Medium significant digit . low significant digit c. Least significant digit c. Nibble d. HARDWIRED CONTROLS c. Backbone bus 60) The external system bus architecture is created using from ______ architecture: b. low significant digit c.com/forum 57) MSD stands for: a. Memory side bus 63) Which bus carry addresses: b. Dennis Ritchie d. Address bus d. Pascal c. Front side bus d. Control bus 64) A 16 bit address bus can generate___ addresses: b. Charles Babbage 61) The network of wires or electronic path ways on mother board back side: b. Rear side bus 62) Which Bus connects CPU & level 2 cache: b. Chip b. Least significant digit b. Medium significant digit 58) _____ a subsystem that transfer data between computer components inside a computer or between computer: a. Multiplexer d. PCB c. System bus c. Von Neumann a. None of these a. 25652 .File hosted by educationobserver. Bus a. None of these a. BUS BOTH A and B d. None of these a. Register d. c. Processor c. 32767 c. Data bus a. Processor 59) Which is called superhighway: b. Most significant digit d. READ 68) Which is not the control bus signal: b. Input 70) When memory write or I/O read are active data is from the processor: b. 16 65) The processor 80386/80486 and the Pentium processor uses _____ bits address bus: b. 12 216=65536 None of these 72) PROM stands for: . Control bus c. None of these a. None of these a. 28=256 b. Processor 71) Using 12 binary digits how many unique house addresses would be possible: c. d. None of these c. Data bus d. Input c. Address bus 67) Which bus transfer singles from the CPU to external device and others that carry singles from external device to the CPU: a. Output Processor d. Control bus c. 65536 d. none of these a. RESET 69) When memory read or I/O read are active data is to the processor : b.File hosted by educationobserver. 32 d. None of these a. WRITE d. 2 =4096 c. Address bus b. c. Output d. Data bus d. 36 66) CPU can read & write data by using : b.com/forum c. 64 a. None of these a. Secondary memory 76) Secondary memory can store____: b. Erasable Programmable read-only memory a. Flash ROM EPROM d. Compiler d. Programmable read-only memory a. None of these a.com/forum a. All of these a. Permanent RAM c. Address 73) EPROM stands for: 74) Each memory location has: b. DDR RAM a. Dynamic RAM c. c. None of these a. None of these a. Both A and B 78) Customized ROMS are called: b. Permanent RAM 80) Which type of RAM needs regular referred: b. Program store code c. Operating system 77) Secondary memory is also called____: b. Processor memory c. Auxiliary c.File hosted by educationobserver. Mask ROM c. Dynamic RAM 79) The ram which is created using bipolar transistors is called: b. Contents d. Backup store d. Static RAM SD RAM 81) Which RAM is created using MOS transistors: . Both A and B 75) Which is the type of microcomputer memory: b. d. All of these a. Static RAM d. Primary memory d. WR signal controls the input buffer c. d. Linear decoding c. SR-Latch 82) Which latch is mostly used creating memory register: b. Write enable c. None of these a. Wrote enable None of these 87) When CS _____ the chip is not selected at all hence D7 to D0 are driven to high impedance state: a. b. Static RAM d. Permanent RAM b. c. If WR is 0 then the input data reaches the latch input a. D-Latch 83) Which statement is false about WR signal: b. The bar over WR means that this is an active high signal 84) Which technique is used for main memory array design: b. SD RAM a. Fully decoding d. T-Latch a. d.File hosted by educationobserver. Chip select Control select d.com/forum a. Cable select c. 8 bit 10 bit . Write envy 86) WE stands for: b. Cable system a. Dynamic RAM c. Medium b. Both A and B 85) CS stands for: b. Low Stand by 88) The capacity of this chip is 1KB they are organized in the form of 1024 words with 8 bit word The what is the site of address bus: a. High c. JK-Latch d. The bar over WR means that this is an active low signal d. Half decoding d.File hosted by educationobserver. 16 bit a. 12 bit d. Linear decoding c. 16 KB 90) In linear decoding address bus of 16-bit wide can connect only ____ of RAM. b. None of these a. Virtual memory a. Address map is not contiguous. MAR c. None of these a. Fully decoding c. None of these 92) The problem of bus confect and sparse address distribution are eliminated by the use of ______ address technique: a. Simple architecture machine c. Confects occur if two of the select lines become active at the same time If all unused address lines are not used as chip selectors then these unused lines become don’t cares d. c. Control memory 93) A microprocessor retries instructions from : b. 12KB 91) Which statement is wrong according to linear decoding : b. Solved architecture machine None of these . Partially 89) Which storage technique dose not decoding circuit: b. Fully decoding d. None of these a. MDR d. Both a & b b. Both A and B 95) SAM stands for: b. d. Both a & b c. Cache memory d. 64KB a.com/forum c. 6KB d. Main memory 94) Which register is used to communicate with memory: b. c. File hosted by educationobserver. Virtual memory address d. d. VAM 99) Which microprocessor to read an item from memory: b. SAM d. Valid memory address c. Memory address recode d. Memory address register c. c. None of these a. 103) a. 101) a. 32-bit MOC stands for: Memory operation complex Micro operation complex Memory operation complete . Variable memory address 98) VAM stands for: b. b. b. Memory data register c. None of these a. Memory data recode d. None of these a. c. Micro data register 97) MDR stands for: b. Micro address register b. c. d.com/forum 96) MAR stands for: a. 102) a. 16-bit d. 100) a. MOC Which bus plays a crucial role in I/O: System bus Control bus Address bus Both A and B Which register is connected to the memory by way of the address bus: MAR MDR SAM None of these How many bit of MAR register: 8-bit b. 64-bit c. b. None of these c. 108) VAM The lower red curvy arrow show that CPU places the address extracted from the memory location on the_____: a. Both A and B The information is transferred from the_____ and ____ specified register: MDR b. CPU c. Data d. MDR d. None of these c. Control bus b. 104) a. None of these Which are the READ operation can in simple steps: Address b.com/forum d. Read d. Memory request b.File hosted by educationobserver. 106) a. d. All of these c. System bus Data bus DMA stands for: Direct memory access Direct memory allocation Data memory access Data memory allocation DMA stands for: Dynamic memory access b. Data memory access d. Both B and C c. 110) a. CPU d. b. d. 105) Control The upper red arrow show that CPU sends out the control signals____ and _____ indicate the data is read from the memory: a. Both A and B The information on the data bus is transferred to the ______register: MOC b. Address bus c. c. None of these c. 107) a. 111) Direct memory access CRT stands for: . 109) a. Both A and B The microcomputer system by using the ____device interface: Input b. 4 bit d. c. Write d. CPU d.File hosted by educationobserver. 118) device: a. d. c. d. b. d. b. 117) a. b. Compared ray tube None of these The CPU sends out a ____ signal to indicate that valid data is available on the data bus: Read b. 116) a. Cathode ray tube c.com/forum a. c. None of these c. 114) a. Both A and B How bit microprocessor inexpensive a separate interface is provided with I/O device: 2 bit b. Output d. Both A and B The ____ place the data from a register onto the data bus: CPU ALU Both A and B None of these The CPU removes the ___ signal to complete the memory write operation: Read Write Both A and B None of these The value memvar must be transferred to the ___: Computer b. 112) a. Command ray tube b. 115) a. 32 bit c. None of these c. 8 bit How many ways of transferring data between the microprocessor and a physical I/O 2 3 4 . 113) a. None of these c. Interrupt Transfer Both None of these The DMA controllers are special hardware embedded into the chip in modern integrate processor that ____and_____ to the system. Burst –block transfer Repeated–block transfer All of these EOC stands for: . d. d. b. a. a. b.com/forum d. b. d. 119) a. 123) IO/M Low High Medium None of these The external device is connected to a pin called the ______ pin on the processor chip. Repeated Burst –block transfer c.File hosted by educationobserver. c. c. 124) a. c. b. 1. c. 122) a. Repeated single transfer f. d. d. g. 125) a. e. c. Data transfer arbitrate access Both A and B None of these The CPU completes yields control of the bus to the DMA controller via: DMA acknowledge signal DMA integrated signal DMA implicitly signal None of these The mode of DMA are: Single transfer b. Block transfer d. b. 5 The standard I/O is also called: Isolated I/O Parallel I/O both a and b none of these 120) standard I/O uses which control pin on the micro processor: 121) A___ on this pin indicates a memory operation: a. d. ISR stands for: 4. Interrupt d. Command series c. a. Priority register b. 6. Chip series . Input service register d. Interrupt mask register b. Interrupt resolver register IRR stands for: b. 7. Priority resolver d. In-service register All of these c. None of these a. Input resolver register a. Priority request b. None of these a. End of conversion c. Interrupt service register b. a. Interrupt address INT stands for: c. End of controller b. c. PR stands for: 5.File hosted by educationobserver. None of these a. INTA stands for: b. 2. 3. Input request register d. c. Input mask register IMR stands for: Input Input mask resolver d. Emphasize of conversion Interrupt mask resolver Both a and b Interrupt access d.com/forum a. Interrupt acknowledge c. 8. Interrupt request register c. None of these a. Command select CS stands for: b. Chip select d. d. Hold acknowledgment d. d. Hold access a. Operational cost words b. c. Hold request Hold read c. a. c.File hosted by educationobserver. High access HRQ stands for: b. Initialization command write Operational conjunction words c. Hour d. 11. d. b. 14. Direct memory acknowledgment a. Operational command words Operational control words c. Register ICW stands for: Initialization command words OCW stands for: a. Direct memory application HLD stands for: High b. 12. Hold HLDA stands for: High acknowledgment b. 15. Read c.com/forum 9. Interrupt command words Interrupt command write b. 16. b. d. DMA stands for: d. None of these a. Real Hold register AEN stands for: Hold resolver Address enable Address equivalent Acknowledgment enable . a. 10. RD stands for: a. Request b. a. c. Direct memory allocation Direct memory access c. 13. None of these c. Digital to digital converters DAC stands for: b. 23. d. Digital to analogue converters c. d. 24. 8259 a. Digital to digital converters Which is the commonly used programmable interface and particular used to provide handshaking: a. None of these a. 22. Analogue to analogue converters c. 8259 b. 20. Memory write d. Which is a programmable communication interface: 8251 Which programmable timer is used to generate timing signal : . Access strobe c. 8255 c. 19. Acknowledgment equivalent ADSTB stands for: a.com/forum 17. Digital to analogue converters a. 8255 a. 8254 d.File hosted by educationobserver. Access strobe b. HRQ and HLDA means: Hold request b. 21. Hold acknowledgment d. 8254 d. a. Analogue to digital converters d. a. Address store Address strobe MEMER and MEMW means: Memory read b. 8255 c. 18. 8251 b. Analogue to digital converters d. Both a and b Both a and b ADC stands for: b. Analogue to analogue converters c. 8254 Which is designed to automatically manage the handshake operation: . 8259 a. 8251 31. 8254 d. Both a and b and i/o device: a. I/O memory mapped d. None of these a.File hosted by educationobserver. 28.com/forum b. 8251 b. Isolated I/O d. 8237 c. 8251 c. 30. Output interface d. Peripheral d. None of these c. Memory mapped I/O c. 8254 d. None of these c. Handshaking c. Which is widely used in interrupt controller with a number of microprocessor: 8255 Which are used DMA controllers with 8085/8086 microprocessor: b. 8259 a. None of these c. The standard I /O is also called: b. 25. Which provide a mechanism to establish a link between the microprocessor Input interface b. I/O ports: Both a and b In which the processor uses a protection of the memory address to represent a. I/O mapped I/O 29. None of these a. Ports b. Both a and b The processor of knowing the status of device and transferring the data with matching speeds is called: a. 27. 8257 d. b. 26. Both a and b b. PC3-PC5 a. PC3-PC5 a. 38. b. PC0-PC2 c. Mode 2 Which mode is used for simple input or output without handshaking: Mode 1 d. None of these a. Mode 2 c. 34. b.com/forum c. Mode 2 Which mode is used for double handshake in 8255: b. Mode 1 d. None of these a. PC6-PC7 Which are used for handshake lines for port A in 8255 mode 2: b. PC0-PC2 35. PC3-PC5 a. PC6-PC7 AL&99H which operation is performed here: Output d. 33. Mode 0 32. None of these a. Which mode is used for single handshake in 8255: b. c. Which are used for port A in 8255 mode 1: b. None of these a. Input c. PC3-PC7 d. Mode 0 c. Mode 0 c. 8259 a.File hosted by educationobserver. Input 39. 34H&AX which operation is performed here: . b. PC3-PC7 d. 37. Which are used for port B in 8255: PC3-PC7 PC6-PC7 d. Mode 1 d. 8255 d. PC0-PC2 36. Both a & b c. 3. 8259 c. the ADC. c.2. Issuing start of conversion pulse to ADC. 4:16 Which chip is used for DAC: AD7522 AD7523 . 45.2. iv. None of these a. 4. Output d. 40. d.1. 8251 c. ii. None of these c. Ensuring the stability of analogue input applied to Which chip is used for analogue to digital converter: 0808 44. Marking the end of the conversion processes by the.1. None of these a. 2. Conversion delay d.1 a. b.File hosted by educationobserver. c.com/forum b. 2:4 Both a & b Which multiplexer by ADC 0808/0809: b. None of these a. 0809 43. a.2. Progress b. iii.4 b. Conversion signal Arrange the flowing step of the general algorithm for ADC interfacing: i.4 b. 4. 3:8 d.3 d. 8255 d. digital output. Which chip used for AD&DA converters in 8086 processor: 8254 The time taken by the ADC from the active edge of SOC pulse till the active edge of EOC signal is called: a. 42.3. AD7521 c.3. 41. c. Conversion over b. Read digital data output of the ADC as equivalent 1. 50. 4 d. 8255 programmable timer d. Analogue to analogue Digital to digital An external feedback resistor acts to control the: Gate Profit Which used to generate accurate time delays and can be used for other timing application such as a real time clock an event counter a digital one shot a square wave generator and a complex wave form generator: a. Enable counting c. Loss b. Both 8254 counters can count in the: . 3output signal c. None of these c. 8254 programmable timer 8254 programmable timer counter has two inputs signals: Both a & b 8254 programmable timer counter has: 2output signal d. d. c. 52. Gain c. AD7524 Which converters convert binary number into their equivalent voltages: a. 8251 programmable timer b. 8 a. a. 53. 1output signal c.File hosted by educationobserver. 48. Digital to analogue c. Gate d. 2 51. 47. b.com/forum d. Analogue to digital d. CLK b. 8254 can operate how many operating modes: b. 6 8254 gate of a counter is to either: b. 49. b. 4output signal a. Disable counting d. None of these a. 46. 8259 programmable timer a. Low c. Hexadecimal 54. CISC stands for: b. 4 d. Decimal d. d.File hosted by educationobserver. 8251 b. A&B a. All of these Complex Instruction System Computer . 8 a. Which is the architecture of microprocessor: a. None of these c.com/forum a. Complex Instruction Set Car c. High d. Which is the state of gate signal for normal contains: b. How many modes in 8254: 6 55. b. Microprocessor c. 2 c. Which generate an interrupt to the microprocessor after a certain interval of time: a. CISC b. a. RAM d. None of these 2. ROM b. Binary b. fabricated on a single chip of semiconductor is called: a. None of these 3. Undefined 56. RISC d. 8254 c. A central processing unit. 8255 8259 1. Heart d. RISC stands for: Reduced Intergraded Set Computer d. Data Bus d. Complex Instruction Set Computer d. Hand c. System Bus Contains: a. Arithmetic and logical unit . Brain ALU d. All of these 9. b. Resource Instruction Set Computer 4.com/forum c. System Bus 5. All of these 6. MOS c. None of these a. Microprocessor is fabricated on single chip using: a. Which is the components of microprocessor: a. Reduced Instruction Set Computer c. Which is the components of computer: b. CPU d. Control Bus b. All of these 7. b. Register unit b. CPU c. Memory Unit b.File hosted by educationobserver. Leg 8. Address Bus c. Resource Instruction System Computer a. Microprocessor is the _____ of computer: a. d. Which system communicates with the outside word via the I/O devices interfaced to it: a. d. A and B b. All of these c. Secondary memory 13. Timing and control unit All of these 10. One c. A and B b. Two 12. Main memory d. Microcomputer d. How many group of memory unit: a. Which is the parts of memory unit: a. d. Memory oxide semiconductor None of these 14.File hosted by educationobserver. Which is an integral part of any microcomputer system and its primary purpose is to hold program and data: a. Processor memory b. Microprocessor b. Memory unit c. Three d. MOS stand for: a. Metal oxide semiconductor c.com/forum c. Register unit None of these 11. All of these c. Four b. Digital computer . 5006 d. None of these c. 8004 b. How are the successful microprocessor: a.com/forum 15. How many generation of microprocessor: a. A computer which has the microprocessor as______ is called as a microcomputer: a. The___ was very successful in the calculator market at that time: a. Intel 8085 19. The organization of I/O devices create a difference between _____: a. Digital computer b. ALU None of these 16. Microprocessor 4004 d. How many microprocessor in the market during the same period: a. Three c. None of these c. Motorola 6800 and 6809 b. Four b. RU b. 4004 20.File hosted by educationobserver. CPU c. d. All of these c. Six 18. Micro computer d. 6 . Five d. A and B 17. Which provided the current: b. Both A and B b. PMOS stands for: a. Slow-cost d. The beginning of very efficient____ microprocessor in second generation: a. None of these a. Low-Output 23. All the above c. 16-bit 25. 64-bit c. 1974-1976 b. NMOS stands for: a. 1974-1978 d. 8 d. Zilog Z80 26. Intel 8085 d. Low-cost 22. 8-bit d. 3 21. 1974-1972 24. P-channel metal-oxide-semiconductor c. 4-bit b. Which are some of popular processor: a.File hosted by educationobserver. All the above c. Second Generation_____? a. 5 c. N-channel metal-oxide-semiconductor . P-channel memory –oxide-semiconductor d.com/forum b. Motorola 6800 and 6809 b. None of these c. 64 bit c. CRT c. _____ Was more common year: b. Which technology speed faster and higher density: a. 8 bit b. 8088 A c. None of these c.File hosted by educationobserver. 1979-1980 d. Intel used HMOS technology to recreate_____: a. d. 1978-1979 30. Third generation microprocessor is dominated by____ microprocessor: a. 4 bit d. 16 bit 31. All the above a. 8085 A 32. 8084 A b. 1978-1980 c. NMOS All the above 29. HMOS b. 8086 A d. Both A and B 28. What is the period of 3 generation: a. PMOS c. 1979-1981 b.com/forum b. P-channel metal-oxide-semiconductor d. N-channel memory-oxide-semiconductor 27. HMOS stands for: . TTL d. They were fabricated using a low power version of the HMOS technology called____: a. None of these a. High performance metal oxide semiconductor c. None of these c.File hosted by educationobserver. HSMOS b. 32 bit c. 32 bit-RISC c. What is the period of fourth generation: b. 1981-1995 d. Hot environment b. 1995-2000 34. 1974-1980 c. 8 bit-RISC . Processing environment All of these 35. Both A and b b. The fourth generation of microprocessor came really as a soon boon to the_____: a. 2 bit-RISC b. Computing environment c. HCMOS d. How many bit microprocessor in the era marked beginning of fourth generation: a. 1979-1980 33.com/forum a. d. 4 bit-RISC d. Motorola introduced _____ processor: a. HSSOM 37. 8 bit d. High processor metal oxide semiconductor d. 4 bit b. 16 bit 36. d. 1946-1957 c. The growth of transistor technology in_____: a.File hosted by educationobserver. The growth of vacuum tube technology has been listed as follow: a. 1978 on words 43. 1958-1964 d. Till 1971 Till 1970 . d. 1978 on words c. 1985-1999 b. 1995-till date c. Motorola introduced 32 bit RISC processor called______: a. 1956 on words b. The growth of medium scale integration in______: a. 1965 on words d. 1946-1957 b.com/forum 38. 1974-1978 b. 1985-1999 42. MC 81100 MC 81000 39. MC 88100 c. 1981-1985 40. None of these c. b. 1958-1964 None of these 41. Period of fifth generation? a. MC 80100 b. 1979-1980 d. How are the growth of SSI technology in_____: a. 1994-1995 b.File hosted by educationobserver. d. d. Zilog c. Motorola d. The growth of SSI up to____: a. The fetch-execute cycle and pipelining c. 200 device on a chip 400 device on a chip 45. VLSI b. How can we make computers work faster? a. None of these c. The assembly None of these . Microprocessor b. Performance of a microprocessor d. The growth of LSI technology on_____: a. 1972-1978 46. Both A and B b. Which is most commonly measured in terms of MIPS previously million instruction per second: a. 300 device on a chip b. The range of this rating for which microprocessor of_____: a. Assembly line 47. Intel 48.com/forum c. d. 100 device on a chip c. Till 1972 Till 1969 44. 1971-1977 d. None of these c. Assembly line b. The assembly None of these 50. The clock period is denoted by: a. None of these c. d. Which process information at a much faster rate than it can retrieve it from memory: a. _____ memory system which is discussed later can improve matters in this respect: a. Throughput b.com/forum 49. Cache 53. ALU b. The fetch-execute cycle is to use a system know as: a. The fetch-execute cycle and pipelining c. Processor d. Flow through time c. Tp . CPU c. Who is the represents the fundamental process in the operation of the CPU: a.File hosted by educationobserver. Data memory b. Both A and B b. Microprocessor 51. The time taken for all stages of the assembly line to become active is called the: a. None of these c. Memory 52. d. Pipelining d. Cache memory d. Clock period All of these 54. Mc6800 c. Which is the microprocessor launched by Motorola corporation introduced: a.File hosted by educationobserver. None of these c. Throughput b. T1+T2+T3-------+T n c. d.com/forum b. d. 4-bit b. 32-bit c. How many bit MC6800 microprocessor: a. The ____ of can assembly line to be I/t p: a. None of these 55. Pt d. Who is the determined by the time taken by the stages the requires the most processing time: a. 8080 RPS-8 59. Throughput 58. Both A and B 56. 8-bit d. Flow through None of these 57. Pipelining d. IMP-8 b. Flow through c. Clock period b. Assembly line d. Throughput b. Ti is the time taken for the ith stage and there are n stages in the: a. 16-bit . Clock period c. Which is the world’s first microprocessor? a. How many stages has fetch execute cycle: a. 40% d. MOSFET stands for? a.com/forum 60. Intel 4004 b. Speed 65. 30% b. Metal-oxide-semiconductor fan effort transistor d. 6 c. Metal-oxide-semiconductor field effect transistor c. 4 d. Intel8008 64. 5 63. 60% c. F-8 d. None of these a. Which is the microprocessor launch by Fairchild company: a. None of these c. Motorola 68020 d. F-6 b. Memory size . 50% 61. Both A and B b. 3 b. None of these c. Both A and B 62. What is the main problem of Intel 4004 microprocessor: b.File hosted by educationobserver. Motorola has declined from having nearly __________ share of the microprocessor market to much smaller share: a. 4040 c. 16 bit 64 bit 68.File hosted by educationobserver. d. Intel 8008 microprocessor realizing in: a. Calculator are based on______ microprocessor: a. 16 bit 64 bit 69. World width All of these 66. 4004 b. 4 bit c.com/forum c. 40964 67. 8008 d. d. 32 bit b. 1999 b. 1973 1988 . 4 bit c. BCD stands for: a. The evolution of the 4 bit microprocessor ended when Intel released in: a. 1971 c. d. d. How many bit microprocessor still survives in low-end application such as microwave ovens and small control system: a. Binary coded decimal c. Based coded decimal None of these 70. d. 32 bit b. Both A and B b. Which year Intel corporation introduced an updated version of the 8080. 1988 c. 8080 c.com/forum 71. Both A and B b. 4004 None of these 72. Which Microprocessor producer continue successfully to create newer and improved version of the microprocessor: a. 48% b. MC6800 microprocessor was introduced by: a.the 8085: . Motorola has declined how many % share of the microprocessor market to a much smaller share: a. Intel 8008 microprocessor’s upgraded version is: a. Intel b. d. 1973 d. Intel 8008 microprocessor was introduced in: a. Motorola d. 1971 b. 50% c.File hosted by educationobserver. 55% 51% 76. 1999 73. d. d. Fairchild None of these 74. None of these c. Both A and B 75. Motorola corporation c. Both A and B b. 8085. 1965 b.5 Million instruction per second b. 8086 d.com/forum a. 8085 81. Which is the main feature of 8085: a. 1985 c. Motorola b. 8 bit d. d. 1. 64 bit c. All of these c.the 8085: a. How many speed of 8088. 1976 d. In 1977 which corporation introduced an updated version of the 8080. All of these c.5 Million instruction per second c.File hosted by educationobserver. 2. 1977 77. 3. Higher clock frequency 80. How many bit microprocessor developed by Intel: a. National c.8086 microprocessor: a. 4 bit b. Which is 16 Bit microprocessor: a. 8088 b. Rockwell 78.5 Million instruction per second 1. Intel d. 32 bit 79. Internal system controller d. Internal clock generator b.6 Million instruction per second . 1965 b. d.com/forum 82. Which corporation decided to use 8088 microprocessor in personal computer: a. IMP-4 IMP-8 . Z-8 b. 1978 d. 8080 d. 64-bit 8086 and 8088 b.in 1983: a. Which is the microprocessor launched by Intel: a. d. Fairchild b. IBM c. Motorola None of these 86. 16-bit 8086 and 8088 c.File hosted by educationobserver. Intel c. 8000 87. 32-bit 8086 and 8088 8-bit 8086 and 8088 85. CRT SPS 84. Who was introduce the 80286 microprocessor updated on 8086. d. 1981 83. 1999 c. Which processor provided 1 MB memory: a. PMN b. Which year Intel family ensured: a. b. None of these c. Which is the microprocessor launched by national semiconductor: a. All of these c. d.File hosted by educationobserver. GUI stands for: a. Visual graphics array d. Visual graph accept 93. d. All of these c.com/forum c. VGA stands for: a. RPS-4 b. Pentium Pro Processor contains: . Graphical use inter b. Which is the microprocessor launched by Rockwell international: a. Graph used Intel None of these 92. CAD stands for: a. Compare aided drafting None of these 91. Z-4 d. RPS-6 d. d. Which is the microprocessor launched by Zilog: a. IMP-6 IMP-7 88. Computer aided drafting c. Graphical user interface c. Z-6 90. Z-2 b. Both A and B b. Z-8 c. RPS-8 89. Visual graph area b. On Mother Board All of these 95. Which is the professional or Business version of Intel Processors: a. Pentium II b. b. On Memory 96. L2 cache memory is places at ______ a. L1 cache memory is places at ______ a. L2 Cache d. c. Socket 370 Version Slot 1 Version in Plastic Cartridge Both a and b . All of these c. d. Pentium Xeon c. d. On Processor b. Pentium III processor is released in the form of: a. 4 GB c. Pentium Pro can address _____ of memory: a. Both L1 & L2 94. Pentium Pro d. Pentium MMX 98. On Processor c.com/forum a. L1 Cache b. On Memory b. None of these c. 128 GB 512 GB 97.File hosted by educationobserver. 256 GB b. On Mother Board d. Alpha AXP is developed by: IBM Intel Which is not the main feature of DEC Alpha: 64 Bit RISC processor b. 101. d. Variable Instruction length a.File hosted by educationobserver. What is the maximum clock speed of P III processors b. 1.3 GHz c. Power PC microprocessor architecture is developed by: Apple b. None of these a. Seven stage split integer/floating point pipeline Which is not the open-source OS: b. 103.2 GHz 100. a. All of these c. b. It is not based on RISC c. DEC c. Motorola Which is not the main architectural feature of Power PC: a.com/forum d. a. Windows c. Paged Memory management architecture a. Designed to replace 32 VAX(CISC) d. 1. Motorola 102. 104. BSD Unix d. Gentoo & Red Hat Linux .0 GHz 99. IBM d. 1. Both 32 & 64 Bit b. 1. Debian c. Superscalar implementation d.1 GHz d. None of these c. 106. a. 3 6 109. DEC stands for: Digital equipment corporation 108. Digital electronic corporation d. CISC d. Which are the architectural paradigms in microprocessor: RISC b. A and B c. Complex instruction set computer c. Compared instruction set computer b. PISC CISC stands for: a. How many architectural paradigms in microprocessor: a. Reduced instruction stands computer b. Reduced Instruction set computer c. Instruction set architecture d.File hosted by educationobserver. d. 2 c.com/forum 105. 4 b. None of these 107. Camper instruct set of computer . Digital electronic computer b. Both a and b RISC stands for: a. a. All of these a. c. Reduced Instruct set compare d. ISA stands for: Instruct set area b. 110. Execution unit c. c. 2.File hosted by educationobserver. 5 Which are the part of architecture of 8086: c. 3. 6 a. None of these a. None of these a. 3 The register can be divided are: b. The bus interface unit b. BIU STAND FOR: a. b. PC’s use____ based on this architecture: ALU d. Pointer or index registers Other register . 4 d. None of these 1.purpose register c. 5. 6. Exchange unit EU STAND FOR: b. d. 4. None of these a. CPU c. None of these a.purpose register Both A and B Which are the four categories of registers: b. Bess interface unit Segment registers e. All of these a. Other register c. MU 111.com/forum d. The execution unit d. A and B b. Segment registers Eight of the register are known as: b. Pointer or index registers d. Execute unit d. General. General. d. Bus interface unit c. CH a. The four index register can be used for: a. None of these a. Counter segment a. Code segment c. DS Stand for: b. CS: Code segment 11. Divide segment a. DS: data segment d.File hosted by educationobserver. BH 13. 8. CL . d. The acculatator is 16 bit wide and is called: b. Instruction paints IP Stand for: b. Multipulation operation Instruction purpose d. AH 14. Data segment c. Subtraction operation b. Cost segment CS Stand for: b. DL a.com/forum 7. BL d. AX c. Coot segment d. Which are the segment: b. The upper 8 bit are called______: b. AL 12. AH d. AL c. All of these a. Instruction pointer c. 9. Direct segment d. ES:extra segment c. The lower 8 bit are called_______: b. Arithmetic operation c. Declare segment 10. SS: Stack segment e. All of these a. 128 bit a.com/forum c. The physical address of memory is : . The size of each segment in 8086 is: b. The status 19. The stack 18. 24 kb d. 64 bit c. Array segment c. Instruction pointer d. Which flag are used to record specific characteristics of arithmetic and logical instructions: b. Logical address 20. Industry pointer 15. Physical address d. Stack segment c. 64 kb c. Index pointer 16. Flag register 17. How many type of addressing in memory: b. None of these a. Both A and B 21. None of these a. All of these a. Stack register d. Status register c. Queue segment d. The queue a. Stand register a. IP stand for: b.File hosted by educationobserver. 16 bit c. 32 bit d. DL a. BL d. 50 kb c. 20 bit 22. How many bits the instruction pointer is wide: b. Which has great important in modular programming: b. The stand d. 16kb a. Which register containing the 8086/8088 flag: b. Deal inline package 26. Pin address 28. Logical None of these 24. d. None of these a. To provide clarity in case of the status register_______ and __________ placeholders are displayed: a. d. 40 pin c. Dual inline package d. Both 25. The pin configuration of 8086 is available in the________: b. SBA stand for: b. Segment bus address c. Project address c. 16 bit d. Segment bit address d. Electrical address None of these . 50 pin d. 20 pin a. 30 pin c. Segment base address 29. PA stand for: b. Segment byte address a. DIP stand for: b. Effect address c. Binary b.File hosted by educationobserver. 64 bit a. Digital inline package a. Physical address d. Both c. Effective address c.com/forum b. 32 bit 23. EA stand for: b. Physical c. Pointer address a. Hexadecimal d. Direct inline package 27. The _______ address of a memory is a 20 bit address for the 8086 microprocessor: b. BP stand for: a. DS stand for: b. Both 36. Segment index 33. Address lower enable 34. project counter . Non mistake interrupt d. AD stand for: b. Definition index c. Simple index a. Address deal a. Bit pointer b. Defect segment d. PC stand for: b. Bus pointer 31. Address latch enable c. Defect index d. Source index d.File hosted by educationobserver. Address delete d. Definition segment a.com/forum 30. DI stand for: b. None of these a. Byte pointer a. NMI stand for: b. Non mask able interrupt c. Address last enable a. Stand index 32. ALE stand for: b. Address date 35. Base pointer d. Delete index a. Destination index c. program counter c. Default segment c. Address data c. Address light enable d. protect counter 37. Delete segment c. SI stand for: b. Application high a. Application low a. Size organization of the cache 45. Accumulator high c. Accumulator low c. Which are the factor of cache memory: b. Extra segment a. AL stand for: b. Conditional flag 40. CX: Count All of these 42.com/forum d. All of these c. 000H to FFFH c. Control flag d. Architecture of the microprocessor c. Both a and b 41. Which are the general register: b. Appropriate low 39. BX: Base d. Address low d. 00H to FFH 44. The offset of a particular segment varies from _________: b. None of these a. ________ is the most important segment and it contains the actual assembly language instruction to be executed by the microprocessor: a. Stack segment 43. 0000H to FFFFH d. Properties of the programs being executed d.File hosted by educationobserver. e. Appropriate high 38. AX: Accumulator c. planning counter a. Data segment b. Code segment d. AH stand for: b. 00000H to FFFFFH a. DX: Data c. Which are the categorized of flag: b. Address high d. ________ is usually the first level of memory access by the microprocessor: . The cache usually gets its data from the_________ whenever the instruction or data is required by the CPU: a. Associative memory c. 2 d. 4 a. Circle size b. The amount of information which can be placed at one time in the cache memory is called_________: a.speed memory used to work directly with the microprocessor: a. Cache memory c. None of these a. Case memory d. which is the small amount of high. Direct mapping is a _________ to implement cache memory : . Main memory c. d. 3 50.com/forum a. Ordinary memory c.File hosted by educationobserver. Case memory All of these 48. All of these a. Cache c. Data memory All of these 46. Cost b. Main memory b. Line size d. Set-associative cache 51. Case Coos 47. Which memory is used to holds the address of the data stored in the cache : b. Wide line size 49. d. Cache memory b. d. 1 c. Fully associative cache c. Cheaper way 52. None of these a. Direct-mapped cache d. Which is the type of cache memory: b. How many type of cache memory: b. LRB stand for: b. Cache memory c. Cache hits c. Cache bit d.com/forum b. L211 controller c.File hosted by educationobserver. None of these a. First in first other c. L214 controller 58. EB stand for: . None of these a. FIFO stand for: b. All of these a. Line fan buffers 59. __________ is the most commonly used cache controller with a number of processor sets: b. First in first over 55. Line root buffers c. A fourth bit called the _________: b. Line full buffers c. Cache line d. First in first out d. Line read buffers c. None of these a. Cache misses 57. All of these a. Case way d. Cache hits 56. LFB stand for: b. Cache line d. Cache memory a. Microprocessor reference that are not available in the cache are called_________: b. d. Direct bit c. Microprocessor reference that are available in the cache are called______: b. Valid bit 54. L210 controller d. Cache way 53. Line ready buffers Line right buffers 60. None of these a. Line fill buffers d. tags c. e. Multi bit error 67. The index high order bits in the address known as_________: b. WB stand for: b. Effecting buffers d. label location 66. Two bit error b. None of these a. d. Effecting buffers d. Wrote allocate Word allocate 64. Effection buffers 61. d. EB stand for: b. point 65. ROM d. Effect buffers b. Single bit error d. None of these a. HDD a. In case of direct. None of these a.mapped cache lower order line address bits are used the access the ___________: a. Effection buffers 62. The parity bits are used to check that a__________: a. Effect buffers c. WA stand for: b. Wrote buffers c. Write allocate c. Write buffers c. Register c. Eviction buffers a. Way allocate 63. RAM c. Who works as cache on the variable: b. Directory b. Memory .File hosted by educationobserver. Written buffers d.com/forum a. Pointer d. Second level d. Fourth level a. TLP d. Both 69. HDD 70. Segment a. Sequentially 72.File hosted by educationobserver. Write* (Write miss rate * Write miss penalty)+write buffer stalls Memory access * Cache miss rate * Cache miss penalty d. Reads* Read miss rate * Read miss penalty 74. Memory access * Cache miss rate * Cache miss penalty 75. Temporal locality d. ROM b. Cache is usually the____________ of memory access by the microprocessor: b. TLB c. WAB a. Who work as a cache for the page table: b. Reads* Read miss rate * Read miss penalty 73. None of these a. Which formula is used to calculate the number of memory stall cycles: . The principal of working of the cache memory largely depends on which locality: b. Which formula is used to calculate the number of write stall cycles: b. Processor a. Second level is a cache on the ________: b.com/forum c. All of these a. Write* (Write miss rate * Write miss penalty)+write buffer stalls d. None of these c. First level c. RAM d. RAM d. The memory system is said to be effective if the access time of the cache is close to the effective access time of the_____: a. Third level c. Which formula is used to calculate the number of read stall cycles: b. Spatial locality 71. None of these c. LEB c. Main memory 68. c. INTRRUPT RONGH b.com/forum a. 17 KB-2MB d. PIU LIU 80. 64-bit AHB-Lite master ports d.File hosted by educationobserver. Cache can be controlled __________: b. Which causes the microprocessor to immediately terminate its present activity: b. INTRRUPT RIGHT INTRRUPT RESET . INTRRUPT REQUEST c. RESET signal c. TIU 79. INTR: it implies the__________ signal: a. 16KB-2MB c. e. d. Write* (Write miss rate * Write miss penalty)+write buffer stalls d. None of these a. Which is responsible for all the outside world communication by the microprocessor: b. BIU c. 19 KB-2MB a. Both 78. 64-bit AHB-Lite slave ports 77. d. INTERUPT signal d. None of these a. Both c. Memory access * Cache miss rate * Cache miss penalty 76. Which are the cache controller ports: b. Reads* Read miss rate * Read miss penalty b. None of these a. 18 KB-2MB c.
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