Advanced CMOS Transistors in the Nanotechnology Era for High-Performance, Low-Power Logic Applications(Invited Paper) Robert Chau*, Mark Doczy, Brian Doyle, Suman Datta, Gilbert Dewey, Jack Kavalieros, Ben Jin, Matthew Metz, Amlan Majumdar, and Marko Radosavljević Components Research, Logic Technology Development, Intel Corporation 5200 N.E. Elam Young Parkway, Mailstop: RA3-252, Hillsboro, OR 97124, USA *Email:
[email protected] Abstract Sustaining Moore’s Law requires continual transistor miniaturization. Through silicon innovations and breakthroughs, CMOS transistor scaling and Moore’s Law will continue at least through early next decade. By combining silicon innovations with other novel nanotechnologies on the same Si platform, it is expected that Moore’s Law will extend well into the next decade. This paper describes the most recent advances made in silicon CMOS transistor technology and discusses the challenges and opportunities presented by the recent emerging nanoelectronic devices such as carbon nanotube field-effect transistors (FET), Si-nanowire FETs and III-V FETs for high-performance, low-power logic applications. 1. Introduction Moore’s Law states that the number of transistors per integrated circuit doubles every 24 months, and it has been the guiding principle for the semiconductor industry for over 30 years. In order to sustain Moore’s Law, the physical gate length (Lg) of the transistor has been scaled by ~30% every generation, as shown in Fig. 1. The current 90 nm generation technology node produces CMOS devices with Lg of ~50 nm. It is 1.0 Transistor Scaling 0.5µm 0.35µm Technology 0.25µm Node 0.18µm Transistor 0.13µm Physical Gate 90nm 65nm Length 130nm 45nm 70nm 30nm 50nm projected that the Lg of the transistor will reach ~10 nm in 2011 [1]. Through silicon technology innovations and breakthroughs such as metal-gate/high-K stacks [2]-[4], uniaxially strained Si channels [5], [6], biaxially strained Si and SiGe channels [7], [8], and the non-planar fully-depleted Tri-gate CMOS transistor architecture [9], [10], CMOS transistor scaling and Moore’s Law will continue at least through early next decade. Recently, tremendous progress has been made in the research of novel nanoelectronic devices such as carbon nanotube FETs [11], [12], Si-nanowire FETs [13], [14], and III-V compound semiconductor FETs [15], [16]. These novel devices present both challenges and opportunities for future nanoelectronics applications [17]. By combining Si innovations with the novel nanotechnologies onto the same Si platform, it is expected that circuit functionality can be greatly enhanced and Moore’s Law will be extended well into the next decade. 2. Si Breakthrough: High-K/Metal-Gate Stacks for High-Performance Si CMOS For more than 15 years the physical thickness of SiO2 has been aggressively scaled for high-performance, low-power CMOS applications [2]. Recently SiO2 with physical thickness of 1.2 nm has been successfully implemented in the 90 nm logic technology node [18]. In addition, SiO2 with physical thickness of 0.8 nm [see Fig. 2(a)] has been demonstrated in the laboratory [1], [24], and has been integrated into 15 nm Lg Si research transistor, whose TEM cross-section is shown in Fig. 2(b) and drain current vs gate voltage (Id-Vg) characteristics shown in Fig. 3. Continual gate oxide scaling, however, will require high-K materials since gate oxide leakage is increasing with decreasing SiO2 thickness and since SiO2 is running out of atoms for further scaling. So far, the most common high-K dielectric materials investigated are Hf-based and Zr-based [2], [3]. 1000 Nanometer Micrometer 0.1 100 Nanotechnology 0.01 1990 30nm 20nm 15nm 1995 2000 Year 2005 10 2010 Figure 1. Scaling of transistor size (physical gate length Lg) to sustain Moore’s Law. 2 0. N-type (n+) metal gate electrode on high-K for NMOS and p-type (p+) metal gate electrode on high-K for PMOS have been engineered.6 -0.2 -0. poly-Si/high-K transistors exhibit severely degraded channel mobility due to the coupling of low-energy surface optical (SO) phonon modes arising from the polarization of the high-K dielectric to the inversion channel charge carriers [2]-[4].05. [3]. 4 [4].0 nm. 1.4 -0. as shown in Fig.6 -0.4 0.0 -1.2 0. 1E-03 1 1.5 P860 W019-BKM 25 nm SiO2 Silicon Silicon Poly-Si/SiO2 Lg = 15 nm Metal/High-K Poly-Si/High-K Figure 2.1 NDK N+ PolySi/SiO2 P+ PolySi/SiO2 SDK P-type Metal on High-K Mid-gap Metal on High-K GATE VOLTAGE (V) Metal G Metal D Metal A Metal H Metal F Metal B N-metal P-metal Metal C DRAIN CURRENT (A/µm) There are two fundamental problems in replacing poly-Si/SiO2 with poly-Si/high-K dielectric stack for high-performance CMOS applications.2 0. Metal I Metal J Figure 3. high-K dielectrics and poly-Si gates are incompatible due to Fermi level pinning at the poly-Si/high-K interface [2].5 TRANSVERSE ELECTRIC FIELD Eeff (MV/cm) 15 nm NMOS Vd = 0. “correct” threshold voltages.8 V DRAIN CURRENT (A/µm) 1E-04 1E-05 1E-06 1E-07 1E-08 0 0.8 nm and (b) 15 nm Lg transistor. First.05 V S.SURFACE PHONON LIMITED MOBILITY (cm2/Vs) (a) Poly Si PolySi (b) 1200 471 1000 800 600 400 200 T = 25 °C 0 0 0.6 0. which causes high threshold voltages in MOSFETs. The use of metal gates is effective in screening the remote phonon-channel charge interaction and improves the transistor channel mobility [4]. 1E-02 1E-03 1E-04 1E-05 1E-06 1E-07 1E-08 1E-09 -1. Second. Id-Vg characteristics of Si NMOS transistor with physical gate length Lg of 15 nm and physical SiO2 of 0. Figure 6 shows the Id-Vg characteristics of the resulting high-K/metal-gate CMOS transistors with Lg = 80 nm.8 -1. Fermi level pinning is most likely caused by defect formation at the poly-Si/high-K dielectric interface [3].5 Å |Vds| = 0. The above fundamental poly-Si/high-K problems can be solved by replacing the conventional poly-Si gate with metal gate electrodes with “correct” work functions. EOT = 1. Id-Vg characteristics of the high-K/metal-gate CMOS transistors with Lg = 80 nm.3 V Gate Electrode Materials PMOS Metal E N+poly P+poly NMOS Figure 6. The use of metal gates is effective in screening the remote phonon-channel charge interaction and improves the transistor channel mobility. Figure 5. To achieve the correct CMOS transistor threshold voltages.8 nm. 5.S. and negligible gate oxide leakage [4].0 -0. TEM cross-section of (a) SiO2 gate oxide with physical thickness of only 0.1 0. N-type Metal on High-K . as shown in Fig. [7]. Vd = 0.6 1 1.4 -1 -0.4 GATE VOLTAGE (V) Lg = 80 nm Toxe = 14. = 95 mV/decade DIBL = 100 mV/V Ioff = 180 nA/µm Transistor Flatband Voltage (V) 0. Metal electrodes with the right work functions are necessary for CMOS transistors to achieve correct threshold voltages. a n-type (n+) metal is needed for NMOS while a p-type (p+) metal is needed for PMOS.8 Figure 4. and reduced hole effective mass and interband scattering rate for PMOS [6].6 1. 7(a). [6]. The transistors have high-K/metal gate stacks. as shown in Fig.0 -1. Figure 9 shows the channel mobility of the biaxially tensile-strained NMOS transistor increases with increasing Ge% in the SiGe layer. (b) NMOS device capped with a high tensile stress silicon nitride layer to induce tensile channel strain in NMOS [5]. [6] as shown in Fig. [20]. Si Figure 10.2 1.71 mA/µm with Ioff = 45 nA/µm at Vd = 1. Uniaxial strain has been successfully implemented in production CMOS transistors in the 90 nm technology node [5]. There are two types of strain: uniaxial and biaxial strain.8 Eeff (MV/cm) Figure 7. electrical oxide thickness of 1.4 1. the use of biaxially tensile-strained Si is not as effective as the uniaxially compressive-strained Si in enhancing the . 8. In the case of uniaxial strain.0 nm.(a) (b) High Stress Film ELECTRON MOBILITY (cm2/Vs) 500 400 300 Universal Mobility Curve High-K / MG on 15% Ge substrate SiGe SiGe High-K / MG on 10% Ge substrate 200 High-K / MG on unstrained Si PMOS NMOS 100 0 0. [6].66 mA/µm with Ioff = 37 nA/µm. Biaxially tensile-strained silicon on relaxed SiGe substrate for NMOS application. a layer of biaxially tensile-strained Si is formed on top of a relaxed SiGe SiO2 Universal Mobility Curve SiO2 Universal Mobility Curve HfO2/TiN on Si HfO2/TiN on SiGe (20% Ge) HfO2/TiN on SiGe (25% Ge) 120 100 80 60 40 20 0 0. (a) A strained epitaxial SiGe film in the S/D region to induce compressive strain in the PMOS channel region [5].2 0.4 -0. 3. However.2 -1. Si Innovations: Uniaxial and Biaxial Strains to enhance Si CMOS Transistor Performance Strain improves transistor performance by enhancing the channel mobility through reduced electron effective mass and intervalley scattering rate for NMOS.3 V [4]. 140 HOLEMobility (cm (cms/Vs) Hole MOBILITY V 2 ) 2 -1 -1 equivalent oxide thickness (EOT) of 1.2 -0. substrate for both NMOS [7] and PMOS [19].8 1 1.4 0.6 -0. Channel mobility of biaxially tensile-strained NMOS transistor increases with increasing Ge% in the SiGe layer. The NMOS transistor achieves record-setting Ion = 1. This mobility gain does not reduce at high transverse channel electric fields like in the case of the biaxially tensile strain in Si. Biaxially compressive-strained SiGe layer formed on top of a Si substrate upon which surface-channel PMOS transistors can be made. In the case of biaxial strain.6 0. [6] as shown in Fig. 7(b). Si Si Relaxed SiGe Graded SixGe1-x Bulk Si substrate SiGe Relaxed SiGe (virtual substrate) Metal-gate/High-K gate stack Strained SiGe SiGe Si Strained SiGe channel Si Figure 8. PMOS mobility gain induced by the biaxially compressive strain in SiGe increases with increasing Ge% in the SiGe layer.8 -1. and negligible gate oxide leakage. while a high tensile-stress silicon nitride cap is used to induce uniaxial tensile strain in the channel of the NMOS transistor [5]. while the PMOS transistor achieves record-setting Ion = 0.4 Eeff (MV/cm) Figure 11. epi-SiGe is used to form the transistor source/drain regions to induce uniaxial compressive strain in the channel of the PMOS transistor [5]. Strained Si Figure 9.45 nm at inversion.0 HfO2/TiN on SiGe (30% Ge) High-K/MG on Si High-K/MG on SiGe (20% Ge) High-K/MG on SiGe (25% Ge) High-K/MG on SiGe (30% Ge) -0. and (c) non-planar Tri-gate transistor. the non-planar double-gate FINFET [23]. [12]. PMOS mobility because the mobility gain induced by the former reduces at high transverse channel electric fields [5]. Figure 10 shows a biaxially compressive-strained SiGe layer formed on top of a Si substrate. and the transistor Ioff increases [1]. as illustrated in Fig. Top-down SEM image of a Tri-gate transistor with multiple Si legs. Figure 15. double-gate FINFET. another way of applying biaxial strain to the PMOS and not having the problem of losing the mobility gain at high transverse channel electric fields [8]. There is. [6]. WSi) Double-Gate (WSi) Single-Gate (TSi) Figure 13. as shown in Fig. Tri-gate requirements are the most relaxed allowing for improved manufacturability. Tri-gate is the easiest to fabricate and is the most manufacturable [9]. [19]. including the planar depleted-substrate transistor (DST) [22]. Figure 15 compares the subthreshold slope of Tri-gate transistors versus conventional planar Si transistors with respect to Lg scaling. [14]. and that this mobility gain does not reduce at high transverse channel electric fields as in the case of the biaxial tensile strain in Si [8]. (a) planar single-gate DST. Si-nanowire FETs [13]. and Tri-gate devices. and the non-planar Tri-gate transistor [9]. Emerging Novel Nanoelectronic Devices for Possible Future Logic Applications Recently. Of the three device architectures shown in Fig. the Tri-gate transistor has the least stringent silicon body thickness (Tsi) and width (Wsi) requirement. [20]. its electrostatics and short channel performance become harder to control. 13. and . Silicon Body Thickness (nm) 60 50 40 30 20 10 0 0 20 40 60 80 Device Gate Length Lg (nm) 3X 1. 12. there has been rapid progress in the research of novel nanoelectronic devices such as carbon nanotube (CNT) FETs [11]. 5. (b) non-planar double-gate FINFET. [10]. Gate Figure 14. The non-planar Tri-gate shows significant improvement over the conventional planar Si MOSFETs. [10]. The data shows that non-planar Tri-gate transistors have much improved electrostatics over the conventional planar Si transistors. 4. Transistor Architecture Innovation: Non-planar Tri-gate CMOS to Improve Device Electrostatics As the Lg of the transistor scales.LG (a) LG TSi TSi LG TSi Source Drain WSi (b) WSi (c) Figure 12. Simulation results showing the silicon geometry requirements for planar single-gate DST. Hence.5X Tri-Gate (TSi. Figure 14 shows a top-down SEM image a Tri-gate transistor with multiple legs. [21]. 12. however. Figure 11 shows the PMOS mobility gain induced by the biaxial compressive strain in SiGe increases with increasing Ge% in the SiGe layer. All three devices utilize a fully-depleted body and can be used to improve short-channel performance. upon which surface-channel PMOS transistors can be made [8]. Several promising device architectures have been proposed to improve the electrostatics and Ioff of the transistor in upcoming logic generations. Subthreshold slope versus transistor physical gate length. . IEDM Tech Digest. Figure 16 compares the PMOS intrinsic gate delay (CV/I) of CNTFETs. et al. et al. et al. Low-dimensional Systems and Nanostructures.. [15] T. The data shows that the III-V FETs exhibit significant improvement in NMOS intrinsic gate delay over the Si MOSFETs.6. [19] K. p. Gate delay (intrinsic device speed CV/I) versus transistor physical gate length of novel nanoelectronic PMOS devices and Si MOSFETs [17]. vol. and planar and non-planar Si MOSFETs.. Hawaii in Oct. vol. Dig. Aug. 2435. 61. Thompson. Ghani. 22. 45. 3. 420. IEEE Electron Devices Letters. et al.. [4] R. 68. . et al. Nano Lett. p. in Proceedings Int. Radosavljević. By combining Si innovations with the other novel nanotechnologies onto the same Si platform.. IEDM Tech. Germany.. p. Chau. on Solid State Devices & Materials. 621. III-V FETs (the transistor channel is made of an III-V compound semiconductor material) [15]. p. [20] K. Dig. we have benchmarked them against state-of-the-art Si CMOS [17]. et al. [12] A. et al. 2002. Tech. 2000. Gate delay (intrinsic device speed CV/I) versus transistor physical gate length of novel nanoelectronic NMOS devices and Si MOSFETs [17]. Si-nanowire FETs. 2001. in Proceedings of Device Research Conference. p. p. vol.. Lauhon. June 2003.5 V) compared to the Si MOSFETs [17].. [6] S. Digest. et al. 517.. p. 2001. 978. 3.. Dig. p. 57. Processing.. 2003. et al. Rim. [13] L. References [1] R. vol. and at least 20x improvement in effective PMOS channel mobility over Si MOSFETs and Si nanowires. p.J.. 2002. 1995. et al. Chau. p. Chau. [14] Y. p. 1997. Chau. [9] R. Nagoya.. to be published in June 2004... [18] S. in Proceedings of 4th IEEE Conference on Nanotechnology. 2003. CMOS transistor scaling and Moore’s Law will continue at least through early next decade. 2002. Chau. Royter. [3] R. et al. these devices do offer tremendous opportunities for future nanoelectronic applications. 191. [5] T. 98. VLSI Symp. 741. p. [2] R... Cui. While the scalability of these novel devices is unknown and many fundamental challenges exist. et al.. [10] B. et al. 19.. Figure 17 compares the NMOS intrinsic gate delay of CNTFETs. 2003... to be presented in SiGe: Materials. Chau. 2004. Conf. IEDM Tech. IEDM Tech. Chau. p. [11] M. IEEE Electron Device Letters. Chau.. in Extended Abstract of International Workshop on Gate Insulator. [24] R. VLSI Symp. Datta.. p. IEDM Tech Digest. p. et al. [23] N. 133. 2003. 1 . et al. Javey. The CNTFETs show significant PMOS CV/I improvement.. 2004. Appl. IEEE Electron Device Letters.. 2003.. 149. Figure 16. p. [17] R. Lindert. Lett. Nature. 487. [7] S. Doyle. 2003.. The improvement shown by the III-V FETs is due to its 50x improvement in effective NMOS channel mobility and its much lower operating supply voltage (Vcc = 0. 2004. et al. [16] Y. To gauge the promise of these emerging devices. [22] R. vol. et al. Digest. III-V FETs. et al. in Proceedings of AVS 5th International Conference on Microelectronics and Interfaces. 2004. 2002. Thompson. 2003. IEDM Tech Digest. Dig. p. IEDM Tech. Phys. Jin. and planar and non-planar Si MOSFETs. 653.. p. 25. 751. et al. et al. 123. 2003. 83. Tech. Through Si breakthroughs and innovations. p. Japan. Rim. [21] R. Dig. Figure 17. Munich. et al. p. p. Physica E. and Devices at the ECS Meeting in Honolulu. 124. [8] B. et al. Chau. 2003. it is expected that Moore’s Law will be extended well into the next decade. [16]. Summary This paper summarizes the most recent Si breakthroughs and innovations made for advanced CMOS transistors in the nanotechnology era. vol. IEDM Tech. 731. Digest. IEDM Tech. Ashley.. et al.