Implementation of All Digital Phase Locked LoopPROJECT REPORT ON ―IMPLEMENTATION OF ALL DIGITAL PHASE LOCKED LOOPS‖ Submitted in partial fulfilment of the requirements for the award of degree of BACHELOR OF ENGINEERING IN ELECTRONICS AND COMMUNICATION ENGINEERING VISVESVARAYA TECHNOLOGICAL UNIVERSITY, BELGAUM SUBMITTED BY: Akshay G H 1BM10EC007 B S Sachin 1BM10EC016 Kashyap N 1BM10EC050 Under the Guidance of, Assistant Professor Soumya Sunkara Department of Electronics and Communication Engineering B.M.S COLLEGE OF ENGINEERING (Autonomous College Affiliated to Visvesvaraya Technological University, Belgaum) Bull Temple Road, Basavanagudi, Bangalore-560019 DEPARTMENT OF ECE, BMSCE Page 1 Implementation of All Digital Phase Locked Loop B.M.S COLLEGE OF ENGINEERING (Autonomous College under VTU) Department of Electronics and Communication Engineering CERTIFICATE This is to certify that the project entitled “Implementation of all digital Phase Locked Loop” is a bonafide work carried out by Akshay G H (USN:1BM10EC007), Sachin B S (1BM10EC016) and Kashyap N (USN:1BM10EC050) in partial fulfillment for the award of Bachelor of Engineering degree by VTU Belgaum, during the academic year 2013-2014. Smt. Sowmya Sunkara Dr.D .Seshachalam Assitant Professor,ECE, BMSCE HOD, ECE, BMSCE External Examination: Dr.K.MallikarjunaBabu Principal,BMSCE Signature with date: 1. 2. DEPARTMENT OF ECE, BMSCE Page 2 Implementation of All Digital Phase Locked Loop ABSTRACT The project presents an all-digital phase locked loop (PLL). PLL is a closed-loop control system that is used for the purpose of synchronization of phase and frequency with that of an incoming signal. The most versatile application of PLL is for clock generation and clock recovery in microprocessor and communication systems. Nowadays, due to higher integration of digital designs, digital PLL are preferred. The present work focuses on the design of ADPLL using tools from Cadence and Xilinx. Code for ADPLL is written in Verilog and compiled using NCVerilog, Simulation is done using ISim and RTL is generated using SoC Encounter. DEPARTMENT OF ECE, BMSCE Page 3 Implementation of All Digital Phase Locked Loop ACKNOWLEDGEMENT The successful completion of any task would be incomplete without mentioning the people who made it possible. We take this opportunity to express a few words of gratitude to all those who helped us in completing this project. We express our sincere gratitude to our principal, Dr Mallikarjuna K Babu for providing us with facilities to complete the project in due course of time. We would like to thank our guide Soumya Sunkara, Asst. Professor, ECE dept, BMSCE for her guidance and support. We are grateful for her help in preparation of this report. Behind every endeavour, there are people who make it happen. We sincerely thank Dr D Seshachalam, HOD, ECE dept, BMSCE for his immense support throughout the project. We would like to thank the Laboratory Supervisors and the Supporting Staff for their valuable support and encouragement during the Project Period. Finally, we thank Almighty for making us capable and giving us the dedication and determination to complete the project in time. DEPARTMENT OF ECE, BMSCE Page 4 Implementation of All Digital Phase Locked Loop LIST OF ABREVATIONS ADPLL-All digital Phase locked loop CMOS-Complementary Metal Oxide DCO- Digital Controlled Oscillator DDS-Digital Direct Synthesis DPD- Digital Phase detector PLL- Phase Locked Loop VCO- Voltage controlled oscillator PFD- Phase frequency detector LF-Loop Filter ID counter/clock- Increment Decrement counter/clock. ISE- Integrated system environment. ECL-Emitter Coupled Logic TTL-Transistor transistor Logic IC-Integrated Circuit FPGA-Field Programmable Gate Array DEPARTMENT OF ECE, BMSCE Page 5 Implementation of All Digital Phase Locked Loop LIST OF FIGURES I. II. Figure 2.1 Block Diagram of PLL Figure 2.2 Clock Distribution using PLL III. Figure 3.1 Block Diagram of All Digital PLL IV. Figure 4.1 XOR based Phase Detector V. Figure 4.2 JK FF based Phase Detector VI. VII. VIII. IX. X. XI. XII. Figure 4.3 Phase Frequency Detector Figure 4.4 Implementation of Digital Phase Detector Figure 4.5 Simulation of Digital Phase Detector Figure 5.1 UP/Down Counter Loop Filter Figure 5.2 K Counter Loop Filter Figure 5.3 Implementation of Loop Filter Figure 5.4 Simulation Results of Loop Filter XIII. Figure 5.5 Synthesized Circuit for Loop Filter XIV. Figure 6.1 Block Diagram of N Counter XV. Figure 6.2 ID out for no Carry and no Borrow XVI. Figure 6.3 ID out for Carry when Toggle FF is low XVII. Figure 6.4 ID out for Carry when Toggle FF is high XVIII. Figure 6.5 ID out for Borrow when Toggle FF is high XIX. Figure 6.6 ID out for Borrow when Toggle FF is low XX. XXI. Figure 6.7 Simulation results of DCO Figure 6.8 Synthesized circuit for DCO XXII. Figure 6.9 Synthesized circuit for Clock Divider XXIII. Figure 7.1 Modules to be synthesized in ADPLL DEPARTMENT OF ECE, BMSCE Page 6 Implementation of All Digital Phase Locked Loop TABLE OF CONTENTS 1. INTRODUCTION…………………………………………… 11 1.1. HISTORY………………………………………………... 11 1.2. MOTIVATION ………………………………………….. 12 1.3. LITERATURE SURVEY………………………………… 12 1.4 ORGANISATION OF THE REPORT……………………. 14 2. PHASE LOCKED LOOP……………………………………. 15 2.1 PRACTICAL ANALOGIES……………………………… 15 2.1.1 Automobile race analogy…………………………… 15 2.1.2 Clock analogy………………………………………. 16 2.2 .STRUCTURE OF PLL…………………………………… 17 2.2.1 Phase detector………………………………………. 17 2.2.2 Filter………………………………………………… 18 2.2.3 Oscillator……………………………………………. 19 2.2.4 Feedback path and optional divider………………… 19 2.3 DIFFERENT TYPES OF PLL: …………………………… 20 2.4 PERFORMANCE PARAMETERS………………………. 21 2.5 APLLICATIONS OF PLL………………………………… 22 DEPARTMENT OF ECE, BMSCE Page 7 Implementation of All Digital Phase Locked Loop 3. IMPLEMENTATION OF ADPLL……………………………. 26 3.1 BLOCK DIAGRAM……………………………………….. 26 3.2 ADVANTAGES OF ADPLL………………………………. 27 3.3 SOFTWARES USED……………………………………… 27 4. DIGITAL PHASE DETECTOR……………………………… 29 4.1 TYPES OF PHASE DETECTORS………………………… 29 4.1.1 Ex-or phase detector………………………………… 29 4.1.2 JK FF based detector………………………………… 30 4.1.3 Phase frequency detector……………………………. 30 4.2 IMPLEMENATION OF PHASE DETECTOR…………….. 31 4.3 SIMULATION OF PHASE DETECTOR …………………. 32 4.4 SYNTHESIS REPORT……………………………………… 32 4.5 AREA REPORT…………………………………………….. 34 4.6 POWER REPORT…………………………………………… 35 5. LOOP FILTER…………………………………………………. 36 5.1 TYPES OF LOOP FILTERS……………………………….. 36 5.1.1. Up/down counter……………………………………… 36 5.1.2 K counter………………………………………………. 37 DEPARTMENT OF ECE, BMSCE Page 8 Implementation of All Digital Phase Locked Loop 5.2 DESIGN IMPLEMENTION………………………………… 37 5.3 SIMULATION OF LOOP FILTERS ………………………. 39 5.4 SYNTHESIS REPORT……………………………………… 40 5.5 POWER REPORT……………………………………………. 42 6. DIGITAL CONTROLLED OSCILLATOR…………………… 46 6.1 TYPES OF DCO: …………………………………………….. 46 6.1.1 Divide by N counter type……………………………….. 46 6.1.2 Increment-Decrement counter type……………………… 46 6.2 DESIGN IMPLEMENTATION……………………………….. 49 6.3 SIMULATION ……………………………………………… 49 For DCO.. 6.4 SYNTHESIS REPORT………………………………………….50 6.5 AREA REPORT…………………………………………………52 6.6 POWER REPORT……………………………………………….53 6.7 TIMING REPORT……………………………………………….53 For Clock Divider.. 6.8 SYNTHESIS REPORT…………………………………………..54 6.9 AREA REPORT………………………………………………….56 6.10 POWER REPORT………………………………………………56 6.11 TIMING REPORT………………………………………………56 DEPARTMENT OF ECE, BMSCE Page 9 Implementation of All Digital Phase Locked Loop 7. RESULTS………………………………………………………… 58 8. CONCLUSION AND FUTURE WORK………………………. 59 9. REFERNCES……………………………………………………. 60 10. APPENDIX A…………………………………………………… 62 11. APPENDIX B……………………………………………………. 66 DEPARTMENT OF ECE, BMSCE Page 10 Implementation of All Digital Phase Locked Loop 1. INTRODUCTION The steady improvement of components for digital applications, more applications pertaining to processing signals are experiencing a shift from the analog to the digital domain. The digital domain compared to the analog domain provide manifold benefits like easy calibration, higher accuracy, better predictability and the probability to increase the complexity without the need for tedious adjustments or calibrations. Thus the digital domain certainly provides a better edge over analog domain which attracts more research and experimentation in this field of study. 1.1 HISTORY Automatic synchronization of electronic oscillators was described in 1923 [1]. Earliest research towards what became known as the phase-locked loop goes back to 1932, when British researchers developed an alternative to Edwin Armstrong's superheterodyne receiver, the Homodyne or direct-conversion receiver. In the homodyne or synchrodyne system, a local oscillator was tuned to the desired input frequency and multiplied with the input signal. The resulting output signal included the original modulation information. The intent was to develop an alternative receiver circuit that required fewer tuned circuits than the superheterodyne receiver. Since the local oscillator would rapidly drift in frequency, an automatic correction signal was applied to the oscillator, maintaining it in the same phase and frequency as the desired signal. The technique was described in 1932, in a paper by Henri de Bellescize, in the French journal L'Onde Électrique [2]. When Signetics introduced a line of monolithic integrated circuits such as the NE565 that were complete phase-locked loop systems on a chip in 1969, applications for the technique multiplied [3]. A few years later RCA introduced the "CD4046" CMOS Micropower PhaseLocked Loop, which became a popular integrated circuit. Since its inspection in early 1930s, where it was used in the synchronization of the horizontal and vertical scans of television, it has come to an advanced form of integrated circuit (IC). Today found uses in many other applications. The first PLL ICs were available around 1965; DEPARTMENT OF ECE, BMSCE Page 11 Implementation of All Digital Phase Locked Loop it was built using purely analog component. Recent advances in integrated circuit design techniques have led to the development of high performance PLL which has become more economical and reliable. Now a whole PLL circuit can be integrated as a part of a larger circuit on a single chip. 1.2 MOTIVATION Nature is analog and so are the circuits that drive wireless communication. But analog devices are generally harder to miniaturize and have slowly been ceding ground to digital components. Radio-frequency circuits are especially sensitive to design changes, and the properties of analog components like inductors don‘t improve as the devices get smaller. As a result, analog chips tend to lag behind their all-digital counterparts by a couple of manufacturing-process generations, which means that their features are much less fine. Over the years, Digital circuits have taken over a bit more of the analog domain. And the poster child of this trend is Phase locked loop (PLL), a core communication block which is implemented using digital circuits. The main advantage of all digital implementation is that the circuits get faster and occupy lesser area with a newer manufacturing process. Phase locked loop (PLL) is the heart of the many modern electronics as well as communication system. Recently plenty of the researches have conducted on the design of phase locked loop (PLL) circuit and still research is going on this topic. Most of the researches have conducted to realize a higher lock range PLL with lesser lock time and have tolerable phase noise. The most versatile application of the phase locked loops (PLL) is for clock generation and clock recovery in microprocessor, networking, communication systems, and frequency synthesizers. Phase locked-loops (PLLs) are commonly used to generate welltimed on-chip clocks in high-performance digital systems 1.3 LITRATURE SURVEY Ronald E Best [4] gives an introduction to PLL and deals with theory, design and applications of Mixed PLLs and Digital PLLs. The discussion includes different types of DEPARTMENT OF ECE, BMSCE Page 12 Implementation of All Digital Phase Locked Loop phase detector (linear and digital), phase frequency detectors with charge pump, Loop Filter and VCOs/NCOs. Shabaany [5], presents a 0.7-to-1.1-GHz all-digital phase locked loop with a new phase frequency detector and controlled oscillator with body-biasing is presented. Digital-tovoltage converter is controlled the bulk voltage in proposed voltage controlled oscillator, which results high frequency resolution and low power consumption. A search algorithm was used to generates the digital code for the digital-to-voltage converter. This all-digital phase locked loop uses a new structure for the phase-frequency-detector, which ensures high accuracy at phase frequency detecting and increasing lock speed. The proposed design was evaluated in PTM 65nm. The power consumption of the proposed circuit at 900 MHz frequency is 4.8mW. Kumm, M [6] presents an all-digital phase-locked loop (ADPLL), and it is implemented on a field-programmable gate array. All components like the phase detector (PD), oscillator, and loop filter are realized as digital discrete-time components fed from analog-to-digital converters. The phase detection is realized by generating first an analytic signal using a compact implementation of the Hilbert transform and then computing the instantaneous phase with the CORDIC algorithm. A phase-unwrap component was realized, which extends the linear range of the PD, so that the linear model is valid in the full frequency range. This property leads to a constant lock-in time for arbitrary frequency changes. An analytic solution for the lock-in frequency range and the stability range including processing delays is given. All relations to design an ADPLL of the presented structure are derived. A detailed example application of an ADPLL designed as an offset local oscillator was given. Das A.[7] presents a linear all-digital phase locked loop based on FPGA. In this ADPLL the phase detection system is realized by generating an analytic signal using a compact implementation of Hilbert transform and then simply computing the instantaneous phase using CORDIC algorithm in vectoring mode of operation. A 16-bit pipelined CORDIC algorithm is employed in order to obtain the phase information of the signal. All the components used in this phase detection system are realized as digital discrete time components. This design did not involve any class of multipliers thus reducing the complexity of the design. The loop filter of the ADPLL has been designed using PI controller DEPARTMENT OF ECE, BMSCE Page 13 Implementation of All Digital Phase Locked Loop which has a low pass behavior and is used to discard the higher order harmonics of the error signal. The CORDIC algorithm in its rotation mode of operation was used to compute sinusoidal values for the DDS. The ADPLL model was implemented using Xilinx ISE 12.3 and ModelSim PE Student Edition 10.1a. Our work is based on Sharma[8]. In this work, a design of an All-Digital Phase Locked Loop (ADPLL) IP core using an accumulator type DCO is proposed in order to generate desired frequency signals. Faster and efficient operation of PLLs was very much desired. Implementation of a digital PLL on a FPGA was used to control the jitter involved in the operation of PLLs to a greater extent that is troubling the current communication industry. 1.4 ORGANIZATION OF REPORT Chapter 1 presents a general introduction to the work, motivation to design an all digital phase locked loop and some works related to all digital phase locked loop. Chapter 2 presents Practical analogies, structure, performances and applications of Phase locked loop. Chapter 3 presents the block diagram, approach and softwares used in the implementation of the all-digital phase locked loop. Chapter 4, Chapter 5 and Chapter 6 presents the various different blocks, implemenatation, simulation and synthesis of Digital Phase Detector, Loop Filter and Digital controlled Oscillator respectively. Chapter 7 presents the final results of simulation and synthesis of all digital phase locked loop. Chapter 8 presents the conclusions and future work DEPARTMENT OF ECE, BMSCE Page 14 Implementation of All Digital Phase Locked Loop 2. PHASE LOCKED LOOP A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. While there are several differing types, it is easy to initially visualize as an electronic circuit consisting of a variable frequency oscillator and a phase detector. The oscillator generates a periodic signal. The phase detector compares the phase of that signal with the phase of the input periodic signal and adjusts the oscillator to keep the phases matched. Bringing the output signal back toward the input signal for comparison is called a feedback loop since the output is 'fed back' toward the input forming a loop [9]. Keeping the input and output phase in lock step also implies keeping the input and output frequencies the same. Consequently, in addition to synchronizing signals, a phase-locked loop can track an input frequency, or it can generate a frequency that is a multiple of the input frequency. These properties are used for computer clock synchronization, demodulation, and frequency synthesis, respectively. Phase-locked loops are widely employed in radio, telecommunications, computers and other electronic applications. They can be used to demodulate a signal, recover a signal from a noisy communication channel, generate a stable frequency at multiples of an input frequency (frequency synthesis), or distribute precisely timed clock pulses in digital logic circuits such as microprocessors. Since a single integrated circuit can provide a complete phase-lockedloop building block, the technique is widely used in modern electronic devices, with output frequencies from a fraction of a hertz up to many Gigahertz [9]. 2.1 PRACTICAL ANALOGIES 2.1.1 Automobile race analogy For a practical idea of what is going on, consider an auto race. There are many cars, and the driver of each of them wants to go around the track as fast as possible. Each lap corresponds to a complete cycle, and each car will complete dozens of laps per hour. The number of laps DEPARTMENT OF ECE, BMSCE Page 15 Implementation of All Digital Phase Locked Loop per hour (a speed) corresponds to an angular velocity (i.e. a frequency), but the number of laps (a distance) corresponds to a phase (and the conversion factor is the distance around the track loop). During most of the race, each car is on its own and the driver of the car is trying to beat the driver of every other car on the course, and the phase of each car varies freely. However, if there is an accident, a pace car comes out to set a safe speed. None of the race cars are permitted to pass the pace car (or the race cars in front of them), but each of the race cars wants to stay as close to the pace car as it can. While it is on the track, the pace car is a reference, and the race cars become phase-locked loops. Each driver will measure the phase difference (a distance in laps) between him and the pace car. If the driver is far away, he will increase his engine speed to close the gap. If he's too close to the pace car, he will slow down. The result is all the race cars lock on to the phase of the pace car. The cars travel around the track in a tight group that is a small fraction of a lap. 2.1.2 Clock analogy Phase can be proportional to time, so a phase difference can be a time difference. Clocks are, with varying degrees of accuracy, phase-locked (time-locked) to a master clock. Left on its own, each clock will mark time at slightly different rates. A wall clock, for example, might be fast by a few seconds per hour compared to the reference clock at NIST. Over time, that time difference would become substantial. To keep his clock in sync, each week the owner compares the time on his wall clock to a more accurate clock (a phase comparison), and he resets his clock. Left alone, the wall clock will continue to diverge from the reference clock at the same few seconds per hour rate. Some clocks have a timing adjustment (a fast-slow control). When the owner compared his wall clock's time to the reference time, he noticed that his clock was too fast. Consequently, he could turn the timing adjust a small amount to make the clock run a little slower. If things work out right, his clock will be more accurate. Over a series of weekly adjustments, the wall DEPARTMENT OF ECE, BMSCE Page 16 Implementation of All Digital Phase Locked Loop clock's notion of a second would agree with the reference time (within the wall clock's stability). An early mechanical version of a phase-locked loop was used in 1921 in the Shortt-Synchronome clock. 2.2 STRUCTURE OF PLL Phase-locked loop mechanisms may be implemented as either analog or digital circuits. Both implementations use the same basic structure. Both analog and digital PLL circuits include four basic elements [4]: Phase detector, Low-pass filter, Variable-frequency oscillator, and Feedback path which may include a frequency divider. Figure 2.1 Block Diagram of PLL 2.2.1 Phase detector: The two inputs of the phase detector are the reference input and the feedback from the VCO. The PD output controls the VCO such that the phase difference between the two inputs is held constant, making it a negative feedback system. There are several types of phase detectors in the two main categories of analog and digital. Different types of phase detectors have different performance characteristics [4]. DEPARTMENT OF ECE, BMSCE Page 17 Implementation of All Digital Phase Locked Loop For instance, the frequency mixer produces harmonics that adds complexity in applications where spectral purity of the VCO signal is important. The resulting unwanted (spurious) sidebands, also called "reference spurs" can dominate the filter requirements and reduce the capture range and lock time well below the requirements. In these applications the more complex digital phase detectors are used which do not have as severe a reference spur component on their output. Also, when in lock, the steady-state phase difference at the inputs using this type of phase detector is near 90 degrees. The actual difference is determined by the DC loop gain. A bang-bang charge pump phase detector must always have a dead band where the phases of inputs are close enough that the detector detects no phase error. For this reason, bang-bang phase detectors are associated with significant minimum peak-to-peak jitter, because of drift within the dead band.[citation needed] However these types, having outputs consisting of very narrow pulses at lock, are very useful for applications requiring very low VCO spurious outputs. The narrow pulses contain very little energy and are easy to filter out of the VCO control voltage. This results in low VCO control line ripple and therefore low FM sidebands on the VCO. In PLL applications it is frequently required to know when the loop is out of lock. The more complex digital phase-frequency detectors usually have an output that allows a reliable indication of an out of lock condition. 2.2.2 Filter The block commonly called the PLL loop filter, usually a low pass filter generally has two distinct functions [4]. The primary function is to determine loop dynamics, also called stability. This is how the loop responds to disturbances, such as changes in the reference frequency, changes of the feedback divider, or at startup. Common considerations are the range over which the loop can achieve lock (pull-in range, lock range or capture range), how fast the loop achieves lock (lock time, lock-up time or settling time) and damping behavior. Depending on the DEPARTMENT OF ECE, BMSCE Page 18 Implementation of All Digital Phase Locked Loop application, this may require one or more of the following: a simple proportion (gain or attenuation), an integral (low pass filter) and/or derivative (high pass filter). Loop parameters commonly examined for this are the loop's gain margin and phase margin. Common concepts in control theory including the PID controller are used to design this function. The second common consideration is limiting the amount of reference frequency energy (ripple) appearing at the phase detector output that is then applied to the VCO control input. This frequency modulates the VCO and produces FM sidebands commonly called "reference spurs". The low pass characteristic of this block can be used to attenuate this energy, but at times a band reject "notch" may also be useful. The design of this block can be dominated by either of these considerations, or can be a complex process juggling the interactions of the two. Typical trade-offs are: increasing the bandwidth usually degrades the stability or too much damping for better stability will reduce the speed and increase settling time. Often also the phase-noise is affected. 2.2.3 Oscillator All phase-locked loops employ an oscillator element with variable frequency capability. This can be an analog VCO either driven by analog circuitry in the case of an APLL or driven digitally through the use of a digital-to-analog converter as is the case for some DPLL designs. Pure digital oscillators such as a numerically controlled oscillator are used in ADPLLs [4]. 2.2.4 Feedback path and optional divider PLLs may include a divider between the oscillator and the feedback input to the phase detector to produce a frequency synthesizer. A programmable divider is particularly useful in radio transmitter applications, since a large number of transmit frequencies can DEPARTMENT OF ECE, BMSCE Page 19 Implementation of All Digital Phase Locked Loop be produced from a single stable, accurate, but expensive, quartz crystal–controlled reference oscillator. Some PLLs also include a divider between the reference clock and the reference input to the phase detector. If the divider in the feedback path divides by N and the reference input divider divides by M, it allows the PLL to multiply the reference frequency by N/M. It might seem simpler to just feed the PLL a lower frequency, but in some cases the reference frequency may be constrained by other issues, and then the reference divider is useful. Frequency multiplication can also be attained by locking the VCO output to the Nth harmonic of the reference signal. Instead of a simple phase detector, the design uses a harmonic mixer (sampling mixer). The harmonic mixer turns the reference signal into an impulse train that is rich in harmonics. The VCO output is coarse tuned to be close to one of those harmonics. Consequently, the desired harmonic mixer output (representing the difference between the N harmonic and the VCO output) falls within the loop filter passband. It should also be noted that the feedback is not limited to a frequency divider. This element can be other elements such as a frequency multiplier, or a mixer. The multiplier will make the VCO output a sub-multiple (rather than a multiple) of the reference frequency. A mixer can translate the VCO frequency by a fixed offset. It may also be a combination of these. An example being a divider following a mixer; this allows the divider to operate at a much lower frequency than the VCO without a loss in loop gain. 2.3 DIFFERENT TYPES OF PLL: Analog or linear PLL (APLL) Phase detector is an analog multiplier. Loop filter is active or passive. It uses a Voltagecontrolled oscillator (VCO). Digital PLL (DPLL) DEPARTMENT OF ECE, BMSCE Page 20 Implementation of All Digital Phase Locked Loop An analog PLL with a digital phase detector such as XOR, edge-trigger JK, phase frequency detector. It may have digital divider in the loop. All digital PLL (ADPLL) Phase detector, filter and oscillator are digital. It uses a numerically controlled oscillator (NCO). Software PLL (SPLL) Functional blocks are implemented by software rather than specialized hardware. Neuronal PLL (NPLL) Phase detector, filter and oscillator are neurons or small neuronal pools. Uses a rate controlled oscillator (RCO). Used for tracking and decoding low frequency modulations ( < 1 kHz), such as those occurring during mammalian-like active sensing. 2.4 PERFORMANCE PARAMETERS Type and order Lock range: The frequency range the PLL is able to stay locked. Mainly defined by the VCO range. Capture range: The frequency range the PLL is able to lock-in, starting from unlocked condition. This range is usually smaller than the lock range and will depend, for example, on phase detector. Loop bandwidth: Defining the speed of the control loop. Transient response: Like overshoot and settling time to a certain accuracy (like 50ppm). Steady-state errors: Like remaining phase or timing error Output spectrum purity: Like sidebands generated from a certain VCO tuning voltage ripple. Phase-noise: Defined by noise energy in a certain frequency band (like 10 kHz offset from carrier). Highly dependent on VCO phase-noise, PLL bandwidth, etc. DEPARTMENT OF ECE, BMSCE Page 21 Implementation of All Digital Phase Locked Loop General parameters: Such as power consumption, supply voltage range, output amplitude, etc. 2.5 APLLICATIONS OF PLL Phase-locked loops are widely used for synchronization purposes; in space communications for coherent demodulation and threshold extension, bit synchronization, and symbol synchronization. Phase-locked loops can also be used to demodulate frequency-modulated signals. In radio transmitters, a PLL is used to synthesize new frequencies which are a multiple of a reference frequency, with the same stability as the reference frequency. Some of the other applications are: Clock recovery Some data streams, especially high-speed serial data streams such as the raw stream of data from the magnetic head of a disk drive, are sent without an accompanying clock. The receiver generates a clock from an approximate frequency reference, and then phasealigns to the transitions in the data stream with a PLL. This process is referred to as clock recovery. In order for this scheme to work, the data stream must have a transition frequently enough to correct any drift in the PLL's oscillator. Typically, some sort of redundant encoding is used, such as 8b/10b encoding [4]. De-Skewing If a clock is sent in parallel with data, that clock can be used to sample the data. Because the clock must be received and amplified before it can drive the flip-flops which sample the data, there will be a finite, and process-, temperature-, and voltage-dependent delay between the detected clock edge and the received data window. This delay limits the frequency at which data can be sent. One way of eliminating this delay is to include a deskew PLL on the receive side, so that the clock at each data flip-flop is phase-matched to the received clock. In that type of application, a special form of a PLL called a delaylocked loop (DLL) is frequently used [10]. DEPARTMENT OF ECE, BMSCE Page 22 Implementation of All Digital Phase Locked Loop Clock generation Many electronic systems include processors of various sorts that operate at hundreds of megahertz. Typically, the clocks supplied to these processors come from clock generator PLLs, which multiply a lower-frequency reference clock usually 50 or 100 MHz up to the operating frequency of the processor. The multiplication factor can be quite large in cases where the operating frequency is multiple Gigahertz and the reference crystal is just tens or hundreds of megahertz [9]. Spread spectrum All electronic systems emit some unwanted radio frequency energy. Various regulatory agencies such as the FCC in the United States, put limits on the emitted energy and any interference caused by it. The emitted noise generally appears at sharp spectral peaks (usually at the operating frequency of the device, and a few harmonics). A system designer can use a spread-spectrum PLL to reduce interference with high-Q receivers by spreading the energy over a larger portion of the spectrum. For example, by changing the operating frequency up and down by a small amount (about 1%), a device running at hundreds of megahertz can spread its interference evenly over a few megahertz of spectrum, which drastically reduces the amount of noise seen on broadcast FM radio channels, which have a bandwidth of several tens of kilohertz [11]. Clock distribution DEPARTMENT OF ECE, BMSCE Page 23 Implementation of All Digital Phase Locked Loop Figure 2.2 Clock Distribution using PLL Typically, the reference clock enters the chip and drives a phase locked loop (PLL), which then drives the system's clock distribution. The clock distribution is usually balanced so that the clock arrives at every endpoint simultaneously. One of those endpoints is the PLL's feedback input. The function of the PLL is to compare the distributed clock to the incoming reference clock, and vary the phase and frequency of its output until the reference and feedback clocks are phase and frequency matched. PLLs are ubiquitous—they tune clocks in systems several feet across, as well as clocks in small portions of individual chips. Sometimes the reference clock may not actually be a pure clock at all, but rather a data stream with enough transitions that the PLL is able to recover a regular clock from that stream. Sometimes the reference clock is the same frequency as the clock driven through the clock distribution, other times the distributed clock may be some rational multiple of the reference. Jitter and noise reduction One desirable property of all PLLs is that the reference and feedback clock edges be brought into very close alignment. The average difference in time between the phases of the two signals when the PLL has achieved lock is called the static phase offset also called the steady-state phase error. The variance between these phases is called tracking jitter. Ideally, the static phase offset should be zero, and the tracking jitter should be as low as possible [9]. Phase noise is another type of jitter observed in PLLs, and is caused by the oscillator itself and by elements used in the oscillator's frequency control circuit. Some technologies are known to perform better than others in this regard. The best digital PLLs are constructed with emitter-coupled logic (ECL) elements, at the expense of high power consumption. To keep phase noise low in PLL circuits, it is best to avoid saturating logic families such as transistor-transistor logic (TTL) or CMOS. DEPARTMENT OF ECE, BMSCE Page 24 Implementation of All Digital Phase Locked Loop Another desirable property of all PLLs is that the phase and frequency of the generated clock be unaffected by rapid changes in the voltages of the power and ground supply lines, as well as the voltage of the substrate on which the PLL circuits are fabricated. This is called substrate and supply noise rejection. The higher the noise rejection, the better. To further improve the phase noise of the output, an injection locked oscillator can be employed following the VCO in the PLL [11]. Frequency synthesis In digital wireless communication systems (GSM, CDMA etc.), PLLs are used to provide the local oscillator up-conversion during transmission and down-conversion during reception. In most cellular handsets this function has been largely integrated into a single integrated circuit to reduce the cost and size of the handset. However, due to the high performance required of base station terminals, the transmission and reception circuits are built with discrete components to achieve the levels of performance required. GSM local oscillator modules are typically built with a frequency synthesizer integrated circuit and discrete resonator VCOs [12]. DEPARTMENT OF ECE, BMSCE Page 25 Implementation of All Digital Phase Locked Loop 3. IMPLEMENTATION OF ADPLL The all-digital PLL offers various advantages compared to other types due to the use of only digital signals. The ADPLL has three components namely [13] Digital Phase Detector Loop Filter Digital controlled Oscillator The task of a PLL is to lock the phase and the frequency of U1(t) to those of U2(t). The phase detector is used to detect the difference between U1(t) and U2(t). The loop filter is used to filter out out-of-band noise. Finally, the voltage-controlled oscillator (VCO) receives the output of the loop filter and adjusts the phase/frequency of the output signal U2(t) accordingly. To realize an ADPLL, all function blocks of the system must be implemented by purely digital circuits. The signal are digital (binary) and may be a single digital signal or a combination of parallel digital signals. There are some advantages: No off-chip components and Insensitive to technology [13]. 3.1 BLOCK DIAGRAM The top level diagram of our ADPLL is as shown below: Ref clock U1(t) Digital Loop Filter Digital phase Detector Digital Controlled Oscillator DCO clock Frequency Divider O/P DCO clock U2(t) Figure 3.1 Block Diagram of All Digital PLL DEPARTMENT OF ECE, BMSCE Page 26 Implementation of All Digital Phase Locked Loop In the above figure U1(t) is the reference signal whereas U2(t) is the required signal output signals. In the succeeding sections the above three blocks are explained in detail. Also the signals involve clock. All the events take place at the positive edge of the clock. 3.2 ADVANTAGES OF ADPLL: ADPLL is chosen over analog PLLs because of the below advantages [12]. 1. Easy to design because of the only three parameters 2. Center frequency can be determined merely by M and N 3. Unlike analog PLL, under-damping transient response is less probable in ADPLL (the frequency domain model shows that the ADPLL is a first order digital filter, which is free from second order damping) 4. Hold range can be simply determined by M, K, and N, while analog PLL can only improve the performance by new technology or fabrication 5. Unlike analog PLL, ADPLL has almost the same hold range and lock range. 3.3 SOFTWARES USED Xilinx ISE 13.2: is used for simulating all digital phase locked loop. Xilinx Integrated Software Environment (ISE) is a software tool produced by Xilinx for synthesis and analysis of HDL designs, enabling the developer to synthesize their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer. Xilinx supports dataflow, behavioral, structural, Gate level and also mixed language descriptionsi.e. VHDL and Verilog in single program. DEPARTMENT OF ECE, BMSCE Page 27 Implementation of All Digital Phase Locked Loop ISim: For the purpose of Simulation we used ISim 13.2. The Xilinx® ISE Simulator (ISim) is a Hardware Description Language (HDL) simulator that enables to perform functional (behavioral) and timing simulations for VHDL, Verilog and mixed-language designs. This provides attractive options to graphically force the clocks and hence verify the truth tables of the logic designs. NCVerilog simulator: The Cadence® NC-Verilog simulator is a Verilog digital logic simulator that combines the high-performance of native compiled code simulation with the accuracy, flexibility, and debugging capabilities of event-driven simulation. The NCVerilog simulator is based on Cadence‘s Interleaved Native Compiled Code Architecture (INCA). The Interleaved Native Compiled Code Architecture (INCA) is an extension of the NativeCompiled Code (NCC) approach to software execution. The NCC approach to simulation addresses the performance challenge of a single-simulation strategy. However, many new factors are rapidly making single-language, event-driven,HDL-based simulation ineffective Cadence SOC encounter: The SoC Encounter System provides fast and flexible feasibility analysis, giving engineers an early, accurate view of whether the most complex designs will meet their targets and be physically realizable. It offers the latest low-power design and yield capabilities and provides a predictable path to design closure. Code for ADPLL is written in Verilog and compiled using NCVerilog, Simulation is done using ISim and RTL is generated using SoC Encounter. DEPARTMENT OF ECE, BMSCE Page 28 Implementation of All Digital Phase Locked Loop 4. DIGITAL PHASE DETECTOR Phase Detector (PD) is used to detect the phase difference between the reference signal and the required signal. The PD was the only component that was digitized long back. It‘s used in the Digital PLL [4]. Similar idea can be extended to the ADPLL. 4.1 TYPES OF PHASE DETECTORS The three common implementations of the digital PD are: o Exclusive-or (EXOR) Gate o Edge triggered JK Flip-Flop o Digital Phase-Frequency Detector 4.1.1 Ex-or phase detector The EXOR mechanism offers a simple yet reliable method of phase detection. One main drawback of this mechanism is its lack of sensitivity to edges. It‘s a flat triggered mechanism. To eliminate this drawback the edge triggered mechanism comes into picture. The edge triggered JK mechanism is the most popular and effective one. It is sensitive to the edges and hence instantaneous corrective action can be achieved. The incoming reference signal acts as one input and the output of the Digital Controlled Oscillator (feedback of the PLL) acts as the other input. This edge triggering mechanism has been used in the design of the current Jitter bounded ADPLL [14]. Figure 4.1 XOR based Phase Detector DEPARTMENT OF ECE, BMSCE Page 29 Implementation of All Digital Phase Locked Loop 4.1.2 JK FF based detector Figure 4.2 JK FF based Phase Detector Using the above shown edge triggering mechanism a logical extension can be done to the simple JK flip-flop such that it is sensitive to the edges and the clock can be eliminated. As shown in the figure 3, the reference signal u1 and the output (or scaled-down output) signal u2 of the DCO are binary-valued signals. They are used to set or reset an edge triggered JK flip-flop. The time period in which the Q output of the flip-flop is a logic 1 is proportional to the phase error ƒáe. The Q signal is used to gate the high-frequency clock signal into the counter. The counter is reset on every positive edge of the u1 signal. The content N of the counter is also proportional to the phase error ƒáe, where N is the n-bit output of this type of phase detector. The frequency of the high-frequency clock is usually Mf0, where f0 is the frequency of the reference signal and M is a large positive integer [14]. 4.1.3 Phase frequency detector The third type of phase detector is the combination of a tri-state phase-frequency detector and a charge pump and it makes a very effective combination for acting as a digital phase detector. But due to the analog components involved in the charge pump, it is not being realized in the current design process. But many DPLL ICs make use of this phase detector. DEPARTMENT OF ECE, BMSCE Page 30 Implementation of All Digital Phase Locked Loop Figure 4.3 Phase Frequency Detector 4.2 IMPLEMENATION OF PHASE DETECTOR XOR based phase detector was implemented due to simplicity of design. Along with the XOR gate we have also included a 15 bit counter to measure the phase error. The XOR gate output Q acts as the clear signal for the counter and the reference signal U1 acts as a reset (negative logic) for the counter. The signal U2 is actually obtained as a feedback signal from the Digital controlled oscillator. The counter counts on the positive edge of the clock. Figure 4.4 Implementation of Digital Phase Detector DEPARTMENT OF ECE, BMSCE Page 31 Implementation of All Digital Phase Locked Loop 4.3 SIMULATION OF PHASE DETECTOR Figure 4.5 Simulation of Digital Phase Detector In the above image we can see that whenever the Q output is one and also the reference signal is high the counter starts the count. After that when Q goes to zero the count is held and for U1 the count value is reset. The value of N is the phase difference. 4.4 SYNTHESIS REPORT rc:/> synthesize -to_mapped -effort medium Mapping PhaseDetector to gates. Global mapping target info ========================== Cost Group 'default' target slack: Unconstrained Global mapping status ===================== Worst Total Neg Operation Area Slack Worst Path -----------------------------------------------------------------------------global_map 6 0 N/A Global incremental target info DEPARTMENT OF ECE, BMSCE Page 32 Implementation of All Digital Phase Locked Loop ============================== Cost Group 'default' target slack: Unconstrained Global incremental optimization status ====================================== Worst Total Neg Operation Area Slack Worst Path -----------------------------------------------------------------------------global_inc 6 0 N/A Incremental optimization status =============================== Worst - - DRC Totals - Total Neg Max Max Operation Area Slack Trans Cap -----------------------------------------------------------------------------init_delay 6 0 0 0 init_drc 6 0 0 0 init_area 6 0 0 0 Incremental optimization status =============================== Worst - - DRC Totals - Total Neg Max Max Operation Area Slack Trans Cap -----------------------------------------------------------------------------init_delay 6 0 0 0 init_drc 6 0 0 0 init_area 6 0 0 0 Done mapping PhaseDetector Synthesis succeeded. DEPARTMENT OF ECE, BMSCE Page 33 Implementation of All Digital Phase Locked Loop Figure 4.6 Synthesized Digital Phase Detector 4.5 AREA REPORT rc:/> report area ============================================================ Generated by: Encounter(R) RTL Compiler v08.10-s121_1 Generated on: Dec 17 2013 04:51:37 PM Module: PhaseDetector Technology library: slow_highvt 1.0 Operating conditions: slow (balanced_tree) Wireload mode: enclosed Area mode: timing library ============================================================ Instance Cells Cell Area Net Area Wireload --------------------------------------------------------PhaseDetector 1 6 0 <none> (D) (D) = wireload is default in technology library DEPARTMENT OF ECE, BMSCE Page 34 Implementation of All Digital Phase Locked Loop 4.6 POWER REPORT rc:/> report power ============================================================ Generated by: Encounter(R) RTL Compiler v08.10-s121_1 Generated on: Dec 17 2013 04:52:31 PM Module: PhaseDetector Technology library: slow_highvt 1.0 Operating conditions: slow (balanced_tree) Wireload mode: enclosed Area mode: timing library ============================================================ Leakage Dynamic Total Instance Cells Power(nW) Power(nW) Power(nW) -------------------------------------------------PhaseDetector 1 5.188 101.990 107.178 rc:/> report timing Warning : Possible timing problems have been detected in this design. [TIM-11] : The design is 'PhaseDetector'. ============================================================ Generated by: Encounter(R) RTL Compiler v08.10-s121_1 Generated on: Dec 17 2013 04:52:57 PM Module: PhaseDetector Technology library: slow_highvt 1.0 Operating conditions: slow (balanced_tree) Wireload mode: enclosed Area mode: timing library ============================================================ Pin Type Fanout Load Slew Delay Arrival (fF) (ps) (ps) (ps) --------------------------------------------------u1 in port 1 1.2 0 +0 0 R g30/B +0 0 g30/Y XOR2XLTH 1 0.0 60 +100 100 F dnup out port +0 100 F --------------------------------------------------Timing slack : UNCONSTRAINED Start-point : u1 End-point : dnup DEPARTMENT OF ECE, BMSCE Page 35 Implementation of All Digital Phase Locked Loop 5. LOOP FILTER The digital loop filter is not always present in phase locked loops. But in higher order loops where applications such as servo control, telecommunications are involved the digital loop filter is necessary. Different Phase Detectors generate different types of signals. It removes high frequency parts of phase error signal [4]. 5.1 TYPES OF LOOP FILTERS: Usually two types of loop filters are used namely, 1. Up/Down counter loop filter 2. K counter loop filter 5.1.1 Up/down counter UP/Down counter loop filter is simple to implement. It is always operate in conjunction with EXOR or JK FF phase detector. For getting clock and direction signal a pulse forming circuit is used. Counter is incremented on each UP pulses and it is decremented on each down signals .So counter adds both pulses. The diagram of this counter is as shown below. UP Clock Pulse Forming Circuit From PD UP/DOWN COUNTER N DN Figure 5.1 UP/Down Counter Loop Filter . DEPARTMENT OF ECE, BMSCE Page 36 Implementation of All Digital Phase Locked Loop 5.1.2 K counter In this type of loop filter a K counter is used. It always works with phase detector. As this is a binary counter K=2n where n is any integer. Output of phase detector is fed into the K counter. K counter clock is M times multiple of the center frequency. M typically be 8, 16, 32. It contains two independent counters. First counter is up counter and second is down counter. But in practice both counts upward. The modulus of counter is K. The range of the both the counters are from 0 to K-1. dn/up signal controls the operation of K counter. If this signal is high, then down counter is active otherwise, if it is low, then up counter is active. If the value of down counter is greater than K/2 then the borrow is set. If the value of up counter is greater than K/2 then the carry is set. DCO operation is controlled by these two signals. The duty cycle of the signal dn/up(Q) is asymmetric due to the phase error present in the loop [8]. Figure 5.2 K Counter Loop Filter 5.2 DESIGN IMPLEMENTION In our project we have implemented the loop filter using the K counter type. In this counter the dn/up signal is nothing but the Q signal generated from the digital frequency detector. The circuit diagram of the counter is shown in fig (vii). Here as we can see that the UP/DN signal which is provided to ―Counter enable (CE)‖ is ‗Q‘ signal from the previous block. The Kclk is the high frequency clock fed to both the counters. In our project to maintain synchronization we have fed both the digital frequency detector and the up and down counters with the same clock [14]. DEPARTMENT OF ECE, BMSCE Page 37 Implementation of All Digital Phase Locked Loop So Kclk here and clk previously are same. Both UP and DOWN counters in our case are 4 bit counters. In the above circuit we can also see that carry and borrow are taken from Q3 or the MSBs of the UP and DOWN counter respectively. This is because the value of a number in the range 0 to K-1 becomes greater than K/2 only if the MSB goes high. Hence we have taken the Q3 bits as carry and borrow respectively. The K-clk frequency is decided by the equation, Fk-clk=2*N*Fref. (2) We have taken the value of N to be 8 to make Fk-clk to be same as Fref as explained earlier. So M=2*N=16. So all the events are controlled by a single clock of frequency 1.6 MHz. The waveform for the Loop filter are as shown in fig(viii). Here we also have included the signals from the digital frequency oscillator for the sake of clarity. The clk in the waveform is nothing but K-clk only and it is forced to frequency of 1.6 MHz. The U1 and U2 signals like earlier are each forced to 10 KHz with the former leading the latter by 720. The carry and borrow signals are obtained from the most significant bits of the up and down counters as shown. DEPARTMENT OF ECE, BMSCE Page 38 Implementation of All Digital Phase Locked Loop UP Counter DOWN Counter Figure 5.3 Implementation of Loop Filter 5.3 SIMULATION OF LOOP FILTERS The value of K is set to 16. Hence, the down counter counts from 0 to 15 whenever the signal Q is high. Similarly when Q is zero the up counter counts from 0 to 15. As discussed earlier whenever the count is in the range [8,15] the MSD is 1 and hence depending on the whether we are considering up counter or down counter, the carry or borrow signals are made high respectively. DEPARTMENT OF ECE, BMSCE Page 39 Implementation of All Digital Phase Locked Loop Figure 5.4 Simulation Results of Loop Filter 5.4 SYNTHESIS REPORT rc:/> synthesize -to_mapped -effort medium Trying carrysave optimization (configuration 1 of 1) on module 'LoopFilter'... Info : Done carrysave optimization. [RTLOPT-20] : There are 2 CSA groups in module 'LoopFilter'... Accepted (2/2). Mapping LoopFilter to gates. Global mapping target info ========================== Cost Group 'default' target slack: Unconstrained Global mapping status ===================== Worst Total Neg Operation Area Slack Worst Path -----------------------------------------------------------------------------global_map 2050 0 N/A Global incremental target info ============================== Cost Group 'default' target slack: Unconstrained DEPARTMENT OF ECE, BMSCE Page 40 Implementation of All Digital Phase Locked Loop Global incremental optimization status ====================================== Worst Total Neg Operation Area Slack Worst Path -----------------------------------------------------------------------------global_inc 2019 0 N/A Incremental optimization status =============================== Worst - - DRC Totals - Total Neg Max Max Operation Area Slack Trans Cap -----------------------------------------------------------------------------init_delay 2019 0 0 0 init_drc 2019 0 0 0 init_area 2019 0 0 0 glob_area 2016 0 0 0 Incremental optimization status =============================== Worst - - DRC Totals - Total Neg Max Max Operation Area Slack Trans Cap -----------------------------------------------------------------------------init_delay 2016 0 0 0 init_drc 2016 0 0 0 init_area 2016 0 0 0 Done mapping LoopFilter Synthesis succeeded. DEPARTMENT OF ECE, BMSCE Page 41 Implementation of All Digital Phase Locked Loop Figure 5.5 Synthesized Circuit for Loop Filter 5.5 POWER REPORT rc:/> report power ============================================================ Generated by: Encounter(R) RTL Compiler v08.10-s121_1 Generated on: Dec 17 2013 05:32:38 PM Module: LoopFilter Technology library: slow_highvt 1.0 Operating conditions: slow (balanced_tree) Wireload mode: enclosed Area mode: timing library ============================================================ Leakage Dynamic Total Instance Cells Power(nW) Power(nW) Power(nW) -----------------------------------------------LoopFilter 327 1713.319 13446.358 15159.677 rem_51_20 109 645.500 3818.634 4464.134 DEPARTMENT OF ECE, BMSCE Page 42 Implementation of All Digital Phase Locked Loop rem_47_19 109 639.339 328.943 968.282 rc:/> report timing Warning : Possible timing problems have been detected in this design. [TIM-11] : The design is 'LoopFilter'. : Use 'report timing -lint' for more information. ============================================================ Generated by: Encounter(R) RTL Compiler v08.10-s121_1 Generated on: Dec 17 2013 05:33:14 PM Module: LoopFilter Technology library: slow_highvt 1.0 Operating conditions: slow (balanced_tree) Wireload mode: enclosed Area mode: timing library ============================================================ Pin Type Fanout Load Slew Delay Arrival (fF) (ps) (ps) (ps) ------------------------------------------------------------dn_reg[1]/CK 0 0 R dn_reg[1]/Q SDFFQX1TH 5 7.2 114 +269 269 R g2038/B +0 269 g2038/Y NAND2XLTH 2 2.6 114 +108 377 F g2014/A +0 377 g2014/Y OR2XLTH 2 2.6 88 +205 582 F g2002/AN +0 582 g2002/Y NAND2BXLTH 2 2.6 121 +180 762 F g1991/AN +0 762 g1991/Y NAND2BXLTH 2 2.6 121 +191 953 F g1984/AN +0 953 g1984/Y NAND2BXLTH 2 2.6 121 +191 1144 F g1979/AN +0 1144 g1979/Y NAND2BXLTH 1 1.6 94 +174 1317 F g1972/A +0 1317 g1972/Y XNOR2XLTH 1 1.2 194 +99 1416 R rem_47_19/A[7] g1862/B0 +0 1416 g1862/Y OAI31XLTH 3 3.6 169 +164 1581 F g1861/B0 +0 1581 g1861/Y OAI21XLTH 1 1.2 112 +79 1660 R g1859/A +0 1660 g1859/Y NAND3XLTH 2 3.7 228 +173 1833 F g1857/A0 +0 1833 g1857/Y OAI21XLTH 4 5.0 256 +221 2054 R g1855/A0 +0 2054 g1855/Y OAI22XLTH 2 2.1 137 +151 2205 F g1854/B0 +0 2205 g1854/Y AO21XLTH 1 1.2 77 +226 2431 F g1852/B0 +0 2431 g1852/Y OAI211XLTH 2 3.1 216 +80 2512 R g1851/A +0 2512 DEPARTMENT OF ECE, BMSCE Page 43 Implementation of All Digital Phase Locked Loop g1851/Y g1850/B g1850/Y g1847/B1 g1847/Y g1846/CI g1846/CO g1845/CI g1845/CO g1844/B0 g1844/Y g1843/B0 g1843/Y g1838/A0 g1838/Y g1891/B0 g1891/Y g1836/CI g1836/CO g1835/CI g1835/CO g1834/CI g1834/CO g1833/B0 g1833/Y g1832/B0 g1832/Y g1831/A g1831/Y g1830/B g1830/Y g1825/B1 g1825/Y g1824/CI g1824/CO g1823/CI g1823/CO g1822/CI g1822/CO g1821/CI g1821/CO g1820/B0 g1820/Y g1819/B0 g1819/Y g1812/A0 g1812/Y g1894/B0 g1894/Y g1810/CI g1810/CO g1809/CI CLKINVX2TH 4 4.5 89 NAND2XLTH 1 1.1 51 AOI22XLTH 2 3.7 200 ADDFX1TH 1 2.5 88 ADDFX1TH 2 2.4 87 OAI21XLTH 1 1.2 140 OAI2B11XLTH 5 7.6 413 OAI21XLTH 1 1.6 170 OAI2B1X1TH 2 3.8 138 ADDFX1TH 1 2.5 88 ADDFX1TH 1 2.5 88 ADDFX1TH 2 2.1 84 AO21XLTH 1 1.2 77 OAI211XLTH 5 6.8 354 INVX2TH 5 5.8 104 NAND2XLTH 1 1.1 54 AOI22XLTH 2 3.7 200 ADDFX1TH 1 2.5 88 ADDFX1TH 1 2.5 88 ADDFX1TH 1 2.5 88 ADDFX1TH 2 2.4 87 OAI21XLTH 1 1.2 141 OAI2B11XLTH 7 10.0 513 OAI21XLTH 1 1.6 191 OAI2B1X1TH 2 3.8 151 ADDFX1TH 1 2.5 88 DEPARTMENT OF ECE, BMSCE +106 +0 +59 +0 +149 +0 +278 +0 +242 +0 +58 +0 +294 +0 +191 +0 +133 +0 +258 +0 +243 +0 +238 +0 +212 +0 +118 +0 +113 +0 +64 +0 +150 +0 +278 +0 +243 +0 +243 +0 +242 +0 +58 +0 +352 +0 +214 +0 +139 +0 +262 +0 2617 2617 2677 2677 2826 2826 3104 3104 3346 3346 3404 3404 3697 3697 3888 3888 4021 4021 4280 4280 4523 4523 4761 4761 4973 4973 5090 5090 5204 5204 5268 5268 5418 5418 5696 5696 5938 5938 6181 6181 6423 6423 6481 6481 6833 6833 7047 7047 7186 7186 7448 7448 F R F F F R F R F F F F F R F R F F F F F R F R F F Page 44 Implementation of All Digital Phase Locked Loop g1809/CO ADDFX1TH 1 2.5 88 +243 7691 F g1808/CI +0 7691 g1808/CO ADDFX1TH 1 2.5 88 +243 7934 F g1807/CI +0 7934 g1807/CO ADDFX1TH 1 2.5 88 +243 8177 F g1806/CI +0 8177 g1806/CO ADDFX1TH 2 2.1 84 +238 8415 F g1805/B0 +0 8415 g1805/Y AO21XLTH 1 1.2 77 +212 8627 F g1804/B0 +0 8627 g1804/Y OAI211XLTH 7 9.3 447 +143 8770 R g1803/A +0 8770 g1803/Y INVX2TH 7 7.9 132 +143 8912 F g1802/B +0 8912 g1802/Y NAND2XLTH 1 1.1 59 +72 8985 R g1795/B1 +0 8985 g1795/Y AOI22XLTH 2 3.7 200 +152 9136 F g1793/CI +0 9136 g1793/CO ADDFX1TH 1 2.5 88 +278 9414 F g1792/CI +0 9414 g1792/CO ADDFX1TH 1 2.5 88 +243 9657 F g1791/CI +0 9657 g1791/CO ADDFX1TH 1 2.5 88 +243 9900 F g1790/CI +0 9900 g1790/CO ADDFX1TH 1 2.5 88 +243 10143 F g1789/CI +0 10143 g1789/CO ADDFX1TH 1 2.5 88 +243 10386 F g1788/CI +0 10386 g1788/CO ADDFX1TH 2 2.5 88 +243 10628 F g1787/A0 +0 10628 g1787/Y OAI22XLTH 8 10.8 537 +302 10931 R g1786/A +0 10931 g1786/Y INVX2TH 8 10.4 162 +175 11106 F g1778/A0 +0 11106 g1778/Y OAI21XLTH 1 1.6 129 +130 11236 R g2/B0 +0 11236 g2/Y OAI2B1X1TH 1 1.0 73 +88 11324 F rem_47_19/REMAINDER[0] dn_reg[0]/SI SDFFQX1TH +0 11324 dn_reg[0]/CK setup 0 +474 11798 R ------------------------------------------------------------Timing slack : UNCONSTRAINED Start-point : dn_reg[1]/CK End-point : dn_reg[0]/SI DEPARTMENT OF ECE, BMSCE Page 45 Implementation of All Digital Phase Locked Loop 6. DIGITAL CONTROLLED OSCILLATOR AND DIVIDER A variety of DCOs can be designed [15][16]. This is the most important part of the phase locked loop. 6.1 TYPES OF DCO: There are two types of DCO usually used[15]. 1. Divide by N counter type 2. Increment-Decrement counter type 6.1.1 Divide by N counter type A simple ÷N counter works as DCO. High frequency signal operates at very high frequency. Divide by N counter produces N bit parallel output. Drawback of it is we can‘t design jitter [4] [15]. The block diagram of it is as shown below: Loop filter o/p Divide by N counter High frequency clock Figure 6.1 Block Diagram of N Counter 6.1.2 Increment-Decrement counter type Increment-Decrement Counter consists of two blocks. Carry is assigned to DECR input and Borrow is assigned to INCR input. ID counter with ÷ N counter for again dividing the OUT. Clock of increment-decrement counter is 2N times multiple of center frequency.[16] DEPARTMENT OF ECE, BMSCE Page 46 Implementation of All Digital Phase Locked Loop The ID counter works on the basis of the carry and borrow signals given by the loop filter i.e the previous block. If no Carries and Borrows are present then ID counter divides OUT by 2 on the positive edges of ID clock. The logical function for ID counter is given by ̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅) If carry is present then half cycle is added and if borrow is present then half cycle is removed from IDOUT signal. Here out is output of increment-decrement counter. The IDout signal is then sent to divide by N counter to being the signal back to the reference frequency. The Toggle FF used here is a special type of flip flop obeying the below conditions [17]. 1) No BORROW or CARRY pulses The toggle-FF switches on every positive edge of the ID clock if no CARRY or BORROW pulses are present. Figure 6.2 ID out for no Carry and no Borrow 2) CARRY input applied when the toggle-FF is in the low state When the toggle-FF goes high on the next positive edge of the ID clock but stays low for the next two clock intervals, the IDout is advanced by one ID clock period. Figure 6.3 ID out for Carry when Toggle FF is low DEPARTMENT OF ECE, BMSCE Page 47 Implementation of All Digital Phase Locked Loop 3) CARRY input applied when the toggle-FF is in the high state The toggle-FF is set to low for the next two clock intervals. Because the CARRY can only be processed when the toggle-FF is in the high state, the maximum frequency of the IDout signal is reached when the toggle-FF follows the pattern of ―high-low-low-high-low-low‖. Therefore, the maximum IDout frequency = 2/3 ID clock frequency. This will limit the hold range of the ADPLL. Figure 6.4 ID out for Carry when Toggle FF is high 4) BORROW input applied when the toggle-FF is in the high A BORROW pulse causes the toggle-FF to be set high on the succeeding two positive edges of the ID clock. This causes the next IDout pulse to be delayed by one ID clock period. The toggle-FF has the pattern of ―low-high-high-low-high-high‖ which gives the min. IDout frequency = 1/3 ID clock frequency. Basically, 1 CARRY pulse adds 1/2 cycle and 1 BORROW pulse removes 1/2 cycle. Figure 6.5 ID out for Borrow when Toggle FF is high DEPARTMENT OF ECE, BMSCE Page 48 Implementation of All Digital Phase Locked Loop 5) BORROW input applied when the toggle-FF is in the low state A BORROW pulse causes the toggle-FF to be set high on the succeeding two positive edges of the ID clock. This causes the next IDout pulse to be delayed by one ID clock period. The toggle-FF has the pattern of ―high-high-low-high-low-high‖ which gives the min. IDout frequency = 1/3 ID clock frequency. Basically, 1 CARRY pulse adds 1/2 cycle and 1 BORROW pulse removes 1/2 cycle. Figure 6.6 ID out for Borrow when Toggle FF is low 6.2 DESIGN IMPLEMENTATION The design used Increment Decrement type counter: 6.3 SIMULATION: The clock was chosen to be 1.6 MHz and the reference signal was taken to be 100 KHz so that the value of N required is 8. DEPARTMENT OF ECE, BMSCE Page 49 Implementation of All Digital Phase Locked Loop Figure 6.7 Simulation results of DCO Sections 6.4-6.7 will give the cadence analysis results for DCO. 6.4 SYNTHESIS REPORT rc:/> synthesize -to_mapped -effort medium Deleting 1 hierarchical instance. It does not transitively drive any primary outputs. Mapping DCO to gates. Info : Replacing a flip-flop with a logic constant 1. [GLO-13] : The instance is 'borrowH_reg62'. : This optimization was enabled by the root attribute 'optimize_constant_1_flops'. Info : Replacing a flip-flop with a logic constant 0. [GLO-12] : The instance is 'borrowL_reg'. : This optimization was enabled by the root attribute 'optimize_constant_0_flops'. Info : Replacing a flip-flop with a logic constant 1. [GLO-13] : The instance is 'borrowL_reg60'. Info : Replacing a flip-flop with a logic constant 1. [GLO-13] : The instance is 'carryH_reg58'. Info : Replacing a flip-flop with a logic constant 0. [GLO-12] : The instance is 'carryL_reg'. Info : Replacing a flip-flop with a logic constant 1. [GLO-13] DEPARTMENT OF ECE, BMSCE Page 50 Implementation of All Digital Phase Locked Loop : The instance is 'carryL_reg56'. Deleting 6 sequential instances. They do not transitively drive any primary outputs. Global mapping target info ========================== Cost Group 'default' target slack: Unconstrained Global mapping status ===================== Worst Total Neg Operation Area Slack Worst Path -----------------------------------------------------------------------------global_map 69 0 N/A Global incremental target info ============================== Cost Group 'default' target slack: Unconstrained Global incremental optimization status ====================================== Worst Total Neg Operation Area Slack Worst Path -----------------------------------------------------------------------------global_inc 69 0 N/A Incremental optimization status =============================== Worst - - DRC Totals - Total Neg Max Max Operation Area Slack Trans Cap -----------------------------------------------------------------------------init_delay 69 0 0 0 init_drc 69 0 0 0 init_area 69 0 0 0 Incremental optimization status =============================== Worst - - DRC Totals - Total Neg Max Max Operation Area Slack Trans Cap -----------------------------------------------------------------------------init_delay 69 0 0 0 init_drc 69 0 0 0 DEPARTMENT OF ECE, BMSCE Page 51 Implementation of All Digital Phase Locked Loop init_area 69 0 0 0 Done mapping DCO Synthesis succeeded. Figure 6.8 Synthesized circuit for DCO 6.5 AREA REPORT rc:/> report area ============================================================ Generated by: Encounter(R) RTL Compiler v08.10-s121_1 Generated on: Dec 17 2013 04:59:36 PM Module: DCO Technology library: slow_highvt 1.0 Operating conditions: slow (balanced_tree) Wireload mode: enclosed Area mode: timing library ============================================================ Instance Cells Cell Area Net Area Wireload ---------------------------------------------------DEPARTMENT OF ECE, BMSCE Page 52 Implementation of All Digital Phase Locked Loop DCO 10 69 0 <none> (D) (D) = wireload is default in technology library 6.6 POWER REPORT rc:/> report power ============================================================ Generated by: Encounter(R) RTL Compiler v08.10-s121_1 Generated on: Dec 17 2013 05:00:25 PM Module: DCO Technology library: slow_highvt 1.0 Operating conditions: slow (balanced_tree) Wireload mode: enclosed Area mode: timing library ============================================================ Leakage Dynamic Total Instance Cells Power(nW) Power(nW) Power(nW) --------------------------------------------DCO 10 44.879 1049.585 1094.464 6.7 TIMING REPORT rc:/> report timing Warning : Possible timing problems have been detected in this design. [TIM-11] : The design is 'DCO'. : Use 'report timing -lint' for more information. ============================================================ Generated by: Encounter(R) RTL Compiler v08.10-s121_1 Generated on: Dec 17 2013 05:00:45 PM Module: DCO Technology library: slow_highvt 1.0 Operating conditions: slow (balanced_tree) Wireload mode: enclosed Area mode: timing library ============================================================ Pin Type Fanout Load Slew Delay Arrival (fF) (ps) (ps) (ps) -------------------------------------------------------------toggleFF_reg/CK 0 0 R toggleFF_reg/Q SDFFQX1TH 5 7.3 142 +314 314 F g354/A +0 314 g354/Y OR2XLTH 1 1.0 64 +190 505 F carryH_reg/SI SDFFQX1TH +0 505 carryH_reg/CK setup 0 +472 977 R -------------------------------------------------------------Timing slack : UNCONSTRAINED DEPARTMENT OF ECE, BMSCE Page 53 Implementation of All Digital Phase Locked Loop Start-point End-point : toggleFF_reg/CK : carryH_reg/SI Sections 6.8- 6.11 will give the cadence analysis results for Clock divider (Divide by N counter) 6.8 SYNTHESIS REPORT rc:/> synthesize -to_mapped -effort medium Deleting 1 hierarchical instance. It does not transitively drive any primary outputs. Trying carrysave optimization (configuration 1 of 1) on module 'Divider'... Info : Done carrysave optimization. [RTLOPT-20] : There is 1 CSA group in module 'Divider'... Accepted. Mapping Divider to gates. Global mapping target info ========================== Cost Group 'default' target slack: Unconstrained Global mapping status ===================== Worst Total Neg Operation Area Slack Worst Path -----------------------------------------------------------------------------global_map 88 0 N/A Global incremental target info ============================== Cost Group 'default' target slack: Unconstrained Global incremental optimization status ====================================== Worst Total Neg Operation Area Slack Worst Path -----------------------------------------------------------------------------global_inc 88 0 N/A Incremental optimization status =============================== Worst - - DRC Totals - Total Neg Max Max DEPARTMENT OF ECE, BMSCE Page 54 Implementation of All Digital Phase Locked Loop Operation Area Slack Trans Cap -----------------------------------------------------------------------------init_delay 88 0 0 0 init_drc 88 0 0 0 init_area 88 0 0 0 rem_inv_qb 86 0 0 0 Incremental optimization status =============================== Worst - - DRC Totals - Total Neg Max Max Operation Area Slack Trans Cap -----------------------------------------------------------------------------init_delay 86 0 0 0 init_drc 86 0 0 0 init_area 86 0 0 0 Done mapping Divider Synthesis succeeded. Figure 6.1 Synthesized circuit for Clock Divider DEPARTMENT OF ECE, BMSCE Page 55 Implementation of All Digital Phase Locked Loop 6.9 AREA REPORT rc:/> report area ============================================================ Generated by: Encounter(R) RTL Compiler v08.10-s121_1 Generated on: Dec 17 2013 05:06:29 PM Module: Divider Technology library: slow_highvt 1.0 Operating conditions: slow (balanced_tree) Wireload mode: enclosed Area mode: timing library ============================================================ Instance Cells Cell Area Net Area Wireload ---------------------------------------------------Divider 10 86 0 <none> (D) (D) = wireload is default in technology library 6.10 POWER REPORT rc:/> report power ============================================================ Generated by: Encounter(R) RTL Compiler v08.10-s121_1 Generated on: Dec 17 2013 05:06:50 PM Module: Divider Technology library: slow_highvt 1.0 Operating conditions: slow (balanced_tree) Wireload mode: enclosed Area mode: timing library ============================================================ Leakage Dynamic Total Instance Cells Power(nW) Power(nW) Power(nW) --------------------------------------------Divider 10 66.878 1936.372 2003.250 6.11 TIMING REPORT rc:/> report timing Warning : Possible timing problems have been detected in this design. [TIM-11] : The design is 'Divider'. : Use 'report timing -lint' for more information. DEPARTMENT OF ECE, BMSCE Page 56 Implementation of All Digital Phase Locked Loop ============================================================ Generated by: Encounter(R) RTL Compiler v08.10-s121_1 Generated on: Dec 17 2013 05:07:07 PM Module: Divider Technology library: slow_highvt 1.0 Operating conditions: slow (balanced_tree) Wireload mode: enclosed Area mode: timing library ============================================================ Pin Type Fanout Load Slew Delay Arrival (fF) (ps) (ps) (ps) ---------------------------------------------------------------clkdiv_reg[1]/CK 0 0 R clkdiv_reg[1]/Q DFFTRXLTH 2 2.8 77 +286 286 R g71/A +0 286 g71/Y NAND2XLTH 2 2.6 114 +96 382 F g69/AN +0 382 g69/Y NAND2BXLTH 2 2.6 121 +189 571 F g67/AN +0 571 g67/Y NAND2BXLTH 4 4.0 160 +215 786 F clkdiv_reg[3]/RN DFFTRXLTH +0 786 clkdiv_reg[3]/CK setup 0 +262 1048 R ---------------------------------------------------------------Timing slack : UNCONSTRAINED Start-point : clkdiv_reg[1]/CK End-point : clkdiv_reg[3]/RN DEPARTMENT OF ECE, BMSCE Page 57 Implementation of All Digital Phase Locked Loop 7. RESULTS: The all-digital phase locked loop was implemented successfully. The Power dissipated and areas occupied by the different modules are Module Name Phase Detector Loop Filter DCO Divider Power Dissipated (nW) 107.178 15159.671 1094.464 2003.250 Area Occupied (µm2) 6 205 69 86 The final synthesized block diagram is Figure 7.1 Fully Synthesized ADPLL DEPARTMENT OF ECE, BMSCE Page 58 Implementation of All Digital Phase Locked Loop 8. CONCLUSIONS AND FUTURE WORK: The Project discusses the implementation of ADPLL. Code for ADPLL is written in Verilog and compiled using NCVerilog, Simulation is done using ISim and RTL is generated using SoC Encounter. The proposed ADPLL consumes a power of 18.3 mW and an area of 376 µm2. The project was a really nice learning experience. There are many Improvements and concepts that still need to be learned, but the basics of an all-digital PLL implementation was covered during this project. The design can be improved by implementing a full custom design. The extra clock input can be removed by implementing a clock independent Digital Control Oscillator and replacing Loop Filter with a Time to Digital Converter (TDC). The PLL can be designed for a particular application such WiMax, GSM, etc and it requires a deeper study in those topics. DEPARTMENT OF ECE, BMSCE Page 59 Implementation of All Digital Phase Locked Loop 9. REFERNCES: 1. E. V. Appleton, Automatic synchronization of triode oscillators, Proc. Cambridge Phil. Soc., 21(Part III):231 (1922-1923) 2. Henri de Bellescize, "La réception synchrone," L'Onde Électrique (later: Revue de l'Electricité et de l'Electronique), vol. 11, pages 230-240 (June 1932) 3. A. B. Grebene, H. R. Camenzind, ―Phase Locking As A New Approach For Tuned Integrated Circuits‖, in Proc. of ISSCC Digest of Technical Papers, pp. 100-101, Feb. 1969. 4. Roland E.Best, ―Phase Locked Loops Design Simulation and Applications‖, McGrawHill, 5th Edition. 5. Shabaany, M.H., Saneei, M., ―A 0.7-to-1.1-GHz all-digital phase-locked loop with a new phase frequency detector and controlled oscillator with body-biasing‖, in Proc. of 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS), 2012, pp. 54 -59, May 2012 6. Kumm M., Klingbeil H., Zipf P, ―An FPGA-Based Linear All-Digital Phase-Locked Loop‖, IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 2487 – 2497 Vol.57 Issue: 9 7. A Das, S Dash, Sahoo A.K. , B C Babu, ―Design and implementation of FPGA based linear all digital phase-locked loop‖, in Proc. of Annual IEEE India Conference (INDICON) 2012, pp. 280 – 285 8. S. Sharma, S. Vallabhaneni, S. Attri, N. Krishman, and R. C. Chauhan. ―Design of an allDigital PLL core on FPGA.‖ http://klabs.org/mapld04/abstracts/sharma_a.doc 9. Saleh R. Al-Araji, Zahir M. Hussain, and Mahmoud A. Al-Qutayri ―Digital Phase Lock Loops: Architectures and Applications‖, Springer, 1st edition 10. M Horowitz, C. Yang, S. Sidiropoulos. "High-speed electrical signaling: overview and limitations". in Proc. of IEEE Microelectronics conference 1999. 11. Bosco Leung, ―VLSI for Wireless Communication‖, Springer, 2nd edition 12. A. H. Khalil, K. T. Ibrahim, and A. E. Salama, ―Digital of ADPLL for good phase and frequency tracking performance,‖ in Proc. of the Nineteenth National Radio Science Conference (NRSC 2002), Alexandria, pp. 284 – 290, March 2002 13. T. Y. Yau and T. Caohuu, ―An Efficient All-Digital Phase-Locked Loop with Input Fault Detection,‖ in Proc. of IEEE conference, Information Science and Applications (ICISA), 2011 14. C. H. Shan, Z. Chen, and Y. Wang, ―An All Digital Phase-Locked Loop Based on Double Edge Triggered Flip-flop,‖ in Proc. of 8th IEEE International Conference on Solid-State and Integrated Circuit Technology, (ICSICT '06), China, pp. 1990-1992, 2006. DEPARTMENT OF ECE, BMSCE Page 60 Implementation of All Digital Phase Locked Loop 15. Kusum Latha and Manoj Kumar: ADPLL Design and Implementation on FPGA, 2013 International Conference on Intelligent Systems and Signal Processing (ISSP). P.no 272277 16. Kusum Latha and Manoj Kumar: ALL Digital Phase-Locked Loop (ADPLL): A Survey, International Journal of Future Computer and Communication, Vol. 2, No. 6, December 2013. P. no 551-555. 17. Kusum Latha and Manoj Kumar: FPGA Implementation of ADPLL with Ripple Reduction Techniques, International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 2012 P.no 99-106. 18. Phase Locked Loops: A control Centric Tutorial by Dann Abramovitch. www.web-ee.com/primers/files/pll_tut_talk.pdf. DEPARTMENT OF ECE, BMSCE Page 61 Implementation of All Digital Phase Locked Loop APPENDIX A The Verilog behavioral codes for different blocks are given in this section Top Module //ADPLL.v module ADPLL(u1,u2,clk); input u1; input clk; inout u2; wire dnup; wire carry; wire borrow; wire divi; PhaseDetector PD(u1,u2,dnup); LoopFilter LF(clk,dnup,carry,borrow); DCO DCO1(clk,carry,borrow,divi); Divider Div(divi,u2); Endmodule Digital Phase detector // PhaseDector.v module PhaseDetector(u1,u2,dnup,clk,reset,N_count); input u1; input u2; output dnup; assign dnup = (u1 ^ u2); // XOR gate for obtaining signal initial begin N=0; end always@(posedge(clk)) //Always loop for obtaining the value of phase begin // error value ‘N’. if(reset) begin if(Q) begin N=N+1; Else N=N; End Else N=0; End End DEPARTMENT OF ECE, BMSCE Page 62 Implementation of All Digital Phase Locked Loop endmodule Loop Filter module LoopFilter(Kclk,dnup,carry,borrow); reg [7:0] K; input Kclk; input dnup; output borrow; output carry; reg borrow; reg carry; reg [7:0] up; reg [7:0] dn; initial begin K = 5'b10000; dn=0; up=0; end always @ (posedge Kclk) begin if(dnup == 1'b1) begin dn = (dn + 1'b1) % K; end else if(dnup == 1'b0) begin up = (up + 1'b1) % K; end end always @ (up) begin if(up>=(K>>1)) begin carry = 1'b1; end else if(up<(K>>1)) begin carry = 1'b0; end end always @ (dn) begin if(dn>=(K>>1)) begin borrow = 1'b1; end DEPARTMENT OF ECE, BMSCE Page 63 Implementation of All Digital Phase Locked Loop else if(dn<(K>>1)) begin borrow = 1'b0; end end endmodule Digital controlled Oscillator module DCO(IDclk,carry,borrow,u2); input IDclk; input carry; input borrow; output u2; wire IDout; reg toggleFF; reg carryL; reg carryH; reg borrowL; reg borrowH; initial begin toggleFF = 1'b0; carryL = 1'b0; carryH = 1'b0; borrowL = 1'b0; borrowH = 1'b0; end always @ (posedge IDclk) begin if(carryH == 1'b1 && toggleFF == 1'b0) begin carryH = 1'b0; end else if(carryL == 1'b1 && toggleFF == 1'b0) begin carryL = 1'b0; carryH = 1'b1; toggleFF = ! toggleFF; end else if(borrowH == 1'b1 && toggleFF == 1'b1) begin borrowH = 1'b0; end else if(borrowL == 1'b1 && toggleFF == 1'b0) begin borrowL = 1'b0; DEPARTMENT OF ECE, BMSCE Page 64 Implementation of All Digital Phase Locked Loop borrowH = 1'b1; toggleFF = ! toggleFF; end else toggleFF = ! toggleFF; end always @ (posedge carry) begin if(toggleFF == 1'b0) carryL = 1'b1; else if (toggleFF == 1'b1) carryH = 1'b1; end always @ (posedge borrow) begin if(toggleFF == 1'b0) borrowL = 1'b1; else if (toggleFF == 1'b1) borrowH = 1'b1; end assign IDout = (!IDclk)&(!toggleFF); assign u2 = IDout; endmodule DEPARTMENT OF ECE, BMSCE Page 65 Implementation of All Digital Phase Locked Loop APPENDIX B: NETLIST GENERATED CODE // Generated by Cadence Encounter(R) RTL Compiler v08.10-s121_1 module PhaseDetector(u1, u2, dnup); input u1, u2; output dnup; wire u1, u2; wire dnup; XOR2XLTH g10(.A (u2), .B (u1), .Y (dnup)); endmodule // Generated by Cadence Encounter(R) RTL Compiler v08.10-s121_1 module remainder_unsigned(A, B, REMAINDER); input [7:0] A, B; output [7:0] REMAINDER; wire [7:0] A, B; wire [7:0] REMAINDER; wire n_0, n_1, n_3, n_4, n_5, n_6, n_7, n_8; wire n_9, n_10, n_11, n_12, n_13, n_14, n_15, n_16; wire n_17, n_18, n_19, n_20, n_21, n_22, n_23, n_24; wire n_25, n_26, n_27, n_28, n_29, n_30, n_31, n_32; wire n_33, n_34, n_35, n_36, n_37, n_38, n_39, n_40; wire n_41, n_42, n_43, n_44, n_45, n_46, n_47, n_48; wire n_49, n_50, n_51, n_52, n_53, n_54, n_55, n_56; wire n_57, n_58, n_59, n_60, n_61, n_62, n_63, n_64; wire n_65, n_66, n_67, n_68, n_69, n_70, n_71, n_72; wire n_73, n_74, n_75, n_76, n_77, n_78, n_79, n_80; wire n_81, n_82, n_83, n_84, n_85, n_86, n_87, n_88; wire n_89, n_90, n_91, n_92, n_93, n_94, n_95, n_96; wire n_97, n_98, n_99, n_100, n_101, n_102, n_103, n_104; wire n_105, n_106, n_107, n_108, n_109, n_110, n_111, n_112; wire n_113, n_114, n_115, n_116, n_117, n_118, n_119, n_120; wire n_128; OAI21XLTH g1778(.A0 (n_119), .A1 (n_8), .B0 (A[0]), .Y (n_128)); OAI22XLTH g1779(.A0 (n_119), .A1 (n_108), .B0 (n_120), .B1 (n_105), .Y (REMAINDER[1])); OAI22XLTH g1780(.A0 (n_119), .A1 (n_112), .B0 (n_120), .B1 (n_99), .Y (REMAINDER[3])); OAI32XLTH g1781(.A0 (n_118), .A1 (n_103), .A2 (B[7]), .B0 (n_120), .B1 (n_103), .Y (REMAINDER[7])); OAI22XLTH g1782(.A0 (n_119), .A1 (n_117), .B0 (n_120), .B1 (n_104), .Y (REMAINDER[6])); DEPARTMENT OF ECE, BMSCE Page 66 Implementation of All Digital Phase Locked Loop OAI22XLTH g1783(.A0 (n_119), .A1 (n_116), .B0 (n_120), .B1 (n_100), .Y (REMAINDER[5])); OAI22XLTH g1784(.A0 (n_120), .A1 (n_101), .B0 (n_119), .B1 (n_114), .Y (REMAINDER[4])); OAI22XLTH g1785(.A0 (n_120), .A1 (n_102), .B0 (n_119), .B1 (n_110), .Y (REMAINDER[2])); INVX2TH g1786(.A (n_120), .Y (n_119)); OAI22XLTH g1787(.A0 (n_118), .A1 (n_106), .B0 (n_103), .B1 (B[7]), .Y (n_120)); ADDFX1TH g1788(.A (n_104), .B (B[6]), .CI (n_115), .S (n_117), .CO (n_118)); ADDFX1TH g1789(.A (n_100), .B (B[5]), .CI (n_113), .S (n_116), .CO (n_115)); ADDFX1TH g1790(.A (n_101), .B (B[4]), .CI (n_111), .S (n_114), .CO (n_113)); ADDFX1TH g1791(.A (n_99), .B (B[3]), .CI (n_109), .S (n_112), .CO (n_111)); ADDFX1TH g1792(.A (n_102), .B (B[2]), .CI (n_107), .S (n_110), .CO (n_109)); ADDFX1TH g1793(.A (n_16), .B (B[1]), .CI (n_105), .S (n_108), .CO (n_107)); AND2X1TH g1794(.A (n_103), .B (B[7]), .Y (n_106)); AOI22XLTH g1795(.A0 (n_96), .A1 (n_13), .B0 (A[1]), .B1 (n_98), .Y (n_105)); AOI22XLTH g1796(.A0 (n_97), .A1 (n_83), .B0 (n_93), .B1 (n_96), .Y (n_104)); AOI32XLTH g1797(.A0 (n_7), .A1 (n_79), .A2 (n_94), .B0 (n_97), .B1 (n_79), .Y (n_103)); AOI22XLTH g1798(.A0 (n_96), .A1 (n_86), .B0 (n_0), .B1 (n_97), .Y (n_102)); AOI22XLTH g1799(.A0 (n_97), .A1 (n_81), .B0 (n_90), .B1 (n_96), .Y (n_101)); AOI22XLTH g1800(.A0 (n_97), .A1 (n_82), .B0 (n_92), .B1 (n_96), .Y (n_100)); AOI22XLTH g1801(.A0 (n_97), .A1 (n_80), .B0 (n_88), .B1 (n_96), .Y (n_99)); NAND2XLTH g1802(.A (B[0]), .B (n_96), .Y (n_98)); INVX2TH g1803(.A (n_97), .Y (n_96)); OAI211XLTH g1804(.A0 (n_79), .A1 (n_7), .B0 (n_95), .C0 (n_6), .Y (n_97)); AO21XLTH g1805(.A0 (n_79), .A1 (n_7), .B0 (n_94), .Y (n_95)); ADDFX1TH g1806(.A (n_83), .B (n_10), .CI (n_91), .S (n_93), .CO (n_94)); ADDFX1TH g1807(.A (n_82), .B (n_9), .CI (n_89), .S (n_92), .CO (n_91)); ADDFX1TH g1808(.A (n_81), .B (n_3), .CI (n_87), .S (n_90), .CO (n_89)); ADDFX1TH g1809(.A (n_80), .B (n_4), .CI (n_85), .S (n_88), .CO DEPARTMENT OF ECE, BMSCE Page 67 Implementation of All Digital Phase Locked Loop (n_87)); ADDFX1TH g1810(.A (n_14), .B (n_5), .CI (n_0), .S (n_86), .CO (n_85)); OAI21XLTH g1812(.A0 (n_78), .A1 (n_8), .B0 (A[2]), .Y (n_84)); OAI22XLTH g1813(.A0 (n_78), .A1 (n_74), .B0 (n_77), .B1 (n_65), .Y (n_83)); OAI22XLTH g1814(.A0 (n_77), .A1 (n_64), .B0 (n_78), .B1 (n_73), .Y (n_82)); OAI22XLTH g1815(.A0 (n_78), .A1 (n_71), .B0 (n_77), .B1 (n_66), .Y (n_81)); OAI22XLTH g1816(.A0 (n_77), .A1 (n_67), .B0 (n_78), .B1 (n_69), .Y (n_80)); OAI32XLTH g1817(.A0 (n_75), .A1 (n_63), .A2 (B[5]), .B0 (n_77), .B1 (n_63), .Y (n_79)); INVX2TH g1818(.A (n_78), .Y (n_77)); OAI2B11XLTH g1819(.A0 (n_10), .A1N (n_63), .B0 (n_76), .C0 (n_15), .Y (n_78)); OAI21XLTH g1820(.A0 (n_63), .A1 (B[5]), .B0 (n_75), .Y (n_76)); ADDFX1TH g1821(.A (n_65), .B (B[4]), .CI (n_72), .S (n_74), .CO (n_75)); ADDFX1TH g1822(.A (n_64), .B (B[3]), .CI (n_70), .S (n_73), .CO (n_72)); ADDFX1TH g1823(.A (n_66), .B (B[2]), .CI (n_68), .S (n_71), .CO (n_70)); ADDFX1TH g1824(.A (n_11), .B (B[1]), .CI (n_67), .S (n_69), .CO (n_68)); AOI22XLTH g1825(.A0 (n_61), .A1 (n_19), .B0 (A[3]), .B1 (n_62), .Y (n_67)); AOI22XLTH g1826(.A0 (n_61), .A1 (n_54), .B0 (n_1), .B1 (n_60), .Y (n_66)); AOI22XLTH g1827(.A0 (n_60), .A1 (n_50), .B0 (n_57), .B1 (n_61), .Y (n_65)); AOI22XLTH g1828(.A0 (n_61), .A1 (n_56), .B0 (n_51), .B1 (n_60), .Y (n_64)); AOI32XLTH g1829(.A0 (n_9), .A1 (n_49), .A2 (n_58), .B0 (n_60), .B1 (n_49), .Y (n_63)); NAND2XLTH g1830(.A (B[0]), .B (n_61), .Y (n_62)); INVX2TH g1831(.A (n_60), .Y (n_61)); OAI211XLTH g1832(.A0 (n_49), .A1 (n_9), .B0 (n_59), .C0 (n_22), .Y (n_60)); AO21XLTH g1833(.A0 (n_49), .A1 (n_9), .B0 (n_58), .Y (n_59)); ADDFX1TH g1834(.A (n_50), .B (n_3), .CI (n_55), .S (n_57), .CO (n_58)); ADDFX1TH g1835(.A (n_51), .B (n_4), .CI (n_53), .S (n_56), .CO (n_55)); ADDFX1TH g1836(.A (n_20), .B (n_5), .CI (n_1), .S (n_54), .CO (n_53)); OAI21XLTH g1838(.A0 (n_47), .A1 (n_8), .B0 (A[4]), .Y (n_52)); OAI22XLTH g1839(.A0 (n_47), .A1 (n_43), .B0 (n_48), .B1 (n_41), .Y (n_51)); DEPARTMENT OF ECE, BMSCE Page 68 Implementation of All Digital Phase Locked Loop OAI22XLTH g1840(.A0 (n_47), .A1 (n_44), .B0 (n_48), .B1 (n_40), .Y (n_50)); OAI32XLTH g1841(.A0 (n_45), .A1 (n_39), .A2 (B[3]), .B0 (n_48), .B1 (n_39), .Y (n_49)); INVX2TH g1842(.A (n_47), .Y (n_48)); OAI2B11XLTH g1843(.A0 (n_3), .A1N (n_39), .B0 (n_46), .C0 (n_23), .Y (n_47)); OAI21XLTH g1844(.A0 (n_39), .A1 (B[3]), .B0 (n_45), .Y (n_46)); ADDFX1TH g1845(.A (n_40), .B (B[2]), .CI (n_42), .S (n_44), .CO (n_45)); ADDFX1TH g1846(.A (n_12), .B (B[1]), .CI (n_41), .S (n_43), .CO (n_42)); AOI22XLTH g1847(.A0 (n_37), .A1 (n_17), .B0 (A[5]), .B1 (n_38), .Y (n_41)); AOI2BB2XLTH g1848(.A0N (n_31), .A1N (n_37), .B0 (n_37), .B1 (n_35), .Y (n_40)); AOI32XLTH g1849(.A0 (n_4), .A1 (n_30), .A2 (n_33), .B0 (n_36), .B1 (n_30), .Y (n_39)); NAND2XLTH g1850(.A (B[0]), .B (n_37), .Y (n_38)); CLKINVX2TH g1851(.A (n_36), .Y (n_37)); OAI211XLTH g1852(.A0 (n_30), .A1 (n_4), .B0 (n_34), .C0 (n_24), .Y (n_36)); AOI211XLTH g1853(.A0 (n_31), .A1 (n_5), .B0 (n_32), .C0 (n_17), .Y (n_35)); AO21XLTH g1854(.A0 (n_30), .A1 (n_4), .B0 (n_33), .Y (n_34)); OAI22XLTH g1855(.A0 (n_31), .A1 (n_21), .B0 (n_17), .B1 (B[1]), .Y (n_33)); NOR2XLTH g1856(.A (n_31), .B (n_5), .Y (n_32)); OAI21XLTH g1857(.A0 (n_29), .A1 (n_8), .B0 (A[6]), .Y (n_31)); MXI2XLTH g1858(.S0 (n_29), .B (n_26), .A (n_28), .Y (n_30)); NAND3XLTH g1859(.A (n_27), .B (n_4), .C (n_24), .Y (n_29)); AOI2BB1XLTH g1860(.A0N (n_26), .A1N (B[1]), .B0 (n_18), .Y (n_28)); OAI21XLTH g1861(.A0 (n_18), .A1 (B[1]), .B0 (n_26), .Y (n_27)); OAI31XLTH g1862(.A0 (n_8), .A1 (B[1]), .A2 (n_25), .B0 (A[7]), .Y (n_26)); NAND2XLTH g1863(.A (n_24), .B (n_4), .Y (n_25)); AND2X1TH g1864(.A (n_3), .B (n_23), .Y (n_24)); AND2X1TH g1865(.A (n_9), .B (n_22), .Y (n_23)); AND2X1TH g1866(.A (n_10), .B (n_15), .Y (n_22)); AND2X1TH g1867(.A (n_17), .B (B[1]), .Y (n_21)); CLKINVX2TH g1868(.A (n_19), .Y (n_20)); NOR2XLTH g1869(.A (A[3]), .B (n_8), .Y (n_19)); NOR2XLTH g1870(.A (A[6]), .B (n_8), .Y (n_18)); NOR2XLTH g1871(.A (A[5]), .B (n_8), .Y (n_17)); NOR2XLTH g1873(.A (A[0]), .B (n_8), .Y (n_16)); NOR2XLTH g1874(.A (B[7]), .B (B[6]), .Y (n_15)); CLKINVX2TH g1875(.A (n_13), .Y (n_14)); NOR2XLTH g1876(.A (A[1]), .B (n_8), .Y (n_13)); DEPARTMENT OF ECE, BMSCE Page 69 Implementation of All Digital Phase Locked Loop NOR2XLTH g1878(.A (A[4]), .B (n_8), .Y (n_12)); NOR2XLTH g1880(.A (A[2]), .B (n_8), .Y (n_11)); INVX2TH g1881(.A (B[5]), .Y (n_10)); INVX2TH g1882(.A (B[4]), .Y (n_9)); INVX2TH g1883(.A (B[0]), .Y (n_8)); CLKINVX2TH g1884(.A (B[6]), .Y (n_7)); INVX1TH g1885(.A (B[7]), .Y (n_6)); INVX2TH g1886(.A (B[1]), .Y (n_5)); INVX2TH g1887(.A (B[2]), .Y (n_4)); INVX2TH g1888(.A (B[3]), .Y (n_3)); OAI2B1X1TH g2(.A0 (n_119), .A1N (n_16), .B0 (n_128), .Y (REMAINDER[0])); OAI2B1X1TH g1891(.A0 (n_47), .A1N (n_12), .B0 (n_52), .Y (n_1)); OAI2B1X1TH g1894(.A0 (n_78), .A1N (n_11), .B0 (n_84), .Y (n_0)); endmodule module remainder_unsigned_1(A, B, REMAINDER); input [7:0] A, B; output [7:0] REMAINDER; wire [7:0] A, B; wire [7:0] REMAINDER; wire n_0, n_1, n_3, n_4, n_5, n_6, n_7, n_8; wire n_9, n_10, n_11, n_12, n_13, n_14, n_15, n_16; wire n_17, n_18, n_19, n_20, n_21, n_22, n_23, n_24; wire n_25, n_26, n_27, n_28, n_29, n_30, n_31, n_32; wire n_33, n_34, n_35, n_36, n_37, n_38, n_39, n_40; wire n_41, n_42, n_43, n_44, n_45, n_46, n_47, n_48; wire n_49, n_50, n_51, n_52, n_53, n_54, n_55, n_56; wire n_57, n_58, n_59, n_60, n_61, n_62, n_63, n_64; wire n_65, n_66, n_67, n_68, n_69, n_70, n_71, n_72; wire n_73, n_74, n_75, n_76, n_77, n_78, n_79, n_80; wire n_81, n_82, n_83, n_84, n_85, n_86, n_87, n_88; wire n_89, n_90, n_91, n_92, n_93, n_94, n_95, n_96; wire n_97, n_98, n_99, n_100, n_101, n_102, n_103, n_104; wire n_105, n_106, n_107, n_108, n_109, n_110, n_111, n_112; wire n_113, n_114, n_115, n_116, n_117, n_118, n_119, n_120; wire n_128; OAI21XLTH g1778(.A0 (n_119), .A1 (n_8), .B0 (A[0]), .Y (n_128)); OAI22XLTH g1779(.A0 (n_119), .A1 (n_108), .B0 (n_120), .B1 (n_105), .Y (REMAINDER[1])); OAI22XLTH g1780(.A0 (n_119), .A1 (n_112), .B0 (n_120), .B1 (n_99), .Y (REMAINDER[3])); OAI32XLTH g1781(.A0 (n_118), .A1 (n_103), .A2 (B[7]), .B0 (n_120), .B1 (n_103), .Y (REMAINDER[7])); OAI22XLTH g1782(.A0 (n_119), .A1 (n_117), .B0 (n_120), .B1 (n_104), .Y (REMAINDER[6])); OAI22XLTH g1783(.A0 (n_119), .A1 (n_116), .B0 (n_120), .B1 (n_100), .Y (REMAINDER[5])); DEPARTMENT OF ECE, BMSCE Page 70 Implementation of All Digital Phase Locked Loop OAI22XLTH g1784(.A0 (n_120), .A1 (n_101), .B0 (n_119), .B1 (n_114), .Y (REMAINDER[4])); OAI22XLTH g1785(.A0 (n_120), .A1 (n_102), .B0 (n_119), .B1 (n_110), .Y (REMAINDER[2])); INVX2TH g1786(.A (n_120), .Y (n_119)); OAI22XLTH g1787(.A0 (n_118), .A1 (n_106), .B0 (n_103), .B1 (B[7]), .Y (n_120)); ADDFX1TH g1788(.A (n_104), .B (B[6]), .CI (n_115), .S (n_117), .CO (n_118)); ADDFX1TH g1789(.A (n_100), .B (B[5]), .CI (n_113), .S (n_116), .CO (n_115)); ADDFX1TH g1790(.A (n_101), .B (B[4]), .CI (n_111), .S (n_114), .CO (n_113)); ADDFX1TH g1791(.A (n_99), .B (B[3]), .CI (n_109), .S (n_112), .CO (n_111)); ADDFX1TH g1792(.A (n_102), .B (B[2]), .CI (n_107), .S (n_110), .CO (n_109)); ADDFX1TH g1793(.A (n_16), .B (B[1]), .CI (n_105), .S (n_108), .CO (n_107)); AND2X1TH g1794(.A (n_103), .B (B[7]), .Y (n_106)); AOI22XLTH g1795(.A0 (n_96), .A1 (n_13), .B0 (A[1]), .B1 (n_98), .Y (n_105)); AOI22XLTH g1796(.A0 (n_97), .A1 (n_83), .B0 (n_93), .B1 (n_96), .Y (n_104)); AOI32XLTH g1797(.A0 (n_7), .A1 (n_79), .A2 (n_94), .B0 (n_97), .B1 (n_79), .Y (n_103)); AOI22XLTH g1798(.A0 (n_96), .A1 (n_86), .B0 (n_0), .B1 (n_97), .Y (n_102)); AOI22XLTH g1799(.A0 (n_97), .A1 (n_81), .B0 (n_90), .B1 (n_96), .Y (n_101)); AOI22XLTH g1800(.A0 (n_97), .A1 (n_82), .B0 (n_92), .B1 (n_96), .Y (n_100)); AOI22XLTH g1801(.A0 (n_97), .A1 (n_80), .B0 (n_88), .B1 (n_96), .Y (n_99)); NAND2XLTH g1802(.A (B[0]), .B (n_96), .Y (n_98)); INVX2TH g1803(.A (n_97), .Y (n_96)); OAI211XLTH g1804(.A0 (n_79), .A1 (n_7), .B0 (n_95), .C0 (n_6), .Y (n_97)); AO21XLTH g1805(.A0 (n_79), .A1 (n_7), .B0 (n_94), .Y (n_95)); ADDFX1TH g1806(.A (n_83), .B (n_10), .CI (n_91), .S (n_93), .CO (n_94)); ADDFX1TH g1807(.A (n_82), .B (n_9), .CI (n_89), .S (n_92), .CO (n_91)); ADDFX1TH g1808(.A (n_81), .B (n_3), .CI (n_87), .S (n_90), .CO (n_89)); ADDFX1TH g1809(.A (n_80), .B (n_4), .CI (n_85), .S (n_88), .CO (n_87)); ADDFX1TH g1810(.A (n_14), .B (n_5), .CI (n_0), .S (n_86), .CO (n_85)); DEPARTMENT OF ECE, BMSCE Page 71 Implementation of All Digital Phase Locked Loop OAI21XLTH g1812(.A0 (n_78), .A1 (n_8), .B0 (A[2]), .Y (n_84)); OAI22XLTH g1813(.A0 (n_78), .A1 (n_74), .B0 (n_77), .B1 (n_65), .Y (n_83)); OAI22XLTH g1814(.A0 (n_77), .A1 (n_64), .B0 (n_78), .B1 (n_73), .Y (n_82)); OAI22XLTH g1815(.A0 (n_78), .A1 (n_71), .B0 (n_77), .B1 (n_66), .Y (n_81)); OAI22XLTH g1816(.A0 (n_77), .A1 (n_67), .B0 (n_78), .B1 (n_69), .Y (n_80)); OAI32XLTH g1817(.A0 (n_75), .A1 (n_63), .A2 (B[5]), .B0 (n_77), .B1 (n_63), .Y (n_79)); INVX2TH g1818(.A (n_78), .Y (n_77)); OAI2B11XLTH g1819(.A0 (n_10), .A1N (n_63), .B0 (n_76), .C0 (n_15), .Y (n_78)); OAI21XLTH g1820(.A0 (n_63), .A1 (B[5]), .B0 (n_75), .Y (n_76)); ADDFX1TH g1821(.A (n_65), .B (B[4]), .CI (n_72), .S (n_74), .CO (n_75)); ADDFX1TH g1822(.A (n_64), .B (B[3]), .CI (n_70), .S (n_73), .CO (n_72)); ADDFX1TH g1823(.A (n_66), .B (B[2]), .CI (n_68), .S (n_71), .CO (n_70)); ADDFX1TH g1824(.A (n_11), .B (B[1]), .CI (n_67), .S (n_69), .CO (n_68)); AOI22XLTH g1825(.A0 (n_61), .A1 (n_19), .B0 (A[3]), .B1 (n_62), .Y (n_67)); AOI22XLTH g1826(.A0 (n_61), .A1 (n_54), .B0 (n_1), .B1 (n_60), .Y (n_66)); AOI22XLTH g1827(.A0 (n_60), .A1 (n_50), .B0 (n_57), .B1 (n_61), .Y (n_65)); AOI22XLTH g1828(.A0 (n_61), .A1 (n_56), .B0 (n_51), .B1 (n_60), .Y (n_64)); AOI32XLTH g1829(.A0 (n_9), .A1 (n_49), .A2 (n_58), .B0 (n_60), .B1 (n_49), .Y (n_63)); NAND2XLTH g1830(.A (B[0]), .B (n_61), .Y (n_62)); INVX2TH g1831(.A (n_60), .Y (n_61)); OAI211XLTH g1832(.A0 (n_49), .A1 (n_9), .B0 (n_59), .C0 (n_22), .Y (n_60)); AO21XLTH g1833(.A0 (n_49), .A1 (n_9), .B0 (n_58), .Y (n_59)); ADDFX1TH g1834(.A (n_50), .B (n_3), .CI (n_55), .S (n_57), .CO (n_58)); ADDFX1TH g1835(.A (n_51), .B (n_4), .CI (n_53), .S (n_56), .CO (n_55)); ADDFX1TH g1836(.A (n_20), .B (n_5), .CI (n_1), .S (n_54), .CO (n_53)); OAI21XLTH g1838(.A0 (n_47), .A1 (n_8), .B0 (A[4]), .Y (n_52)); OAI22XLTH g1839(.A0 (n_47), .A1 (n_43), .B0 (n_48), .B1 (n_41), .Y (n_51)); OAI22XLTH g1840(.A0 (n_47), .A1 (n_44), .B0 (n_48), .B1 (n_40), .Y (n_50)); DEPARTMENT OF ECE, BMSCE Page 72 Implementation of All Digital Phase Locked Loop OAI32XLTH g1841(.A0 (n_45), .A1 (n_39), .A2 (B[3]), .B0 (n_48), .B1 (n_39), .Y (n_49)); INVX2TH g1842(.A (n_47), .Y (n_48)); OAI2B11XLTH g1843(.A0 (n_3), .A1N (n_39), .B0 (n_46), .C0 (n_23), .Y (n_47)); OAI21XLTH g1844(.A0 (n_39), .A1 (B[3]), .B0 (n_45), .Y (n_46)); ADDFX1TH g1845(.A (n_40), .B (B[2]), .CI (n_42), .S (n_44), .CO (n_45)); ADDFX1TH g1846(.A (n_12), .B (B[1]), .CI (n_41), .S (n_43), .CO (n_42)); AOI22XLTH g1847(.A0 (n_37), .A1 (n_17), .B0 (A[5]), .B1 (n_38), .Y (n_41)); AOI2BB2XLTH g1848(.A0N (n_31), .A1N (n_37), .B0 (n_37), .B1 (n_35), .Y (n_40)); AOI32XLTH g1849(.A0 (n_4), .A1 (n_30), .A2 (n_33), .B0 (n_36), .B1 (n_30), .Y (n_39)); NAND2XLTH g1850(.A (B[0]), .B (n_37), .Y (n_38)); CLKINVX2TH g1851(.A (n_36), .Y (n_37)); OAI211XLTH g1852(.A0 (n_30), .A1 (n_4), .B0 (n_34), .C0 (n_24), .Y (n_36)); AOI211XLTH g1853(.A0 (n_31), .A1 (n_5), .B0 (n_32), .C0 (n_17), .Y (n_35)); AO21XLTH g1854(.A0 (n_30), .A1 (n_4), .B0 (n_33), .Y (n_34)); OAI22XLTH g1855(.A0 (n_31), .A1 (n_21), .B0 (n_17), .B1 (B[1]), .Y (n_33)); NOR2XLTH g1856(.A (n_31), .B (n_5), .Y (n_32)); OAI21XLTH g1857(.A0 (n_29), .A1 (n_8), .B0 (A[6]), .Y (n_31)); MXI2XLTH g1858(.S0 (n_29), .B (n_26), .A (n_28), .Y (n_30)); NAND3XLTH g1859(.A (n_27), .B (n_4), .C (n_24), .Y (n_29)); AOI2BB1XLTH g1860(.A0N (n_26), .A1N (B[1]), .B0 (n_18), .Y (n_28)); OAI21XLTH g1861(.A0 (n_18), .A1 (B[1]), .B0 (n_26), .Y (n_27)); OAI31XLTH g1862(.A0 (n_8), .A1 (B[1]), .A2 (n_25), .B0 (A[7]), .Y (n_26)); NAND2XLTH g1863(.A (n_24), .B (n_4), .Y (n_25)); AND2X1TH g1864(.A (n_3), .B (n_23), .Y (n_24)); AND2X1TH g1865(.A (n_9), .B (n_22), .Y (n_23)); AND2X1TH g1866(.A (n_10), .B (n_15), .Y (n_22)); AND2X1TH g1867(.A (n_17), .B (B[1]), .Y (n_21)); CLKINVX2TH g1868(.A (n_19), .Y (n_20)); NOR2XLTH g1869(.A (A[3]), .B (n_8), .Y (n_19)); NOR2XLTH g1870(.A (A[6]), .B (n_8), .Y (n_18)); NOR2XLTH g1871(.A (A[5]), .B (n_8), .Y (n_17)); NOR2XLTH g1873(.A (A[0]), .B (n_8), .Y (n_16)); NOR2XLTH g1874(.A (B[7]), .B (B[6]), .Y (n_15)); CLKINVX2TH g1875(.A (n_13), .Y (n_14)); NOR2XLTH g1876(.A (A[1]), .B (n_8), .Y (n_13)); NOR2XLTH g1878(.A (A[4]), .B (n_8), .Y (n_12)); NOR2XLTH g1880(.A (A[2]), .B (n_8), .Y (n_11)); DEPARTMENT OF ECE, BMSCE Page 73 Implementation of All Digital Phase Locked Loop INVX2TH g1881(.A (B[5]), .Y (n_10)); INVX2TH g1882(.A (B[4]), .Y (n_9)); INVX2TH g1883(.A (B[0]), .Y (n_8)); CLKINVX2TH g1884(.A (B[6]), .Y (n_7)); INVX1TH g1885(.A (B[7]), .Y (n_6)); INVX2TH g1886(.A (B[1]), .Y (n_5)); INVX2TH g1887(.A (B[2]), .Y (n_4)); INVX2TH g1888(.A (B[3]), .Y (n_3)); OAI2B1X1TH g2(.A0 (n_119), .A1N (n_16), .B0 (n_128), .Y (REMAINDER[0])); OAI2B1X1TH g1891(.A0 (n_47), .A1N (n_12), .B0 (n_52), .Y (n_1)); OAI2B1X1TH g1894(.A0 (n_78), .A1N (n_11), .B0 (n_84), .Y (n_0)); endmodule module LoopFilter(Kclk, dnup, carry, borrow); input Kclk, dnup; output carry, borrow; wire Kclk, dnup; wire carry, borrow; wire \K[0] , \K[0]_29 , \K[1] , \K[2] , \K[3] , \K[4] , \K[5] , \K[6] ; wire \dn[0] , \dn[1] , \dn[2] , \dn[3] , \dn[4] , \dn[5] , \dn[6] , \dn[7] ; wire n_0, n_1, n_2, n_3, n_4, n_5, n_6, n_7; wire n_8, n_9, n_10, n_11, n_12, n_13, n_14, n_15; wire n_16, n_17, n_18, n_19, n_20, n_21, n_22, n_23; wire n_24, n_25, n_26, n_27, n_28, n_29, n_30, n_31; wire n_32, n_33, n_34, n_35, n_36, n_37, n_38, n_39; wire n_40, n_41, n_42, n_43, n_44, n_45, n_46, n_47; wire n_48, n_49, n_50, n_51, n_52, n_53, n_54, n_55; wire n_56, n_57, n_58, n_59, n_60, n_61, n_62, n_63; wire n_64, n_65, n_66, n_67, n_68, n_69, n_70, n_71; wire n_72, n_73, n_74, n_75, n_76, n_77, n_78, n_79; wire n_80, n_81, n_82, n_83, n_84, n_85, n_86, n_88; wire n_89, n_90, n_91, n_92, n_93, n_94, n_95, n_96; wire n_97, n_98, n_99, n_100, n_101, n_102, n_103, n_104; wire n_105, n_108, n_109, n_110, n_111, n_112, n_113, n_114; wire n_116, n_117, n_118, n_119, n_120, n_121, n_122, n_123; wire n_124, \up[0] , \up[1] , \up[2] , \up[3] , \up[4] , \up[5] , \up[6] ; wire \up[7] ; remainder_unsigned rem_47_19(.A ({n_81, n_82, n_83, n_98, n_99, n_84, n_85, n_86}), .B ({\K[6] , \K[5] , \K[4] , \K[3] , \K[2] , \K[1] , \K[0] , \K[0]_29 }), .REMAINDER ({n_108, n_109, n_110, n_111, n_112, n_113, n_114, n_116})); remainder_unsigned_1 rem_51_20(.A ({n_75, n_76, n_77, n_96, n_97, DEPARTMENT OF ECE, BMSCE Page 74 Implementation of All Digital Phase Locked Loop n_78, n_79, n_80}), .B ({\K[6] , \K[5] , \K[4] , \K[3] , \K[2] , \K[1] , \K[0] , \K[0]_29 }), .REMAINDER ({n_117, n_118, n_119, n_120, n_121, n_122, n_123, n_124})); TLATX1TH borrow_reg(.G (n_68), .D (n_67), .Q (borrow), .QN ()); TLATX1TH carry_reg(.G (n_73), .D (n_71), .Q (carry), .QN ()); XNOR2XLTH g1972(.A (n_72), .B (\dn[7] ), .Y (n_81)); XNOR2XLTH g1973(.A (n_74), .B (\up[7] ), .Y (n_75)); XNOR2XLTH g1975(.A (n_70), .B (\dn[6] ), .Y (n_82)); XNOR2XLTH g1976(.A (n_69), .B (\up[6] ), .Y (n_76)); NAND2BXLTH g1977(.AN (n_69), .B (\up[6] ), .Y (n_74)); OR2XLTH g1978(.A (n_71), .B (n_59), .Y (n_73)); NAND2BXLTH g1979(.AN (n_70), .B (\dn[6] ), .Y (n_72)); OAI211XLTH g1980(.A0 (n_66), .A1 (n_16), .B0 (n_48), .C0 (n_13), .Y (n_71)); XNOR2XLTH g1982(.A (n_65), .B (\dn[5] ), .Y (n_83)); XNOR2XLTH g1983(.A (n_64), .B (\up[5] ), .Y (n_77)); NAND2BXLTH g1984(.AN (n_65), .B (\dn[5] ), .Y (n_70)); NAND2BXLTH g1985(.AN (n_64), .B (\up[5] ), .Y (n_69)); OR2XLTH g1986(.A (n_67), .B (n_61), .Y (n_68)); OR3XLTH g1987(.A (n_62), .B (n_39), .C (\dn[7] ), .Y (n_67)); OAI2B11XLTH g1988(.A0 (\up[4] ), .A1N (n_101), .B0 (n_63), .C0 (n_22), .Y (n_66)); XNOR2XLTH g1989(.A (n_56), .B (\dn[4] ), .Y (n_98)); XNOR2XLTH g1990(.A (n_57), .B (\up[4] ), .Y (n_96)); NAND2BXLTH g1991(.AN (n_56), .B (\dn[4] ), .Y (n_65)); NAND2BXLTH g1992(.AN (n_57), .B (\up[4] ), .Y (n_64)); OAI21XLTH g1993(.A0 (n_55), .A1 (n_102), .B0 (n_60), .Y (n_63)); OAI22XLTH g1994(.A0 (n_58), .A1 (n_18), .B0 (n_11), .B1 (n_88), .Y (n_62)); AOI222XLTH g1995(.A0 (n_30), .A1 (n_54), .B0 (n_3), .B1 (\dn[6] ), .C0 (n_30), .C1 (n_31), .Y (n_61)); OAI2BB1XLTH g1996(.A0N (n_102), .A1N (n_55), .B0 (\up[3] ), .Y (n_60)); AOI222XLTH g1997(.A0 (n_32), .A1 (n_29), .B0 (n_3), .B1 (\up[6] ), .C0 (n_53), .C1 (n_29), .Y (n_59)); AOI32XLTH g1998(.A0 (n_17), .A1 (n_27), .A2 (n_51), .B0 (n_37), .B1 (\dn[4] ), .Y (n_58)); XNOR2XLTH g1999(.A (n_47), .B (\up[3] ), .Y (n_97)); XNOR2XLTH g2000(.A (n_46), .B (\dn[3] ), .Y (n_99)); NAND2BXLTH g2001(.AN (n_47), .B (\up[3] ), .Y (n_57)); NAND2BXLTH g2002(.AN (n_46), .B (\dn[3] ), .Y (n_56)); AOI21XLTH g2003(.A0 (\up[2] ), .A1 (n_43), .B0 (n_52), .Y (n_55)); AOI22XLTH g2004(.A0 (n_50), .A1 (n_45), .B0 (\K[4] ), .B1 (n_4), .Y (n_54)); AOI22XLTH g2005(.A0 (n_49), .A1 (n_42), .B0 (\K[4] ), .B1 (n_0), .Y (n_53)); DEPARTMENT OF ECE, BMSCE Page 75 Implementation of All Digital Phase Locked Loop AOI2BB1XLTH g2006(.A0N (n_43), .A1N (\up[2] ), .B0 (n_103), .Y (n_52)); OAI221XLTH g2007(.A0 (n_10), .A1 (n_91), .B0 (n_8), .B1 (n_92), .C0 (n_44), .Y (n_51)); OAI2B11XLTH g2008(.A0 (\dn[1] ), .A1N (\K[1] ), .B0 (n_41), .C0 (n_26), .Y (n_50)); OAI2B11XLTH g2009(.A0 (\up[1] ), .A1N (\K[1] ), .B0 (n_40), .C0 (n_25), .Y (n_49)); AOI32XLTH g2010(.A0 (n_22), .A1 (n_15), .A2 (n_33), .B0 (\up[6] ), .B1 (n_9), .Y (n_48)); XNOR2XLTH g2011(.A (n_24), .B (\dn[2] ), .Y (n_84)); XNOR2XLTH g2012(.A (n_23), .B (\up[2] ), .Y (n_78)); NAND2BXLTH g2013(.AN (n_23), .B (\up[2] ), .Y (n_47)); OR2XLTH g2014(.A (n_24), .B (n_8), .Y (n_46)); OAI211XLTH g2015(.A0 (\dn[3] ), .A1 (n_20), .B0 (n_34), .C0 (n_19), .Y (n_45)); OAI21XLTH g2016(.A0 (n_36), .A1 (\dn[0] ), .B0 (n_28), .Y (n_44)); OAI21XLTH g2017(.A0 (n_21), .A1 (n_104), .B0 (n_38), .Y (n_43)); OAI211XLTH g2018(.A0 (\up[3] ), .A1 (n_20), .B0 (n_35), .C0 (n_19), .Y (n_42)); OAI211XLTH g2019(.A0 (n_2), .A1 (\K[1] ), .B0 (n_86), .C0 (\K[0] ), .Y (n_41)); OAI211XLTH g2020(.A0 (n_1), .A1 (\K[1] ), .B0 (n_80), .C0 (\K[0] ), .Y (n_40)); NOR3BXLTH g2021(.AN (n_17), .B (n_6), .C (n_89), .Y (n_39)); OAI2BB1XLTH g2022(.A0N (n_104), .A1N (n_21), .B0 (\up[1] ), .Y (n_38)); NOR2BXLTH g2023(.AN (n_17), .B (n_90), .Y (n_37)); OAI21XLTH g2024(.A0 (n_2), .A1 (n_93), .B0 (n_94), .Y (n_36)); OAI21XLTH g2025(.A0 (n_14), .A1 (\K[3] ), .B0 (n_7), .Y (n_35)); OAI21XLTH g2026(.A0 (n_10), .A1 (\K[3] ), .B0 (n_8), .Y (n_34)); OAI22XLTH g2027(.A0 (n_12), .A1 (n_100), .B0 (n_0), .B1 (n_101), .Y (n_33)); OAI22XLTH g2028(.A0 (n_12), .A1 (\K[5] ), .B0 (n_0), .B1 (\K[4] ), .Y (n_32)); OAI22XLTH g2029(.A0 (n_6), .A1 (\K[5] ), .B0 (n_4), .B1 (\K[4] ), .Y (n_31)); AOI22XLTH g2030(.A0 (n_6), .A1 (\K[5] ), .B0 (\K[6] ), .B1 (n_11), .Y (n_30)); AOI22XLTH g2031(.A0 (n_12), .A1 (\K[5] ), .B0 (\K[6] ), .B1 (n_5), .Y (n_29)); AOI22XLTH g2032(.A0 (n_2), .A1 (n_93), .B0 (n_92), .B1 (n_8), .Y DEPARTMENT OF ECE, BMSCE Page 76 Implementation of All Digital Phase Locked Loop (n_28)); AOI22XLTH g2033(.A0 (n_4), .A1 (n_90), .B0 (n_91), .B1 (n_10), .Y (n_27)); AOI22XLTH g2034(.A0 (n_8), .A1 (\K[2] ), .B0 (\K[3] ), .B1 (n_10), .Y (n_26)); AOI22XLTH g2035(.A0 (n_7), .A1 (\K[2] ), .B0 (\K[3] ), .B1 (n_14), .Y (n_25)); OAI22XLTH g2036(.A0 (n_86), .A1 (\dn[1] ), .B0 (n_2), .B1 (\dn[0] ), .Y (n_85)); OAI22XLTH g2037(.A0 (n_80), .A1 (\up[1] ), .B0 (n_1), .B1 (\up[0] ), .Y (n_79)); NAND2XLTH g2038(.A (\dn[0] ), .B (\dn[1] ), .Y (n_24)); NAND2XLTH g2039(.A (\up[0] ), .B (\up[1] ), .Y (n_23)); NAND2XLTH g2040(.A (n_95), .B (n_5), .Y (n_22)); AND2X1TH g2041(.A (n_80), .B (n_105), .Y (n_21)); NOR2XLTH g2042(.A (\K[3] ), .B (\K[2] ), .Y (n_20)); NAND2XLTH g2043(.A (\K[3] ), .B (\K[2] ), .Y (n_19)); AND2X1TH g2044(.A (n_6), .B (n_89), .Y (n_18)); NAND2XLTH g2045(.A (n_88), .B (n_11), .Y (n_17)); INVX1TH g2046(.A (n_15), .Y (n_16)); NAND2XLTH g2047(.A (n_100), .B (n_12), .Y (n_15)); INVX2TH g2048(.A (\up[3] ), .Y (n_14)); INVX2TH g2049(.A (\up[0] ), .Y (n_80)); INVX1TH g2050(.A (\up[7] ), .Y (n_13)); CLKINVX2TH g2051(.A (\up[5] ), .Y (n_12)); INVX2TH g2052(.A (\dn[6] ), .Y (n_11)); INVX2TH g2053(.A (\dn[3] ), .Y (n_10)); INVX1TH g2054(.A (n_95), .Y (n_9)); INVX2TH g2055(.A (\dn[2] ), .Y (n_8)); INVX2TH g2056(.A (\up[2] ), .Y (n_7)); CLKINVX2TH g2057(.A (\dn[5] ), .Y (n_6)); INVX2TH g2058(.A (\up[6] ), .Y (n_5)); INVX2TH g2059(.A (\dn[0] ), .Y (n_86)); INVX2TH g2060(.A (\dn[4] ), .Y (n_4)); CLKINVX2TH g2061(.A (\K[6] ), .Y (n_3)); INVX2TH g2062(.A (\dn[1] ), .Y (n_2)); INVX2TH g2063(.A (\up[1] ), .Y (n_1)); INVX2TH g2064(.A (\up[4] ), .Y (n_0)); SDFFQX1TH \dn_reg[0] (.CK (Kclk), .D (\dn[0] ), .SI (n_116), .SE (dnup), .Q (\dn[0] )); SDFFQX1TH \dn_reg[1] (.CK (Kclk), .D (\dn[1] ), .SI (n_114), .SE (dnup), .Q (\dn[1] )); SDFFQX1TH \dn_reg[7] (.CK (Kclk), .D (\dn[7] ), .SI (n_108), .SE (dnup), .Q (\dn[7] )); SDFFQX1TH \up_reg[0] (.CK (Kclk), .D (n_124), .SI (\up[0] ), .SE (dnup), .Q (\up[0] )); SDFFQX1TH \up_reg[1] (.CK (Kclk), .D (n_123), .SI (\up[1] ), .SE (dnup), .Q (\up[1] )); DEPARTMENT OF ECE, BMSCE Page 77 Implementation of All Digital Phase Locked Loop SDFFQX1TH \up_reg[2] (.CK (Kclk), (dnup), .Q (\up[2] )); SDFFQX1TH \dn_reg[2] (.CK (Kclk), (dnup), .Q (\dn[2] )); SDFFQX1TH \up_reg[3] (.CK (Kclk), (dnup), .Q (\up[3] )); SDFFQX1TH \up_reg[4] (.CK (Kclk), (dnup), .Q (\up[4] )); SDFFQX1TH \up_reg[5] (.CK (Kclk), (dnup), .Q (\up[5] )); SDFFQX1TH \up_reg[6] (.CK (Kclk), (dnup), .Q (\up[6] )); SDFFQX1TH \dn_reg[3] (.CK (Kclk), (dnup), .Q (\dn[3] )); SDFFQX1TH \dn_reg[4] (.CK (Kclk), (dnup), .Q (\dn[4] )); SDFFQX1TH \up_reg[7] (.CK (Kclk), (dnup), .Q (\up[7] )); SDFFQX1TH \dn_reg[5] (.CK (Kclk), (dnup), .Q (\dn[5] )); SDFFQX1TH \dn_reg[6] (.CK (Kclk), (dnup), .Q (\dn[6] )); endmodule .D (n_122), .SI (\up[2] ), .SE .D (\dn[2] ), .SI (n_113), .SE .D (n_121), .SI (\up[3] ), .SE .D (n_120), .SI (\up[4] ), .SE .D (n_119), .SI (\up[5] ), .SE .D (n_118), .SI (\up[6] ), .SE .D (\dn[3] ), .SI (n_112), .SE .D (\dn[4] ), .SI (n_111), .SE .D (n_117), .SI (\up[7] ), .SE .D (\dn[5] ), .SI (n_110), .SE .D (\dn[6] ), .SI (n_109), .SE // Generated by Cadence Encounter(R) RTL Compiler v08.10-s121_1 module DCO(IDclk, carry, borrow, u2); input IDclk, carry, borrow; output u2; wire IDclk, carry, borrow; wire u2; wire borrowH, borrowL, carryH, carryL, n_0, n_1, n_3, n_4; wire n_5, n_6, toggleFF; assign carryL = 1'b0; assign carryL = 1'b1; assign borrowL = 1'b0; assign borrowL = 1'b1; assign carryH = 1'b1; assign borrowH = 1'b1; DFFQXLTH borrowH_reg(.CK (IDclk), .D (n_6), .Q (borrowH)); SDFFQX1TH carryH_reg(.CK (IDclk), .D (carryH), .SI (n_1), .SE (n_4), .Q (carryH)); NOR2XLTH g348(.A (toggleFF), .B (n_5), .Y (n_6)); AOI21XLTH g349(.A0 (n_3), .A1 (borrowL), .B0 (borrowH), .Y (n_5)); NOR2XLTH g350(.A (toggleFF), .B (n_3), .Y (n_4)); SDFFQX1TH toggleFF_reg(.CK (IDclk), .D (n_0), .SI (borrowH), .SE (toggleFF), .Q (toggleFF)); NOR2XLTH g352(.A (carryH), .B (carryL), .Y (n_3)); NOR2XLTH g353(.A (toggleFF), .B (IDclk), .Y (u2)); OR2XLTH g354(.A (toggleFF), .B (n_0), .Y (n_1)); DEPARTMENT OF ECE, BMSCE Page 78 Implementation of All Digital Phase Locked Loop INVXLTH g355(.A (carryH), .Y (n_0)); Endmodule // Generated by Cadence Encounter(R) RTL Compiler v08.10-s121_1 module Divider(u21, u22); input u21; output u22; wire u21; wire u22; wire \clkdiv[0] , \clkdiv[1] , \clkdiv[2] , n_0, n_1, n_2, n_3, n_4; wire n_5, n_6; DFFTRXLTH \clkdiv_reg[3] (.CK (u21), .D (n_5), .RN (n_6), .Q (u22), .QN ()); DFFTRXLTH \clkdiv_reg[0] (.CK (u21), .D (n_6), .RN (n_0), .Q (\clkdiv[0] ), .QN (n_0)); DFFTRXLTH \clkdiv_reg[1] (.CK (u21), .D (n_6), .RN (n_1), .Q (\clkdiv[1] ), .QN ()); DFFTRXLTH \clkdiv_reg[2] (.CK (u21), .D (n_6), .RN (n_3), .Q (\clkdiv[2] ), .QN ()); XNOR2XLTH g66(.A (n_4), .B (u22), .Y (n_5)); NAND2BXLTH g67(.AN (n_4), .B (u22), .Y (n_6)); XNOR2XLTH g68(.A (n_2), .B (\clkdiv[2] ), .Y (n_3)); NAND2BXLTH g69(.AN (n_2), .B (\clkdiv[2] ), .Y (n_4)); XNOR2XLTH g70(.A (\clkdiv[1] ), .B (n_0), .Y (n_1)); NAND2XLTH g71(.A (\clkdiv[1] ), .B (\clkdiv[0] ), .Y (n_2)); endmodule DEPARTMENT OF ECE, BMSCE Page 79