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CURRICULUM VITAEKeshab K. Parhi Email: [email protected] http://www.ece.umn.edu/users/parhi EDUCATION • Ph.D., Electrical Engineering and Computer Sciences, University of California, Berkeley, September 1988, Research Advisor: Prof. David G. Messerschmitt. THESIS: Algorithm and Architecture Designs for High-Speed Digital Signal Processing • M.S.E.E., Univ. of Pennsylvania, Philadelphia, May 1984, Concentrated on signal processing and VLSI IC design. Research Advisor: Prof. Raymond S. Berkowitz. THESIS: Application of Importance Sampling for False Alarm Setting in Complex MultiDimensional Signal Processing Systems • B.Tech. (Honors), Indian Institute of Technology, Kharagpur, India, May, 1982, Electrical Engineering. THESIS: Design of a Machine To Compute Complexity of Algorithms INDUSTRIAL AND ACADEMIC EXPERIENCE • Professor (Tenured), Department of Electrical Engineering, University of Minnesota, Minneapolis, MN, 55455 (starting July 1995). Edgar F. Johnson Professor (Starting July 1997). Distinguished McKnight University Professor (Starting July 2000). Associate Professor with Tenure (July 1992 - June 1995), Assistant Professor (Oct. 1988 - June 1992), Research efforts directed towards VLSI Architectures for Digital Signal Processing with Applications to Wireless and Video Processing, VLSI Digital Filters, Adaptive Filters and Beamformers, Video Compression, Error Control Coders, Cryptography, Computer Arithmetic, Low-Power Digital Systems, CAD for Low-Power, Digital IC Design and FPGA System Prototyping. Current research is also directed towards biomedical signal processing and signal classification, particularly with the use of machine learning techniques. • President, Leanics Corporation, 2005-present • Medtronic, Inc., Minneapolis, MN, 2006-2007, on Sabbatical Leave • Broadcom Corp., Irvine, (2000-2002), Senior Principal Scientist and Technical Director DSP Systems, Office of CTO (on Leave ) • Technical Advisory Board, Morphics, Inc. (2002-2003) • Visiting Professor, Lund Univ., Sweden (April 1999) July 7, 2012 • Visiting Researcher, NEC C&C Laboratories, Kanagawa, Japan (1996-7 Academic Year, on Leave as National Science Foundation Fellow) • Visiting Professor, Delft Univ., The Netherlands (March - April, 1996) • Associate Professor (Tenured), Department of Electrical Engineering, University of Minnesota, Minneapolis, (July 1992 - June 1995). • Assistant Professor, Department of Electrical Engineering, University of Minnesota, Minneapolis, (October 1988 - June 1992). • Visiting Researcher, NEC C&C Laboratories, Kanagawa, Japan (April 1992 - June 1992), Researched VLSI Architectures for Discrete Wavelet Transforms. • Consultant to Dorsey and Whitney (2007), Theseus Logic (1996-1999), United Nations Development Program (1995), Top-Vu Technology, Inc. (1994) US West Advanced Technologies (1989), Bell Labs (1987 - 1988), • Summer Job at AT&T Bell Laboratories, Holmdel, NJ during Summer 1987. • Summer job at the IBM T.J. Watson Research Center, Yorktown Heights, NY, during Summer 1986. AWARDS AND HONORS • IEEE Charles A. Desoer Technical Achievement Award, IEEE Circuits and Systems Society (2012) • Frederick Emmons Terman Award from American Society of Engineering Education (2004) • ACM Great Lakes Symp. Best (Student) Paper Award, 2004 • IEEE Kiyo Tomiyasu Technical Field Award (2003) • IEEE W.R.G. Baker Best Paper Award (2001) • Distinguished McKnight University Professorship (2000-) • IEEE Circuits and Systems Society Golden Jubilee Medal (1999) • Judge, IEEE Fellow Selection Committee (1998-2000) • Fellow, IEEE (1996) • Best Paper Award at 33rd Design Automation Conference, June 1996 • IEEE Circuits and Systems Society Distinguished Lecturer (1994-1999) • Darlington Best Paper Award of the IEEE Circuits and Systems Society, 1994 • Guillemin-Cauer Best paper Award of the IEEE Circuits and Systems Society, 1993 • National Science Foundation Young Investigator Award, 1992-1997 • McKnight - Land Grant Professorship at the Univ. of Minnesota, 1992 - 1994 • IEEE Signal Processing Society Paper Award, 1991, • IEEE Browder J. Thompson Memorial Prize paper Award, 1991 • NSF Research Initiation Award, 1989 • Listed in Marquis’ Who’s Who in the American Education, World, Science and Engineering, Finance and Business • Eliahu Jury Award (for excellence in systems research), 1987, U.C. Berkeley • Demetri Angelakos Award (for altruistic activities afforded fellow graduate students), 1987, U.C. Berkeley • IBM Graduate Fellowship, 1987-88 • U.C. Regents Fellowship, 1986-87 440.856. ”Low-Error Fixed-Width Modified Booth Multiplier”. ”Low-Latency Architectures for High-Throughput Viterbi Decoders”. Parhi. K. October 23.239. Patent Number 6. US Patent 7. 2006 12.K. W. Issued May 17.Issued Patents 1.333. U. Parhi. ”Area-Efficient Parallel Turbo Decoding”.010.271. ”LDPC Code and Encoder/Decoder Regarding Same”. Parhi. Parhi.892. 2008 .A.K. Issued July 3.907. ”Fast Parallel cascaded Array Modular Multiplier”. K.K.215. 2007 14.K. US Patent 7. 2007 15.K. October 16. Parhi and J. 2007 13. and K. Parhi. Zhang and K. Chung and S. Freking and K. 10.-G. 2001 3.895. 2006 10. US Patent 7. J. R. R. ”Concurrent Method for Parallel Huffman Compression Coding and Other Variable Length Encoding and Decoding”. Issued July 18.K. 2005 5.545. Patent Number 6.-M. and Applications there of”.K. Z. 2005 7. US Patent 7. ”Pipelined Add-Compare-Select Circuits and Methods. Freking and K.978. Issued March 28. K.831. Kong. K.308.A. Freking and K.115.J.K. 2005 8. Parhi. U.580.G.197. ”System and Method for Generating Cyclic Codes for Error Control in Digital Communications”.640.S. ”Systolic Cylindrical Array Modular Multiplier”. US Patent 7. Issued December 11. US Patent 7. Freking and K. K. Parhi.120. Parhi.S.K. R.304. Parhi.307.489.080. Parhi. U. 2005 6. Chung.S. Parhi.561. ”Pipelined Parallel Processing of Feedback Loops in a Digital Circuit”. J. K. 2006 9. W. Issued May 10.K. Wang and K. Parhi. ”Fast and Small Serial Variable Length Encoder with an Optimally High Rate for Encoding Including Huffman Encoding”. Freking and K.K. ”Fast and Small Serial Huffman Decoder for Decoding at an Optimally High Rate”.K. Patent Number 6. W. August 7. Issued April 3.020. US Patent 7.200.K. Cho. 2006 11. Issued Oct. 19. US Patent Number 6. ”Pipelining of Multiplexor Loops in a Digital Circuit”. U. Patent Number 6. US Patent Numbber 6. ”Systolic Ring Planarized Cylindrical Array Modular Multiplier”. Parhi. 2001 4.S. Freking and K.426. Issued June 14. US Patent Number 6. Kim.689. ”Low-Error Canonic-Signed-Digit Fixed-Width Multiplier.K. and Method for Designing Same”. 2001 2.A. Issued December 20. T. US Patent 7.K. Issued March 7.652. Issued Feb. K. Parhi.799. ieee. C. A. Parhi. ”Low-Complexity Hybrid LDPC Code Encoder”. ”High-Speed Precoders for Communications Systems”.ieee. 2011 24. 2.ieee.233. Issued April 26. US Patent 7. Parhi and Y. Lutkemeyer. ”DSP Based Equalization for Optical Channels”. K.693.-G. Us Patent 7. Parhi and Y. Lutkemeyer. K. US Patent 7.769. C. Wakayama.E. hatamian. K. Issued July 14.K. Y.823. March 2000.K. K. Agazzi. ”Pipelining Tomlinson Harashima Precoders”. K. K.K. Lee.K.A.K.org/groups/802/3/ae/public/mar00/parhi 1 0300. Issued August 30. K.K.200.” US Patent 7. and R. K.K.K. Parhi.K. ”System and Method for MIMO Equalization for DSP Transceivers”. http://grouper. 2010 22. 2011 IEEE 802.3 Standards Presentations 1.ieee. ”System and Method for Designing RS Based LDPC Code Decoder”. 2010 20.K.009. Issued April 6. Gu. ”Parallel Implementation of the DSP Functions of the PAM-5 10 Gb/s Transceiver”. J. ”Low-Error Fixed-Width Modified Booth Multiplier. A. Kim.pdf . Chan. Ungerboeck.H. Parhi. K.561.099. Issued Feb. Parhi and Y. Cho. K. Phanse. Parhi and Y.org/groups/802/3/ae/public/sep00/agazzi 1 0900. US Patent 7. Abnous and M.816. Parhi. 19.-J.341. K. 2009 19. Issued August 3. US Patent 7.pdf 3. Gu.334. Feb. Issued May 11.pdf 2. O.org/groups/802/3/10GBT/public/jul03/parhi 1 0703. 2008 17.539.K.933. Gu . K.K. Parhi.pdf 4. P. Parhi. Parhi. and M. Liu. Cohen and K. Kota.M. ”Parallel Tomlinson Harashima Precoders”. 2009 18.E. ”System and method for generating cyclic codes for error control in digital communications”. US Patent 7716553.633.16. Gopinathan. Gu and K.T. ”Interleaved Trellis Coded Modulation and Decoding”. ”System and Method for Low-Power Echo and NEXT Cancellers”.org/groups/802/3/an/public/sep04/parhi 1 0904. Parhi and Y. Chung. 2010 21. Agazzi. G. ”System and method for high speed communications using digital signal processing”. http://grouper. V. Gu. 2010 23.918. http://grouper. K. Vorenkamp.-C. O. A. http://grouper. US Patent 7. Issued May 26. S. K. K.657. Gu. Parhi. IEEE 802 Plenary meeting. US Patent 8. R. Parhi. Chung and K. Elsevier Science Publisher. Monterey. Oct. 370-384 (Chapter 17. 3-14 9. K. CRC Press. (Chapter 12) in VLSI Implementations for Image Communications. Parhi. VLSI Digital Signal Processing Systems: Design and Implementation. Parhi. Parhi. pp.K. Taylor.1) 12. pp. Amsterdam. CA. IEEE Computer Society Press.K. in VLSI Signal Processing III.-G. ”VLSI For Signal Processing: Special Architectures”. Parhi. Kluwer Academic Publishers. Hartley. Chapter 1. Nov.K. 1988. Netherlands).K. K. Nishitani and K. ”Parallel Processing and Pipelining in Huffman Decoder”.K. ”A High Sample Rate Recursive Filter Chip”. T. in VLSI Signal Processing V. 1999 Book Chapters 8. IEEE Press. Shanbhag. Nishitani. Parhi. of the Fifth IEEE VLSI Signal Processing Workshop. Section 17. and V. Wiley. Oct. Parhi. Parhi. and K.K. 1995 4.Books 1.. of the Third IEEE VLSI Signal Processing Workshop). (Proc. and G. 114-122 . Kluwer Academic Publishers. J. 1995 3. Dorf. Parhi. of the sixth IEEE VLSI Signal Processing Workshop. 257-266 10. IEEE Press. 1993. Parhi.K. Digit-Serial Computation. J. K. Architectures. IEEE Press. pp. and Processors. N. Proceedings 1996 International Conference on Application Specific Systems. 1993 (Proc. K. Hatamian. NY 1999 7.R. Parhi and T. IEEE Press. in The Electrical Engineering Handbook. 1996 6. 2. Kluwer Academic Publishers.. and K. pp. K. Ed. 1996 5. Fortes.I. Pipelined Adaptive Digital Filters.K. ”A Concurrent Loss-Less Coder for Video Compression”. NY. N.K. Ed. Series Advances in Image Communications (Edited by Peter Pirsch). Veldhoven. pp.. 1994 2. R. 1992 (Proc. VLSI Signal Processing VIII. Shanbhag. ed. Marcel Dekker. ”VLSI Implementation of a 100 MHz Pipelined ADPCM Codec Chip”. CA). in VLSI Signal Processing VI. K. and K. Napa Valley. 365-395 11. Parhi.K.K. Shrimali. Digital Signal processing for Multimedia Systems. Vol. C. Pipelined Lattice and Wave Digital Recursive Filters. edited by Richard C. 1993. and M. Mongenet. K. 13. Oct.K. of the 1996 IEEE Workshop on VLSI Signal Processing. pp. L. Kluwer Academic Press. Parhi. 615-627. Parhi.K. 306-315. 589-601. ”Video Compression”. October 1995 (Proc. in VLSI Design Methodologies for Digital Signal Processing Architectures. N. Edited by R. New York. K. edited by M.Y. and K. Parhi. pp. 1995 17. IEEE Press (ISCAS-96 Tutorial Book) 22. in VLSI Signal Processing VII. Sakai. J. edited by B. Parhi. Parhi and T.. 1994 14. Sakai. S. Jain and K. Satyanarayana. October 1995 (Proc.1 in Microsystems Technology for Multimedia Applications: An Introduction. of the Seventh IEEE VLSI Signal Processing Workshop. in VLSI Signal Processing IX. 1999 . 189-198. of the 1995 IEEE Workshop on VLSI Signal Processing. Catthoor.”Systematic Design of Architectures for M-ary Tree-Structured Filter Banks”. IEEE Press. in VLSI Signal Processing VII. Parhi. IEEE Press. 169-205. Wang.K. 501-510. IEEE Press. 207-216. Nishitani.C. Parhi. Cavin and W.K. in VLSI Signal Processing VIII. 447-507. IEEE Press. La Jolla. ”Efficient Power Based Galois Field Arithmetic Architectures”. 1994 (Proc. ”Pipelined Wave Digital Filter Design for Narrow-Band Sharp-Transition Digital Filters”. pp. Parhi.-G. 1995 18. Chapter 2 in Digital Signal Processing for Multimedia Systems. 1994 (Proc. ”Pipelined Adaptive Digital Filters”. ”High-Level Transformations for DSP Synthesis”. IEEE Press.2 in Microsystems Technology for Multimedia Applications: An Introduction. pp.K. Edited by K. Montalvo. pp. K. IEEE Press. 1995 19. K. ”The MARS High-Level DSP Synthesis System”. Parhi. ”Estimation of Average Energy Consumption of Ripple-Carry Adder Based on Maximum Average Carry Chains”. in VLSI Signal Processing VIII.K. Wei. Parhi. Chapter 8.H. ”High-Level DSP Synthesis”. 575-587.K. Sheu et al. K. Oct. June 1997 (ISCAS-97 Tutorial Book) 24. ”Design of High-Performance DSP Systems”. CA) 16. ”Low-Power Digital VLSI Approaches”. Sheu et al. pp. pp.-Y. C.. Chapter in Circuits and Systems in the Information Age. T.K. Chung and K. IEEE Press. Japan) 20. CA) 15. La Jolla. pp. Chapter 8. pp. K. Marcel Dekker. October 1996 (Proc. San Francisco) 23. of the 1995 IEEE Workshop on VLSI Signal Processing. IEEE ISCAS-95 Tutorial Book. Sheu et al.”Register Minimization in Cost-Optimal Synthesis of DSP Architectures”. edited by B. Liu. Chapter in Emerging Technologies: Designing Low-Power Digital Systems.K. pp. Chapter 8. Denk and K. pp. Parhi.R. Wang and K. Huang and C.K. K. C. Edited by Y. Parhi.K. Japan) 21. 3-22. IEEE Press. IEEE ISCAS-95 Tutorial Book. pp. of the Seventh IEEE VLSI Signal Processing Workshop.4 in Microsystems Technology for Multimedia Applications: An Introduction.K. Shanbhag and K. edited by B. Bayoumi. 17-41.. IEEE Press.K. and J. Parhi and F. Ito and K. 157-166. IEEE ISCAS-95 Tutorial Book. New York. 1999 27. June 1989. Vol. pp. H. New York. Chapter 21 in Digital Signal Processing for Multimedia Systems.K. 2010 32. Springer Science+Business Media LLC. Parhi. ”Concurrent Cellular VLSI Adaptive Filter Architectures”. 589-621.F. 551-587.K. on Circuits and Systems. Chapter 19 in Digital Signal Processing for Multimedia Systems. Apolinario. ”Power Estimation Approaches”. 1141-1151 34. L. Parhi. Parhi and T.H. Messerschmitt.E. pp. Edited by J. pp.K. E. Parhi and T. Parhi and T. Jr. pp. pp. Marcel Dekker. 1558-1563 35. IEEE Transactions of Circuits and Systems. pp. Raghunath and K. Deprettere. ”Signal Flow Graphs and Data Flow Graphs”. New York. Patil. ”Wavelet VLSI Architectures”. 329-353. J. pp. K. Song and K. Edited by K. 1999 26. CAS-34. New York. 791-816. Parhi and D. Nishitani.K. Takala. 12. December 1987. Chapter 13 in Digital Signal Processing for Multimedia Systems. CAS-34.K.C. Edited by K.K. 1999 30. ”Speaker Identification over Narrowband VoIP Networks”.. Handbook of Signal Processing Systems. Ma and K. Parhi and Y. Marcel Dekker. and D.S. 741-772. pp. ”Finite Field Arithmetic Architectures”. pp. Parhi. October 1987.J. Denk and K. A. H. Leupers and J. 2011 Journal Publications 33. Parhi and T.25. pp. No.K.A.K. Springer-Verlag.K. 269-297. Parhi. Vol. R. Marcel Dekker. 125-151. Chapter 25 in Digital Signal Processing for Multimedia Systems. Vol. Bhattacharyya. Cohen. T. Neustein and H. Nishitani.K. pp. K. ”Pipelined RLS for VLSI: STAR-RLS Filters”. Nishitani.P. No. 519-550.K. 813-829 . Nishitani. K. Chapter 20 in Digital Signal Processing for Multimedia Systems. Parhi and R. Berkowitz. 2009 31.K. New York. K. 1999 29. Parhi. ”On Optimizing Importance Sampling Simulations”.G. Chapter 6 in Advances in Forensic Speaker Recognition: Criminal Justice and Counterterrorism.K. IEEE Transactions on Circuits and Systems. ”On Pipelined Implementations of QRD-RLS Adaptive Filters”. ”Division and Square-Root”. 10. CAS-36(6). Chapter in QRD-RLS Adaptive Filters. 1999 28.K. Patil. Edited by K. Edited by K.K. Parhi. Marcel Dekker. Springer-Verlag.R. Edited by S.G. Edited by K. and K. ”Concurrent Architectures for Two-Dimensional Recursive Digital Filtering”. IEEE Trans. Nishitani.A. J. Parhi and T. Srinivas and K. Edited by A. Vol. 4. Marcel Dekker. K.K.S. Parhi. Satyanarayana and K. Messerschmitt. Chen. Parhi. K. pp. pp. K. Asian Scientific Information Bulletin of the Office of Naval Research Office. Parhi. ”A Systematic Approach for Design of Digit-Serial Signal Processing Architectures”. ”Technology for the 90s: VLSI Signal and Image Processing Systems”. 175-183 48. Vol. 7. on Signal Processing. ”Pipeline Interleaving and Parallelism in recursive Digital Filters. July 1989. 178-195 40.Y. pp.K. ”Pipelining In Dynamic Programming Architectures”. Parhi.G.K. on Circuits and Systems. Speech. IEEE Trans. Parhi.G. 93-98 46. 39.K. 6. and Signal Processing. 1. IEEE Transactions on Acoustics. Messerschmitt. and D. Vol. June 1991. Vol. No. July 1991. February 1992. ”An 85-MHz Fourth-Order Programmable IIR Digital Filter Chip”. 16(4). Messerschmitt. Part II: Pipelined Incremental Block Filtering”. 38. IEEE Journal of Solid State Circuits. Parhi. 16-17 45. 745-754 44. 6. 1992. pp. IEEE Transactions on Acoustics. No. No. ”Pipeline Interleaving and Parallelism in recursive Digital Filters.K. 37(7).K. 7(4). on Circuits and Systems.K. No. Vol. Speech. 2/3. K. No. M. Parhi. 4. Messerschmitt. 1450-1454 43. Proceedings of the IEEE. No. June 1991. 38. Wang. K. IEEE Trans. July 1989. Vol. and Signal Processing. 1442-1450 42. Special Issue on Supercomputer Technology. Vol. 1099-1117 37.R. IEEE Trans.K. 37(7). October . A. K. 40(2). K. Parhi. H. Parhi.K.K. No. C.K.P. Vol. pp. IEEE Journal of Solid State Circuits. 1118-1135 38. and D. 77(12). Parhi. pp. K.K. 39.G. pp. pp. 1879-1895 39.36. pp. 4. 29-43 47. December 1989. 27. ”Finite Word Effects in Pipelined Recursive Filters”. 2. January 1992.December 1991. K. ”Pipelining in Algorithms with Quantizer Loops”. Journal of VLSI Signal Processing. K. February 1991. on Signal Processing. 177-198 . Hatamian and K. pp. Vol. and K. 27. Part I: Pipelining using Scattered Look-Ahead and Decomposition”. Parhi. K. Parhi. pp. ”Algorithm Transformation Techniques for Concurrent Processors”. Vol. ”High-Speed VLSI Arithmetic Processor Architectures Using Hybrid Number Representation”. IEEE Trans. 358-375 41. IEEE Circuits and Devices Magazine (special technology forecast issue). ”Synthesis of Control Circuits in Folded Pipelined DSP Architectures”. K. ”Research on VLSI For Digital Video Systems in Japan”. K. pp. Brown. April 1991. Parhi. Parhi. IEEE Trans. pp. Parhi.K. on Computers. Vol. Vol. and D. July 1991 (invited article). Srinivas. ”Static Rate-Optimal Scheduling of Iterative Data Flow Programs via Optimum Unfolding”. N.K. Parhi. Ganesan. F.49. on Signal Processing. 1925-1939 55. July 1992.K.H. IEEE Transactions on Signal Processing. Shanbhag. May 1993. Vol. 385-391 51. 347-349 54. K. 1063-1068 58.-G. 6. 43(1). Vol. and T. pp. 1178-1189. ”High-Speed VLSI Architectures for Huffman and Viterbi Decoders”. Shanbhag. Vol. Parhi. IEEE Transactions on Circuits and Systems. ”A Fast VLSI Adder Architecture”.R. N. Parhi. No. 7. IEEE Transactions on Signal Processing. Srinivas. ”Relaxed Look-Ahead Pipelined LMS Adaptive Filters and Their Application to ADPCM Coder”. No. No. and K. N. pp.K. Shanbhag. Lucke. April 1994 61. 2. 1(2). 751-761. June 1993. IEEE Transactions on Circuits and Systems For Video Technology. January 1994 60. IEEE Transactions on Signal Processing. June 1992.K. Part II: Analog and Digital Signal Processing.R. on Circuits and Systems. IEEE Trans. L. 40(12). 191-202 57. K. K.K. Nishitani.K. K. on VLSI Systems.K.R. and K. J. ”Pipelining of Lattice IIR Digital Filters”. Part II: Analog and Digital Signal Processing. pp. L. ”A Pipelined Adaptive Differential Vector Quantizer for Low-Power Speech Coding Applications”. 42(4). July 1993. and K. 27. and K. and K. Lucke. Parhi. June 1992. and K. N. K. and K. 761-767 50. K. Parhi. 42(5). pp.K. May 1993. IEEE Trans. pp. 255-267 52. No. Raghunath. 1956-1961 56. IEEE Trans. and K.E. 39. 104-109. ”Parallel Processing Architectures for Rank-Order and Stack Filters”. pp. 12(7).R. Vol. pp. H. 5. pp. pp. ”Finite Precision Analysis of the ADPCM Coder”. 423-440 53. pp.R. 364-368. 41(5). IEEE Transactions on Circuits and Systems. May 1993. ”Parallel Adaptive Decision Feedback Equalizers”. IEEE Journal of Solid State Circuits. Wu. and K. IEEE Transactions on Circuits and Systems-Part II: Analog and Digital Signal Processing. on Circuits and Systems. Parhi.J. pp. Vol. Parhi. Parhi.E. IEEE Trans. pp. ”Video Data Format Converters Using Minimum Number of Registers”. Parhi. May 1994 . May 1992. ”Sequential and Parallel Neural Network Vector Quantizers”. ”Data-Flow Transformations for Critical Path Time Reduction For High-Level DSP Synthesis”. ”Systematic Synthesis of DSP Data Format Converters using Life-Time Analysis and Forward-Backward Register Allocation”.K.K. pp. May 1994 62. IEEE Transactions on Computer Aided Design of Integrated Circuits And Systems.K. Parhi. Chung. Parhi. Parhi. 41(5). Part II: Analog and Digital Signal Processing. Shanbhag. 753-766 59. Parhi.K. IEEE Transactions on Computers. 39.K.K. Part II: Analog and Digital Signal Processing. and K. 41(5). ”VLSI Architectures for Discrete Wavelet Transforms”. 40(5). 2. Parhi. pp. December 1993. ”A Pipelined Adaptive Lattice Filter Architecture”. Part II: Analog and Digital Signal Processing. August 1994 66. pp.R. 2(4). 41(7). 274-295. pp. ”High-Level DSP Synthesis using Concurrent Transformations. Vinnakota. pp. IEEE Circuits and Systems Transactions . Parhi. 121-143. Parhi. pp. Parhi. Lin. Journal of VLSI Signal Processing. Parhi. IEEE Transactions on Circuits and Systems . ”A Fast Radix-4 Division Algorithm”. Shanbhag. 278-282. Parhi. October 1995 74. 434-436. pp. ”Corrections to ”Finite Precision Analysis of the ADPCM Coder””. June 1996 76. pp. September 1995 73.R. Journal of VLSI Signal Processing. IEEE Transactions on Computers. December 1994 67. and K. Parhi. 2591-2604.K. N.J. Srinivas. and K. 41(6).-G.63. H. ”Pipelined Adaptive DFE Architectures using Relaxed Look-Ahead”. Parhi. Parhi. pp.Part II: Analog and Digital Signal Processing. Adams III. B. on VLSI Systems. 44(6). June 1995 71. J.K. 14(3).K. ”High-Level Algorithm and Architecture Transformations for DSP Synthesis”. and K. and K.C. Kim and K. and K.K. 38. Signal Processing.-G. IEEE Transactions on Signal Processing.-Y. 42(9). C. IEEE Trans. K. and K. Chung. Srinivas. on Signal Processing.K.K.R. pp.K. 42(4). 44(10). Parhi. Journal of VLSI Signal Processing. K. Raghunath.K. K. Wang. 9(1). Parhi. June 1994 64. and K. Parhi. and Allocation”. 441-453.Part II: Analog and Digital Signal Processing.K. J.K.B. ”Pipelined RLS Adaptive Filtering using Scaled Tangent Rotations (STAR)”. and K. 11(3). ”Calculation of Minimum Number of Registers in Arbitrary Life Time Chart”. 493. ”Lower Bounds on Memory Requirements for Statically Scheduled DSP Programs”. 1368-1385. ”Resource Constrained Loop List Scheduler for DSP Algorithms”. ”Pipelined Lattice WDF Design for Wideband Filters”.K. pp. Parhi. pp. June 1995 72. January 1995 68. 247-264. 43(6). Chung. Ito and K.K. IEEE Trans. 12(3). H. December 1995 75. N. 616-618. Journal of VLSI Signal Processing. Wang. IEEE Transactions on Circuits and Systems-Part II: Analog and Digital Signal Processing. IEEE Trans. Parhi. E. pp. pp.-Y. Coyle. 229-244. T. pp. October 1996 . Parhi.J. C.K. Lucke. G. Denk and K. 472-488. April 1995 70. K. L. L. 75-96.R. July 1994 65. ”A C-Testable Carry-Free Divider”.E. IEEE Transactions on Computer Aided Design. ”Scaled Normalized Lattice Digital Filters”.K. 11(1/2). March 1995 69. 826-831. ”Determining the Minimum Iteration Period of an Algorithm”. Scheduling. Shanbhag. on Circuits and Systems. H. pp. ”Input Compression and Efficient VLSI Architectures for Rank-Order and Stack Filters”. and K. ”Low-Energy Digit-Serial/Parallel Finite Field Multipliers”. Parhi. Majumdar and K. 44(6). 149-166. 129-132. Journal of VLSI Signal Processing. ”Radix-2 Division with Over-Redundant Quotient Selection”. 473-481. pp. Parhi. L. and A. 16(1). Parhi. Jan. ”A Theoretical Approach to Estimation of Bounds on Power Consumption in Digital Multipliers”. Satyanarayana and K. Parhi. 1997 78. ”Low Area/Power Parallel FIR Digital Filter Implementations”. Parhi. Aug. 57-72. 1997 79. 6(1). July 1998 89. Part II: Analog and Digital Signal Processing. IEEE Trans.77. May 1997 80. Fu and K. pp. and L. May 1997 81. Ito and K. Parhi. on Circuits and Systems. 1998 90. ”Exhaustive Scheduling and Retiming of Digital Signal Processing Systems”. Parhi. 44(2). December 1997 85. H. 45(7). March 1998 86. on Circuits and Systems.A. and K.K. S. pp. K. pp. ”Synthesis of Low-Area Data Format Converters”. Guyot.K. on VLSI Systems. Feb. ”VLSI Architectures for Lattice Structure Based Orthonormal Discrete Wavelet Transforms”. June 1998 88. T. Denk and K. Song and K.K. C. 75-92. ”Efficient Semi-Systolic VLSI Architectures for Finite Field Arithmetic”. 85-92. 47(9).J. Song and K. Wang. on Circuits and Systems. Srinivas. Part II: Analog and Digital Signal Processing. 11931209. ”STAR Recursive Least Square Lattice Adaptive Filters”.K. K. Parhi. Parhi. Sept. Denk and K.C. Montalvo. on Computers. Raghunath and K. ”A Generalized Technique for Register Counting and its Application to Cost-Optimal DSP Architecture Synthesis”. pp.K. Part II: Analog and Digital Signal Processing. pp. IEEE Trans. M. Parhi. Parhi. ”New Svoboda-Tung Division”. May 1997 82. 19(3). 45(5). June 1997 83. pp. Journal of VLSI Signal Processing. 1997 84. ”Finite Precision Error Analysis of QRD-RLS and STAR-RLS Adaptive Filters”.Y. 821-838. pp. Y. Chang.K. ”Loop-List Allocation and Scheduling with using Heterogeneous Functional Units”.II: Analog and Digital Signal Processing. L.K. J. 1040-1054.H. 19(2). IEEE Transactions on Communications. Part II: Analog and Digital Signal Processing. Journal of VLSI Signal Processing. Montalvo. K. Part . Sept. Parhi. 101-113. L. Li and K.-N. 45(5). 44(12).K. ”Generalized Multiplication Free Arithmetic Codes”. 243-256.K.R. 45(4).K. pp. 1998 . IEEE Transactions on Circuits and Systems.C. IEEE Transactions on Signal Processing. on Computers. pp. T. April 1998 87.K. Parker and K. pp. Y.K. 504-508. 1014-1020. IEEE Trans. pp. IEEE Trans.K. Journal of VLSI Signal Processing.K. 17(1). 46(1). IEEE Transactions on Circuits and Systems. pp. D. Jain. 497-501. Parhi. B. IEEE Trans. pp. IEEE Trans. K. Parhi. IEEE Trans. T. May 1999 95. Apr. 1998 94. Kim and K. July 2000 . 555-559. on Communications. Shalash and K. Nov. Part-II: Analog and Digital Signal Processing. 47(6). Parhi. Parhi. IEEE Trans. 1585-1596. IEEE Trans. ”Low-Energy CSMT Carry-Generators and Binary Adders”. Parhi. pp. ”High-Performance Digit-Serial Complex Multiplier”. on VLSI Systems. 47(11). A. pp. 1998 93. June 1999 96.K. Y. pp. pp. IEEE Trans. Dec. 21(1).K. ”Synthesis of Folded Pipelined Architectures for Multirate DSP Algorithms”. Parhi. J. K. L.-N. 37-60. Lucke and K. 45(12).K. J. Parhi. June 2000 103.C. on Circuits and Systems. pp.H. A.K. IEEE Trans. ”Angle-Constrained IIR Filter Pipelining for Reduced Roundoff Errors”. Dec. Denk and K. Parhi. 8(2). 1999 97.K. Srinivas and K. Journal of VLSI Signal Processing. Parhi. Ito. ”A 2 Mb/s 256-State 10 mW Rate-1/3 Viterbi Decoder”. Vol. Song. Shalash and K. ”ILP Based Cost-Optimal DSP Synthesis with Module Selection and Data Format Conversion”. April-June 2000 101.E. ”Theoretical Analysis of Word-Level Switching Activity in the Presence of Glitching and Correlation”. Y. pp. J. 2000 100. ”Power Estimation of Digital Datapaths using HEAT Tool”. pp. on VLSI Systems.-N. IEEE Trans. 570-572. Part-II: Analog and Digital Signal Processing. June 2000 104.K. 25(3). 101-110. Nishitani. T. Chang. 1655-1667. pp.C. Parhi. 35. pp. J. ”Hardware/Software Codesign of Finite Field Datapath for Low-Energy Reed-Solomon Codecs”.K.K. 6(4). June 2000 102. Kuroda. H. 8(2). IEEE Journal of Solid State Circuits. K. pp. 148-159. 826-834. 595-607. ”Power-Efficient Folding of Pipelined LMS Adaptive Filters with Applications to Wireline Digital Communications”.K. Denk and K. 1998 92. ”Systematic Design of High-Speed and Low-Power Digit-Serial Multipliers”. on Circuits and Systems. Parhi. on VLSI Systems. Dec.F. pp.K. Parhi. T. 582594. IEEE Trans. Dec.H. pp. IEEE Trans. Y. Chung.K. pp. on Circuits and Systems. IEEE Trans. 1999 98. IEEE Design and Test Magazine. Chang. 17(2). Parhi. 7(4). 450-462.-N. on VLSI Systems. 198-211.R. ”Two-Dimensional Retiming”.G. 2000 99. Parhi. ”Multi-Dimensional Carrierless AM/PM Systems for Digital Subscriber Loops”. I. K.K. ”A Floating Point Radix 2 Shared Division/Square-Root Chip”. Part II: Analog and Digital Signal Processing. H. 6(4). 160-172. Parhi.K. 6. Suzuki and K. Satyanarayana and K. 7(2). Journal of VLSI Signal Processing. Apr.K. IEEE Trans. Chang and K. 199-213. H. Satyanarayana and K. 47(6). L. pp.91. on VLSI Systems. No. Parhi. on VLSI Systems. Satyanarayana and K. Hekstra and E. J. Ma. IEEE Trans. 48(8). Parhi. IEEE Trans. ”Efficient Implementations of Pipelined CORDIC Based IIR Digital Filters using Fast Orthonormal Micro-rotations”. 424-437. on Signal Processing. K. pp. IEEE Trans. Ma. M.F. ”Fast and Exact Transistor Sizing Based on Iterative Relaxation”. ”Performance-Scalable Array Architectures for Modular Multiplication”. V. 2000 108.K. Freking and K. Sapatnekar and K. 734-749. T. October 2001 115. Chi. K. Sep. 2712-2716. Parhi. Parhi. K. on CAD. 50(7). on Signal Processing. 568-581.K. ”A Novel Low-Power Shared Division and Square-Root using the GST Algorithm”. ”Pipelined CORDIC Based Cascade Orthogonal IIR Digital Filters”. 2001 111. pp. 2000 107. 2000 106. Dec.K. 29(3). July 2001 114. Sundararajan and K. Sundararajan. on Circuits and Systems.K. ”Hierarchical Pipelining and Folding of QRD-RLS Adaptive Filters and Its Application to Digital Beamforming”. pp. Feb. IEEE Trans.K. Parhi and E. pp. 48(9). M. pp. 1238-1253. 48(7). May 2001 112. PartII: Analog and Digital Signal Processing. pp. on Circuits and Systems. Kuhlmann and K. IEEE Trans. 661-674.F. 21(5). November 2001 116. Zhang and K. ”Approaches to Low-Power Implementation of DSP Systems”. Nov. on Circuits and Systems. Journal of VLSI Signal Processing Systems. 435-450. 49(2). on Signal Processing. ”Hybrid Annihilation Transformation (HAT) for Pipelining QRD Based Least Square Adaptive Filters”. pp. pp. Parhi. K. Journal of VLSI Signal Processing Systems. 48(10).K.K. 101-116.L. April 2002 117. 2000 109. 365-376. 1503-1519. Parhi. pp.F. pp.105. 209-222. 19(7). on Computers. V. J. Elsevier. Gao and K. 31(2). H. J.K. Parhi. Deprettere. Parhi. IEEE Trans. Journal of Image and Vision Computing. ”VLSI Implementation of Turbo/MAP Decoders”. Part-I: Fundamental Theory and Applications. Parhi. 1214-1224. J. Parhi and E. Parhi and E. July 2001 113.F.K. G. pp. K. 47(12). VLSI Design. Ma and K. Ma. Suzuki and K. IEEE Trans. 2414-2431. 12(3). Zervakis. Part-II: Analog and Digital Signal Processing. Deprettere. Z. pp.K. Part-II: Analog and Digital Signal Processing. Deprettere.K. L. Aug. J. ”Annihilation-Reordering Look-Ahead Pipelined CORDIC Based RLS Adaptive Filters and Their Application to Adaptive Beamforming”. W. ”A Novel Systematic Design Approach for Mastrovito Multipliers over GF(2m )”. Deprettere. ”A Unified Algebraic Transformation Approach for Parallel Recursive and Adaptive Filtering and SVD Algorithms”. IEEE Trans. May 2002 . Z.K. 2001 110. Wang. on Circuits and Systems. pp.E. 47(11). ”Vector Processing of Wavelet Coefficients for Robust Image Denoising”. IEEE Trans. Ma. S.K. Parhi.J. Parhi. Vol. 2002. Nov. on Circuits and Systems. Vol. 119-136. Tenhunen. ”A Low Power Correlator for CDMA Wireless Systems”. on Circuits and Systems: Part-II: Analog and Digital Signal Processing. 530-542. X. Parhi. Z. Wang.K. IEEE Trans. 51(6). August 2003 131. ”Performance Improvement and Implementation Issues of Turbo/SOVA Decoders”. IEEE CAS Magazine. pp. Z. IEEE Trans. IEEE Trans. ”On-Line Extraction of Soft Decoding Information and its Applications in VLSI Turbo Codes”. ”An Efficient Pipelined FFT Implementation”. J. Sundararajan and K. IEEE Trans. May 2003 128. 10(6). I. 2002 122. ”P-CORDIC: A Precomputation Based CORDIC Algorithm for the Circular Mode”. IEEE Trans. 2003(6). ”Frequency spectrum based low-area low-power parallel FIR filter design”. T. Sansaloni. June 2003 129. No. 2003 . 1954-1965. Valls.K. T. Dec. Eurasip Journal on Applied Signal Processing. 50(6). Vol. pp. ”Hardware Implementation of Advanced Encryption Standard Algorithm”. Eurasip Journal on Applied Signal Processing. Kuhlmann and K. Zhang and K. Parhi and J. Z. pp. pp. Parhi. 32(3). on Signal Processing. 2002 120. Parhi. Vol. pp. Parhi. 436-443. J. Chung and K. K. Sahoo and K. pp. Parhi. 9. Journal of VLSI Signal Processing. M. Valls and K. 2002 123. Zhang and K.K. Jan. B. 2002 125.G. ”Evaluation of CORDIC Algorithms for FPGA design”.-N. Eurasip Journal on Applied Signal Processing. pp. 570-579. Dec. 760-769. 2002 121. Wang and K.K. 101-115. Parhi. April 2003 127. ”Energy Efficient Signaling in DSM Technology”.K.K. Journal of VLSI Signal Processing. Parhi and H. 2002 124. V. Y. Sept. K.K. Chang and K. Wang and K. L. 9. 35(2). 322-325. Vol. Parhi. Parhi. ”Relaxed Annihilation-Reordering Look-Ahead QRD-RLS Adaptive Filters”. 15(3). ”Digit-Serial Complex Number Multipliers on FPGAs”. J. Vol. 563-586. 444-453. Vol. Parhi. ”An FPGA Implementation of (3. VLSI Design: Special Issue on Timing Analysis and Optimization for Deep Sub-Micron ICs.K. 105-112. 2002 119. 33(1). 207-222. pp. Parhi.K. ”Synthesis of Minimum Area Folded Architectures for Multi-Dimensional Multirate DSP Systems”.K. pp. Vol. Journal of VLSI Signal Processing. Z. Gao.118. pp. Journal of VLSI Signal Processing. pp. June 2003 130. 2(4). pp. 2002. 49(12). on Communications. on VLSI Systems.K. Dec. Parhi. Parhi. Ben Dhaou. K.K. Kuhlmann. Chi and K. ”Area-Efficient High Speed Decoding Schemes for Turbo/MAP Decoders”.6) Regular Low-Density Parity-Check Code Decoder”. Ma. pp. 2003 126. 51(4). M. Part-II: Analog and Digital Signal Processing.K.K. 35(1). 24-46. No. 50(3). Parhi. pp. Lee. on VLSI Systems. Chung and K. pp. Parhi. on TODAES.K. 52. 2102-2119. May 2004 142.K. Parhi. 504-511. on VLSI Systems. 2003(13). on Circuits and Systems. 9(3). 51(6). pp. 1328-1324. Parhi. pp. K.K. IEEE Trans. J. J. K. Y. June 2004 143. pp. 12(6).-M.K. March 2004 137. K. 984-993. 51(3). Kim. and K. Y.K. Chi. December 2003 135. K. 173-175. IEEE Trans.K. 642-651. Kong and K. 2. May 2004 140. Zhang and K. 2004 136. K. ”Design of Low-Error Fixed Width Modified Booth Multiplier”. Ma and K. J. March 2004 138. Feb. Cho.K. IEEE Communications Letters. 273-289. IEEE Trans. ”Overlapped Message Passing of Quasi-Cyclic Low-Density Parity Check Codes”. L. ”Reduced Complexity Decoding Algorithms for Space-Time Block Turbo Coded System”. IEEE Trans. 2003(13). 1065-1079. July 2004 . K. IEEE Trans. S. Kong and K. Vol. 1106-1113. pp. J. on Circuits and Systems. on Circuits and Systems. Part-I: Regular Papers. Signal Processing. Vol. S. Parhi. J. T. 512-516. pp.K. ”Joint (3. 545-549. on VLSI Systems. Part-I: Regular Papers. ”An Improved Pipelined MSB-First Add-Compare-Select Unit Structure for Viterbi Decoders”. Part-II: Analog and Digital Signal Processing. Chen and K.-G. Parhi. EURASIP Journal on Applied Signal Processing.-C. ACM Trans. June 2004 141.-J. ”Interleaved Convolutional Code and its Viterbi Decoder Architecture”.132. ”A New Approach for Integration of Min-Area Retiming and Min-Delay Padding for Simultaneously Addressing Short Path and Long Path constraints. ”Small Area Parallel Chien search Architectures for Long BCH Codes”. Chen and K. July 2004 144. on Circuits and Systems. Parhi.k)-regular LDPC Code and Decoder/Encoder Design”. 2003 134. 1335-1345. pp. Vol. Chen and K.K. Parhi. Parhi. Signal Processing. ”Low error CSD Fixed-Width Multiplier with Efficient Sign Extension”.-G. IEEE Trans. Song and K. 52(7). Complexity Tradeoffs of Block Turbo Decoder Design”. V. IEEE Trans. pp. Parhi. 12(5). ”Pipelined CORDIC Based State-Space Orthogonal Recursive Digital Filters using Matrix Look-Ahead”. Sapatnekar and K. April 2004 139. IEEE Trans. Part-I: Regular Papers. pp. ”Low-Latency Architectures for High-Throughput Viterbi Decoders”. pp.K. Sundararajan. ”On the Performance. 51(3). pp. Parhi. 12(5). Y. Z. Parhi. EURASIP Journal on Applied Signal Processing. 522-531. 52(4).K. pp. 2003 133. Parhi. Chung. IEEE Trans. No. ”Eliminating the Fanout Bottleneck in Parallel Long BCH Encoders”. March 2006 155.K. Parhi. 25-46.K.K. 53(10). ”Hardware Efficient Fast Computation of the Discrete Fourier Transform”. Apr.K. IEEE Trans. IEEE Trans. 2004 147. ”Fast Factorization Architecture in Soft-Decision Reed-Solomon Decoding”. Parhi. Parhi. Chi.K. 366-369. Circuits and Systems-II: Express Briefs. 13(4). Parhi. Nov. Sept. on VLSI Systems. July 2005 153.K. pp. Springer Journal of VLSI Signal Processing. K. pp. IEEE Trans. ”Hardware Efficient Fast DCT Based on Novel Cyclic Convolution Structures”. C. Parhi. IEEE Trans. 2006 159. Zhang and K. Cheng and K. pp. Apr. Pipelining and Retiming”. pp. X. pp. 2006 157. Wang and K. Oct. X. pp. C.-H. 2006. IEEE Trans. Journal of VLSI Signal Processing Systems. Parhi. Lin and K. Cheng and K. pp.K. 2005 151. Zhang and K. on Circuits and Systems. pp. Zhang and K. Parhi. pp. Gao and K. 1492-1500. 35(1). J. C.K. 1153-1157. Oct. Gu and K. Z. August 2006 156. ”High-Speed Architectures for Parallel Long BCH Encoders”. 51(8). IEEE Trans. on Signal Processing. Sep. ”On the Performance and Implementation Issues of Interleaved Single Parity Check Turbo Product Codes” Journal of VLSI Signal Processing Systems. Jan. on VLSI Systems. pp. 13(4). ”High-Speed Parallel CRC Implementation Based on Unfolding. C. 44(2). ”A Novel Systolic Array Structure for DCT”. 1435-1439. 52(9). 4419-4434 . 52(5). IEEE Trans. 12(9). on VLSI Systems. Parhi. 42(2). 54(11). X. ”On the Optimum Constructions of Composite Field for the AES Algorithm”. pp. on Circuits and Systems. 2006 158.145.K. Journal of VLSI Signal Processing Systems.K. ”Interleaved Trellis Coded Modulation and Decoder Optimizations for 10 Gigabit Ethernet over Copper”. ”Models for Architectural Power and Power Grid Noise Analysis on Data Bus”. bf 13(7). L. IEEE Trans. Cheng and K. Parhi. 2006 154. pp. on Signal Processing. 872-877.K. 2004 149. on Communications. Parhi. C. Parhi.K. Oct. on VLSI Systems. Part-I: Regular Papers. Feb. X. 2005 150. 1017-1021.K. 957-967. IEEE Trans. ”Hardware Efficient Fast Parallel FIR Filter Structures Based on Iterated Short Convolution”. ”Parallelization of Context Based Adaptive Binary Arithmetic Coders”. Part-II: Express Briefs. 42(3).K.K. Parhi. Cheng and K. ”On the Better Protection of Short Frame Turbo Codes”. 53(10). IEEE Trans. Zhang and K. 489-493. 211-221. Y. 159-172. Parhi. Aug. pp. 54(10). 3702-3711. 413-426. ”Design of Multi-Gigabit Multiplexer Loop Based Decision Feedback Equalizers”. Parhi. 2004 146. IEEE Trans. 2005 148. Circuits and Systems-II: Express Briefs. pp. Parhi. Chen and K. Y. ”High-Speed VLSI Architectures for the AES Algorithm”. Cheng and K. July 2005 152. Z. B. Saberinia. Circuits and Systems-II: Transactions Briefs. Tang. ”High-Speed VLSI Implementation of 2-D Discrete Wavelet Transform”. 2007. 54(10). ”Pipelined Parallel Decision Feedback Decoders (PDFDs) for High-Speed Ethernet over Copper”. Gu and K. 280-290 163. K. Y. 2008. 2008 170. and K.K.-K. Parhi. S. Cheng and K. 56(6). Cho. 54(9). Chen. ”High-Throughput VLSI Architecture for FFT Computation”. Parhi. C. pp. K. Kim. Circuits and Systems-I: Regular Papers. ”High-Speed Architecture Design of Tomlinson-Harashima Precoders”.K. Parhi. 55(10).K. 2009 171. on Vehicular Technology. Y. 720-726. Park. 54(1). Parhi. 1254-1258. 393-403 167. C. Part-II: Express Briefs. pp.-S. March 2009 172.K. pp. IEEE Trans. pp. Circuits and Systems-I: Regular Papers. A. pp. E. Jan. pp. 54(2). Parhi. 1929-1937. 2007 166. 2008 169. ”Low Complexity ECHO And NEXT Cancellers for High-Speed Ethernet Transceivers”.-G. Circuits and Systems-II: Express Briefs¡/I¿. Circuits and Systems-I: Regular Papers.K. Gu and K. 19-23 161. C. 2827-2840. IEEE Trans. pp. ”Probabilistic Spherical Detection and VLSI Implementation for Multiple-Antenna Systems”. IEEE Trans. Parhi. J. Gu. Tewfik. 2007 165. pp. 55(5). 56(3). Y. Gu and K. Parhi.K. Oct. on Signal Processing. Circuits and Systems-I: Regular Papers. Cheng and K. IEEE Trans. Feb. Chung and K. ”Low-Cost Fast VLSI Algorithm for Discrete Fourier Transform”. Oct. Feb. Parhi. Gu and K.K. IEEE Trans. C. on Circuits and Systems. and K. Park. May 2008 168. pp. Parhi. Circuits and Systems-I: Regular Papers. Parhi. ”Hardware Efficient Low-Latency Architecture for High Throughput Rate Viterbi Decoders”. 55(12).K. J. Y. IEEE Trans.K. pp. Parhi. 55(2). Cheng and K. 2007. and S. 2007.-C. IEEE Trans. Y. pp. ¡I¿ IEEE Trans. ”Pulsed OFDM Modulation for Ultra Wideband Communications”. Sep.H. 54(4).-J. Circuits and Systems-II: Transactions Briefs. Cheng and K. Jan. 707-715 162. IEEE Trans. 56(1). 2007. IEEE Trans. Circuits and Systems-I: Regular Papers. 863-867. J. 58(2). 1272-1285. Cheng and K. ”Design of Parallel Tomlinson-Harashima Precoders”. IEEE Trans. Parhi. IEEE Trans. Feb. Parhi.160. June 2009 . IEEE Trans. Chen. pp. on Signal Processing.K.K. Dec. 447-451. ”Novel FEXT Cancellation and Equalization for High Speed Ethernet Transmission”. C. 685-698.K. 791-806 164. Park.K. Apr. J. ”Low Cost Parallel FIR Filter Structures with 2-Stage Parallelism”. ”Design of a Sample Rate Converter from CD to DAT using Fractional Delay Allpass Filter”. J. pp. ”Computation Error Analysis in Digital Signal Processing System with Overscaled Supply Voltage”.E. 2011 186. Garrido. VLSI Systems. ”Low Complexity Decoder Architecture for Low-density ParityCheck Codes”. Elsevier Computer Networks Journal. Parhi. 58(2). and J. 2009 177. Ayinala and K. 1761-1770. IEEE Trans. Y. IEEE Circuits and Systems Magazine. 2010 180. 11(4). IEEE Trans. 2010 179.E. 2011 184. ”Power Reduction in Frequency-Selective FIR Filters under Voltage Overscaling”. Nov. ”Fast Elliptic Curve Cryptography Accleration for GF(2m) on 32-Bit Processors”. Parhi. 2009 176. Cohen and K. Apr. Oct. Signal Processing. R. Zhang and K.K. D. pp.K. 56(12).E.K. June 2009 174. of Emerging Technologies in Circuits and Systems (JETCAS). 57(1). pp. pp. Sept.K. 2011 183. 56(10). Parhi. 60(1). ”High-Speed Parallel VLSI Architectures for Linear Feedback Shift Registers”.3an (10GBase-T) Ethernet”. Oh and K. Parhi. Dec. pp. IEEE Trans. Luo. Circuits and Systems-II: Transactions Briefs. Liu and K. Jan. ”Seizure Prediction with Spectral Power of EEG Using Cost-Sensitive Support Vector Machines”. 2011 182. D. Parhi.K. pp. 2010 178.E. ”A Low-Complexity Hybrid LDPC Code Encoder for IEEE 802. Cohen. Parhi. Journal of VLSI Signal Processing Systems. March 2012 . ”Secure Variable Data Rate Transmission”.K. 217-228. Signal Processing. 2009 175. A. A. A. 59(9). 4459-4469. IEEE J. Oh and K. pp. Parhi. 1343-1356. L. K. 343-356. Liu and K. Lin and K.K. 100-104.E. Parhi. Jan. M. Y. IEEE Trans. pp. 2634-2643. IEEE Trans. 105-115. IEEE Trans. 85-94. Oh and K. 18(4). IEEE Trans.K. pp. pp. July 2010 181. 31-45. J. ”Low-Latency Low-Complexity Architectures for Viterbi Decoders”. pp. IEEE Trans. pp. Parhi. Cohen and K. ”A Pipelined FFT Architecture for Real-Valued Signals”.K. 57(10). Netoff. Parhi. A. pp. 2315-2324. 18(1). 56. Feb.K.173. Cohen and K.K. pp. Parhi. 1(3). 4085-4094. Circuits and Systems-I: Regular Papers. Epilepsia. Circuits and Systems-I: Regular Papers. Parhi. Oct. Sept. A. K. Parhi and T. Parhi. Park. ”Low Complexity Switch Networks for Reconfigurable LDPC Decoders”. 56(4). Liu. Grajal. 52(10). Cohen and K.K. D. VLSI Systems. Springer Journal on Signal Processing Systems. 2011 185. ”Min-Sum Decoder Architecture with Reduced Word-Length for LDPC Codes”. T. Circuits and Systems-I: Regular Papers. ”Architectures for RSA Cryptosystems: A Tutorial”.K. Oct.K. 517-526. ”Variable Data Rate (VDR) Network Congestion Control”. R. M. Madhavi. VLSI Systems. K. and K. ”Comments on ”Low-Energy CSMT Carry Generators and Binary Adders”” IEEE Trans. Kung. 149152.K.K. 1(3). 29(3). and K. June 2012 189. Parhi. H. to appear 193. ”Optimized Joint Timing Synchronization and Channel Estimation for OFDM Systems. pp. IEEE Trans. Parhi. Journal of Speech Technology. to appear 192.C. Jiang.K.-L.J. C. Patil. Parhi.K. Riedel.”Static And Dynamic Iinformation Derived from Source and System Features for Person Recognition from Humming. M. Ayinala.” IEEE Wireless Communications Letters. Parhi. H. Zhang and K. 59(6). Hu and K. Brown and K.K. ”Digital Signal Processing with Molecular Reactions”. 1068-1081. ”Pipelined Parallel FFT Architectures via Folding Transformation”.K. VLSI Systems. to appear . IEEE Design and test Magazine. June 2012 191. Parhi. Springer Journal of Signal Processing Systems.187. ”A Network-Efficient Non-Binary QC-LDPC Decoder Architecture”. Part-I: Regular Papers.” Springer Int. June 2012 190. May/June 2012 188. M. T. M. 20(6). Y.K. and K. IEEE Trans. Parhi. M. ””Design and Optimization of Multiplierless FIR Filters Using Sub-Threshold Circuits”. Parhi. Circuits and Systems. pp. K. Seattle. ”Pipelined VLSI Recursive Filter Architectures using Scattered Look-Ahead and Decomposition”. Parhi and D. 645-648 198.K. Messerschmitt. Proceedings of the IEEE International Conference ef Acoustics. Dallas. pp. 1986. Helsinki. pp. pp. K. pp.K. ”Two-Dimensional Recursive Digital Filtering: Pipelining. October 6-9. W. K. ”Distributed Scheduling of Broadcasts in a Radio Network”. Proceedings of the 1987 IEEE International Symposium on Circuits and Systems. Rye Town. June 1988. K. April 1989. ”Area-Efficient High-Speed VLSI Adaptive Filter Architectures”. May 1987. Philadelphia. Parhi. ”False Alarm Threshold Setting in Complex Multi-Variate Systems using Importance Sampling Technique”.K. 635-640 . August 1986.K. K. Messerschmitt. ”Look-Ahead Computation: Improving Iteration Bound in Linear Recursions”. K. Nebraska.K. Philadelphia. May 1989. May 1989. 1923-1928 204.Refereed Conference Publications 194. K. ”Block Digital Filtering via Incremental Block-State Structure”. and D.K.G. K. Messerschmitt. IEEE International Symposium on Circuits and Systems. pp. ”Architecture Considerations for High Speed Recursive Filtering”. Speech. K. Parhi. ”Nibble-Serial Arithmetic Processor Designs via Unfolding”. Proceedings of the 1989 IEEE Infocom.G.K. R. One.K. Parhi. June 1987. 1855-1858 197. Proceedings of the IEEE International Conference on Computer Design.K. Parhi and R. Proceedings of the IEEE International Conference on Communications.and Two-Dimensional Block Processing”. and D. K. and K.K. Proceedings of the IEEE International Symposium on Circuits and Systems. Proceedings of the IEEE International Conference on Acoustics. pp. ”A Bit Parallel Bit Level Recursive Filter Architecture”. (invited talk). Chen. Parhi. IEEE International Symposium on Circuits and Systems. and D. and Signal Processing. Oregon. Parhi. 2120-2123 201. invited talk 200. April 1987. K. pp. Parhi. 1521-1524 202. Rye.G. Messerschmitt.S. Parhi and D. Lincoln. pp. Parhi. 284-289 196. Proceedings of the 29th Midwest Symposium on Circuits and Systems. Speech.G.K.G. April 1988.L.G. Messerschmitt. Ottawa 203. 227-230 195. Messerschmitt.K. NY. May 1987. 374-377 199. Parhi and D. Ramaswami. Oregon. IEEE ISCAS 1989 (invited talk). IEEE International Symposium on Circuits and Systems. 1382-1387 205. ”Look-Ahead in Dynamic Programming and Quantizer Loops”. pp. Messerschmitt. Messerschmitt. ”Rate-Optimal Fully-Static Multiprocessor Scheduling of Data-Flow Signal Processing Programs”. and Signal Processing. pp.G. Parhi and D. Berkowitz. and D.G. 206. K.K. Parhi and D.G. Messerschmitt, ”Fully-Static Rate-Optimal Scheduling of Iterative Data-Flow Programs via Optimum Unfolding”, Proc. of the 1989 International Conference on Parallel Processing, August 1989, pp. I:209-216, St. Charles (Illinois) 207. K.K. Parhi, ”High-Speed Architectures for Dynamic Programming Problems”, in Proc. of 1990 IEEE International Conference on Acoustics, Speech, and Signal Processing, April 1990, Albuquerque, pp. 1041-1044 208. K. K. Parhi, G.S. Munson, and L.Q. Pham, ”Quantization Effects in High-Speed Pipelined Recursive Filters”, in Proc. of IEEE International Conference on Acoustics, Speech, and Signal Processing, April 1990, Albuquerque, pp. 1743-1746 209. K.K. Parhi, ”High-Speed Architectures for Algorithms with Quantizer Loops”, in Proc. of the IEEE International Symposium on Circuits and Systems, May 1990, New Orleans (invited talk), pp. 2357-2360 210. K.K. Parhi, and C.Y. Wang, ”Digit-Serial DSP Architectures”, Proceedings of the Third Conference on Application-Specific Array Processors, September 1990, Princeton, IEEE Computer Society Press, pp. 341-351 211. C.Y. Wang, and K.K. Parhi, ”Automatic Generation of Control Circuits in Pipelined DSP Architectures”, in Proceedings of the IEEE International Conference on Computer Design, September 1990, Cambridge (MA), pp. 324-327 212. C.-Y. Wang, and K.K. Parhi, ”Dedicated DSP Architecture Synthesis using the MARS Design System”, Proc. of the 1991 IEEE Int. Conf. on Acoustics, Speech, and Signal Processing, pp. 1253-1256, Toronto, May 1991 213. K.K. Parhi, and J.-S. Lee, ”Register Allocation for Design of Data Converters”, Proc. of the 1991 IEEE Int. Conf. on Acoustics, Speech, and Signal Processing, pp. 1133-1136, Toronto, May 1991 214. F.H. Wu, K.K. Parhi, and K. Ganesan, ”Neural Network Vector Quantizer Design using Sequential and Parallel Learning Techniques”, Proc. of the 1991 IEEE Int. Conf. on Acoustics, Speech, and Signal Processing, pp. 637-640, Toronto, May 1991 215. L.E. Lucke, A.P. Brown, and K.K. Parhi, ”Unfolding and Retiming for High-Level Synthesis”, in Proc. of 1991 IEEE International Symposium on Circuits and Systems, June 1991, Singapore (invited talk), pp. 2351-2354 216. K.K. Parhi, ”Register Minimization in DSP Data Format Converters”, in Proc. of 1991 IEEE International Symposium on Circuits and Systems, June 1991, Singapore (invited talk), pp. 2367-2370 217. H.R. Srinivas, and K.K. Parhi, ”High-Speed VLSI Arithmetic Processor Architectures Using Hybrid Number Representation”, in Proc. of the 1991 IEEE Int. Conf. on Computer Design, October 1991, Cambridge, Massachusetts, pp. 564-571 218. K.K. Parhi, ”High-Speed Huffman Decoder Architectures”, in Proc. of Twenty-Fifth Annual Asilomar Conference on Signals, Systems, and Computers, Nov. 4-6, 1991, Pacific Grove (CA), pp. 64-68 219. N.R. Shanbhag, and K.K. Parhi, ”A Pipelined LMS Adaptive Filter Architecture”, in Proc. of Twenty-Fifth Annual Asilomar Conference on Signals, Systems, and Computers, Nov. 4-6, 1991, Pacific Grove (CA), pp. 668-672 220. J-G. Chung, and K.K. Parhi, ”Design of Pipelined Lattice IIR Digital Filters”, in Proc. of Twenty-Fifth Annual Asilomar Conference on Signals, Systems, and Computers, Nov. 4-6, 1991, Pacific Grove (CA), pp. 1021-1025 221. L.E. Lucke, and K.K. Parhi, ”Parallel Structures For Rank-Order and Stack Filters”, in Proc. of the 1992 IEEE Int. Conf. on Acoustics, Speech, and Signal Processing, March 1992 (San Francisco), pp. V-645-648 222. K.J. Raghunath, and K.K. Parhi, ”Parallel Adaptive DFE Algorithms”, in Proc. of the 1992 IEEE Int. Conf. on Acoustics, Speech, and Signal Processing, March 1992 (San Francisco), pp. IV-353-356 223. L.E. Lucke, and K.K. Parhi, ”A New VLSI Architecture for Rank-Order and Stack Filters”, in Proc. of the IEEE International Symposium on Circuits and Systems, San Diego, May 1992, pp. 101-104 224. C.-Y. Wang, and K.K. Parhi, ”High-Level DSP Synthesis using Mars System”, in Proc. of the IEEE International Symposium on Circuits and Systems, San Diego, May 1992 (invited talk), pp. 164-167 225. N.R. Shanbhag, and K.K. Parhi, ”A High-Speed Architecture for ADPCM Coder and Decoder”, in Proc. of the IEEE International Symposium on Circuits and Systems, San Diego, May 1992, pp. 1499-1502 226. N.R. Shanbhag, and K.K. Parhi, ”A Pipelined Adaptive Lattice Filter Architecture”, in Proc. of the IEEE International Symposium on Circuits and Systems, San Diego, May 1992, pp. 2196-2199 227. N.R. Shanbhag, and K.K. Parhi, ”A Pipelined Adaptive Lattice Filter Architecture”, Proc. of the 1992 European Signal Processing Conference, August 24-28, 1992, Brussels (Belgium), pp. 1057-1060 228. N.R. Shanbhag, and K.K. Parhi, ”A Pipelined Adaptive Differential Vector Quantizer for Real-Time Video Compression”, Proc. of the IEEE Workshop on Visual Signal Processing and Communications, September 1992, Raleigh, North Carolina, pp. 9-14 229. K.K. Parhi, ”Impact of Architecture Choices on DSP Circuits”, Proc. of the IEEE TENCON: Region 10 Int. Conference on Computers, Communications, and Automation, Nov. 9-13, 1992, Melbourne, Australia, pp. 784-788 (invited talk) 230. L.E. Lucke, and K.K. Parhi, ”VLSI Structures for Weighted Order Statistics Filters”, in Proc. of IEEE Winter Workshop on Nonlinear Digital Signal Processing, Tampere, Finland, January 17-20, 1993, pp. 5.2.2.1-5.2.2.5 231. G. Shrimali, and K.K. Parhi, ”Fast Arithmetic Decoder Architectures”, Proceedings of Sixth SIAM Conference on Parallel Processing for Scientific Computing, March 22-24, 1993, Norfolk, VA, pp. 1025-1032 232. L.E. Lucke, and K.K. Parhi, ”Block Processing for Rank-Order Filtering using the RankOrder State Machine Architecture”, in Proc. of the 1993 IEEE Int. Conf. on Acoustics, Speech, and Signal Processing, April 1993, Minneapolis (MN), pp. I-357-360 233. G. Shrimali, and K.K. Parhi, ”Fast Arithmetic Coder Architectures”, in Proc. of the 1993 IEEE Int. Conf. on Acoustics, Speech, and Signal Processing, April 1993, Minneapolis (MN), pp. I-361-364 234. T.C. Denk, K.K. Parhi, and V. Cherkassky, ”Combining Neural Network and the Wavelet Transform for Image Compression”, in Proc. of the 1993 IEEE Int. Conf. on Acoustics, Speech, and Signal Processing, April 1993, Minneapolis (MN), pp. I-637-640 235. J.-G. Chung, and K.K. Parhi, ”The Scaled Normalized Lattice Digital Filter”, Proc. of the 1993 IEEE Int. Symp. on Circuits and Systems, May 1993, Chicago, pp. 483-486 236. N.R. Shanbhag, and K.K. Parhi, ”Roundoff Error Analysis of the Pipelined ADPCM Coder”, Proc. of the 1993 IEEE Int. Symp. on Circuits and Systems, May 1993, Chicago, pp. 886-889 237. C.-Y. Wang, and K.K. Parhi, ”Loop List Scheduler for DSP Algorithms under Resource Constraints”, Proc. of the 1993 IEEE Int. Symp. on Circuits and Systems, May 1993, Chicago, pp. 1662-1665 238. K.K. Parhi, and T. Nishitani, ”Folded VLSI Architectures for Discrete Wavelet Transforms”, Proc. of the 1993 IEEE Int. Symp. on Circuits and Systems, May 1993, Chicago, pp. 1734-1737 239. N.R. Shanbhag, and K.K. Parhi, ”A Pipelined Adaptive Differential Vector Quantizer for Low-Power Speech Compression”, Proc. of the 1993 IEEE Int. Symp. on Circuits and Systems, May 1993, Chicago, pp. 1956-1958 240. K.J. Raghunath, and K.K. Parhi, ”High-Speed RLS using Scaled Tangent Rotation (STAR)”, Proc. of the 1993 IEEE Int. Symp. on Circuits and Systems, May 1993, Chicago, pp. 1959-1962 241. L.E. Lucke, and K.K. Parhi, ”Generalized ILP Scheduling and Allocation for High-Level DSP Synthesis”, in Proc. of IEEE Custom Integrated Circuit Conference, May 9-12, 1993, San Diego, CA, pp. 5.4.1-5.4.4 Pacific Grove (CA). Parhi. and Implementations IV.K. Australia 253. and K. June 14-18. Parhi. Geneva (Switzerland). Raghunath. Parhi. III-81-III-84. J. ”Parallel Processing Architectures for Rank-Order and Stack Filters”. 15-17. Parhi. ”Fixed and Floating Point Error Analysis of QRD-RLS and STAR-RLS Adaptive Filters”.J. Parhi. July 11-16. ”Pipelined Implementation of High Speed STAR-RLS Adaptive Filters”. Conf. and K.K. and K. G. Architectures. Sept.K. and K. ”Calculation of Minimum Number of Registers in 2-D Discrete Wavelet Transforms using Lapped Block Processing”.K. MA. and Computers. and K. Proc. 65-76 249. ”A C-Testable Carry-Free Divider”. Pacific Grove (CA). 1993. Shanbhag.K. ”Pipelining of Orthogonal Double-Rotation Digital Lattice Filters”. 1993 Int. Oct. Shanbhag.J. Nov. N. Vol. H. pp. California 247. on Circuits and Systems. in Proc. Calcutta. Denk. ”Pipelined Adaptive Quantizers using Relaxed LookAhead”.K. 206-213 248. 1993. K. and Implementations IV. Stanford Sierra Camp. 1993. San Diego (CA).C. Parhi. Adelaide. ”High-Speed Arithmetic Decoder Architectures”. Lake Tahoe. pp. July 11-16. Venice (Italy). of the 1993 Int. 1993. Parhi. pp. Proc. May 23-26. Proc. pp. India. of the SPIE Advanced Signal Processing Algorithms. Vol. 1993 Int.K. Systems. Symp. Conf.R. and Eng. Vinnakota. ”Algorithms and Architectures for High-Speed or Low-Power Digital Signal Processing”. Cambridge. on Signals. of the SPIE Advanced Signal Processing Algorithms. May 30 .. and K. Proc. and K. and K. of the 27th Annual Asilomar Conf. pp. K. Sci. and Eng. San Diego (CA). Conference on Communications. April 19-22. K. Sci. N. Architectures. Proc. 1993. on Optical Appl. of the 27th Annual Asilomar Conf.June 2. Greece. Srinivas. of the IEEE Int. 1994. Shrimali.K. 222-226 243.K.-G. and K. ”A Pipelined Kalman Filter Architecture”. 1-3. pp. 1993. 1993..R. pp. 3. ”Calculation of Minimum Number of Registers in Arbitrary Life Time Chart”. 1994 252.R. Parhi. 8386. N. pp. on Acoustics. 122-133 245.R. 1993. and K. Symp. Proceedings of the 1993 IEEE Int. 134-145 246. Raghunath. of 1994 IEEE Int. 1993. Parhi. ”Pipelined Adaptive DFE Architectures”.K. pp. on Optical Appl. Parhi. Conf. K. 2027. January 5-8. Parhi. Speech. 2027. London . Proceedings of the 4th International Conference on Advances in Communications and Control (COMCON 4). Systems. B.80. and Signal Processing. 1994.242. October 3-6. on Signals. Lucke. T. on Computer Design. IEEE Computer Society Press. and Computers. Proc. L.77-3. 1-3. Symp. on VLSI Design. on Application Specific Array Processors. 1225-1229 250. Proc. Chung. pp.K. 259-270 244. Shanbhag. 1613-1617 251. Nov.K. Parhi. of the 1994 IEEE Int.E. Conf. Rhodes. of the Seventh Int. of the 1993 IEEE Workshop on VLSI in Communications. Proc. pp. in Proc. ”Architectures for Lattice Structure Based Orthonormal Discrete Wavelet Transforms”. 4-7. and Computers. in Proc. Arlington (VA) 256. 31 . Speech and Signal Processing.K. 5-8.K. Symp. 1994. 2747-2750. August 1994 257. Seattle. ”Synthesis and Pipelining of Ladder Wave Digital Filters in Digital Domain”.K. pp. pp. Symp.. in Proc. Raghunath and K. San Jose (CA) 260. K. Amendola. 231-234. Parhi. on Acoustics. J. 1994. Conf. of the 1995 IEEE Int. 77-80. 259-270. Proc. Proc.311-4. May 1995 264. Parhi and T. CA (Invited Talk) 259. of the 1995 IEEE Int. of the IEEE Asia-Pacific Conference on Circuits and Systems. on Circuits and Systems. ”Two VLSI Design Advances in Arithmetic Coding”. of 1994 IEEE Int. Parhi. and K. Symp. of the 28th Asilomar Conf.K. pp. 31 . ”A Low-Latency Standard Basis GF(2m ) Multiplier”. Parhi.K. ”VLSI Discrete Wavelet Transform Architectures”. Jain and K. Proc. 322-329.June 2. Oct. of the 8th Int. H. 3187-3190. Parhi. B. K. Jan.K. Detroit (MI) . on Signals. ”Generalized Multiplication Free Arithmetic Codes”.J. Parhi. 154-170. Pearson and K. K. Speech and Signal Processing. pp. Ito and K.K.Nov.K. of the 1995 IEEE Int. Jr. Parhi. pp. on VLSI Design. on Computer Aided Design. Proc. ”Low-Power FIR Digital Filter Architectures”. in Proc. in Proc. 1994. pp. in Proc. of the 1995 IEEE Int. Grand Hotel. H. Systems. 1995. 1994. Conf. Parhi. ”Module Selection and Data Format Conversion for Cost-Optimal DSP Synthesis”. Srinivas. May 30 . Taipei 261. 1303-1308. CA (Invited Talk) 258. 6-10. T. Proc. Parhi.R. S. on Signals. pp. India 262. Parhi. 4.K.2 Micron CMOS Multiplier Chip with Low Latency Vector Merging”. Srinivas. of the 1995 IEEE Int. May 1995.-G. Seattle. Chung and K. Fu and K. Parhi. ”Computer Arithmetic Architectures with Redundant Number System”.254.K. Detroit (MI) 267. May 1995 263. 2. Seattle. Conf. ”A Fast Radix-4 Division Algorithm”. of the 1994 Int. ”Determining the Iteration Bound of Data-Flow Graphs”. Srinivas and K. of the 1995 IEEE Int. Proc. Symp. K. K. Conf.C.K. in Proc. 1994. Parhi. 1994.314. and Computers. 2. ”A 100 MHz RLS Adaptive Filter Chip”. of the 28th Asilomar Conf. on Circuits and Systems. pp. L. Denk. pp. pp. Conf. on Circuits and Systems. W. Dec. New Delhi. D. B. of the 1st ARPA RASSP Conference. pp. 1440-1443. Systems. ”A 16-Bit X 16-Bit 1. 163-168. May 1995 265. Ito.Nov. in Proc. pp. pp. on Acoustics. Lucke and K. IEEE Computer Society Press.R. San Francisco.K. London 255. 15-18. Pacific Grove. and K. Seattle. H. Oct. May 1995 266. on Application Specific Array Processors. Parhi. on Circuits and Systems. 437-440.C.K. Nov. and K. Aug. Symp. Denk.K. May 1995. on Circuits and Systems. 182-186. Pacific Grove. pp. Parhi. ”VLSI Digital Signal Processing Education”. Proc. of the IEEE/ACM Int.E. Fu and K. 398-402.R. Denk and K. on Circuits and Systems. in Proc. Proc. in Proc. of 1996 IEEE Int. Parhi. on Circuits and Systems.K. Parhi. Atlanta 279. May 1996. on Circuits and Systems. November 1995 (invited talk) 272. pp. ”Comparison of Discrete Multitone and Carrierless AM/PM Techniques for Line Equalization”. Wang and K.K. M. Wang. pp. of 1996 IEEE Int. Srinivas and K. T. Proc. of 1995 IEEE Workshop on Nonlinear Signal Processing. II: 389-392. of Mentor Graphics Users’ Group Annual Conference. Atlanta 278. 145-148. ”Efficient Standard Basis Reed-Solomon Encoder”. ”MARS: A High-Level DSP Synthesis Tool Integrated within the Mentor Graphics Environment”. on Circuits and Systems. Chang. Symp. of 1996 IEEE Int.R. May 1996. ”A Hierarchical Approach to Transistor Level Power Estimation of Arithmetic Units”. May 1996. pp. Parhi. Atlanta 277. 895-898.C. 2-7. Y.K. Parhi. 3287-3290.K. Montalvo and K. Ames (Iowa) 273. Y. Satyanarayana and K. of the 1995 IEEE Int. May 1996.K.Y. Thessaloniki. Atlanta 280.K. pp. Symp. L. Greece 269. pp. J. C. ”STAR RLS Lattice Adaptive Filters”. C. H. II: 560-563. ”Trading off Concurrency for Low-Power in Linear and Nonlinear Computations”. Majumdar and K. of 1996 IEEE Int. Atlanta 274. in Proc. Parhi.N. K. in Proc.K. on Signals. Parhi. Systems and Computers. ”A Unified Framework for Characterizing Retiming and Scheduling Solutions”. Atlanta 275. Portland 271. in Proc. Parhi. on Acoustics. Chang. on Acoustics. Atlanta 276. Majumdar and K. Parhi. ”High-Level DSP Synthesis with Heterogeneous Functional Units using the MARS-II System”. and K. T.Y.268. in Proc. Symp. May 1996. October 22-27. 568-571. June 1995. Proc.K. 81-84. pp. October 1995. Conf.K.K. in Proc. 3338-3341. Symp.K. ”Loop List Scheduling for Heterogeneous Functional Units”. May 1996. A. Y. Parhi. pp. of 1996 IEEE Int. Speech and Signal Processing. Parhi. M. 109-116. Symp. Wang and K. Parhi. pp. Parhi. Parhi.K. Speech and Signal Processing. Atlanta . Denk. Shalash and K. of Sixth Great Lakes Symp. Conf. Speech and Signal Processing. ”A Floating Point Radix 2 Shared Division/Square Root Chip”.-N.C. pp. Conf. on VLSI. on Computer Design. May 1996. Proc. of 1996 IEEE Int. Conf. C. in Proc. Jain and K. 472-478. pp. Austin 270.K. of the 1995 Asilomar Conf. ”Radix-2 Over-Redundant Digit-Set Converters”.K. pp. 3330-3333. Li and K. on Acoustics. Pacific Grove (CA). ”Two-Dimensional Retiming with Low Memory Requirements”. in Proc. pp. of 1996 IEEE Int. on Circuits and Systems. S.-Y. ”Synthesis of Low-Area Data Format Converters”. of 1996 IEEE Int. March 1996. 1995. May 1996. 11-16. Parhi. of ProRISC/IEEE Workshop. Trivandrum (India). August 1996 283. October 1996. pp. April 1997 291. pp. of IEEE Int. Parhi. ”Pipelining of Cordic Based IIR Digital Filters”. Architectures. December 1996 (Invited Talk) 289. Proc. Proc. ”Three-Dimensional Carrierless AM/PM Line Code for Unshielded Twisted Pair Cables”. on Applications-specific Systems. Proc. pp. UMIST (UK) (Invited Talk) 286. Proc.F. D. ”Estimation of Average Energy Consumption of Ripple Carry Adder Based on Average Length Carry Chains”. Mierlo.K. 2196-2199. Architectures. Satyanarayana and K. 72-82. of IEEE Int. on Circuits and Systems. J. of the 1996 Int.K.L. 535-538. of the 1996 Int.K.F. Parhi. C. of ACM IEEE Design Automation Conference. Speech and Signal Processing. J. Nov. August 1996 284. Proc. Conf. 93-111. of 3rd Int. Parhi. Proc. on High Performance Computing. Chung and K. Parhi. pp. Parhi. on Circuits and Systems. Deprettere. Deprettere. and Processors. Parhi. L. Shalash and K. ”Order-Configurable Programmable Power Efficient FIR Filters”. Barcelona (Spain). Parhi. Proc. November 1996. Satyanarayana.K. Proc. Symp.K. on Computer Design.K. Las Vegas. of IEEE Int.-Y. Chang. C. 2136-2139. Chicago. and Processors.-Y. A. ”Pipelining of Cordic Based IIR Digital Filters”.P. on Acoustics. Song and Y. The Netherlands. ”Efficient Finite Field Serial/Parallel Multiplication”. Proc. Ma. Montalvo and K. ”Low-Area Dual-Basis Divider Over GF (2M )”. K. Austin (Texas) 285. Munich. 1996 287.H. pp. Proc. Parhi. 627-530. ”Low Area/Power Parallel FIR Digital Filters”. Parhi. Chang ”Systematic Analysis of Bounds on Power Consumption in Pipelined and Non-pipelined Multipliers”. Kim. pp. Proc. J. C. June 1997 . 9-14. J.K. pp. 1996 288. of IEEE Int. L. L. Conf. pp. on Circuits and Systems.K. H. Nov. K.K. April 1997 290. 492-499. Chicago. on Applications-specific Systems. K.K. Wang and K. L. pp. Conf. Xu. of 1996 Design of Integrated Circuits and Systems Conf. 1996 282. Conf. Proc. Xu. Conf. of 1996 IEEE Int. Satyanarayana and K.K. Parker and K.-G. Proc. 357-361. Song and K. and E. pp. Munich. ”Order-Configurable Programmable Power Efficient FIR Filters”. J. pp. Wang and K.A. 643-646. Conf. (DCIS). Song and K. Ma. C. Parhi. of IEEE Int. ”Low-Power Digit-Serial Architectures”. Hong Kong.P.L.K. Hong Kong. June 1997 (Invited Talk) 293. pp. June 1997 (Invited Talk) 292. Y. ”HEAT: Hierarchical Energy Analysis Tool”.K. Workshop on Image and Signal Processing. on Acoustics. Hong Kong. Parhi and E. Speech and Signal Processing.N. Symp.N. 2164-2167. of Int.281. Parhi. Symp. June 3-7. ”Low-Noise Implementation Technique for Pipelined Filters with Crowded Poles”. J. K. M. on Computer Design. Polla. of 1997 IEEE Workshop on Signal Processing Systems: Design and Implementation. 29 . L.K. November 1997 Invited Talk 302. 1997 298. of Government Microcircuit Applications Conference. Vu. Proc.H. R. M.S. R. 22-24. M. K. March 16-19. Sundararajan and K. Parhi. October 12-15. 232-241. of 1997 IEEE Workshop on Signal Processing Systems: Design and Implementation. C. J. September 1997 296. Seoul.T. Vu. Vu. 1997 299. and K. Schiller and M.D. October 26-29. E. Proc. Sundararajan. Nov. C.L. Kuroda and T. P. Michigan. ”Low-Power Multimedia DSP Systems”. Nguyen. Proc.K. Control. I-632-I-635. Parhi. Proc.K. Shur. 1997 304. 375-384. V. Vu.C. Parhi. pp. L. Leicester. M. Y. ”Pipelined Cordic Based QRD-RLS Adaptive Filtering Using Matrix Look-Ahead” Proc. on Computer Design.Oct.L. Schaumann.J. ”Design and Implementation of LowPower Digit-Serial Multipliers”. Sept.K. Conf. of 35th Annual Allerton Conference on Communication.K. D. Proc. and Computing. Parhi. 1997 Invited Talk 297. of 1997 IEEE Workshop on Signal Processing Systems: Design and Implementation. Conf. J. of IEEE Conf. Parhi. Bui. A.K. of IEEE Workshop on Non-Linear Signal Processing. Nguyen. Nguyen. 1997 301.N. on VLSI and CAD (ICVC). T. Vu..K. Systems and Computers. ”Gallium Arsenide Based Microsensor Systems”. Boston. pp. Illinois. ”A Wavelet-Domain Algorithm for Denoising in the Presence of Noise Outliers”. 1997.. Harjani. pp. pp. Polla.K. D. Leicester. Nov. pp.-N. ”Heterogeneous Digit-Serial Finite Field Multipliers and Low-Energy Reed-Solomon Codecs”. J. ”Optimum Primitive Polynominals for Low Area and Low Power Finite Field Semi-Systolic Multipliers”. ”Low-Power Digital Filters using Residue Arithmetic”. 13-15. K. 1. K. ”Microsensors Fabricated in Gallium Arsenide”. U.K. K. Vu. Proc. 1998. Proc. R. Federal Laboratory Consortium.C. of IEEE Int.L. Plenary Talk 300.K.H.D. of IEEE Conf. Schaumann.T..C.C. on Signals. October 12-15. Nov.K. Nguyen. Parhi. 131-140. I. of 1997 Asilomar Conf.T. Santa Barbara. 1997. of 1997 Int. ”Fast VLSI Binary Addition”. 739-743. and Technology Utilization Foundation). A. Parhi.294. W. K. 1997 305. J. K. Chang. Zervakis and K. Arlington. Satyanarayana. pp.H. T. L. Bui. Proc.K. Proc. ”Fast Low-Energy VLSI Binary Addition”. Parhi. Korea. 10-17. pp. MA 295. on Image Processing.J. Virginia . Oct. Austin. Nguyen. V. L.L.K.K. Sept. Proc. Song. U. Parhi.T. R. Proc. U. 676-684. Austin.N. Freking and K. Schiller and M. Zervakis.E.E. Song and K. Deprettere and K.F. Parhi. pp. Harjani. Parhi. Shur. Parhi. ”Area/Power Efficient Implementation of a Wavelet Domain Robust Image Denoising System”.C. Leicester. Nishitani. P. Kinney. P. Nguyen.C. P. Ma. 186-195.S. of Technology 1997 (NASA Tech Briefs. 1997 303. Proc. 1998 315. Proc. Deprettere. pp. of IEEE Int. 1998 313. II-433-II-436. J.K. of IEEE Int. Kuhlmann and K. on Circuits and Systems. and T. Pipelined Architectures for MultiDimensional Multirate Systems”. Boston . Symp. V. A. of IEEE Int. and Instrumentation.K. ”Synthesis of Folded. L.June 3. May 31 . V. Seattle 307. Symp. 275-284. on Circuits and Systems.K. Freking and K. Symp. on Circuits and Systems. Proc. I. Eng. Parhi. Song and K.-J. Ma. Nishitani.K. Monterey. ”Theoretical Estimation of Power Consumption in Binary Adders”. Conf. on Circuits and Systems. pp. May 31 . Symp. and Implementations VIII.K.F. Architectures. of IEEE Int.. pp. in Proc. 1998. Parhi. Chung. pp. pp. R. July 19-24.306. Proc.. Symp. of the SPIE Advanced Signal Processing Algorithms. K. pp. San Diego (CA) 317. Hekstra. 3089-3092.K. of IEEE Int. 1998 Int. ”Efficient implementations of Cordic-based IIR digital filters using fast orthonormal micro-rotations. Conf. Nishitani. May 1998. 3025-3028.June 3. May 1998. 1998 312. Sundararajan and K. ”Three-Dimensional Equalization for the 3-D QAM System with Strength Reduction”. on Acoustics. Symp.J.June 3. of IEEE Int. Y. May 1998. and Instrumentation. Parhi. ”Low-Energy Programmable Finite Field Datapath Architectures”. Parhi. Parhi. on Circuits and Systems. of IEEE Int. Speech and Signal Processing. Parhi. ”Pipelined Cordic Based QRD-MVDR Adaptive Beamforming”. Monterey. Kuroda and T.June 3. J. pp. and E. Kuroda. K. on Optical Sci. H. and E. Seattle 309.K. pp.June 3. Oct.K. Proc. Monterey. on Circuits and Systems. Shalash and K. Song. Monterey. Proc. Symp. pp.K. K. Deprettere. San Diego (CA) 316. 1998 Int. 1998 310. Sundararajan and K. 3049-3052.-B. and E. V-354-V-358. ”High-Speed Cordic Based Parallel Weight Extraction For QRD-RLS Adaptive Filtering”. in Proc. on Optical Sci. ”Low-energy Heterogeneous Digit-Serial Reed-Solomon Codecs”. of IEEE Int. Seattle 308. K. Speech and Signal Processing. M. Parhi. May 31 . Parhi. Proc. V-245-V-248. of 1998 IEEE Workshop on Signal Processing Systems: Design and Implementations (SiPS). Parhi. 1998 311. and K. ”Scheduling Strategies for Low-Energy Programmable DigitSerial Reed-Solomon Codecs”. July 19-24. Ma. and Implementations VIII. J. pp. ”Efficient Parallel FIR Filter Implementations using Frequency Spectrum Characteristics”. I. K. Jeong. of IEEE Int. Proc. J. Proc. IV-453-IV-456. Monterey. G. L.F. ”Synthesis of Folded Multi-Dimensional DSP Systems”. Deprettere. in Proc.K. Parhi.-G. Song.F. 1998 314. ”Power Comparison of SRT and NST Dividers”. II-453-II-457. L.K. Symp. Architectures. May 31 . May 31 . Ma. Monterey. Conf. on Acoustics. Kim. 1998. Parhi. Parhi. Eng. 8-10. II-406-II-409. 1998. Speech and Signal Processing. of the SPIE Advanced Signal Processing Algorithms. May 31 . on Acoustics.June 3.K. K. Sundararajan and K. ”High-Performance Digit-Serial Complex-Number MultiplierAccumulator”. March 1999. Systolic VLSI Architectures for 1-D Discrete Wavelet Transforms”. Denk and K. Oct. Freking and K.K. pp. 1-4. of 1998 Asilomar Conf. Pacific Grove (CA) 323. R. pp.K. Chang and K. of 1998 IEEE Int. on VLSI. of 1999 Advanced Research on Conference on VLSI. Parhi. 1937-1940. Pacific Grove (CA) 326. pp. Proc. Pacific Grove (CA) 324. ”Performance Tradeoffs in Digit-Serial DSP Systems”. Proc. 1998. on Computer Design. H.K. Nov. Proc. Kuhlmann and K. ”Low-Power Gate Resizing of Combinational Circuits by Buffer Redistribution”. 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IEEE CAS Society (Chair-Elect: 2000-2002. Faculty Promotion and Tenure Committee of Electrical Eng. Dept. Founding Member. Electrical Eng. Director of Graduate Stuides (2008-2011) 2. Instructor for Oral Presentation Training (1990) 8. Member. Member. 1998. Chair-Systems and Hardware Track for Univ. Graduate Standards Committee (2007-2008) 3. Member.D.D. Member. Member. Faculty Recruiting Committee of Electrical Eng. Committee (1989. Ph. (1990-95) (1998- 5. (1995-96) (1998-99) 6. Written Qual. Fellow. on Visual Signal Processing and Communications. IEEE CAS society 8. IEEE Signal Processing Society (1990-) 9. Cmt. 2004-5. Member. Member. (1989-90) (1997-98) (2003-2004) 4. on Digital Signal Processing. IEEE – Signal Processing Society 3. Member. 2002-3. 2009-10) 7. Fellow . Michael Zervakis. Univ. Korea (2001) 11. Greece (1996) 5. University of Saitama.Post Doctoral Fellows and Visitors Supervised 1. Paul] 2. ”Applying Parallel Processing Techniques to Digital Signal Processing Algorithms and Architectures for High Level VLSI Synthesis”. Boca Raton. Spain) (2007) 14.LSI Division. 2006) 13. Steve Summerfield. Spain (1999) 9. Florida Atlantic University. Universidad Politecnica de Valencia. Chania. Naresh R. Prof. ”MARS: A High-Level Synthesis Tool for Digital Signal Processing Architecture Design”.K. Nanjing Univ. Lori E. Universidad Politecnica de Valencia. Mario Garrido (ETSI Telecomunicacion. Chonbuk National Univ. Ching-Yi Wang. of Technology. Isfahan Univ. St. December 1992 [Currently with Minnetronix Corp. Japan (1997-1999) 7. Spain (1999) 8. of Illinois at Urbana] . India (2009) 15. July 1993 [Currently Associate Professor at Univ. Paul (1993-1996) 3. Chunlei Xia (Shanghai. Florida (1999) 10. St. (KAIST. Kazuhito Ito. Prof. Iran (2011-12) Ph. Shanbhag. Valencia. Hiroshi Suzuki. Luis Montalvo. Japan (1992-1993) 2. Hemant Patil. Theses Supervised 1. Gandhinagar. France Telecom. Valencia. France (1995-1996) 4. Chiba. Ching-Yi Wang.D. of Warwick. Yuke Wang. Technical Univ. China (2010) 16. Crete. Kawasaki Steel . Coventry. Javier Valls. St. DA-IICT. Xiaoping Li. Lucke. of Crete. Meylan Cedex. (1997) 6. Paul] 3. Madrid. December 1992 [Currently with Boston Scientific.. Ahmad Salehi. Jin-Gyun Chung. Trini Sansaloni. ”Design of Pipelined VLSI Adaptive Digital Filters with Relaxed Look-Ahead”. CPI Guidant. Summer 2005) 12. U. China. Chester Park. November 1994 [Currently Professor at Chonbuk National University. Tracy C. NJ] 9. Ahmed Shalash. July 1999 [Currently Professor at Shanghai Jiao Tung University.R. Vijay Sundararajan. ”Pipelined STAR RLS Adaptive Filters”. Leilei Song. June 1999 [Currently Marvell Technology Group. ”High-Performance Low-Power Arithmetic. South Korea] 7. China] 13. March 1998 [Currently with LSI Logic. Jin-Gyun Chung. 2000 [Currently with Broadcom Inc. Jan. Architectures and Circuits”. Holmdel. ”Low-Power VLSI Architectures for Finite-Field Applications”. ”Retiming. Irvine. CA] 5. Taiwan] 12.4. Folding and Register Minimization”. Egypt] 10. Dec.. H. Warren. ”Low-Power Bit-Serial and Digit-Serial DSP Systems”. July 1996 [Currently with Newport Media. Srinivas. ”Pipelined RLS Adaptive Filters”. June 1999 [Currently on the Faculty at National Sun Yat-Sen University. ”Floating Point Computer Arithmetic Architectures”. Jun Ma. Ibiquity Corp. Denk. Satyanarayama. ”Design of Low-Power DSP Systems”. NJ] 6. CA] 8. Chonju. Yun-Nan Chang.. Martin Kuhlmann. Janardhan H. Irvine.. ”Performance Optimization Methodologies for Design of Digital VLSI Systems”. Calif. Irvine. CA] 14. ”Architecture and System Design for Digital Subscriber Loop Communications”. K. CA] . Irvine. September 1994 [Currently with Broadcom. June 1998 [Currently Member th Cairo University. ”Pipelined IIR Lattice and Wave Digital Filters”.J. Raghunath. October 1994 [Currently Member of Technical Staff. 1999 [Currently with Broadcom Inc. Shanghai.] 11. Kaohsiung. 2000 [Currently with Texas Instruments. R. NY] 21. ”VLSI Architectures for High-Speed Transceivers”.P. Dallas] 16.] 24. ”Algorithms and Architectures for High-Performance Public-Key Cryptography Systems”.. July 2006 [Currently with Newport Media Inc. Chen. October 2000 [Currently with MIT Lincoln Laboratories] 18. Troy. Freking. October 2000 [Currently with MIT Lincoln Laboratories] 17. J. Zhipei Chi.M. ”Low-Complexity High-Speed VLSI Architectures for Error-Correction Decoders”.. Freking. ”Architectures for OFDM Based Ultra Wideband Systems”. ”Structural Strategies for High-Performance Undelimited-Codeword Source Coding”. Prof. Professor of ECSE Dept. 2005 [Currently with Samsung. June 2002 [Currently Assoc.”Efficient VLSI Architectures for Error Control Coders”. Zhang. T. Gu.] 26. ”Classical and Quantum Convolutional Codes: Design and Implementation”. Irvine] 25. ”Architecture Design and Mapping of DSP Systems”. ”Efficient VLSI Architectures for Error Correction Coding”. June 2001 [Currently with Link-A-Media.] .. Y. ”High-Performance and Low-Cost VLSI Design of Turbo Decoders”. High Speed VLSI Architectures for Wireless Communication Applications”.15. 2001 [Currently with Medtronic Inc. at Case Western Reserve Univ. July 2005 [Currently with Newport Media Inc. Aug. Tang. ”Architectures for Error Control Coders and Cryptography Systems”. Feb. Zhang. S. Robert A. Lijun Gao. Oct. CA] 22. ”High Performance. June 2003 [Currently with Marvell Technology Group. Kim .I. Minneapolis] 19. Y. X.. J. Kong. Feb. June 2005 [Currently Assoc. Korea] 23. 2006 [Currently with Qualcomm Inc. CA] 20. Zhongfeng Wang. William L. Cohen. CA] 29. Yuping Zhang. CA] . Riedel) [Currently with Synopsis. ”Architectures for Cryptography Accelerators” September 2007 [Currently with Naval Research Lab. Theoden I. ”Digital Logic and Signal Processing Computations with Molecular Reactions. May 2007 [Currently with Marvell Technology Group. Chao Cheng. 2007 [Currently with Newport Media. Korea] 32. ”Reduced-Complexity Epileptic Seizure Prediction with EEG. 2010 [Currently with Broadcom Corp. 2008 [Currently with Marvell Semiconductors.] 28. RI] 35. Hua Jiang. J. Daesun Oh. ”Error Control Algorithms and Architectures for Reliable DSP Systems”. May 2008 [Currently with Samsung. Washington. Renfei Liu. ”Algorithm and Architectures for Next Generation Multimedia Systems”. Irvine..” May 2012 (Coadvised by Prof. Jianhung Lin. Yun Sang Park. CA] 34. 2012 (Coadvised by Prof. Marc D. Providence. ”High-Speed Low-Cost VLSI DSP Algorithms Based on Novel Fast Convolutions and Look-Ahead Pipelining Structures”. LDPC Code Decoder and List Sphere Decoder”. Inc. ”Efficient VLSI Architectures for High-Speed Ethernet Transceivers”. May 2007 [Currently with Marvell Technology Group. CA] 30. Nov. Aug.27. CA] 33. Netoff) [Currently with Brown University.” Jan. ”VLSI Architectures for Turbo Code Decoder. Jan. DC] 31. Aaron E. Chen. ”Low Complexity VLSI Architectures for LDPC Decoders”. Yuet Li. November 1989 4. ”Power-Speed Reconfigurable FIR Filters”. ”Roundoff Error in Digital Filters using Redundant Numbers”. May 1996 20. Wayne C. ”Synthesis of Pipelined Lattice IIR Digital Filter”. ”Reduction of Hardware Overhead in Recursive Filters by Interleaving”. ”Finite Precision Effects in Scattered and Clustered Look-Ahead Pipelined Recursive Digital Filter Implementations”. ”Low-Area/Power Parallel FIR Filters”. Jim Malaney. Andrew P. Projects Supervised 1. June 1993 11. ”A New Approach For Design Of Data Format Converter Architectures Using Register Allocation”. February 1996 19. Santosh Misra. Chung. November 1991 10. David A. Syed Babar Raza. ”iSchematic: An Automatic Schematic Generator for OCT 5. Darren Pearson. H. October 1991 9. ”Low-Area Data Format Converters”. Gregory S. Lai Q. Gireesh Shrimali. January 1991 5. November 1989 3. ”Fast Arithmetic Coder Architectures”. Brown. September 1991 8.S. July 1991 7. June 1995 16.. ”STAR Adaptive Lattice Recursive Least Square Filters”. ”Low Power Strategies for VLSI Implementation of Digital Filters”. Bin Fu. ”Efficient VLSI Architectures for Finite Field Arithmetic”. Yun-Nan Chang. February 1996 18. May 1995 14. Munson.R. Iyer.M. ”VLSI Implementation of a 200 MHz 16X16 Redundant Digit Multiplier and a 125 MHz 16X16 Booth-Encoded Redundant Digit Multiplier”. J. ”High-Level DSP Synthesis using Heterogeneous Functional Units”. ”CDMA Based Mobile Communication Systems”. N. Mayukh Majumdar. Jr. Srinivas. May 1991 6. Pham. June 1995 17. June 1993 12. Parker. Joo-Sang Lee. May 1995 13. ”VLSI Design Advances in Arithmetic Coding”. June 1989 2. ”Design of a Programmable Digital Filter”.0 Data Base”. Amendola. May 1995 15. June 1996 . Chong Xu. Surendra Jain. ”Applications of Circuit Retiming to DSP Architecture Design”. ”High-Speed VLSI Arithmetic Processor Architectures Using Hybrid Number Representation”.-G. May 2005 41. ”Power Efficiency of the Carry-Select Adder”. Ashish Karandikar. ”Efficient Bit-Serial Finite Field Multipliers”. Nikhil Sarpotdar. Dhiraj Kumar. ”VHDL Interface for MARS DSP Synthesis System”. Jan. 2000 36. ”Low-Complexity Pipelined-Parallel Decision Feedback Decoder (PDFD) for 1 Gbps Ethernet”. Ziyu Li. Hojun Kim. Mousumi Gayen. March 2005 40. ”Performance Tradeoffs of DCT Architectures in Xilinx FPGAs”. Ru-Guang Chen. Aug. Bibhudatta Sahoo. ”LDPC Decoder for DVB System”. June 1996 23. William Ho. Priyadharshini Vijayakumar. December 1997 28. John Bratt. Aug. Sept. ”Minimal Switching Activity Schedules for Various FIR Filters”. Manoj Yadav. 2000 37. ”VLSI Design and Implementation of Two Viterbi Decoders”. Siwei Chen. Robin Bansal. 2008 . ”Timing Variations in Digital Filters with Supply Voltage Variations”. Jan. Leilei Song. ”Radix-2 Division and Square Root Algorithms: Study and Implementation”. ”ILP Scheduling with Processor Interconnection”. Zhipei Chi. Nidish Kamath. Karuna Prasad. ”Coefficient Optimization in Pipelined IIR Digital Filters”. June 1996 22. ”Pipelined Single and Multi-Channel Lattice RLS Adaptive Filters”. 2000 35. 1997 25. Jan.21. July 1999 32. April 1999 31. Aug. July 1996 24. August 2004 39. ”Scheduling of DSP Algorithms for Low-Power Design”. Wenhao Wu. August 1999 33. Feb. 1998 29. July 1997 26. Lina Long. ”DLMS Adaptive FIR Filter: Bit-Serial Systolic Array VLSI Implementation”. 2001 38. 1999 30. ”Double Error Correction on Residue Number System”. ”A VLSI Implementation for Viterbi Decoder in Ultra Wide-band System”. ”A Low Power Correlator”. ”Optimized Power and Delay Solutions for Digital CMOS Circuits by Transistor Reordering using HEAT”. 2000 34. Saurabh Jain. ”Power Analysis of 4-2 and 5-2 Compressors”. August 1997 27. ”Low-Power and High-Performance Static Random Access Memory”. Aug. May 2011 49. Michael J. Lan Luo. Yingbo Hu. 2010 47.” September 2011 50. Prashant Metkar. ”A Low-Complexity Seizure Prediction Algorithm. Brown. Xiaoming Zhu. ”Research for the Development of an Apparatus To Help Prevent Sudden Infant Death”. Manohar Ayinala.” November 2011 . May 2009 44. Jaime Rivera. ”Lung Sound Separation by Independent Component Analysis”. August 2010 46. May 2009 43.42. ”High-Throughput VLSI Architectures for CRC/BCH Encoders and FFT Computations”. Nov. ”A Low-Complexity Seizure Prediction Algorithm”. Michael Brown. ”Improved Approach for Calculating Model Parameters in Speaker Recognition using Gaussian Mixture Models”. ”Subthreshold Circuit Design”. ”Frame Start Synchronization in OFDM System. ”Postprocessing of Seizure Prediction by Kalman Filter”. May 2011 48. June 2009 45. Te-Lung Kung. 2. Te-Lung Kung (PhD) 3. Sohini Roychowdhury (PhD) 8. Developed a new class ”VLSI Communications Systems” in Spring-2003 (EE-8950) 5. I developed the ”VLSI Low-Power and Digital Video Systems (EE 8451)” Course in Fall 1997. 3. Error Control Coding and Cryptography Architectures” (EE 5953)” Course in Winter 1999 4. Yingjie Lao (PhD) 5. Zisheng Zhang (PhD) 9. Tingting Xu (PhD) 7. Taught ”Ethics and Professional Conduct in EE” (Fall-2010) . 1. I developed the ”Digital Arithmetic. I developed a new class ”VLSI Digital Signal Processing Architectures (EE 8207)” in Spring 1990. Ahmad Salehi (PhD) Course Development 1. Bo Yuan (PhD) 6. Taught ”Teaching Experience in EE” class (2010-11) 6.Graduate Advisees I am currently advising following Graduate Students. Manohar Ayinala (PhD) 2. Chuan Zhang (PhD) 4.