798IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 57, NO. 10, OCTOBER 2010 On-Chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits Kyung Ki Kim, Member, IEEE, Wei Wang, and Ken Choi, Senior Member, IEEE Abstract—Accurate performance-degradation monitoring of nanometer MOSFET digital circuits is one of the most critical issues in adaptive design techniques for overcoming the performance degradation due to aging phenomena such as negative bias temperature instability (NBTI) and hot carrier injection (HCI). Therefore, this paper proposes new on-chip aging sensor circuits which deploy a threshold voltage detector for monitoring the performance degradation of an aged MOSFET. The new aging sensor circuits measure the threshold voltage difference between a NBTI/HCI stressed MOSFET device and a NBTI/HCI unstressed MOSFET device using an inverter chain and a phase comparator and digitalize the phase difference induced by the threshold voltage difference. The proposed sensor circuits achieve a direct correlation between the threshold voltage degradation and the phase difference (a phase difference resolution of 1 ns per 0.01 V threshold voltage shift). Also, the circuits are almost independent of temperature variation due to symmetrical circuit structures. A 45 nm CMOS technology and predictive NBTI/HCI models have been used to implement and evaluate the proposed circuits. The implemented layout size is 18.58 × 7.97 μm2 ; the post-layout power consumption is 18.57 μW during NBTI/HCI stress mode and 30.86 μW during NBTI/HCI measurement mode on average. Index Terms—Aging, degradation, hot carrier injection (HCI), negative bias temperature instability (NBTI), reliability. I. I NTRODUCTION S MOSFET technology is scaled down more aggressively, it has become even harder to design reliable circuits with each nanometer technology node; under normal operation conditions, a transistor device can be affected by various reliability mechanisms (or aging phenomena) such as negative bias temperature instability (NBTI), hot carrier injection (HCI), and time-dependent dielectric breakdown (TDDB). These mechanisms lead to device aging resulting in performance degradation and eventually design failure during the expected system lifetime [1]–[3]. Among these reliability mechanisms, the NBTI-stress impact on PMOSFETs and the HCI-stress impact on NMOSFETs have become a major reliability concern in digital circuit design. The NBTI stress describes the A Manuscript received December 16, 2009; revised April 6, 2010 and June 30, 2010; accepted July 14, 2010. Date of publication September 30, 2010; date of current version October 15, 2010. This paper was recommended by Associate Editor P. Li. K. K. Kim is with the School of Electronic Engineering, Daegu University, Gyeongsan 712-714, South Korea (e-mail:
[email protected]). W. Wang and K. Choi are with the Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, IL 60616 USA (e-mail:
[email protected];
[email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCSII.2010.2067810 parameter degradation under a negative (static) bias stress mode at elevated temperature: it increases PMOS threshold voltage (hereafter called Vth ) with time, thereby causing the circuit delay degradation. As for the HCI stress, it is the result of electron trapping or interface-state generation induced by the impact ionization of channel carriers near the drain region and causes the degradation of the electrical parameters of a transistor when the transistor is switching. The HCI stress used to be considered less critical than the NBTI stress, but it should be considered as another critical issue as gate lengths are getting shorter than 50 nm. Although the reliability mechanisms have traditionally been considered as an area of process researchers/engineers, the reliability mechanism starts to emerge as a circuit designer’s problem because in the future even the smallest of variations can slow down MOSFET circuit speed and an aging MOSFET device may not perform adequately at a very low voltage. As an easy solution to the problem, circuit designers need to consider these reliability mechanisms in the early design stages to make sure that MOSFET circuits are operated with enough margins to function correctly over their entire lifetime. However, since this solution excessively increases the circuit size and power dissipation of a system, new circuit design techniques should be introduced for the resilient circuits. This challenge for resilient circuits will require a design paradigm shift to adaptive design for overcoming the performance degradation due to aging phenomena; hence an accurate on-chip sensor circuit technique to monitor aging phenomena would be one of the key issues in the adaptive design techniques. The outputs of the sensor circuits can be used as control signals in the adaptive systems using substrate body biasing and/or power supply voltage scaling techniques. Recently, onchip NBTI sensor circuits have been proposed but they have some weak points in measuring the impact of NBTI on digital circuits: [4] and [5] propose a fully digital on-chip NBTI monitor, but the proposed circuits suffer from a less direct correlation between the frequency-degradation of the monitor circuit and the Vth -degradation caused by NBTI stress. [6] presents a compact structure in the subthreshold region to digitalize the NBTI stress, but the presented structure is too sensitive to temperature variation due to the circuit operation in the subthreshold region. With regard to the HCI sensor circuit, to the best of our knowledge, no HCI sensor circuit has been presented. In this paper, we propose new fully digital on-chip NBTI and HCI sensor circuits using a 45 nm CMOS technology and predictive NBTI/HCI models where outputs are strongly correlated with the Vth -degradation caused by NBTI and HCI stress and are almost independent of temperature variation. 1549-7747/$26.00 © 2010 IEEE Second.: ON-CHIP AGING SENSOR CIRCUITS FOR RELIABLE NANOMETER MOSFET DIGITAL CIRCUITS 799 where A is linearly proportional to the hole density and has an exponential dependence on temperature and the electric field.25 ·T 0. the channel carriers will reach a velocity higher than the thermally limited diffusion drift velocity. it may produce an electron-hole pair by impact ionization also called avalanche pair production as shown in Fig.25 · ⎣ 1− 1− η(1−β)/n 2n 2 ⎤0. and the others are the measured coefficients. δ is the constant (5 mV). tox is the gate oxide thickness. That is. HCI HCI stress describes a degradation of the electrical parameters of MOSFETs under a dynamic stress mode. [7]. hence the term hot carriers. The long term Vth -degradation due to NBTI after n-cycles of stress and recovery can be described as [7] ⎡ ⎢ 1− 1− η(1−β)/n ΔVth = Kv ·β 0. the dynamic NBTI model is generated under AC operation conditions and the AC operations can lead to observable recovery (known as recovery effect) when a PMOS device is unstressed by the NBTI. An increase in Vth reduces the voltage overdrive (VDD − Vth ) which degrades the circuit stability and margins.9 nm. both of which lead to Vth increase (drain-current decrease) as shown in Fig. At high drain-to-source (Vds ) bias. when the gate is grounded and a positive bias is applied to the source/drain.622 V) under long term AC operation conditions. in which the threshold voltage of the stressed PMOS device shifts up as the number of cycles in the stress signal increases. δv is the constant (5 mV). 1(b) shows the Vth -degradation of a stressed PMOS device (45 nm technology. Fig. it has to be considered critically in circuit design and simulation. Electrons from impact ionization could have enough energy to be injected into the gate oxide region and charge existing oxide traps or generate new oxide interface traps. n is the number of cycles. First. The end result of hot carrier injection into the gate oxide (1) . II. tox is the gate oxide thickness. T is the clock period. and the presence of impurities in the oxide originate interface and oxide charge traps. 1(a). In this paper. the lateral electric field rises gradually from the source to the drain with a sharp peak near drain junction region. tox = 1. NBTI NBTI stress affects PMOSFETs when a negative bias is applied to the gate or equivalently. and initial Vth0 = 0. NBTI degrades performance and device-yield of PMOSFET [1]–[3].5 ⎥ ⎦ +δv (2) where β is the duty cycle. 1. If a channel hot carrier collides with a crystal atom near the drain region. and the n is the time exponent. the boron penetration into the gate oxide. Since the recovery effect can nullify the effects of NBTI stress and lead to overestimation of NBTI stress. 2(a). predictive NBTI lifetime models under AC operation conditions are employed for a long term circuitdegradation simulation [6]. NBTI can be divided by two models depending on the gate voltage of PMOS and time: static NBTI and dynamic NBTI. NBTI effect on a PMOSFET device in a 45 nm technology: (a) NBTI stress. Cox is the oxide capacitance per unit area. R ELIABILITY I SSUES A. the static NBTI model for a PMOS device is generated under constant stress (gate voltage is grounded) and the Vth variation due to the static NBTI at time t can be given by [7] ΔVth = A · (1 + δ)tox + C(t − t0 ) 2n where k is the Boltzmann constant. holes can be injected into these traps which lead to Vth increase and Idsat decrease. B. and the Kv is given by Kv = A · tox · Cox (Vgs − Vth ) · exp · 1− (Vgs − Vth )/tox E0 (3) Vds Ea · exp − α(Vgs − Vth ) kT Fig. In inversion mode.KIM et al. The presence of hydrogenated Si-bonds (Si-H) at the interface between Si and gate oxide. (b) Vth dependence on NBTI effect [9]. Due to the presence of the high field. Carriers in the channel travelling from source to drain are subjected to a varying electric field depending upon the transistor bias conditions. the threshold voltage almost linearly increases and the mobility almost linearly decreases. predictive HCI lifetime models under a dynamic stress mode are used for a long term circuit-degradation simulation [9]. In other words. HCI effect on a NMOSFET device in a 45 nm technology: (a) HCI stress. As the stress time is accumulated. and phase-to-digital converter as shown in Fig. and the others are the measured coefficients. t is the stress time. n is 0. NO. . is a degradation of transistor parameters such as saturation current (Idsat ) and threshold voltage (Vth ) [1]–[3]. Depending on the number of cycles in the stress signal. In this paper. 4(a) except that M1 is not under the NBTI stress due to high-level voltage input and that M2 is added to charge VVDD2 node to the voltage level of VVDD1 node in Fig. tox = 1. 2. 10. OCTOBER 2010 Fig. During the stress period. phase comparator. 2(b) shows the Vth -degradation of a stressed NMOS device (45 nm technology. 4(b) presents an inverter chain which has the same structure as Fig. Fig. λ is the hot electron mean free path. 4(a) in stress mode. The Vth -degradation due to HCI during stress time as follows: q K Cox Eox E0 exp − ϕit qλEm tn III. while Fig. and initial Vth0 = 0.800 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS. ϕit is the trap generation energy. 57.622 V) under a dynamic operation condition. 4(a) shows an NBTI sensor circuit to detect the longterm Vth -degradation due to NBTI after n-cycles of stress and recovery where M1 PMOS is under the NBTI stress through M5 and M6 (transmission gate) during stress period. M1 will age due only to the NBTI stress. VOL. 3. the threshold voltage of M1 in ΔVth = Qi exp (4) where Qi is the inversion charge. The core circuits for detecting Vth degradation due to NBTI and HCI effect consist of NBTI/HCI generating (stressed) circuit. (b) Vth dependence on HCI effect [9]. 3. (b) Reference circuit of the NBTI sensor circuit. E0 is a processdependent factor. The proposed circuits measure the threshold voltage of a NBTI/HCI stressed MOSFET device and a NBTI/HCI unstressed MOSFET device and they digitalize the difference in the measured threshold voltages. 4. Fig. the stress signal is asserted to M1 through M5 and M6 in Fig. Block diagram of the proposed monitoring circuit. Circuit schematic of NBTI sensor circuit: (a) NBTI generating circuit. reference (unstressed) circuit. 4(a). Fig. O N -C HIP NBTI/HCI S ENSOR C IRCUITS This section presents new on-chip NBTI/HCI sensor circuits based on the aforementioned NBTI and HCI models. in which the threshold voltage of the stressed NMOS device shifts up as the actual stress time (not aging time but switching time) increases.9 nm. Fig.45. [8]. due to the same circuit structure in Fig. 5(a). which makes the M1 device operated as a NMOS diode structure. Therefore. we changed the temperature when the number of cycles is 6E15. M2 is connected to ground during the stress mode and the VVDD1 and VVDD2 node simultaneously keep “0” voltage during the stress period. 5(b)] is not affected by other variation effects. In addition. 5. The low-voltage output of each inverter chain is converted to the high voltage using a level converter circuit. In addition. once the Enable signal is triggered. At the same time. The phase-to-digital converter in the HCI monitor is identical with the circuit of the NBTI sensor circuit as shown in Fig. M1 is disconnected from the stress signal in Fig. and the propagation time of the start signal through an inverter chain is determined by V DD–[Vth of (unstressed M1)]. Circuit schematic of HCI sensor circuit: (a) HCI generating circuit. the arrival time difference [T 1 − T 2 = T d in Fig. which means that the proposed sensor circuit is almost independent of the temperature variation as expected. each T flip-flop in Fig. which constructs a PMOS diode structure and generates the threshold voltage of the stressed M1. Depending on the Vth shift by the NBTI stress. E XPERIMENTAL R ESULTS The proposed circuits have been designed and evaluated using a 45 nm predictive technology model (VDD = 1. .: ON-CHIP AGING SENSOR CIRCUITS FOR RELIABLE NANOMETER MOSFET DIGITAL CIRCUITS 801 Fig. 5(b) shows an example of the signal waveforms in the NBTI sensor circuit during the measurement mode. The Enable signal in Fig.5 duty cycle and 2 GHz frequency. the propagation time of the start signal through an inverter chain is determined. except that M1 is changed from PMOS to NMOS and the transmission gate consisting of M3 and M4 connects the input of M1 to the supply voltage VDD. 6(a) and (b). IV.01 V.1) and predictive NBTI/HCI models. For a long term NBTI-stress simulation. whereas the M1 device in Fig. such as temperature variation. As shown in Fig. M2 is turned off. Fig. (b) Waveform during measurement mode. the same circuit structure as the aforementioned NBTI sensor circuit would be deployed as shown in Fig. 5(b)] and the amount of the time difference (phase) is directly correlated with the threshold voltage of each M1 device due to the almost linear relationship between timing delay and supply voltage of the inverter chain. a phase comparator is employed to generate a pulse signal (Enable) as shown in Fig. 5(a) starts to count the Osc signal and each OUT signal in the counter can be employed as control signals in adaptive systems for overcoming the performance degradation due to aging phenomena. 5(a). Fig. 7(a) shows the VVDD1 in Fig. 4(a) and (b). The HCI stress time for these experiments is 400 μsec which is not age (run time) but actual stress time (switching time). Once each output signal is triggered. the unstressed M1 of Fig. 4(a). 6. In order to show the weak dependence of the proposed NBTI monitor on temperature variation. During the measurement period. whereas being connected to VVDD1 through M3 and M4. 4(a) is changed. Fig. 4(a) and (b) would have different arrival times [T1 and T2 in Fig. the VVDD1 almost linearly decreases and the arrival time (phase) difference increases (reversely proportional to the VVDD1 decrease). Block diagram of the phase-to-digital converter: (a) Circuit schematic. 4(b) is connected to VVDD2 during the measurement mode. (b) Reference circuit of the HCI sensor circuit. 7(b). 4 and phase dependence on the NBTI stress: as the number of cycles increases. we have increased the number of cycles in the stressed input-signal with 0. Fig. 4(b) does not have any stress effect. the phase difference variation depending on temperature is less than 1 ns and the voltage difference (V V DD2 − V V DD1) variation is less than 0. to make a high drain-to-source voltage in the M1 device. two output signals of Fig.KIM et al. In order to monitor Vth -degradation due to HCI stress during stress period. 5(a) triggers the ring oscillator which is only operated at the high-voltage level of the Enable signal. VVDD1 voltage is changed from VDD voltage to V DD–[Vth of (stressed M1)] voltage. On the other hand. At the same time. “Compact modeling of MOSFET wearout mechanisms for circuit-reliability simulation. and C.” IEEE Trans. vol. no. 8 shows the implemented layout of the proposed sensor circuits. 2006. Apr. Sylvester. “Design challenges at 65 nm and beyond. Jul. and C. pp. asu.” IEEE J. B. It is demonstrated that the new sensor circuits achieve lower power and smaller area than other circuits. Conf. [3] X.58 × 7. Autom. 10. Singh. and D.86 μW during measurement mode on average. 2008. 2008. pp.. Solid-State Circuits. Device Mater.57 μW during stress mode and 30. Keane. Moreover.” in Proc. Fig. “Compact in-situ sensors for monitoring negative bias-temperature-instability effect and oxide degradation. Blaauw. Vattikonda. (b) Temperature variation of NBTI sensor circuit. D.. the post-layout power consumption is 18.01 V threshold voltage shift. Symp. [7] S. “Predictive modeling of the NBTI effect for reliability. IEEE Reliab. Jun. J.97 μm2 . “Reliability challenges for 45 nm and beyond. pp. Li. W. 57. Fig. 6 decrease over the stress (switching) time.eas. pp.. Kahng.” in Proc. pp. 1. Roux. NO. where the difference increases in inverse relation to VVDD1 in Fig. and TDDB. 7(d) shows that the HCI monitor also has weak dependence of the proposed HCI monitor on temperature variation. Federspiel. H. 6) and phase dependence on HCI stress. “Silicon odometer: An on-chip reliability monitor for measuring frequency degradation of digital circuits. [4] J. The simulation results show that the proposed circuits achieve high phase-difference resolution as well as low temperature dependence.” in Proc. Kim. 4.. V. IEEE ISSCC Conf. 7(c) presents the phase-difference dependence on the HCI stress. 2007. 874–880. 98–121. Y. W. 189–192. 281–287. vol. Post-layout simulation results of the proposed circuits: (a) VVDD1 (in Fig. P. and S. [6] E. Mar. “Correction of selfheating for HCI lifetime prediction.” in Proc. 410–411. [5] T. whose size is 18. Kim. and J.” in Proc. Cao. 1–2. 4) and phase dependence on NBTI stress. 2008. For a good adaptive design technique for overcoming the performance degradation due to aging phenomena. Karl. and P. R. 43. Sep. Also. [8] J. IEEE CICC Conf. our accurate sensor circuits would be a practicable solution in nanoscale CMOS circuits. Bernstein. Fig. M. [Online].edu/~ptm/ Fig. OCTOBER 2010 TABLE I C OMPARISON OF R ELIABILITY M ONITORING C IRCUITS 0. C ONCLUSION This paper proposes novel on-chip fully digital sensor circuits in a 45 nm technology to monitor the Vth -degradation due to the long term NBTI/HCI stress. IEEE VLSI Circuits Conf. Qin. Wang. Persaud. Persaud.” in Proc. Available: http://www. D.. where the actual stress (switching) time is 120 μsec. [9] Reliability PTM Model Website. IEEE Des. 8. Roy. “An all-in-one silicon odometer for separately monitoring HCI. Rel. 2006. IEEE DATE Conf. Implemented layout of the proposed sensor circuits. Phys. R. Mar. X. Vrudhula.802 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS. VOL. R EFERENCES [1] A. Apr. 8. (c) VVDD1(in Fig.. 108–109. [2] J. pp. no. 2009. D. Kim. McPherson. pp. respectively. the NBTI/HCI sensor circuits achieve a direct correlation between the threshold voltage degradation and the phase difference (between the output of NBTI/HCI generating circuit and the output of reference circuit): the phase-difference resolution is 1 ns per . The simulation results of the proposed sensor circuits are compared with those of previously published reliability sensor circuits as shown in Table I. pp. BTI. (d) Temperature variation of HCI sensor circuit. 7. Bhardwaj. 2007. 176–181.. the Fig. B. Abramowitz. H. Feb.