TMS320C5X Architecture Details2/21/2014 Abhishek Kumar Srivastava 1 Categories of Texas Instruments DSP’s What is Word?? A word is basically a fixed sized group of bits that are handled as a unit by the instruction set and/or hardware of the processor. The majority of the registers in a processor are usually word sized and the largest piece of data that can be transferred to and from the working memory in a single operation is a word in many (not all) architectures. 2/21/2014 Abhishek Kumar Srivastava 2 TMS320 Family Overview • The TMS320 family consists of two types of single-chip DSPs: 16-bit fixed point and 32-bit floating-point. • These DSPs possess two unique qualities: the operational flexibility of high-speed controllers and the numerical capability of array processors (vector processor). • Combining these two qualities, the TMS320 processors are inexpensive alternatives to custom-fabricated VLSI and multichip bit-slice processors. 2/21/2014 Abhishek Kumar Srivastava 3 • The following characteristics make this family the ideal choice for a wide range of processing applications: i. High-speed performance iv. Innovative. Very flexible instruction set ii. parallel architectural design v. Inherent operational flexibility iii. Cost-effectiveness 2/21/2014 Abhishek Kumar Srivastava 4 . ’C57. • The ’C5x is designed to execute up to 50 million instructions per second (MIPS). ’C56. ’C53. which are fabricated by CMOS integrated-circuit technology. on-chip peripherals. and a highly specialized instruction set. 2/21/2014 Abhishek Kumar Srivastava 5 .TMS320C5x Overview • The ’C5x generation consists of the ’C50. ’C52. ’C53S. a CPU with application-specific hardware logic. on-chip memory. ’C51. and ’C57S DSPs. • The operational flexibility and speed of the ’C5x are the result of combining an advanced Harvard architecture (which has separate buses for program memory and data memory). and ’C2xx DSPs for fast and easy performance upgrades 5. Modular architectural design for fast development of spin-off devices (Spin-off product is a new product which uses the brand name of another product which already has a well-developed image). Enhanced instruction set for faster algorithms and for optimized high-level language operation 6. Advanced integrated-circuit processing technology for increased performance and low power consumption 4. Reduced power consumption 2/21/2014 Abhishek Kumar Srivastava 6 . 3. ’C2x.Advantages of ‘C5x devices 1. Source code compatibility with ’C1x. Enhanced TMS320 architectural design for increased performance and versatility 2. 2/21/2014 Abhishek Kumar Srivastava 7 . 2/21/2014 Abhishek Kumar Srivastava 8 . added to. 2/21/2014 Abhishek Kumar Srivastava 9 . • In addition. repeated operations. at the same time. a new address can be generated (program bus). the ’C5x includes the control mechanisms to manage interrupts.Bus Structure • Separate program and data buses allow simultaneous access to program instructions and data. while data is multiplied (multiplier). logic. a previous product can be loaded into. • Such parallelism supports a powerful set of arithmetic. providing a high degree of parallelism. and function calling. or subtracted from the accumulator and. and bit-manipulation operations that can all be performed in a single machine cycle. • For example. Program bus (PB) 2. Data read address bus (DAB) 2/21/2014 Abhishek Kumar Srivastava 10 . Data read bus (DB) 4. Program address bus (PAB) 3.• The ’C5x architecture is built around four major buses: 1. • The DB interconnects various elements of the CPU to data memory space. • The PB also carries the instruction code and immediate operands from program memory space to the CPU. • DAB: Bus that provides the data address used by CPU. 2/21/2014 Abhishek Kumar Srivastava 11 .• The PAB provides addresses of program memory space for both reads and writes. • It is an internal bus that carries data from data memory to the central arithmetic logic unit (CALU) and the auxiliary register arithmetic unit (ARAU). In simple words. • PAB—provide program address of program memory to CPU • PB—provide instructions and operands from program memory to CPU • DAB—provide data address from data memory to CPU • DB—provide data from data memory to CPU • The program and data buses can work together to transfer data from on-chip data memory and internal or external program memory to the multiplier for single-cycle multiply/accumulate operations. 2/21/2014 Abhishek Kumar Srivastava 12 . Memory-mapped registers 5.Central Processing Unit (CPU) • The ’C5x CPU consists of these elements: 1. Central arithmetic logic unit (CALU) 2. Auxiliary register arithmetic unit (ARAU) 4. Parallel logic unit (PLU) 3. Program controller 2/21/2014 Abhishek Kumar Srivastava 13 . • The ’C5x CPU maintains source-code compatibility with the ’C1x and ’C2x generations while achieving high performance and greater versatility. additional scaling capabilities. • Improvements include a 32-bit accumulator buffer (A register that temporarily stores the contents of the accumulator (ACC)). 2/21/2014 Abhishek Kumar Srivastava 14 . and a host of new instructions. • Data management has been improved through the use of new block move instructions (16 bit register use to move block of data) and memory-mapped register instructions. Additional shifters at the outputs of both the accumulator and the product register (PREG) • PREG—A register that holds the output from the multiplier. 16-bit x 16-bit multiplier 2. • The CALU consists of these elements: 1. 32-bit accumulator (ACC) 4.Central Arithmetic Logic Unit (CALU) • The CPU uses the CALU to perform 2’s complement arithmetic. 2/21/2014 Abhishek Kumar Srivastava 15 . 32-bit arithmetic logic unit (ALU) 3. • The high and low words of the PREG can be accessed individually. 32-bit accumulator buffer (ACCB) 5. or toggle bits in a status register. clear. • Results of a PLU function are written back to the original data memory location. 2/21/2014 Abhishek Kumar Srivastava 16 . but in parallel with. control register. which operates separately from.Parallel Logic Unit (PLU) • The CPU includes an independent PLU. • The PLU performs Boolean operations or the bit manipulations required of high-speed controllers. test. the ALU. without affecting the contents of the ACC or PREG. • The PLU can set. or any data memory location. and auxiliary register compare register (ARCR). 2/21/2014 Abhishek Kumar Srivastava 17 . • Auxiliary registers (ARs): Register file of eight auxiliary registers (16-bit) used for temporary data storage or indirect addressing of data memory. index register (INDX).Auxiliary Register Arithmetic Unit (ARAU) • The CPU includes an unsigned 16-bit arithmetic logic unit that calculates indirect addresses by using inputs from the auxiliary registers (ARs). • Index register (INDX): A memory-mapped register that specifies increment sizes greater than 1 for indirect addressing updates. • The contents of these registers (AR & ARP) can also be stored in data memory or used as inputs to the CALU. 2/21/2014 Abhishek Kumar Srivastava 18 . respectively. The CMPR instruction compares the ARCR to the selected AR and places the result of the compare in the TC bit of ST1 (TC=0 if result false else TC=1).• Auxiliary register compare register (ARCR): The 16-bit ARCR is used for address boundary comparison. designating AR0 through AR7. • These registers are referenced with a 3-bit auxiliary register pointer (ARP) that is loaded with a value from 0 through 7. the address of the desired memory location is placed into the selected auxiliary register. • For indirect data memory addressing. the CALU is free for other operations in parallel. • The ARAU can auto index (auto increment or decrement) the current AR while the data memory location is being addressed and can index either by ±1 or by the contents of the INDX. or by an immediate operand (immediate data) defined in the instruction. the ACC. accessing data does not require the CALU for address manipulation.• The auxiliary registers and the ARP can be loaded from data memory. therefore. • As a result. the product register. 2/21/2014 Abhishek Kumar Srivastava 19 . • The auxiliary register file (AR0-AR7) is connected to ARAU. • The memory-mapped registers are used for indirect data address pointers. CPU status and control. • All ’C5x DSPs have 28 core CPU registers and 16 input/output (I/O) port registers but have different numbers of peripheral and reserved registers (in general. temporary storage. 17 peripheral registers. 2/21/2014 Abhishek Kumar Srivastava 20 . and 35 reserved registers. or integer arithmetic processing through the ARAU.Memory-Mapped Registers (MMR) • The ’C5x has 96 registers mapped into page 0 of the data memory space.). they can be written to and read from in the same way as any other data memory location. • Since the memory-mapped registers are a component of the data memory space. stores the status of CPU operations. and decodes the conditional operations. • Parallelism of architecture lets the ’C5x perform three concurrent memory operations (using DARAM not SARAM) in any given machine cycle: fetch an instruction.Program Controller • The program controller contains logic circuitry that decodes the operational instructions. 2/21/2014 Abhishek Kumar Srivastava 21 . and write an operand. manages the CPU pipeline. read an operand. Address generation logic 5. (8 X 16)-bit Hardware stack 4. 16 bit Status registers ST0.• The program controller consists of these elements: 1. Instruction register 6. Interrupt flag register and interrupt mask register 2/21/2014 Abhishek Kumar Srivastava 22 . 16 bit Program counter (PC) 2. ST1. processor mode status register (PMST) and circular buffer control register (CBCR) 3. • PMST: A MMR that contains status and control bits. 2/21/2014 Abhishek Kumar Srivastava 23 . • The PMST has an associated 1-level deep shadow register stack for automatic context-saving when an interrupt trap is taken. • The PMST resides in the memory-mapped register space of data memory page 0. • The PMST can be acted upon directly by the CALU and the PLU. This bit enables/disables the internal program address to be visible at the address pins. Abhishek Kumar Srivastava 24 0 BRAF 2/21/2014 0 . This bit indicates that a block repeat is currently active/de-active.Bit 15—11 Name IPTR RST value 00000 Function Interrupt vector pointer bits. Address visibility bit. 4 RAM 0 3 MP/MC This bit enables/disables the on-chip ROM to be addressable in program memory space. 0 NDX=0 Any ’C2x-compatible instruction that modifies or writes AR0 also modifies or writes the INDX and ARCR NDX=1 reverse of previous statement 2 NDX 1 TRM 0 TRM=0 Any ’C2x-compatible instruction that loads TREG0 also loads TREG1 and TREG2 TRM=1 reverse of previous statement Block repeat active flag bit. 7 AVIS 0 5 OVLY 0 This bit enables/disables the on-chip single-access RAM (SARAM) to be addressable in data memory space This bit enables/disables the on-chip single-access RAM (SARAM) to be addressable in program memory space. These bits select any of 32 2K-word pages where the interrupt vectors reside. • CBCR: A MMR that enables/disables the circular buffers (CENB1 and CENB2 bits) and defines which auxiliary registers (AR selected by CAR1 for circular buffer 1 and CAR2 for circular buffer 2) are mapped to the circular buffers. • Hardware Stack: The stack which is 16 bits wide and 8 levels deep. is accessible via the PUSH and POP instructions. 2/21/2014 Abhishek Kumar Srivastava 25 . • Therefore. 2/21/2014 Abhishek Kumar Srivastava 26 . and bottom (eighth) location of the stack is lost. the previous contents of each level are pushed down.• Whenever the contents of the PC are pushed onto the top of the stack (TOS). data is lost if more than eight successive pushes occur before a pop. • Address generation logic (Program & data): Logic circuitry that generates the addresses for program memory/data memory reads and writes • Can generate one address per machine cycle. • Interrupt flag register (IFR): A memory-mapped register that indicates pending interrupts. • Writing a 1 to any IMR bit position enables the corresponding interrupt (when INTM (interrupt mode bit) = 0). 2/21/2014 Abhishek Kumar Srivastava 27 . • Interrupt mask register (IMR): A memory-mapped register used to mask external and internal interrupts. 15-13 ARP 12 OV 11 OVM 10 1 9 INTM 8-0 DP Fig: Status register 0 (ST0) bit assignment 2/21/2014 Abhishek Kumar Srivastava 28 . • These registers are restored upon a return from interrupt.Some flags in Status Register • The status registers can be stored into data memory and loaded from data memory. • The ST0 and ST1 each have an associated 1-level deep shadow register stack for automatic context-saving when an interrupt TRAP (software interrupt.) is taken. thereby allowing the ‘C5X status to be saved and restored for subroutines. transfer control to program memory location 22h. When the ARP is loaded. An overflowed result is loaded into the accumulator without modification. 2/21/2014 Abhishek Kumar Srivastava 29 . An overflowed result is loaded into the accumulator with either the most positive (00 7FFF FFFFh) or the most negative value (FF 8000 0000h). the previous ARP value is copied to the auxiliary register buffer (ARB) in ST1. • OVM=0.• Significance of various bits of ST0 and ST1 are: a) ARP (Auxiliary Register Pointer) These bits selects the AR to be used in indirect addressing. • OVM=1. b) OVM (Overflow mode) bit enables/disables accumulator overflow saturation mode in ALU. 2/21/2014 Abhishek Kumar Srivastava 30 .d) OV (overflow) flag bit indicates arithmetic operation overflow in the ALU d) INTM (Interrupt Mode) bit globally masks or enables all interrupts. • DP bits (0-8 bits) are concatenated with the 7 LSBs of an instruction word to form a direct memory address of 16 bits (like 8051 2k page access of ROM). • The INTM bit has no effect on the non-maskable RS and NMI interrupts. e) DP (Data memory page pointer) bits specify the address of current data memory page. • Whenever the ARP is loaded. the previous ARP value is copied to the ARB. • When the ARB is loaded using the LST #1 instruction. the same value is also copied to the ARP.Status Register 1 (ST1) • ARB (Auxiliary Register Buffer): This three bit field holds the previous value contained in the ARP in ST0. 15-13 ARB 2/21/2014 12 CNF 11 TC 10 SXM 9 C 8-7 11 6 HM 5 1 4 XF 3-2 11 1-0 PM 31 Fig: Status register 1 (ST 1) bit assignment Abhishek Kumar Srivastava . • LST--Load data memory value to Status Register 0 or 1. except when using the LST #0 instruction. • Useful when restoring context (not using automatic context save) in a subroutine that modifies the current ARP. 2/21/2014 Abhishek Kumar Srivastava 32 . • CNF (configuration control bit) can be modified by LST #1 instruction. • When CNF=0. on chip DRAM block 0 is mapped into program memory space (SETC CNF). CNF on-chip RAM configuration control bit This 1 bit field enables the on-chip dual access RAM block 0 (DARAM B0) to be addressable in data memory space or program memory space. • When CNF=1. on chip DRAM block 0 is mapped into data memory space (CLRC CNF). • DARAM: Memory space that can be read from and written to in the same clock cycle. SFR performs a logical shift. shifting out the LSBs and shifting in a 0 for the MSB 2/21/2014 Abhishek Kumar Srivastava 33 . maintaining the sign of the ACC data. TC Test/control flag bit 1 bit flag stores the result of ALU or parallel logic unit (PLU) test bit operations. SXM sign-extension mode bit 1-bit field enables/ disables sign extension of an arithmetic operation. • When SXM = 1. call and return instructions are to be executed. When SXM = 0. • The SXM bit affects the definition of the shift accumulator right (SFR) instruction. SFR performs an arithmetic right shift. • The status of the TC determines if the condition branch. C Carry bit 1-bit field indicates an arithmetic operation carry or borrow in the ALU. XF is set high at device reset. HM Hold mode bit 1 bit field determines whether the CPU stops or continue execution when acknowledging an active HOLD signal (from DMA). The XF pin signals to external devices via software. 2/21/2014 Abhishek Kumar Srivastava 34 . Shift or rotate affect the C bit. XF pin status bit 1 bit determines the level of the external flag (XF) output pin. PM bits B1 0 0 1 1 B0 0 1 0 1 Function P-SCALER mode for PREG output No shift Left-shifted 1 bit. Product always sign extended 2/21/2014 Abhishek Kumar Srivastava 35 . 4 LSB zero filled Right-shifted 6 bits. LSB zero filled Left-shifted 4 bits. 6 LSB lost.• PM product shift mode bits 2 bit field determines the product shifter (P-SCALER) mode and shift value for the PREG (product register) output into the ALU. Program read-only memory (ROM) 2. Data/program dual-access RAM (DARAM) 3. 64K-word local data memory space. Data/program single-access RAM (SARAM) • The ’C5x has a total address range of 224K words x 16 bits. and 4. 64K-word input/ output ports. 3. 32K-word global data memory space. 64K-word program memory space. • The memory space is divided into four individually selectable memory segments: 1.On-Chip Memory • The ’C5x architecture contains a considerable amount of onchip memory to aid in system performance and integration: 1. 2/21/2014 Abhishek Kumar Srivastava 36 . 2. • The ’C50 and ’C57S DSPs have boot loader code (main function of the boot loader is to transfer code from an external source to the program memory at power-up) resident in the on-chip ROM. the boot ROM space can be removed from program memory space by setting the MP/MC bit in the (PMST) processor mode status register. • Once the custom program has been booted into RAM.Program ROM • All ’C5x DSPs carry a 16-bit on-chip maskable programmable ROM. • This memory is used for booting program code from slower external ROM or EPROM to fast on-chip or external RAM. all other ’C5x DSPs offer the boot loader code as an option. 2/21/2014 Abhishek Kumar Srivastava 37 . • The on-chip ROM is selected at reset by driving the MP/MC pin low. you can submit the ROM code to Texas Instruments for implementation into your device. • The on-chip ROM may be configured with or without boot loader code. the ’C5x devices start execution from off-chip memory. the on-chip ROM is intended for your specific program. • However. 2/21/2014 Abhishek Kumar Srivastava 38 . • Once the program is in its final form. • If the on-chip ROM is not selected. the TMS320 becomes a microcomputer that executes customized programs from the on-chip ROM. the code can be submitted to Texas Instruments for masking into the on-chip program ROM. 2/21/2014 Abhishek Kumar Srivastava 39 . • In this mode of operation. test. • At that time. the TMS320 acts as a standard microprocessor by using external program memory. • When the algorithm has been finalized. • Should the code need changing or upgrading.• The microprocessor/microcomputer (MP/MC) mode is available on all ROM-coded TMS320 DSP devices when accesses to either on-chip or off-chip memory are required. the TMS320 can once again be used in the microprocessor mode. and refine a system application. • The microprocessor mode is used to develop. • DARAM blocks B1 and B2 are always configured as data memory. 512-word data DARAM block B1.Data/Program Dual-Access RAM (DARAM) • All ’C5x DSPs carry a 1056-word x 16-bit on-chip dual-access RAM (DARAM). • The DARAM is divided into three individually selectable memory blocks: 512-word data or program DARAM block B0. DARAM block B0 can be configured by software as data or program memory. can be used to store programs as well. • The DARAM is primarily intended to store data values but. 2/21/2014 Abhishek Kumar Srivastava 40 . and 32-word data DARAM block B2. when needed. however. Decode.• DARAM improves the operational speed of the ’C5x CPU. the second instruction could be reading data at the same time the first instruction is writing data. • Hence. the CPU reads data on the third stage and writes data on the fourth stage. • In this pipeline. Execute. • The CPU operates with a 4-deep pipeline (Fetch. for a given instruction sequence. Write Back). • The dual data buses (DB and DAB) allow the CPU to read from and write to DARAM in the same machine cycle. 2/21/2014 Abhishek Kumar Srivastava 41 . Data/Program Single-Access RAM • All ’C5x DSPs except the ’C52 carry a 16-bit on-chip singleaccess RAM (SARAM) of various sizes. once it is loaded into the on-chip SARAM. • Code can be booted from an off-chip ROM and then executed at full speed. • The SARAM can be configured by software in one of three ways: All SARAM configured as data memory All SARAM configured as program memory SARAM configured as both data memory and program memory 2/21/2014 Abhishek Kumar Srivastava 42 . • However.• The SARAM is divided into 1K. • In other words. • All ’C5x CPUs support parallel accesses to these SARAM blocks. the CPU can read from or write to one SARAM block while accessing another SARAM block. 2/21/2014 Abhishek Kumar Srivastava 43 .and/or 2K-word blocks contiguous in address memory space. one SARAM block can be accessed only once per machine cycle. 2/21/2014 Abhishek Kumar Srivastava 44 . an instruction fetch and data fetch that could be performed in one machine cycle with DARAM (using PB and DB) may take two machine cycles with SARAM. • However. because of simultaneous program and data mapping.• SARAM supports more flexible address mapping than DARAM because SARAM can be mapped to both program and data memory space simultaneously. • The ’C5x DSP on-chip peripherals available are: Clock generator Hardware timer Software-programmable wait-state generators Parallel I/O ports Host port interface (HPI) Serial port Buffered serial port (BSP) Time-division multiplexed (TDM) serial port User-maskable interrupts 2/21/2014 Abhishek Kumar Srivastava 45 .On-Chip Peripherals • All ’C5x DSPs have the same CPU structure. they have different on-chip peripherals connected to their CPUs. however. 2/21/2014 Abhishek Kumar Srivastava 46 . so you can use a clock source with a lower frequency than that of the CPU.Clock Generator • The clock generator consists of an internal oscillator and a phase-locked loop (PLL) circuit.6 MHz. • The PLL circuit can generate an internal CPU clock by multiplying the clock source by a specific factor. • The clock generator can be driven internally by a crystal resonator circuit or driven externally by a clock source. • The PLL has a maximum operating frequency of 28. • This circuit compares the phase of the input signal with the phase of the signal derived from its output oscillator and adjusts the frequency of its oscillator to keep the phases matched.PLL • A phase-locked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input "reference" signal. 2/21/2014 Abhishek Kumar Srivastava 47 . • It is an electronic circuit consisting of a variable frequency oscillator and a phase detector. • The signal from the phase detector is used to control the oscillator in a feedback loop. • Consequently, a phase-locked loop can track an input frequency, or it can generate a frequency that is a multiple of the input frequency. • The former property is used for demodulation, and the latter property is used for indirect frequency synthesis. • Phase-locked loops are widely employed in radio, telecommunications, computers and other electronic applications. 2/21/2014 Abhishek Kumar Srivastava 48 2/21/2014 Abhishek Kumar Srivastava 49 Hardware Timer • A 16-bit hardware timer with a 4-bit pre-scaler is available. • This programmable timer clocks at a rate that is between 1/2 and 1/32 of the machine cycle rate (CLKOUT1), depending upon the timer’s divide-down ratio (in 8051, timer’s frequency is 1/12 of crystal freq.). • CLKOUT1: Master clock output signal. This signal cycles at the machine-cycle rate of the CPU. The frequency of CLKOUT1 is one-half the crystal oscillating frequency or CLKIN rate (2040 MHz). Some times, CLKOUT rate=CLKIN rate. • The internal machine cycle is bounded by the rising edges of this signal. • The timer can be stopped, restarted, reset, or disabled by specific status bits. 2/21/2014 Abhishek Kumar Srivastava 50 the internal clocks to the timer are shut off. 2/21/2014 Abhishek Kumar Srivastava 51 . • A timer interrupt (TINT) is generated each time the counter decrements to 0. allowing the circuit to run in a low-power mode of operation. • When the timer is stopped (TSS = 1). • The timer provides a convenient means of performing periodic I/O or other functions.PRD=timer period register Synchronized reset Timer reload bit TIM= timer counter register specifies current count value PSC=specify count for timer Timer stop status Timer interrupt Timer output • The timer is driven by a pre-scaler which is decremented by 1 at every CLKOUT1 cycle. 2/21/2014 Abhishek Kumar Srivastava 52 . 2/21/2014 Abhishek Kumar Srivastava 53 . Software-Programmable Wait-State Generators • Software-programmable wait-state logic is incorporated in ’C5x DSPs allowing wait-state generation without any external hardware for interfacing with slower off-chip memory and I/O devices. • This feature consists of multiple wait state generating circuits. 2/21/2014 Abhishek Kumar Srivastava 54 . • Each circuit is user-programmable to operate in different wait states for off-chip memory accesses. sixteen of these ports are memory-mapped in data memory space page 0. • The IS signal indicates a read or write operation through an I/O port. • Each of the I/O ports can be addressed by the IN or the OUT instruction.Parallel I/O Ports • A 16-bit parallel I/O ports are available. • The memory-mapped I/O ports can be accessed with any instruction that reads from or writes to data memory. 2/21/2014 Abhishek Kumar Srivastava 55 . • The ’C5x can easily interface with external I/O devices through the I/O ports while requiring minimal off-chip address decoding circuits. 2/21/2014 Abhishek Kumar Srivastava 56 .Host Port Interface (HPI) • The HPI available on the ’C57S and ’LC57 is an 8-bit parallel I/O port that provides an interface to a host processor. • Information is exchanged between the DSP and the host processor through on-chip memory that is accessible to both the host processor and the ’C57. 2/21/2014 Abhishek Kumar Srivastava 57 . full-duplexed serial port interface that provides direct communication with serial devices such as codecs. a time-division multiplexed (TDM) serial port. serial analog-to-digital (A/D) converters. • The serial port is capable of operating at up to one fourth the machine cycle rate (CLKOUT1). • Data is framed either as bytes or as words. • Each ’C5x contains at least one general-purpose. 2/21/2014 Abhishek Kumar Srivastava 58 . and a buffered serial port (BSP).Serial Port • Three different kinds of serial ports are available: a general-purpose serial port. and other serial systems. • The serial port transmitter and receiver are doublebuffered and individually controlled by maskable external interrupt signals. highspeed synchronous. double buffered serial port and an auto buffering unit (ABU). • The ABU supports high-speed data transfer and reduces interrupt latencies. • The BSP provides flexibility on the data stream length.Buffered Serial Port (BSP) • The BSP available on the ’C56 and ’C57 devices is a full-duplexed. 2/21/2014 Abhishek Kumar Srivastava 59 . and ’C53 devices is a full duplexed serial port that can be configured by software either for synchronous operations or for timedivision multiplexed operations. ’C51. 2/21/2014 Abhishek Kumar Srivastava 60 . • The TDM serial port is commonly used in multiprocessor applications.TDM Serial Port • The TDM serial port available on the ’C50. 2/21/2014 Abhishek Kumar Srivastava 61 . the CPU registers’ contents are restored. • When a return from interrupt instruction is executed. the contents of the program counter are saved on an 8-level hardware stack.User-Maskable Interrupts • Four external interrupt lines (INT1–INT4) and five internal interrupts. a timer interrupt and four serial port interrupts. • When an interrupt service routine (ISR) is executed. are user maskable. and the contents of eleven specific CPU registers are automatically saved (shadowed) on a 1-level-deep stack (shadow registers). ’LC51.Test/Emulation • On the ’C50. 2/21/2014 Abhishek Kumar Srivastava 62 . • It can be used to test pin-to-pin continuity and to perform operational tests on devices that are peripheral to the ’C5x. ’C51. • This logic provides the boundary scan to and from the interfacing devices. ’C57S and ’LC57S. ’LC53. ’LC50.1 (JTAG) interface with boundary scan capability is used for emulation and test. an IEEE standard 1149. ’C53. Thank you for listening !! 2/21/2014 Abhishek Kumar Srivastava 63 .