User`s ManualMTK-85 8085 Microprocessor Training Kit Copyright 2005 by Wichit Sirichote August 22. 2005 WWW.MTK-85.COM 2 Contents Overview.................................3 Hardware Features SoItware Features Getting Started.............................4 DC Adapter LED Display and Keypad RESET ADDR DATA INC DEC HOME ALT RUN STEP MOD Program #1 Program #2 Program #3 Connecting Terminal..........................9 Command A` Command C` Command D` Command E` Command F` Command H` Command I` Command J` Command K` Command L` Command M` Command N` Command Q` Command R` Command S` Command W` Command SPACE BAR` Hardware...............................16 CPU Memory GPIO Programmable Port 8255 Programmable Counter 8254 Headers and Connectors Interrupt Test Button Technical SpeciIications Monitor Call Number-NVRAM Bootable Appendix A LCD Driver Routines Appendix B SCAN Keyboard and Display Subroutine Appendix C UART Driver Routines Appendix D Using NVRAM Bootable Appendix E Machine Code and Mnemonics oI 8085 Instructions Appendix F Hardware Schematic 3 Overview The MTK-85 is a low-cost single board computer designed Ior selI-learning the 8085 Microprocessor. The kit enables studying Irom low level programming with direct machine code entering to high level programming with PC tools easily. A nice Ieature. single-step running. helps students learn the operation oI microprocessor instructions quickly and clearly. The user registers provide simple means to veriIy the code execution. Using a PC as the terminal. the MTK-85 can receive the Intel hex Iile and disassemble the machine code into 8085 instructions. Hardware Features: •! CPU: Mitsubishi M5M80C85AP-2 4MHz •! Memory: 32kB Monitor ROM and 32kB SRAM •! Simple I/O Port: 8-bit GPIO built with 74LS175 D-type F-F and 74LS126 Tri-state buIIer •! Programmable Ports: two 8255 chips. system and user ports •! Programmable Counter: 8254 •! UART: 16C550 compatible •! onboard I/O devices: •! 6-digit seven segment LED. •! 28-keypad. •! 4-bit dot LED indicates status oI GPIO. •! magnetic buzzer. •! Direct BUS interIace 20x4 LCD (optional). •! Serial InterIace: RS232C 9600bit/s 8-data bit no parity one stop bit •! ¹5V Power Supply: low-dropout voltage regulator with input protection •! 40-pin header Ior CPU bus •! 40-pin header Ior user port. 8255 and 8254 •! 16-pin header Ior simple GPIO port •! onboard logic probe power supply •! Test button Ior single pulse generation to the interrupt pins •! Brown-out Protection •! No iumper settings Software Features: •! Enter the machine code in hexadecimal •! Single-step execution •! Examine and modiIy user registers •! Run user code with soItware breakpoint •! Built-in LCD drivers 4 •! Download Intel Hex Iile •! Disassemble machine code into 8085 instructions •! Display user registers and disassemble the instruction aIter single-stepping •! NVRAM Bootable. runs user code when power up the board Getting Started DC Adapter The MTK-85 board requires DC power input to operate. The input voltage excepts Irom ¹6V to ¹12V. You may Iind any AC-to-DC adapter having DC iack with polarity as shown below. + - Since the onboard voltage regulator is low-dropout. so dissipation oI the voltage regulator will be (Vin-Vout) x 230mA. The minimum voltage developed across Vout and Vin is 0.2V. So to provide ¹5VDC to the logic board. we can have Vin as low as say ¹6V. With such input. the dissipation oI the voltage regulator will only be less than 250mW. LM2940-5.0 VI N VOUT 230mA COMMON GND + 5V The common AC-to-DC adapters mostly have ¹12VDC output. You can use it also. The maximum current is 230mA at ¹12VDC input so we can use any adapters that provide at least 300mA. When power up the board. the cold message running text 8085 will show on 7-segment LED and the onboard dot LED will turn on. 5 LED Display and Keypad The MTK-85 has 6 digits 7-segment LED and 28 tact switches keypad. Four digits labeled with text 'ADDRESS¨ is Ior displaying the memory address and user registers contents. Two digits labeled with text 'DATA¨ is Ior displaying the 8-bit data byte at address shown in the leIt-hand. The dot that shows 1E. indicating current mode is data entry. Typing Hex key will enter into data Iield. The onboard keypad has two groups: the leIt-hand is 16-hex key and the right-hand is 10- Iunction key. The hex key has alternate Iunctions when used with ALT key. 9 0 0 0 1 E. 16-HEX key 10-Function key Let`s see the Iunctions key as Iollows. RESET RESET is hardware reset. We can press reset to Iorce the CPU begins execution the ROM monitor at address 0000H. The reset out signal which is active high also supplied to the UART and two 8255 PPI. ADDR ADDR changes current mode to ADDRESS entry mode. The dot indicator will move to digit4. 6 DATA DATA changes current mode to DATA entry mode. The dot indicator will move to digit6. INC INC increments current address by one. The content oI new address will show in data Iield LED. DEC DEC decrements current address by one. The content oI new address will show in data Iield LED. HOME HOME brings home address back to current display. The home address is 8100H. ALT ALT enables alternate Iunctions that used with HEX key. Below is the ALT Iunction with HEX key. 0/AF displays user register AF. The Accumulator and Flag registers. 1/BC displays user register BC. 2/DE displays user register DE. 3/HL displays user register HL. 4/SP displays user register SP. 5/PC displays user register PC. 6/CY displays CARRY Ilag. 7/Z displays ZERO Ilag. 8/S displays SIGN Ilag. 9/AC displays halI CARRY Ilag. A/P displays PARITY Ilag. B/SBR sets break address. C/CBR clears break address. RUN RUN Iorces CPU to iump Irom monitor program to user program at current address. 7 STEP STEP executes one instruction at address shown in current display. MOD MOD modiIies the user registers. It was used together with ALT 0-5. Program #1 Let`s learn how the keypad helps testing your Iirst program. 9000 3C main: inr a 9001 D300 out 0 9003 C30090 jmp main This simple program increments the content oI Accumulator. send its content to the output port at location 00 then repeat it. We see that the machine code has only 6 bytes i.e. 3C. D3. 00. C3. 00. 90. Now enter the code into memory address 9000H. Step 1 Press RESET. then press key 3 and key C. The 3C byte will enter to address 9000H. Step 2 Press INC to increment address. Then repeat step1 until 90 byte was entered to address 9005H. You can use INC or DEC to check the code. you can modiIy it easily in DATA entry mode. We will begin set the value to user Accumulator beIorehand. The purpose is to clear it to zero. Press key ALT. 0/AF. display will show content oI user Accumulator and Flag register. Press key MOD. then key 0.0.0.0. The AF will be 0000. Press key STEP. the display will show next instruction to be executed at address 9001. We can examine the content oI AF by key ALT. 0/AF. We see that now Accumulator is 01. Press key STEP again. the 01 will send to onboard GPIO. The next instruction. JMP 9000H will be executed. We can press key STEP and see the value has changed on GPIO LED! 8 Instead oI execution one instruction using single step. we can run the program without stopping Ior each instruction. We will try with key RUN. Program #2 This program shows how to use key RUN to Iorce CPU iump Irom monitor program to user program. 9000 1E02 main: mvi e,2 9002 CF rst 1 9003 C30090 jmp main This program has only 6 bytes i.e.. 1E. 02. CF. C3. 00. 90. Enter the code. and press key HOME. RUN. We will see the cold message repeat running on the display. RST 1 having machine code CF is the method that used to call built-in monitor Iunctions. Register E is monitor call number. To stop program#2 running. we must press RESET key. Program #3 We can test the program with soItware breakpoint. The instruction RTS 7 having machine code FF returns control back to monitor program and save the content oI CPU registers to user registers. We can check the result in user registers easily. Here is the program that adds two BCD numbers 19H and 02H. The result will be 21H. 9000 3E19 mvi a,19h 9002 0602 mvi b,2 9004 80 add b 9005 27 daa 9006 FF rst 7 AIter enter the code. you can run it with key RUN. Check the result in Accumulator with ALT 0. In case oI testing long program. the board also provides tool that helps inserting the RST 7 instruction to the speciIied location. This tool called set break point. Suppose we want to know the result aIter add b instruction. We want to set break point at location 9005. We can do by setting the address to 9005 with key ADDR 9.0.0.5. Then press ALT B. the display will show this address was set breakpoint. Press HOME and RUN. check user AF with ALT 0. we see that aIter addition. the result in Accumulator is 1B. To clear this break address. press ALT C. The display will show 9 current address 9005. The code 27 will be restored back to address 9005. We can continue execution. press RUN. check result in AF again. we will get 21. Connecting Terminal The ROM monitor contains powerIul commands when using UART to connect a terminal. The UART drivers and serial commands are automatically conIigured when UART chip was inserted. Communication is based on 9600 bit/sec. 8 data bit. no parity and one stop bit. We can use PC running terminal emulation Ior VT100. The PC has HyperTerminal program that can emulate terminal VT100. say. There is no need to switch between standalone mode and terminal mode. The monitor control code Ior both is working concurrently. When press reset the prompt appears on screen. MTK-85 8085 MICROPROCESSOR TRAINING KIT (? HELP) 9000> Type ? Ior help menu listing. MTK-85 8085 MICROPROCESSOR TRAINING KIT (? HELP) A - ASCII code C - clear watch variables D - disassemble E - edit memory F - fill constant H - hex dump I - i/o address map J - jump to user program K - display user STACK L - load Intel hex file M - monitor call number N - new location pointer Q - quick home location R - user register display S - set value to user register W - watch variables SPACE BAR - single step ? - help menu 9000> 10 Command A` prints the hexadecimal code Ior printable ASCII characters. Command C` clears the 16-byte watch variables. The monitor provides quick access to a16-byte RAM Ior program testing. The watch variables use RAM space Irom F000- F00F. 9000> F000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9000> Command D` disassembles the machine code into 8085 instructions. 9000>disassemble... 9000 3E19 MVI A,19 9002 0602 MVI B,02 9004 80 ADD B 9005 27 DAA 9006 FF RST 7 9007 0D DCR C 9008 30 SIM 9009 FA6DFC JM FC6D 900C C8 RZ 900D 46 MOV B,M 900E 49 MOV C,C 900F 0B DCX B 9010 CEFD ACI FD 9012 89 ADC C 9013 B6 ORA M 9014 F64B ORI 4B 9016> Command E` examines and modiIy the data in memory. We can use this command to enter machine code. To view the content. uses Space key and to enter byte. press two digits. To quit iust press ENTER. 9016>edit memory location = 9000 Enter to quit, SPACE key to view content ADDR DATA 9000 [3E] 9001 [19] 39 9002 [06] 9003 [02] 19 9004 [80] 9005 [27] 9006 [FF] 9016> 11 Command F` Iills 8-bit constant to memory. The example shows Iilling byte 00 to address 9010-9020. 9016>Begin address = 9010 End address = 9020 Data = 00 9016> Command H` dumps memory. The content oI memory Irom current pointer 9010 to 908F will display in hexadecimal. The ASCII code Ior each byte will be displayed also. The dot will be displayed Ior nonprintable ASCII code. 9010> 9010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 9020 4D C2 97 CB DA DF A0 BE 9E 73 1A 34 E3 A6 83 4E M........s.4...N 9030 97 47 81 CE C1 99 98 CB 14 ED 45 DE 35 6A 7C F1 .G........E.5j|. 9040 F0 36 B2 69 CF 1D 90 90 70 F1 73 D8 C1 4F DF 56 .6.i....p.s..O.V 9050 A8 E2 30 84 76 AA C5 18 A7 84 C5 32 81 BF B9 03 ..0.v......2.... 9060 8A 13 8C FD 4A 82 B9 99 4E 24 33 9E EB 16 A8 0D ....J...N$3..... 9070 A9 31 CD B7 BB 4E 8D BE FF 5B 3C 8D EA 5E 4F 7F .1...N...[<..^O 9080 41 00 89 F3 54 BF EC BF E0 9F 72 CB 7D E8 34 7A A...T.....r.}.4z 9090> Command I` displays onboard I/O address. 9090> 00H-0FH onboard 4-bit GPIO, D0-D3=output port D4-D7=input port 10H-13H 8255 system PPI, 10H=PORTA, 11H=PORTB, 12H=PORTC, 13H=CONTROL 20H-23H 8254 programmable counter, 20H=counter0, 21H= counter1 22H=counter2, 23H control register 30H-33H 8255 user PPI, 30H=PORTA, 31H=PORTB, 32H=PORTC, 33H=CONTROL 40H-47H C16550 UART registers 9090> Command 1` iumps Irom monitor program to user program. The example shows iump to address 9000. The user register displays results aIter running the code. The RST 7 returns control back to monitor program. 9090>jump to address [9006] = 9000 12 AF=5800 BC=19F4 DE=C256 HL=9504 SP=F098 PC=9007 S=0 Z=0 AC=0 P=0 CY=0 9090> Command K` displays user STACK memory. The example below shows running instruction PUSH H. We Iirst check the user register with command r`. We see that TOP oI STACK is F098. AIter pressing SPACE BAR Ior single step. the SP is now F096. We can see the content oI STACK memory with command k. The content oI HL was saved in STACK. 9000>press r for user register display AF=5800 BC=19F4 DE=C256 HL=9504 SP=F098 PC=9000 S=0 Z=0 AC=0 P=0 CY=0 9000>press SPACE bar for single step 9000 E5 PUSH H AF=5800 BC=19F4 DE=C256 HL=9504 SP=F096 PC=9001 S=0 Z=0 AC=0 P=0 CY=0 9000>press k for STACK display ADDR DATA F096 [04] F097 [95] F098 [C0] 9000> Command L` loads Intel Hex Iile to memory. The Assembler and C compiler Ior 8085 CPU can produce standard Intel Hex Iile. The hex Iile contains machine code represented by ASCII letters. The example below uses HyperTerminal to download the hex Iile. The hex Iile is ASCII text Iile. So with HyperTerminal we can go to TransIer. Send text Iile. Or press ALT T T. the Iile browser will open asking what text Iile to be sent. We can let it show only Iile with .hex extension by typing *.hex. Then double clicks at the hex Iile. The onboard dot LED will run to indicate downloading is on going. When completed. the report will show number oI byte received and print checksum error. II no error it will show 0 errors. 9080>load Intel hex file...000005 bytes loaded 0 errors 9080> Command M` shows monitor call number. Some oI common subroutines can be called through RST 1 with Iunction number preloaded in register E. 9080> see input parameters in user manual 1Enn MVI E,function_number CF RST 1 13 00 - demo 01 - delay 02 - cold_boot 03 - scan 04 - cin 05 - cout 06 - put_str 07 - init_lcd 08 - lcd_ready 09 - clear_lcd 0A - goto_xy 0B - put_str_lcd 0C - put_ch_lcd 0D - demo2 9080> Command N` sets new location pointer at prompt. The example sets new pointer to E000 and press d` to disassemble. 9080>new location = e000 E000>disassemble... E000 53 MOV D,E E001 32DE2A STA 2ADE E004 62 MOV H,D E005 25 DCR H E006 C9 RET E007 1C INR E E008 43 MOV B,E E009 CC4A05 CZ 054A E00C 2655 MVI H,55 E00E 67 MOV H,A E00F 04 INR B E010 F3 DI E011 0E25 MVI C,25 E013 54 MOV D,H E014 AF XRA A E015 C3F0C3 JMP C3F0 E018> Command Q` sets location pointer at prompt to 9000 and sets user PC to 9000. 9000> AF=5800 BC=19F4 DE=C256 HL=9504 SP=F096 PC=9000 S=0 Z=0 AC=0 P=0 CY=0 9000> 14 Command R` displays user registers content. 9000> AF=5800 BC=19F4 DE=C256 HL=9504 SP=F098 PC=9000 S=0 Z=0 AC=0 P=0 CY=0 9000> Command S` sets value to user registers. 9013>set value to user register (enter A for AF) ? AF=0404 ff00 9013> AF=FF00 BC=19F4 DE=0434 HL=0534 SP=F096 PC=9006 S=0 Z=0 AC=0 P=0 CY=0 9013> Command W` prints watch variables. 9013> F000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Command SPACEBAR` executes the instruction at address in user PC. The instruction will show on screen with user registers result aIter execution. Suppose we write a program shown below. org 9000h xra a loop: out 0 mov h,a inr h push h pop d mov a,d jmp loop end Then translate it to machine code Iile using the Assembler program. Download hex Iile. 9000>load Intel hex file...000011 bytes loaded 0 errors 9000>disassemble... 9000 AF XRA A 9001 D300 OUT 00 9003 67 MOV H,A 9004 24 INR H 15 9005 E5 PUSH H 9006 D1 POP D 9007 7A MOV A,D 9008 C30190 JMP 9001 900B 00 NOP 900C 00 NOP 900D 00 NOP 900E 00 NOP 900F 00 NOP 9010 00 NOP 9011 00 NOP 9012 00 NOP 9013>print user register with command r AF=5800 BC=19F4 DE=C256 HL=1234 SP=F098 PC=9000 S=0 Z=0 AC=0 P=0 CY=0 9013>press SPACE key to execute instruction at 9000, we see A=00 9000 AF XRA A AF=0044 BC=19F4 DE=C256 HL=1234 SP=F098 PC=9001 S=0 Z=1 AC=0 P=1 CY=0 9013>press SPACE key, the content of A will send to GPIO 9001 D300 OUT 00 AF=0044 BC=19F4 DE=C256 HL=1234 SP=F098 PC=9003 S=0 Z=1 AC=0 P=1 CY=0 9013>press SPACE key, the content of A will copy to H 9003 67 MOV H,A AF=0044 BC=19F4 DE=C256 HL=0034 SP=F098 PC=9004 S=0 Z=1 AC=0 P=1 CY=0 9013> press SPACE key, the content of H will increment by 1 9004 24 INR H AF=0000 BC=19F4 DE=C256 HL=0134 SP=F098 PC=9005 S=0 Z=0 AC=0 P=0 CY=0 9013> press SPACE key, the content SP will decrement by 2 9005 E5 PUSH H AF=0000 BC=19F4 DE=C256 HL=0134 SP=F096 PC=9006 S=0 Z=0 AC=0 P=0 CY=0 9013> press K, to see the content of STACK memory ADDR DATA F096 [34] F097 [01] F098 [C0] 9013> press SPACE key, DE will be loaded with top of STACK 9006 D1 POP D AF=0000 BC=19F4 DE=0134 HL=0134 SP=F098 PC=9007 S=0 Z=0 AC=0 P=0 CY=0 9013> press SPACE key, the content of D will copy to A 9007 7A MOV A,D AF=0100 BC=19F4 DE=0134 HL=0134 SP=F098 PC=9008 S=0 Z=0 AC=0 P=0 CY=0 9013> press SPACE key, PC will be loaded with 9001 9008 C30190 JMP 9001 AF=0100 BC=19F4 DE=0134 HL=0134 SP=F098 PC=9001 S=0 Z=0 AC=0 P=0 CY=0 9013> press SPACE key, the content of A will send to GPIO, see LED! 9001 D300 OUT 00 AF=0100 BC=19F4 DE=0134 HL=0134 SP=F098 PC=9003 S=0 Z=0 AC=0 P=0 CY=0 16 Hardware A block diagram oI the MTK-85 board is shown below. For complete hardware schematic. see Appendix D. CPU The CPU is CMOS 80C85. The XTAL Irequency is 4MHz. The reset signal is generated by simple RC circuit. The CPU is protected by brownout circuit. In case oI power supply is dipped caused by AC supply voltage dropped. The brownout circuit detects VCC. iI it is below threshold level. it will reset the CPU. The brownout condition can emulate by using variable power supply. To test it. adiust the board VIN Irom 0-12V slowly and see the CPU can start running properly or not. Memory The board has 64kB memory. The 32kB ROM monitor 27C256 is placed at address 0000-7FFFH. And the 32kB SRAM 62256. is placed at address 8000H-FFFFH. Some oI interrupt vectors are relocated to RAM. so user can write the iump instruction to the location oI such interrupt service routine easily. Here is the location oI interrupts. 8010H RST 2 8018H RST 3 8020H RST 4 8028H RST 5 802CH RST 5.5 17 8030H RST 6 8034H RST 6.5 803CH RST 7.5 Note: 1.! RST 7 is used Ior soItware breakpoint. 2.! RST 1 is used Ior monitor Iunction call. 3.! TRAP is used Ior hardware single-step. 4.! RST 7.5 is tied to OUT0 oI 8254 programmable counter. 5. Monitor program uses last page oI RAM Ior data storage. STACK area. and monitor control Iunctions. The space is Irom F000H to F098H. GPIO GPIO provides 4-bit output port using D type F-F. 74LS175 and 4-bit input port using tri- state buIIer. 74LS126. The address is 00 Ior both ports. The low-nibble D0-D3 is output port. The higher-nibble D4-D7 is input port. The signal Irom both ports appeared at J1. 16-pin header. System Programmable Port 8255 The I/O addresses oI system port. 8255 are PORTA÷10H. PORTB÷11H. PORTC÷12H and Control Port ÷ 13H. Buzzer control pin is PORT C bit 7. To enable buzzer. write 7FH to PORTC. 18 User Programmable Port 8255 The board provides a user programmable parallel port. 8255. The 8255`s registers are mapped to I/O address Irom 30H to 33H. 30H PORTA 31H PORTB 32H PORTC 33H CONTROL PORT Programmable Counter 8254 The programmable counter. 8254 was supplied with clock signal Irom CLOCKOUT or 2MHz Ior counter0 and counter1. The internal registers oI 8254 are mapped to I/O space Irom 20H to 23H. 20H COUNTER0 21H COUNTER1 22H COUNTER2 23H CONTROL REGISTER Headers and Connectors CPU Header JP1 19 User 8255 and 8254 Header JP1 Onboard LCD Header JR1 20 RS232C DB9 male connector VB1 Interrupts Test Button The interrupt test button provides a single positive pulse that tied to CPU hardware interrupt pins. RST5.5. RST6.5 and INTR. User can select the pulse to be triggered Ior each pin by dip switch SW1. The onboard LED. D4 indicates the pulse is activated when press Test button. Technical SpeciIications CPU: CMOS 80C85 (4MHz Memory: 64kB. 32kB 27C256. 32kB 62256 I/O port: Programmable Parallel port 8255x2. 8-bit GPIO Counter: Programmable Counter 8254 UART: 16-byte FIFO TL16C550 compatible ROM monitor: 8085.asm Brownout Protection: KIA7045 Board Size: 8.90 x 8.13 inch Weight: 320g (complete components except LCD) DC Power Supply: AC-to-DC adapter 6V-12V 250mA Power consumption: 2.76W (230mA (12VDC) Monitor Call Number 00 - demo Scan 7-segment display with buIIer display pointed by HL Entry: HL Exit: none 21 01 - delay Delay subroutine using register pair DE. D is outer loop delay. E is inner loop. Entry: DE Exit: none 02 - cold_boot Display cold-boot message on 7-segment LED. Entry: none 03 - scan Scan keyboard and display one cycle. Entry: HL points the display buIIer Exit: key ÷ scan code 1 no key pressed 04 - cin Get character Irom console Entry: none Exit: A ÷ character received 05 - cout Send character to console Entry: A ÷ character to be sent Exit: none 06 - put_str Print string to console. string is terminated by 0. Entry: HL Exit: none 07 - init_lcd Initialize LCD module Entry: none Exit: none 08 - lcd_ready Wait until LCD module is ready. Entry: none Exit: none 09 - clear_lcd Clear LCD display Entry: none Exit: none 0A - goto_xy Set cursor position oI LCD Entry: HL. H ÷ x. L ÷ y 22 Exit: none 0B - put_str_lcd Print string to LCD. string is terminated by 0 Entry: HL Exit: none 0C - put_ch_lcd Print character to LCD at current cursor position Entry: A Exit: none 0D - demo2 Running GPIO LED Entry: none Exit: none NVRAM Bootable User can replace U3. SRAM with a Nonvolatile RAM Ior program storage. when the board is power oII. A JMP instruction placed at 8000H will enable NVRAM bootable. The monitor program checks the location 8000H. II it has C3 (opcode oI JMP instruction). it will iump to address 8000H. The Ieature allows application code to run easily. The monitor subroutines are still available Ior the application program. To get back to monitor mode. user can press USER1 key while press RESET. The byte C3 at location 8000H will change to 00. The sample code that demonstrates NVRAM Bootable is shown in Appendix D. 23 Appendix AOnboard LCD Driver Routines ;------------------- onboard LCD registers ----------------- command_write equ 50h command_read equ 52h data_write equ 51h data_read equ 53h busy equ 80h ;--------------------- LCD driver routines ----------------- lcd_ready: push psw lcd_ready1: in command_read ani busy jnz lcd_ready1 ; wait until lcd ready pop psw ret clear_lcd: call lcd_ready mvi a,1 out command_write exit_clear: ret init_lcd: call lcd_ready mvi a,38h out command_write call lcd_ready mvi a, 0ch out command_write call clear_lcd ret ; print ASCII text on LCD ; entry: HL pointer with 0 for end of string put_str_lcd: mov a,m ; get A from [HL] cpi 0 jnz put_str_lcd1 ret put_str_lcd1: call lcd_ready out data_write inx h jp put_str_lcd 24 ; goto_xy set cursor location on lcd ; entry: HL: H = x, L = y goto_xy: call lcd_ready mov a,l cpi 0 jnz goto_xy1 mov a,h adi 80h out command_write ret goto_xy1: cpi 1 jnz goto_xy2 mov a,h adi 0c0h out command_write ret goto_xy2: cpi 2 jnz goto_xy3 mov a,h adi 094h out command_write ret goto_xy3: cpi 3 jnz goto_xy4 mov a,h adi 0d4h out command_write ret goto_xy4: ret ; put_ch_lcd put character to lcd ; entry: A put_ch_lcd: call lcd_ready out data_write ret 25 Appendix B Subroutine Scan keyboard and Display ; subroutine scan keyboard and display ; entry: hl pointer to display buffer ; exit: key = scan code ; -1 no key pressed ; scan: push h push b push d mvi c,6 ; for 6-digit LED mvi e,0 ; digit scan code appears at 4-to-10 decoder mvi d,0 ; key position mvi a,0ffh ; put -1 to key sta key ; key = -1 scan1: mov a,e ori 0f0h ; high nibble must be 1111 out system_port_c ; active digit first mov a,m ; load a with [hl] out system_port_b ; then turn segment on mvi b,0 ; delay for electron transition process wait1: dcr b jnz wait1 in system_port_a ; read input port mvi b,8 ; check all 8-row shift_key: rar ; rotate right through carry jc next_key ; if carry = 1 then no key pressed push psw mov a,d sta key ; save key position pop psw next_key: inr d ; next key position dcr b ; until 8-bit was shifted jnz shift_key mvi a,0 ; clear a out system_port_b ; turn off led 26 inr e ; next digit scan code inx h ; next location dcr c ; next column jnz scan1 pop d pop b pop h ret ;---------- 8255 PPI system port I/O address --------------- system_port_a: equ 10h system_port_b: equ 11h system_port_c: equ 12h system_port_control: equ 13h 27 Appendix C UART Driver Routines ;---------- 16C550 compatible UART I/O address ------------ ; e.g. UM8250B, 16C450, 16C550 uart_buffer: equ 40h uart_line_status: equ 45h uart_fifo: equ 42h uart_lcr: equ 43h uart_divisor_lsb: equ 40h uart_divisor_msb: equ 41h uart_scr: equ 47h ; initialize 16C550 uart to 9600 8n1 with 2MHz clock ; 2MHz/13 = 153846Hz init_uart: mvi a,83h out uart_lcr ; set DLAB bit to access divider mvi a,13 out uart_divisor_lsb mvi a,0 out uart_divisor_msb ; 2MHz/13 = 153846 Hz ; 153846Hz/16 = 9615Hz mvi a,7 out uart_fifo ; init fifo and clear all buffers mvi a,03h out uart_lcr ; clar DLAB ; check uart line status, if the byte is FF then no uart ; ; xra a out uart_scr ; check if there is uart in uart_scr cpi 0 jz found xra a sta uart_found ret found mvi a,1 sta uart_found ret cout: mov b,a ; save a cout1: in uart_line_status 28 ani 20h ; transmitter ready? jz cout1 mov a,b ; restore a out uart_buffer ret cin: in uart_line_status ani 1 ; data available? jz cin in uart_buffer ret ; print string terminated by 0 ; input: HL put_str: mov a,m ; get A from [HL] cpi 0 jnz put_str1 ret put_str1: call cout inx h jp put_str 29 Appendix D Using NVRAM Bootable ; MTK-85 8085 Microprocessor Training Kit ; exp1.asm ; ; Using 8254 to produce 30.52Hz interrupt signal at RST7.5 ; ; The 8254 counter0 was loaded with 0000 by system monitor. ; The input clock to the 8254 is 2MHz, the OUT0 then produces ; 2MHz/65536 = 30.52Hz interrupt at RST7.5! ; CPU "8085.TBL" ;CPU TABLE HOF "INT8" ;HEX FORMAT gpio equ 0 ; enable NVRAM boot running org 8000h jmp start ; put instruction JMP to boot from RAM org 803ch ; interrupt vector of RST7.5 (relocated from 003CH) jmp service_rst7.5 org 8100h start: mvi a,11111011b ; enable rst7.5 sim ; set interrupt mask register ei ; enable interrupt jmp $ ; jump here service_rst7.5: lda count ; increment count inr a sta count out gpio ; write to onboard LED ei ret org 0e000h count dfs 1 ; use RAM one byte for count variable end Appendix E Machine Code and Mnemonic oI 8085 Instructions MOVE, LOAD and STORE 40 MOV B,B 41 MOV B,C 42 MOV B,D 43 MOV B,E 44 MOV B,H 45 MOV B,L 46 MOV B,M 47 MOV B,A 48 MOV C,B 49 MOV C,C 4A MOV C,D 4B MOV C,E 4C MOV C,H 4D MOV C,L 4E MOV C,M 4F MOV C,A 50 MOV D,B 51 MOV D,C 52 MOV D,D 53 MOV D,E 54 MOV D,H 55 MOV D,L 56 MOV D,M 57 MOV D,A 58 MOV E,B 59 MOV E,C 5A MOV E,D 5B MOV E,E 5C MOV E,H 5D MOV E,L 5E MOV E,M 5F MOV E,A 60 MOV H,B 61 MOV H,C 62 MOV H,D 63 MOV H,E 64 MOV H,H 65 MOV H,L 66 MOV H,M 67 MOV H,A 68 MOV L,B 69 MOV L,C 6A MOV L,D 6B MOV L,E 6C MOV L,H 6D MOV L,L 6E MOV L,M 6F MOV L,A 70 MOV M,B 71 MOV M,C 72 MOV M,D 73 MOV M,E 74 MOV M,H 75 MOV M,L 77 MOV M,A 78 MOV A,B 79 MOV A,C 7A MOV A,D 7B MOV A,E 7C MOV A,H 7D MOV A,L 7E MOV A,M 7F MOV A,A 3E nn MVI A,byte 06 nn MVI B,byte 0E nn MVI C,byte 16 nn MVI D,byte 1E nn MVI E,byte 26 nn MVI H,byte 2E nn MVI L,byte 36 nn MVI M,byte 01 nnnn LXI B,dble 11 nnnn LXI D,dble 21 nnnn LXI H,dble 31 nnnn LXI SP,dble 02 STAX B 12 STAX D 0A LDAX B 1A LDAX D 32 nnnn STA adr 3A nnnn LDA adr 22 nnnn SHLD adr 2A nnnn LHLD adr EB XCHG STACK C5 PUSH B D5 PUSH D E5 PUSH H F5 PUSH PSW C1 POP B D1 POP D E1 POP H F1 POP PSW E3 XTHL F9 SPHL 33 INX SP 3B DCX SP ARITHEMATICS C6 nn ADI byte CE nn ACI byte 80 ADD B 81 ADD C 82 ADD D 83 ADD E 84 ADD H 85 ADD L 86 ADD M 87 ADD A 88 ADC B 89 ADC C 8A ADC D 8B ADC E 8C ADC H 8D ADC L 8E ADC M 8F ADC A D6 nn SUI byte DE nn SBI byte 90 SUB B 91 SUB C 92 SUB D 93 SUB E 94 SUB H 95 SUB L 96 SUB M 97 SUB A 98 SBB B 99 SBB C 9A SBB D 9B SBB E 9C SBB H 9D SBB L 9E SBB M 9F SBB A 09 DAD B 19 DAD D 29 DAD H 39 DAD SP LOGICAL E6 nn ANI byte EE nn XRI byte F6 nn ORI byte A0 ANA B A1 ANA C A2 ANA D A3 ANA E A4 ANA H A5 ANA L A6 ANA M A7 ANA A A8 XRA B A9 XRA C AA XRA D AB XRA E AC XRA H AD XRA L AE XRA M AF XRA A B0 ORA B B1 ORA C B2 ORA D B3 ORA E B4 ORA H B5 ORA L B6 ORA M B7 ORA A COMPARE FE nn CPI byte B8 CMP B B9 CMP C BA CMP D BB CMP E BC CMP H BD CMP L BE CMP M BF CMP A ROTATE 07! RLC 17 RAL 0F RRC 1F RAR JUMP C3 nnnn JMP adr DA nnnn JC adr D2 nnnn JNC adr CA nnnn JZ adr C2 nnnn JNZ adr F2 nnnn JP adr FA nnnn JM adr EA nnnn JPE adr E2 nnnn JPO adr E9 PCHL CALL CD nnnn CALL adr DC nnnn CC adr D4 nnnn CNC adr CC nnnn CZ adr C4 nnnn CNZ adr F4 nnnn CP adr FC nnnn CM adr EC nnnn CPE adr E4 nnnn CPO adr RETURN C9 RET D8 RC D0 RNC C8 RZ C0 RNZ F0 RP F8 RM E8 RPE E0 RPO RESTART C7 RST 0 CF RST 1 D7 RST 2 DF RST 3 E7 RST 4 EF RST 5 F7 RST 6 FF RST 7 INPUT/OUTPUT DB nn IN byte D3 nn OUT byte INCREMENT/DECREMENT 04 INR B 0C INR C 14 INR D 1C INR E 24 INR H 2C INR L 34 INR M 3C INR A 03 INX B 13 INX D 23 INX H 05 DCR B 0D DCR C 15 DCR D 1D DCR E 25 DCR H 2D DCR L 35 DCR M 3D DCR A 0B DCX B 1B DCX D 2B DCX H SPECIALS 2F CMA 37 STC 3F CMC 27 DAA CONTROL 00! NOP F3 DI FB EI 76 HLT 20 RIM 30 SIM 5 5 4 4 3 3 2 2 1 1 D D C C B B A A 0 x 0 0 0 0 - 0 x 7 F F F M o n i t o r P r o g r a m 0 x 8 0 0 0 - 0 x F F F F 3 2 k B S R A M , N V R A M m e m o r y & i / o d e c o d e r N O N C < D o c > 2 8 0 8 5 M i c r o p r o c e s s s o r T r a i n i n g K i t B 1 4 S a t u r d a y , J u l y 3 0 , 2 0 0 5 T i t l e S i z e D o c u m e n t N u m b e r R e v D a t e : S h e e t o f D 2 D 6 A 1 2 / R D D 1 A [ 8 . . 1 4 ] A L E D 0 D 1 D 2 D 3 A 9 / R D R A M _ C E A 1 1 D 3 A 8 D 0 D 5 A 1 1 / W R D 1 D 0 A 1 1 D 5 D 0 A 1 0 D 7 D 2 D 4 D 7 D 6 D 3 A 1 5 / W R A 9 A 6 D [ 0 . . 7 ] A 9 A 8 A 1 3 / R D D 5 D 6 D 4 D 3 A 8 A 1 4 A 1 3 D 2 A 1 2 A 1 4 A 1 0 A 1 0 D 5 A 5 D 6 A 1 2 A 1 3 D 4 A 1 5 D 7 D 1 D 7 A 1 4 R O M _ C E D 4 A L E R E S E T _ I N I O / M R A M _ C E R O M _ C E S O D S I D R E S E T _ O U T D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 / R D S O D S 1 C L K O U T S I D A L E / W R S 0 R E A D Y I O / M A 4 A 6 A 7 A 2 A 3 A 0 A 5 A 1 * I N T R * R S T 6 . 5 * R S T 7 . 5 I N T A H O L D * R S T 5 . 5 R E S E T _ O U T H L D A H O L D I N T A C L K O U T A 7 H L D A R E A D Y A 3 A 2 A 7 A 3 A 3 A 5 A 4 A 4 A 4 A 7 A 1 A 2 A 0 A 2 A [ 0 . . 7 ] A 6 A 1 A 1 A 6 A 0 A 4 A 5 A 0 A 5 A 6 A 7 T R A P R S T 5 . 5 S 0 A L E T R A P S 1 S 0 S 1 I N T R R S T 7 . 5 R S T 6 . 5 * R S T 5 . 5 * R S T 6 . 5 * I N T R R S T 5 . 5 R S T 6 . 5 R S T 7 . 5 I N T R D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 G P I O _ L E D 1 G P I O _ L E D 2 G P I O _ L E D 3 G P I O _ L E D 4 G P I O / W R / R D R E S E T _ I N G P I O _ L E D 1 G P I O _ L E D 2 G P I O _ L E D 3 G P I O _ L E D 4 V S S S I D S Y S T E M _ P P I G P I O D [ 0 . . 7 ] r e s e t C T C U S E R _ P P I U A R T L C D _ E A [ 0 . . 7 ] C L K O U T W R R D T R A C E * R S T 7 . 5 V C C + 5 V + 5 V + 5 V + 5 V + 5 V + 5 V + 5 V + 5 V + 5 V + 5 V + 5 V V C C + 5 V + 5 V + 5 V R 3 4 . 7 k J 1 1 3 5 7 9 1 1 1 3 1 5 2 4 6 8 1 0 1 2 1 4 1 6 + + + + + + + + + + + + + + + + U 2 5 K I A 7 0 4 5 1 2 3 V C C G N D O U T U 9 E 7 4 L S 0 4 1 1 1 0 D 4 L E D U 9 A 7 4 L S 0 4 1 2 U 9 B 7 4 L S 0 4 3 4 U 9 F 7 4 L S 0 4 1 3 1 2 U 9 C 7 4 L S 0 4 5 6 U 4 7 4 H C 5 7 3 1 1 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 2 3 4 5 6 7 8 9 O E L E V C C 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Q 8 Q 1 D 2 D 3 D 4 D 5 D 6 D 7 D 8 D R 1 1 0 0 k U 9 D 7 4 L S 0 4 9 8 U 6 D 4 0 0 1 1 2 1 3 1 1 U 2 2 7 C 2 5 6 1 0 9 8 7 6 5 4 3 2 5 2 4 2 1 2 3 2 2 6 2 7 2 0 2 2 1 1 1 1 2 1 3 1 5 1 6 1 7 1 8 1 9 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 1 0 A 1 1 A 1 2 A 1 3 A 1 4 C E O E V P P O 0 O 1 O 2 O 3 O 4 O 5 O 6 O 7 U 3 H M 6 2 2 5 6 B 1 0 9 8 7 6 5 4 3 2 5 2 4 2 1 2 3 2 2 6 1 2 0 2 2 2 7 1 1 1 2 1 3 1 5 1 6 1 7 1 8 1 9 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 1 0 A 1 1 A 1 2 A 1 3 A 1 4 C E O E W E D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 U 1 0 7 4 L S 1 6 4 1 2 8 9 3 4 5 6 1 0 1 1 1 2 1 3 A B C L K C L R Q A Q B Q C Q D Q E Q F Q G Q H S W 2 P S 2 2 7 3 2 1 3 R 7 3 3 0 U 7 M S M 8 0 C 8 5 A 3 6 1 2 5 6 9 8 7 1 0 1 1 2 9 3 3 3 9 3 5 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 3 0 3 1 3 2 3 4 3 3 7 4 3 8 R S T - I N X 1 X 2 S I D T R A P R S T 5 . 5 R S T 6 . 5 R S T 7 . 5 I N T R I N T A S 0 S 1 H O L D R E A D Y A D 0 A D 1 A D 2 A D 3 A D 4 A D 5 A D 6 A D 7 A 8 A 9 A 1 0 A 1 1 A 1 2 A 1 3 A 1 4 A 1 5 A L E W R R D I O / M R S T - O T C L K O S O D H L D A D 1 1 N 4 1 4 8 R 5 4 . 7 k U 6 A 4 0 0 1 1 2 3 R 2 1 k U 6 B 4 0 0 1 5 6 4 D 2 L E D D 3 L E D D 5 L E D R 4 4 . 7 k D 6 L E D R 1 0 4 . 7 k S W 1 S W D I P - 4 / S M 1 2 3 4 8 7 6 5 U 1 7 4 L S 1 7 5 4 5 1 2 1 3 9 1 2 3 7 6 1 0 1 1 1 5 1 4 D 1 D 2 D 3 D 4 C L K C L R Q 1 Q 1 Q 2 Q 2 Q 3 Q 3 Q 4 Q 4 U 5 7 4 L S 1 2 6 1 2 3 4 5 6 8 9 1 0 1 1 1 2 1 3 1 O E 1 A 1 Y 2 O E 2 A 2 Y 3 Y 3 A 3 O E 4 Y 4 A 4 O E U 8 G A L 1 6 V 8 D 1 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 3 4 5 6 7 8 9 I / C L K I / O E I / O / Q I / O / Q I / O / Q I / O / Q I / O / Q I / O / Q I / O / Q I / O / Q I I I I I I I I U 6 C 4 0 0 1 8 9 1 0 Q 1 4 M H z + C 3 1 u F J P 1 H E A D E R 2 0 X 2 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 S 1 R E S E T R 2 1 4 . 7 k R 6 3 3 0 C 1 4 7 p F R 1 5 4 . 7 k R 8 3 3 0 C 2 4 7 p F R 9 3 3 0 R 1 1 3 3 0 5 5 4 4 3 3 2 2 1 1 D D C C B B A A C O M M O N C A T H O D E 6 - D I G I T 7 - S E G M E N T L E D u s e r _ k e y 1 u s e r _ k e y 2 0 x 1 0 - 0 x 1 3 < D o c > 2 8 0 8 5 M i c r o p r o c e s s o r T r a i n i n g K i t B 2 4 S a t u r d a y , J u l y 3 0 , 2 0 0 5 T i t l e S i z e D o c u m e n t N u m b e r R e v D a t e : S h e e t o f S P E A K E R P A 0 P A 1 P A 2 P A 3 P A 4 P A 5 P C 0 P C 1 P C 2 P C 3 P C 3 P C 0 P C 2 P C 1 P A 7 P A 6 P A 0 P A 1 P A 2 P A 3 P A 4 P A 5 P A 6 P A 7 P B 7 P B 6 P B 5 P B 4 P B 3 P B 2 P B 1 P B 0 P B 0 P B 1 P B 2 P B 3 P B 4 P B 5 P B 6 P B 7 D 7 D 1 D 6 D 0 D 2 D 5 D 4 D 3 A 1 A 0 S P E A K E R P A 7 P A 6 A 0 A 4 A 5 A 6 A 1 A 2 A 3 A 7 P C 5 P C 4 V S S T R A C E r e s e t D [ 0 . . 7 ] S Y S T E M _ P P I A [ 0 . . 7 ] R D W R V C C + 5 V + 5 V V C C + 5 V S W 1 8 U 1 2 T O S - 5 1 6 1 A E 7 6 4 2 1 9 10 5 3 8 a b c d e f g dp com1 com2 S W 2 8 U 1 6 T O S - 5 1 6 1 A E 7 6 4 2 1 9 10 5 3 8 a b c d e f g dp com1 com2 U 1 8 7 4 L S 1 4 5 1 5 1 4 1 3 1 2 1 2 3 4 5 6 7 9 1 0 1 1 A B C D 0 1 2 3 4 5 6 7 8 9 R 1 3 1 0 0 S W 2 2 U 1 9 8 2 5 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 5 3 6 9 8 3 5 6 4 3 2 1 4 0 3 9 3 8 3 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 1 4 1 5 1 6 1 7 1 3 1 2 1 1 1 0 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 R D W R A 0 A 1 R E S E T C S P A 0 P A 1 P A 2 P A 3 P A 4 P A 5 P A 6 P A 7 P B 0 P B 1 P B 2 P B 3 P B 4 P B 5 P B 6 P B 7 P C 0 P C 1 P C 2 P C 3 P C 4 P C 5 P C 6 P C 7 U 1 7 T O S - 5 1 6 1 A E 7 6 4 2 1 9 10 5 3 8 a b c d e f g dp com1 com2 Q 2 B C 3 2 7 1 2 3 S W 2 6 S W 2 9 S W P U S H B U T T O N U 1 4 T O S - 5 1 6 1 A E 7 6 4 2 1 9 10 5 3 8 a b c d e f g dp com1 com2 U 1 5 T O S - 5 1 6 1 A E 7 6 4 2 1 9 10 5 3 8 a b c d e f g dp com1 com2 S W 4 S W 6 S W 1 1 S W 2 3 S W 9 C R 1 4 4 . 7 k 1 2 3 4 5 6 7 8 9 S W 1 5 S W 1 9 S W 1 3 S W 1 7 S U 1 S P E A K E R S W 2 7 U 1 1 7 4 L S 2 4 4 2 4 6 8 1 1 1 3 1 5 1 7 1 1 9 1 8 1 6 1 4 1 2 9 7 5 3 1 A 1 1 A 2 1 A 3 1 A 4 2 A 1 2 A 2 2 A 3 2 A 4 1 G 2 G 1 Y 1 1 Y 2 1 Y 3 1 Y 4 2 Y 1 2 Y 2 2 Y 3 2 Y 4 S W 2 1 R 1 2 R - P A C K 1 1 6 2 1 5 3 1 4 4 1 3 5 1 2 6 1 1 7 1 0 8 9 U 1 3 T O S - 5 1 6 1 A E 7 6 4 2 1 9 10 5 3 8 a b c d e f g dp com1 com2 S W 7 S W 2 5 S W 1 2 S W 1 6 S W 5 S W 2 0 S W 3 S W 1 0 S W 8 S W 1 4 S W 2 4 5 5 4 4 3 3 2 2 1 1 D D C C B B A A t e x t L C D R / W R S R S 2 3 2 l e v e l c o n v e r t e r U s e r P P I c o u n t e r / t i m e r U A R T 0 x 2 0 - 0 x 2 3 0 x 3 0 - 0 x 3 3 0 x 4 0 - 0 x 4 7 0 x 5 0 - 0 x 5 3 2 M H z < D o c > 2 8 0 8 5 M i c r o p r o c e s s o r T r a i n i n g K i t B 3 4 S a t u r d a y , J u l y 3 0 , 2 0 0 5 T i t l e S i z e D o c u m e n t N u m b e r R e v D a t e : S h e e t o f D 2 D 3 D 4 D 7 D 5 D 6 D 0 D 1 D 2 D 3 D 4 D 7 D 5 D 6 D 0 D 1 D 2 D 3 D 4 D 7 D 5 D 6 D 0 D 1 A 0 A 1 A 1 A 0 A 0 A 1 A 2 D 2 D 3 D 0 D 4 D 1 D 6 D 5 L C D _ E A 1 D 7 A 0 A 3 A 7 A 4 A 2 A 1 A 5 A 0 A 6 U S E R _ P A 5 U S E R _ P A 6 U S E R _ P A 0 U S E R _ P A 3 U S E R _ P A 2 U S E R _ P A 4 U S E R _ P A 1 U S E R _ P A 7 T x D R x D T x D R x D D C D D C D R T S R T S V S S U S E R _ P A 7 U S E R _ P A 6 U S E R _ P A 5 U S E R _ P A 4 U S E R _ P A 3 U S E R _ P A 2 U S E R _ P A 1 U S E R _ P A 0 r e s e t U S E R _ P P I C T C U A R T D [ 0 . . 7 ] A [ 0 . . 7 ] C L K O U T * R S T 7 . 5 L C D _ E W R R D W R R D W R R D r e s e t V C C + 5 V + 5 V + 5 V + 5 V + 5 V V C C + 5 V + 5 V U 2 2 8 2 5 5 3 4 3 3 3 2 3 1 3 0 2 9 2 8 2 7 5 3 6 9 8 3 5 6 4 3 2 1 4 0 3 9 3 8 3 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 1 4 1 5 1 6 1 7 1 3 1 2 1 1 1 0 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 R D W R A 0 A 1 R E S E T C S P A 0 P A 1 P A 2 P A 3 P A 4 P A 5 P A 6 P A 7 P B 0 P B 1 P B 2 P B 3 P B 4 P B 5 P B 6 P B 7 P C 0 P C 1 P C 2 P C 3 P C 4 P C 5 P C 6 P C 7 U 2 1 8 2 5 4 8 7 6 5 4 3 2 1 2 2 2 3 1 9 2 0 2 1 9 1 1 1 0 1 5 1 4 1 3 1 8 1 6 1 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 R D W R A 0 A 1 C S C L K 0 G 0 O U T 0 C L K 1 G 1 O U T 1 C L K 2 G 2 O U T 2 U 2 0 T L 1 6 C 5 5 0 A 1 0 1 1 1 2 1 3 1 4 1 8 1 9 2 1 2 2 2 5 3 5 3 6 3 7 3 8 3 9 1 6 9 2 8 2 7 2 6 1 2 3 4 5 6 7 8 3 4 3 1 2 3 2 4 2 9 3 0 3 2 3 3 1 7 1 5 S D I S D O C S 0 C S 1 C S 2 W R 1 W R 2 R D 1 R D 2 A D S M R C T S D S R D C D R I X I N R C L K A 0 A 1 A 2 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 7 O U T 1 O U T 2 D D I S T X R D Y R X R D Y I N T R P T R T S D T R X O U T B A U D O U T S W 3 0 b a c k l i g h t 2 1 3 J R 1 C O N N R E C T 1 6 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 + C 7 1 0 u F + C 8 1 0 u F + C 9 1 0 u F R 1 7 4 . 7 k R 1 8 4 . 7 k R 1 9 1 0 K 1 3 2 U 2 3 M A X 2 3 2 A 1 3 8 1 1 1 0 1 3 4 5 2 6 1 2 9 1 4 7 R 1 I N R 2 I N T 1 I N T 2 I N C + C 1 - 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PT&#_#3*7#"&4)#&2)"7$*3724)&(7&(HH$#""&":4D)&2) 3*$$#)7&H2"5+(9A 'BN&U4H2K2#"&7:#&*"#$&$#62"7#$"A&R7&D("&*"#H 746#7:#$&D27:&?O.:2"&"2U5+#&5$46$(U&2)3$#U#)7"&7:#&34)7#)7&4K&?33*U*+(74$@&"#)H&27"&34)7#)7&74&7:# 4*75*7&54$7&(7&+43(724)&11&7:#)&$#5#(7&27A =#&"##&7:(7&7:#&U(3:2)#&34H#&:("&4)+9&]&<97#"&2A#A&F8@&NF@&11@&8F@&11@&X1A S4D&#)7#$&7:#&34H#&2)74&U#U4$9&(HH$#""&X111GA >7#5&W&T$#""&QP>P.0A O#7%"&+#($)&:4D&7:#&`#95(H&:#+5"&7#"72)6&94*$&K2$"7&5$46$(UA 9000 3C 9001 D300 9003 C30090 main: inr a out 0 jmp main .&T$#""&RS8&74&2)3$#U#)7&(HH$#""A&.:#&?I&D2++&<#&1111A T$#""&`#9&>.@&7:#)&5$#""&`#9&F&()H&`#9&8A&.&
[email protected]&(6(2)@&7:#&1W&D2++&"#)H&74&4)<4($H<RBA&.?&#)7$9 U4H#A =#&D2++&<#62)&"#7&7:#&C(+*#&74&*"#$&?33*U*+(74$&<#K4$#:()HA&.PT&()H&"##&7:#&C(+*#&:("&3:()6#H&4)<RB&OPNo 7 .PT@&7:#&H2"5+(9&D2++&":4D&)#_7&2)"7$*3724)&74&<#&#_#3*7#H&(7&(HH$#""&X11WA =#&3()&#_(U2)#&7:#&34)7#)7&4K&?I&<9&`#9&?O.:#&F8&<97#&D2++&#)7#$&74&(HH$#"" X111GA >7#5&.:#&)#_7&2)"7$*3724)@&Z'T X111G&D2++&<#&#_#3*7#HA =#&3()&5$#""&`#9&>.@&1d?I@&H2"5+(9&D2++&":4D&34)7#)7&4K&*"#$&?33*U*+(74$&()H&I+(6&$#62"7#$A T$#""&`#9&'BN@&7:#)&`#9&1@1@1@1A&.:#)&$#5#(7&"7#5W&*)72+&X1&<97#&D("&#)7#$#H&74 (HH$#""&X110GA j4*&3()&*"#&RS8&4$&NP8&74&3:#3`&7:#&34H#@&94*&3()&U4H2K9&27&#("2+9&2)&N?.@&1d?IA&=#&"##&7:(7&)4D&?33*U*+(74$&2" 1WA T$#""&`#9&>.:#&5*$54"#&2"&74&3+#($&27&74 c#$4A T$#""&`#9&?O.E C'7 E)"6)-F/GH >. R)"7#(H&4K&#_#3*724)&4)#&2)"7$*3724)&*"2)6&"2)6+#&"7#5@&D#&3()&$*)&7:#&5$46$(U&D27:4*7 "74552)6&K4$&#(3:&2)"7$*3724)A&=#&D2++&7$9&D27:&`#9&Q!SA E)"6)-F/GI .@&8I@&8F@&11@&X1A&P)7#$&7:#&34H#@&()H&5$#""&`#9 GB'P@&Q!SA =#&D2++&"##&7:#&34+H&U#""(6#&$#5#(7&$*))2)6&4)&7:#&H2"5+(9A&Q>.:#)&5$#""&?O.4&"745&5$46$(UV.:2"&5$46$(U&:("&4)+9&]&<97#"&2A#A@&WP@&1.GA&.2)&U4)274$&K*)3724)"A&Q#62"7#$&P&2"&U4)274$&3(++ )*U<#$A .:#&2)"7$*3724)&Q.2 rst 1 jmp main .19h b.&$*))2)6@&D#&U*"7&5$#""&QP>P.&1A R)&3("#&4K&7#"72)6&+4)6&5$46$(U@&7:#&<4($H&(+"4&5$4C2H#"&744+&7:(7&:#+5"&2)"#$72)6&7:#&Q>.&1@&D#&"##&7:(7&(K7#$&(HH2724)@&7:#&$#"*+7 2)&?33*U*+(74$&2"&W\A&.4&3+#($&7:2"&<$#(`&(HH$#""@&5$#""&?O.WGA 9000 9002 9004 9005 9006 3E19 0602 80 27 FF mvi mvi add daa rst a.2 b 7 ?K7#$&#)7#$&7:#&34H#@&94*&3()&$*)&27&D27:&`#9&Q!SA&8:#3`&7:#&$#"*+7&2)&?33*U*+(74$&D27: ?O.:2"&744+&3(++#H&"#7&<$#(`&542)7A&>*554"#&D#&D()7 74&`)4D&7:#&$#"*+7&(K7#$&(HH&<&2)"7$*3724)A&=#&D()7&74&"#7&<$#(`&542)7&(7&+43(724)&X110A =#&3()&H4&<9&"#772)6&7:#&(HH$#""&74&X110&D27:&`#9&?NNQ&X@1@1@0A&. e&2)"7$*3724)&74&7:#&"5#32K2#H&+43(724)A&.:2"&5$46$(U&":4D"&:4D&74&*"#&`#9&Q!S&74&K4$3#&8T!&i*U5&K$4U&U4)274$&5$46$(U&74 *"#$&5$46$(UA 9000 1E02 9002 CF 9003 C30090 main: mvi e.&`#9A E)"6)-F/GJ =#&3()&7#"7&7:#&5$46$(U&D27:&"4K7D($#&<$#(`542)7A&.&W&:(C2)6&U(3:2)#&34H# 8I&2"&7:#&U#7:4H&7:(7&*"#H&74&3(++&<*2+7.>&e&:(C2)6 U(3:2)#&34H#&II&$#7*$)"&34)7$4+&<(3`&74&U4)274$&5$46$(U&()H&"(C#&7:#&34)7#)7&4K&8T! $#62"7#$"&74&*"#$&$#62"7#$"A&=#&3()&3:#3`&7:#&$#"*+7&2)&*"#$&$#62"7#$"&#("2+9A G#$#&2"&7:#&5$46$(U&7:(7&(HH"&7D4&\8N&)*U<#$"&WXG&()H&1.:#&H2"5+(9&D2++&":4D 8 .&8A&.:#&$#"*+7&D2++&<#&.&\@&7:# H2"5+(9&D2++&":4D&7:2"&(HH$#""&D("&"#7&<$#(`542)7A T$#""&GB'P&()H&Q!S@&3:#3`&*"#$&?I&D27:&?O. W11A&.set value to user register W .W11@&"(9A .:#&T8&:(" G95#$.ASCII code C .watch variables SPACE BAR .WA !"##%K$*#6/@%)F*#-< .:#&!?Q.3*$$#)7&(HH$#""&X110A&.:#&U4)274$ 34)7$4+&34H#&K4$&<47:&2"&D4$`2)6&34)3*$$#)7+9A =:#)&5$#""&$#"#7&7:#&5$4U57&(55#($"&4)&"3$##)A MTK-85 8085 MICROPROCESSOR TRAINING KIT (? HELP) 9000> .&74&34))#37&( 7#$U2)(+A&.&3:25&D("&2)"#$7#HA&84UU*)23(724)&2"&<("#H&4)&X]11&<27d"#3@&/&H(7(&<27@&)4&5($279 ()H&4)#&"745&<27A&=#&3()&*"#&T8&$*))2)6&7#$U2)(+&#U*+(724)&K4$&^.:#&34H#&.edit memory F .single step ? .user register display S .help menu 9000> 9 .clear watch variables D .&H$2C#$"&()H&"#$2(+&34UU()H"&($#&(*74U(723(++9&34)K26*$#H&D:#) !?Q.#$U2)(+&5$46$(U&7:(7&3()&#U*+(7#&7#$U2)(+&^.e&D2++&<#&$#"74$#H&<(3`&74&(HH$#""&X110A&=#&3() 34)72)*#&#_#3*724)@&5$#""&Q!S@&3:#3`&$#"*+7&2)&?I&(6(2)@&&D#&D2++&6#7&.:#&QB'&U4)274$&34)7(2)"&54D#$K*+&34UU()H"&D:#)&*"2)6&!?Q.:#$#&2"&)4&)##H&74&"D273:&<#7D##)&"7()H(+4)#&U4H#&()H&7#$U2)(+&U4H#A&.display user STACK L .i/o address map J .monitor call number N .fill constant H .load Intel hex file M .jump to user program K .disassemble E .95#&p&K4$&:#+5&U#)*&+2"72)6A MTK-85 8085 MICROPROCESSOR TRAINING KIT (? HELP) A .hex dump I .new location pointer Q .quick home location R . /L!M&3+#($"&7:#&W].M C.:#&D(73:&C($2(<+#"&*"#&Q?'&"5(3#&K$4U&I111.M&#_(U2)#"&()H&U4H2K9&7:#&H(7(&2)&U#U4$9A&=#&3()&*"#&7:2"&34UU()H&74 #)7#$&U(3:2)#&34H#A&./L8M&5$2)7"&7:#&:#_(H#32U(+&34H#&K4$&5$2)7(<+#&?>8RR&3:($(37#$"A !"FF-#.C B FD C M 4B 10 .. I11IA 9000> F000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 9000> !"FF-#.:#&U4)274$&5$4C2H#"&a*23`&(33#""&74 (W]./L. 9000 9002 9004 9005 9006 9007 9008 9009 900C 900D 900E 900F 9010 9012 9013 9014 9016> !"FF-#.4&C2#D&7:#&34)7#)7@&*"#"&>5(3#&`#9&()H&74&#)7#$&<97#@&5$#""&7D4 H2627"A&.<97#&Q?'&K4$&5$46$(U&7#"72)6A&.PQA 9016>edit memory location = 9000 Enter to quit. SPACE key to view content ADDR 9000 9001 9002 9003 9004 9005 9006 9016> DATA [3E] [19] 39 [06] [02] 19 [80] [27] [FF] 3E19 0602 80 27 FF 0D 30 FA6DFC C8 46 49 0B CEFD 89 B6 F64B MVI MVI ADD DAA RST DCR SIM JM RZ MOV MOV DCX ACI ADC ORA ORI A..!"FF-#.4&a*27&i*"7&5$#""&PS.02 B 7 C FC6D B.<97#&D(73:&C($2(<+#"A&./L7M&H2"(""#U<+#"&7:#&U(3:2)#&34H#&2)74&/1/0&2)"7$*3724)"A 9000>disassemble.19 B. }.:#&34)7#)7&4K&U#U4$9&K$4U&3*$$#)7&542)7#$&X1W1&74 X1/I&D2++&H2"5+(9&2)&:#_(H#32U(+A&.:#&?>8RR&34H#&K4$&#(3:&<97#&D2++&<#&H2"5+(9#H&(+"4A ...... 11H=PORTB.4.. .. 32H=PORTC.1A 9016>Begin address = 9010 End address = 9020 Data = 00 9016> !"FF-#...E.G...2. 20H=counter0. D0-D3=output port D4-D7=input port 10H-13H 8255 system PPI.. 21H= counter1 22H=counter2. ..4z !"FF-#... 30H=PORTA..X1.:#&H47&D2++&<#&H2"5+(9#H&K4$&)4)5$2)7(<+#&?>8RR&34H#A 9010> 9010 9020 9030 9040 9050 9060 9070 9080 9090> 00 4D 97 F0 A8 8A A9 41 00 C2 47 36 E2 13 31 00 00 97 81 B2 30 8C CD 89 00 CB CE 69 84 FD B7 F3 00 DA C1 CF 76 4A BB 54 00 DF 99 1D AA 82 4E BF 00 A0 98 90 C5 B9 8D EC 00 BE CB 90 18 99 BE BF 00 9E 14 70 A7 4E FF E0 00 73 ED F1 84 24 5B 9F 00 1A 45 73 C5 33 3C 72 00 34 DE D8 32 9E 8D CB 00 E3 35 C1 81 EB EA 7D 00 A6 6A 4F BF 16 5E E8 00 83 7C DF B9 A8 4F 34 00 4E F1 56 03 0D 7F 7A ...:#&*"#$&$#62"7#$&H2"5+(9"&$#"*+7"&(K7#$&$*))2)6&7:#&34H#A&...&e $#7*$)"&34)7$4+&<(3`&74&U4)274$&5$46$(UA 9090>jump to address [9006] = 9000 11 .N$3.J. 33H=CONTROL 40H-47H C16550 UART registers 9090> !"FF-#....6../LAM&H2"5+(9"&4)<4($H&RdB&(HH$#""A 9090> 00H-0FH onboard 4-bit GPIO.<27&34)"7()7&74&U#U4$9A&.. 10H=PORTA./L0M&K2++"&/.M&H*U5"&U#U4$9A&....v..i... 23H control register 30H-33H 8255 user PPI.:#&#_(U5+#&":4D"&K2++2)6&<97#&11&74 (HH$#""&X1W1.0.:#&#_(U5+#&":4D"&i*U5 74&(HH$#""&X111A&..^O A......... ...O...s...p. 12H=PORTC../L. M..s. 31H=PORTB...N .!"FF-#.1.T.../LNM&i*U5"&K$4U&U4)274$&5$46$(U&74&*"#$&5$46$(UA&..r..V ..[<.N....:#&Q>.....5j|.. 13H=CONTROL 20H-23H 8254 programmable counter.. ?8-A 9000>press r for user register display AF=5800 BC=19F4 DE=C256 HL=9504 SP=F098 PC=9000 S=0 Z=0 AC=0 P=0 CY=0 9000>press SPACE bar for single step 9000 E5 PUSH H AF=5800 BC=19F4 DE=C256 HL=9504 SP=F096 PC=9001 S=0 Z=0 AC=0 P=0 CY=0 9000>press k for STACK display ADDR F096 F097 F098 9000> DATA [04] [95] [C0] !"FF-#.?8-&U#U4$9&D27:&34UU()H&`A&..#$U2)(+&D#&3()&64&74&.@&7:#&K2+#&<$4D"#$&D2++&45#)&("`2)6&D:(7&7#_7&K2+#&74&<#&"#)7A&=#&3()&+#7 27&":4D&4)+9&K2+#&D27:&A:#_&#_7#)"24)&<9&7952)6&qA:#_A&.000005 bytes loaded 0 errors 9080> !"FF-#.$()"K#$@&>#)H&7#_7&K2+#A B$&5$#""&?O.:# :#_&K2+#&2"&?>8RR&7#_7&K2+#A&>4&D27:&G95#$.function_number CF RST 1 12 .&.?8-&U#U4$9A&.#$U2)(+&74&H4D)+4(H&7:#&:#_&K2+#A&./LCM&":4D"&U4)274$&3(++&)*U<#$A&>4U#&4K&34UU4)&"*<$4*72)#"&3()&<#&3(++#H 7:$4*6:&Q>.:#&#_(U5+#&<#+4D&":4D"&$*))2)6 2)"7$*3724)&T!>G&GA =#&K2$"7&3:#3`&7:#&*"#$&$#62"7#$&D27:&34UU()H&Y$%A&=#&"##&7:(7&.:#&?""#U<+#$&()H&8&34U52+#$&K4$&/1/0 8T!&3()&5$4H*3#&"7()H($H&R)7#+&G#_&K2+#A&.&.:#&4)<4($H&H47&OPN&D2++&$*)&74&2)H23(7#&H4D)+4(H2)6&2"&4)&642)6A&=:#)&34U5+#7#H@&7:# $#54$7&D2++&":4D&)*U<#$&4K&<97#&$#3#2C#H&()H&5$2)7&3:#3`"*U&#$$4$A&RK&)4&#$$4$&27&D2++ ":4D&1&#$$4$"A 9080>load Intel hex file.BT&4K&>.:#&34)7#)7&4K&GO&D("&"(C#H&2)&>.:#&#_(U5+#&<#+4D&*"#"&G95#$.:#)&H4*<+#&3+23`"&(7&7:#&:#_&K2+#A .:#&:#_&K2+#&34)7(2)"&U(3:2)#&34H#&$#5$#"#)7#H <9&?>8RR&+#77#$"A&.AF=5800 BC=19F4 DE=C256 HL=9504 SP=F098 PC=9007 S=0 Z=0 AC=0 P=0 CY=0 9090> !"FF-#./L>M&H2"5+(9"&*"#$&>.&W&D27:&K*)3724)&)*U<#$&5$#+4(H#H&2)&$#62"7#$&PA 9080> see input parameters in user manual 1Enn MVI E./L:M&+4(H"&R)7#+&G#_&K2+#&74&U#U4$9A&..?8-&2"&I1X/A ?K7#$&5$#""2)6&>T?8P&\?Q&K4$&"2)6+#&"7#5@&7:#&>T&2"&)4D&I1X]A&=#&3()&"##&7:#&34)7#)7 4K&>. H A C3F0 13 .25 D.D H E B./LBM&"#7"&)#D&+43(724)&542)7#$&(7&5$4U57A&. E000 E001 E004 E005 E006 E007 E008 E009 E00C E00E E00F E010 E011 E013 E014 E015 E018> !"FF-#.E 2ADE H..:#&#_(U5+#&"#7"&)#D&542)7#$&74 P111&()H&5$#""&YH%&74&H2"(""#U<+#A 9080>new location = e000 E000>disassemble./LOM&"#7"&+43(724)&542)7#$&(7&5$4U57&74&X111&()H&"#7"&*"#$&T8&74&X111A 9000> AF=5800 BC=19F4 DE=C256 HL=9504 SP=F096 PC=9000 S=0 Z=0 AC=0 P=0 CY=0 9000> 53 32DE2A 62 25 C9 1C 43 CC4A05 2655 67 04 F3 0E25 54 AF C3F0C3 MOV STA MOV DCR RET INR MOV CZ MVI MOV INR DI MVI MOV XRA JMP D.E 054A H.00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D - demo delay cold_boot scan cin cout put_str init_lcd lcd_ready clear_lcd goto_xy put_str_lcd put_ch_lcd demo2 9080> !"FF-#.55 H.A B C.. :#&2)"7$*3724) D2++&":4D&4)&"3$##)&D27:&*"#$&$#62"7#$"&$#"*+7&(K7#$&#_#3*724)A >*554"#&D#&D$27#&(&5$46$(U&":4D)&<#+4DA org 9000h xra a loop: out 0 mov h./L3E8!.:#)&7$()"+(7#&27&74&U(3:2)#&34H#&K2+#&*"2)6&7:#&?""#U<+#$&5$46$(UA&N4D)+4(H&:#_&K2+#A 9000>load Intel hex file./L3M&"#7"&C(+*#&74&*"#$&$#62"7#$"A 9013>set value to user register (enter A for AF) ? AF=0404 ff00 9013> AF=FF00 BC=19F4 DE=0434 HL=0534 SP=F096 PC=9006 S=0 Z=0 AC=0 P=0 CY=0 9013> !"FF-#...000011 bytes loaded 0 errors 9000>disassemble.d jmp loop end .!"FF-#./LPM&5$2)7"&D(73:&C($2(<+#"A 9013> F000 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 !"FF-#..Q8?M&#_#3*7#"&7:#&2)"7$*3724)&(7&(HH$#""&2)&*"#$&T8A&.A H 14 . 9000 9001 9003 9004 AF D300 67 24 XRA OUT MOV INR A 00 H.a inr h push h pop d mov a./L?M/H2"5+(9"&*"#$&$#62"7#$"&34)7#)7A 9000> AF=5800 BC=19F4 DE=C256 HL=9504 SP=F098 PC=9000 S=0 Z=0 AC=0 P=0 CY=0 9000> !"FF-#.. to see the content of STACK memory ADDR F096 F097 F098 DATA [34] [01] [C0] 9013> press SPACE key. DE will be loaded with top of STACK 9006 D1 POP D AF=0000 BC=19F4 DE=0134 HL=0134 SP=F098 PC=9007 S=0 Z=0 AC=0 P=0 CY=0 9013> press SPACE key.D AF=0100 BC=19F4 DE=0134 HL=0134 SP=F098 PC=9008 S=0 Z=0 AC=0 P=0 CY=0 9013> press SPACE key. the content SP will decrement by 2 9005 E5 PUSH H AF=0000 BC=19F4 DE=C256 HL=0134 SP=F096 PC=9006 S=0 Z=0 AC=0 P=0 CY=0 9013> press K.D 9001 9013>print user register with command r AF=5800 BC=19F4 DE=C256 HL=1234 SP=F098 PC=9000 S=0 Z=0 AC=0 P=0 CY=0 9013>press SPACE key to execute instruction at 9000. see LED! 9001 D300 OUT 00 AF=0100 BC=19F4 DE=0134 HL=0134 SP=F098 PC=9003 S=0 Z=0 AC=0 P=0 CY=0 15 . the content of A will send to GPIO 9001 D300 OUT 00 AF=0044 BC=19F4 DE=C256 HL=1234 SP=F098 PC=9003 S=0 Z=1 AC=0 P=1 CY=0 9013>press SPACE key. PC will be loaded with 9001 9008 C30190 JMP 9001 AF=0100 BC=19F4 DE=0134 HL=0134 SP=F098 PC=9001 S=0 Z=0 AC=0 P=0 CY=0 9013> press SPACE key.9005 9006 9007 9008 900B 900C 900D 900E 900F 9010 9011 9012 E5 D1 7A C30190 00 00 00 00 00 00 00 00 PUSH POP MOV JMP NOP NOP NOP NOP NOP NOP NOP NOP H D A.A AF=0044 BC=19F4 DE=C256 HL=0034 SP=F098 PC=9004 S=0 Z=1 AC=0 P=1 CY=0 9013> press SPACE key. the content of D will copy to A 9007 7A MOV A. the content of H will increment by 1 9004 24 INR H AF=0000 BC=19F4 DE=C256 HL=0134 SP=F098 PC=9005 S=0 Z=0 AC=0 P=0 CY=0 9013> press SPACE key. we see A=00 9000 AF XRA A AF=0044 BC=19F4 DE=C256 HL=1234 SP=F098 PC=9001 S=0 Z=1 AC=0 P=1 CY=0 9013>press SPACE key. the content of A will copy to H 9003 67 MOV H. the content of A will send to GPIO. e8./0&<4($H&2"&":4D)&<#+4DA&I4$&34U5+#7#&:($HD($# "3:#U(723@&"##&?55#)H2_&NA 8T! .&0A0 16 .8G Q>.:#&8T!&2"&8'B>&/18/0A&./G /1.W.0]@&2"&5+(3#H&(7&(HH$#""&/111G.&F Q>.0]&2"&5+(3#H&(7&(HH$#"" 1111.:#&F..:#&<$4D)4*7&34)H2724)&3()&#U*+(7#&<9&*"2)6&C($2(<+#&54D#$&"*55+9A&.:#&<$4D)4*7&32$3*27&H#7#37"&^88@&2K&27 2"&<#+4D&7:$#":4+H&+#C#+@&27&D2++&$#"#7&7:#&8T!A .-.:#&<4($H&:("&]M`\&U#U4$9A&.&M Q>.1G /1.&0 Q>.4&7#"7&27@&(Hi*"7&7:#&<4($H&^RS&K$4U 1.eIIIGA&?)H&7:#&F.`\&QB'&U4)274$&.?O&K$#a*#)39&2"&M'GcA&.:#&m.&.-).`\&>Q?'&]. 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"7(7#&<*KK#$@&eMO>W.8A 17 .?rW1G@&TBQ.52)&:#(H#$A >9"7#U&T$46$(UU(<+#&T4$7&/.\rWWG@&TBQ.?8-&($#(@&()H U4)274$&34)7$4+&K*)3724)"A&."7#5A Q>.:#&:26:#$.8rW.4&#)(<+#&<*cc#$@&D$27# eIG&74&TBQ.]A&.:#&+4D.0M&5$46$(UU(<+#&34*)7#$A '4)274$&5$46$(U&*"#"&+("7&5(6#&4K&Q?'&K4$&H(7(&"74$(6#@&>.Ne&2"&2)5*7&54$7A&.NF&2"&4*75*7 54$7A&.1&4K&/./1F1G /1FMG /1F8G S47#b WA! .&eA0 Q>.00&($#&TBQ.<27&2)5*7&54$7&*"2)6&7$2.I@&eMO>We0&()H&M.<27&4*75*7&54$7&*"2)6&N&795#&I.:#&"26)(+&K$4U&<47:&54$7"&(55#($#H&(7&ZW@ W]. 0M&($#&U(55#H&74&RdB&"5(3# K$4U&.%-.&4$ ..? TBQ.1G&74&.:#&<4($H&5$4C2H#"&(&*"#$&5$46$(UU(<+#&5($(++#+&54$7@&/.%)&/-#.00%"&$#62"7#$"&($# U(55#H&74&RdB&(HH$#""&K$4U&F1G&74&FFGA F1G FWG F.G . 8BS.\ TBQ.QBO&QPLR>.8 8BS.1G .WG .0M .:#&2)7#$)(+&$#62"7#$"&4K&/.!"#$&T$46$(UU(<+#&T4$7&/.FGA .:#&5$46$(UU(<+#&34*)7#$@&/.00 .PQW 8B!S.QBO&TBQ.0M&D("&"*55+2#H&D27:&3+43`&"26)(+&K$4U&8OB8-B!.PQ1 8B!S. T$46$(UU(<+#&84*)7#$&/./!"##%K$")& 8T!&G#(H#$&ZTW 18 .00A&.:#&/.'Gc&K4$&34*)7#$1&()H&34*)7#$WA&.G FFG TBQ.PQ .PQ.FG 8B!S. 0M&G#(H#$&ZTW B)<4($H&O8N&G#(H#$&ZQW 19 .00&()H&/.!"#$&/. 00_.N8&(H(57#$&]^.Q>.01U? T4D#$&34)"*U5724)b&.74.0]@&F.W.Ae]=&f.0A0@&Q>.#"7&<*774)A .#"7&\*774) .@&/.^&.OW]8001&34U5(72<+# QB'&U4)274$b&/1/0A("U \$4D)4*7&T$47#3724)b&-R?e1M0 \4($H&>2c#b&/AX1&_&/AWF&2)3: =#26:7b&F.QA&!"#$&3()&"#+#37&7:#&5*+"#&74&<#&7$266#$#H&K4$ #(3:&52)&<9&H25&"D273:&>=WA&.0M !?Q.0] RdB&54$7b&T$46$(UU(<+#&T($(++#+&54$7&/..F.:#&4)<4($H&OPN@&NM&2)H23(7#"&7:#&5*+"#&2"&(372C(7#H&D:#) 5$#""&.8&N\X&U(+#&34))#374$&^\W R)7#$$*57"&.<27<RB 84*)7#$b&T$46$(UU(<+#&84*)7#$&/.e8.b&W].`\&].^N8g '4)274$&8(++&S*U<#$ 00 .:#&2)7#$$*57&7#"7&<*774)&5$4C2H#"&(&"2)6+#&54"272C#&5*+"#&7:(7&72#H&74&8T!&:($HD($# 2)7#$$*57&52)"@&Q>.`\&.demo >3()&e.F1U?&sW.#3:)23(+&>5#32K23(724)" 8T!b&8'B>&/18/0&sM'Gc '#U4$9b&]M`\@&F.]A0&()H&RS."#6U#)7&H2"5+(9&D27:&<*KK#$&H2"5+(9&542)7#H&<9&GO P)7$9b&GO P_27b&)4)# 20 .16&f34U5+#7#&34U54)#)7"&#_3#57&O8Ng N8&T4D#$&>*55+9b&?8.<97#&IRIB&. lcd_ready =(27&*)72+&O8N&U4H*+#&2"&$#(H9A P)7$9b&)4)# P_27b&)4)# 09 ."#6U#)7&OPNA P)7$9b&)4)# 03 .scan >3()&`#9<4($H&()H&H2"5+(9&4)#&393+#A P)7$9b&GO&542)7"&7:#&H2"5+(9&<*KK#$ P_27b&`#9&r&"3()&34H#&JW&)4&`#9&5$#""#H 04 .goto_xy >#7&3*$"4$&54"2724)&4K&O8N P)7$9b&GO@&G&r&_@&O&r&9 21 .clear_lcd 8+#($&O8N&H2"5+(9 P)7$9b&)4)# P_27b&)4)# 0A .init_lcd R)272(+2c#&O8N&U4H*+# P)7$9b&)4)# P_27b&)4)# 08 .delay N#+(9&"*<$4*72)#&*"2)6&$#62"7#$&5(2$&NP@&N&2"&4*7#$&+445&H#+(9@&P&2"&2))#$&+445A P)7$9b&NP P_27b&)4)# 02 .01 .<447&U#""(6#&4)&e.cout >#)H&3:($(37#$&74&34)"4+# P)7$9b&?&r&3:($(37#$&74&<#&"#)7 P_27b&)4)# 06 .put_str T$2)7&"7$2)6&74&34)"4+#@&"7$2)6&2"&7#$U2)(7#H&<9&1A P)7$9b&&GO P_27b&)4)# 07 .cold_boot N2"5+(9&34+H.cin L#7&3:($(37#$&K$4U&34)"4+# P)7$9b&)4)# P_27b&?&r&3:($(37#$&$#3#2C#H 05 . P_27b&)4)# 0B .put_str_lcd T$2)7&"7$2)6&74&O8N@&"7$2)6&2"&7#$U2)(7#H&<9&1 P)7$9b&GO P_27b&)4)# 0C .demo2 Q*))2)6<RB&OPN P)7$9b&)4)# P_27b&)4)# S^Q?'&\447(<+# !"#$&3()&$#5+(3#&!F@&>Q?'&D27:&(&S4)C4+(72+#&Q?'&K4$&5$46$(U&"74$(6#@&D:#)&7:# <4($H&2"&54D#$&4KKA&?&Z'T&2)"7$*3724)&5+(3#H&(7&/111G&D2++&#)(<+#&S^Q?'&<447(<+#A .put_ch_lcd T$2)7&3:($(37#$&74&O8N&(7&3*$$#)7&3*$"4$&54"2724) P)7$9b&? P_27b&)4)# 0D .:#&U4)274$&5$46$(U&3:#3`"&7:#&+43(724)&/111GA&RK&27&:("&8F&f4534H#&4K&Z'T 2)"7$*3724)g@&27&D2++&i*U5&74&(HH$#""&/111GA&.A&.:#&U4)274$&"*<$4*72)#"&($#&"72++&(C(2+(<+#&K4$&7:#&(55+23(724)&5$46$(UA .:#&<97# 8F&(7&+43(724)&/111G&D2++&3:()6#&74&11A .:#&"(U5+#&34H#&7:(7&H#U4)"7$(7#"&S^Q?'&\447(<+#&2"&":4D)&2)&?55#)H2_&NA 22 .:#&K#(7*$#&(++4D"&(55+23(724)&34H#&74&$*) #("2+9A&.4&6#7&<(3`&74&U4)274$&U4H#@&*"#$&3()&5$#""&!>PQW&`#9&D:2+#&5$#""&QP>P. /:!7/7)*(%)/?"1$*#%& . 0ch out command_write call clear_lcd ret .onboard LCD registers ----------------command_write equ 50h command_read equ 52h data_write equ 51h data_read equ 53h busy equ 80h . print ASCII text on LCD .899%#. get A from [HL] cpi 0 jnz put_str_lcd1 ret put_str_lcd1: call lcd_ready out data_write inx h jp put_str_lcd .m .*R/8'#S"-).38h out command_write call lcd_ready mvi a. entry: HL pointer with 0 for end of string put_str_lcd: mov a.------------------.1 out command_write exit_clear: ret init_lcd: call lcd_ready mvi a.--------------------. wait until lcd ready 23 .LCD driver routines ----------------lcd_ready: push psw lcd_ready1: in command_read ani busy jnz lcd_ready1 pop psw ret clear_lcd: call lcd_ready mvi a. h 094h command_write 3 goto_xy4 a..l cpi 0 jnz goto_xy1 mov a.h 0c0h command_write 2 goto_xy3 a. goto_xy set cursor location on lcd . entry: HL: H = x. L = y goto_xy: call lcd_ready mov a. put_ch_lcd put character to lcd .h 0d4h command_write goto_xy1: cpi jnz mov adi out ret goto_xy2: cpi jnz mov adi out ret goto_xy3: cpi jnz mov adi out ret goto_xy4: ret .h adi 80h out command_write ret 1 goto_xy2 a. entry: A put_ch_lcd: call lcd_ready out data_write ret 24 . if carry = 1 then no key pressed . exit: key = scan code . key = -1 scan1: mov ori out mov out a. for 6-digit LED .8 shift_key: rar jc next_key push psw mov a. digit scan code appears at 4-to-10 decoder mvi d.m . put -1 to key sta key . rotate right through carry ./7*&9<-= . save key position .0 .6 mvi e. until 8-bit was shifted . then turn segment on .899%#.*R/Q/31S)"1$*#%/3K-#/T%=S"-). key position mvi a. delay for electron transition process wait1: mvi b. clear a .0 .0 out system_port_b 25 .0 dcr b jnz wait1 in system_port_a ./-#.0ffh . turn off led mvi a. next key position . high nibble must be 1111 system_port_c . scan: push h push b push d mvi c.d sta key pop psw next_key: inr d dcr b jnz shift_key . active digit first a. load a with [hl] system_port_b . -1 no key pressed . read input port mvi b. subroutine scan keyboard and display .e 0f0h . check all 8-row . entry: hl pointer to display buffer . ---------.8255 PPI system port I/O address --------------system_port_a: equ 10h system_port_b: equ 11h system_port_c: equ 12h system_port_control: equ 13h 26 .inr e inx h dcr c jnz scan1 pop d pop b pop h ret . next location . next column . next digit scan code . e. init fifo and clear all buffers a. save a cout: cout1: 27 .*R/!/D8?@/7)*(%)/?"1$*#%& . set DLAB bit to access divider a.0 uart_divisor_msb . check uart line status.---------. if the byte is FF then no uart . check if there is uart in uart_scr cpi 0 jz found xra a sta uart_found ret found mvi a. initialize 16C550 uart to 9600 8n1 with 2MHz clock .7 uart_fifo . 2MHz/13 = 153846 Hz . clar DLAB .13 uart_divisor_lsb a.83h out uart_lcr mvi out mvi out mvi out mvi out . 153846Hz/16 = 9615Hz a.a in uart_line_status . xra a out uart_scr .16C550 compatible UART I/O address -----------. . 2MHz/13 = 153846Hz init_uart: mvi a. 16C550 uart_buffer: equ 40h uart_line_status: equ uart_fifo: equ uart_lcr: equ uart_divisor_lsb: equ uart_divisor_msb: equ uart_scr: equ 45h 42h 43h 40h 41h 47h . 16C450.899%#. UM8250B.g.03h uart_lcr .1 sta uart_found ret mov b. m .b out uart_buffer ret cin: in uart_line_status ani 1 jz cin in uart_buffer ret . get A from [HL] cpi 0 jnz put_str1 ret put_str1: call cout inx h jp put_str 28 . data available? . restore a . input: HL put_str: mov a. transmitter ready? . print string terminated by 0 .ani 20h jz cout1 mov a. . 2MHz/65536 = 30. write to onboard LED . .TBL" .5 The 8254 counter0 was loaded with 0000 by system monitor. enable rst7.5! .*R/7/D&*#6/BU?8C/Q""$-S<% . interrupt vector of RST7. jump here org 0e000h count dfs 1 end . put instruction JMP to boot from RAM .899%#.5 (relocated from 003CH) jmp service_rst7. The input clock to the 8254 is 2MHz.HEX FORMAT gpio equ 0 . set interrupt mask register ei . .52Hz interrupt at RST7.52Hz interrupt signal at RST7. MTK-85 8085 Microprocessor Training Kit exp1.11111011b .5 sim . . CPU "8085.CPU TABLE HOF "INT8" .asm Using 8254 to produce 30. enable NVRAM boot running org 8000h jmp start org 803ch . use RAM one byte for count variable 29 . increment count .5: lda inr sta out ei ret count a count gpio . the OUT0 then produces . . enable interrupt jmp $ service_rst7. .5 org 8100h start: mvi a. B C.E B.C L.H D.L E.dble B D B D adr adr adr adr nnnn nnnn nnnn nnnn STAX STAX LDAX LDAX STA LDA SHLD LHLD XCHG STACK C5 D5 E5 F5 PUSH PUSH PUSH PUSH B D H PSW .A M.E A.byte B.A D.(/1(2324(5$6789.A H.M E.C E.D L.H B.byte L.byte D.D B.L A.A L.D D.E D.B L.B D.C D.M C.D A.B A.L M.M B.H A.-&$#(.C M.A A.D M.L H.A A.L C.A C.C A.B M. LOAD and STORE 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV B.H L.L 6E 6F 70 71 72 73 74 75 77 78 79 7A 7B 7C 7D 7E 7F 3E 06 0E 16 1E 26 2E 36 01 11 21 31 02 12 0A 1A 32 3A 22 2A EB nn nn nn nn nn nn nn nn nnnn nnnn nnnn nnnn MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MVI MVI MVI MVI MVI MVI MVI MVI LXI LXI LXI LXI L.M L.D H.B H.dble SP.B E.L D.E L.H M.dble H.E H.byte M.D C.M A.byte H.H H.B B.E M.byte E.M D.H C.!""#$%&'()(*+.A E.byte C.M H.E C.dble D.L B.D E.C B.byte B.C H.C C.E E./%#(+$%(*$#0/$&.H E.7&/$6 MOVE. C1 D1 E1 F1 E3 F9 33 3B ARITHEMATICS C6 nn CE nn 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F D6 nn DE nn 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F POP POP POP POP XTHL SPHL INX DCX B D H PSW SP SP 09 19 29 39 LOGICAL E6 nn EE nn F6 nn A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 DAD DAD DAD DAD B D H SP ADI ACI ADD ADD ADD ADD ADD ADD ADD ADD ADC ADC ADC ADC ADC ADC ADC ADC SUI SBI SUB SUB SUB SUB SUB SUB SUB SUB SBB SBB SBB SBB SBB SBB SBB SBB byte byte B C D E H L M A B C D E H L M A byte byte B C D E H L M A B C D E H L M A ANI XRI ORI ANA ANA ANA ANA ANA ANA ANA ANA XRA XRA XRA XRA XRA XRA XRA XRA ORA ORA ORA ORA ORA ORA ORA ORA byte byte byte B C D E H L M A B C D E H L M A B C D E H L M A COMPARE FE nn B8 B9 BA BB BC BD BE BF CPI CMP CMP CMP CMP CMP CMP CMP CMP byte B C D E H L M A ROTATE . 07! 17 0F 1F RLC RAL RRC RAR F7 FF RST RST 6 7 INPUT/OUTPUT DB nn D3 nn IN OUT byte byte JUMP C3 DA D2 CA C2 F2 FA EA E2 E9 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn JMP JC JNC JZ JNZ JP JM JPE JPO PCHL adr adr adr adr adr adr adr adr adr INCREMENT/DECREMENT 04 0C 14 1C 24 2C 34 3C 03 13 23 05 0D 15 1D 25 2D 35 3D 0B 1B 2B INR INR INR INR INR INR INR INR INX INX INX DCR DCR DCR DCR DCR DCR DCR DCR DCX DCX DCX B C D E H L M A B D H B C D E H L M A B D H CALL CD DC D4 CC C4 F4 FC EC E4 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn CALL CC CNC CZ CNZ CP CM CPE CPO adr adr adr adr adr adr adr adr adr RETURN C9 D8 D0 C8 C0 F0 F8 E8 E0 RET RC RNC RZ RNZ RP RM RPE RPO SPECIALS 2F 37 3F 27 CMA STC CMC DAA RESTART C7 CF D7 DF E7 EF RST RST RST RST RST RST 0 1 2 3 4 5 CONTROL 00! F3 FB 76 20 30 NOP DI EI HLT RIM SIM . 7k U9E 10 11 TRACE QA QB QC QD QE QF QG QH R11 3 4 5 6 10 11 12 13 R8 330 LED D3 LED D5 R9 330 LED D6 330 LED 13 74LS04 74LS04 Size B Date: 5 4 3 2 5 4 2 3 4 5 6 7 8 9 12 13 14 15 16 17 18 19 RAM_CE ROM_CE I I I I I I I I I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q C 6 S0 S1 A4 A5 A6 A7 U7 47pF C1 4MHz Q1 2 SID TRAP 5 6 9 8 7 10 INTA 11 29 33 39 READY 35 R3 ALE WR RD IO/M RST-OT CLKO SOD HLDA 30 31 32 34 3 37 4 38 S0 S1 HOLD +5V A15 ALE A8 A9 A10 A11 A12 A13 A14 RST5.5 1 2 RST5... 2005 Sheet 1 of 4 1 . July 30.7] A[0.7k R15 4.5 RST 6.5 3 4 RST6.5 *RST6..5 RST7.5 RST 7.5 INTR 36 RST-IN AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A8 A9 A10 A11 A12 A13 A14 A15 IO/M 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 D0 D1 D2 D3 D4 D5 D6 D7 4001 D1 1N4148 47pF R1 100k C2 A15 /RD /WR SYSTEM_PPI GPIO CTC USER_PPI UART LCD_E 1 11 I/CLK I/OE GAL16V8D +5V VCC S1 VCC VSS RESET R2 1k + 3 2 1 OUT GND VCC U25 B KIA7045 C3 1uF U9A WR RD RESET_OUT CLKOUT reset CLKOUT SW1 1 2 3 4 8 7 6 5 *RST5.7] D[0.5 A 8085 Microprocesssor Training Kit Document Number <Doc> Rev 2 Saturday.7k 74LS04 U9C +5V 10 GPIO_LED1 SW2 GPIO_LED2 NO 2 NC GPIO_LED3 1 3 PS2273 U6D +5V R10 12 11 13 GPIO_LED4 4.5 B +5V SOD HLDA +5V R4 4.7k 4001 U9F 12 Title D4 LED 9 4001 R7 330 5 D2 6 RST7.7k U6C 74LS04 U9B SW DIP-4/SM *RST6.5 74LS04 U9D *INTR 9 8 INTR ALE 8 CLK CLR 74LS164 9 A 74LS04 *RST7..5 4 3 2 1 D[0.7] A[0..7k +5V 8 R6 330 SID U10 1 2 A B +5V TRAP R21 4.5 *RST7. NVRAM D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 RAM_CE /RD /WR 20 22 27 CE OE WE HM62256B 10 9 8 7 6 5 4 3 25 24 21 23 2 26 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 D0 D1 D2 D3 D4 D5 D6 D7 11 12 13 15 16 17 18 19 U3 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 /RD /WR IO/M SID ALE SOD S0 S1 CLKOUT READY RESET_OUT 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 HEADER 20X2 GPIO /WR U6A 1 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 JP1 A0 A1 A2 A3 A4 A5 A6 A7 D0 U1 4 D1 D1 5 D0 D1 D2 D3 D4 D5 D6 D7 2 3 4 5 6 7 8 9 1D 2D 3D 4D 5D 6D 7D 8D LE OE VCC 74HC573 +5V +5V 27C256 A[8.5 INTR INTA S0 S1 HOLD READY MSM80C85A 4.5 *INTR INTA HOLD HLDA 9 1 CLK CLR 74LS175 U5 +5V D4 D5 D6 D7 3 6 8 11 1Y 2Y 3Y 4Y 1A 2A 3A 4A 2 5 9 12 3 2 4001 1OE 2OE 3OE 4OE 1 4 10 13 74LS126 U6B U8 /RD C memory & i/o decoder RESET_IN +5V 1 X1 X2 SID TRAP RST 5.7] J1 +5V 0x0000-0x7FFF Monitor Program U4 D 0x8000-0xFFFF 32kB SRAM.5 +5V R5 4.14] ROM_CE /RD 20 22 1 CE OE VPP A8 A9 A10 A11 A12 A13 A14 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 11 1 20 19 18 17 16 15 14 13 12 A0 A1 A2 A3 A4 A5 A6 A7 ALE A0 A1 A2 A3 A4 A5 A6 A7 10 9 8 7 6 5 4 3 25 24 21 23 2 26 27 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 O0 O1 O2 O3 O4 O5 O6 O7 11 12 13 15 16 17 18 19 U2 D2 D2 12 D3 D3 13 D4 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 2 3 7 6 10 11 15 14 1 GPIO_LED1 3 5 GPIO_LED2 7 9 GPIO_LED3 11 13 GPIO_LED4 15 + + + + + + + + + + + + + + + + 2 4 6 8 10 12 14 16 D RESET_IN *RST5.5 RST6. 7k A A D[0..7] SW25 SW26 SW27 SW28 Title Size B Date: 5 4 3 2 8085 Microprocessor Training Kit Document Number <Doc> Rev 2 Saturday. July 30.7] U13 U14 U15 U16 U17 1 19 18 16 14 12 9 7 5 3 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 D U11 R12 +5V VCC D VCC VSS A0 A1 A2 A3 A4 A5 A6 A7 com1 com2 com1 com2 com1 com2 com1 com2 com1 com2 TOS-5161AE 3 8 3 8 3 8 3 8 U18 0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 9 10 11 TOS-5161AE TOS-5161AE TOS-5161AE 3 8 COMMON CATHODE 6-DIGIT 7-SEGMENT LED TOS-5161AE 3 8 com1 com2 TOS-5161AE a b c d e f g dp SPEAKER 1 C PC0 PC1 PC2 PC3 15 14 13 12 A B C D 2 Q2 BC327 3 C R13 100 74LS145 SYSTEM_PPI SW29 SU1 0x10-0x13 8255 SPEAKER PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 TRACE SW4 SW5 SW6 SW7 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC5 PC4 PC3 PC2 PC1 PC0 SW9 SW13 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 SW17 SW10 SW14 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 37 38 39 40 1 2 3 4 10 11 12 13 17 16 15 14 25 24 23 22 21 20 19 18 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 SW PUSHBUTTON SPEAKER SW3 PA6 user_key1 SW8 SW11 SW12 PA7 +5V B reset A1 A0 WR RD D7 D6 D5 D4 D3 D2 D1 D0 27 28 29 30 31 32 33 34 D7 D6 D5 D4 D3 D2 D1 D0 U19 6 35 8 9 36 5 CS RESET A1 A0 WR RD user_key2 SW15 SW16 B +5V PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 SW18 SW19 SW20 R14 2 3 4 5 6 7 8 9 1 C SW21 SW22 SW24 SW23 4. 2005 Sheet 2 of 4 1 ..5 4 3 2 1 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 2 4 6 8 11 13 15 17 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 R-PACK 7 6 4 2 1 9 10 5 7 6 4 2 1 9 10 5 7 6 4 2 1 9 10 5 7 6 4 2 1 9 10 5 7 6 4 2 1 9 10 5 7 6 4 2 1 9 10 5 1G 2G 74LS244 U12 a b c d e f g dp a b c d e f g dp a b c d e f g dp a b c d e f g dp a b c d e f g dp A[0. ..7] CTC A0 A1 A2 A3 A4 A5 A6 A7 A0 A1 U21 D 2MHz counter/timer C User PPI 0x30-0x33 D0 D1 D2 D3 D4 D5 D6 D7 34 33 32 31 30 29 28 27 D0 D1 D2 D3 D4 D5 D6 D7 RD WR A0 A1 RESET CS 18 19 20 21 22 23 24 25 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 5 36 9 8 35 6 4 3 2 1 40 39 38 37 RD WR A0 A1 reset USER_PPI U22 UART +5V C VCC VCC VSS +5V SW30 1 2 D7 D6 D5 D4 D3 D2 D1 D0 3 0x50-0x53 backlight text LCD B USER_PA0 USER_PA1 USER_PA2 USER_PA3 USER_PA4 USER_PA5 USER_PA6 USER_PA7 R/W RS LCD_E A1 A0 B LCD_E 2 CONN RECT 16 +5V 3 VB1 A A Title RS232 level converter 8085 Microprocessor Training Kit Size B Date: Document Number <Doc> Rev 2 Saturday.5 4 3 2 1 D[0. (male) use straight cable 10uF + C9 + JR1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 16 17 28 27 26 12 13 14 A0 A1 A2 +5V 18 19 21 22 25 35 36 37 38 39 WR RD reset DCD 10 RxD +5V 0x40-0x47 UART D0 D1 D2 D3 D4 D5 D6 D7 1 2 3 4 5 6 7 8 D0 D1 D2 D3 D4 D5 D6 D7 SDO OUT1 OUT2 DDIS TXRDY RXRDY INTRPT RTS DTR TxD 11 34 31 +5V R17 4.7k R18 4. 2005 4 3 2 Sheet 3 of 4 5 1 . July 30.7k RTS 23 24 29 30 32 33 0x20-0x23 D D0 D1 D2 D3 D4 D5 D6 D7 8 7 6 5 4 3 2 1 D0 D1 D2 D3 D4 D5 D6 D7 CLK0 G0 OUT0 *RST7.5 CLK1 G1 OUT1 CLK2 G2 OUT2 18 16 17 15 14 13 9 11 10 RD WR A0 A1 CS 8254 22 23 19 20 21 RD WR A[0.7] CLKOUT U20 SDI WR1 WR2 RD1 RD2 ADS MR CTS DSR DCD RI XIN XOUT A0 A1 A2 9 15 RCLK BAUDOUT CS0 CS1 CS2 TL16C550A USER_PA0 USER_PA1 USER_PA2 USER_PA3 USER_PA4 USER_PA5 USER_PA6 USER_PA7 JP2 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 8255 +5V 10uF C7 R19 10K C+ C1C2+ C2V+ V6 14 7 13 8 T1OUT T2OUT R1IN R2IN MAX232A T1IN T2IN R1OUT R2OUT 1 3 4 5 11 10 12 9 + 14 15 16 17 13 12 11 10 HEADER 20X2 1 10uF 10V C6 U23 2 5 9 4 8 3 7 2 6 1 C8 + 10uF TxD RTS RxD DCD SUB-D 9. 1uF C17 0.1uF C15 0.1uF VCC VSS B B +5V + C24 10uF + C25 10uF + C26 10uF + C27 10uF A A Title Size B Date: 5 4 3 2 8085 Microprocessor Training Kit Document Number <Doc> Rev Saturday. 2005 Sheet 4 of 4 1 .1uF C11 1000uF25V 2 1N4007 1 3 VOUT VIN GND C13 10uF 16V C14 0.1uF C22 0.1uF C10 2 C18 0.1uF C21 0.1uF C16 0.1uF + TP2 GND 0.0 D8 1 + C19 0.1uF +5V 1 J6 1 2 DC Input +5V C C +5V VCC C20 0.1uF 1 C12 0.1uF C23 0.5 4 3 2 1 J5 1 2 3 D7 D R20 2k CON3 D POWER LED (red) +5V TP1 U24 LM2490-5. July 30.