Modeling Registers With Uvm Tom Fitzpatrick

Design and Verification in the SoC Era: Modeling Registers with UVMTom Fitzpatrick Verification Evangelist DVT October 2011 The Idea Behind The Methodology  OVM & UVM underpin best practices — It's all about people... — Team Development  Peopleware is most important — — — — Develop Skill Set Common language Strategy and cohesion Clarity and transparency  A Guiding Methodology — Provides Freedom From Choice — Avoids Chaos and Repetition — Ease of Use APIs — Not just for Super-heroes! © 2011 Mentor Graphics Corp. Company Confidential 2 TF - UVM Recipe of the Month 10/11 www.mentor.com UVM Foundations Objective      Justification      Separation of stimulus generation from delivery Raise the abstraction level of stimulus and checking Test bench configuration Interoperability Reuse — Standard class library & API Several people can develop stimulus Increase productivity Avoid expensive recompilation Important for intra and inter company development Key to productivity — VIP — Testbench components — Stimulus © 2011 Mentor Graphics Corp. Company Confidential 3 TF - UVM Recipe of the Month 10/11 www.mentor.com UVM Testbench - Architectural Design For Each Interface: • How does the interface work? • What information is transferred? • Transaction variants? • Uni/bidirectional? Pipelined? APB DUT SPI I/F IRQ For the Design: • What does it do? • What are the use cases? • Which test cases are required? • What type of stimulus scenarios are required? • What represents correct behavior? • What kind of functional coverage do I need? 4 TF - UVM Recipe of the Month 10/11 www.mentor.com © 2011 Mentor Graphics Corp. Company Confidential UVC Structural Building Block Analysis port: Send transactions for checking .UVM Recipe of the Month 10/11 www.Pass information on how agent should behave Detects transactions on the interface UVC(agent) Configuration Object Sequencer Monitor One per interface Sends stimulus to Driver seq_item Driver DUT Stimulus Converts seq_item to pin wiggles © 2011 Mentor Graphics Corp.Contains virtual interface handle . Company Confidential 5 TF .com .mentor. write(0xDE).com . 0xDE). © 2011 Mentor Graphics Corp.UVM Registers are Layered  UVM Register Layer provides protocol-independent register-based layering UVM Reg Layer Predict RegSeq UVC(agent) Configuration Object Sequencer Monitor Driver DUT Device specific cfg.mentor.UVM Recipe of the Month 10/11 Bus specific wr(0xAF. Company Confidential www. 7 TF . Registers. Blocks & Maps Registers contain bits & fields Register Map contains Registers Register Block contains Maps One Map per physical interface Blocks are hierarchical 31:14 Reserved 13 ASS 12 IE 11 10 9 8 7 R 6:0 Char_Len R R/W R/W R/W R/W R/W R/W LSB TxNeg RxNeg GoBsy Rsrv R/W © 2011 Mentor Graphics Corp. Company Confidential 8 TF .com .UVM Recipe of the Month 10/11 www.mentor. Company Confidential 9 TF .com .UVM Recipe of the Month 10/11 www.mentor. AXI Master2 (Fabric) UVC(agent) Monitor Sequencer Driver DUT © 2011 Mentor Graphics Corp.The Register Map – uvm_reg_map  Contains offsets for: — Registers and Memories — (Hierachical blocks) — (Sub-maps) SQR  Also provides means to access registers — Handle for target sequencer — Handle for register layer adapter  A block can have > 1 map SQR — AXI Master1. Set this bit in this register rather than write x to address y – If the bus agent changes.com .UVM Register Use Models  Stimulus Generation — Stimulus reuse — Abstraction of stimulus: – i.e. the stimulus still works – Front door is via an agent – Back door is directly to the hardware via the simulator database — Front and Back Door access:  Configuration — Register model reflects hardware programmable registers — Set up desired configuration in register model then dump to DUT – Randomization with configuration constraints  Analysis ‘Mirror’ — Current state of the register model matches the DUT hardware — Useful for scoreboards and functional coverage monitors © 2011 Mentor Graphics Corp.UVM Recipe of the Month 10/11 www. Company Confidential 10 TF .mentor. "RW"). super. 16'hffff.Register Model Code Example (Only 1 Reg) Register class with one field Block containing Register class spi_reg_block extends uvm_reg_block. 0.configure(this. rand uvm_reg_field ratio. "RW". 16). Company Confidential www. null.mentor. endfunction virtual function void build(). lock_model(). divider_reg = divider::type_id::create("divider").add_hdl_path_slice("divider". divider_reg. ratio. endfunction: build endclass: spi_reg_block 11 TF . `uvm_object_utils(divider) uvm_reg_field reserved. divider_reg. 32'h00000014. 0. endfunction endclass #bits Coverage function new(string name = "spi_reg_block"). add_hdl_path("DUT". endfunction virtual function void build(). divider_reg.add_reg(divider_reg. 0.com . "RTL"). ""). 'h800.build(). 4.new(name. UVM_NO_COVERAGE). 16. 1. UVM_LITTLE_ENDIAN). 1). super. // Block map class divider extends uvm_reg.new(name. `uvm_object_utils(spi_reg_block) rand divider divider_reg. uvm_reg_map APB_map. 32. APB_map. function new(string name = "divider"). build_coverage(UVM_CVR_ADDR_MAP)). 1.configure(this. ratio = uvm_reg_field::type_id::create("ratio"). APB_map = create_map("APB_map".UVM Recipe of the Month 10/11 #bits lsb mode reset Build is not the component build A map is a component of a block © 2011 Mentor Graphics Corp. 32. divider_reg. rand uvm_reg_field ratio. ""). 1. Build is not the component build A map is a component of a block add_hdl_path("DUT". 32'h00000014. ratio = uvm_reg_field::type_id::create("ratio"). "RW"). endfunction: build endclass: spi_reg_block 12 TF . APB_map = create_map("APB_map". rand divider divider_reg.new(name.mentor. build_coverage(UVM_CVR_ADDR_MAP)). 16'hffff. null.add_reg(divider_reg. "RW". endfunction virtual function void build().configure(this. UVM_LITTLE_ENDIAN). UVM_NO_COVERAGE). // Block map UVM_CVR_FIELD_VALS endclass function new(string name = "spi_reg_block"). `uvm_object_utils(spi_reg_block) class divider extends uvm_reg. `uvm_object_utils(divider) uvm_reg_field reserved. super. 4. "RTL").com .configure(this.build().new(name.add_hdl_path_slice("divider". endfunction uvm_reg_map APB_map. lock_model(). UVM_CVR_ADDR_MAP ratio. APB_map. 16. 'h800. 16). 0. divider_reg = divider::type_id::create("divider"). function new(string name = "divider").UVM Recipe of the Month 10/11 © 2011 Mentor Graphics Corp. endfunction UVM_NO_COVERAGE UVM_CVR_REG_BITS virtual function void build(). Company Confidential www. divider_reg. UVM_CVR_ALL super. 1). divider_reg. 0.Register Model Code Example (Only 1 Reg) Register class with one field Block containing Register class spi_reg_block extends uvm_reg_block. 0. 1. Company Confidential www.Register Assistant* Overview  Register/Memory Definition & Management for the Entire Design Process Central.mentor. Scalable & Extensible Register/Memory Datamodel — — — — Enables easy specification of registers Manages register changes Eliminates hand coding & resultant mistakes Completely customizable  Automatically Generates Register Outputs — — — — OVM/UVM Register Package Synthesizable RTL Documentation Extensive roadmap * Included with Certe Testbench Studio 13 Supports the entire design team © 2011 Mentor Graphics Corp.com . Common Register Path    Generate the UVM/OVM register model Generate the DUT registers Use Certe templates to generate UVM sequences.mentor. Company Confidential 14 www. adaptor class & the bus agent Template Generated SQR Register Assistant -Generation UVC(agent) Template-Generated RegSeq Sequencer Monitor Driver DUT © 2011 Mentor Graphics Corp.com . UVM Register Package Generation Optional Blocks & Block Maps Customer Example Register Definitions Early in project: 335 Registers  11.500 lines Final project: 1.000 Registers  35.000+ lines of Register Package code © 2011 Mentor Graphics Corp. Company Confidential 15 www.com .mentor. Register Documentation Generation  Communicate the register layer to all team members Final documents auto-generated Customizable content & style   © 2011 Mentor Graphics Corp. Company Confidential 16 www.mentor.com . Definitions Documentation Blocks A Readers P I Datamodel A P I Writers RTL Block Map OVM/UVM Pkg.The Architecture – Open & Extensible Spreadsheet (CSV) IP-XACT API calls Control File Reg.mentor.com . Company Confidential 17 www. Checks © 2011 Mentor Graphics Corp. Company Confidential 18 www.mentor.com .UVM Coverage   You can specify the coverage model you wish to generate for instances in a block Simply add a column to your spreadsheet © 2011 Mentor Graphics Corp. com . Company Confidential 19 TF .mentor. register model updated with result — Can be used for individual fields — Desired value  The register model has two register variables: — Mirrored value – For when a field has been updated.poke() — For back door accesses.UVM Recipe of the Month 10/11 www.read() and reg.UVM Register Class Access API Direct access methods  reg.write()  — Access the hardware register and update the register database — Can specify front or back door access – Front door access takes time and may create side effects – Uses bus agent and consumes clock cycles – Uses simulation database and access API (VPI) – Back door access is instant and does not cause side effects — Not used for individual fields  reg.peek() and reg. but not the hardware – Containing the latest known value © 2011 Mentor Graphics Corp. ctrl.UVM Recipe of the Month 10/11 www.write(status. Company Confidential 20 TF .mentor.Register Access Method Fields Type uvm_status_e uvm_reg_data_t uvm_path_e uvm_reg_map uvm_sequence_base int uvm_object string int Name status value path map parent prior extension fname lineno Purpose Indicates Access completed OK Data value transfered Front or back door access Map to use for access Parent sequence Sequence priority on sequencer Transfer extension object Filename (For reporting) Line number (For reporting)   Good news – most of these fields have defaults! A typical register access only needs a few of these: spi_rm. wdata. . © 2011 Mentor Graphics Corp.com .parent(this)). // Returning access status // Common functionality: // Getting a handle to the register model task body.com . `uvm_object_utils(spi_bus_base_seq) // SPI Register model: spi_reg_block spi_rm.Register Stimulus Examples – Base Class class spi_bus_base_seq extends uvm_sequence #(uvm_sequence_item).UVM Recipe of the Month 10/11 www. spi_rm = m_cfg.mentor. status • register model handle // Properties used by the various register access methods: rand uvm_reg_data_t data. // For passing data uvm_status_e status. m_cfg = spi_env_config::get_config(m_sequencer). // SPI env config object (contains register model spi_env_config m_cfg. Sequence base class contains variables common to all register sequences: handle) • data.spi_rm. Company Confidential 21 TF . endtask: body endclass: spi_bus_base_seq © 2011 Mentor Graphics Corp. 16'h40.write(status. Company Confidential 22 TF .divider_reg. super.} task body. . 16'h4. 16'h20.parent(this)).com . data. // Write to the divider register spi_rm. `uvm_object_utils(div_load_seq) // Interesting divisor values: constraint div_values {data[15:0] inside {16'h0.UVM Recipe of the Month 10/11 www. 16'h8. 16'h2. // Randomize the local data value assert(this.Register Stimulus Example: Set Divider Value class div_load_seq extends spi_bus_base_seq.body.randomize()).mentor. 16'h10. endtask: body endclass: div_load_seq Extends base sequence Randomizes data value with specific constraint Writes data to divider register © 2011 Mentor Graphics Corp. 16'h80}. 16'h1. spi_rm.Register Sequence Example – TX Data Load class data_load_seq extends spi_bus_base_seq.rxtx2_reg.update(status. . Gets an array of register handles super.path(UVM_FRONTDOOR).com .UVM Recipe of the Month 10/11 www. // Set up the data register handle array data_regs = '{spi_rm.mentor.rxtx0_reg. spi_rm.randomize()). `uvm_object_utils(data_load_seq) Extends the base class uvm_reg data_regs[]. Randomizes the array index order // Randomize order data_regs. data_regs[i]. Foreach reg in the array: foreach(data_regs[i]) begin Randomize the content // Randomize register content and then update Updates the register assert(data_regs[i].body. Company Confidential 23 TF .shuffle(). // Array of registers task body.rxtx1_reg.rxtx3_reg}.parent(this)). . spi_rm. end endtask: body endclass: data_load_seq © 2011 Mentor Graphics Corp. Read or Write — The register access method forms a generic register command: — This is then sent through a layering to the target bus agent  The layering has to convert: — Generic register requests to target bus sequence items  This conversion takes place in the adapter B SQR — Extended from uvm_reg_adapter UVC(agent) Monitor RegSeq Reg Sequencer Driver DUT © 2011 Mentor Graphics Corp.com .How Do Front Door Register Accesses Work?  When an explicit register access method is called – Address.UVM Recipe of the Month 10/11 www.mentor. Company Confidential 24 TF . Data. HWRITE = (rw.DATA.status = UVM_IS_OK.DATA = rw. endfunction reg2bus() converts register item to bus item – note single access only virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw). rw. `uvm_object_utils(reg2ahb_adapter) function new(string name = "reg2ahb_adapter").data. rw. super.HADDR = rw. ahb.HADDR. return ahb. if (!$cast(ahb.kind = (ahb. ahb.com . rw.Register Adapter Class Example class reg2ahb_adapter extends uvm_reg_adapter. bus_item)) begin `uvm_fatal("NOT_AHB_TYPE".mentor.UVM Recipe of the Month 10/11 www.addr = ahb. endfunction endclass: reg2ahb_adapter bus2reg() converts bus item to reg item © 2011 Mentor Graphics Corp.HWRITE == AHB_READ) ? UVM_READ : UVM_WRITE. Company Confidential 25 TF . endfunction virtual function void bus2reg(uvm_sequence_item bus_item.data = ahb. end rw.kind == UVM_READ) ? AHB_READ : AHB_WRITE. ahb_seq_item ahb. ref uvm_reg_bus_op rw).addr. ahb.new(name)."Provided bus_item is not of the correct type") return. ahb_seq_item ahb = ahb_seq_item::type_id::create("ahb"). mentor.UVM Recipe of the Month 10/11 © 2011 Mentor Graphics Corp. Company Confidential www.com .Keeping The Register Model Up To Date  Need to update register model with results of hardware access — This is referred to as prediction — Auto prediction  Two ways: – Register model updates based on value written or read back – OK in simple situations where only one way to access the DUT registers – Requires no additional components – A predictor component: — Explicit prediction (UVM Default) – Observes bus analysis transactions – Updates the register model on what it observes – Works for normal to complex scenarios – Supports hierarchical reuse 26 TF . Breq SQR UVC(agent) Monitor RegSeq Sequencer Reg www.UVM Recipe of the Month 10/11 .mentor.Auto Prediction  For ‘simple’ scenarios: — Only sequences accessing the bus agent are register sequences — Register can only be accessed via one bus — Based on value read or written to the register   The register model updates itself Has to be enabled – reg_model.set_auto_predict(1). Company Confidential 27 TF .com Driver reg © 2011 Mentor Graphics Corp. Explicit Prediction .UVM Recipe of the Month 10/11 www.Recommended   Supports arbitrary complexity Predictor component updates register model — Based on any detected bus transaction — Regardless of origin  Supports vertical reuse Reg Breq SQR UVC(agent) Predictor RegSeq Monitor Reg Sequencer Breq Driver Breq reg © 2011 Mentor Graphics Corp.mentor. Company Confidential 28 TF .com . UVM Recipe of the Month 10/11 www.Explicit Prediction .com . Company Confidential 30 TF .Recommended Predictor RegSeq Sequencer Driver UVC(agent) Monitor SQR SQR reg UVC(agent) Predictor RegSeq Sequencer Driver Monitor reg © 2011 Mentor Graphics Corp.mentor. Company Confidential 31 TF . end endfunction: connect © 2011 Mentor Graphics Corp. reg2apb).bus_in).Register Model Testbench Integration class spi_env extends uvm_env. // Connect the predictor to the bus agent monitor analysis port m_apb_agent.TOP_map.ss_rm. spi_env_config m_cfg.mentor.UVM Recipe of the Month 10/11 www. if(m_cfg.adapter = reg2apb. Register adapter specific to bus agent function void spi_env::connect_phase(uvm_phase phase).active == UVM_ACTIVE) begin reg2apb = reg2apb_adapter::type_id::create("reg2apb").map = m_cfg. apb_agent m_apb_agent. uvm base class // Register predictor: uvm_reg_predictor #(apb_seq_item) apb2reg_predictor.TOP_map.m_apb_agent_cfg. // Set the predictor map: apb2reg_predictor. Predictor is integrated during // Set the predictor adapter: the connect phase apb2reg_predictor. // Register layering adapter: Predictor is a parameterised reg2apb_adapter reg2apb.connect(apb2reg_predictor.set_sequencer(m_apb_agent.com . // Register sequencer layering part: m_cfg.ss_rm.m_sequencer.ap. UVM Recipe of the Month 10/11 www. Company Confidential 32 TF .mentor.Register Read And The Register Mirror Before mirrored value After mirrored value  Read cycle results in the register model being updated desired value desired value hardware value hardware value Mirrored and desired value updated at the end of the bus read cycle Mirrored and desired value out of step with hardware value © 2011 Mentor Graphics Corp.com . Company Confidential 33 TF .UVM Recipe of the Month 10/11 www.mentor.com .Register Write And The Register Mirror Before mirrored value During mirrored value After mirrored value desired value desired value desired value hardware value Initial state. hardware and reg model in sync hardware value Hardware value changed by bus write cycle hardware value Mirrored and desired value updated at the end of the write cycle © 2011 Mentor Graphics Corp. get_reset()  reg.com .update() — Cause the hardware to be updated if register model content has changed via reg.Register Model Internal Access And Update()    Indirect methods: — Only access the register database — Can be used on registers and fields — set/get the register or field reset value reg. Company Confidential TF .randomize() — Can specify front or back door access  34 These methods set the desired value © 2011 Mentor Graphics Corp.UVM Recipe of the Month 10/11 www.mentor. reg.set().set().get().reset() or reg.reset(). reg. reg. reg. Company Confidential 35 TF .com . set()) hardware value Update() transfers desired value to HW via a write bus cycle hardware value Mirrored value updated at the end of the write cycle © 2011 Mentor Graphics Corp.Register Write And The Register Mirror Before mirrored value set() mirrored value update() mirrored value After mirrored value desired value desired value desired value desired value hardware value Initial state.UVM Recipe of the Month 10/11 www. hardware and reg model in sync hardware value Desired value changed by indirect access method (e.g.mentor. g. Clock enable bit — Mechanism is to use the uvm_resource_db to set an attribute for the register © 2011 Mentor Graphics Corp.g.UVM Recipe of the Month 10/11 www. Company Confidential 36 TF . Read only registers are not bit bashed — Read only memories are not tested  Memories.Built-In Sequences  Sequences are automatic — Low overhead to use — Useful for initial sanity checks on bus connectivity  Access modes are respected — e.mentor.com . Registers or Fields can be opted out of a test — e. com .mentor. Company Confidential 37 TF .UVM Recipe of the Month 10/11 www. checks that accesses can be made from each map © 2011 Mentor Graphics Corp.Register Built-In Sequences Sequence Name uvm_reg_hw_reset_seq uvm_reg_single_bit_bash_seq uvm_reg_bit_bash_seq uvm_reg_single_access_seq uvm_reg_access_seq uvm_reg_shared_access_seq Description Checks register reset values Checks R/W path to each register bit in a register Runs single_bit_bash_seq on a register block Checks that both front and back door accesses work correctly for a register Runs single_access_seq on a register block If a register is in multiple maps. UVM Recipe of the Month 10/11 www.Stimulus Reuse (Bridge Example)    SPI master is integrated inside an AHB peripheral block Host bus sequences can reused as is Testbench structure changes AHB to APB Bridge SPI Master SPI Host Bus Sequence AHB APB Bus Agent APB SPI Another DUT APB ANI Another DUT APB ANI APB ANI © 2011 Mentor Graphics Corp.com .mentor. Company Confidential Another DUT 38 TF . active == UVM_ACTIVE) begin reg2apb = reg2apb_adapter::type_id::create("reg2apb").TOP_map.m_sequencer.set_sequencer(m_apb_agent. // Set the predictor map: apb2reg_predictor. function void spi_env::connect_phase(uvm_phase phase).adapter = reg2apb.ap.ss_rm.com .UVM Recipe of the Month 10/11 www.connect(apb2reg_predictor. // Set the predictor adapter: apb2reg_predictor. // Connect the predictor to the bus agent monitor analysis port m_apb_agent.m_apb_agent_cfg.Stimulus Reuse Code Example class spi_env extends uvm_env. // Register layering adapter: reg2apb_adapter reg2apb.bus_in). // Register predictor: uvm_reg_predictor #(apb_seq_item) apb2reg_predictor.ss_rm.map = m_cfg.TOP_map. Company Confidential 39 TF . apb_agent m_apb_agent. end endfunction: connect © 2011 Mentor Graphics Corp. if(m_cfg. spi_env_config m_cfg. // Register sequencer layering part: m_cfg. reg2apb).mentor. // Set the predictor map: apb2reg_predictor.UVM Recipe of the Month 10/11 www.bus_in). reg2ahb_adapter reg2ahb. end endfunction: connect © 2011 Mentor Graphics Corp.m_ahb_agent_cfg. m_cfg. // Register predictor: uvm_reg_predictor #(apb_seq_item) apb2reg_predictor.ss_rm.adapter reg2ahb.adapter = reg2apb.map = m_cfg.m_sequencer. apb_agent m_apb_agent. ahb2reg_predictor.m_apb_agent_cfg.m_sequencer.Stimulus Reuse Code Example class spi_env extends uvm_env. Company Confidential 40 TF .connect(ahb2reg_predictor.connect(apb2reg_predictor.map m_cfg. reg2apb).bus_in).set_sequencer(m_ahb_agent. m_ahb_agent. reg2ahb reg2ahb_adapter::type_id::create("reg2ahb"). // Set the predictor adapter: apb2reg_predictor.active reg2apb = reg2apb_adapter::type_id::create("reg2apb").ap. // Register sequencer layering part: m_cfg. #(ahb_seq_item) ahb2reg_predictor. ahb2reg_predictor.TOP_map. ahb_agent m_ahb_agent.TOP_map.TOP_map.io_ss_rm. io_ss_env_config m_cfg.ap. if(m_cfg. spi_env_config m_cfg. // Connect the predictor to the bus agent monitor analysis port m_apb_agent.active == UVM_ACTIVE) begin if(m_cfg. io_ss_env extends uvm_env.mentor. reg2ahb).io_ss_rm. function void spi_env::connect_phase(uvm_phase phase).set_sequencer(m_apb_agent.TOP_map.com .ss_rm. // Register layering adapter: reg2apb_adapter reg2apb. com . Company Confidential 41 TF .Stimulus Reuse Layer II – Across Fabric SPI Host Bus Sequence AXI Bus Fabric AXI Bus Agent AXI 2 AHB Bridge AHB to APB Bridge SPI Master APB SPI © 2011 Mentor Graphics Corp.mentor.UVM Recipe of the Month 10/11 www. write(status.UVM Recipe of the Month 10/11 www. 16'h40. `uvm_object_utils(div_load_seq) // Interesting divisor values: constraint div_values {data[15:0] inside {16'h0. 16'h4.parent(this)). 16'h10. // Randomize the local data value Sequence works as before but via the AHB agent assert(this. data.randomize()). Company Confidential 42 TF .body. 16'h1. 16'h8.divider_reg. // Write to the divider register spi_rm. 16'h2.com .mentor. model handle from config object. Extends base sequence which gets register super. 16'h80}.} task body. 16'h20. endtask: body endclass: div_load_seq © 2011 Mentor Graphics Corp. .Register Stimulus Reuse: Set Divider Value class div_load_seq extends spi_bus_base_seq. UVM Recipe of the Month 10/11 www. Company Confidential 43 TF .sys_rm. // Set the predictor adapter: axi2reg_predictor. // Set the predictor map: axi2reg_predictor.m_axi_agent_cfg. // Register predictor: uvm_reg_predictor #(axi_seq_item) axi2reg_predictor. // Connect the predictor to the bus agent monitor analysis port m_axi_agent. if(m_cfg.adapter = reg2axi.com .TOP_map.set_sequencer(m_axi_agent. // Register sequencer layering part: m_cfg. sys_env_config m_cfg.Relevant Parts Of Top Level Environment class sys_env extends uvm_env.bus_in).map = m_cfg. function void spi_env::connect_phase(uvm_phase phase).connect(axi2reg_predictor. reg2axi).active == UVM_ACTIVE) begin reg2axi = reg2axi_adapter::type_id::create("reg2axi").sys_rm.TOP_map. axi_agent m_axi_agent.m_sequencer.mentor.ap. // Register layering adapter: reg2ahb_adapter reg2axi. end endfunction: connect © 2011 Mentor Graphics Corp. function void spi_env::connect().svh” `include “uvm_reg_macros. axi_agent m_axi_agent.mentor. // Connect the predictor to the bus agent monitor analysis port m_axi_agent.com .m_axi_agent_cfg.sys_rm. Company Confidential 44 TF .TOP_map.svh” import ovm_pkg::*. // Register predictor: uvm_reg_predictor #(axi_seq_item) axi2reg_predictor. // Set the predictor map: axi2reg_predictor.m_sequencer. // Register sequencer layering part: m_cfg. sys_env_config m_cfg.ap. if(m_cfg.connect(axi2reg_predictor.TOP_map.adapter = reg2axi.active == UVM_ACTIVE) begin reg2axi = reg2axi_adapter::type_id::create("reg2axi"). class sys_env extends ovm_env.sys_rm. import uvm_reg_pkg::*.set_sequencer(m_axi_agent.UVM Recipe of the Month 10/11 www. // Register layering adapter: reg2ahb_adapter reg2axi.UVM Register Package Works with OVM `include “ovm_macros. // Set the predictor adapter: axi2reg_predictor. reg2axi). end endfunction: connect © 2011 Mentor Graphics Corp.map = m_cfg.bus_in). mentor. Blocks. Company Confidential TF .UVM Register Summary    Register model follows hardware structure — Fields. Registers.com . set() etc — External access – Front and Backdoor – Sets up desired value  Access layered via model — Generic sequences adapted to target bus sequences — Sequence reuse straight-forward    45 Use explicit prediction Built in sequences available for initial testing Works with OVM © 2011 Mentor Graphics Corp. Maps — Certe Register Assistant Register model generator available: Register access API: — Internal access – get().UVM Recipe of the Month 10/11 www. Mentor + UVM = Success  Mentor is uniquely able to meet your verification needs — Tools — Technology — Resources © 2011 Mentor Graphics Corp. Company Confidential 46 TF .com .mentor.UVM Recipe of the Month 10/11 www. com .© 2011 Mentor Graphics Corp. Company Confidential www.mentor.