Microprocessor 1

Chapter 10Memory Interface Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Objectives • Describe various memory types • Describe memory pin connections • Use decoders and PLDs (programmable logic devices) to decode memory addresses • Explain how to interface RAM and ROM to a microprocessor • Interface dynamic RAM to the microprocessor • Explain operation of dynamic RAM controller • Interface memory to all Intel microprocessors using 8-, 16-, 32-, and 64-bit data buses Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Types of Memory Devices Two main types of memory: • ROM - Read Only Memory - Non Volatile data storage (remains valid after power off) - For permanent storage of system software and data - Can be PROM, EPROM or EEPROM (Flash) memory • RAM - Random Access Memory (a misnomer - better Read/Write) - Volatile data storage (data disappears after power off) - For temporary storage of application software and data - Can be SRAM (static) or DRAM (dynamic) Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Memory Pin Connections • Address • Address Inputs: • Data • Control - Select the required location in memory. - Address lines are numbered from A0 to as many as required M to address all memory locations Write Enable e.g. 12-bit address: A0-A11 ⇒ 212 = 4K memory locations Only for RAM - Today’s memory devices Chip Output Chip Output have capacities upto around Select Enable Select Enable 1G locations (30 address lines) -Select chip -Specify whether you want - Example: 4K memory: 12 bits: a READ or WRITE operation Decode 000H-FFFH. e.g. from this part 301000H to 301FFFH on an ROMs have no WE control for CS 80286 system Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Memory Pin Connections • Address • Data • Control • Data Inputs/Outputs (RAM) Data Outputs (ROM) - Number of lines = width of data storage, usually a byte D0-D7 (M=7) - Processor with wider data buses use multiple of such byte-wide memory devices, e.g. 64-bit ⇒ 8 x 8-bit devices - Sometimes the total memory capacity is expressed in bits, e.g. a 64K x 8-bit = 512 Kbit Brey: The Intel Microprocessors, 7e M Write Enable Only for RAM Chip Select Output Enable © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Memory Pin Connections • • Address • Data • Control Control Inputs - Chip Enable (#CE), or Chip Select (#CS), or simply Select (#S). Select the memory device for READ or WRITE operations. Could be multiple pins - In addition, Indicate whether you want to READ or Write: Æ READ: Enable device output for READ operations (only operation on ROMs) using #OE or #G. If not enabled, output will be Hi-Z (floating), OR Æ WRITE: (for RAM only) Enable device for writing using #WE input. Should not be active simultaneously with #OE - Some memory devices have one READ/WRITE control: R/#W Brey: The Intel Microprocessors, 7e M Write Enable Only for RAM Chip Select Or #CE #S Or #G Output Enable © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Memory Organization • Many memory device are 8-bits in width. • A 4K x 8 memory chip contains 4,096 (4K) memory locations, each containing 8-bits • A 16M x 4 memory chip has 16 M memory locations, each being 4-bits wide • A 512M byte DDR* memory card for your PC is organized as a 64M x 8 bytes. It contains eight 64M x 1-byte memory devices ___________________________________ * Double Data Rate, SDRAM with data transfer at both clock edges Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Read Only Memory Devices Types of read only memory: (Programming getting easier…) • ROM - Device permanently programmed in factory by manufacturer - Must be large number (≈10,000 pieces) to justify cost - Once manufactured, can not be erased or reprogrammed • PROM - Programmable ROM (Programmed once) - When number of devices required is too small to justify high factory programming cost - Programmed in a PROM programmer that burns fuse links (not in situ) - Once programmed, can not be erased for reprogramming - Changes? Throw device away and program another one! Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Read Only Memory Devices • EPROM - Erasable Programmable ROM (Programmed many) - Used when: * Contents need to be changed, e.g. during the development phase of a product - Erased and reprogrammed in an EPROM programmer (i.e. not in situ) - Erasing is by exposure to UV light for say 20 minutes Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Read Only Memory Devices, Contd. • EEPROM - Electrically Erasable Programmable ROM (Programmed many many … and in situ) - Other names: RMM (Read mostly memory), NOVRAM (Non Volatile RAM), Flash memory - Erasing and reprogramming is made so easy (and in situ) that it can be thought of as writing (hence RAM, but with data not volatile) - Erasing/writing takes longer time than writing into a RAM, but this is OK since it is done less frequent - Applications: BIOS, Memory for digital cameras and MP3 audio players, USB storage devices, etc. Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Memory Example: The 2716 EPROM • 2K x 8 read only memory Address • 1 bit + 10 bits = 11 Address inputs • 8 Data outputs Ctrl • Members of the 27XXXX family: 2704 : 512 x 8 All devices are 8-bit wide 2708 : 1K x 8 2716 : 2K x 8 2732 : 4K x 8 2764 : 8K x 8 27128 : 16K x 8 = Memory capacity 27256 : 32K x 8 in K bits 27512 : 64K x 8 271024: 128K x 8 2716 Data Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Vpp: Programming Supply Voltage 2 Control Pins #OE/P Same Effect Chip Select Program: Apply Desired Data Content DIN to Outputs = OE/P READ/Program ≈ #R/W 3-bit 8 Columns Select a Byte = OE/P 8-bit 8 Bytes Byte The 2K memory locations are organized as a matrix of 256 rows x 8 columns Brey: The 11-bit Intel address Microprocessors, 7e © 8-bit 2006 Pearson 3-bit Education, Upper Saddle River, NJ 07458. All Rights Reserved. 256 Rows Device is being read For the 8088/86: Max memory access time allowed was 420 ns So, this EPROM needs 1 wait state inserted! A0-A10 from μP A11-A19 from μP ? Æ Decode for #CS #RD from μP Note: Here #CS and PD/PGM are used interchangeably. We Prefer to have CS obtained through address decoding Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Memory Access Time = 450 ns Max RAM Memory Devices • Writing is needed more often than with EEPROMs → should be easier, faster • Two main types of RAM: - Static RAM - Dynamic RAM Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. RAM Memory Devices Static RAM • A memory device that retains data for as long as power is applied. A static RAM memory cell consists of a pair of inverters connected as a flip flop for each bit of storage Bistable Multi-vibrator 0 1 0 Momentarily to 0 to write a Has 2 stable states. Permanent 0 at output (O/P=1 or O/P =0). Momentarily to 0 to write a Permanent 1 at output It remains indefinitely in its current state Until changed by the inputs, or power is brought down Brey: The Intel Microprocessors, 7e Flip Flop keeps Input data saved after it disappears from the input © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Static RAM (SRAM) • A relatively complex cell circuit (several transistors per bit storage) • That is why static RAM devices are more expensive and are typically smaller in capacity compared to dynamic RAM (A given # of transistors available on a chip gives fewer memory locations) • Faster than dynamic RAMs, speeds down to 1 ns access time are now available • Used for high speed cache memories (small, fast) • It is rarely the case that a large computer RAM system uses only static memory type Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Static RAM Example: the 4016 • 2K x 8 RAM (same size as the 2716) Address • 11 bit address (A0-A10), 8-bit data (DQ1-DQ8): Data in/Data out • Also produced with the numbers 2016 and 4116 • #CS is #S, #OE (#RD) is #G, #WR is #W D Q (I/P) (O/P) • Range of speeds: access times in the range 120 ns to 250 ns (various chip versions, e.g. TMS4016-25 has 250 ns access time) • All can be interfaced with the 8088/8086 without Control wait states (ta< 420 ns) Brey: The Intel Microprocessors, 7e Control Data © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. • See Fig. 10-5 for notes and timing details 4016 SRAM Min Cycle time Note #G is #OE: (#RD) So, Output is disabled i.e. HiZ whenever #G is high #WR is inactive high throughout (not shown) Enable O/P READ Cycle ta(A) = Access time (from address) = 250 ns for the TMS4016-25 Generated by decoding A11-A19 & M/#IO Hi-Z Strobe data in by μP at start of T4 Stored data appears at O/P WRITE Cycle Note setup (su) and hold (h) time requirements for Address (A), data (D), and control (S) relative to #W Generated by #RD is Inactive High throughout (#RD) Disable O/P (makes O/P Hi-Z) Can be late (#WR) Strobe data in by memory at #W edge O/P goes Hi-Z to enable data in © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. decoding A11-A19 & M/#IO : Active Control Brey: The Intel Microprocessors, 7e Same pin 4016 SRAM: Data Tables 1. Electrical Characteristics DC supply voltage and currents. Range of output voltages and currents recommended to ensure specified operating characteristics Specified as: (Min or Max) 2. Minimum Timing Requirements Minimum timing requirements that must be satisfied for the device to work properly, e.g. on pulse widths, setup times, hold times. Specified as: Min 3. Timing Characteristics Several Models with different speeds Delays, etc. that actually take place in the device. Guaranteed values, e.g. Max access time. Specified as: (Max or Min) Figure 10-5 Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Dynamic RAM (DRAM) Unlike static RAM, data is store as a voltage across a capacitor (charge) Charge of course leaks with time, and data needs to be refreshed (re-written) every say 2-4 ms • Recent devices usually organized as XX K x 1 bit, largest is say 2G x 1 • Advantages: – Simpler cell circuit (1 Transistor/bit) – Hence larger capacities allowed: With Largest SRAM ≈ 8 Mbits, Largest DRAM ≈ 1024 Mbits – and lower cost than SRAM • Disadvantages: – Slower access times (e.g. 20 ns Vs 1 ns) – Needs refreshing: e.g. every 4 ms max (added complexity) But not that bad!: Occurs also during normal reads and writes. Special hidden refresh cycles occurring simultaneously with other memory accesses (cycle stealing). Dedicated DRAM refresh controller chips available. – Large storage capacity → large address inputs → large number of chip pins required → Need for chip pin multiplexing (added complexity) Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. • • DRAM Example: the 4464 • • • • 64 K x 4 DRAM D Q (I/P) (O/P) 6 bits + 10 bits = 16 bits memory address But only 8 address lines on the chip! 16 address lines split into row and column 8-bit parts: MSB 15 Row 9 8 7 3 2 1 0 Column Also a chip select #S 16-bit Address • • • • • • MS 8-bit row address is first latched in using the #RAS input (Row Address Select) Then 8-bit column address is latched in using the #CAS input This loads the 16-bit address into a latch on the chip #CAS also acts as #CS #OE is #G, #WE is #W, #CS is #CAS Access time: Fastest version is 100 ns? * and chip select * (Read) Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Timing Diagram for Address Strobing #CS Setup Times Hold Times Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Multiplexing the Row/Column Address A0-A7: 8-bit Column Address (LS) A8-A15: 8-bit Row Address (MS) 16-bit Full Address 2 x (4 x 2-to-1 MUXs) From μP S = 0 (Column)) S = 1 (Row) 74157 Data Multiplexers 8-bit Muxed Address + Row Strobe To 4464 DRAM chip Select Row Address Select Column Address Select Input MUX Delay RA Selector & Strobe 8 address Inputs to chip Carry row then Column address Row Strobe We still require A #CAS Strobe MUX O/P MUX delay > Required Hold time for row address So #RAS can be used as a selector I/P for the MUX and also as input to the DRAM to strobe Row address in, i.e. #RAS signal select the row then the Col address & its falling edge Brey: The Intel Microprocessors, 7e strobes in the row address Muxing: The opposite of Demuxing © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Internal Structure of a DRAM 8 8 2 A whole row can be refreshed at once 512 Row 512 Col 256 K x 1 bit DRAM = (256 x 256 x 4) x 1 bit (on the chip organization) 8 = • 4 sections of 256 x 256 bits each Refresh whole bits + 10 bits • Each section is addressed by 8 bits of rows and 8 bits for columns rows: Only 512 • Remaining 2 address bits select the section addressed refresh ops 18 bit address • Row and column addresses are common to all 4 sections • A whole row of 4 x 256 = 1024 bits is addressed simultaneously (Speeds up refreshing) • The 4 data bits in the addressed column in the 4 sections are addressed simultaneously • Only the bit from the required section is selected by the remaining 2 address bits using Muxed to the chip on 9 Row/Column Address Lines MUX # 3 8 Select Row Same in all 8 Select Column row enabled 4 sections Column Selectors Same column enabled in all 4 sections 4 data bits from the 4 sections Select Section 2 bits of address Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. DRAM Memory Refreshing • • • When a row is accessed in a refresh cycle, all memory cells on that row are refreshed This means that we need only 256 refresh operations to refresh all the 256K x 1 DRAM described in the previous slide To refresh the whole memory at the minimum rate of once every 4 ms, we need to do a refresh cycle every 4 ms/256 = 15.6 μs 0.8 μs 15.6 μs 15.6 μs … Only 256 Refresh operations Cover all the memory! 4 ms (Refresh whole memory chip) • If a refresh cycle needs a bus cycle (4T with the 8088/86), the % of bus cycles lost for refreshing an 8088/86 running at a clock speed of 5 MHz is: = 4 x 0.2 μs / 15.6 μs = 5.1% (not bad … for the cost saving we achieve using dynamic RAM) • For a Pentium 4 with a clock cycle of 3 GHz and a bus/instruction cycle of 1T, this % is: = 1 x 0.33 ns / 15.6 μs = 0.2% (i.e. the penalty for DRAM refreshing is much more tolerable with modern, faster processors) Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. What happens in a refresh cycle? • #RAS only refresh cycles 4 ms/256 = 15.6 μs • #RAS strobes a row address indicating the row of bits to be accessed simultaneously for refreshing • This row address is not a full memory address and can be generated by a small on-chip counter (e.g. 8-bits for the 256 rows in the 256K x 1 DRAM described) • The row cells read are fed back for re-writing into the same locations to refresh them Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Advanced DRAM Technologies • EDO (Extended Data Output) Memory - All 256 bits of the row from the selected section are saved in latches on the memory chip. So this data will be ready for future access without experiencing the slow memory access time again - Such locations are close to the already accessed data, and are likely to be accessed soon (locality principle) - Improves system performance by 15-25% SDRAM (Synchronous Dynamic RAM) Memory - Memory runs synchronously to the system bus clock, e.g. at 100-133-200 MHz Burst (block) Transfers Burst transfers of say 4 x 64-bit numbers between the processor and the memory. First number experiences normal delays, but 2nd, 3rd, and 4th transfers suffer much less delay, thus improving average access time. DDR (Double Data Rate) Memory – Data Transferred at double the SDRAM rate by using the two edges of the clock – This does not exactly double the data transfer rate due to access time limitations • • • • Combinations exist, e.g. DDR SDRAM © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Brey: The Intel Microprocessors, 7e DRAM Memory Modules • DRAMs are often mounted on memory modules interfaced to the PC SIMM: Single In-Line Memory Module: Devices and connection pins mounted on one side. Available in 2 types: – Older 30-Pin SIMMs – Newer 72-Pin SIMMs 1 2 • 4 M x 1 bit Only 11 address lines Why? • DIMM: Dual In-Line Memory Module: Devices and pins mounted on both sides. 168-Pin Used for Pentium- Pentium 4 processors with 64-bit data bus (8 Bytes of data for each memory address) Card can have one EPROM containing info on size and speed of the devices for Plugand-Play use 9 30-Pin SIMM 9 x (4 M x 1 bit) = 4M x (8 + 1 Parity) = 4MB of data 1 Byte- wide e.g. for 8088 4 M x 4 bits 4 M x 8 bits - Larger address - Wider data bus 72-Pin SIMM 168-Pin DIMM Brey: The Intel Microprocessors, 7e 8 Bytes4 Bytes- 8 x (4 M x Byte) 8 x (4 M x 4 bits wide = 4M x (4 bytes) = 32 MB of data wide © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. = 16 MB of data in DRAM , EDO and SDRAM MSB 2 bits 3 bits LSB 00 23 Locations Interfacing Memory to the Microprocessor: Address Decoding 01 23 Locations Binary addresses of 32 locations 5 bits of address: 10 23 Locations 3 bits of address on memory 2 bits of address to decode for #CS 11 23 Locations Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Interfacing Memory to the 8088/86 Microprocessor: Address Decoding • Memory devices interfaced are usually of 19 11 10 0 smaller storage capacity than the full address space of the processor A10-A0 • For example, the 2716 is 2 K x 8 memory 9 Selector bits 11 Address bits device has 11 (= 1 + 10) address inputs (A0-A10) 9 to 1 • When interfaced to a microprocessor Chip Select Decoder with 20 address lines there is a mismatch • The extra 9 address pins (A11-A19) are Memory chip decoded using a decoder such that they 111111111 FFFFFH select the memory device for a unique High Memory 511 LS (11 bits) MS (9 bits) position in the memory map of the (ROM) processor 11 10 0 510 Selector 19 • Here the μP address space is bits 2 = . 9 End 512 times 2 times the size of the memory chip . Address 00FFFH • Decoding A11-A19 and using them for 000000001xxxxxxxxxxxb 1 selecting the memory chip fixes the Low 00800H 2 = Memory position of the memory locations in the Start 00000H 0 2048 (RAM) Address μP address map 9 11 Address from μP LS (11 bits) MS (9 bits) μP Memory Map Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. WK6 Address Decoding Techniques A11 A10 1. Using a NAND Gate (CS is active low) Memory locations:FF800H-FFFFFH (2KB @ Top of the memory map) A19 A0 11111111100000000000 Start (all 0’s for address within device) 8088 Processor 2716: 2K x 8 EPROM 11111111111111111111 End (all 1’s for address within device) Common part makes the A0-A10 9 selector bits (decoder I/Ps) Address within memory device Problems with using a NAND: - Small memory devices require large NAND gates - Need one NAND gate for each memory device - Not ideal for a memory Block of several contagious memory Chips Æ Use decoders A0-A10 Device selector Address Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. • Another Example (NAND Gate): 8088 Processor - 32 K x 8 memory device: 215 locations Æ15 bit on-chip address: - “Chip Selector” address: 20 – 15 = 5 bits - If we want the memory locations to start at 10000H, What is the selector address to decode?: LSB Start Address 00010000000000000000 = 10000H - Selector 5 bits: 00010 (Remain fixed) - End address 00010111111111111111 = 17FFFH - Check: These are 7FFF+1 = 8000H = 215 locations MSB Start End 5 Select bits 00010 MSB 0 To chip Select #CS (Active low) Note: Should also include M/#IO Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. 2. Using an n-to-2n Decoder ICs (e.g. 3-to-8) • The Decoder is used for demultiplexing (expanding) (few to many) • An n-input decoder replaces 2n NAND gates • Active low outputs also suit the #CS memory inputs • Two common decoders are the 74138 and the 74139 – The ‘138 is a 3-to-8 decoder with 3 Enable inputs Æ Problem: all memory devices selected using the outputs of a given decoder must occupy contiguous locations in the memory map Æ The ‘139 is a dual 2-to-4 decoder (2 separate halves) with 1 Enable input for each half Brey: The Intel Microprocessors, 7e n LSB 1….0 1…0 1…0 138 3-to-8 2n Decoder Enables Selection Address bits #CS signals to 8 identical Memory devices occupying Contiguous address locations 2 2-to-4 139 22 2 2-to-4 22 (Advantage for the ‘139) © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. ‘138 Truth Table LSB Outputs DisabledNo selection- all outputs are Inactive high 0 1 2 Outputs EnabledSelection activated 3 4 5 6 7 Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. ‘138 Application - Block of Eight 2764 EPROM chips - Each is 64 K bit = 8 K B 3 10 = 213 x 8 - Selector address bits = 20 – 13 = 7 bits (A19-A13) LSB 13 bits To all 8 devices Analysis Vs Design Any problems from Sharing the data bus? 8 bits To all 8 devices Bottom of 0 1 Whole block: 8 x 8 KB = 64 K B (16 addr lines) 2 3 4 ? 5 6 7 • Decoder selected when G2B = 0 & G1 = 1, i.e. when A19-A16 = 1111 = FH • So, first address in whole block of 8 EPROMs = F0000H, Last is FFFFFH • Address range for chip 5: For Line 5, Inputs CBA = 101, so 7 selector bits = 1111101 • So, first address in chip 5 is 11111010000000000000 = FA000H and last address is © 11111011111111111111 = FBFFFH Brey: The Intel Microprocessors, 7e 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. ‘139 Truth Table • Two independent halves, each 2-to-4 decoder Advantage: The two memory blocks (each up to 4 chips) do not have to be adjacent in the memory map, e.g. one can be at high memory (ROM) and one at low memory (RAM)… 0 To #CS on 4 Memory Chips To #CS on 4 Memory Chips Truth Table For each half 1 Selection Enabled 2 3 Disabled Brey: The Intel Microprocessors, 7e 1 1 1 All O/P Disabled © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. 128 K x 8 EPROM= 128 KB Analysis Vs Design 1024 K bits On-Chip Address: 7+10 = 17 bit Inverter = 1 for memory accesses 1/2 00 01 10 11 17 Address bits (LS) EPROM MS 3-bit address 111 Only Read Remaining 3 Address bits G = 0 (Enabled) (MS): A19-A17 For memory accesses & A19 = 1 IO/#M G = 0 (Enabled) For memory accesses 00 01 10 11 1110→ E0000H 1111→ FFFFFH 1/2 High Memory FFFFFH Top 128 K x 8 DRAM Inverter Low 00000H Bottom Memory RAM Read Write #RD #WR A18A17 = 00 0000→ 00000H 0001→ 1FFFFH Brey: The Intel Microprocessors, 7e CE2 = 1 (Enabled) MS 3-bit address © 2006 Pearson Education, Upper NJ 07458. All Rights Reserved. For A19 = 0Saddle River, 000 3. PLD Decoders (Ultimate Flexibility) • • • Many modern systems use programmable logic decoders in place of integrated decoders They give total freedom in decoding different addresses for individual memory devices Programmable logic devices have may be called: - PLDs: Programmable logic devices - PLAs: Programmable logic array - PALs: Programmable array logic - GALs: Gate Array Logic - SPLDs: Simple programmable logic devices - CPLDs: Complex programmable logic devices They are all programmable logic devices. Nowadays they can be programmed using VHDL (Verilog Hardware Definition Language) Some types are programmed only once (fused links), similar to PROMs Some types are erasable like EPROMs The next slide shows one of the most common low cost (49¢) devices: the PAL16L8 • • • • Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. The PAL16L8 1 AA BB CC Upto 16-input Wired AND 7-input OR O/P No connection Inverter/buffer AND-OR-INVERT (Inverted sum of Products) A Inverter B -10 Fixed Inputs - 2 Fixed Outputs - 6 programmable C as inputs/outputs I/O Programmable O/Ps I/O For pin 16 to be input, set this buffer to have Hi-Z o/p I/O I/O Y 10 Inputs (1 to 10) Y = (ABC)+(ABC) Active low O/Ps Suit #CS inputs I/O Chip comes with all cross points linked. Programming removes all unwanted links, e.g. by blowing out fused links Brey: The Intel Microprocessors, 7e I/O OE O/P 10 © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. D0 - D7 128 K x 8 EPROM Using A PAL to generate the select signals for the EPROM and DRAM of the 139 decoder example. PLD Inputs: IO/#M A17 A19 PLD Outputs EPROM #CE: ROM DRAM #CE1: RAM DRAM CE2: AX19 D0-D7 #CE: Enable = low 128 K x 8 DRAM #CE1: Enable = low #RD #WR Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. CE2: Enable = high VHDL Code library ieee; Caution: Possible errors in textbook use ieee.std_logic_1164.all; entity DECODER_10_17 is port ( A19, A18, A17, MIO: in STD_LOGIC; Input declaration ROM, RAM, AX19: out STD_LOGIC; output declaration ); end; architecture V1 of DECODER_10_17 is begin Consider a NAND alternative ROM <= not A19 or not A18 or not A17 or MIO; ROM = #CE = 0 for RAM <= A18 or A17 or MIO; AX19 <= not A19; end V1; A19A18A17MIO = 1110 RAM: #CE1 = 0 for A18A17MIO = 000 CE2: AX19 = 1 for A19 = 0 Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Interfacing memory to the 8088/80188 • 8-bit μP data bus → Easily interfaced to 8-bit memory devices • Assume minimum mode: Memory sees the μP as a device having: - Address bus: A19-A0 - Data bus: D7-D0 - Control signals: IO/#M, #RD, #WR (use in generating CS and Read/Write signals to memory) • In maximum mode: the 8088 bus controller combines two control signals into one: - IO/#M with #WR ⇒ #MWTC (C= control) - IO/#M with #RD ⇒ #MRDC • Will discuss : - Interfacing EPROM - Interfacing SRAM - Interfacing EEPROM (Flash) Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. 3 x 32 KB of EPROM at top of memory map Active low. To circuit generating a wait state request for every memory access having A19A18 = 11, i.e. addresses C0000H to FFFFFH 32 K x 8 32 K x 8 32 K x 8 8-bit Data 15-bit Address Start End E8000H EFFFFH F0000H F7FFFH F8000H FFFFFH End FFFFFH FFFF0H E8000H 96 KB at upper memory A19 A18 A17 A16 A15 1 1 1 0 1 So start address is: E8000H 1 1 1 1 0 A19 A18 A17 A16 A15 1 1 1 1 1 Brey: Theaddress Intel Microprocessors, 7e So end is: FFFFFH Interfacing EPROM to the 8088 00000H JUMP to EFFF0H (cold start after RESET) (450 ns Access time - Requires a Wait state) © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Address from the processor LSB Log2 m Log2 p Log2 q block Location on device Device in block Level 1 Decoding Device level: Which location in device Log2 m Address bits Level 2 Decoding Block Level: Which device in block Memory Device Of m locations q blocks X (p devices X m locations) Level 3 Decoding Top Level: Which block in memory system Select I/Ps (Log2 p) to p Decoder Enable I/P Contiguous Block … … Block 0 (p Devices) Log2 p Address bits q such blocks (Log2 q) to q Decoder q p m = total addressing space Log2 (q p m) = size of address bus, bits = log2 q + log2 p + log2 m Memory Address Decoding Hierarchy Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. … (Log2 p) to p Decoder … … Block 1 (p Devices) 8088 address pins: A0-A14 • SRAMs are easier To interface than EPROM: Faster Æ do not require Waits • SRAMs occupy lower memory Where interrupt vectors reside. As these need to be changed by software • 4 blocks, each of (8 x 32K x8) for a total of 512 KB in lower Memory (1/2 the memory space) (only 2 blocks are shown) • Which device in a block: Selected by a 3-to-8 decoders at level 2 • Which block: selected by a 2-to-4 decoder at level 3 Level 3 Always 1 Decoder: Always Enabled! A19A18 3-to-8 Used as a 2-to-4! Each address pin connected to 16 inputsSo buffering is needed, particularly if expansion likely! Output Buffers: Address & Control Bidirectional Buffer: Data Two 3-to-8 Decoders in level 2 1 2-to-4 Decoder in level 3 A15 LSB 20-bit Address Level 1 SRAM 65256 3 bit 15 bit 2 bit Which Which On-chip Address Block? chip In block? Level 3 Level 2 Level 1 Decoding Hierarchy 8 x (32 K x 8) = 256 KB 5+10 = 15 bit On-chip address Level 2 Decoders A17A16A15: This device: 00100000…0=20000H 00100111…1=27FFFH To remaining 2 decoders for memory blocks at A19A18 = 10,11 Level 1 SRAM 65256 Hi-Z when not enabled, to allow others to control the data bus 0: Any Mem 1: Any addresses Address Standard is Buffer direction #DEN 1 = Memory Access controlled by #RD not DT/#R. DT/#R is the standard way Only 1st 2 out of 4 Block decoders shown A15 1 MB = 4 x 256 KB i.e. 4 blocks Only the lower 2 blocks (SRAMs) are shown FFFFFH 8 x (32 K x 8) 7FFFFH SRAM Block of 8 ROM 00000H A19=0 for all SRAMs Interfacing SRAM Brey: The Intel Microprocessors, 7e to the 8088 © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Interfacing EEPROM (Flash) Memories Main Flash memory applications: Used when contents need to be changed only infrequently, e.g.: • • • Storing system BIOS USB pen drives MP3 audio players Similarities with SRAMs: Both need the 3 basic memory control inputs: CE, OE, and WE Differences with SRAMs: 1. EEPROM needs additional: Æ Programming controls Æ Programming (erasing) power supply. Used to be 25 or 12 V, now 5 or even 3.3 V. 2. EEPROM is much slower to write (erase) a byte: e.g. 0.4 s Versus 10 ns for SRAM Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Interfacing EEPROM (Flash) to the 8088 Select Byte (not Word) operation Data bus for byte operation unused 28F400 Flash Memory Top of map 1 0 E 0 1/2 Address: Start: 10000000000000000000 The 3 main memory control inputs (as in SRAM): End: 11111111111111111111 - CE by decoder i.e. 80000H to FFFFFH In Byte operation, DQ15 is an input accepting A0 address bit. 00 01 512K x 8 0 (In the Byte Mode) In the word mode: 256 K x 16 18-bit address starting with A1 FFFFFH 80000H 7FFFFH - OE during memory read - WE during memory write Enable Power down mode 00000H Additional controls for Flash memory. Used for programming (erasing) Programming supply voltage Brey: The Intel Microprocessors, 7e Flash occupies the top Half of the memory map © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Interfacing 16-bit Memory to the 8086, 80286, and 80386SX • Main differences: 8086 from the 8088: - The M/#IO control signal replaces the IO/#M - The data bus is now 16 bits (word) not 8 bits (byte) - But processor should also be able to write into any byte it chooses: Remember… AX can be used as AL and AH! - A new control output, #BHE [Bus (byte) High Enable] - A0 has a special use as #BLE [Bus (byte) Low Enable] • Main differences between 8086/186 and 80286/386SX: - 80286/386SX has 24-bit address bus (A23-A0) - The M/#IO, #RD, #WR are replaced by #MRDC, #MWTC, #IORDC and #IOWTC- more specific signals Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. 16-Bit Wide Memory • 16-bit wide memory is organized in two separate 8-bit wide memory banks: - Low bank (even-numbered byte locations: 0, 2, 4, 6, …) Æ low 8 bits of the data bus (D0-D7): LS Byte - High bank (odd-numbered byte locations: 1, 3, 5, 7, …) Æ high 8 bits of the data bus (D8-D15): MS Byte • Processor must be able to access any 16 or 8 bit locations • This is achieved through bank selection (Bank Enable) signals • On the 8086, these byte selection signals are - The #BLE (A0) signal active: selects low bank - The #BHE signal active: selects high bank - Both #BLE and #BHE signals active: select both bytes (word) • Only with writes…. For Reads, the processor will take the byte it wants and no need to enforce any byte (bank) selection Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. = A0 Banks Select Bytes Select Words A19…A1 00010 00001 00000 A0 1 0 1 0 1 0 High Bank Word address: A0 is ‘Don’t care’ within a word (takes 0,1). Æ Word count starts with A1 D15-D8 Invalid word accessCrossing word boundaries (A1 changes!) D7-D0 Word’s full address is is the address of its starting byte All valid word addresses are even Enable with A0 (#BLE) Same address from μP for Word or low byte….! Æ Use #BHE to remove ambiguity Enable with #BHE High Byte Low Byte (MS Byte) (LS Byte) Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Blocks Word address: 12 10 8 6 4 same 2 0 Low Bank WK 7 Implementing Write Bank Selection Two ways to do bank selection during writes: - 1. With the Chip Select #CS (Separate Decoders for the two banks): Same write signals for both banks, but separate decoders: • More costly circuit (uses duplicate decoders) • But power saving on memory: Only required bank is enabled - 2. With the Write Control #WE: (Same decoder for the two banks) Important: Same decoder for both banks, but separate write signals: Common address to both chips • Least circuit cost (No duplicate decoders) • But a bank is enabled even if not needed (increases power consumption) Address selects a word. It start with A1 not A0! Address W Control OR Memory chip consumes less power when not selected by the #CS Decoder Brey: The Intel Microprocessors, 7e W Control Chip Select Chip Select Low HighSaddle Bank © 2006 Pearson Education, Upper River, NJ 07458. AllBank Rights Reserved. High bank data bits Low bank data bits Writes 1. Using Separate Decoders High Byte of Block: 8 x (64K x 8) 15 High Low 0 16-bit Data A16 16-bit (on-chip Address address numbering) High Bank of Block Block Note: Starting with A1 not A0 First 16 bits of the μP Address, excluding A0 0000 A0 Start Byte Address: 000000H End Byte Address: 0FFFFFH Enabled only For high bytes WR, RD signals are common to both banks (Not shown) Top 64K words Low Byte of Block: 8 x (64K x 8) Total: 2 x 8 x 64 K bytes = 1 M bytes - Same Read, Write Controls to both banks - Separate bank decoders Enabled only For low bytes Low Bank of Block Block with the 80386SX (Or A0) Modify to enable both decoders during reads Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Bank Selection with Separate Write Signals A0 may be called #BLE signal (microprocessor dependent) #RD #HRD #LRD Common- No byte selection for reads For 8086. For 80286/386SX Use #MWTC (Or #BLE) Write Enable for High bank chips Write Enable for Low bank chips • Why consider this only with write access (not Reads)? Because the processor can choose only the byte(s) it wants to read from the full 16-bit data placed on the data bus by the 2 banks. So we always enable both banks for READs Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. High bank data bits Low bank data bits Note: A1 not A0 32K x 8 32K x 8 Memory Interfacing with separate Write strobes For the two banks (80286 Processor) Decode memory as 16-bit wide memory: 2 X 32K X 8 = 64K X 8 = 64 K Bytes = 32K X 16 = 32K words This renders A0 a don’t care (the 2 bytes are taken as one entity) Æ 15 bits of device address are taken from No bank selection for READs A1-A15 Common to both banks Processor is 80286/386SX (24 bit address) Just the way Address Inputs Are numbered On the chipBut A0 is taken From processor A1 Low Bank Write Enable for high bank High Bank All Active Write Low Enable for low bank 80286 Processo Common CE for both banks Active Low (one decoder) For generating LWR and HWR Brey: The Intel Microprocessors, 7e If start byte address is 060000, last byte address is 06FFFFH SEL = A23 + A22 + A21 + A20 + A19 + #A18 + #A17 + A16 (active low) Education, Upper Saddle River, NJ 07458. All Rights Reserved. © 2006 Pearson library ieee; use ieee.std_logic_1164.all; entity DECODER_10_28 is port ( A23, A22, A21, A20, A19, A18, A17, A16, A0, BHE, MWTC: in STD_LOGIC; SEL, LWR, HWR: out STD_LOGIC ); end; architecture V1 of DECODER_10_28 is begin SEL <= A23 or A22 or A21 or A20 or A19 or (not A18) or (not A17) or A16; LWR <= A0 or MWTC; HWR <= BHE or MWTC; end V1; Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Example: SRAM & EEPROM for the 8086 128 KB (64 K words) of SRAM • Byte address Range: E0000H to FFFFF (1717 bits changed) Æ2 High Byte (D15-D8) Low Byte (D7-D0) Row of Devices Block of Devices E0003 • 4 x 32 KB devices in 2 rows Rows, Blocks = 128 K bytes Banks E0002 64 KB (32 K words) of EEPROM • Byte address Range: 00000H to 0FFFF (16 bits changed) Æ216 = 64 K bytes • 4 x 16 KB devices in 2 rows EEPROM EEPROM Note: Usually SRAM is in lower memory and EPROM in upper memory, not as shown in this example • Note several corrections for Fig. 10-29 Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. SRAM Address Ranges: 1110→ E0000H to EFFFFH 1111→ F0000H to FFFFFH 11 SRAM 64 KWord 32 K B A15 32 K B Bottom A15 32 K B 32 K B Top High High Top, Low, High Bottom Low 11 10 Low 0 1 0 0 To Wait Gen 0 0000 EEPROM 16 K B A14 Bottom A14 16 K B 16 K B 16 K B Top Inverting Buffer EEPROM Address Ranges: 00000→ 00000H to 07FFFH Brey: 00001 The Intel 7e →Microprocessors, 08000H to 0FFFFH Low No bank Selection for High Low High The EEPROMs (No Writes enabled, © 2006 Pearson used as Education, EPROM) Upper Saddle River, NJ 07458. All Rights Reserved. Example: SRAM & EEPROM for the 80386SX • 24-bit Addressing Æ 128 KB (64 K words) of SRAM: 4 x 32 KB devices (in 2 rows) • Byte address Range: 000000H to 01FFFFH (000000H to 00FFFFH) & (010000H to 01FFFF) Blocks: Bottom SRAM Row Top SRAM Row + Æ 256 KB (128 K words) of EEPROM: 4 x 64 KB devices ( in 2 rows) Byte address Range: FC0000H to FFFFFF (FC0000H to FDFFFFH) & (FE0000H to FFFFFF) Blocks: Bottom EEPROM Row Top EEPROM Row (000000H to 00FFFF) 00 = 00000000 (FC0000H to FDFFFFH) FC = 11111100 FD = 11111101 CE Input bits are the address bits that do not change over the full address range of the memory device • • Note several corrections for Fig. 10-30 Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. RB3: Bottom EEPROMs A23….A17A16 A15 …..…A1 1111110XXXXXXXXXX RB3=NOT(A23.A22.A21.A20.A19.A18.A17) 128 K Words EEPROM 32 K BK Word 64 (Top) 32 K B 64 K Word (Bottom) High Low High Low RB2: Top EEPROMs A23….A17A16 A15 …..…A1 1111111XXXXXXXXXX RB2=NOT(A23.A22.A21.A20.A19.A18.A17) EEPROM No byte selection For EEPROMs (only READs used) 3 2 SRAM 64 K Words SRAM 32 K Word (Top) 32 K Word (Bottom) RB0: Bottom SRAMs A23….A17A16 A15 …..…A1 00000000XXXXXXXXX RB0=A23+A22+A21+A20+A19+A18+A17+A16 RB1: Top SRAMs A23….A17A16 A15 …..…A1 0000001XXXXXXXXX Brey: The Intel Microprocessors, 7e RB1=A23+A22+A21+A20+A19+A18+A17+A16 High Low High Low © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. library ieee; use ieee.std_logic_1164.all; entity DECODER_10_30 is port ( A23, A22, A21, A20, A19, A18, A17, A16, A0, BHE, MWTC: in STD_LOGIC; LWR, HWR, RB0, RB1, RB2, RB3: out STD_LOGIC ); end; architecture V1 of DECODER_10_30 is begin LWR <= A0 or MWTC; HWR <= BHE or MWTC; RB0 <= A23 or A22 or A21 or A20 or A19 or A18 or A17 or A16; RB1 <= A23 or A22 or A21 or A20 or A19 or A18 or A17 or not(A16)); RB2 <= not(A23 and A22 and A21 and A20 and A19 and A18 and A17); RB3 <= not(A23 and A22 and A21 and A20 and A19 and A18 and not(A17)); end V1; Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Interfacing Memory to the 80386DX and 80486 32-bit (address) Processors Valid 2n -byte entity: • Four banks of 8-bit wide memory are required to build a functioning 32-bit Only n bits of address 00000007H wide memory system Change when moving 00000006H • 4 byte wide memory implies that μP Within the entity address bits A0 and A1 are don’t Double Word 00000005H care. The processor uses them internally to generate four separate 000000….001 00000004H #BE signals: #BE0,1,2,3 A31 A2 • The 80486 does not provide address 00000003H pins A0 and A1 on the bus • Connect processor address to A0 & A1 take all 00000002H memory address starting with A2 Possible combinations Within the double word • Use the BEi signals for byte →Don’t Care in double 00000001H word accesses selection in writes 00000000H • With the large number of address bits (32), Decoding employs PLDs 000000….000 Invalid Invalid A31 A2 rather than IC decoders or gates Word Double Word address → More decoding) Brey: (large The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. • With 32 bit addressing: 2+30 bits → 4 G Bytes can be addressed, i.e. 1 GB in each bank • Processor provides 4 bit enable signals: #BE3, #BE2, #BE1, and #BE0 to allow 8, 16, and 32 bitwide memory accesses • Use separate Write strobe signals to implement the data write operation Brey:required The Intel Microprocessors, 7e Byte Write Selection Processor O/Ps © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Example: Interfacing a block of 256 KB of SRAM to an 80486 using 32 KB devices 80486 Æ 4 data bytes Æ 4 memory banks Æ 4 devices per row 4 Banks Device How many Rows (R) In the block ?? Number of double words in block = R x 32 K Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. How to determine the number of rows of devices (R) needed? Express the required total memory size required M bytes as 2 : 8086 4 : 80486 8 : Pentium M bytes = R X (Number of banks) x Size of device in Bytes If R ≤ 1 Æ Need only one row If R > 1 Æ Need R rows Example: M = 256 KB, 80486, Using 32 KB devices R = 256 KB / (4 x 32 K) = 256 K / (128K) = 2 rows of devices Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Address Decoding Design • 256 K B of SRAM:- Top: 128KB, Bottom:128KB Enable row of devices by = 2 x (4 x 32) KB Decoding bits that do not change = 2 rows (Top: 128KB, Bottom:128KB) Over block address range • A 32 K B device uses 15 address lines on-chip: A16-A2 • Byte Address Range (Given): A31 15 bits From A17 A16 Device Address A16-A2 A1 A0 00 11 To 02000000H 0201FFFFH 02020000H 0203FFFFH Bottom Row 128 KB Top Row 128 KB 0000001000000000 0000001000000001 RB0 = A31+A30+…..+ #A25+A24+….+A17 A31 A17 Device Address A16-A2 0000001000000010 0000001000000011 A1 A0 00 11 RB1 = A31+A30+…..+ #A25+A24+….+#A17 Active low Row Enables • Note several corrections for Fig. 10-29 Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. 256 K bytes = 64 K x 4 banks 4 bytes (banks) R = 256 K/(4*32K) = 2 A16-A2 Interfacing 256 KB of SRAM to the 80486 using 32 KB devices 15 Address Lines : A16-A2 Write Bank Enable Signals No byte selection For READs RB1 32 KB Top Row Bank 3 Bank 2 Bank 1 Bank 0 Same value for both rows RB0 Y Bottom Row Two PLDs needed (large bus) Brey: The address Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Interfacing 64-bit Memory to the Pentium 2 and Pentium 4 Processors • More banks! Pentium: 64-bit wide memory is organized as an 8-bank wide system. • The Pentium provides 8 bank enable signals (#BE0 to #BE7) • Address bits A2-A0 are don’t care (ignored if present) • Pentium: 32-bit address ⇒ 4 GB Address space ⇒ /8 = ½ GB per bank • Pentium Pro to Pentium 4: 36 bit address ⇒ 64 GB ⇒ /8 = 8 GB per bank M/#IO #MWTC 8 #bank write select signals W/#R Brey: The Intel Microprocessors, 7e #BEi © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Pentium: 32-bit address ⇒ 4 GB Address space ⇒ 4/8 = 512 MB per bank Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Interfacing Memory to the Pentium • A valid entity starts at entity boundaries (does not start in another entity of the same type) • An entity is referenced by its start byte address • A byte (1) can “start” at any address • A word address (2) should start with 0 • A double word (4) should start with 00 • A quad word (8) should start with 000 Questions (for a Pentium): 0110 Valid 2n -byte entity: Only n bits of address Change when moving Within the entity Entity Boundaries 00000007H 00000006H 00000005H 00000004H 00000003H 00000002H 00000001H 00000000H • Is 56BED7A6 a valid byte, w, dw, qw? • How is ambiguity resolved? • If a word: Æ Which BEi signals are activated? Æ Which of the 8 memory banks are enabled for writes? Brey: The Intel Microprocessors, 7e Invalid Invalid Invalid QW DW W B Word D Word Q Word © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Data Bus R = 512 KB / 8 x 64 KB = 1 (only one block) Interfacing 512 KB of EPROM to a Pentium using 64KB devices 64 KB 16 on-chip address lines (A18-A3) R = 512K/(8*64KB) = 1 64KB devices: Æ satisfy Requirement with only ONE row of devices vertically No bank selection for Reads (EPROM) Data Bus Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Located at top of upper memory: Total 512 K bytes = 19 bit Last Address: FFFFFFFF 13 +16+3 First address: FFF80000 #CS = NOT(A31.A30.A29.A28.A27.A26.A25.A24.A23. Interfacing 4 MB of EPROM to the Pentium using ½ MB devices R = 4 MB / (8 x ½ MB) = 1 Require only ONE row of devices vertically ½ MB 19 on-chip Address Lines A21-A3 No bank selection for Reads (EPROM) Located at top of upper memory: Total 4 M bytes = 22 bits 10 + (19 + 3) = 32 Last Address: FFFFFFFF First address: FFC00000 #CS = NOT(A31.A30.A29.A28.A27.A26.A25.A24.A23. A22) (Start from left) Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. library ieee; use ieee.std_logic_1164.all; entity DECODER_10_36 is port ( A31, A30, A29, A28, A27, A26, A25, A24, A23, A22: in STD_LOGIC; SEL: out STD_LOGIC ); end; architecture V1 of DECODER_10_36 is begin SEL <= not(A31 and A30 and A29 and A28 and A27 and A26 and A25 and A24 and A23 and A22); end V1; Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved. Overview • Described various memory types • Described memory pin connections • Used decoders and PLDs (programmable logic devices) to decode memory addresses • Explained how to interface RAM and ROM to a microprocessor • Interfaced dynamic RAM to the microprocessor • Explained operation of dynamic RAM controller • Interfaced memory to all Intel microprocessors using 8-, 16-, 32-, and 64-bit data buses Brey: The Intel Microprocessors, 7e © 2006 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved.