PROBLEMSCircuit Basics organized. (Hint: In your search, first consider all parallel combinations, then consider series combinations, and then As a review of the basics of circuit analysis and in order consider series-parallel combinations, of which there are two for the readers to gauge their preparedness for the study of kinds.) electronic circuits, this section presents a number of relevant circuit analysis problems. For a summary of Thévenin’s and 1.5 In the analysis and test of electronic circuits, it is often Norton’s theorems, refer to Appendix D. The problems are useful to connect one resistor in parallel with another to obtain grouped in appropriate categories. a nonstandard value, one which is smaller than the smaller of the two resistors. Often, particularly during circuit testing, Resistors and Ohm’s Law one resistor is already installed, in which case the second, when connected in parallel, is said to “shunt” the first. If the 1.1 Ohm’s law relates V , I, and R for a resistor. For each of original resistor is 10 k, what is the value of the shunting the situations following, find the missing item: resistor needed to reduce the combined value by 1%, 5%, 10%, (a) R = 1 k, V = 5 V and 50%? What is the result of shunting a 10-k resistor by (b) V = 5 V, I = 1 mA 1 M? By 100 k? By 10 k? (c) R = 10 k, I = 0.1 mA (d) R = 100 , V = 1 V Voltage Dividers Note: Volts, milliamps, and kilohms constitute a consistent 1.6 Figure P1.6(a) shows a two-resistor voltage divider. set of units. Its function is to generate a voltage VO (smaller than the 1.2 Measurements taken on various resistors are shown power-supply voltage VDD ) at its output node X. The circuit below. For each, calculate the power dissipated in the resistor looking back at node X is equivalent to that shown in and the power rating necessary for safe operation using Fig. P1.6(b). Observe that this is the Thévenin equivalent of standard components with power ratings of 1/8 W, 1/4 W, the voltage-divider circuit. Find expressions for VO and RO . 1/2 W, 1 W, or 2 W: VDD (a) 1 k conducting 20 mA (b) 1 k conducting 40 mA (c) 100 k conducting 1 mA R1 (d) 10 k conducting 4 mA X RO X (e) 1 k dropping 20 V VO (f) 1 k dropping 11 V 1.3 Ohm’s law and the power law for a resistor relate V , I, R, R2 VO and P, making only two variables independent. For each pair identified below, find the other two: RO (a) R = 1 k, I = 5 mA (a) (b) (b) V = 5 V, I = 1 mA (c) V = 10 V, P = 100 mW Figure P1.6 (d) I = 0.1 mA, P = 1 mW (e) R = 1 k, P = 1 W 1.7 A two-resistor voltage divider employing a 2-k and a 3-k resistor is connected to a 5-V ground-referenced power supply to provide a 2-V voltage. Sketch the circuit. Assuming Combining Resistors exact-valued resistors, what output voltage (measured to 1.4 You are given three resistors whose values are 10 k, ground) and equivalent output resistance result? If the 20 k, and 40 k. How many different resistances can you resistors used are not ideal but have a ±5% manufactur- create using series and parallel combinations of these three? ing tolerance, what are the extreme output voltages and List them in value order, lowest first. Be thorough and resistances that can result? = Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem 46 Chapter 1 Signals and Amplifiers PROBLEMS D 1.8 You are given three resistors, each of 10 k, and a 9-V this problem. What is the value of the resistor required in battery whose negative terminal is connected to ground. With each case? What is the input resistance of the current divider a voltage divider using some or all of your resistors, how many in each case? positive-voltage sources of magnitude less than 9 V can you D 1.13 A particular electronic signal source generates cur- design? List them in order, smallest first. What is the output rents in the range 0 mA to 0.5 mA under the condition that resistance (i.e., the Thévenin resistance) of each? its load voltage not exceed 1 V. For loads causing more than CHAPTER 1 D *1.9 Two resistors, with nominal values of 4.7 k and 10 1 V to appear across the generator, the output current is no k, are used in a voltage divider with a +15-V supply to longer assured but will be reduced by some unknown amount. create a nominal +5-V output. Assuming the resistor values This circuit limitation, occurring, for example, at the peak of to be exact, what is the actual output voltage produced? Which a sine-wave signal, will lead to undesirable signal distortion resistor must be shunted (paralleled) by what third resistor that must be avoided. If a 10-k load is to be connected, what to create a voltage-divider output of 5.00 V? If an output must be done? What is the name of the circuit you must use? resistance of exactly 3.33 k is also required, what do you How many resistors are needed? What is (are) the(ir) value(s)? suggest? What is the range of current through the load? Current Dividers Thévenin Equivalent Circuits 1.10 Current dividers play an important role in circuit design. 1.14 For the circuit in Fig. P1.14, find the Thévenin equiva- Therefore it is important to develop a facility for dealing lent circuit between terminals (a) 1 and 2, (b) 2 and 3, and (c) with current dividers in circuit analysis. Figure P1.10 shows a 1 and 3. two-resistor current divider fed with an ideal current source I. Show that 1 R2 I1 = I R1 + R2 1 kΩ R1 I2 = I 1.5 V 2 R1 + R2 and find the voltage V that develops across the current divider. 1 kΩ 3 I1 I2 Figure P1.14 I R1 R2 V 1.15 Through repeated application of Thévenin’s theorem, find the Thévenin equivalent of the circuit in Fig. P1.15 Figure P1.10 between node 4 and ground, and hence find the current that flows through a load resistance of 3 k connected between D 1.11 Design a simple current divider that will reduce the node 4 and ground. current provided to a 10-k load to one-third of that available from the source. 1 20 kΩ 2 20 kΩ 3 20 kΩ 4 D 1.12 A designer searches for a simple circuit to provide one-fifth of a signal current I to a load resistance R. Suggest a solution using one resistor. What must its value be? 10 V 20 kΩ 20 kΩ 20 kΩ What is the input resistance of the resulting current divider? For a particular value R, the designer discovers that the otherwise-best-available resistor is 10% too high. Suggest two circuit topologies using one additional resistor that will solve Figure P1.15 = Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem Problems 47 Circuit Analysis CHAPTER 1 a much easier approach is possible: Find the Thévenin equivalent of the circuit to the left of node 1 and the Thévenin 1.16 For the circuit shown in Fig. P1.16, find the current in equivalent of the circuit to the right of node 2. Then solve the each of the three resistors and the voltage (with respect to resulting simplified circuit. ground) at their common node using two methods: *1.18 For the circuit in Fig. P1.18, find the equivalent (a) Loop Equations: Define branch currents I1 and I2 in R1 and resistance to ground, Req . To do this, apply a voltage Vx R2 , respectively; write two equations; and solve them. between terminal X and ground and find the current drawn PROBLEMS (b) Node Equation: Define the node voltage V at the common from Vx . Note that you can use particular special properties node; write a single equation; and solve it. of the circuit to get the result directly! Now, if R4 is raised to Which method do you prefer? Why? 1.2 k, what does Req become? 10 V X 5 V Req R2 R1 5 k 10 k R1 R3 1 kV 1 kV R5 R3 1 kV 2 k R2 R4 1 kV 1 kV Figure P1.16 Figure P1.18 1.17 The circuit shown in Fig. P1.17 represents the equiva- lent circuit of an unbalanced bridge. It is required to calculate the current in the detector branch (R5 ) and the voltage across it. 1.19 Derive an expression for vo /vs for the circuit shown in Although this can be done by using loop and node equations, Fig. P1.19. 10 V R1 R3 1 k 9.1 k 1 R5 2 Rs 2 k R2 R4 vs vp rp ro RL vo 1.2 k 11 k gmvp Figure P1.17 Figure P1.19 = Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem 48 Chapter 1 Signals and Amplifiers AC Circuits PROBLEMS sources, calculate the internal resistance, Rs ; the Norton current, is ; and the Thévenin voltage, v s : 1.20 The periodicity of recurrent waveforms, such as sine waves or square waves, can be completely specified using (a) v oc = 1 V, isc = 0.1 mA only one of three possible parameters: radian frequency, ω, (b) v oc = 0.1 V, isc = 1 μA in radians per second (rad/s); (conventional) frequency, f , 1.24 A particular signal source produces an output of 40 mV in hertz (Hz); or period T , in seconds (s). As well, each when loaded by a 100-k resistor and 10 mV when loaded CHAPTER 1 of the parameters can be specified numerically in one by a 10-k resistor. Calculate the Thévenin voltage, Norton of several ways: using letter prefixes associated with the current, and source resistance. basic units, using scientific notation, or using some com- bination of both. Thus, for example, a particular period 1.25 A temperature sensor is specified to provide 2 mV/°C. −1 5 may be specified as 100 ns, 0.1 μs, 10 μs, 10 ps, or When connected to a load resistance of 5 k, the output −7 1 × 10 s. (For the definition of the various prefixes voltage was measured to change by 10 mV, corresponding to used in electronics, see Appendix J.) For each of the a change in temperature of 10°C. What is the source resistance measures listed below, express the trio of terms in scientific of the sensor? −7 notation associated with the basic unit (e.g., 10 s rather 1.26 Refer to the Thévenin and Norton representations of the −1 than 10 μs). signal source (Fig. 1.1). If the current supplied by the source −4 (a) T = 10 ms is denoted io and the voltage appearing between the source (b) f = 1 GHz output terminals is denoted v o , sketch and clearly label v o (c) 2 ω = 6.28 × 10 rad/s versus io for 0 ≤ io ≤ is . (d) T = 10 s 1.27 The connection of a signal source to an associated (e) f = 60 Hz signal processor or amplifier generally involves some degree (f) ω = 1 krad/s of signal loss as measured at the processor or amplifier (g) f = 1900 MHz input. Considering the two signal-source representations shown in Fig. 1.1, provide two sketches showing each 1.21 Find the complex impedance, Z, of each of the signal-source representation connected to the input terminals following basic circuit elements at 60 Hz, 100 kHz, and (and corresponding input resistance) of a signal processor. 1 GHz: What signal-processor input resistance will result in 95% of (a) R = 1 k the open-circuit voltage being delivered to the processor? (b) C = 10 nF What input resistance will result in 95% of the short-circuit (c) C = 10 pF signal current entering the processor? (d) L = 10 mH (e) L = 1 μH Section 1.2: Frequency Spectrum of Signals 1.28 To familiarize yourself with typical values of angular 1.22 Find the complex impedance at 10 kHz of the following frequency ω, conventional frequency f , and period T , networks: complete the entries in the following table: (a) 1 k in series with 10 nF (b) 10 k in parallel with 0.01 μF Case ω (rad/s) f (Hz) T (s) (c) 100 k in parallel with 100 pF (d) 100 in series with 10 mH a 5 × 109 b 2 × 10 9 c 1 × 10−10 Section 1.1: Signals d 60 e 6.28 × 104 1.23 Any given signal source provides an open-circuit f 1 × 10−5 voltage, v oc , and a short-circuit current, isc . For the following = Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem *** = very challenging. (1. show its spectrum to contain adjacent components (spectral (b) Convince yourself that the maximum error in the lines) at 98 kHz and 126 kHz of amplitudes 63 mV and conversion (called the quantization error) is half the N 49 mV. a high-voltage transmission-line voltage in PROBLEMS North America 1. a somewhat common peak voltage in Section 1.9 V peak. Each of the N bits of period T that provides the same power as a sine wave of peak the digital word to be converted controls one of the switches. highest value? Its frequency? Its period? (a) Show that the least significant bit (LSB) corresponds to N 1. 28.32 Measurements taken of a square-wave signal using a a change in the analog signal of VFS /(2 − 1). and 59. what would direct resolution. D = design problem .5. each change in (c) 0. This is the frequency-selective voltmeter (called a spectrum analyzer) resolution of the converter. b3 . * = difficult problem. What is its between 0 and VFS (where the subscript FS denotes “full 5 average value? Its peak-to-peak value? Its lowest value? Its scale”). 1.33 Find the amplitude of a symmetrical square wave of digital-to-analog converter (DAC).29 For the following peak or rms values of some important amplitude V̂ and the same frequency. calculate the corresponding other value: on equality of the frequencies of the two waveforms? (a) 117 V rms. is 1. respectively. in which the most significant bit. Does this result depend sine waves.0 V? For +2. how many bits are required to obtain a amplitude to be? What is the rms value of the fundamental? resolution of 2 mV or better? What is the actual resolution What are the peak-to-peak amplitude and period of the obtained? What is the resulting quantization error? originating square wave? 1. measurement of the fundamental show its frequency and (c) For VFS = 5 V.7 V? For −2.35 Consider a 4-bit digital word b3 b2 b1 b0 in a format called signed-magnitude. (d) 220 kV rms. Sketch the waveform. a household-power voltage in North America (b) 33.2-V peak-to-peak and 2000-rad/s frequency b0 corresponds to a 0.8 V? association with Fig. (a) 10-V peak amplitude and 1-kHz frequency What is peculiar about the representation of zero? For a (b) 120-V rms and 60-Hz frequency particular analog-to-digital converter (ADC).3: Analog and Digital Signals rectifier circuits 1.31 Using the information provided by Eq. that is.37 shows the circuit of an N-bit 1.36 Consider an N-bit ADC whose analog input varies 1 sin 10. the quantization error = VFS /2(2 − 1). 000πt + · · · ). 11. For this signal.37 Figure P1. Vref 2R 4R 8R 2NR b1 b2 b3 bN 0 1 0 1 0 1 0 1 iO Figure P1.30 Give expressions for the sine-wave voltage signals interpreted as a sign bit—0 for positive and 1 for negative having: values.34 Give the binary representation of the following decimal (c) 220 V rms.37 = Multisim/PSpice. a household-power voltage in parts of Europe numbers: 0. Problems 49 CHAPTER 1 1.5 V? For −3. List the values that can be represented by this scheme. 6.2) in +2. characterize the signal repre- sented by v(t) = 1/2 + 2/π(sin 2000π t + 13 sin 6000πt + 1.5-V change in the analog input. ** = more difficult. What (d) 100-mV peak and 1-ms period is the full range of the analog signal that can be represented? What signed-magnitude digital code results for an input of 1. 0 V of either supply.40 An amplifier operating from ±3-V supplies provides 1. What overall voltage gain results as ratios and in decibels as well as the supply power. and amplifier efficiency. respectively) both as with the load connected? If the amplifier has a peak ratios and in dB: output-current limitation of 20 mA. did all the gain go? What would the gain be if the source was connected directly to the load? What is the ratio of these 1. RL = 100 output is possible? What is the corresponding output power (b) v I = 10 μV. What is the speed of this system in bits Calculate the overall voltage gain v o /v s in each case.Vref is a constant reference to pseudo-square waves.5: Circuit Models for Amplifiers (b) Which bit is the LSB? Which is the MSB? 1. v O = 10 V. find the maximum Fig.38 In compact-disc (CD) audio technology. the switch is in the position labeled 0. with ±5-V supplies? With ±10-V supplies? resistance of 1 M and an output resistance of 20 . 200-k source and a 100- = Multisim/PSpice. open-circuit Section 1. so-called clipping mode.45 A 10-mV signal source having an internal resistance a 2. and power gains (Av . 1. iI = 100 μA. RL = 10 k available? (c) v I = 1 V. R = 10 k. *** = very challenging. iI = 100 nA. amplifier brings.1 kHz. in which Av o = 100 V/V under the following value of iO obtained. ** = more difficult. Ai . and power gain expressed as in turn to a 100- load. v O = 1 V. what is the rms value of the largest sine-wave input for which an undistorted (a) v I = 100 mV. * = difficult problem. For each. For an amplifier with a small-signal voltage. what peak value of input sinusoid is needed to produce an output whose extremes (a) Show that are just at the edge of clipping? Clipped 90% of the time? Clipped 99% of the time? CHAPTER 1 Vref b1 b2 b iO = + + · · · + NN R 21 22 2 Section 1.46 A buffer amplifier with a gain of 1 V/V has an input and input needed.2-V peak input from which 1. 50 Chapter 1 Signals and Amplifiers PROBLEMS When the bit is 0.2-V peak sine wave across a 100- load when provided of 100 k is connected to an amplifier for which the input with a 0. RL = Ro signal is sampled at 44. the audio (b) Ri = Rs . its gain is 200 V/V. operating in the when the bit is 1.44 An amplifier with 40 dB of small-signal.Find and the output resistance is 1 k. What is the change in iO resulting conditions: from the LSB changing from 0 to 1? (a) Ri = 10Rs . can be used to convert sine waves The analog output is the current iO .16(b).4: Amplifiers voltage gain. RL = Ro /10 by 16 bits. drives a load of 500 . 1. an input resistance of 1 M. RL = 10 1. RL = 10Ro 1. The amplifier is connected the voltage gain. What voltage as listed below using rms values. v O = 5 V. The resistance is 10 k.41 An amplifier using balanced power supplies is known to two gains? This ratio is a useful measure of the benefit the saturate for signals extending within 1. 1. and N = 8. and power gains (expressed in dB) would you expect current. It With ±15-V supplies? is connected between a 1-V.0 mA peak is drawn. current gain. and Ap . the open-circuit voltage gain is 1000 V/V. D = design problem . iI = 1 mA.39 Various amplifier and load combinations are measured resistance of 100 . find the voltage. Each sample is represented (c) Ri = Rs /10. average current in each supply is measured to be 20 mA. gain of 1000 and clipping levels of ±10 V. the switch is in the position labeled 1. expressed per second? both directly and in decibels. What is the rms value of the largest undistorted sine-wave output available.42 Symmetrically saturating amplifiers. 1. amplifier measured from the source internal voltage to the load? Where dissipation. and an output 1.43 Consider the voltage-amplifier circuit model shown in (c) For Vref = 10 V. For linear operation. Find the load operating circuit. 100-k source and a 100- what is the smallest input resistance allowed? For the load. for B. D *1. 100 k. Find the 2 V across a 1-k load. evaluate the two possible connections between output resistance allowed? source S and load L. and (b) What is the voltage gain from source to load? Ro = 1 k (c) What is the voltage gain from the amplifier input to the (c) A low-output-resistance type with Ri = 10 k. and it is Ro to the nearest value of the form 1 × 10 . D = design problem .5 W of signal D 1. Find the (d) For the design with Ri as in (b) and Ro as in (c). (Hint: Use parallel rather than series voltage and power output realized. Compare this value with the result in Example 1.5 M. load? and Ro = 20 (d) If the output voltage across the load is twice that needed and there are signs of internal amplifier overload.e. Which v amplifier arrangement is best? required value of open-circuit voltage gain. and comment. How many amplifier stages are required? What is the achievable. Your (c) If the amplifier power supply limits the peak value of problem is to decide how the amplifiers should be connected. and a gain of a 30-mV rms signal and has a resistance of 0. o .49 A designer has available voltage amplifiers with an of the amplifier? input resistance of 10 k. Av o = 100. Av o = 10. in cascade between a 10-mV. you are able to increase Ri n an open-circuit voltage gain of 10.51 It is required to design a voltage amplifier to be voltage. as a possible design option. connections. what is the voltage gain for each both as a ratio and in decibels. * = difficult problem.3.. 10 V/V.3. The amplifiers have voltage gain. ** = more difficult. 1 k. SABL and SBAL. v i RL = ∞ D *1. (a) What is the required voltage gain from the source to the load? PROBLEMS 1. A and B. and (iii) the open-circuit voltage gain now output voltage actually obtained? required to meet the specifications. the output open-circuit voltage to 3 V. Your design should utilize the minimum number of that would produce the desired output. and design with this value of Ri .52 A voltage amplifier with an input resistance of power to a 100- load resistance. Choose an stages and should ensure that the signal level is not reduced arrangement that would cause minimum disruption to an below 10 mV at any point in the amplifier chain. What load voltage results? What are the corresponding D *1. and Ro = 10 k (a) What output voltage results? (b) A high-gain type with Ri = 10 k. and power gain. find (i) required to provide a signal of at least 3 V rms to a 200- the input resistance achievable.48 You are given two amplifiers. and power gains (in dB)? driven from a signal source having a 5-mV peak amplitude and a source resistance of 10 k to supply a peak output of 1. current. find the overall current gain output resistance as follows: for A. 10 k. respectively. Problems 51 CHAPTER 1 load. The signal source has a to the nearest value of the form 1 × 10 and to decrease m 10-k resistance and provides a 5-mV rms signal. Three 1000 V/V is connected between a 100-k source with an types of voltage-amplifier stages are available: open-circuit voltage of 10 mV and a 100- load. i. The signal source provides 20 k.50 Design an amplifier that provides 0. to connect (b) If the peak current available from the source is 0. Design a suitable amplifier using a combination of these suggest the location and value of a single resistor stages. namely. an output resistance of 100 . and (e) If. respectively.47 Consider the cascade amplifier of Example 1. overall voltage gain v o /v s obtained when the first and second stages are interchanged. (ii) the output resistance load. Av o = 1. 10 k. an output resistance of 1 k. *** = very challenging. For this situation: (a) A high-input-resistance type with Ri = 1 M. what is the largest To proceed. 100 V/V.1 μA. input resistance.) = Multisim/PSpice. When the load resistance is increased to 12 k. What are the values of the open-circuit output voltage and the output resistance of the amplifier? 1. arrange to add short-circuit output current of a transducer and to provide currents. Rin ≡ v x /ix .57 A designer is required to provide. each having a source resistance of 10 voltage. Find the input resistance is known to vary over the range of 1 k to 10 k. She has a number of transconductance amplifiers for across the load. v O = 10v 1 + 20v 2 . 52 Chapter 1 Signals and Amplifiers PROBLEMS 1. of voltage gain v o /v s . and Ro = 20 k is fed with a voltage source the range of 1 k to 10 k. corresponding to the specified change in Rs should be 10% at most. and Gm = 20 mA/V. It was found that the output voltage decreases by 5 mV when RL is decreased to 780 . What are the values of current gain io /ii . ** = more difficult.58 Figure P1. across a the specified change in RL should be limited to 10%. and of power gain expressed directly and in D 1. (Hint: Apply a test change in load current corresponding to the specified change voltage v x between the two input terminals. together with a selection of suitable Specify appropriate values for Ri and Ro of the form m resistors. The equivalent 1. the weighted sum. of input corresponding to a 10-mV transducer open-circuit output signals v 1 and v 2 . D = design problem .54 A current amplifier supplies 1 mA to a load resistance CHAPTER 1 of 1 k. 10-k load. the change current ix drawn from the source. The Rin of the resulting one-port network.55 A current amplifier for which Ri = 100 . additional resistors selected to provide the desired result. D 1. Also. (Hint: In your design. Then. the load resistance whose output is fed back to its input. Find the voltage gain realized.60 It is required to design an amplifier to sense the fiers and resistors. Also. the load resistance varies having a source resistance of 1 k and is loaded with a 1-k in the range of 1 k to 10 k. Your design should utilize the minimum number of ampli. What type of amplifier is required? Sketch which the input and output resistances are both 10 k its circuit model. the output current decreases to 0. *** = very challenging.58 shows a transconductance amplifier the range of 1 k to 10 k. Similarly. The equivalent source resistance of the transducer is specified to vary in 1. * = difficult problem. the amplifier should provide a minimum of 1 V k.56 A transconductance amplifier with Ri = 2 k. and specify the values of its parameters.) in load current corresponding to the specified change in RL = Multisim/PSpice.) a proportional current through a load resistor.58 10 k. and Ais = 100 A/A is to be connected between a 100-mV source with a resistance of 10 k and a load of 1 k. What are the values of the short-circuit output current and the output resistance of the amplifier? Rin 1. the change in load voltage corresponding to D **1.5 mA. Similarly. Sketch an appropriate amplifier topology with 1 × 10 . The change in load voltage resistance. and find the in Rs is required to be limited to 10%.59 It is required to design an amplifier to sense the decibels? open-circuit output voltage of a transducer and to provide a proportional voltage across a load resistor. Gm = source resistance of the transducer is specified to vary in 60 mA/V. Similarly. Ro = Figure P1.53 A voltage amplifier delivers 200 mV across a load resistance of 1 k. 99 V.63. *** = very challenging. * = difficult problem. the amplifier is required to provide connected in a special configuration. Let gm = 100 mA/V and R = 5 k. = vb RE + [rπ /(β + 1)] PROBLEMS D 1. What type of v 1 and v 2 .65(a) shows two transconductance amplifiers output current of 10 μA. and power gain expressed as ratios and in Rs should be 10% at most. For Ri and Ro . What type of amplifier is required? Sketch the amplifier circuit model.62 It is required to design an amplifier to sense the short-circuit output current of a transducer and to provide a 1. Also. the load resistance is an open-circuit output voltage of 10 V. Also. give the values of the voltage in load voltage corresponding to the specified change in gain.01 V and v 2 = 0. Problems 53 CHAPTER 1 should be 10% at most. (Note: This circuit is called m appropriate values in the form 1 × 10 . the change in load decibels. Figure P1. show that output current of the transducer of 10 μA. voltage corresponding to the specified change in RL is to be limited to 10%. Similarly. specify values m in the form 1 × 10 . find the value of v o . and specify values for its parameters.64 An amplifier with an input resistance of 5 k. D = design problem . specify v 1 = 1. The equivalent source resistance of the transducer is specified to vary in the ib range of 1 k to 10 k. when proportional voltage across a load resistor. the amplifier is required to provide RE ve a minimum of 1 mA current through the load. For Ri and Ro .65 Figure P1. for a nominal short-circuit 1. has a short-circuit output current of 5 mA and the range of 1 k to 10 k. and specify v 2 = 1 V. What type of amplifier is required? Sketch the circuit model of the amplifier. The change in the current supplied to the load corresponding to the specified change in Rs is to be 10% at most. the change in vb RL vc load current corresponding to the specified change in RL is to E be 10% at most. ** = more difficult.61 It is required to design an amplifier to sense the open-circuit output voltage of a transducer and to provide B C a proportional current through a load resistor.63 D 1. current gain. P1. a differential amplifier and is given the symbol shown = Multisim/PSpice. If v 1 = amplifier is required? Sketch its circuit model. Also. and specify values for its param. the amplifier vc −βRL is required to provide a minimum of 1 mA through the = vb rπ + (β + 1)RE load. Find v o in terms of a minimum voltage across the load of 1 V. Similarly. find v o for the case the values of the model parameters. Select appropriate values for Ri and Ro in the form ve RE m 1 × 10 . and eters. for a nominal transducer open-circuit output voltage of 10 mV. If the amplifier is known to vary in the range of 1 k to 10 k. Also. Also.63 For the circuit in Fig. The equivalent driven by a current source of 1 μA and a source resistance source resistance of the transducer is specified to vary in of 200 k. for a nominal transducer short-circuit 1. The change used to drive a 2-k load. the load resistance is known r ib to vary in the range of 1 k to 10 k. Similarly. and show that it is of the low-pass STC type. its g-parameter representation is described by the two equations: Rs I1 = g11 V1 + g12 I2 Vs Ri Ci Vi V2 = g21 V1 + g22 I2 Figure P1. and show that the transfer functions are of the form given at (b) the top of Table 1.66 (a) Section 1.68 shows a signal source connected to the input of an amplifier. For the voltage amplifier. Av o . P1. 54 Chapter 1 Signals and Amplifiers PROBLEMS in Fig. convenient representation is in terms of the g parameters.68 = Multisim/PSpice. 1. identify corre- known as an operational amplifier will be studied in sponding currents and voltages as well as the correspondence Chapter 2. 1. the 3-dB frequency for the case Rs = 10 k.) between the parameters of the amplifier equivalent circuit and the g parameters. Here Rs is the source resistance.2. ** = more difficult.16(a)? I1 g22 I2 V1 1 V2 g11 g12 I2 g21V1 Figure P1. Hence give the g parameter that corresponds to each of Ri . A particular type of differential amplifier to that of the voltage amplifier in Fig. Ri = 40 k.65 1. By comparing this equivalent circuit Figure P1.67 Use the voltage-divider rule to derive the transfer functions T (s) ≡ Vo (s)/Vi (s) of the circuits shown in Fig. the most Ci = 5 pF.66 Any linear two-port network including linear amplifiers Vi (s)/Vs (s).68 Figure P1. If the amplifier input port is labeled as port 1 and the output port as port 2. * = difficult problem. *** = very challenging. respectively. and Ro .16(a). 1. Figure P1. Derive an expression for 1.65(b). D = design problem .66 shows an equivalent circuit representation of these two equations. Notice that there is an additional g parameter with no correspondence in the amplifier equivalent circuit. Find can be represented by one of four possible parameter sets. and Ri and Ci are the input resistance and input capacitance.6: Frequency Response + of Amplifiers vo – 1. Which one? What does it signify? What assumption CHAPTER 1 did we make about the amplifier that resulted in the absence of this particular g parameter from the equivalent circuit in Fig. and given in Appendix C.22. of the amplifier. sketch and clearly label the magnitude fre- (i. Also. For Rs = 5 k and RL = 20 k. provide a Bode plot) for this amplifier.. and show that it is of the high-pass STC type. D = design problem .2. quency response (Bode plot) of this amplifier.71 Measurement of the frequency response of an amplifier function T (s) = Vo (s)/Vi (s). sketch and clearly label the magnitude frequency Vi Vo response (i. as well as by letting s → ∞ in your f (Hz) | T | (dB) ∠ T (◦ ) expression for T (s). P1.73 = Multisim/PSpice.. Vl /Vs ). ** = more difficult. * = difficult problem. Derive an Provide approximate plausible values for the missing table expression for the transfer function from source to load entries.73 The unity-gain voltage amplifiers in the circuit of 100 Hz. R2 = 40 k. Is this a high-pass or a low-pass network? What is its transmission at very high frequencies? [Estimate this directly. and arrange it in the appropriate yields the data in the following table: standard form from Table 1. find the smallest coupling capacitor that will result in a 3-dB frequency no greater than 1. Fig.e.69 For the circuit shown in Fig. What is the 100 40 0 PROBLEMS value of |T ( jωo )|? 1000 104 37 −45 105 20 0 C R1 Provide plausible approximate values for the missing entries.73 have infinite input resistances and zero output Vi Vo Figure P1.72 Measurement of the frequency response of an amplifier yields the data in the following table: Figure P1. find the transfer 1.e. *** = very challenging. Problems 55 CHAPTER 1 1.69.69 f (Hz) 10 102 103 104 105 106 107 | T | (dB) 0 20 37 40 37 20 0 D 1. and C = 1 μF. R2 1. P1. find f0 . Also.70 It is required to couple a voltage source Vs with a resistance Rs to a load RL via a capacitor C.] What is the corner frequency ω0 ? For 0 40 0 R1 = 10 k. 78 For the circuit shown in Fig. ** = more difficult. 10 Hz. 10 Hz.74 A manufacturing error causes an internal node of a For the situation in which the basic amplifier has an high-frequency amplifier whose Thévenin-equivalent node open-circuit voltage gain (Av o ) of 100 V/V. to ground with a small capacitor. *** = very challenging. lowering the 3-dB frequency from Ti (s) = Vi (s)/Vs (s) and the corresponding cutoff (corner) 3 MHz to 200 kHz and 20 kHz. What are RC circuit is 1.2). Furthermore. and 10 Hz. If she knows frequency. If the measured 3-dB bandwidth of the amplifier *1. between the output 2 3 4 5 6 7 10 Hz. D 1. evaluate To (s) = Vo (s)/Vi (s) and the that each amplifier stage has an input resistance of 100 k.e. * = difficult problem.76 An amplifier with an input resistance of 100 k assume that their gain is frequency independent.e. What is economically? the bandwidth between 3-dB cutoff points? C2 R1 100 nF 100 k Vs Vi R2 R3 C1 Vo 10 pF GmVi 100 k 10 k Gm 100 mA V Figure P1. Convince and an output resistance of 1 k is to be capacitor-coupled yourself that the overall gain Vo /Vi will drop by 3 dB below to a 10-k source and a 1-k load. 10 Hz. between the output of the second stage and the range over which the gain remains within 3 dB of the input of the third stage. and combine node A? At node B? What capacitor value should she them to form the overall transfer function. first to node *1. If the original cutoff frequency Av = 2 can be attributed to a small parasitic capacitor at the same f 10 1+j 5 1+ internal node (i. Put each of the transfer what output resistance must the driving stage have at functions in the standard form (see Table 1. 56 Chapter 1 Signals and Amplifiers PROBLEMS resistances and thus function as perfect buffers. estimate the 1000 value of the shunting capacitor.24). 8 of the first stage and the input of the second stage. Available capacitors −n the value at dc at the frequency for which the gain of each have values only of the form 1 × 10 F.78. 10 Hz. 10 Hz.. D = design problem . what would 10 jf you estimate it to be? Using the Bode plots for low-pass and high-pass STC D *1. 1.23 and 1. sketch a Bode plot for |Av |.. Provide a Bode magnitude plot for |T ( jω)|. she connects a capacitor of 1 nF. respectively.0 dB down. the node is connected to ground through a capacitor). What is that frequency in terms the values of the smallest capacitors needed to ensure of CR? that the corner frequency associated with each is less than 100 Hz? What actual corner frequencies result? CHAPTER 1 1. Second. between the node and ground). a capacitor (i.78 = Multisim/PSpice. While measuring the overall frequency response of the amplifier. shunting one of two nodes: Node A. first evaluate A and then to node B. P1. T (s) = Ti (s) × connect to which node to solve her design problem most To (s).77 A voltage amplifier has the transfer function is reduced from the expected 5 MHz to 100 kHz. maximum value). frequency of a three-stage amplifier to 10 kHz considers Give approximate values for the gain magnitude at f = 10 Hz.75 A designer wishing to lower the overall upper 3-dB networks (Figs. corresponding cutoff frequency. find an expression resistance is 100 k to be accidentally shunted to ground by for T (s) = Vo (s)/Vs (s). and Find the bandwidth of the amplifier (defined as the frequency Node B. Gm . x = 10%.24. Figure P1. 1. the circuit is called a compensated attenuator and is lent circuit shown in Table 1. and f3 dB = 2 MHz. Problems 57 CHAPTER 1 D **1.79 A transconductance amplifier having the equiva. and its output is connected to a Find the transmission of the compensated attenuator in terms load consisting of a resistance RL in parallel with a capacitance of R1 and R2 . and CL . P1.. What do you expect the corner frequencies of these 100 V/V. R2 C2 Vo (c) The dc gain Vo /Vs is equal to or greater than a specified value A0 .7° over the amplifier bandwidth. Ro . Ro ≤ 2πf3 dB CL − (1/RL ) which extends from 100 Hz to 1 kHz.80. two circuits to be? What is the drop in gain in decibels *1.80 Use the voltage-divider rule to find the transfer (relative to the maximum gain) at the two frequencies that function Vo (s)/Vi (s) of the circuit in Fig. Vi (b) The 3-dB frequency of the amplifier is equal to or greater than a specified value f3 dB . having a source resistance Rs .1 is fed with a voltage source Vs frequently employed in the design of oscilloscope probes.) = Multisim/PSpice. Under this condition and 1. RL = 10 k. CL . and Gm for Rs = 10 k.23 if the condition C1 R1 = C2 R2 applies. Vi ≥ [1 − (x/100)]Vs ).e. *** = very challenging. RL . and Ro to meet the following design constraints: PROBLEMS R1 C1 (a) At most.81 An amplifier with a frequency response of the type Ri ≥ − 1 Rs x shown in Fig. x% of the input signal is lost in coupling the signal source to the amplifier (i. D = design problem . It has been found A /[1 − (x/100)] that the gain falloff at the low-frequency end is determined Gm ≥ 0 by the response of a high-pass STC circuit and that at the (RL Ro ) high-frequency end it is determined by a low-pass STC Find Ri . 1. CL = 20 pF.80 Show that these constraints can be met by selecting 100 *1. Show that define the amplifier bandwidth? What are the frequencies at the transfer function can be made independent of frequency which the drop in gain is 3 dB? (Hint: Refer to Figs.21 is specified to have a phase shift of 1 magnitude no greater than 5. A0 = circuit. * = difficult problem. it is required to specify the values of the amplifier parameters Ri . ** = more difficult. For given values of Rs . where A0 is the dc gain. including in the analysis a dc source VOS in series with the op-amp positive input lead. D = design problem . frequently employed in analog signal-processing gain falls off with frequency at a rate of −20 dB/decade. In a closed-loop amplifier. IOS is the input offset current. For both the inverting and The maximum rate at which the op-amp output voltage the noninverting configurations. rise to a dc offset voltage at the output of magnitude IB R2 . This voltage can be reduced to IOS R2 by connecting The difference amplifier of Fig. It provides v O = (1 + R2 /R1 )(R4 /R3 ) IOS = |IB1 − IB2 |. part of R1 can be made variable. IB1 and IB2 . width). Op-amp slewing can result in nonlinear distortion of output signal waveforms. the op-amp gain |A| ft /f . saturation (due to the effect of VOS and IB ). that is. functions such as filters (Chapter 17) and oscillators reaching unity at a frequency ft (the unity-gain band- (Chapter 18). The slew rate. (v I2 − v I1 ). voltage that when applied between the op-amp input and fb is the 3-dB frequency of the open-loop gain. with appropriate polarity. and to investigate Section 2.1: The Ideal Op Amp important issues such as allowable signal swing and amplifier nonlinear distortion. is called the without distortion: fM = SR/2π Vo max . 2. 2. Problems identified by the Multisim/PSpice icon are intended to demonstrate the value of using SPICE simulation to verify hand analysis and design. that the op-amp rated output voltage (Vo max ) can be produced flow in the input terminals of the op amp. IB gives connect a high-resistance source to a low-resistance load. For both the inverting and the noninverting closed- loop configurations. Frequency ft is also known as the gain–bandwidth The input offset voltage. At any terminals. at which an output sinusoid with an amplitude equal to The average of the two dc currents. voltage at the output to zero.1 What is the minimum number of pins required for a and Multisim simulations for all the indicated problems so-called dual-op-amp IC package. and R1 and Connecting a large resistance in parallel with the capacitor R2 selected to provide the required gain.16 is designed with a resistance in series with the positive input terminal R4 /R3 = R2 /R1 . ** = more difficult. is the magnitude of dc product of the op amp: ft = A0 fb . is voltage at the output of VOS (1 + R2 /R1 ). resulting in v O = (R2 /R1 )(v I2 − v I1 ). fM .20(b) is a input terminal. amps? What is the number of pins required for a so-called Note that if a particular parameter value is not specified quad-op-amp package. Instructions to assist in setting up PSPice 2. 2.24(a) is a popular For most internally compensated op amps. PROBLEMS Computer Simulation Problems in the problem statement. VOS results in a dc offset can change is called the slew rate. the open-loop circuit. equal to the total dc resistance seen by the negative The instrumentation amplifier of Fig. one containing four op-amps? = Multisim/PSpice. one containing two op can be found in the corresponding files on the website.116 Chapter 2 Operational Amplifiers follower. you are to make a reasonable assumption. the 3-dB frequency is equal to The effect of VOS on performance can be evaluated by ft /(1 + R2 /R1 ). is the maximum frequency voltage at the output considerably. IB . It is usually designed with R3 = R4 . frequently employed as a buffer amplifier to input bias current. If an adjustable of an op-amp inverting integrator prevents op-amp gain is needed. usually specified in V/μs. SR. The inverting Miller integrator of Fig. *** = very challenging. Capacitively coupling an op amp reduces the dc offset The full-power bandwidth. very popular circuit. VOS . reduces the dc offset frequency f (f fb ). * = difficult problem. 00 1.005 V. defined as input is −1.3 Measurement of a circuit incorporating what is thought to be an ideal op amp shows the voltage at the op-amp output to where Ad is the differential gain (referred to simply as A be −2.3 except for a mismatch Gm between the in view of the possibility of experimental error? What do transconductances of the two channels. What closed-loop gain would you 2.6 The two wires leading from the output terminals of a transducer pick up an interference signal that is a 60-Hz.. Suggest an appropriate topology.7 Nonideal (i.99 2. 7 5.00 −0.3. The output signal of the transducer is sinusoidal of 5-mV amplitude and 1000-Hz frequency.00 1. E2. what is likely to be the actual gain of the Ad amplifier? CMRR = 20 log Acm 2. Thus Figure P2. that is.8 Assuming ideal op amps. *** = very challenging. find for having a finite gain A.00 1.2 uses an op amp that is ideal except For equal transconductances Gm and a transresistance Rm .2 the output voltage of the op amp can be expressed as v O = Ad v Id + Acm v Icm 2.0 V. what value of A results? 2. What is the op-amp gain A? and Rm = 1 × 10 .8.e.00 3 1. What is the maximum permitted percentage mismatch between the two 1 0. 2. Give expressions PROBLEMS for v cm .2 The circuit of Fig.4 for signal representation).9 A particular inverting circuit uses an ideal op amp and two 10-k resistors.00 V? = Multisim/PSpice.00 0. D = design problem . Acm .01) op amp using two transconductance amplifiers and one times the nominal value. P2. This problem explores an alter. predict values of the measurements that were accidentally omitted (the blank Gm1 = Gm − 21 Gm entries).0 V an expression for the open-loop gain A.5 Refer to Exercise 2.10 10. real) operational amplifiers respond to both the differential and common-mode components of their input signals (refer to Fig.1 5 2.99 2.00 0. what outputs result? If the 10-k resistors are said to be “1% we wish to model the internal structure of a particular resistors. Are the results consistent? If not.00 0. Gm2 = Gm + 21 Gm Experiment # v1 v2 vO Find expressions for Ad .00 Gm values if a minimum CMRR of 60 dB is required? 2 1. expect to actually measure for an input of precisely 1. what range of outputs would you transresistance amplifier.2: The Inverting Configuration 4 1. find the voltage gain v o /v i and 6 1. native internal structure for the op amp. 2-V sinusoid.00 V is applied at the input. For Gm = 40 mA/V 6 when v I = 1. The results are tabulated Consider an op amp whose internal structure is of the type below.00 1.000 V. * = difficult problem. In particular. v d . Measurements indicate v O = 4. Problems 117 CHAPTER 2 2. shown in Fig. P2.00 Section 2.00 input resistance Rin of each of the circuits in Fig. are they reasonable.10 2.10 −5. what would you expect the voltage at be zero in the text).000 V and that at the negative input to be −1. ** = more difficult.4 A set of experiments is run on an op amp that is ideal except for having a finite gain A. For in the text) and Acm is the common-mode gain (assumed to the amplifier to be ideal. expect? If a dc voltage of +1.” having values somewhere in the range (1 ± 0. they show the gain to be? Using this value. 2.01 2. The op amp’s effectiveness in rejecting the positive input to be? If the measured voltage at the positive common-mode signals is measured by its CMRR. and CMRR. and the total signal between each wire and the system ground. What is the input closed-loop gain results? resistance of your design? (a) R1 = 10 k. one 10-k resistor and another equal or larger resistor. Using series and parallel resistor combinations.5 with (b) R1 = 10 k. 2. R2 = 10 k 2. What is its average value? What is its highest value? D 2. (d) R1 = 100 k.15 An ideal op amp is connected as shown in Fig.13 Design an inverting op-amp circuit for which the gain possible? What is the largest (noninfinite) available voltage is −10 V/V and the total resistance used is 110 k. what are the values of the What is its lowest value? resistors R1 and R2 to be used to design amplifiers with the closed-loop gains listed below? In your designs.10 You are provided with an ideal op amp and three 10-k (c) −5 V/V resistors.16 For the circuit in Fig.14 Using the circuit of Fig.12 Given an ideal op amp. D = design problem .16.11 For ideal op amps operating with the following the largest possible input resistance under the constraint of feedback networks in the inverting configuration. R2 = 1 M voltage.8 2. (d) −100 V/V how many different inverting-amplifier circuit topologies are D 2. 118 Chapter 2 Operational Amplifiers PROBLEMS 20 k 20 k 20 k CHAPTER 2 (a) (b) 20 k 20 k 20 k 20 k (c) (d) Figure P2. 2. ** = more difficult. R2 = 1 k signal with levels of 0 V and −1 V is applied at the input. what having to use resistors no larger than 1 M.5 and assuming an ideal op amp. * = difficult problem. P2. R2 = 10 M Sketch and clearly label the waveform of the resulting output (e) R1 = 100 k. *** = very challenging. where (b) −2 V/V does the additional current come from? = Multisim/PSpice. use at least 2. Since the current supplied by the op amp is greater (a) −1 V/V than the current drawn from the input signal source. A symmetrical square-wave (c) R1 = 10 k. R2 = 100 k R1 = 10 k and R2 = 100 k. design an inverting amplifier with a gain of 46 dB having 2. assuming an ideal op amp. find the currents through all branches and the voltages at all nodes. gain magnitude? What is the smallest (nonzero) available gain magnitude? What are the input resistances in these two cases? D 2. If the larger resistor used is 100 k. what is the range of the output voltages that might be found? 2. and 10%.25 Figure P2.18 An ideal op amp with 5-k and 15-k resistors is used (b) A is finite. to what must the find the value of a resistor RIa such that when it is placed in smaller be adjusted? With what resistor must a 2-k resistor shunt with R1 . 1%. the input resistance is given by actual values are the range bounded by the nominal value R2 ±1%. Problems 119 10 k voltage ranges from −10 V to +10 V. What are the voltages at the ends of the 5-k 2. find the minimum value that the op-amp open-loop 2. what are the limits of the output voltage produced? If Rin = R1 + A+1 the −15-V supply can also vary by ±1%. what do you expect the closed-loop gain of your circuit Rc R2 to be (assuming the resistors have precise values)? (c) Give the value of a resistor you can place in parallel Vi (shunt) with R1 to restore the closed-loop gain to its R1 Vo nominal value.. 1 V 2 k PROBLEMS Figure P2.1%.22 is frequently used to provide an output voltage v o proportional to an input signal current ii .22 The circuit in Fig. To compensate for the gain reduction due to gain of −200 V/V and an input resistance of 1 k. ** = more difficult. connected to the input be shunted to achieve this goal? (Note that a resistor Ra is said to be shunted by resistor Rb when Rb *2. * = difficult problem. what is the range of gain values input resistance Ri ≡ v i /ii for the following cases: expected from such a circuit? (a) A is infinite.23 Show that for the inverting amplifier if the op-amp gain resistor? If these resistors are so-called 1% resistors. what is the maximum CHAPTER 2 voltage by which the “virtual ground node” departs from its 1 k ideal value? 2. (b) If the op amp is known to have an open-loop gain of 5000 V/V.25 shows an op amp that is ideal except is placed in parallel with Ra . 2.17 An inverting op-amp circuit is fabricated with the resistors R1 and R2 having x% tolerance (i.25 = Multisim/PSpice. If the nominal closed-loop Derive expressions for the transresistance Rm ≡ v o /ii and the gain is −100 V/V and x = 1. 2.24 For an inverting amplifier with nominal closed-loop gain R2 /R1 .20 (a) Design an inverting amplifier with a closed-loop G = R2 /R1 .22 ±x%). *** = very challenging.19 An inverting op-amp circuit for which the required gain gain A must have (in terms of R2 /R1 ) so that the gain error (due is −50 V/V uses an op amp whose open-loop gain is only to the finite A) is limited to 0. the gain is restored to its nominal value. the value of each resistance can deviate from the nominal value by as much as Figure P2.) for having a finite open-loop gain and is used to realize an inverting amplifier whose gain has a nominal magnitude D 2. D = design problem . P2. In each case 500 V/V.16 vi vo 2. to create a +5-V supply from a −15-V reference. whose is A. If in this application the output Figure P2.21 An op amp with an open-loop gain of 5000 V/V is used in the inverting configuration. Sketch the circuit.e. Use the closest standard 1% resistor value (see Appendix J). What is the tolerance on the realized closed-loop gain? Assume the op amp to be ideal. 31 = Multisim/PSpice. op-amp gain A gives rise to a reduction |G| in the magnitude of the closed-loop gain G with |G| and A related by R2 vX R4 |G|/|G| 1 + R2 /R1 R3 A/A A R A iI Assume that 1 + 2 A and 1.5) to obtain the amplifier open-loop CHAPTER 2 maximum value. R2 . A decreases by 10%. vI R1 A (b) If in a closed-loop amplifier with a nominal gain (i.5) to show that a reduction A in the use the voltage-divider rule applied to R4 and (R2 R3 ). Use this observation to derive an expression for the ≤10%.30 1 M. D = design problem .e. ** = more difficult. R 1 R/2 2 R/2 3 R/2 4 I R1 R R2 R R3 R R4 I1 I2 I3 I4 2 0V 1 Ideal Figure P2. * = difficult problem. Rc A−G (a) For the simple two-resistor circuit. Specify R1 .28 Consider the circuit in Fig. For the latter *2. 2.30 in a way that emphasizes the observation that R2 and R3 in effect are in parallel (because (b) Design an inverting amplifer for a nominal closed-loop the ideal op amp forces a virtual ground at the inverting input gain of −100.8 is used with three resistors of D *2. a resistor Rc is shunted across R1 . and a gain error of terminal). what input resistance = R1 1+G would result? (b) If the circuit in Fig. R2 .8 with R1 = R2 = R4 = Figure P2. and assume the op amp to be ideal.30 The inverting circuit with the T network in the feedback G − Gnominal e ≡ Gnominal is redrawn in Fig. 2. node 2. R1 0V vO R2 /R1 ) of 100. (2. R3 . R4 . 2.26 (a) Use Eq.1%? 2. Show D 2. what is the minimum nominal A required to limit the percentage change in | G | to 0.8. and node 4.27 (a) Use Eq. (2.. *** = very challenging. (a) −100 V/V (b) −10 V/V (a) Find the resistances looking into node 1. P2.29 An inverting op-amp circuit using an ideal op amp that perfect compensation is achieved when Rc is selected must be designed to have a gain of −500 V/V using resistors according to no larger than 100 k. (c) −2 V/V node 3. 2.31 The circuit in Fig. R1 .31 can be considered to be an extension of the circuit in Fig. what input resistance results? What is gain A required to realize a specified closed-loop gain the value of the smallest resistor needed? (Gnominal = −R2 /R1 ) within a specified gain error e. an input resistance of 1 k. and the minimum A required. Find values for R3 to obtain the following gains: *2. gain (v O /v I ) by first finding (v X /v I ) and (v O /v X ). P2. 120 Chapter 2 Operational Amplifiers PROBLEMS the finite A. 32 The circuit in Fig. V3 . and I4 . I2 .34 I2 IL D 2. Express v O in terms of v 1 amplifier with gain iL /iI = 11 A/A. ** = more difficult.35 to have an 10 kV VX RL input resistance of 100 k and a gain that can be varied from −1 V/V to −100 V/V using the 100-k potentiometer I3 100 V R4 .5-V battery and design so that the current drawn from the battery is 0. and 4. and V4 in terms of (IR). whose output is = Multisim/PSpice. If v 1 = 1 V and v 2 = −1 V. possible? (d) If the amplifier is fed with a current source having a D 2. Choose relatively low values of amplifier? resistors but ones for which the input current (from each (c) If RL = 1 k and the op amp operates in an ideal manner input signal source) does not exceed 50 μA for 1-V input as long as v O is in the range ±12 V.32 utilizes an ideal op amp. find iL . and v 2 . 2 vO (a) Find I1 .37 Design an op-amp circuit to provide an output (b) What are the input and the output resistance of this current v O = −[2v 1 + (v 2 /2)]. 3. op-amp circuit with inputs v 1 . what is v O ? (a) Find the required value for R.2 mA and a source resistance of 10 k. V1 . P2. D 2. P2. P2. A signal v 1 is connected to two of the inputs while a design the circuit shown in Fig. If the op amp saturates at ±10 V. v 2 . 2. (c) If RL is varied in the range 100 to 1 k.34 to implement a current signal v 2 is connected to the third.35 Design the circuit shown in Fig. * = difficult problem. For the smallest resistance in the circuit. IL . in terms of the input 10 kV RL current I. that is. P2. R iI 2. Problems 121 iL CHAPTER 2 (b) Find the currents I1 .1 mA. I3 . Assume the availability of a 1. (c) Find the voltages at nodes 1.38 Use the scheme illustrated in Fig.10 to design an current of 0.35 value that RL can have while the current source supplying it operates properly? 2. what is the corresponding change in IL and in VO ? Figure P2.1 mA 1 to a variable resistance RL .34 Assuming the op amp to be ideal.33 Use the circuit in Fig. it is required to 50 k.32 R1 vI 2 D 2. use 500 . D = design problem .36 A weighted summer circuit using an ideal op amp has three inputs using 10-k resistors and a feedback resistor of D 2. PROBLEMS 1 (b) If VO is not to be lower than −13 V. and Vx . V2 . *** = very challenging. I3 . What voltage gain results when the potentiometer is set exactly at its middle value? I1 10 kV 2 R3 VO 1V 1 R2 R4 Figure P2.32 as an inspiration to vO design a circuit that supplies a constant current IL of 3. and v 3 . what is the maximum Figure P2. find the maximum allowed value for RL . 2. what range of iI is signals. I2 . Assume that in addition to the sine-wave signal you have a dc reference voltage of 1. using if a2 is 0 then switch S2 connects the 20-k resistor to ground. Sketch the output signal waveform. *** = very challenging. and a3 take the values of 0 or 1. the 1000-Hz component in the process. while if a2 is 1 then S2 connects the 20-k resistor to the +5-V Which of these can be easily converted to have a gain of = Multisim/PSpice. Draw Configuration a circuit that finds the required difference using two op amps D 2.01 sin(2π × 1000t) volts. v 2 .44 Given an ideal op amp to implement designs for the and mainly 100-k resistors. 2. for a weighted summer that shifts the dc level of a sine-wave signal of 3 sin(ωt) V from zero to −3 V. Note that there are two possibilities.43 take the difference between two signals. what values of resistors (R1 . how this basic circuit can be used to implement the following functions: (a) v O = –(v 1 + 2v 2 + 3v 3 ) (b) v O = –(v 1 + v 2 + 2v 3 + 2v 4 ) (c) v O = –(v 1 + 5v 2 ) (d) v O = –6v 1 In each case find the input resistance seen by each of the signal sources supplying v 1 .43 shows a circuit for a digital-to-analog (b) +2 V/V converter (DAC). The circuit accepts a 4-bit input binary word (c) +21 V/V a3 a2 a1 a0 . 122 Chapter 2 Operational Amplifiers v O = −(2v 1 + 4v 2 + 8v 3 ) using small resistors but no smaller power supply.43 Figure P2. Rf 0 1 2 3 vO = − [2 a0 + 2 a1 + 2 a2 + 2 a3 ] D 2. complete with component values.5? D 2. a2 . (a) +1 V/V *2. Show.5 V available. and v 4 . except that their output voltage swing is limited to ±10 V. one of v 1 = 2 sin(2π × 60t) + 0.45 Design a circuit based on the topology of the controls the correspondingly numbered switch.41 Use two ideal op amps and resistors to implement the summing function v O = v 1 + 2v 2 – 3v 3 – 5v 4 D 2. only 10-k resistors.5 V/V. How would you realize a summing coefficient that is 0. Find the value of Rf so that v O ranges and six 100-k resistors are connected to the inverting input from 0 to −12 volts. and (d) +100 V/V it provides an analog output voltage v O proportional to the value of the digital input. * = difficult problem. The op amps available are ideal resistor as the smallest resistor in your design. Suggest at least two additional summing functions that you can realize with this circuit.39 An ideal op amp is connected in the weighted summer 16 configuration of Fig. v 3 . there is a need to Figure P2.10. D = design problem . ** = more difficult. by sketching the various CHAPTER 2 circuit configurations.42 In an instrumentation system. For instance. The feedback resistor Rf = 100 k.3: The Noninverting of v 2 = 2 sin(2π × 60t) − 0. a1 . Since it is desirable to amplify following closed-loop gains.40 Give a circuit. terminal of the op amp. Each of the bits of the input word D 2. use at least one 10-k overall gain of 100 as well. arrange to provide an R2 ) should be used? Where possible. D 2. where a0 .01 sin(2π × 1000t) volts and another Section 2. noninverting amplifier to obtain a gain of +1. where Rf is in kilohms. Show that v O is given by PROBLEMS than 1 k. P2.1 sin(2π × 1000t). For (b) Design a circuit to obtain v 1 = 10 sin(2π × 60t) − 0. D = design problem . P2. Assuming that the moving coil produces full-scale PROBLEMS deflection when the current passing through it is 100 μA. whose output is v O = v I1 + 2v I2 − 9v I3 + 4v I4 . volts The smallest resistor used should be 10 k. and 2. *** = very challenging.47 is given by R3 vO Rf Rf Rf vI R4 vO = v N1 + v N2 + · · · + v Nn RN1 R RNn N2 Rf RP RP R + 1+ v P1 + v P2 + · · · + P v Pn RN RP1 RP2 RPn Figure P2. = Multisim/PSpice.1 sin(2π × 1000t). volts v O = –4v N1 + v P1 + 3v P2 v 2 = 10 sin(2π × 60t) + 0. Assume an ideal op amp.0 V/V simply by short-circuiting a CHAPTER 2 single resistor in each case? D 2. Does the meter resistance shown affect the voltmeter calibration? RP0 Figure P2. of the circuit in Fig. Figure P2. v O /v I .50. * = difficult problem. use superposition to find RP = RP1 RP2 · · · RPn RP0 v O in terms of the input voltages v 1 and v 2 . P2.49 where RN = RN1 RN2 · · · RNn . P2.49. (Hint: Use a structure similar to that shown in general form in Fig.47 (a) Use superposition to show that the output of the circuit in Fig.0 V/V or +2. find v O .) V 2. ** = more difficult.49 Derive an expression for the voltage gain.46 Figure P2.47.46 R2 R1 D *2.46 shows a circuit for an analog voltmeter of very high input resistance that uses an inexpensive moving-coil meter. Problems 123 either +1.48 Design a circuit.47 D *2. using one ideal op amp. The voltmeter measures the voltage V applied between the op amp’s positive-input terminal and ground. find the value of R such that a full-scale reading is obtained when V is +10 V.50 For the circuit in Fig. 51 2.01. Find the required F for x = 0.56 A noninverting op-amp circuit with nominal gain of 10 V/V uses an op amp with open-loop gain of 100 V/V and a lowest-value resistor of 10 k. Utilize configuration to realize a gain of +10 V/V. In each case find the percentage error in gain magnitude from the nominal value of unity. the actual closed-loop gain G that is achieved. P2. 10R 2. Figure P2. 103 . and the compensated one)? Figure P2.54 Derive an expression for the gain of the voltage follower of Fig.55 Complete the following table for feedback amplifiers created using one ideal op amp. What should the resistor f +11 V/V 100 k value be? g −0. 102 .58 For each of the following combinations of op-amp appear across the load if: open-loop gain A and nominal closed-loop gain G0 . 2.52 Given the availability of resistors of value 1 k op amp must exceed G0 by at least a factor F = (100/x) − 1 and 10 k only. then the open-loop gain of the D 2. * = difficult problem. 0. Derive b −1 V/V 100 k an expression for the gain as a function of the potentiometer c −2 V/V 200 k setting x.51 utilizes a 10-k a −10 V/V 10 k potentiometer to realize an adjustable-gain amplifier. = Multisim/PSpice. an op amp of gain 200 V/V were used. What closed-loop gain actually results? With what value resistor can which resistor be shunted to achieve the nominal gain? If in the manufacturing process. what closed-loop gain would result in each case (the uncompensated one. Calculate the value of the closed-loop gain for CHAPTER 2 A = 1000. Assume the op amp to be ideal. (2. Find the voltage that will 2.50 Case Gain Rin R1 R2 D 2.51 The circuit shown in Fig. 124 Chapter 2 Operational Amplifiers PROBLEMS In each case find the load current and the current supplied 10R by the source. What is the input these results to find for each value of x the minimum required resistance of your amplifier? open-loop gain to obtain closed-loop gains of 1. resistance of 1 M to a 1-k load. *** = very challenging.53 It is required to connect a 10-V source with a source and 104 V/V. design a circuit based on the noninverting 100/x. and 10. Note that Rin signifies input resistance and R1 and R2 are feedback-network resistors as labeled in the inverting and noninverting configurations. Where does the load current come from in case (b)? 2. magnitude |G0 |. calculate (b) A unity-gain op-amp buffer is inserted between the source the percentage by which |G| falls short of the nominal gain and the load.14. D = design problem . 1.11) to show that if the reduction in the closed-loop gain G from the nominal value G0 = 1 + R2 /R1 is to be kept less than x% of G0 . 10. ** = more difficult. 100. assuming the op amp to be ideal except for having a finite gain A.1.5 V/V 20 k D 2. and 10. Also.57 Use Eq. What is the range d +1 V/V ∞ of gains obtained? Show how to add a fixed resistor so that e +2 V/V 100 k the gain range can be 1 to 11 V/V. calculate (a) The source is connected directly to the load. 2. 25 Figure P2. (2. What is the differential input resistance Rid ? If the case. * = difficult problem. For R2 /R1 = R4 /R3 .59 shows a circuit that provides an output voltage v O whose value can be varied by turning the wiper of the 100-k potentiometer. What is the input resistance seen by v 1 f −10 1000 alone? By v 2 alone? By a source connected between the two PROBLEMS g +1 2 input terminals? By a source connected to both input terminals simultaneously? 2.61 Using the difference amplifier configuration of approximately by Fig. let all the resistors be 10 k ± x%. e = 0. Neglect the effect of resistor tolerances on Ad . ** = more difficult.60 Find the voltage gain v O /v Id for the difference amplifier worst-case common-mode gain that results. *** = very challenging.16.16 and assuming an ideal op amp. show that if gain Acm to be? Also. say. find the change in v O corresponding to each turn of the pot. 2.16. 2.62.15) Figure P2. design the circuit to provide the following differential gains. 2. Evaluate this for of Fig. express v O as a e −10 100 function of v 1 and v 2 . D = design problem .59 in order for the amplifier to function as an ideal difference amplifier? Section 2. 4e = Multisim/PSpice. what do you expect the common-mode 2. Problems 125 CHAPTER 2 Case G0 (V/V) A (V/V) (a) 1 V/V (b) 5 V/V a −1 10 (c) 100 V/V b +1 10 (d) 0. Find an expression for the 2. 2. for. P2. Also.5 V/V c −1 100 d +10 10 2. evaluate the resulting CMRR in each 100 k.4: Difference Amplifiers *2. 5% resistor. 2. What condition must apply in addition to the condition in Eq.59 Figure P2.05) then the worst-case CMRR is given D 2. 2.1.62 For the circuit shown in Fig. 1.63 Consider the difference amplifier of Fig.64 Consider the circuit of Fig.62. Find the range over which v O can be varied.16 for the case R1 = R3 = 5 k and R2 = R4 = x = 0. and let each of the v I1 and v I2 signal sources have a series resistance Rs . and 5. the K +1 CMRR 20 log differential input resistance should be 20 k..e.66 For the difference amplifier of Fig. show that 25 the input common-mode resistance is (R3 + R4 ) (R1 + R2 ).62 2. two key resistance ratios (R2 /R1 ) and (R4 /R3 ) are different from each other by 1%.16 with the two input terminals connected together to an input common-mode signal source. P2. Neglect the each resistor has a tolerance of ±100 e% (i. find the CMRR in this case. a effect of the ratio mismatch on the value of Ad .65 For the difference amplifier shown in Fig. If the potentiometer is a “20-turn” device. In each case. 2. What will now be the values of Ad .69 To obtain a high-gain. resistance of 2 k. that is. 126 Chapter 2 Operational Amplifiers where K is the nominal (ideal) value of the ratios (R2 /R1 ) β R6 |(R5 + R6 ). * = difficult problem. R R v1 *2. Show that the differential gain is given by PROBLEMS and (R4 /R3 ). and another 10-k resistor between node B and ground. What resistor tolerance is needed if a CMRR of 80 dB is required? (Hint: Use superposition. the op amp to be ideal. Figure P2.68 (a) Find Ad and Acm for the difference amplifier circuit shown in Fig. R5 . P2. Select values for R. (b) If the op amp is specified to operate properly as long vId vO as the common-mode voltage at its positive and negative inputs falls in the range ±2.5 V. better than x%). Show that the differential A vO voltage gain is given by vI2 B 100 k vO R R = −2 2 1 + 2 100 k v Id R1 RG (Hint: The virtual short circuit at the op-amp input causes the current through the R1 resistors to be v Id /2R1 ). D = design problem .g.67 Design the difference amplifier circuit of Fig. a voltage divider (R5 .16 Design the circuit to obtain a differential gain of 10 V/V and to realize a differential gain of 1000. Acm .. Assume that R5 and R6 are much smaller than R so that the current through R is much lower than the current in the voltage divider. such that (R5 + R6 ) ≤ R/100. Specify both the resistor values and their required tolerance (e.70 Figure P2. *** = very challenging.69 100 k *2.68. a differential input differential input resistance of 2 M. what is the corresponding R5 limitation on the range of the input common-mode signal v Icm ? (This is known as the common-mode range of the differential v2 bvO amplifier.) R R R6 (c) The circuit is modified by connecting a 10-k resistor between node A and ground. the circuit in Fig.) CHAPTER 2 D *2.68 D *2. Specifically.70 shows a modified version of the differ- ence amplifier. high-input-resistance differ- ence amplifier. back to the positive-input terminal of the op amp through a resistor R. in addition to the negative feedback provided by the resistor R connected from the output to the negative input of the op amp. assuming that the op amp is ideal and that 1% v Id 1−β resistors are used. ** = more difficult. a voltage βv O . P2. Calculate the value of worst-case CMRR for an amplifier designed to have a differential gain of ideally vO 1 Ad ≡ = 100 V/V. R6 ) connected vId across the output feeds a fraction β of the output. and the input common-mode range? Figure P2.69 employs positive feedback.70 = Multisim/PSpice. with the result that Figure P2. 100 k vI1 which can be used to vary the gain. Assume and R6 . and a minimum CMRR of 88 dB. The modified circuit includes a resistor RG . laser-trimmed.77 is intended to 25 k 25 k A C supply a voltage to floating loads (those for which both terminals are ungrounded) while making greatest possible use of the available power supply.20(b) with a common-mode input voltage of +3 V (dc) and a differential input signal of 100-mV peak sine wave. D = design problem . 2. difference amplifier of unity gain. and comment on the difference between the two circuits. R2 = 50 k. Let 2R1 = 2 k. find a convenient node to evaluate Acm of the second stage. (b) Show how the circuit can be used to implement *2. taking into account such considerations Fig.71 The circuit shown in Fig. common-mode components. the first stage of this instrumentation amplifier and hence the B.14. When more than one circuit implementation is possible. O 20 k B D 25 k 25 k Figure P2.71 is a representation of a versatile. and CMRR (iii) +2 V/V result? Reevaluate the worst-case values for these for the (iv) +1/2 V/V situation in which all resistors are specified as ±1% units. commercially available IC. 2.76 Design the instrumentation-amplifier circuit of ative merits of each. Figure P2. 2. It consists of an op amp and precision. ** = more difficult. P2. the INA105. If the op amps are ideal except that their outputs saturate at ±12 V. 1. * = difficult problem.20(b) to realize a differential gain.” picking up interference and noise of the first stage on CMRR? (Hint: Eq. utilizing a 100-k pot as variable resistor.72 Consider the instrumentation amplifier of Fig. variable in the range as dependence on component matching and input resistance.20(b). common-mode gain. comment on the rel. CMRR. Problems 127 2. For ideal components. (2. D.73 (a) Consider the instrumentation amplifier circuit of Fig.77 = Multisim/PSpice. R3 = R4 = 10 k. manu.77 The circuit shown in Fig. for such a terminal to 1 k. 2. 2.) connect such a terminal in a redundant way. a designer proposes to make R2 = R3 = (i) −1 V/V R4 = 100 k. PROBLEMS (b) Repeat for the circuit in Fig. C. 2. 2. What do you conclude about the effect of the gain may act as an “antenna.75 For an instrumentation amplifier of the type shown single-ended amplifiers with gains: in Fig.74 (a) Expressing v I1 and v I2 in terms of differential and CHAPTER 2 D *2. (b) Repeat (a) for the circuit in Fig. 2 to 100.20(b). 2.20(b). and 2R1 = 10 k. (ii) +1 V/V what difference-mode gain. metal-film resistors.71 2. *** = very challenging. The circuit can be configured for a variety Now find the differential gain and the common-mode gain of of applications by the appropriate connection of terminals A. Find the voltage 30 k at every node in the circuit. find v O1 and v O2 in the circuit factured by Burr-Brown and known as a differential amplifier in Fig. v O2 − v O1 and their common-mode component 21 (v O1 + v O2 ). P2. Repeat the latter analysis for the case in which 2R1 is reduced Avoid leaving a terminal open-circuited.20(a) and hence find their differential component module. find the maximum allowed input common-mode signal for the case R1 = 1 k and R2 = 100 k.20(a).19) can be used to through capacitive coupling. *2. Rather. D 2. and comment on the (a) Show how the circuit can be used to implement a difference between the two circuits. and O. in the manner shown in Fig. both its peak-to-peak and rms values. a 2-V. D 2. Comment on the differences between the two circuits. change. (a) At what frequency (in Hz) are the input and output signals D 2. wave 2 sin 10 t is applied to the input. at which moment v O = −10 V.14). D = design problem . At what frequency load impedance ZL with a current proportional to v I and is its gain reduced to −1 V/V? What is the integrator time independent of the value of ZL . how does the phase of the output sine components are needed? For long-term stability. a with output initially at 0 V. 100-μs pulse is applied to resistor R of 10 k.83 Design a Miller integrator whose input resistance equal in amplitude? is 10 k and unity-gain frequency is 100 kHz. A sine-wave the input. Section 2. Also sketch v O . and a capacitor C of 1 nF. by what factor does the output voltage at A.78 are intended to function 2.78 = Multisim/PSpice. ** = more difficult. and find for each circuit iO as a function of v I . what is the largest CHAPTER 2 and an input resistance of 100 k. 2. * = difficult problem.79 A Miller integrator incorporates an ideal op amp. they supply the 10 kHz to have a voltage gain of −100 V/V.5: Integrators and Differentiators Sketch the output you would expect for the situation in which.80 Design a Miller integrator with a time constant of 1 s the manner shown in Fig. A dc voltage of −1 volt is sine-wave output that can be accommodated? Specify applied at the input at time 0. P2. What (b) At that frequency. that is. sketch the voltage waveforms at (c) If the frequency is lowered by a factor of 10 from that nodes B and C for a 1-V peak-to-peak sine wave applied found in (a).81 An op-amp-based inverting integrator is measured at as voltage-to-current converters. 128 Chapter 2 Operational Amplifiers PROBLEMS (a) Assuming ideal op amps.82 Design a Miller integrator that has a unity-gain frequency of 10 krad/s and an input resistance of 100 k. Characterize the output that results when a sine 4 signal is applied to its input. 1. How long does it take the output to reach 0 V? +10 V? *2. Show that this is indeed the constant? case.78 The two circuits in Fig. and in what direction (smaller or larger)? (b) What is the voltage gain v O /v I ? (d) What is the phase relation between the input and output (c) Assuming that the op amps operate from ±15-V power in situation (c)? supplies and that their output saturates at ±14 V (in D 2. *** = very challenging. a feedback wave relate to that of the input? resistor is introduced across the capacitor to limit the dc gain R1 R1 ZL vI iO R vI R R1 R1 iO ZL (a) (b) Figure P2. v O = 0. when fed with a string resistor.89.85).86 shows a circuit that performs a low-pass STC function. a dc gain of 40 dB. D = design problem . ** = more difficult. and a 3-dB frequency of 1 kHz. Indicate what happens if the input levels are ±2 V.84 be at t = T ? Assume that at t = 0. P2.87 Show that a Miller integrator implemented with an op amp with open-loop gain A0 has a low-pass STC transfer function.88 A differentiator utilizes an ideal op amp. Sketch and label the output waveform that results.85 Consider a Miller integrator having a time constant of 2. 2.89 = Multisim/PSpice. Problems 129 CHAPTER 2 to 40 dB. Design the circuit to obtain an input resistance of no dc stabilization (but with the output initially at 0 V) and 10 k.2 D 2. How many pulses are required for an output voltage sine-wave input with frequency equal to 10f0 ? change of 1 V? 2.85 0. Figure P2. 1-V positive-input pulse (initially at 0 V) with (a) ω0 = 1/CR2 . with the time constant the same (1 ms) and with the time constant raised to 2 ms.86 Figure P2. What is the frequency f0 (in Hz) of pulses of 10-μs duration and 1-V amplitude rising from at which its input and output sine-wave signals have equal 0 V (see Fig. sketch and label its waveform. What is the pole frequency of the STC function? How does this compare with the pole frequency of the ideal integrator? If an ideal Miller integrator is fed with a −1-V pulse signal with a width T = CR. Repeat for an integrator with an op amp having A0 = 1000. *** = very challenging. At (b) the feedback resistor connected.84 A Miller integrator whose input and output voltages are initially zero and whose time constant is 1 ms is driven by PROBLEMS the signal shown in Fig. a 10-k 1 ms and an output that is initially zero. and a 1-nF capacitor. Figure P2. Derive the transfer function and 3-dB frequency? Sketch and label the output that results with show that the dc gain is (−R2 /R1 ) and the 3-dB frequency a 10-μs.89 An op-amp differentiator with 1-ms time constant is driven by the rate-controlled step shown in Fig. Sketch and label the output waveform magnitude? What is the output signal for a 1-V peak-to-peak resulting.86 *2.84. * = difficult problem. what frequency does the magnitude of the transfer function reduce to unity? *2. what will the output voltage Figure P2. Such a circuit is known as a first-order. Vo Figure P2. P2. What is its value? What is the associated lower low-pass active filter. Assuming v O to be zero initially. P2. 93 Derive the transfer function of the circuit in 2.01 sin ωt. single-time-constant function. 2. and an input resistance (at ω ω1 ) of 2 k.92 shows a circuit that performs the high-pass. Assuming that the circuit is the maximum amplitude of the sine wave that can be applied is designed such that ω2 ω1 .93 transfer function and show that the high-frequency gain is (−R2 /R1 ) and the 3-dB frequency ω0 = 1/CR1 . volts.93 (for an ideal op amp) and show that it can be written amp having an input offset voltage of ±2 mV. ** = more difficult. D = design problem . P2.” a low-frequency 3-dB point at 200 Hz.94 An op amp wired in the inverting configuration with the input grounded.1 μF. D **2. has R = 20 k and C = 0.95 A noninverting amplifier with a gain of 100 uses an op Fig.6: DC Imperfections 2. Observe that the circuit performs as At what frequency does the magnitude of the transfer function an amplifier whose gain rolls off at the low-frequency reduce to unity? end in the manner of a high-pass STC network. Design the circuit to provide a gain of 40 dB in the “middle-frequency range. a Use these approximations to sketch a Bode plot for the high-frequency gain of 40 dB. find the input offset voltage. Figure P2. and at the high-frequency end in the manner of a low-pass STC network. When a regions: triangle wave of ±1-V peak amplitude at 1 kHz is applied to (a) ω ω1 the input. what form of output results? What is its frequency? (b) ω1 ω ω2 What is its peak amplitude? What is its average value? What (c) ω ω2 value of R is needed to cause the output to have a 12-V peak amplitude? CHAPTER 2 2. What are the gains and phase shifts found for this circuit at one-tenth and 10 times the unity-gain frequency? A series input resistor is added to limit the gain magnitude at high frequencies to 100 V/V. Find the output in the form when the input is 0.92 has an output dc voltage of −0. and a 3-dB frequency of 2 kHz. *** = very challenging. Derive the Figure P2.90 An op-amp differentiator. Vo −R2 /R1 2. Vo Section 2.2 V. find approximate expressions at the input without the output clipping? If the amplifier is = Multisim/PSpice. What where ω1 = 1/C1 R1 and ω2 = 1/C2 R2 .27(a). employing the circuit shown for the transfer function in the following frequency in Fig. 130 Chapter 2 Operational Amplifiers PROBLEMS 2.96 A noninverting amplifier with a closed-loop gain of = Vi [1 + (ω1 /jω)][1 + j(ω/ω2 )] 1000 is designed using an op amp having an input offset voltage of 3 mV and output saturation levels of ±12 V. having R2 = 100 k and R1 = 2 k.91 Use an ideal op amp to design a differentiation circuit −3 for which the time constant is 10 s using a 10-nF capacitor. * = difficult problem.92 Figure P2. magnitude response. Design the circuit to obtain a high-frequency input resistance of 1 k. Such a circuit is known as a first-order high-pass active filter. If the input bias current is known to be very small. What is the associated 3-dB frequency? What gain and phase shift result at 10 times the unity-gain frequency? Vo D 2. a high-frequency 3-dB point at 200 kHz. In order results with the input grounded? to compensate for the bias current in this case. what does the output offset become? 2.6 V.105 An op amp intended for operation with a closed-loop VOS = 5 mV. 2.3 V when measured with the input open and +5 V with the input grounded.98 A particular inverting amplifier with nominal gain of −100 V/V uses an imperfect op amp in conjunction with 100-k and 10-M resistors.30 V. what values of C1 and offset voltage (due to offset current alone)? C2 are needed? (d) With bias-current compensation as in (c) in place. what is the resulting output 100 Hz. What is its output offset voltage? is found to be +0. Problems 131 CHAPTER 2 capacitively coupled in the manner indicated in Fig.102 uses an op amp of R3 be? With input grounded. For an amplifier offset voltage of 0 mV.28.97 An op amp connected in a closed-loop inverting configuration having a gain of 1000 V/V and using relatively small-valued resistors is measured with input grounded to have a dc output voltage of −1.103 Using offset-nulling facilities provided for the op amp. and that due to C2 at 10 Hz. what resistor (b) If the input offset voltage is ±2 mV and the input bias would you use? And where? current as in (a).2 μA. the output offset voltage having a ±3-mV offset. IB = 1 μA. find the worst-case gain of –100 V/V uses resistors of 10 k and 1 M with a (largest) dc offset voltage at the output. D = design problem . R2 .99 A noninverting amplifier with a gain of +10 V/V said separately about the polarity of the output offset at either using 100 k as the feedback resistor operates from a 5-k 0 or 75°C.16.8 V. and IOS = 0. a large capacitor is placed what would the maximum possible amplitude be? in series with a 1-k resistor. terminal and ground.104 An op amp is connected in a closed loop with gain of additional resistor to compensate for the bias currents. instead. offset-voltage drift is specified to be 20 μV/°C. to produce zero output with the input grounded. the required resistor? If the offset current is no more than and R3 should be used? For a break frequency due to C1 at one-tenth the bias current. What +100 utilizing a feedback resistor of 1 M. If the input offset voltage = Multisim/PSpice. 2. If the op amp has *2.101 Consider the difference amplifier circuit in Fig. Estimate the input offset current What does the output offset become with the input ac coupled assuming zero input offset voltage. a closed-loop amplifier with gain of +1000 is adjusted at 25°C nected).36 is used to create an can be observed with the input grounded? ac-coupled noninverting amplifier with a gain of 100 V/V (c) If bias-current compensation is used. effect of offset voltage and offset current? Let R1 = R3 = 10 k and R2 = R4 = 1 M. What values of R1 . P2. With the input left floating (discon. the output dc voltage is measured to be −0. 2. * = difficult problem. 2. what would you expect their relative polarities to source. bias-current-compensation resistor R3 . What is its input offset voltage? Prepare an offset-voltage-source sketch resembling PROBLEMS that in Fig. What should the value *2. what is the value of using resistors no larger than 100 k. (c) A 10-M resistor is connected between the positive-input 2.102 direction does it flow? (b) Estimate the value of the input offset voltage. Be careful of polarities. through a capacitor C? If. what output voltage wishes to use this amplifier with a 15-k source. what is the largest dc voltage at the output due to the combined *2. ** = more difficult. what range of outputs would you expect? Indicate where you would add an 2. 2.100 The circuit of Fig. If the input Estimate the input offset current. The output voltage is found to be +5. what output would you expect at 0°C and at 100°C? While nothing can be D *2.36. *** = very challenging. does the range of possible outputs then become? A designer (a) If the input bias current is 200 nA. what is the largest possible output that D 2.102 The circuit shown in Fig. (a) What is the bias current of this amplifier? In what Figure P2. but with a bias be? current of 2 μA and an offset current of 0.2 μA. 113 Find the ft required for internally compensated op dc output voltage of the integrator when the input is amps to be used in the implementation of closed-loop grounded.106 A Miller integrator with R = 10 k and C = 10 nF closed-loop amplifier? What is its gain at 0. Fill in the blank entries. What is the 3-dB 2. D *2. find the worst-case 2. this shows it is 40 dB.117 This problem illustrates the use of cascaded (c) 1800 V/V and 0. 1 MHz A0 fb (Hz) ft (Hz) (g) −1 V/V.108 A measurement of the open-loop gain of an internally frequency of the follower? At what frequency is the gain of compensated op amp at very low frequencies shows it to be the follower 1% below its low-frequency magnitude? If the 98 dB. *** = very challenging. Specifically. and ft . time of the output voltage. characterized by a resistor is connected across the capacitor. * = difficult problem. op amp intended for high-frequency operation indicate that the note that the 10%–90% rise time of a low-pass STC circuit gain is 4 × 103 at 100 kHz and 20 × 103 at 10 kHz. amplifiers with the following nominal dc gains and 3-dB bandwidths: Section 2. a 1-M 2. What 10−1 106 is the highest gain available under these conditions? 2 × 105 10 2.115 Consider a unity-gain follower utilizing an internally compensated op amp with ft = 2 MHz. gain–bandwidth product of 20 MHz. it is required that the output be within 1% of its at which the gain has dropped by 20 dB.1 MHz closed-loop amplifiers to obtain an overall bandwidth greater (d) 100 V/V and 0.111 An inverting amplifier with nominal gain of −50 V/V PROBLEMS can be as large as 1 mV of unknown polarity. What must the ft of the op the 3 dB and unity-gain frequencies? amp be? (Note: The step response of STC low-pass networks is discussed in Appendix E. (d) −2 V/V.107 The data in the following table apply to internally (c) +2 V/V. what range of offset current is possible? employs an op amp having a dc gain of 104 and a unity-gain frequency of 106 Hz. (Note: The step response of STC 2. 100 kHz and Bandwidth on Circuit Performance (b) +50 V/V.) its 3-dB frequency. For each. What is the 3-dB frequency f3dB of the 2. = Multisim/PSpice. a resistor is connected At what frequency does the closed-loop amplifier exhibit a in series with the positive-input terminal of the op amp.112 A particular op amp. at 100 kHz. what are final value of 1 V in at most 200 ns. and its dc gain. Estimate with a time constant τ is 2.1 GHz than can be achieved using a single-stage amplifier with the (e) 25 V/mV and 250 kHz same overall gain. For a particular 103 108 system application. 10 kHz (f) +1 V/V.110 Measurements made on the internally compensated with a dc gain of 10.109 Measurements of the open-loop gain of a compensated low-pass networks is discussed in Appendix E. 100 kHz 2. and IOS = 20 nA.) (a) 2 × 105 V/V and 5 × 102 Hz (b) 20 × 105 V/V and 10 Hz D *2. a bandwidth of 32 kHz is required.7: Effect of Finite Open-Loop Gain (a) −50 V/V. What 3-dB bandwidth results? (a) To compensate for the effect of IB .1 μA. its unity-gain frequency. fb .2τ . D = design problem .114 A noninverting op-amp circuit with a gain of 96 V/V 106 106 is found to have a 3-dB frequency of 8 kHz.116 It is required to design a noninverting amplifier 2. 1 MHz 105 102 2. 132 Chapter 2 Operational Amplifiers 2. 5 MHz compensated op amps. When a step voltage of 100 mV is applied amplifiers listed below provide the dc gain and the frequency at the input. ** = more difficult. To provide a finite dc gain. Estimate values for input to the follower is a 1-V step.1 f3dB and at 10 f3dB ? is implemented by using an op amp with VOS = 2 mV. is operated with a CHAPTER 2 closed-loop gain of +100 V/V. 5 MHz (e) −1000 V/V. find the 10% to 90% rise A0 . IB = 0. −6° phase shift? A −84° phase shift? What should its value be? (b) With the resistor of (a) in place. 124 For operation with 10-V output pulses with the Whatunity-gainfrequencywouldasingleoperationalamplifier requirement that the sum of the rise and fall times represent require to satisfy her need? Unfortunately. PROBLEMS op amp with ft = 2 MHz.122 Consider an op amp connected in the inverting (c) If Vi = 50 mV.8: Large-Signal Operation op amp with ft = 20 MHz. 2. what is the useful frequency range of configuration to realize a closed-loop gain of −100 V/V operation? utilizing resistors of 1 k and 100 k. what is the amplifier has an ft of 40 MHz. SR = 10 V/μs. what is the maximum frequency before the an inverting amplifier configuration of gain −100. A load resistance RL (d) If f = 50 kHz. V/V at 5 MHz.120 Consider an inverting summer with two inputs V1 and wave can be produced at the output? V2 and with Vo = −(V1 + 3V2 ). used while ensuring full-amplitude output? For such a pulse. in the unity-gain follower configuration.and 90%-height points. what is the maximum possible value of (b) It is required to design a noninverting amplifier with a dc Vp while an undistorted output sinusoid is obtained? gain of 40 dB utilizing a single internally compensated (b) Repeat (a) for RL = 200 . Comment on the results. considers her choice of amplifier topologies. what product (GBP ≡ |Gain| × f3dB ).119 Consider the use of an op amp with a unity-gain 2. * = difficult problem. What is the 3-dB frequency (c) If it is desired to obtain an output sinusoid of 10-V peak obtained? amplitude. ** = more difficult. This problem illustrates the point by considering the use of an Section 2. each is connected from the output to ground. *** = very challenging.125 What is the highest frequency of a triangle wave of frequency ft in the realization of: 10-V peak-to-peak amplitude that can be reproduced by an op amp whose slew rate is 20 V/μs? For a sine wave of the (a) An inverting amplifier with dc gain of magnitude K. Assume a sine-wave input with peak amplitude Vi . Problems 133 CHAPTER 2 (a) Show that cascading two identical amplifier stages.118 A designer. what is the output distorts? rms value of the largest possible sine wave that can be applied (b) If f = 200 kHz. imposed by the op-amp finite be set to zero—an application of superposition.5 V.123 An op amp having a slew rate of 10 V/μs is to be used noninverting amplifiers each with a dc gain of 20 dB. wanting to achieve a stable gain of 100 describe the output resulting. is the highest frequency at which a 20-V peak-to-peak sine *2. How many such amplifiers slew-rate requirement for an op amp to handle pulses 2 μs connected in a cascade of identical noninverting stages would wide? (Note: The rise and fall times of a pulse signal are she need to achieve her goal? What is the 3-dB frequency of usually measured between the 10%. frequency f1 . √ f3dB = 2–1 f1 (a) For RL = 1 k. signal that remains undistorted? In each case find the 3-dB frequency and the gain–bandwidth 2. linearly for outputs in the range −14 V to +14 V. D **2.127 In designing with op amps one has to check the each of the gain functions Vo /V1 and Vo /V2 in terms of the op limitations on the voltage and frequency ranges of operation amp ft . and a low-frequency having a low-pass STC frequency response with a 3-dB sine-wave signal of peak amplitude Vp is applied to the input. Find the 3-dB frequency of D *2. (Hint: In each case.) bandwidth (ft ). what minimum value of RL is allowed? (c) Redesign the amplifier of (b) by cascading two identical 2. results in an overall amplifier with a 3-dB Let the op amp be ideal except that its output voltage saturates frequency given by at ±10 V and its output current is limited to the range ±20 mA. What is the shortest pulse that can be Compare this to the value obtained in (b) above. the best available only 20% of the pulse width (at half-amplitude). If used in (a) If Vi = 0. slew rate (SR). and output saturation (Vo max ). what is the useful input voltage range? = Multisim/PSpice. what is the maximum value of Vi before at the input without output clipping? the output distorts? 2. and Vo max = 10 V of Op Amps in the design of a noninverting amplifier with a nominal gain 2. with input pulses What is the 3-dB frequency of the overall amplifier? that rise from 0 to 2 V.126 For an amplifier having a slew rate of 40 V/μs. the other input to the summer can of the closed-loop amplifier. what is the maximum amplitude of output (b) A noninverting amplifier with a dc gain of K. D = design problem . same frequency.121 A particular op amp using ±15-V supplies operates of 10.) each stage she can use? What is the overall 3-dB frequency? 2. Dp = 12 cm /s. aiming to develop intuition concern- ing conducting paths within an integrated circuit. At 1200 cm /V · s and μp = 500 cm /V · s. (Recall that R = ρL/A. denoted pn0 .1. and 1 μm thick. use the 3. find the density of the current that will flow in the x direction. PROBLEMS 2 If in the following problems the need arises for the values of of 3 V is imposed. Let μn = 1350 cm /V · s and μp = 2 particular parameters or physical constants that are not stated. Here “excess” means 3. established in the n-type silicon region. *** = very challenging.11 Both the carrier mobility and the diffusivity decrease as data in Table 3. The constant B = 3. Use μn = 2 2 for silicon at −55°C. what 22 Recall that a silicon crystal has approximately 5 × 10 donor concentration is needed to realize a current density 3 atoms/cm .) Section 3. 2 of 2 mA/μm in response to an applied voltage of 1 V? 3. For doped silicon.1.2: Doped Semiconductors 3.4 For a silicon crystal doped with phosphorus.10 16 3 (d) p-doped silicon with NA = 5 × 10 /cm (e) aluminum with resistivity of 2. find the hole and electron con- centrations at 27°C and 125°C. 3. the details of which 3.5 In a phosphorus-doped silicon layer with impurity 17 3 concentration of 10 /cm . For intrinsic silicon.6 A young designer. find the hole and electron concentrations excess-hole concentration profile shown in Fig. and 125°C. what must over and above the thermal-equilibrium concentration (in the 16 3 ND be if at T = 300 K the hole concentration drops below the absence of hole injection).11 1200 cm /V · s.3 For a p-type silicon in which the dopant concentration are not important for this question).42 eV.9 In a 10-μm-long bar of donor-doped silicon.56 × 10 cm K −3 −3/2 and the concentration. assume μn = 3μp = 2 the doping concentration of silicon is increased. the 18 3 NA = 5 × 10 /cm . 20°C.10 is at T = 300 K. 10 3 2 8 intrinsic level by a factor of 10 ? ni = 1. made of various materials.5 × 10 /cm .8 Find the current that flows in a silicon bar of 10-μm length having a 5-μm × 4-μm cross-section and having Section 3.1: Intrinsic Semiconductors 4 3 16 free-electron and hole densities of 10 /cm and 10 /cm . examines the end-to-end resistance of a connecting bar 10-μm long.10 Holes are being steadily injected into a region of n-type silicon (connected to other devices. * = difficult problem. 3. P3. to be constant and use 1350 cm /V · s. ** = more difficult. each temperature. pn(x) Section 3. 3 3. D = design problem . The designer considers: pn0 (a) intrinsic silicon 16 3 (b) n-doped silicon with ND = 5 × 10 /cm 0 W x 18 3 (c) n-doped silicon with ND = 5 × 10 /cm Figure P3. 3-μm wide. Use the Einstein relationship to obtain the a 10-μm layer of intrinsic silicon across which a voltage corresponding values for Dn and Dp . = Multisim/PSpice.2 Calculate the value of ni for gallium arsenide (GaAs) at (Note: Although the carrier mobilities change with doping 14 T = 300 K.7 Contrast the electron and hole drift velocities through concentration. If ND = 10 /cm . 480 cm /V · s· please consult Table 3. and W = 50 nm.8 μ· cm Find the resistance in each case. what fraction of the atoms is ionized? 3.3: Current Flow in Semiconductors 108 pn0 n region 3. In the steady state. when a 1 V is applied end-to-end. 0°C.) provides a few data points for μn and μp versus doping 3. Table P3. 75°C.1 Find values of the intrinsic carrier concentration ni respectively. the value for intrinsic silicon. as a first approximation you may assume μn 2 bandgap voltage Eg = 1. 4: The pn Junction charge stored on either side of the junction. Assume that the junction area is 2 Ip Dp Ln NA 100 μm . (3. ND = 3 18 3 concentration on that side of the junction is 10 /cm .11 PROBLEMS Doping Concentration 3 2 2 2 2 (carriers/cm ) μn (cm /V · s) μp (cm /V · s) Dn (cm /s) Dp (cm /s) Intrinsic 1350 480 16 10 1200 400 17 10 750 260 CHAPTER 3 18 10 380 160 Section 3.18 Show that for a pn junction reverse-biased with same factor by which IS changes for a 5°C rise in temperature. 3.5 × 10 /cm . find W and QJ . 2 10 3 by a factor of 10? A = 100 μm . 17 3 16 3 is 10 /cm and the donor concentration is 10 /cm .2) to determine the factor by which ni changes as T junction specified in Problem 3. changes from 300 K to 305 K. 2 2 Dp = 10 cm /s.16 By how much does V0 change if NA or ND is increased a pn junction for which NA = 10 /cm .1-μm depletion layer on one side of a 10-μm × 10-μm junction. Section 3.14 Estimate the total charge stored in a 0. Ln = 10 μm. The doping 18 Evaluate this ratio for the case NA = 10 /cm . Also calculate QJ for the I = 100 μA. * = difficult problem. With the terminals left open. and the depletion 2 Dn = 20 cm /s.13 If.12 Calculate the built-in voltage of a junction in which the 16 p and n regions are doped equally with 5 × 10 atoms/cm . and 3. Assume ni = 1. use the expression for 3. 3. Calculate the magnitude of the charge stored on given by either side of the junction.13.2 μm. ND = 10 /cm . *** = very challenging. ni = 1.21 Assuming that the temperature dependence of IS arises 2 mostly because IS is proportional to ni . find the magnitude of the charge QJ = QJ0 1 + stored on either side of the junction. and how far does it extend into the p and n regions? If the cross-sectional area 2 VR of the junction is 20 μm .5: The pn Junction with an Applied Voltage 3.5 × 10 /cm .5 × 10 /cm . W = W0 1 + V0 what is the width of the depletion region. for a particular junction. Lp = 5 μm. Ln = 10 μm. D = design problem . 3 10 3 VR Assume ni = 1. a voltage VR . and Dn = 18 cm /s. find the 10 3 junction built-in voltage. This will be approximately the 3.15 In a pn junction for which NA ND . Also.19 In a forward-biased pn junction show that the ratio find the width of the depletion region (W) and its extent in of the current component due to hole injection across the each of the p and n regions when the junction terminals are junction to the component due to electron injection is left open. 16 3 2 10 /cm . Dp = 10 cm /s. the depletion-layer width W and the What is the factor? = Multisim/PSpice. = In Dn Lp ND 3. V0 3. can be expressed as 3.20 Calculate IS and the current I for V = 750 mV for 17 3 16 3 3. find V0 if ND = 10 /cm . QJ . Lp = 5 μm. 172 Chapter 3 Semiconductors Table P3. 2 case A = 10 μm . the acceptor concentration where W0 and QJ0 are the values in equilibrium.17 If a 3-V reverse-bias voltage is applied across the 2 ni in Eq. ** = more difficult. and hence find Ip and In for the case layer exists mostly on the shallowly doped side with W = in which the pn junction is conducting a forward current 16 3 0. Assume operation at 300 K where region is a straight line rather than the exponentials shown in 10 3 ni = 1. 3.28 For the p n junction specified in Problem 3. maximum allowable) power dissipation of to Fig.6: Capacitive Effects in the pn Wn − xn ND Wp − xp NA i Junction and 3.47) and (3. Fig.22.29 A short-base diode is one where the widths of the p PROBLEMS 17 3 2 For the specific case in which ND = 10 /cm .1 mA. 3.45) [or equivalently. and n regions are much smaller than Ln and Lp . 2 by combining Eqs. show that eA τT Cj = Cd = I W VT Show that this approach leads to a formula identical to that where obtained by combining Eqs. and A = 10 μm .e. I Ip = Aqni e −1 Lp ND *3. the excess minority-carrier distribution in each obtained when I = 1 mA. 4 2 Lp = 10 μm. * = difficult problem.48)]. (3.23 A pn junction for which the breakdown voltage is 12 V (a) For the short-base diode.26 The junction capacitance Cj can be thought of as that of a parallel-plate capacitor and thus given by (c) Also. Dp = 10 cm /s.25 For a particular junction for which Cj0 = 0. Show that and calculate the excess minority-carrier charge and the value 2 Dp V/VT of the diffusion capacitance at I = 0. What diffusion capacitance do you expect this junction should Wn be? Assume Dp = 10 cm /s. = Multisim/PSpice.. 2 Dp p 3. D = design problem . find τp across the junction.27 A pn junction operating in the forward-bias region with a current I of 1 mA is found to have a diffusion capacitance of (d) If a designer wishes to limit Cd to 8 pF at I = 1 mA. assuming Q Qp .25 W. for Wn xn and 10 V.22 A p n junction is one in which the doping concentration in the p region is much greater than that in the n region.12 and assume as in Fig. the forward current is mostly due to hole injection + 3. and m = 1/3. 3. find Cj at reverse-bias voltages of 1 V 1 Wn I . ** = more difficult. 1 Wn τT = 2 Dp 3. respectively. What continuous current in the breakdown region (b) Following a derivation similar to that given in Section will raise the dissipation to half the rated value? If breakdown 3. 1 Wn − xn Qp = Ip 2 Dp 3.12 that NA ND . find IS and the voltage V As a result.5.43) and (3.13. V0 = 2 0.4 pF. *** = very challenging.24 For the pn junction specified in Problem 3.12. sketch a figure corresponding has a rated (i.2. 0. show that if the widths of the p and n regions are occurs for only 10 ms in every 20 ms.1 mA? What is the mean transit time for this CHAPTER 3 3. find Cj0 2 and Cj at VR = 3 V. (3.75 V. what 2 5 pF. I Ip . Problems 173 + to have at I = 0. In such junction? a junction. 3.5 × 10 /cm . what average breakdown denoted Wp and Wn then current is allowed? Dp Dn + 2 V/V I = Aqn e T −1 Section 3. a voltage regulator is employed. is connected values? = Multisim/PSpice.1 An AA flashlight cell. In this way the output waveform has a nonzero reduced considerably by connecting a capacitor C across average or dc component. *** = very challenging. either The bridge-rectifier circuit is the preferred full-wave the positive or negative peaks of the signal will be clamped rectifier configuration. The output waveform then consists of a By cascading a clamping circuit with a peak-rectifier dc voltage almost equal to the peak of the input sine circuit. and the circuit is known as a dc the output load resistance R. be found in the corresponding files on the website. P4. Section 4.5 V and a resistance of 1 .230 Chapter 4 Diodes In many applications. 5-V peak sine wave. 4. one or both extremities of the output waveform from going Half-wave rectifiers do this by passing the voltage in half beyond predetermined values.2 For the circuits shown in Fig. What are the diode current and terminal Problems identified by the Multisim/PSpice icon are voltage when (a) the connection is between the diode cathode intended to demonstrate the value of using SPICE simulation and the positive terminal of the battery and (b) the anode and to verify hand analysis and design. and to investigate the positive terminal are connected? important issues such as allowable signal swing and amplifier nonlinear distortion.1: The Ideal Diode v I is a 1-kHz. Full-wave rectifiers accomplish Applying a time-varying waveform to a circuit consisting the task by passing the voltage in half of each cycle and of a capacitor in series with a diode and taking the inverting the voltage in the other half-cycle. resistors. What are its positive and negative peak voltage source of 1. peak rectifier. Describe two possible situations that result. output across the diode provides a clamping function. Combination of diodes. statement.7 V. PROBLEMS Computer Simulation Problems to the terminals of an ideal diode. whose Thévenin equivalent is a resulting at v O . a conducting diode is modeled as wave. of each cycle and blocking the opposite-polarity voltage in the other half of the cycle. the limiting level(s). Vp . ** = more difficult. and Multisim simulations for all the indicated problems can find the values of the voltages and currents indicated. amplitude Vr = Vp /2fCR. find the values of the labeled voltages and currents.4 In each of the ideal-diode circuits shown in Fig. The resulting circuit is the restorer. depending on the polarity of the diode. and possibly reference voltages can be used to design voltage limiters that prevent Rectifiers convert ac voltages into unipolar voltages. on which is superimposed a ripple component of having a constant voltage drop. to the voltage at the other terminal of the diode (usually The variation of the output waveform of the rectifier is ground). a voltage doubler is realized. P4. Sketch the waveform 4.3 For the circuits shown in Fig. you are to make a reasonable assumption. D = design problem . * = difficult problem. P4. usually approximately frequency 2f (in the full-wave case) and of peak-to-peak 0. A diode biased to operate at a dc current ID has a small-signal resistance rd = VT /ID . Instructions to assist in setting up PSPice 4.4. To reduce this ripple voltage further.3 using ideal diodes.2 using ideal diodes. Specifically. Note that if a particular parameter value is not specified in the problem 4. D = design problem .3 D1 D1 D2 D1 D2 vI vO vI vO vI vO 1 k 1 k 1 k (a) (b) (c) D3 D1 D2 D1 vI vO vI vO vI vO 1 k 1 k D2 1 k D2 D1 (d) (e) (f ) Figure P4.4 = Multisim/PSpice. *** = very challenging. ** = more difficult. Problems 231 CHAPTER 4 3 3 3 3 PROBLEMS 3 3 3 3 (a) (b) (c) (d) Figure P4.2 D 3 2 2 D D 2 2 3 D (a) (b) Figure P4. * = difficult problem. Using diodes. 232 Chapter 4 Diodes 1 k vI vO PROBLEMS 1 k 1 k vI vO vI vO 1 k D1 D1 D2 D1 CHAPTER 4 (g) (h) (i) 15 V 1 mA D1 vO 1 k vI vO 1 k 1 k D1 D2 vI ( j) (k) Figure P4. What logic of v I is reduced by 10%. * = difficult problem. P4. I is a 60-mA current source. Here v I is a 6-V peak sine wave. Sketch and label the waveform of the battery current iB . What prepare a table with four columns including all possible input is its peak value? What is its average value? If the peak value combinations and the resulting values of X and Y. what do the peak and average values function is X of A and B? What logic function is Y of A and B? of iB become? For what values of A and B do X and Y have the same value? For what values of A and B do X and Y have opposite values? D3 A I iB I D1 B Y vI vO D4 D1 D2 A X I B B D2 (a) (b) Figure P4. P4.6 The circuits shown in Fig.4 continued 4. D = design problem . D1 and D2 are ideal gates for input voltages that are either high or low.6 = Multisim/PSpice.5 The circuit shown in Fig. *** = very challenging.5 is a model for a battery 4.6 can function as logic charger.5 Figure P4. ** = more difficult. “1” to denote the high value and “0” to denote the low value. and B is a 3-V battery. resembling that 6 k 12 k in Fig.5(a).16 can be used in a signaling system using one wire plus a common ground return.9 peak-to-peak voltage only to the nearest volt. 4. the input has one of three values: +3 V.13 for the situation in which the average voltage of the square wave is 1 V. 4. P4. ** = more difficult. 4.10 would you choose to guarantee the required charging current? are ideal. while its peak-to-peak value remains at 5 V.14 Repeat Problem 4. 4. P4.3(a) and employing a 100- resistor.8 Repeat Problem 4. in which current flows to the 12-V battery 25% of the time with an average value of 100 mA. let the input sine wave have 120-V rms value and assume the diode to Figure P4.16 = Multisim/PSpice. assume ideal diodes be ideal. what design 4.13 A symmetrical square wave of 5-V peak-to-peak 3V 3V amplitude and zero average is applied to a circuit resembling that in Fig. Problems 233 CHAPTER 4 D 4.15 Design a battery-charging circuit. sketch and clearly label the transfer characteristic v O versus v I .5(b). PROBLEMS ideal.4(a) and using an ideal diode.2 mA.3(a). find the values of the labeled voltages and currents.10 D 4. What peak-to-peak sine-wave voltage is required? 3V 3V What resistance is required? What peak diode current flows? (a) (b) What peak reverse voltage does the diode endure? If resistors can be specified to only one significant digit.16 The circuit of Fig. At any moment. 0 V. Select a suitable value for R so that the peak diode and input voltage levels of 0 V and +5 V. 4.3(a) in the event D 4. the average diode current? What is the peak diode current? What peak reverse voltage does the diode endure? 5V 5 V 3 V 4.7 for the logic gate of Fig. 4. 10 k 10 k I V 10 10 k 10 k D D (a) (b) Figure P4. and the Figure P4. D = design problem . What is the peak output voltage that results? What is the average output 12 k 6 k voltage that results? What is the peak diode current? What is the average diode current? What is the maximum reverse voltage across the diode? D D D D 4.11 For the rectifier circuit of Fig.10 Assuming that the diodes in the circuits of Fig.9 are Rs = R and assuming the diode to be ideal. that the input source v I has a source resistance Rs . D *4. 4. –3 V.7 For the logic gate of Fig. For the case 4.12 Consider the rectifier circuit of Fig. * = difficult problem. utilize Thévenin’s theorem to simplify the circuits What fraction of the cycle does diode current flow? What is and thus find the values of the labeled currents and voltages. *** = very challenging. What is the greatest reverse value for R so that the current required from each of the input voltage that will appear across the diode? signal sources does not exceed 0. Find a suitable current does not exceed 40 mA.9 Assuming that the diodes in the circuits of Fig. 4. P4. 20 A particular diode is found to conduct 1 mA with a supplied with a constant current I. and the voltage VD that appears the diode current.2: Terminal Characteristics of Junction Diodes CHAPTER 4 4.00 A together and fed with a constant current I. (a) 10.000IS ? In terms of IS . all on one wire!) Section 4.17 Calculate the value of the thermal voltage.27. For each diode.7 V? Figure P4. Find the value of the current I required I2 V to obtain an output voltage VO = 2. The two anodes are joined together and 4. What is the effect on the junction voltage of 0.0 V.21 The following measurements are taken on particular fed with a constant current I.650 V at I = 1.27 In the circuit shown in Fig.25 Two diodes with saturation currents IS1 and IS2 are in junction voltage will increase the diode current by a factor connected in parallel with their cathodes joined together and of 10? connected to grounds.650 V at I = 10 μA areas should these diodes have if their currents must have (d) V = 0. What current will flow in this diode forward voltage of the diode if an identical diode is connected if the junction voltage is raised to 0.18 At what forward voltage does a diode conduct a current equal to 10. P4. *** = very challenging.7 V. In each case. ** = more difficult.69 V? To 0.6 V? What change 4.23 utilizes three identical diodes −14 having IS = 10 A. 4. what is the change in output voltage? Figure P4.26 Four diodes are connected in parallel: anodes joined (a) V = 0. VT . 700 mV 10 mA (c) 10 A. and +125°C. P4. with the smallest being 0. 234 Chapter 4 Diodes PROBLEMS What is the status of the lamps for each input value? (Note that the lamps can be located apart from each other and that there may be several of each type of connection.22 Listed below are the results of measurements taken on several different junction diodes. at –55°C.7 V at 1. At what temperature is VT exactly 25 mV? 4.700 V at I = 100 mA binary-weighted ratios. D = design problem .0 mA.24 A junction diode is operated in a circuit in which it is 4.71 V? To 0. * = difficult problem. 600 mV D2 D1 4. estimate values of IS and across their parallel combination. If a current of 1 mA 3 mA is drawn away from the output terminal by a load. 700 mV I1 (b) 1.0 mA. For each diode. What is the value of the current? 4. the data 4.5 V.19 A diode for which the forward voltage drop is 0.0 mA is operated at 0. 700 mV (e) 10 μA. What value of V results? To obtain a value voltage V. the terminal voltage at 10% of the measured current.23 The circuit in Fig. what current I2 is needed? 10I and I/10. what current flows in the same diode when its forward voltage is 0.700 V at I = 1. and the diode voltage at for V of 60 mV.8 V? If the in parallel? junction voltage is lowered to 0. and cathodes joined (b) V = 0. What relative junction (c) V = 0.1 mA? What value of I is needed? 4.00 mA together and connected to ground. 800 mV (d) 1 mA.27 = Multisim/PSpice. D1 has 10 times the provided are the diode current I and the corresponding diode junction area of D2 . estimate IS .23 4. 0°C. Find the currents ID1 and ID2 that junction diodes for which V is the terminal voltage and I is flow through the two diodes. +40°C. However. D1 is a large-area. P4. diode in its final state? What is the temperature rise per watt of power dissipation? (This is called the thermal resistance.31 When a 10-A current is applied to a particular diode. one that has v D = 0. P4.34 Consider the graphical analysis of the diode circuit of Fig. supply two diodes of different junction areas with equal cur- high-current diode whose reverse leakage is high and rents and to measure their junction-voltage difference. Two independent of applied voltage. types of diodes are available: for a forward voltage of 700 mV. it is found that the voltage decreases and 1 mA) is connected in series with a 500- resistor to a 1..10 for 4. and a diode having −15 IS = 10 A. Find the value of R for which V = 50 mV.33 As an alternative to the idea suggested in Prob- lem 4. What do you expect each. By how much does it differ from the graphically estimated value? Figure P4. for which the D2 D1 nominal current at 0.32 A designer of an instrument that must operate I over a wide supply-voltage range. A power diode. = Multisim/PSpice.36 A “1-mA diode” (i. Problems 235 CHAPTER 4 4.28 *4. while D2 is a much smaller. −15 VDD = 1 V. in addition. considers the use of a large diode to establish a small PROBLEMS relatively constant voltage. At an ambient temperature of 20°C. what range of difference voltages result? What is the the voltages VR1 and V2 to become at 0°C and at 40°C? effect of a temperature change of ±20°C on this arrangement? 10 V Section 4. ** = more difficult.3: Modeling the Diode Forward Characteristic R1 *4. R = 1 k. Calculate a small number of points on the diode characteristic in the vicinity of where you expect the load D1 V1 line to intersect it. current mirroring).e.35 Use the iterative-analysis procedure to determine the diode current and voltage in the circuit of Fig. 4.1 mA. *** = very challenging. one conducts 0. * = difficult problem. both diodes are junction temperature? What is the power dissipated in the identical. the temperature changes by ±20°C. low-current diode. while the other conducts 1 A.29 A diode fed with a constant current I = 1 mA has a supply: It relies on the ability to make quite accurate copies voltage V = 690 mV at 20°C. 4.30 4.0 V eventually reaches 600 mV. If the current source feeding the diode changes in the range 1 mA to 3 mA and if. is available.) *4.28 For the circuit shown in Fig.8 V is 10 A. What is the apparent rise in supply. and use a graphical process to refine your estimate of diode current. the designer considers a second approach to produc- ing a relatively constant small voltage from a variable current 4.28. it is found that the junction voltage immediately becomes 700 mV. What value of diode current and voltage do you find? Analytically. as the power being dissipated in the diode 4. Subsequent identical currents in the range of 1 mA to 3 mA supplied to measurement indicates that R1 is 520 k. noting that a diode’s 10 mA junction-voltage drop is relatively independent of junction current. D = design problem . what R V is the expected range of diode voltage? Figure P4.32. The designer proposes to use this idea to 4.30 In the circuit shown in Fig. find the voltage D2 V2 corresponding to your estimate of current.10 with VDD = 1 V.30. R = 1 k.7 V at iD = raises its temperature. Find the diode voltage at −20°C of any small current that is available (using a process called and at +85°C. and a diode having IS = 10 A. for resistor R1 is adjusted to make VR1 = V2 = 520 mV. Now. 40 Solve the problems in Example 4.7 V. vo = vs VT + IRs 4. 236 Chapter 4 Diodes PROBLEMS (a) Provide a rough estimate of the diode current you would 4. constant-voltage-drop (VD = 0.2 associated with the wire bonds to the junction. P4. find the voltages and currents indicated.7 V) diode model.7-V drop when the to be 3. in series with a resistor R connected to a 4.43 For the circuits in Fig. what 4.48 = Multisim/PSpice. using the constant-voltage-drop (VD = 0. P4. and 1 μA.1 A. current through it is 20 mA) connected in parallel operate at a total current of 0.45 Repeat Problem 4. Let constant-voltage-drop (VD = 0. Use the diode small-signal model to show that the signal component of the output voltage is 4. At what value of I does v o become one-half of v s ? voltages and currents indicated.7 V) diode model. D 4.2. find the Rs = 1 k. 4.3. is uncertain whether to use 0. How different is the resulting design? Figure P4.7 V) diode model. If each of the 20-mA diodes has a series resistance of the calculated values of current only 1%? For V = 3 V and 0. 0. rem to simplify the circuits and find the values of the labeled vo currents and voltages. find the C1 C2 values of the labeled currents and voltages.75 V at iD = 1 mA.41 For the circuits shown in Fig. using the attenuation factor controlled by the value of the dc current I. For the diodes closely matched.7 V) model.7 V with the incremental resistance of a single diode conducting or 0.1 mA.39 A designer has a supply of diodes for which a current of 2 mA flows at 0. How many diodes are needed? What block the dc current from flowing into the signal source or the voltage is actually achieved? load (not shown). To what percentage current change (b) Estimate the diode current more closely using iterative does this correspond? (Consider both positive and negative analysis. variations of about 5 mV. Capacitors C1 and C2 are very large. ten “20-mA diodes” 15-V power supply. what is R = 1 k. *** = very challenging.3 V.10.11. * = difficult problem. what two current estimates would result from the equivalent resistance of the 10 parallel-connected diodes? the use of the two values of VD ? What is their percentage What connection resistance would a single diode need in difference? order to be totally equivalent? (Note: This is why the parallel connection of real diodes can often be used to advantage.7 V) diode model. design a circuit that utilizes four diodes CHAPTER 4 connected in series. 4. For what value of V is the difference in 0. P4. I is a dc current and designer wishes to create a reference voltage of 1.42 For the circuits shown in Fig. utilize Thévenin’s theo.37 Assuming the availability of diodes for which v D = to 10%? 0. considering using a resistance of each diode and of the combination? Compare this constant-voltage model. the 4.47 In a particular circuit application.46 The small-signal model is said to be valid for voltage expect.48 In the circuit shown in Fig. a combination of series and parallel diodes that will do the their function is to couple the signal to and from the diode but job as well as possible. The voltage across the string of diodes is (a 20-mA diode is a diode that provides a 0.) What is the maximum allowable voltage signal (positive or negative) if the current change is to be limited D 4. P4.) 4.38 A diode operates in a series circuit with a resistance current flows in each? What is the corresponding small-signal R and a dc source V. representing the diode by the constant-voltage-drop (VD = 0.7 V). Note that this circuit functions as a signal attenuator with the 4. Using a 1-mA current source.9.2 using the VT constant-voltage-drop (VD = 0. A designer.44 For the circuits in Fig.1 A. P4.48. Suggest v s is a sinusoidal signal. find v o for I = 1 mA. D = design problem . signals. ** = more difficult.3 V.6 V for VD . Assume that conducting diodes can be represented by the constant-voltage-drop model (VD = 0. using the If v s = 10 mV. 51 for small input signals.50 In the capacitor-coupled attenuator circuit shown in What is the total current in each diode? Fig. for the circuit in Fig. and each exhibits a voltage drop of 0.7 V at +9. what is the largest possible output signal PROBLEMS signals correspond? for which the diode currents deviate by at most 10% of their dc values? What is the corresponding peak input? 4. find the sketch the required VTC. +10. Find v o /v i for I = 0 μA. observe that values of the small-signal transmission v o /v i for various as vO increases and iO correspondingly increases. so that the diodes can be represented by their small-signal resistances rd1 and rd2 . 10-mV peak). same) equal amounts.52 In Problem 4.10? 0. that is. use the diode exponential Figure P4. +2 V. +11 V. and 1 mA. 600 μA. the voltage drop across each of the four diodes. I is a dc current that varies from 0 mA to 1 mA. the current in each of the four diodes. diodes D1 through the input voltage v I .99 V. and C1 and C2 are large coupling capacitors. 10 μA.50? 0. +9. +5 V. D = design problem .9 V. data. 500 μA. vi D3 D1 10 μA. what is the largest The diode is a 1-mA device. Use these a 1-mA current. it exhibits a voltage drop signal-voltage magnitude that it can support while the of 0. *** = very challenging.51. 900 μA. 1 μA.51 C1 vi **4. where I is in mA.001? In each case. 990 μA.50 characteristic to construct a table that gives the values of: the current iO in the 10-k resistor. what is the largest input signal that can peak input. iD3 and iD2 values of I: 0 μA.g. In this problem I we wish to find the voltage-transfer characteristic (VTC) v O versus v I for −12 V ≤ v I ≤ 12 V for the case I = 1 mA and each of the diodes exhibits a voltage drop of 0.49 In the attenuator circuit of Fig. 100 μA. For very small input signals. to (a) For small input signals (e. CHAPTER 4 (b) For a forward-conducting diode. For small input signals. what corresponding signal current is limited to 10% of the dc value of current I is needed for v o /v s = 0. * = difficult problem. Also sketch the VTC that results if small-signal equivalent circuit and use it to determine I is reduced to 0. (Hint: From symmetry. P4. Note that this is a signal attenuator whose transmission is linearly controlled by the dc current I.7 V at a dc current of 1 mA. what is the smallest value of I for which the be used while ensuring that the signal component of the diode diode currents remain within ±10% of their dc values? current is limited to ±10% of its dc current? What output (c) For I = 1 mA. for 10-mV 0.51 we investigated the operation of the circuit in Fig. let Rs = 10 k. and increase by equal amounts and iD4 and iD1 decrease by (the 10 mA. 1 mA..01? bias current? Now. Toward this end. P4. +9 V.50. P4. +1 V. give the small-signal v rd2 I equivalent circuit and thus show that o = and hence v i rd1 + rd2 vo that = I.7 V at a current of 1 mA. 1 μA. with extrapolation to negative values of v I and v O .51. and +12 V. for v O = 0. D4 are identical. and *4. P4.5 V.5 mA. Problems 237 4.51 In the circuit shown in Fig. P4.) = Multisim/PSpice. vo vi 10 k D2 D4 1 mA C2 I vo D1 D2 Figure P4.48. ** = more difficult. 100 μA. 54 diode current with the load connected? What is the increase resulting in the output voltage when the load is disconnected? (a) Use the diode small-signal model to show that the change What change results if the load resistance is reduced to 1 k? in output voltage corresponding to a change of 1 V in To 750 ? To 500 ? (Hint: Use the small-signal diode model + V is to calculate all changes in output voltage. If V is nominally 15 V. P4. and thus find the phase shift *4. which is a function of I. D = design problem . + by its small-signal resistance rd . 238 Chapter 4 Diodes PROBLEMS *4.7 + VT voltage VO (across the diode) of 0.7-V drop at a current of 1 mA. ** = more difficult. *** = very challenging.5 V. (b) If the value of R is selected such that at no load the voltage across the diode is 0. specify the diode required in terms of its IS .7m V). and find the range of phase shift achieved from the output terminal. Select the lowest possible value for ID that results in a V + load regulation whose magnitude is ≤ 5 mV/mA. Find the value of I that will provide a CHAPTER 4 Fig P4.7 V.56 Design a diode voltage regulator to supply 1.53 In the circuit shown in Fig. sinusoidal output voltage Vo . P4. VO D *4.54. Use two diodes specified to have a 0. show Figure P4. voltage 1.7 V (and VO = 0.7 V and the diode current is ID .1 times to 10 times this value.55 Consider the voltage-regulator circuit shown in between Vi and Vo . The diodes are to be connected to a +5-V supply through a resistor R.7 series fed with a constant-current source is used as a This quantity is known as the line regulation and is usually replacement for a single carbon–zinc cell (battery) of nominal expressed in mV/V. Representing the diode voltage across each diode is 0.53. The value of R is selected to obtain an output IL ID V − 0. (a) If the value of IL is sufficiently small that the corre- sponding change in regulator output voltage VO is small enough to justify using the diode small-signal model. R (c) Generalize the expression derived in (b) for the case of m diodes connected in series and R adjusted to obtain VO = 0. I show that vo VO = − rd R IL C 10 nF This quantity is known as the load regulation and is vi usually expressed in mV/mA.54 Consider the voltage-regulator circuit shown in VO V V −0.53 that the expression derived in (a) becomes + *4.) VO VT = + D *4. * = difficult problem. sketch (c) Calculate the value of line regulation for the case V = the small-signal equivalent circuit and use it to determine the 15 V (nominally) and (i) m = 1 and (ii) m = 4.57 A voltage regulator consisting of two diodes in V + V + VT − 0. What is the Figure P4. what value of R is required? Also. Specify the value for R.7m V at no load.7 =− T + Fig. as I is varied over the range of 0.5-k load. The regulator load current varies from 2 mA to = Multisim/PSpice.5 V to a 1.54 under the condition that a load current IL is drawn phase shift of –45°. I is a dc current (b) Generalize the expression above for the case of m diodes and v i is a sinusoidal signal with small amplitude (less than connected in series and the value of R adjusted so that the 10 mV) and a frequency of 100 kHz. each what is the power rating of each of the diodes described above? has a voltage drop of 0. Two kinds of zener diodes are available: 6. P4. rz = 750 . find the load regulation. For the second design.1-V zener diode exhibits its nominal voltage at a test VO 150 current of 20 mA.5 varies over its full range? Assuming that the power rating of a breakdown diode is **4. In this calculation neglect the effect of the regulator resistance R.64 Provide two designs of shunt regulators utilizing the what percentage does the output voltage change for each 1N5235 zener diode. For both designs. and VZK = 17. (a) VZ = 10.5-V zener regulator circuit using a 7. design find the value of R and the line regulation.25 mA.1 V of its nominal value? resistor that can be used while the zener operates at a current (d) What does the loaded output voltage become when the no lower than the knee current while the supply is 10% low? 5-V supply is raised by the same amount as the drop What is the load voltage in this case? found in (c)? (e) For the range of changes explored in (c) and (d).8 V percentage change of supply voltage in the worst case? and rz = 5 for IZ = 20 mA. VZK = 9. to what value can the 5-V supply What is the output voltage when both the supply is 10% high be lowered while maintaining the loaded output voltage and the load is removed? What is the smallest possible load within 0.61 A shunt regulator utilizing a zener diode with an 200 incremental resistance of 8 is fed through an 82- resistor.63 Design a 7. VZ = 7. what is the corresponding change in the regulated output voltage? D1 4. The (a) What is the regulator output voltage VO with the 150- regulator operates from a 10-V supply and has a 1.62 A 9. assume no load.1 V at IZ = 9 mA. 10 mA.59 Partial specifications of a collection of zener diodes are assume that the current from the raw supply is limited. The zener has an incremental resistance rz = 30 and a knee current of 0. Fig.58 A particular design of a voltage regulator is shown in established at about twice the specified zener current (IZT ).1-V zener (b) IZT = 10 mA.60 A designer requires a shunt regulator of approxi- diode exponential model and iterative analysis to answer the mately 20 V. by D 4. that is. For each. 4.5-V Figure P4. Find the zener voltage at a current of 10 mA and at 50 mA.5 mA. identify the missing parameter and therefore you are forced to operate the diode at 0. output voltage when the supply is 10% high? Is 10% low? (c) With the load connected. * = difficult problem. and why? What (d) VZ = 18 V. and rz = 30 diode for which VZ = 9.8-V following questions: devices with rz of 10 and 5.5 V. Find VZ0 of the zener model.1 V.58. At this current the incremental resistance D2 is specified as 10 . For 5 V the two major choices possible. Diodes D1 and D2 are 10-mA units. and thus operate the diode at 20 mA. at IZ = 0. VZ = 9.5-k load. IZT = 5 mA. VZ = 6. the supply voltage is Section 4. For the first design. load connected? What is the value of R you have chosen? What is the regulator (b) Find VO with no load. nominally 9 V and varies by ±1 V. 4.25 mA (nearer the knee). and rz = 1.4: Operation in the Reverse Break. If the raw supply changes by 1. Which would you choose. and 15 mA are available.0 V. and provided below. Note from Fig.7 V at a current of 10 mA. Constant-current supplies of 5 mA.65 A zener shunt regulator employs a 9. D 4. Problems 239 (c) rz = 2 . For each is very small. which is specified as follows: VZ = 6. *** = very challenging.6 V. ** = more difficult. For estimate its value.19 that VZK VZ0 and IZK the purpose of these initial designs. with rz = 40 and = Multisim/PSpice. 4. and VZK = 6.6 V CHAPTER 4 7 mA.1-V devices with rz of 25 . and IZT = 50 mA D *4. down Region—Zener Diodes assume that the availability of supply current is not a problem.0 V.8 V. Use the PROBLEMS D 4.58 zener specified at 10 mA. D = design problem .6 V change in output voltage would result when the load current (e) IZT = 200 mA. 72 A full-wave bridge-rectifier circuit with a 1-k load design is required to conduct? What is the zener power operates from a 120-V (rms) 60-Hz household supply through dissipation under this condition? a 12-to-1 step-down transformer having a single secondary winding.69 Consider a half-wave rectifier circuit with a regulation when the supply voltage is low? What is the lowest triangular-wave input of 5-V peak-to-peak amplitude and possible output voltage that results? Calculate values for the zero average.7 V. Assume that the diode line regulation and for the load regulation for this circuit using can be represented by the constant-voltage-drop model with the numerical results obtained in this problem. 4.71 A full-wave rectifier circuit with a 1-k load operates (a) Find VZ0 . The regulator is required to supply a cycle does the diode conduct? What is the average output load current of 0 mA to 20 mA. corresponding to the ±25% drop for all currents. VD = 0. its rz is 7 . The raw modeled to have a 0. show that as much as ±10%. What is the peak voltage of the rectified change in VS ? output? For what fraction of a cycle does each diode conduct? (d) Find the load regulation.23(a) For a nominal load resistance RL of 1 k and a nominal zener has the transfer characteristic current of 10 mA.73 It is required to design a full-wave rectifier circuit (a) Sketch the transfer characteristic. 50%.68 Using the exponential diode characteristic. What is the change in VO uses two silicon diodes that can be modeled to have a 0.66 It is required to design a zener shunt regulator to 4. (d) Find the peak current in the diode. It uses four diodes. what is the value of VZ0 ? for v S and v O both greater than zero. voltage of: (c) Find the average value of v O . * = difficult problem. 4. D *4. It (c) Find the line regulation. At this current. The available supply voltage of 15 V can vary PROBLEMS 4. What is the peak value of the rectified voltage across the load? For what fraction of a 4. available has a nominal value of 20 V but can vary peak voltage of the rectified output? For what fraction of the by as much as ±25%. from a 120-V (rms) 60-Hz household supply through a 6-to-1 (b) Calculate the required value of R.7 V. 4.24 to provide an average output (b) Sketch the waveform of v O .23(a) cycle does each diode conduct? What is the average voltage with the diode reversed. 240 Chapter 4 Diodes IZK = 0. using the circuit of Fig. The available 10-V.7-V drop for any current. from a 120-V (rms) 60-Hz household supply through a 12-to-1 1-W zener of type 1N4740 is specified to have a 10-V drop at step-down transformer. what variation characteristic v O vs. Use the constant-voltage-drop load? diode model with VD = 0. (b) 100 V = Multisim/PSpice. 4. What nominal output voltage results? CHAPTER 4 this relationship can be used to obtain the voltage transfer For a ±10% change in the supply voltage. specified to one significant digit.70 A half-wave rectifier circuit with a 1-k load operates provide a regulated voltage of about 10 V. Find the average value of v O .7-V expressed as a percentage.5 mA. each of which can be modeled Section 4. Note that at least that current. D = design problem . It uses a silicon diode that can be a test current of 25 mA. to provide where v S and v O are in volts and R is in kilohms. what current must flow in the supply resistor R? For the nominal value of supply voltage. and with R = 1 k.7-V drop for any current. (a) 10 V (e) Find the PIV of the diode. D 4.5: Rectifier Circuits to have a 0. ** = more difficult. and let R = 1 k. VS . select a value v O = v S − v D at iD = 1 mA − VT ln v O /R for resistor R. *** = very challenging. transformer having a center-tapped secondary winding. v S by finding v S corresponding to various in output voltage results? If the load current is reduced by values of v O . the circuit of Fig. what increase in VO results? What is the smallest value of load resistance that can be tolerated while maintaining 4. By what percentage does VO What is the average output voltage? What is the average change from the no-load to the full-load condition? current in the load? (e) What is the maximum current that the zener in your 4. Design for a minimum zener voltage? What is the average current in the load? current of 5 mA. For this diode. What is the supply. Let v S be a sinusoid with 10-V peak across the load? What is the average current through the amplitude.67 Consider the half-wave rectifier circuit of Fig. Sketch and clearly label conduction. (i) 10% of the peak output and (ii) 1% of the peak output. Problems 241 CHAPTER 4 D D D D PROBLEMS Figure P4. 4. The rectifier feeds a load of 200 . D *4.83 Consider a half-wave peak rectifier fed with a voltage v S having a triangular waveform with 24-V (a) What average output voltage results? peak-to-peak amplitude.77 for the rectifier in Problem 4.78 Repeat Problem 4. The diodes of Fig.74 Repeat Problem 4. find the required (b) Find the required value of the filter capacitor.7-V drop when conducting. The rectifier is fed from the line D 4.24 when the opts for the half-wave circuit: transformer turns ratio is such that the voltage across the entire (a) Specify the rms voltage that must appear across the secondary winding is 20 V rms. (120 V rms) fluctuates by as much as ±10%. If the magnitude of the average of D *4.81 Repeat Problem 4. and specify the PIV rating of the diode. power supply that provides an average dc output voltage of The ac line voltage is 120 V rms.77 Augment the rectifier circuit of Problem 4. the time interval during which the diode conducts. Assume a 0.80 for the case in which the each output is to be 12 V.70 with a D *4. the waveforms of v O and v O . (Remember to use a factor of safety in your (c) Find the maximum reverse voltage that will appear across design. find the required amplitude of the designer opts for a full-wave circuit utilizing a center-tapped sine wave across the entire secondary winding. If the designer D 4. Find the average dc output voltage. ** = more difficult.7-V drop when conducting.80 for the case in which the capacitor chosen to provide a peak-to-peak ripple voltage of designer opts for a full-wave bridge-rectifier circuit. In each case: D *4. D = design problem .7-V drop across each conducting diode. + − (e) Calculate the peak diode current. and the maximum diode 4. (c) What is the average diode current? Let the load resistance R = 100 and the filter capacitor (d) What is the peak diode current? C = 100 μF.79 Repeat Problem 4. zero average.25.75 Consider the full-wave rectifier in Fig.72. 4. (b) What fraction of the cycle does the diode conduct? Assume that the diode has a 0.80 It is required to use a peak rectifier to design a dc Assume that a conducting diode has a voltage drop of 0. * = difficult problem.77 for the rectifier in Problem 4. 60 Hz) through a transformer. available have 0. diode current during conduction.73 for the bridge-rectifier circuit voltage (120 V rms. the average 4.76 The circuit in Fig.) the diode.82 Repeat Problem 4. PIV of the diodes. *** = very challenging. and 1-kHz frequency. P4.7 V.76 implements a (d) Calculate the average current through the diode during complementary-output rectifier. current.76 In each case find the required turns ratio of the transformer. 4. PIV of each diode? 4.71. = Multisim/PSpice. 12 V on which a maximum of ±1-V ripple is allowed. If the input ac line voltage transformer secondary. What is the transformer. 86 (c) vI = −1 V (d) vI = −3 V Also. and v A for: (a) vI = +1 V (b) vI = +3 V Figure P4.87.7 V. vI D vO vA 3 V v R RL R vI vO 1 k (a) Figure P4.86 is ideal with output saturation levels of ±12 V.6: Limiting and Clamping Circuits symmetrical square wave of 1-kHz frequency. *** = very challenging. All diodes begin conducting at a forward voltage drop of 0. 5-V amplitude. Design the circuit to provide ±12-V dc output voltages with a peak-to-peak ripple no greater than 1 V.7 V when conducting a current iD ≥ 1 mA. P4. Assume that (d) v I = −3 V the diodes available exhibit a 0. diodes.87 = Multisim/PSpice.7-V drop when conducting. * = difficult problem.5 V and have voltage drops of 0. P4. P4. v A . Each supply R should be capable of providing 100-mA dc current to its load resistor R.84 Consider the circuit in Fig. ** = more difficult. and v O vI vO for: 1 k (b) (a) v I = +1 V (b) v I = +3 V Figure P4.7-V drop when conducting. 242 Chapter 4 Diodes (c) v I = −1 V PROBLEMS D *4.76 with two equal filter capacitors placed across the load resistors R. vO v Assume that when conducting the diode exhibits a constant vA voltage drop of 0. and the D1 CHAPTER 4 transformer. Completely specify the capacitors.86 The op amp in the circuit of Fig. D = design problem . the limiter circuits shown in Fig.85 3 V 4. P4.85 The op amp in the precision rectifier circuit of vI D2 Fig. 4.85 is ideal with output saturation levels of ±13 V. R 4. Find v − .87 Sketch the transfer characteristic v O versus v I for and zero average. Find v − . v O . find the average output voltage obtained when v I is a Section 4. The diodes exhibit a constant 0. Problems 243 1 k CHAPTER 4 the diodes can be represented by the constant-voltage-drop vI vO model with VD = 0.7 V. Also assume that the zener voltage is 6.8 V and that rz is negligibly small. *4.91 Plot the transfer characteristic of the circuit in Fig. P4.91 by evaluating v I corresponding to v O = 0.5 V, 3 V 0.6 V, 0.7 V, 0.8 V, 0 V, –0.5 V, –0.6 V, –0.7 V, and –0.8 V. (c) Use the exponential model for the diodes, and assume that they PROBLEMS have 0.7-V drops at 1-mA currents. Characterize the circuit 1 k vI vO as a hard or soft limiter. What is the value of K? Estimate L+ and L− . 3 V (d) Figure P4.87 continued 4.88 The circuits in Fig. P4.87(a) and (d) are connected as follows: The two input terminals are tied together, and the two output terminals are tied together. Sketch the transfer Figure P4.91 characteristic of the circuit resulting, assuming that the cut-in voltage of the diodes is 0.5 V and their voltage drop when conducting a current iD ≥ 1 mA is 0.7 V. 4.89 Repeat Problem 4.88 for the two circuits in 4.92 Design limiter circuits using only diodes and 10-k Fig. P4.87(a) and (b) connected together as follows: The two resistors to provide an output signal limited to the input terminals are tied together, and the two output terminals range: are tied together. 4.90 Sketch and clearly label the transfer characteristic of (a) –0.7 V and above the circuit in Fig. P4.90 for −15 V ≤ v I ≤ +15 V. Assume that (b) +2.1 V and below (c) ±1.4 V Assume that each diode has a 0.7-V drop when conducting. D D 4.93 Design a two-sided limiting circuit using a resistor, two diodes, and two power supplies to feed a 1-k load with nominal limiting levels of ±2.2 V. Use diodes modeled by a constant 0.7 V. In the nonlimiting region, the voltage gain should be at least 0.94 V/V. D D **4.94 In the circuit shown in Fig. P4.94, the diodes exhibit a 0.7-V drop at 0.1 mA. For inputs over the range of ±5 V, use the diode exponential model to provide a calibrated sketch Figure P4.90 of the voltages at outputs B and C versus v A . For a 5-V peak, = Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem 244 Chapter 4 Diodes 1 V PROBLEMS 100-Hz sinusoid applied at A, sketch the signals at nodes B and C. 1 k 5 k D1 A B 3 k CHAPTER 4 vI vO D2 D3 D2 D1 D4 C D3 1 k 1 k 2 V Figure P4.94 Figure P4.95 4.96 A clamped capacitor using an ideal diode with cathode grounded is supplied with a sine wave of 5-V rms. What is **4.95 Sketch and label the voltage-transfer characteristic the average (dc) value of the resulting output? v O versus v I of the circuit shown in Fig. P4.95 over a ±10-V range of input signals. Use the diode exponential model and *4.97 For the circuits in Fig. P4.97, each utilizing an ideal assume that all diodes are 1-mA units (i.e., each exhibits a diode (or diodes), sketch the output for the input shown. Label 0.7-V drop at a current of 1 mA). What are the slopes of the the most positive and most negative output levels. Assume characteristics at the extreme ±10-V levels? CR T . = Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem Problems 245 CHAPTER 4 PROBLEMS (a) (b) (c) (d) (e) (f) (g) (h) Figure P4.97 PROBLEMS Computer Simulations Problems (c) The device is replaced with another fabricated in the same technology but with both the width and length Problems identified by the Multisim/PSpice icon are doubled. intended to demonstrate the value of using SPICE simulation (d) The device is replaced with another fabricated in a more to verify hand analysis and design, and to investigate advanced technology for which the oxide thickness is important issues such as allowable signal swing and amplifier halved and similarly for W and L (assume μn remains nonlinear distortion. Instructions to assist in setting up PSPice unchanged). and Multisim simulations for all the indicated problems can be found in the corresponding files on the website. D 5.5 An NMOS transistor fabricated in a technology for Note that if a particular parameter value is not specified 2 which kn = 400 μA/V and Vt = 0.5 V is required to operate in the problem statement, you are to make a reasonable with a small v DS as a variable resistor ranging in value from assumption. 250 to 1 k. Specify the range required for the control voltage VGS and the required transistor width W. It is required Section 5.1: Device Structure and to use the smallest possible device, as limited by the minimum Physical Operation channel length of this technology (Lmin = 0.18 μm) and the maximum allowed voltage of 1.8 V. 5.1 MOS technology is used to fabricate a capacitor, utilizing the gate metallization and the substrate as the capacitor 5.6 Sketch a set of iD −v DS characteristic curves for an NMOS electrodes. Find the area required per 1-pF capacitance transistor operating with a small v DS (in the manner shown in for oxide thickness ranging from 2 nm to 10 nm. For 2 Fig. 5.4). Let the MOSFET have kn = 5 mA/V and Vtn = a square plate capacitor of 10 pF, what dimensions are 0.5 V. Sketch and clearly label the graphs for VGS = 0.5, 1.0, needed? 1.5, 2.0, and 2.5 V. Let VDS be in the range 0 to 50 mV. Give 5.2 Calculate the total charge stored in the channel of an the value of rDS obtained for each of the five values of VGS . 2 NMOS transistor having Cox = 9 fF/μm , L = 0.36 μm, Although only a sketch, your diagram should be drawn to and W = 3.6 μm, and operated at VOV = 0.2 V and scale as much as possible. VDS = 0 V. D 5.7 An n-channel MOS device in a technology for which 5.3 Use dimensional analysis to show that the units of oxide thickness is 4 nm, minimum channel length is 0.18 μm, 2 the process transconductance parameter kn are A/V . What 2 kn = 400 μA/V , and Vt = 0.5 V operates in the triode region, are the dimensions of the MOSFET transconductance with small v DS and with the gate–source voltage in the range parameter kn ? 0 V to +1.8 V. What device width is needed to ensure that the minimum available resistance is 1 k? 5.4 An NMOS transistor that is operated with a small v DS is found to exhibit a resistance rDS . By what factor will rDS 5.8 Consider an NMOS transistor operating in the triode change in each of the following situations? region with an overdrive voltage VOV . Find an expression for (a) VOV is doubled. the incremental resistance (b) The device is replaced with another fabricated in the same ∂i D rds ≡ 1 technology but with double the width. ∂ v DS v =V DS DS = Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem Problems 293 Give the values of rds in terms of kn and VOV for VDS = 0, voltage, VDS , obtained when v GS = 5 V and iD = 1 mA. If CHAPTER 5 0.2VOV , 0.5VOV , 0.8VOV , and VOV . μp 0.4 μn , what must W/L be for a p-channel device that 2 provides the same performance as the n-channel device in this 5.9 An NMOS transistor with kn = 4 mA/V and Vt = 0.5 V application? is operated with VGS = 1.0 V. At what value of VDS does the transistor enter the saturation region? What value of ID is 5.14 Consider an n-channel MOSFET with tox = 6 nm, μn = 2 obtained in saturation? 460 cm /V · s, Vt = 0.5 V, and W/L = 10. Find the drain current in the following cases: PROBLEMS 5.10 Consider a CMOS process for which Lmin = 0.25 μm, 2 tox = 6 nm, μn = 460 cm /V · s, and Vt = 0.5 V. (a) v GS = 2.5 V and v DS = 1 V (b) v GS = 2 V and v DS = 1.5 V (a) Find Cox and k . n (c) v GS = 2.5 V and v DS = 0.2 V (b) For an NMOS transistor with W/L = 20 μm/0.25 μm, (d) v GS = v DS = 2.5 V calculate the values of VOV , VGS , and VDS min needed to operate the transistor in the saturation region with a dc *5.15 This problem illustrates the central point in the current ID = 0.5 mA. electronics revolution that has been in effect for the past four (c) For the device in (b), find the values of VOV and VGS decades: By continually reducing the MOSFET size, we are required to cause the device to operate as a 100- resistor able to pack more devices on an IC chip. Gordon Moore, for very small v DS . co-founder of Intel Corporation, predicted this exponential growth of chip-packing density very early in the history of 5.11 A p-channel MOSFET with a threshold voltage Vtp = the development of the integrated circuit in the formulation −0.7 V has its source connected to ground. that has become known as Moore’s law. (a) What should the gate voltagebe for the device to operate The table on the next page shows four technology with an overdrive voltage of VOV = 0.4 V? generations, each characterized by the minimum possible (b) With the gate voltage as in (a), what is the highest voltage MOSFET channel length (row 1). In going from one allowed at the drain while the device operates in the generation to another, both L and tox are scaled by the same saturation region? factor. The power supply utilized VDD is also scaled by the (c) If the drain current obtained in (b) is 0.5 mA, what would same factor, to keep the magnitudes of all electrical fields the current be for VD = −20 mV and for VD = −2V? within the device unchanged. Unfortunately, but for good reasons, Vt cannot be scaled similarly. 5.12 With the knowledge that μp = 0.4 μn , what must be Complete the table entries, noting that row 5 asks for the relative width of n-channel and p-channel devices having the transconductance parameter of an NMOS transistor with equal channel lengths if they are to have equal drain currents W/L = 10; row 9 asks for the value of ID obtained with when operated in the saturation mode with overdrive voltages VGS = VDS = VDD ; row 10 asks for the power P = VDD ID of the same magnitude? dissipated in the circuit. An important quantity is the power 2 5.13 An n-channel device has kn = 100 μA/V , Vt = 0.7 V, density, P/A, asked for in row 11. Finally, you are asked to and W/L = 20. The device is to operate as a switch for find the number of transistors that can be placed on an IC chip small v DS , utilizing a control voltage v GS in the range 0 V fabricated in each of the technologies in terms of the number to 5 V. Find the switch closure resistance, rDS , and closure obtained with the 0.5-μm technology (n). = Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem . What value of VGS is required (i. (How?) What is the slope at v DS = 0 minimum required v DS . = Multisim/PSpice. to obtain rDS = 200 ? Find the corresponding resistance and plotting iD /kn versus v OV for v DS ≥ v OV . find the slope at a point v OV = VOV . Furthermore.5 0.18 A particular MOSFET for which Vtn = 0. *** = very challenging.17 An NMOS transistor having Vt = 0. λ = 0). plotting iD /kn versus v DS for various values of v OV .5 0.13 2 tox (nm) 10 2 3 Cox (fF/μm ) CHAPTER 5 2 4 kn (μA/V ) 2 (μn = 500 cm / V · s) 2 5 kn (mA/V ) For W/L = 10 2 6 Device area. With VGS = 1.8 V is operated in the triode region with v DS small.7 0.6 mA/V is to be operated in the saturation graphs apply equally well to the PMOS transistor by a simple region. * = difficult problem. representation of the iD −v DS and iD −v GS characteristics of the NMOS transistor. 294 Chapter 5 MOS Field-Effect Transistors (MOSFETs) PROBLEMS 1 L (μm) 0.4 9 ID (mA) For VGS = VDS = VDD 10 P (mW) 2 11 P/A (mW/μm ) 12 Devices per chip n Section 5.25 0. A (μm ) 7 VDD (V) 5 8 Vt (V) 0. In the following problems. Repeat for iD = 200 μA. when λ is not specified. it is found 5.4 0.2: Current–Voltage Characteristics of each of the iD /kn versus v DS graphs? For the iD /kn versus v OV graph.18 0. these kn (W/L) = 1. If iD is to be 50 μA.5 V and 2 both technology and device independent. D = design problem .2 V. assume it is zero.16 Show that when channel-length modulation is neglected to have a resistance rDS of 1 k. ** = more difficult.e. results in universal values obtained with a device having twice the value of W. 5. the resulting graphs are 5. That is. find the required v GS and the relabeling of variables. 21 An NMOS transistor. What are the values of kn and Vt for this v v device? D 5.4 mA at VGS = VDS = 1 V and of 0. what is the VDD device W/L ratio? What current would you expect to flow with v GS = 2 V and v DS = 0.26 = Multisim/PSpice. Clearly label your sketch.4 V. fabricated with W = 20 μm and vS 2 L = 1 μm in a technology for which kn = 100 μA/V and Vt = 0. (c) both the width and length are halved? 5. what is the largest value of v DS for which the channel remains continuous? 5.8 V. and Vt = 0. Problems 295 CHAPTER 5 5. for which Vt = 0. D = design problem . sketch iD versus v S for v S region with v DS = 50 mV.25 resistor values can be obtained? What is the available range if 5. What is the apparent 2 value of threshold voltage Vt ? If kn = 50 μA/V .26 For the circuit in Fig.5 V. Figure P5. * = difficult problem.18 μm.8 V. a two-terminal device known as a “diode-connected transistor” results. Show that (a) the i–v relationship is given by 1 W 2 i= k v − Vt 2 L vDS (b) the incremental resistance r for a device biased to operate at v = Vt + VOV is given by ∂i W r≡1 = 1 k VOV ∂v L Figure P5.24 shows such devices obtained iD from MOS transistors of both polarities.8 V. find an expression for (a) the device width is halved? v DS in terms of iD . Sketch and clearly label a graph for v DS (b) the device length is halved? versus iD . the transcon.24 5. and what is the corresponding drain current? 5.8 V. P5.0 V to 4. what range of Figure P5.22 For an NMOS transistor.1 mA at VGS = VDS = 0. a drain PROBLEMS (a) (b) current of 2 mA is required of a device of minimum length of 0.25. v GS = 1 V and 50 μA for v GS = 1. P5.26.0 V to 1. is found to conduct 25 μA for varying from 0 to VDD .23 An NMOS transistor. operating in the linear-resistance 5. is to be operated at very low values of v DS as a linear resistor.24 When the drain and gate of a MOSFET are connected together.20 For a particular IC-fabrication process. 2 ductance parameter kn = 400 μA/V . *** = very challenging.25 For the circuit in Fig.19 A particular n-channel MOSFET is measured to have a i i drain current of 0.1 V? If the device is operated at v GS = 2 V. ** = more difficult.8 V. In an application in which v GS = v DS = Vsupply = 1. at what value of v DS will the drain end of the MOSFET channel just reach pinch-off. What value of channel width must the design use? Figure P5. For v GS varying from 1. iD operating with v GS in the range of 1.5 V. 5 d +1.28 The NMOS transistor in Fig.0 f +1.0 +2. gate.5 0 e 0 +2.0 +0. Sketch and clearly label iD versus v G Assume that the nominal value of Vt is 0.0 +1. * = difficult problem.0 V Q1 Q2 vG Figure P5.5 +1.29 = Multisim/PSpice.5 +1.4 V and the maximum resulting mismatch in the drain currents? 2 kn (W/L) = 1 mA/V .5 V iD ID1 ID2 1.6 V. table entries.29 Figure P5. 296 Chapter 5 MOS Field-Effect Transistors (MOSFETs) PROBLEMS Voltage (V) Case VS VG VD VGS VOV VDS Region of operation a +1.27 The table above lists 10 different cases labeled (a) to 5. ** = more difficult.28 Figure P5.5 0 0 i −1. You are required to complete the mum possible mismatch in their W/L ratios of 3%. You can do this because the MOSFET (b) If the two devices are matched except for a maximum is a symmetric device.5 +2.8 V.0 CHAPTER 5 b c +1. possible mismatch in their Vt values of 10 mV.5 *5. D = design problem .0 +1.0 0 0 h −1. Note that if you encounter a case for which v DS what is the maximum resulting mismatch in the drain is negative.0 +2. case the voltages at the source. with v G varying in the range 0 to +1.0 0 +1.0 +1. and drain (relative to the (a) If the two devices are matched except for a maxi- circuit ground) are specified.0 g −1.28 has Vt = 0. you should exchange the drain and source before currents? solving the problem. 1V 2. what is 5.0 +1. P5. Give equations for the various portions of the resulting graph.0 +2. *** = very challenging.0 j +0.5 +2. In each saturation at equal VGS and VDS .29 shows two NMOS transistors operating in (j) for operating an NMOS transistor with Vt = 1 V.0 +1. If the two drain currents are to be matched 0. what percentage two currents is 1%).5 μm. Complete the table entries.5 μm and W = 15 μm. 0 V. What dimensional change can be made to solve the problem? What is the new device MOS 1 2 3 4 length? The new device width? The new W/L ratio? What is VA for the standard device in this IC? The new device? λ (V−1 ) 0. v SD .34 An NMOS transistor is fabricated in a 0.02 VA (V) 20 100 D 5. P5. For operation at lowered to +2 V.29 with both transis- correspond? tors perfectly matched but with the dc voltage at the drain of Q1 5. If a particular device for which L is 1. b. Find corresponding signed values for v GS . *** = very challenging. and kp (W/L). in ID (mA) 0. about 15 of that needed.52 mA for v DS = 2 V.36 Consider the circuit in Fig. and –5 V.v DS = 4 V. 5. an NMOS device with W/L of 10 which describes characteristics of suitably biased NMOS operating at 200 μA is found to have an output resistance of transistors: 100 k. what does the drain current become if 5.35 If in an NMOS transistor. the maximum difference allowed between the In each case. VS VG VD VSG |VOV | VSD Region of operation a +2 +2 0 b +2 +1 0 c +2 0 0 d +2 0 +1 e +2 0 +1.03 V . Also. If L = 1.1 which the minimum channel length is 0. factor of 2? +2 V. and having kn = 200 μA/V and VA = 20 V/μm of channel length. find VA and λ.5 V and VDS = 2 V.40 The table below lists the terminal voltages of a PMOS this operating point. What values of ro . d.37 Complete the missing entries in the following table. Problems 297 CHAPTER 5 5.39 A p-channel transistor for which Vt = 0. +1 V. find the value of ro at 5.5 μm operates in saturation at v DS = 1 V with a drain current of 100 μA.30 For a particular MOSFET operating in the saturation 5.0 V.5 f +2 0 +2 = Multisim/PSpice. * = difficult problem.38 A PMOS transistor has kp (W/L) = 100 μA/V2 . for a change in v DS of 1 V. If VDS is increased by 1 V. by what factor does ro change? and 0. c.32 In a particular IC design in which the standard 5. channel length is 1 μm.5 0. and λ = –0.1 mA and 1 mA. and f.8 V and VA = 2 40 V operates in saturation with v GS = 3 V.33 For a particular n-channel MOS technology. both W and L are quadrupled region at a constant v GS . The gate is connected to ground represent? What can be done to reduce the percentage by a and the source to +5 V.e. Vt . the associated ro (k) 25 100 500 −1 value of λ is 0. λ. D = design problem . Find the value v DS . VA . what is the minimum required value of PROBLEMS change in drain current would you expect? VA ? If the technology is specified to have VA = 100 V/μm. what are the expected output resistances? within 1% (i. what is the minimum channel length the designer must use? D 5.31 A particular MOSFET has VA = 20 V. Vt = v DS is raised to 5 V? What percentage change does this −1. of ID that results when the device is operated with an overdrive voltage of 0.02 V−1 .5 mA for v DS = 1 V and VOV is halved.5-μm process 5. iD = 3 mA. Find the drain current for v D = +4 V. e. ** = more difficult. and λ D 5. VA . The transistor corresponding change in ID ? has Vtp = −1 V. v SG . iD is found to be 0. what is the transistor in six cases.. labeled a. I in μA. Find the voltages V1 .25 V current source I requires at least 0.1 mA. V3 . and V4 . are measured in operation. If Vt = 0.43 V3 have the same values of Vt . Moreover.5 V. V3 . Specify the values of v G at which the device changes modes 2.43 All the transistors inthe circuits shown in Fig. For each transistor. 298 Chapter 5 MOS Field-Effect Transistors (MOSFETs) PROBLEMS 5. numbered 1 to 4.5 V between its terminals (c) (d) to operate properly. Q2 CHAPTER 5 I 3 V V2 V1 Q1 I vG 1 V 1. with V in volts.43 Case Transistor VS VG VD ID Type Mode μCox W/L Vt a 1 0 1 2. and V4 become? moves through all of its three possible modes of operation. V4 *5. λ is VGS = Q3 I negligibly small.41 (a) (b) 2. D = design problem .41 The PMOS transistor in Fig. what do V1 . the transistor latter limiting situation. as shown in the table at the bottom of the page. Assume λ = 0. k . ** = more difficult. V2 . what is the largest resistor that can be placed in series with each MOSFET source while ensuring Figure P5. * = difficult problem.5 400 b 2 5 3 −4. how large a resistor can be inserted in series with each drain while maintaining saturation? If the 1. V2 . P5. As saturated-mode operation of each transistor at ID = I? In the the gate voltage v G is varied from +3 V to 0 V.5 450 c 3 5 3 4 200 3 5 2 0 800 d 4 −2 0 0 72 4 −4 0 −3 270 = Multisim/PSpice.5 V 1 V 1 V of operation. find the values of I Q4 μCox W/L and Vt that apply and complete the table.5 50 2 5 2 −0.42 Various NMOS and PMOS transistors. *** = very challenging.5 V 1.5 100 1 0 1.5 V Figure P5. W/L.5 V and I = 0.25 V *5.41 has Vtp = −0.5 2. P5. All operate in saturation at ID = I and VDS = 1 V. and μCox W/L in μA/V2 . and λ. Problems 299 Section 5.3: MOSFET Circuits at DC CHAPTER 5 edge of saturation is obtained when the following condition is satisfied: Note: If λ is not specified, assume it is zero. W RD 2.5 k D 5.44 Design the circuit of Fig. P5.44 to establish a drain L current of 0.1 mA and a drain voltage of +0.3 V. The 2 MOSFET has Vt = 0.5 V, μn Cox = 400 μA/V , L = 0.4 μm, and W = 5 μm. Specify the required values for RS and RD . 1.3 V PROBLEMS 1 V RD RD Figure P5.47 RS D 5.48 It is required to operate the transistor in the circuit 1 V of Fig. P5.47 at the edge of saturation with ID = 0.1 mA. If Vt = 0.4 V, find the required value of RD . Figure P5.44 D 5.49 The PMOS transistor in the circuit of Fig. P5.49 2 has Vt = −0.5 V, μp Cox = 100 μA/V , L = 0.18 μm, and λ = 0. Find the values required for W and R in order to establish 5.45 The NMOS transistor in the circuit of Fig. P5.44 has a drain current of 180 μA and a voltage VD of 1 V. 2 Vt = 0.4 V and kn = 4 mA/V . The voltages at the source and the drain are measured and found to be −0.6 V and +0.2 V, respectively. What current ID is flowing, and what 1.8 V must the values of RD and RS be? What is the largest value for RD for which ID remains unchanged from the value found? D 5.46 For the circuit in Fig. E5.10, assume that Q1 and Q2 are matched except for having different widths, W1 and 2 W2 . Let Vt = 0.5 V, kn = 0.4 mA/V , L1 = L2 = 0.36 μm, W1 = 1.44 μm, and λ = 0. (a) Find the value of R required to establish a current of 50 μA in Q1 . Figure P5.49 (b) Find W2 and R2 so that Q2 operates at the edge of saturation with a current of 0.5 mA. D 5.50 The NMOS transistors in the circuit of Fig. P5.50 2 5.47 The transistor in the circuit of Fig. P5.47 has kn = have Vt = 0.5 V, μn Cox = 250 μA/V , λ = 0, and L1 = L2 = 2 0.4 mA/V , Vt = 0.4 V, and λ = 0. Show that operation at the 0.25 μm. Find the required values of gate width for each of Q1 = Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem 300 Chapter 5 MOS Field-Effect Transistors (MOSFETs) PROBLEMS and Q2 , and the value of R, to obtain the voltage and current the drain current is 0.5 mA and the drain voltage is +7 V. If values indicated. the transistor is replaced with another having Vt = 1.5 V with 2 kn (W/L) = 1.5 mA/V , find the new values of ID and VD . Comment on how tolerant (or intolerant) the circuit is to 2.5 V changes in device parameters. D 5.53 Using a PMOS transistor with Vt = −1.5 V, kp CHAPTER 5 2 (W/L) = 4 mA/V , and λ = 0, design a circuit that resembles 0.5 mA that in Fig. 5.24(a). Using a 10-V supply, design for a 1.8 V gate voltage of +6 V, a drain current of 0.5 mA, and a drain voltage of +5 V. Find the values of RS and RD . Also, find the values of the resistances in the voltage 1.0 V divider feeding the gate, assuming a 1-μA current in the divider. 5.54 The MOSFET in Fig. P5.54 has Vt = 0.4 V, kn = 2 500 μA/V , and λ = 0. Find the required values of W/L Figure P5.50 and of R so that when v I = VDD = +1.3 V, rDS = 50 and v O = 50 mV. D 5.51 The NMOS transistors in the circuit of Fig. P5.51 2 have Vt = 0.5 V, μn Cox = 90 μA/V , λ = 0, and L1 = L2 = VDD L3 = 0.5 μm. Find the required values of gate width for each of Q1 , Q2 , and Q3 to obtain the voltage and current values indicated. R vO 2.5 V vI 90 A 1.5 V Figure P5.54 0.8 V 5.55 In the circuits shown in Fig. P5.55, 2transistors are characterized by Vt = 1 V, k W/L = 4 mA/V , and λ = 0. (a) Find the labeled voltages V1 through V7 . Figure P5.51 (b) In each of the circuits, replace the current source with a resistor. Select the resistor value to yield a current as close to that of the current source as possible, while 5.52 Consider the circuit of Fig. 5.24(a). In Example 5.5 using resistors specified in the 1% table provided in 2 it was found that when Vt = 1 V and kn (W/L) = 1 mA/V , Appendix J. = Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem Problems 301 5 V CHAPTER 5 5 V 5 V 2 k 5 V V2 V1 V2 PROBLEMS 2 mA V1 V3 10 A 100 A 2 mA (a) (b) 5 V (a) (b) 5 V 5 V 5 V 10 A V3 2 mA V4 1 mA V4 V6 (c) (d) V5 V7 5 V 1.5 k 2 mA 1 mA 400 k 5 V V5 V6 (c) (d) Figure P5.55 5.56 For each of the circuits in Fig. P5.56, find the labeled 2 (e) (f) node voltages. For all transistors, kn (W/L) = 0.5 mA/V , Vt = 0.8 V, and λ = 0. Figure P5.56 continued = Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem 302 Chapter 5 MOS Field-Effect Transistors (MOSFETs) 5 V 10 V PROBLEMS 5 V VSG 2.2 k VSD V7 V8 400 k R CHAPTER 5 5 V (g) (h) I Figure P5.56 continued 5.57 For each of the circuits shown in Fig. P5.57, find the Figure P5.58 labeled node voltages. The NMOS transistors have Vt = 0.9 V and kn (W/L) = 1.5 mA/V . 2 5.59 For the circuits in Fig. P5.59, μn Cox = 3 μp Cox = 270 μA/V , Vt = 0.5 V, λ = 0, L = 1 μm, and W = 3 μm, 2 5V unless otherwise specified. Find the labeled currents and voltages. 5V 3V 3V 2.5 V 1k V3 Q1 Q1 I1 I3 V1 V4 V4 Q2 V2 Q2 V2 V5 1k 1k (a) (b) 3V 2.5 V (a) (b) Figure P5.57 W = 9 μm *5.58 For the circuit in Fig. P5.58: I6 V5 (a) Show that for the PMOS transistor to operate in saturation, the following condition must be satisfied: IR ≤ | Vtp | (b) If the transistor is specified to have |Vtp | = 1 V and 2 kp = 0.2 mA/V , and for I = 0.1 mA, find the voltages VSD and VSG for R = 0, 10 k, 30 k, and 100 k. (c) Figure P5.59 = Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem Vt = 2 −1 (a) (W/L)1 = (W/L)2 = 20 −2 V. and 5. P5.) Sketch the i−v relationship for the 2 case: Vt = −2 V and kn (W/L) = 2 mA/V . V3 i 200 A v Figure P5. cases: 5.66 For a particular depletion-mode NMOS device. V2 . Problems 303 *5. For γ = 0. the i−v relationship is given by 20 k 20 k 2 1 i = kn (W/L) v − 2Vt v for v ≥ Vt 2 V1 V2 1 2 i = − kn (W/L)Vt for v ≤ Vt 2 Q1 Q2 (Recall that Vt is negative.61 In the circuit of Fig.63 A p-channel transistor operates in saturation with its PROBLEMS 1/2 source voltage 3 V lower than its substrate. (b) If Vt decreases by 2 mV for every °C rise in temperature. *5.60.60 1 V is operated at VGS = 5 V. Find V2 and I2 . kn W/L = 200 μA/V .67.5(W/L)2 = 20 ated at v GS = 0.67 = Multisim/PSpice. 3 V.7 V.6 V. find Vt . an n-channel MOSFET W = 10 μm. and Vt0 = −0.75 V. If the gate oxide thickness is increased by a factor of 4.e.02 V . Find the region of operation and the drain Vt = 0.4: The Body Effect and Other Topics CHAPTER 5 Vt = 1 V. D = design problem .5 V and 2φf = 0. 2 V. and 10 V? What does each of these currents become if the device width is doubled with L the same? With L also doubled? 2. 3 V.2%/°C when the NMOS transistor with Vt = Figure P5. * = difficult problem. and 5 V. what does the threshold voltage become? 5 V 5. derive an expression for the per unit change in iD V2 per °C ∂iD /iD /∂T in terms of the per unit change in kn per °C ∂kn /kn /∂T . and V3 for each of the following channel-length-modulation effect. If Vt0 is nominally if Q3 and Q4 are made to have W = 100 μm? 1/2 1.61. find the range of Vt that results if γ = 0. When oper- (b) (W/L)1 = 1. μn Cox = 50 μA/V2 . and the process transconductance parameter kn = current for v D = 0. P5.5 V *5.62 In a particular application.5 V .67 Neglecting the channel-length-modulation effect. show that for the depletion-type NMOS transistor of Fig.60 For the devices in the circuit of Fig. what is the drain current that flows for v DS = 1 V.65 A depletion-type n-channel MOSFET with kn W/L = 2 2 mA/V and Vt = −3 V has its source and gate 5. 2φf = 0. L = 1 μm. find the temperature coefficient of kn that results in iD decreasing by 0. Neglect the 2 125 μA/V . 1 V. ** = more difficult.1 V.7 V. the temperature coefficient of Vt in Q3 Q1 V/°C ∂Vt /∂T . P5.61 Figure P5. How do these values change operates with VSB in the range 0 V to 4 V. 5.64 (a) Using the expression for iD in saturation and Q4 Q2 neglecting the channel-length modulation effect (i. Section 5. and λ = 0. let I2 λ = 0).0 V. transistors Q1 and Q2 have grounded. *** = very challenging. Find V1 . and VGS and Vt .. λ = 0. 6. For each case. Find β and α for this device.8 In a particular BJT.9 Find the values of β that correspond to α values of 0. have collector currents of 0.7 0 −0. Note that equal to that provided by the smaller transistor at v BE = if a particular parameter value is not specified in the problem 700 mV? Assume active-mode operation in all cases. 10. 20. Assume active-mode operation. and the 5 1.7 0.12 An npn transistor of a type whose β is specified to range times larger.6 6. a typical Section 6. reference terminal to which the black (negative) probe of the 6.70 V? What is its base–emitter voltage for 3 −0. 0 indicates the 0.4 μm.11 Show that for a transistor with α close to unity. for a transistor whose nominal β is 100. 0. fabricated with the same technology if α changes by a small per-unit amount (α/α). *6.8 0. Case E B C Mode 6. 0. 6 0 0 5.1 The terminal voltages of various npn transistors are These typical devices have vastly different junction areas and measured during operation in their respective circuits with base width.99.0 iC = 5 μA? 4 −0.98.0 collector current is 800 μA.5 Find the collector currents that you would expect for important issues such as allowable signal swing and amplifier operation at v BE = 700 mV for transistors for which IS = nonlinear distortion.7 0. 0.3 2. What current will it 2 0 0. voltmeter is connected. where the entries are in volts. *** = very challenging. 0. 6.3 In a particular technology. and 0. and 1000.999. the but having different junction areas. the base current is 10 μA. ** = more difficult. What are the β α β relative junction areas? β α 6. and to investigate 6. when operated at a corresponding per-unit change in β is given approximately by base-emitter voltage of 0. * = difficult problem. and a current of 10 μA injected into the base–emitter voltage of the latter transistor at iC = 1 mA? base.2 Two transistors. Instructions to assist in setting up PSPice 10−13 A and IS = 10−18 A.4 μm × 0.95.5.5 mA and 2 mA. what is the v BE required to provide a collector current be found in the corresponding files on the website.0 6. identify the mode of 2. what do you expect the difference in their Problems identified by the Multisim/PSpice icon are v BE values to be? intended to demonstrate the value of using SPICE simulation to verify hand analysis and design.76 V at a collector current of 5 mA. What is the maximum power dissipated in the 6. For the transistor with the larger and Multisim simulations for all the indicated problems can EBJ. 0. For our purpose here we wish to determine the the following results: v BE required to establish a collector current of 1 mA in each of the two typical devices. What percentage change in its α value corresponding to a drop in is the corresponding saturation current? For a transistor in its β of 10%.10 Find the values of α that correspond to β values of 1. D = design problem . we contrast two BJT integrated-circuit fabrication technologies: For the “old” technology.995. PROBLEMS Computer Simulations Problems transistors are operated in the active mode and conduct equal collector currents. what is the saturation current? What current from 50 to 300 is connected in a circuit with emitter grounded. 100. the same technology but with an emitter junction that is 32 6.6 In this problem.75 V. a small BJT operating at Now.0 5. Find IS for each device.4 Two transistors have EBJ areas as follows: AE1 = transistor? (Note: Perhaps you can see why this is a bad way 200 μm × 200 μm and AE 2 = 0. find the v BE = 30VT conducts a collector current of 200 μA. that can result.8.) = Multisim/PSpice.9. Calculate the range of collector and emitter currents Assume active-mode operation in all cases.1: Device Structure and Physical npn transistor has IS = 2 × 10−15 A. 50.7 0 1. If the two to establish the operating current in the collector of a BJT. and for the “new” Operation technology. 500. In this table. statement. 6. you are to make a reasonable assumption. a typical npn transistor has IS = 2 × 10−18 A. will this transistor conduct at v BE = 30VT ? What is the collector at + 10 V.1 conduct at v BE = 0.7 Consider an npn transistor whose base–emitter drop is 1 0 0. 200. operation of the transistor. VCEsat . Present your results in tabular 6.21 Use Eqs.7 V. Also find the forward current each junction in the active mode with v BE set to 0. iBC . Let IS = ing in the active mode with iE = 1 mA indicate base currents of 10−15 A.700 V. 0.16) to show that an npn value as well as α. 20 μA.2 V). iBE .14). transistor operated in saturation exhibits a collector-to-emitter voltage.14 Measurements made on a number of transistors operat. 0.20 We wish to investigate the operation of the npn 6. given by . If the transistor is operated current of 1 mA. (6. iC . (6. calculate the missing current *6.15 Measurements of VBE and two terminal currents taken form. β = 100.15). find iC . and iC /iB . v BE = 0. For each of CHAPTER 6 10 μA.4 V. For each. find v BC . 6. Also find v CE that results in iC = 0.9. and 0. on a number of npn transistors operating in the active mode are tabulated below. *6. β. transistor in saturation using the model of Fig. β. and iE . and IS as indicated by the table. and 50 μA. 356 Chapter 6 Bipolar Junction Transistors (BJTs) 6. and (6.13 A BJT is specified to have IS = 5 × 10−15 A and β that PROBLEMS and across CBJ when each is forward biased and conducting a falls in the range of 50 to 200. iB . For each device.5 V. find the expected would conduct when forward biased with 0.3 V. and ISC /IS = 100. three values of v CE (namely. and α. range of iC . iB . 000 1. find is said to have β = 10. to have β = 50 and IS = 5 × 10−15 A.11 a 2-k resistor. 5. what voltage base current. results at the emitter? What does the collector current become D 6. the emitter current. the base is connected to a current source that pulls 10 μA out of the base terminal. If IS = 10−15 A.2-k resistor. 6.5(b). D = design problem . an emitter current of 5 A. 6.0 V. 6. 6.11(b) IS applied to a transistor having IS = 10−14 A and β = 50.020 0. Present your results in a table.70 V and 8. What do you expect v EB to become at iC = 10 mA? the case of a transistor for which the base is connected to At iC = 100 mA? ground. what are its base and collector currents? the voltages at the emitter and the collector and calculate the In which direction do they flow? If IS = 10−15 A. what base current is required? 6. the emitter with the polarity so that current is drawn out of and a 1-mA current is injected into its emitter. * = difficult problem.16 When operated in the active mode. 6. Use these data to create specific transistor models and the base voltage.6(b). 6. collector at –2. *** = very challenging.22 Consider the pnp large-signal model of Fig.5(a) to (d).10 Use this relationship to evaluate VCEsat for β forced = 50. the collector is connected to a 5-V dc source through 6.000 10. find the voltage drop across EBJ junction area of this transistor with that of a small-signal = Multisim/PSpice.24 A pnp transistor modeled with the circuit in Fig.17 Using the npn transistor model of Fig. Transistor a b c d e ISC 1 + β forced VCEsat = VT ln VBE (mV) 700 690 580 780 820 IS 1 − β forced /β IC (mA) 1. iB = 10 μA.25 A pnp power transistor operates with an a collector-to-emitter voltage VCE of 1 V. and 6.7 V at a collector current 6.00 times that of the EBJ.8 V. a particular npn BJT the collector is connected to a negative supply of −5 V via a conducts a collector current of 1 mA and has v BE = 0. IB (μA) 10 5 120 1050 and 1 for a transistor with β = 100 and with a CBJ area 100 IE (mA) 1. find the collector voltage. and VEB = 0.5(d).) and RC that will establish a collector current IC of 0.18 Consider an npn transistor operated in the active if a transistor with β = 1000 is substituted? (Note: The fact mode and represented by the model of Fig.235 75. If the transistor the emitter terminal. 6. consider of 1 mA. 10.19 An npn transistor has a CBJ with an area 100 times that What is IS for this transistor? Compare the emitter–base of the EBJ. Let the that the collector current changes by less than 10% for a large transistor be connected as indicated by the equivalent circuit change in β illustrates that this is a good way to establish a shown in Fig. α β 6. It is required to calculate the values of RB specific collector current.23 A pnp transistor has v EB = 0. If the emitter is connected to ground. of the form shown in Fig. If β = 100 and IS = 5 × 10−15 A.5 mA and 6. and a 2-mA current source is connected to (b) is connected with its base at ground. The BJT is specified emitter-to-collector voltage of 5 V. For β = 20. ** = more difficult. P6.3 V 45 k + 3.4 k I6 5k 20 k 3k (a) (b) (c) (d) Figure P6. *** = very challenging.29 = Multisim/PSpice.28.5 provides four possible large-signal have very large β.0 V 200 k 27 k⍀ 2k 750 ⍀ 1.2: Current–Voltage Characteristics CHAPTER 6 much larger is it? 6. with the results indicated in the figure. Some measurements have been made on equivalent circuits for the npn transistor.70 V. the missing two. * = difficult problem. Problems 357 transistor that conducts iC = 1 mA with v EB = 0. only two equivalent these circuits. Supply values of the other labeled voltages and currents. 5.28 7V 6. give the labeled voltages as indicated.28 For the circuits in Fig.29 Measurements on the circuits of Fig. How Section 6.26 While Fig. 6.11. P6.9.6 k 2 5k V3 9.5 k (a) (b) (c) Figure P6. 6. D = design problem . transistor. Find the value of β for each equivalent circuit of a pnp transistor in saturation.7 V 2. ** = more difficult. 6. assume that the transistors 6.27 By analogy to the npn case shown in Fig. 6.29 produce PROBLEMS 6. Find the circuits for the pnp transistor are provided in Fig.1 k I5 15 k V7 V4 4V V2 0V 0. 64 V at IE = 0.1 mA.30 A very simple circuit for measuring β of an npn PROBLEMS D 6.5 V RC RC M IC VC RE Figure P6. use approximate calculations neglect for our purposes here.7 k 2k 2.32 Design the circuit in Fig. collector voltages and currents.5 V Figure P6. Use β = 50.5 V at the collector. The transistor v EB = 0.2 are 5. VCC 1. D = design problem . a resistor current of 1 mA? Now.35 = Multisim/PSpice. find the emitter. what value of RC would establish collector current and collector voltage that are likely to result. In a particular design. base.8 V reading is 1/5 of full scale? 1/10 of full scale? at iC = 1 mA.34 Design the circuit in Fig.5 mA in the emitter and a voltage of −0.7 V and α 1) to determine the values of VBE = 0. * = difficult problem. VBE 0.8 V independent of current level.2 mA and VC = 0.5 V Figure P6. ** = more difficult. of 0. To what value can RC be increased while the collector current remains unchanged? 2.33 Examination of the table of standard values for resis- transistor is shown in Fig. P6.7 k 2k RC 1.31 Repeat Exercise 6. P6.35 For each of the circuits shown in Fig.5 V β = 100.g.5 V RE Q1 Q2 2. The transistor exhibits v BE of 0. to what value of β does a CHAPTER 6 D 6.8 k.5 V.. and β = 100. 358 Chapter 6 Bipolar Junction Transistors (BJTs) 6. 6.35.1 k 50-μA full scale and relatively low resistance that you can and 6.30 1.30.5 V 1.7 V at IE = 1 mA. P6.34 6.32 Figure P6. P6.32 to establish a current but assume VBE = 0. M is a current meter with a values to those found in the design of Example 6.13 for the situation in which the power supplies are reduced to ±2.5 V.34 to establish IC = meter reading of full scale correspond? What is β if the meter 0.5 V (a) (b) 2. Assuming that the transistor has (e. and 1. VCC tors with 5% tolerance in Appendix J reveals that the closest is provided by a 9-V battery. For these values. and D 6.5 V 1. *** = very challenging. 5 mA at 20°C has an emitter–base voltage of transistor? For operation at 10 mA. P6. and 0. iC .2 mA? What is the value of the Early 700 mV and at v BE = 500 mV.1 mA. what currents flow in R1 and R2 ? What voltage PROBLEMS would you expect at node E? Noting that the temperature coefficient of v BE for IE constant is −2 mV/°C. resistance become? (a) What does v EB become if the junction temperature rises 6.36 The current ICBO of a small transistor is measured to be 10 nA at 25°C. what is its to 50°C? output resistance at 1 mA? At 100 μA? (b) If the transistor is operated at a fixed emitter–base voltage 6.38 A BJT whose emitter current is fixed at 1 mA has a 6.18) to plot iC versus v CE for an npn transistor CHAPTER 6 −15 having IS = 10 A and VA = 100 V.7 k would you expect at node E? Clearly state any simplifying assumptions you make.42. *** = very challenging. 6.45 Measurements of the iC –v CE characteristic of a of 700 mV. and iE become? If I the base lead is open-circuited while the emitter is connected to ground. ** = more difficult. and at 25°C v BE = 680 mV at iE = 1 mA.6 k TC of v E ? For an ambient temperature of 75°C. Figure P6.72. what voltage 4. To what value of output resistance does this 6. What current flows for v BE = 0. what is the 5.1 mA at v CE = 5 V and that iC = 1.42 6. Provide curves for v BE = 0.40 Consider a transistor for which the base–emitter voltage iC = 1.8 k 6.39 A particular pnp transistor operating at an emitter correspond? What is the value of the Early voltage for this current of 0.8 × 10 .0 V 1.7 V at 10 mA.2 k for v CE up to 15 V.65.19(a) by a current source representing ICBO . the iC –v CE characteristic has a slope voltage would you expect at 0°C? At 100°C? −5 of 0. What base–emitter 680 mV and IC = 1 mA. what do the terminal currents iB .5 V? What is the corresponding value of iC near saturation? At what Evaluate the ratio of the slopes of the iC –v BE curve at v BE = value of v CE is iC = 1.3 mA at v CE = 15 V.73. D = design problem .43 For a particular npn transistor operating at a v BE of base–emitter voltage of 0. 1. what do you expect ICBO to become? R1 6. (c) (d) Figure P6. what emitter current flows at 20°C? At 50°C? small-signal transistor operating at v BE = 710 mV show that 6.44 For a BJT having an Early voltage of 50 V. Show the characteristics 10 k 8. and the collector is connected to a positive supply. (6. find the emitter and collector currents.74 volts. drop is 0. current source I is 1.5 V. 0.70. If the temperature of the device is raised to 125°C.41 Use Eq. what would the output 692 mV. Problems 359 3V 3V 6. * = difficult problem.37 Augment the model of the npn BJT shown in Fig.70 V at 25°C. 0.5 V *6. At 25°C Q3 Q4 with β = 100. The large ratio confirms the voltage for this transistor? What is the output resistance that point that the BJT has an “apparent threshold” at v BE 0.35 continued R2 68 k 6. corresponds to operation at v BE = 710 mV? = Multisim/PSpice.42 In the circuit shown in Fig. In terms of this addition. 0. Assume E that ro is very large and thus can be neglected. Figure P6. P6. Section 6. 6.50 has β = 50. 6. D = design problem . P6.50 The pnp transistor in the circuit in Fig.51 The transistor in the circuit of Fig.51 has a very high β. VC what collector current results? Assume VA = 100 V. It is found that when v CE is held constant.47 A BJT operating at iB = 10 μA and iC = 1. P6.51 has a very dissipated in the circuit. Also. What values of VE and VC result? At what for the transistor to operate at the edge of saturation? value of VB does the emitter current reduce to one-tenth of = Multisim/PSpice.48 let VCC = 10 V.0 V. The BJT has β = 50.52 The transistor in the circuit of Fig. 6.0 mA undergoes a reduction in base current of 1. * = difficult problem. (c) deep in saturation with β forced = 10.53 for VB at –1 V. the corresponding reduction in RB 10 k collector current is 0. 6.49 Consider the circuit of Fig. Find the value of VBB that results in the transistor operating (a) in the active mode with VC = 2 V. Assume that β β forced and VC . Use VB for which the transistor operates in saturation with a 1% resistors (see Appendix J).50 (b) at the edge of saturation. design the circuit to high β. 6. forced β of 2. P6. 360 Chapter 6 Bipolar Junction Transistors (BJTs) 5V PROBLEMS 6. P6.19 for the npn case. and (c) 0 V. Find VE and VC for VB (a) +2.3: BJT Circuits at DC Assume VBE 0.46 Give the pnp equivalent circuit models that correspond to those shown in Fig.08 mA.51 of Fig.48 for the case VBB = VCC . (b) +1. VCC 3V VBB IC RC 1k VC VB RB VC VE Figure P6.0 μA.21 to derive an expression for β forced in terms of VCC and RB /RC . use the equivalent circuit Figure P6. 0 V. What are the values of β and the CHAPTER 6 incremental β or β ac that apply? If the base current is increased from 10 μA to 12 μA and v CE is increased from 8 V to 10 V. and RB = 10 k. To what value should RB be increased in order is very high. For VCC = 5 V. ** = more difficult. Find the highest value of VB for which the transistor obtain operation at a forced β as close to 10 as possible while still operates in the active mode. *** = very challenging.7 V.7 V. find the value of limiting the power dissipation to no larger than 20 mW. Also derive an expression for the total power 6.48 For the circuit in Fig. If the BJT is saturated. P6. and +1 V. 6. 1k 6. RC = 1 k.48 1k D *6.53 Consider the operation of the circuit shown in Show that the BJT is operating in the saturation mode and find Fig. 51 with the base just at the edge of conduction? (v BE = 0.2 V. P6. 6. ** = more difficult. What are the values 50 k VC of VE and VC for VB = 0 V? For what value of VB does the transistor cut off? Saturate? In each case.56 A single measurement indicates the emitter voltage of 1k the transistor in the circuit of Fig.5 mA and VBC = 1 V. What exact values VB of RE and RC would be needed? Now.54 calculated? = Multisim/PSpice.58 In the circuit shown in Fig.56 4 mA VC D 6. if the BJT β = 100. * = difficult problem.56 to be 1. Design for a 0. design the voltage divider to VE correspond? Find the value of VB for which the transistor obtain VB = 1. VC β. P6..5 V at the edge of conduction. Problems 361 its value for VB = 0 V? For what value of VB is the transistor CHAPTER 6 D 6. What values of resistors VE have you chosen? What are the values of IE and VBC that result? 2 mA 1k 6. IC . what values of VE 5k and VC result? 3V +5 V Figure P6. analyze the circuit to determine the collector current and the collector PROBLEMS 3V voltage. and α ? (Note: Isn’t it surprising what a little measurement can lead to?) VB VE 3V 1k 5k 3V VE Figure P6. that provided in Appendix J) to select suitable practical values. VC .5 V) What values voltage VB obtained using a voltage divider across the 3-V of VE and VC correspond? For what value of VB does the supply.. D = design problem . P6. *** = very challenging.0 V. If RB is raised to 100 k. what –5 V value of β would return the voltages to the values first Figure P6. assume α 1 and v BE = 0.54.55 Consider the circuit in Fig.54 For the transistor shown in Fig. what voltages result? With RB = 100 k.7 V. Find the values of VB . IE .1-mA current in the operates in saturation with a forced β of 2. what are VB . Now.57 Design a circuit using a pnp transistor for which α 1 using two resistors connected appropriately to ±3 V 1k so that IE = 0. P5. Assuming the transistor β to be very large (i. and VC .e. Under the assumption that VBE = 0.g. the transistor has β = 40. transistor reach the edge of saturation? What values of VC and ignoring the base current). IB . VE . voltage divider.58. consult a table of standard 5% resistor values (e.53 VB 6. 58. and VC for RB = 100 k. Let β = 100. and 1 k. and verify that the 3V transistor is operating in the active mode. find values for the labeled node voltages and branch currents. * = difficult problem.7 k 0. the transistor has β = 50.75 V 43 k 110 k V6 V5 V9 4.61.60 For the circuit in Fig. P6. Find the values of VB . D = design problem . VE . find VB . and VC . Assume β to be very RE high.6 k 6. *** = very challenging.59 In the circuit shown in Fig. P6.58 V1 4.2 k VE CHAPTER 6 3V 3V VB RB 20 k VC 3. P6.60 Figure P6. VE . ** = more difficult.2 k V7 V8 0. What is the largest value that RC can have while the transistor remains in the (a) (b) active mode? 6.6 k RC V2 V3 2. 3V 3V 3.7 k 10 k 3V 3V (c) (d) Figure P6.6 k 3.61 = Multisim/PSpice.60.2 k 43 k 3V I4 Figure P6. 362 Chapter 6 Bipolar Junction Transistors (BJTs) 3V PROBLEMS 6. 2.61 For the circuits in Fig.5 mA 6. 10 k. 6. the specified emitter current is obtained when β = 100 and VC1 .61 ***6. with R open-circuited change by more than 10% of its nominal value. and VC2 .64 *6. and RC to the nearest kilohm.7 V low as 50 and as high as 150. D = design problem . RE . Give the values of RB . VE1 .2 k having β = 100? Give the value of VC in the latter 180 k V11 case.65 Consider the circuit shown in Fig. * = difficult problem.65. What happens if the transistor is replaced with another 6. VE2 . Find all the labeled node voltages and branch resembles that in Fig. note diodes D1 and D2 are included to make design (and D **6. P6. Also. currents. the β value can be as (more on this later in the book!). First. The transistor type resistor R. find the voltages VB1 . for as large a value for RB as possible. initially with R open-circuited and then that at the extreme values of β the emitter current does not with R connected. However. V10 3V PROBLEMS V12 300 k 10 k 3V (e) Figure P6. then connected.30 but includes other features. VB2 .63 Figure P6. note voltage of −1 V appears at the collector.65 = Multisim/PSpice. Your design should ensure that independent of current. whose purpose is to provide negative feedback used has a nominal β of 100. ** = more difficult. Second.62 Repeat the analysis of the circuits in Problem 6. It using β = 100. P6. Find the value for RC to obtain VC = +2 V.64 has β = 50. Problems 363 3V CHAPTER 6 D 6.61 continued Figure P6. and β = ∞.63 It is required to design the circuit in Fig. Repeat for β = 100. Using VBE and VD = 0.64 The pnp transistor in the circuit of Fig.63 analysis) easier and to provide temperature compensation so that a current of 1 mA is established in the emitter and a for the emitter–base voltages of Q1 and Q2 . P6. design initially. What is the expected range 9V of collector current and collector voltage corresponding to the full range of β values? +5V 2k 100 80 k D2 E Q2 Q1 R D1 2k C 40 k 2k 100 –5V Figure P6. *** = very challenging. The BJTs have 9. PROBLEMS *6.3 k 3V Figure P6.66 D *6. and Q3 Figure P6. and V3 = 0. *** = very challenging.) Q2 V7 V3 Q1 Q3 V2 V5 V6 R4 R1 R6 5V Figure P6. P6. For each resistor.1 k β = 50.1 k 4. and 1 mA. and V7 .66. V6 .5 V Fig.67 Using β = ∞. V5 . design the circuit shown in 2.5 mA.5 V. (Hint: Initially.67 so that the emitter currents of Q1 .68. P6. P6. P6. respectively.5 V V1 Q1 100 k V3 Q2 V4 9. find VB and VE for v I = 0 V. find the labeled node voltages for: V5 = −2 V. Q2 .69 are specified to have a minimum β of 50. V4 .68 For the circuit in Fig.1 k V2 V5 2. for β = 100.68 5V **6. and V7 = 1 V.66 For the circuit shown in Fig. and verify the assumption. 5. and –5 V. find the values of (b) β = 100 V3 . 3V CHAPTER 6 *6.69 All the transistors in the circuits of Fig. +2 V. 364 Chapter 6 Bipolar Junction Transistors (BJTs) are 0. Find approximate R3 values for the collector voltages and calculate forced β for R2 R5 V4 each of the transistors. ** = more difficult. –2.5 mA. Now. assume all transistors are operating in saturation. 0.67 = Multisim/PSpice. * = difficult problem. select the nearest standard value utilizing the table of standard values for 5% (a) β = ∞ resistors in Appendix J. D = design problem . 69 . Problems 365 5V CHAPTER 6 5V 5V PROBLEMS 20 5V Figure P6. kn = 10 mA/V . 7. 1. reduces the allowable output signal swing amplifier? Assuming linear operation. Also.1 For the MOS amplifier of Fig. Instructions to assist in setting up PSpice saturation? What is the amplitude of the output voltage and Multisim simulations for all the indicated problems can signal that results? What gain value does the combination be found in the corresponding files on the website. and RD = 20 k. This.2 For the MOS amplifier of Fig.3 It is required to bias the MOS amplifier of Fig.1: Basic Principles for which the drain resistor RD is 20 k.5 V. (7. 2 process transconductance parameter kn is 200 μA/V . 7.5 V.5 V. what is the MOSFET’s W/L? D 7.2(a) with VDD = 5 V.16) can be written in as the transistor is replaced with another having twice the value of the transconductance parameter kn .2(a) with VDD = 5 V 2 and kn = 5 mA/V . VRD .6 Various measurements are made on an NMOS amplifier Section 7. however. First. when operated with saturated is VDD = 2 V. 7.5 V and the gate-to-source bias voltage to be 0. What is the small-signal voltage gain of this VDS . what to verify hand analysis and design. and disregarding the distortion intended to demonstrate the value of using SPICE simulation caused by the MOSFET’s square-law characteristic. 7. Then. you are to make a reasonable assumption. Assuming linear operation around allowable negative signal swing at the output? What is the the bias point. Find the where VDS is the bias voltage at the drain. the gain 2 kn = 10 mA/V . show that the largest possible negative output corresponding peak input signal? signal peak v̂ o that is achievable while the transistor remains 7. determine the ac measurements with small signals show the voltage gain to coordinates of the active-region segment (AB) of the VTC be –10 V/V. 7. Note that of these amplitudes imply? By what percentage is this if a particular parameter value is not specified in the problem gain value different from the incremental gain value statement. to be 7.4(a). find the value of ID and of the incremental gain Av at the bias point. Vt = 0. and indicates that for given values of VDD and VOV . Problems identified by the Multisim/PSpice icon are (c) For the situation in (b).4 The MOS amplifier of Fig. This expression required value of RD when VDD = 5 V.2 V and VDS = 1 V. 2 Vt = 0. is found to have a maximum small-signal voltage . What is the value of Vt for this transistor? If the [Fig. what is the maximum in the negative direction. calculated above? Why is there a difference? 7.2(b)]. dc measure- ments show the voltage across the drain resistor. point B. at VDS = 0. it is required to have the end point of the *7. What value of RD is required? If given in Eq.7 The expression for the incremental voltage gain Av VTC. what new value of RD 2 VDD − VDS is needed? Av = − VOV D 7.PROBLEMS Computer Simulation Problems Q on the transfer characteristic. and to investigate is the largest amplitude of a sine-wave voltage signal that important issues such as allowable signal swing and amplifier can be applied at the input while the transistor remains in nonlinear distortion. Also specify the coordinates of the VTC magnitude can be increased by biasing the transistor at a lower end point B.3 at point Q for which VOV = 0.7 V. 7.4(a) to obtain (b) If the amplifier is biased to operate with an overdrive maximum gain while allowing for an output voltage swing voltage VOV of 0. kn (W/L) = 1 mA/V . that is. Av 7. and (a) Find the coordinates of the two end points of the 2 2. 2 V. gain magnitude of 14 V/V. provide a table of values for Av . Find VOV and VDS for bias point Q 1 v̂ o = VDS − VOV 1+ at which a voltage gain of −12 V/V is obtained. ** = more difficult. *** = very challenging. If kn (W/L) = 1 mA/V .5 Consider the amplifier of Fig. RD = 24 k. find the coordinates of the bias point of at least ±0. * = difficult problem. points A and B on the sketch of Fig.8 Design the MOS amplifier of Fig. Let VDD = 5 V. and utilize an overdrive = Multisim/PSpice.4(b).5 V. find ID and RD for the design saturation-region segment of the amplifier transfer char- for which VDS = 1 V.5 V. and Vt = 1 V.4(a) for the case VDD = 2 5 V. 7.5 V.5 V. and the corresponding v̂ i for VDS = 1 V. 1. For VDD = 5 V and VOV = 0. v̂ o . acteristic.5 V. D = design problem . D *7. 7. 11 For the amplifier circuit in Fig.9 = Multisim/PSpice.12 Consider the CE amplifier circuit of Fig. the point at which the transistor should be biased. without v CE decreasing below 0.6 is operated with VCC = + 5 V and is biased at VCE = +1 V. For transistors that saturate at VCE = find the voltage gain. show operated with a dc supply VCC = +5 V. for find the value of VCE so that the output sine-wave signal v ce resulting from an input sine-wave signal v be of 5-mV peak Vt1 ≤ v I ≤ v O + Vt1 amplitude has the maximum possible magnitude. what W/L ratio is required for the and RC = 1 k. at what VCE should the transistor be biased to obtain maximum gain? What is the gain achieved with each of the supply iD2 voltages? (Notice that all of these gains are independent of the value of IC chosen!) Q2 D *7.4 V is required.5 μm). 7. that is. 2. 0.5.9 Figure P7.3 V. or 3.6 is to be vO designed to support relatively undistorted sine-wave output iD1 signals of peak amplitudes P volt without the BJT entering saturation or cutoff and to have the largest possible voltage vI Q1 gain. amplifier designs utilizing power supplies with voltage VCC For (W/L)1 = (50 μm/0.6 when transistors conduct equal drain currents.0. and 4. find VCE and the voltage gain at the following PROBLEMS MOSFET? dc collector bias currents: 0.5 μm) and (W/L)2 = (5 μm/0.13 A designer considers a number of low-voltage BJT functions as a linear amplifier. *** = very challenging.5-V signal amplitude at the output? corresponding maximum input signal permitted. What is the peak amplitude of the output sine wave and the value of the the output voltage will be given by gain obtained? Assume linear operation around the bias point. * = difficult problem. 7. v DG of Q2 is zero.5 mA.9 shows an amplifier in which the load negative-output signal swing as determined by the need to resistor RD has been replaced with another NMOS transistor keep the transistor in the active region. 7. Note that because in a table. the maximum allowed output negative (b) What is the gain achieved? What is the signal amplitude swing without the transistor entering saturation. you need to bias the transistor as close to the v O = VDD − Vt + V − v (W/L)2 t (W/L)2 I edge of saturation as possible without entering saturation at any time.10 A BJT amplifier circuit such as that in Fig. ** = more difficult. give the maximum possible positive. it will be operating in saturation at all times.5 mA. 4 mA. (a) Specify VDS at the bias point. what value of RD is needed? 7. Present your results Q2 connected as a two-terminal device. Find the voltage gain. D = design problem . what gains are achieved? If a negative-going output signal swing of 0. even when v I = 0 and iD2 = iD1 = 0. Problems 481 CHAPTER 7 voltage of approximately 0. (Hint: To obtain the maximum possible output amplitude for (W/L)1 (W/L)1 a given input.14 A BJT amplifier such as that in Fig. For each. Using iD1 = iD2 . what is the largest possible voltage gain achievable with each of these supply voltages? If in each case biasing VDD is adjusted so that VCE = VCC /2.0 V. even for large input signals. 1.2 V. of 1. It is required to find that for the range of v I over which Q1 is operating in saturation.) where we have assumed Vt1 = Vt2 = Vt . (c) If the dc bias current in the drain is to be 100 μA.3 V. and the vˆ gs that results in the 0.6 with VCC = + 5 V 2 (d) If kn = 200 μA/V . 2. Show that the minimum supply voltage VCC needed is given by VCC = VCEsat + P + Av VT Figure P7.0. that is. 7. 1 mA. Thus the circuit 7.and *7. denoted Av V/V. that is. 7.5 mA. Note also that the two D 7. specified to the nearest 0. P = 0. For a change . P = 1. 7. find IC and the small-signal voltage gain. What is the voltage gain? 1+ C C 1 + CC VA + VCE VA + VCE (Hint: Use Thévenin’s theorem to convert the circuit to the form in Fig.0 V Eq.6.4) and including the factor 1 + VCE /VA in (f) Av = −500 V/V. (7. (7. P = 0.15 is biased at Av = = − CC I R V − VCE a dc collector current of 0. P = 0. P = 1.0 V in Eq. Show that the gain expression changes to (g) Av = −500 V/V.15 The transistor in the circuit of Fig. P = 1. 482 Chapter 7 Transistor Amplifiers PROBLEMS Also. vO For VCC = +5 V and RC = 1 k. 7. the dc voltage at the collector is found to be +2 V. P7.3 mA. find VCC .17 In deriving the expression for small-signal voltage following situations: gain Av in Eq. for the *7. (7.5 V v BE /VT v CE (c) Av = −100 V/V. 7.5 V iC = I S e 1+ VA (d) Av = −100 V/V.0 V CHAPTER 7 (e) Av = −200 V/V.5 V. Derive this expression including the Early effect by substituting (a) Av = −20 V/V.6 is biased with a 10 k certain VBE .18 When the amplifier circuit of Fig.21) we neglected the Early effect. what is the gain 5V without and with the Early effect taken into account? Let VA = 100 V. P = 2.11).) For the case VCC = 5 V and VCE = 3 V.0 V −I C RC /VT V − VCE VT 7.2 V (b) Av = −50 V/V. calculate the vI resulting .v BE = +5 mV. v O . Calculate it two ways: by using the transistor 10 k exponential characteristic . Repeat for .iC . using the small-signal voltage gain. and approximately. 7.v BE = −5 mV.6 when oper- ated with a supply voltage VCC = +3V. 7.15 *7. what value of RC should be used? vI (d) What is the value of VBE required to provide the vO bias point mentioned above? Assume that the BJT has vO −15 IS = 10 A.5 mA. (a) What is the theoretical maximum voltage gain that this amplifier can provide? VCC 5V (b) What value of VCE must this amplifier be biased at to provide a voltage gain of –60 V/V? (c) If the dc collector current IC at the bias point in (b) is to vI be 0.19 Consider the amplifier circuit of Fig. = Multisim/PSpice.16. ** = more difficult. D = design problem . RC (e) If a sine-wave signal v be having a 5-mV peak ampli- RC tude is superimposed on VBE . (a) (b) (f) Characterize the signal current ic that will be superim- Figure P7. *** = very challenging.16 Sketch and label the voltage-transfer characteristics of the pnp amplifiers shown in Fig. find the corresponding output voltage signal v ce that will be superimposed VCC = 5 V on VCE assuming linear operation around the bias point. Summarize your results in a table. * = difficult problem.16 posed on the dc bias current IC . P7. Figure P7. Characterize the signal at VCE = 21 VCC . v CE . Be bias current into the base is 50 μA. corresponding iC −v CE curve. Also. sketch iC .22 Sketch the iC −v CE characteristics of an npn transistor evaluate the incremental (or small-signal) input resistance having β = 100 and VA = 100 V. and 100 μA. find the value of IC and IB .7 V and if RB = 100 k. If the dc a dc or average value and a superimposed sine wave. and iB versus time. for iB = 20 μA. Sketch characteristic curves of the amplifier. *7. of this sketch. If at this current ib that will be superimposed on the base current VBE = 0. write the equation for the careful of the phase relationships of the sine waves. 80 μA. 7. 50 μA. value of VBB . (h) Dividing the amplitude of v be by the amplitude of ib . Problems 483 over the range 10 μA to 40 μA? If the BJT is biased CHAPTER 7 (g) What is the value of the dc base current IB at the bias point? Assume β = 100. find the required current IB . and solve the two equations to obtain VCE and IC .20 The essence of transistor operation is that a change If the input signal causes a sinusoidal signal of 30-μA peak in v BE . Note that each graph consists of the load line obtained for VCC = 10 V and RC = 1 k. Also. . assume that iC = β iB at v CE = 0. write the equation for the load line. For the purpose PROBLEMS (i) Sketch and clearly label correlated graphs for v BE . . produces a change in iC .v BE . iC . find the corresponding ing . amplitude to be superimposed on IB . By keep. .v BE small. iC is approximately linearly related to signal components of iC and v CE . . .v BE . iC = gm . By passing .v BE . where gm is known as the transistor transconductance. an output voltage signal .iC through RC . Let the signal v gs 7. and 40 μA. find the minimum overdrive voltage at which the transistor should be operated so that the second-harmonic distortion is kept to less than 1%. Using the trigonometric identity Sketch iC −v CE characteristic curves for the BJT for iB = 2 sin θ = 21 − 21 cos 2θ. P7. and let β = 100.28). 20 μA. and substitute v gs = tion of graphical analysis to the circuit shown in Fig. What peak-to-peak collector voltage swing will result for iB varying 1 Vgs Second-harmonic distortion = × 100 4 VOV VCC If in a particular application Vgs is 10 mV.21 The purpose of this problem is to illustrate the applica- be a sine wave with amplitude Vgs . what dc bias current ID results? If a 0. (7. 30 μA.. expressed as a percentage horizontal (i. ** = more difficult. Let the transistor be biased at VOV = 0. For operation in RB saturation. *** = very challenging.21. sketch the load line. Use the expression for the small-signal voltage gain in Eq. find the corresponding increment in vCE collector current by evaluating the total collector current iD iB and subtracting the dc bias current ID .2: Small-Signal Operation for gm . = Multisim/PSpice. VBB iC RC 2 7. *7. D = design problem . neglect the Early effect).5 mA.24 Consider an NMOS transistor having kn = 10 mA/V .33). Compare with the value of gm obtained using Figure P7. Assume the lines to be frequency 2ω to that at frequency ω. (known as the second-harmonic distortion) is For VCC = 5 V and RC = 1 k. Vgs sin ωt in Eq.02-V signal.e. (7.02-V signal is superimposed on VGS . show that the ratio of the signal at 10 μA. (7. Find the value of gm for a transistor biased at and Models IC = 0. Use these results to estimate gm of the FET at this bias point.2 V.20) to derive an expression Section 7. * = difficult problem.v O is obtained.21 Eq.23 This problem investigates the nonlinear distortion introduced by a MOSFET amplifier. Repeat for a –0. To keep PROBLEMS 7. If it is desired to operate this transistor at ID = 200 μA. find VGS .8 V. assuming that 2 D *7. we bias RD = 10 k.5 25 h P 3 1 0.5 0.25 Consider the FET amplifier of Fig.41). find ro at the bias point is given by and calculate the voltage gain. the MOSFET to operate at an overdrive voltage VOV v̂ i .4 V.8 V.4 V. v̂ i = 2 if μn Co x = 200 μA/V ? If Vt = 0. find VOV . and Av = − =− 2 VOV VOV Co x = 0.20-V peak output signal across a 20-k load that can be VDS = 1 + 2 v̂ i /VOV used as a drain resistor.5 i P 10 4000 2 j P 10 4 k P 1 30 3 l P 5 0.4 fF/μm . consistent with allowing a negative signal voltage swing at the (c) Calculate the value of the voltage gain.10. we design (a) Find the dc quantities ID and VDS . VDD = 1.8 40 4 g P 0. Although some data is not available. and m = 15. let the maximum positive input signal be v̂ i . or 2ID RD 2 VDD − VDS 2 2 (7. kn = 5 mA/V . (7. If a gain of at least 10 V/V is needed. 484 Chapter 7 Transistor Amplifiers Next.10 for the case 2 Vt = 0. −1 drain of Av v̂ i while maintaining saturation-mode operation CHAPTER 7 (d) If the MOSFET has λ = 0.7 0. (7.8 0. Assume μn = 500 cm /V· s. * = difficult problem.26 An NMOS amplifier is to be designed to provide VOV + v̂ i + 2VDD v̂ i /VOV a 0. VDS . to maximize the voltage gain Av .5 V. and v̂ o for the case VDD = 2. ** = more difficult. for MOS transistors operating gain expression Av = −gm RD together with Eq. complete as many entries as to show that possible.1 10 2 f N 1. 7. and the second-harmonic distortion to an acceptable level.08 = Multisim/PSpice. 7.40). what values of ID and VOV would you choose? What W/L ratio is required Now.42) for gm under a variety of conditions. for the lowest possible VDS . Let VOV = mv̂ i . *** = very challenging.6 V. First. VGS = 0.28 In the table below. μp = 250 cm /V · s. Voltages (V) Dimensions (μm) Case Type ID (mA) V V VOV W L W/L k (W/L) gm (mA/V) GS t a N 1 3 2 1 b N 1 0.5 e N 0. 20 mV.27 In this problem we investigate an optimum design for this process technology kn = 100 μA/V .5 50 c N 10 2 1 d N 0.1 V . Show that the minimum VDS that is (b) Calculate the value of gm at the bias point. use the voltage 7. Av . it is always possible to calculate gm using one of Eqs. D *7. find the values of RD and W/L. what gm is required? Using a dc supply of 1. of the CS amplifier circuit of Fig. Now.42). D = design problem . (7. The input signal v sig is coupled to the gate through a very large capacitor (shown as infinite).33 Figure P7. the NMOS transistor has Vt = 0. CHAPTER 7 2 2 Vt = 0.5 μm and operating at ID = transistor with its T equivalent circuit.33 shows a discrete-circuit amplifier. Figure P7. assume these values.31 In the circuit of Fig.5 V. 2 of W that results in gm = 2 mA/V at ID = 0.6 fF/μm .33 = Multisim/PSpice. For a transistor with L = 0.30 (b) Find gm and ro if VA = 100 V. *** = very challenging.0 V. find the overdrive voltage at which each device expressions for the voltage gains v s /v i and v d /v i . assuming all capacitors behave as short circuits What is the voltage gain v o /v i ? What do VD and the gain at signal frequencies.32 For a 0. P7. v o /v gs . Also. 2 (a) If the transistor has Vt = 1 V. That is. and v o /v sig . assuming λ = 0.5 μm.5 V and VA = 50 V and operates with VD = 1 V. (c) Draw a complete small-signal equivalent circuit for the 7. Problems 485 2 7. find the value Vtp = –0. v gs /v sig .30 For the NMOS amplifier in Fig. 15 V 10 M 16 k vo Rsig = 200 k vgs 16 k vo vsig 5 M 7 k Rin Figure P7. P7. and C the required VGS . μp Co x = 100 μA/V .5 mA.31 Figure P7. Derive 100 μA.25 mA.18-μm CMOS fabrication process: Vtn = 0. ** = more difficult. VA (p-channel devices) = 6L (μm). ID = 0. VA (n-channel devices) = 5L (μm). * = difficult problem. All capacitors behave as short circuits for signals and as open circuits for dc. and kn = 4 mA/V .29 An NMOS technology has μn Co x = 250 μA/V and 7. amplifier. Find the small-signal model parameters (gm and ro ) for both an NMOS and a PMOS 7.5 V. Also.30. The transistor source is connected to ground at signal frequencies via a very large capacitor (shown as infinite).5 V. find o x = 8. and verify that they are consistent with the values of the circuit components and the device parameters. verify that the bias circuit establishes VGS = 1. μn Co x = 400 μA/V . The output voltage signal that develops at the drain is coupled to a load resistance via a very large capacitor (shown as infinite). PROBLEMS must be operating.5 V. *7. and VD = +7. replace the transistor having W/L = 10 μm/0. D = design problem .31. become for I increased to 1 mA? (d) Find Rin . VBE is adjusted so that VC = (b) using the small-signal approximation. –10 mV.. +8 mV. For the design that results in the largest signal at 5-k resistor connects the collector to a +5-V supply.41 We wish to design the amplifier circuit of Fig. and a signal v be = 0. If VCC = 3 V. show is the resulting collector voltage VC ? Now. –2 mV. without the BJT leaving the active region. 7. approximation. –8 a β that ranges from 50 to 150.34 Consider a transistor biased to operate in the active What collector-bias current should he choose? What is the mode at a dc collector current IC . +5 mV. +2 mV. where V̂be is the maximum value for acceptable VBE = 0. Also. v C (t). find expressions for the total instantaneous a column for the error introduced by the small-signal quantities iC (t). D *7. What are the do the calculation two ways: extreme values found of the resistance looking into the base? CHAPTER 7 (a) using the exponential characteristic.39 A transistor operating with nominal gm of 40 mA/V has +1 mV. Comment on the range of validity of the What is the voltage gain? small-signal approximation. Calculate the collector signal minimum β he can tolerate for the transistor used? current as a fraction of IC (i. if a signal applied to that the base raises v BE to 705 mV. RC = 2 k.20 under the constraint that VCC is fixed. being mV.5 mA. –1 mV.005 sin ωt Present your results in the form of a table that includes volts is applied. What the collector.35 An npn BJT with grounded emitter is operated with V̂be sin ωt. and 7. +10 mV.700 V. at which the collector current is 0.20.e. Let the input signal v be = 7. ic /IC ) for input signals v be of 7. allows a ±20% variation in IC . the bias circuit. –5 mV. and –12 mV. 7. 1 V. +12 mV. A linearity. 486 Chapter 7 Transistor Amplifiers PROBLEMS 7.40 In the circuit of Fig. and iB (t). find the resulting total collector . In each case less than ideal. The transistor has β = 100. what output signal voltage results? 7.37 A pnp BJT is biased to operate at IC = 1. It has a β of 100 and VA of 100 V.25 and 7.0 mA. Transistor a b c d e f g α 1. what is the value of fiers under various conditions. Repeat for a bias current of 50 μA. what are v be and v c ? RC IC = VCC − 0.00 1. What is of a number of BJTs of different types. D 7. and re . gain. For VCC = 3 V and V̂be = 5 mV.1 k = Multisim/PSpice. 7.36 A transistor with β = 100 is biased to operate at a dc the amplitude of the output voltage signal.00 5 IB (mA) 0. 7.90 β 100 ∞ IC (mA) 1. ** = more difficult. current iC and total collector voltage v C using the exponential V̂be iC –v BE relationship. 7.3 1+ VT Calculate the voltage gain v c /v be . rπ .5 mA.10 gm (mA/V) 700 re () 25 100 rπ () 10.27) of the of 30 mA/V and a base input resistance of 3000 or more. *** = very challenging. the small-signal resistance seen looking into the emitter (re )? (Note: Isn’t it remarkable how much two parameters can Into the base (rπ )? If the collector is connected to a 5-k load. Provide the missing entries. * = difficult problem. D = design problem . and the voltage collector current of 0. and find an expression for the voltage gain obtained. For this situation. operating as ampli- the associated value of gm ? If β = 100. Compare with the value obtained using the small-signal approximation. reveal?) with a signal of 5-mV peak applied between base and emitter. find the dc voltage at the collector. BJT complete with the values of their parameters.020 1. –gm RC .43 A BJT is biased to operate in the active mode at a dc collector current of 1 mA.42 The table below summarizes some of the basic attributes 7. that is.000 0. Find the values of gm .00 IE (mA) 1.38 A designer wishes to create a BJT amplifier with a gm Give the four small-signal models (Figs. 51 shows a transistor with the collector 10 k connected to the base. Use the model of Fig. RC = 2 k. Find the dc voltage vsig at the collector.50 Figure P7.” The bias arrangement Rin ≡ v π /ib . has a small-signal resistance r equal to re . 7. the voltage transmission from source to amplifier is not shown. CHAPTER 7 7. Replace the BJT with its T equivalent-circuit = Multisim/PSpice. known as a diode-connected transistor.52 shows a particular configuration of BJT equivalent circuit of Fig. Use these to show that the overall voltage gain v o /v sig equal to rπ . 6. 7. show that the input resistance between base and emitter.26(a). gm = 50 mA/V.24(b) is the incremental version of the large-signal model of Fig. the BJT can be replaced by one of the small-signal models of Figs.46 Show that the hybrid-π model of Fig.48 is biased with a RC vo current source I and has a very high β.51 a signal source v sig with a source resistance Rsig . Hence find the voltage gain v c /v i . ix I 0.26(b) and show that the resulting two-terminal device. and β = 100.47 Show that the T model of Fig. 6.26(b) is the incremental version of the large-signal model of Fig. The bias arrangement is not shown.23.52 Figure P7.24 and 7.26. v sig rπ + Rsig PROBLEMS 7.51 Figure P7. Also.24(a). D = design problem . is given by 7.48 7. is v o /v π .44 Using the T model of Fig.2 mA vx Figure P7.48 The transistor amplifier in Fig. 7. Replace the v transistor with the T model of Fig. Rsig ib 7.26(b) is equal to that provided by the model in =− Fig.49 For the conceptual circuit shown in Fig. 7. 7. and the voltage gain from base to collector. VC .26(b) (note that the dc current source I should be replaced with an open circuit). 7.50 7. If a peak-to-peak v output voltage of 1 V is measured at the collector. 7. Rin 3 Figure P7. looking into the base.45 Show that the collector current provided by the model vo βRC of Fig. ** = more difficult. Replace the BJT with its hybrid-π 7.5(b). * = difficult problem. Since a zero v BC implies operation in the active mode. v π /v sig . *** = very challenging. 7. P7.26(a). 7. 7. Find the input resistance amplifiers known as “emitter follower. 7. find the value of re . what are r = ix the peak-to-peak values of v be and ib ? x 7.5(d). Problems 487 input.50 shows the circuit of an amplifier fed with Figure P7. The bias circuitry is not shown. 7.54 In the circuit shown in Fig. What is the dc voltage at the collector? Replacing the Rin ≡ = (β + 1) re + Re BJT with one of the hybrid-π models (neglecting ro ). the signal component Figure P7.) The amplifier is to have the greatest Rin possible voltage gain and the largest possible output signal but retain small-signal linear operation (i. * = difficult problem.54 model for the BJT (use α = 0.33 mA that the amplifier input resistance match this value.25(a). the transistor has a β PROBLEMS model of Fig.53 across the base–emitter junction should be limited to no more = Multisim/PSpice.30(a).e.99). Find the input resistances Re = Rib and Rin and the overall voltage gain v o /v sig . draw a complete small-signal equivalent circuit utilizing an appropriate T Figure P7. load RL resistances need to be “matched” to the equivalent resistances Q1 12 k of the interconnecting cables.53 For the circuit shown in Fig. Rsig C1 D *7. What value of voltage gain results? vo Grounded-base circuits of this kind are used in systems such as cable TV. The power supplies available are ±5 V. Show that vi of 200. D 7. Your circuit should show the values of all components. and it is required vsig 0. 488 Chapter 7 Transistor Amplifiers 7.57 Design an amplifier using the configuration of 75 Fig. what is the largest possible voltage gain available for a signal source gain v o /v sig .5 V 10 mA 10 k vi Rsig vb Re vo 1k vo vsig Rin RC 100 Figure P7. P7. P7.. *** = very challenging.52 Rin Rib 7. 7.54. including the model parameters. for highest-quality signaling. connected directly to the base and a very-high-resistance load? Calculate the value of the maximum possible gain for 5V VA = 25 V and VA = 125 V. in which.30(a) by raising the 12 k RC resistor values by a factor n to increase the resistance seen C2 by the input v i to 75 . what values of v sig and v b are required? CHAPTER 7 5V ib 1.4 V. For an output vi Re + re signal of ±0.26(b). D = design problem . 7. (Note that Rin = re RE re . 7. The input signal source has a resistance of 50 . draw the ib vo equivalent circuit of the amplifier. Disregarding how biasing is to be done.53. 7.55 Consider the augmented hybrid-π model shown in What is the input resistance Rin ? Calculate the overall voltage Fig.56 Redesign the circuit of Fig. ** = more difficult. Find the overall voltage gain Gv . P7. sig R L =∞ = Multisim/PSpice. Rsig ) and is connected to a load resistance RL show that the gain of the amplifier proper Av is given by Av = Gm Ro RL and the overall voltage gain Gv is given by Rin Gv = G R R Rin + Rsig m o L 3. with the small-signal equivalent-circuit model of Fig.61 Section 7. 3.26(b) (b) If the load resistance changes from the nominal value of PROBLEMS (remember to replace the dc power supply with a short circuit). if the amplifier is fed with a signal source (v sig . what does the voltage gain v o2 /v i become? Figure P7. the change in output voltage Analyze the resulting amplifier equivalent circuit to show that is limited to 5% of nominal value. defined as the ratio of the load current to the v Gv o = v o current drawn from the signal source. What D 7.58 The transistor in the circuit shown in Fig.58 vi Rin Gmvi Ro vo Find the values of these voltage gains (for α 1). and (c) The nominal overall voltage gain is 10 V/V. Av o .61 Figure P7.6 Io Figure P7. 2-k load.62. Rsig ) and connected to a load RL open-circuit voltage gain of 100 V/V. and Ro of an is the value of voltage gain realized from signal source to amplifier that is to be connected between a 100-k source output? and a 2-k load and is required to meet the following specifications: *7. if the terminal labeled v o1 is connected to ground. find the collector bias current IC .34(b) show that Gm = Av o /Ro .60 Specify the parameters Rin . v o1 RE 7. Problems 489 CHAPTER 7 than 10 mV). ** = more difficult. 2 k to a low value of 1 k.61 shows an alternative equivalent-circuit v i = RE + re representation of an amplifier. P7.58 is biased to operate in the active mode. an with a signal source (v sig . Replace the transistor connection to the amplifier input. Assuming that β is very (a) No more than 5% of the signal strength is lost in the large. and an output resistance is shown in Fig. 7.62 An alternative equivalent circuit of an amplifier fed 7.59 An amplifier with an input resistance of 100 k. D = design problem . If this circuit is to be equivalent v o2 −αRC to that in Fig. 7. * = difficult problem. Here Gv o is the open-circuit overall of 100 is connected between a 20-k signal source and a voltage gain.3: Basic Configurations 7. Also find the current gain. Also convince v i = RE + re yourself that the transconductance Gm is defined as io Gm = v i R 5V L =0 and hence is known as the short-circuit transconductance. Find appropriate values for RE and RC . Now.3 Now. *** = very challenging. Which of the amplifier characteristic parameters is most Ri Gv o = A affected by Rf (that is.64 Calculate the overall voltage gain of a CS amplifier fed with a 1-M source and connected to a 10-k load. Rin depends 400 μA/V and W/L = 10. RD is reduced to RD = RL . Rf = PROBLEMS different than Ro . Show that 1 M. 490 Chapter 7 Transistor Amplifiers and Rout is the output resistance with v sig set to zero. to increase the 1 + R2 /Rf output signal swing.62 Rsig ii Rf vsig vi R1 g mvi R2 RL vo Rin Figure P7.25 V. where Ri = Rin R . P7. This is Evaluate Rin . L =∞ CHAPTER 7 Also show that the overall voltage gain is 7. Av o . Gv . Also. what must the peak amplitude of v sig be? Show that 7. If. at the output.66 A common-source amplifier utilizes a MOSFET oper- Rf + R2 RL ated at VOV = 0. if a 0.2-V peak sine-wave signal is required this amplifier. Gv = Gv o RL The MOSFET has gm = 2 mA/V. It is biased at ID = 320 μA and uses on RL . relative to the case with Rf = ∞)? Ri + Rsig v o For Rsig = 100 k determine the overall voltage gain. D = design problem .63 = Multisim/PSpice. what does Gv Ro = R2 Rf become? Rsig Rout io vsig vi Rin RL vo Gvovsig Figure P7. with and without Rf present. gm = 100 mA/V. Find Rin . and a drain resistance RL + Rout RD = 10 k is utilized. Av o . and RL = 1 k. **7.63 the RD = 10 k.63 Most practical amplifiers have internal feedback 7. and Ro for the case R1 = 100 k. In such a case. It is Rf that makes the amplifier non-unilateral. what overall voltage gain Gv Rf models the internal feedback mechanism that is present in is realized? Now. *** = very challenging. The amplifier feeds a load resistance Rin = R1 RL = 15 k. and Ro . The designer selects RD = 2RL . If it is required 1 + gm R2 RL to realize an overall voltage gain Gv of −10 V/V what gm is 1 − 1/ gm Rf Av o = −gm R2 needed? Also specify the bias current ID . R2 = 100 . if a load resistance of equivalent circuit of an amplifier where a feedback resistance 10 k is connected to the output. * = difficult problem.65 A CS amplifier utilizes a MOSFET with μn Co x = 2 that make them non-unilateral. ** = more difficult. To illustrate this point we show in Fig. the gain doubled. First determine the nominal value and the range of = Multisim/PSpice. Rsig = 200 k. the peak allowable range of β? amplitude of v π is 5 mV.71 A MOSFET connected in the CS configuration has to the drain of the second stage. find the resulting Av and 7. 50 to 150. and Ro .25 mA and has β = 100. to be? PROBLEMS (b) Calculate the overall voltage gain Gv . If the peak voltage of the sine wave appearing between Consider the case RL = 10 k and Rsig = 10 k.75 Design a CE amplifier with a resistance Re in the (a) What is the nominal value of Gv ? (b) If β can be anywhere between 50 and 150. If the peak voltage of the sine wave appearing between resistance Rs = 0. (7. Gv . the BJT be biased at IC = 1 mA.76 Inclusion of an emitter resistance Re reduces the 7. What do you estimate the value of Rs (a) Sketch the equivalent circuit of the two-stage amplifier. (d) If it is not possible to restrict β to the range found in (c). A load resistance RL = 10 k is connected 7. The BJT has a nominal β of and what output voltage signal appears across the load? 100. D 7. The BJT is biased at IC = 1 mA and its β IC = 0.5 k in the source lead was measured and base and emitter is to be limited to 5 mV. What must gm be? What value of Rs is needed to obtain an overall voltage D *7. The first stage is fed with a source v sig having a resistance (b) Find the overall voltage gain. Each BJT is biased at RC RL of 10 k. but the circuit and what output voltage signal appears across the load? operation remained linear.70 Two identical CE amplifiers are connected in cascade. of a new nominal value? What is the nominal value of Gv in this case? D 7. D = design problem .15 V and a source resistance of 30 k. IC = 0. When a resistance Rs is at ID = 0. If the amplifier is fed with a signal source having Rsig /β + 1/gm a resistance of 10 k. (c) If in a particular design. Each MOSFET is biased a transconductance gm = 5 mA/V. variability of the gain Gv due to the inevitable wide variance The first stage is fed with a source v sig having a resistance in the value of β. IC = 0. and Av o . *** = very challenging. If the to 150. what is the emitter to meet the following specifications: corresponding range of Gv ? (i) Input resistance Rin = 15 k.5 mA and has a collector resistance RC = 12 k and a resistance Re = 250 connected in the emitter. and a load resistance RL = 10 k is connected to the output terminal.5 mA. If the amplifier is fed with a signal source have to reduce the overall voltage gain to −5 V/V? having a resistance of 10 k.69 In this problem we investigate the effect of the gain of −16 V/V? inevitable variability of β on the realized gain of the CE amplifier. what is the maximum of 0. R Gv = L Av o .114). find the resulting Av and where RL = RL RC . ** = more difficult. what value of bias current IC would result in Gv total resistance in the collector is 6 k. is reduced to 2 mA/V. found to be −10 V/V. v o2 /v sig . it is required to maintain Gv (ii) When fed from a signal source with a peak amplitude within ±20% of its nominal value. Consider a CE amplifier operating between a Rsig = 10 k. use the overall gain expression 7. Find Rin . Ro . For this purpose. Problems 491 CHAPTER 7 7. Each stage connected in the source lead. The BJT has β = 74. When Rs was shorted. the effective transconductance utilizes a drain resistance RD = 10 k.73 The overall voltage gain of a CS amplifier with a Gv .74 A CE amplifier utilizes a BJT with β = 100 biased at in Eq.67 Two identical CS amplifiers are connected in cascade. Each stage utilizes a collector is specified to be nominally 100 but can lie in the range of resistance RC = 10 k. and the designer has to contend with β in the range 50 Specify Re and the bias current IC . it has a collector resistance RC = 10 k.68 A CE amplifier utilizes a BJT with β = 100 biased at 2 mA/V is found to have an overall voltage gain of −10 V/V. and let base and emitter is to be limited to 5 mV.72 A CS amplifier using an NMOS transistor with gm = 7.3 mA and operates with VOV = 0. what v̂ sig is allowed. (a) Sketch the equivalent circuit of the two-stage amplifier. what v̂ sig is allowed. Find What value should a resistance Rs inserted in the source lead Rin . 7. A load resistance RL = 10 k is connected signal source with Rsig = 10 k and a total collector resistance to the collector of the second stage. and a load resistance RL = 12 k is connected to the output terminal.2 V. find the overall voltage falling in a range of ±20% gain Gv and the peak amplitude of the output signal v o . * = difficult problem. v b /v sig . isig Rsig (b) If the signal amplitude across the base–emitter junction is to be limited to 10 mV. * = difficult problem. which the BJT can be biased? At this bias current.84 An emitter follower is required to deliver a 0.5 mA/V . What must gm of the MOSFET be? If the MOSFET is biased at what are the maximum and minimum currents that the ID = 0.2 mA with RC = RL = 7. 492 Chapter 7 Transistor Amplifiers Gv without resistance Re .86 An emitter follower is operating at a collector bias 10 k and is driven by a signal source with Rsig = 0. and the MOSFET transconductance 12 V/V. If the peak amplitude of v gs is to Rsig = 100 is found to have an overall voltage gain of be limited to 50 mV. the new nominal value of Gv . what is the lowest value of ID signal generator the overall voltage gain decreased to 10 V/V. and the expected range of Gv .78 A CG amplifier when fed with a signal source having sinusoid to a 2-k load. 7. the maximum and minimum currents that the BJT will be conducting (at the positive and negative peaks of the output sine wave)? If the resistance of the signal source is 200 k.5 k.5 k and as high as 5 k. and v o /v sig . RC = peaks of the output sine wave)? What must the peak amplitude 10 k. (a) Find Rin .79 A CB amplifier is operating with RL = 10 k.80 Gv obtained in (a). RC vo 7.81 A CB amplifier is biased at IE = 0. If the nominal value of β is 100. If the maximum signal amplitude a 1-k load.5-V peak 7. α 1. At what current IC should the transistor of v sig be? be biased for the input resistance Rin to equal that of the signal source? What is the resulting overall voltage gain? Assume D 7. The amplifier is driven by a voltage source must have if the output voltage is to remain within ±10% of having a 750- resistance. Then select a value for Re that will what are the corresponding amplitudes of v sig and v o ? Assume PROBLEMS ensure that Gv be within ±20% of its new nominal value. When a 100- resistance was added in series with the 2 parameter kn is 5 mA/V .5-V α 1. What is the input resistance of 2 nominal value? If the MOSFET has kn = 2.5 k. what value of Gv is obtained? Thus determine the required amplitude of v sig .80. ** = more difficult. What gm = 2 mA/V has a 5-k drain resistance RD and a 5-k load is the maximum output resistance that the source follower CHAPTER 7 resistance RL . Use these values first to verify the value of Figure P7.85 An emitter follower with a BJT biased at IC = 2 mA and having β = 100 is connected between a source with Rsig = 10 k and a load RL = 0. what is the lowest value of IE at 7. at what the amplifier? What is the overall voltage gain Gv ? By what current ID must it be biased? At what overdrive voltage is the factor must the bias current ID of the MOSFET be changed so MOSFET operating? that Rin matches Rsig ? D 7. what are Find v o . what output of the voltage between base and emitter is limited to 10 mV.5 mA and is used to connect a 10-k source to the overall voltage gain Gv . at which the MOSFET can be biased? At this bias current. *** = very challenging.83 A source follower is required to deliver a 0. Find current of 0. and Rsig = 50 .82 A source follower is required to connect a high-resistance source to a load whose resistance is nominally 7. Assume β = 100.77 A CG amplifier using an NMOS transistor for which 2 k but can be as low as 1. let Rsig re and α 1. then to find the value of Gv obtained with RL reduced to 250 . P7.25 mA.80 For the circuit in Fig. peak sinusoid to a 2-k load. D = design problem . 7. Specify the value of Re . If the peak amplitude of v be is to be limited to 5 mV. what is the corresponding amplitude of v sig and v o ? (c) Find the open-circuit voltage gain Gv o and the output resistance Rout . at what overdrive voltage must it be operating? MOSFET will be conducting (at the positive and negative D 7. resistance Rout and overall voltage gain Gv result? Now if = Multisim/PSpice. 1.94 In an electronic instrument using the biasing Figure P7.25 mA. gain of a CE amplifier with a collector resistance RC = 10 k What is the value of VG created? If supplier specifications 2 is calculated to be −100 V/V. Then. If the BJT is biased at IC = 1 allow kn to vary from 0.48(c) is used in a what must the values of gm and ro be? design with VG = 5 V and RS = 2 k. Observe the effect of ro on limiting Gv as IC is increased. a manufacturing error reduces 7. 7. 10 k. using a 9-V supply. gain of the source follower becomes What extreme values of current now result? vo RL ro Gv ≡ = 1 7.0 V. RG1 = 10 M.96 The bias circuit of Fig.2 to 0.90 Show that when ro is taken into account. with a signal source having Rsig = 10 k and having RC ||RL = was found to have an output resistance Rout of 150 . with about one-third of the supply voltage across each vc of RS and RD . RG2 . The BJT is specified to have β = 100 and VA = 25 V. and kn = 2 mA/V . the overall voltage RS to zero. (a) Find expressions for v c /v sig and v e /v sig . 7.93 Using the circuit topology displayed in Fig. provide a better estimate from 1. Section 7. 2 Y Vt = 1.5 mA? Choose an *7. λ = 0.88 scheme shown in Fig. Consider the situation of a CE amplifier operating 7. Use a gate-bias resistor of 10 M. and RD that you have chosen? RB ib X Specify them to two significant digits. For the MOSFET. RS .98. 7. D = design problem . when driven from a 5-k source. the bias current IC on the overall voltage gain Gv of a CE amplifier.5 V. we investigate the effect of changing corresponding range of Rout and Gv .3 mA/V and Vt to vary mA and the Early voltage is 100 V.4: Biasing and node Y is disconnected from ground and connected D 7. D *7. and RG2 = 5. it is found that the gain is halved at RL = 500 . the voltage gain is carefully measured If a transistor for which kn is 50% higher is used. what are the extreme values of ID that of the voltage gain Gv . If the amplifier remained linear throughout this measurement. Let VDD = 15 V. 7. ** = more difficult. Fig. For the NMOS transistor.0 mA.87 An emitter follower. neglect the Early effect. *** = very challenging. 7. 0. What bias current results? Now. (b) If v sig is disconnected from node X. may result? What value of RS should have been installed to limit the maximum value of ID to 1. node X is grounded.1 mA.0 V to 1. gain when the follower is driven by a 10-k source and loaded PROBLEMS by a 1-k resistor. What are the values of RG1 . For a MOSFET with = Multisim/PSpice.48(c). The transistor 2 has Vt = 1 V and kn = 2 mA/V . The available supplies are ±5 V.48(c). 2 λ = 0. (7. Problems 493 transistor β is specified to lie in the range 50 to 150. P7. and 1. arrange to bias the NMOS transistor at ID = 0. find the new expression for v c /v sig . how RC far is the drain voltage from the edge of saturation? ie ve D 7.48(c). Use 22 M for the larger of RG1 and RG2 . 0. find the CHAPTER 7 D 7. with RL removed.91 In this problem.92 Consider the classical biasing scheme shown in to v sig . with VG = 5 V and RS = 3 k.48(e).1 M.88 For the general amplifier circuit shown in Fig. 7. when RL is connected and its value resulting percentage increase in ID ? is varied. Arrange that the drain current is ic 1 mA.2 mA. * = difficult problem. Find the value of IC that results in 7. the voltage appropriate standard 5% resistor value (refer to Appendix J).114) (with ro included in parallel with RC and RL in resistance was increased to 10 k. The output resistance increased to 250 when the source Use Eq.5 mA. what is the and found to be 0.5 mA with VD vsig RE midway between cutoff and the beginning of triode operation. Specify RS and RD to two significant digits. Find the overall voltage the numerator) to find Gv at IC = 0.89 When the Early effect is neglected. and kn = 1 mA/V . For your design.88 Gv = 50 V/V.95 An NMOS transistor is connected in the bias circuit of v sig RL ro + gm Fig. Vt = 1 V. 494 Chapter 7 Transistor Amplifiers 2 kn = 2 mA/V . the source voltage was measured and found PROBLEMS and its value. What must Vt be for this device? If a device for of K. when multiplied by the variability (or tolerance) to be 2 V. which Vt is 0. provides the corresponding expected variability of ID .5 V less is used. what does VS become? What . ID I . 99 A very useful way to characterize the stability of VG and a resistance RS included in the source lead.25 mA/V 2 the expected variability of ID in this case. Let VDD = VSS = 5 V.25 V. to the variability (Vt /Vt ) in the threshold voltage Vt can be evaluated from 10 V ID I Vt = SVDt ID Vt I R1 RS where SVDt . find the required ∂I /I ID ∂I K value of (ID RS ) and VG to limit ID /ID to ±5%.5 mA and for the largest Fig. for of ±10% and Vt = 1 V. specify the values of VG . Also. Let the MOSFET be biased at VOV = 0. find the value of RS that would each of the following two devices (use a 10-μA current in the result in ID = 100 μA with a variability of ±1%. find the value of RS for (a) Vt = 1 V and kp W/L = 0. (c) If the available supply VSS = 5 V. SKD = 1 1 + 2 KID RS D 7.98 ±5%. What S ≡ D D= D K ∂K/K ∂K ID value of RS is needed if ID is 100 μA? = Multisim/PSpice. with ID = 1 mA and VD = 3 V. show that R2 RD I 2Vt SVDt = − VOV and find the variability in ID for Vt = 0.48(e) for a MOSFET 2 The purpose of this problem is to investigate the use of having Vt = 1 V and kn = 4 mA/V .5 mA/V 2 ID = 100 μA.97 Design the circuit of Fig. ** = more difficult. voltage divider): find VGS and the required value of VSS . R1 . at the drain.K bias current results? = SKD ID K D 7. For each case. Assume that the signal voltage on the source I terminal of the FET is zero. the sensitivity function in the design of the bias circuit of CHAPTER 7 Design for a dc bias current of 0. VD . show the bias current ID is to evaluate the sensitivity of ID relative that to a particular transistor parameter whose variability might be 2Vt I large. the sensitivity of ID relative to Vt . VS . The sensitivity of ID relative to the MOSFET parameter SVDt = − VOV + 2ID RS K ≡ 21 k (W/L) is defined as For the same parameters given in (a). D = design problem . R2 . P7. D **7. *** = very challenging. is defined as I ∂ID Vt VS SVDt = ∂Vt ID VG VD (a) For the case of a MOSFET biased with a fixed VGS . Evaluate the sensitivity function. RS .100 The variability (ID /ID ) in the bias current ID due and RD .48(e). possible voltage gain (and thus the largest possible RD ) consistent with allowing a 2-V peak-to-peak voltage swing (a) Show that for Vt constant. * = difficult problem.98 Design the circuit in Fig.5 V and Vt /Vt = Figure P7.98 so that the 2 transistor operates in saturation with VD biased 1 V from the (b) For a MOSFET having K = 100 μA/V with a variability edge of the triode region. and give (b) Vt = 2 V and kp W/L = 1. (b) For the case of a MOSFET biased with a fixed gate voltage D **7. 7. 7. what is the range obtained for VBE ? Check your design by evaluating the resulting range What is the corresponding range of IC ? If RC = 2 k.103 shows a variation of the D 7. 7.104 For the circuit in Fig. RG1 .0 V for β equal to its nominal If VCC = 3 V. = Multisim/PSpice. RB2 are 1% resistors. find the required values of R1 . Then choose suitable significant digits. that is. VDD and R2 . For each of the following two biasing arrangement. * = difficult problem. Use a voltage-divider current of negative signal swing at the drain. The transistor β is specified to be (b) Vt = 2 V and kn = 1. R1 . D 7. or slightly higher. transistors.107 Repeat Problem 7. If you have RG1 the data available. find RD to establish a drain expected range for IC and VCE ? Comment on the efficacy of current of 0. Provide a design using a 9-V supply in which the 2 NMOS transistor for which Vt = 0. let RG = 10 M.106 Consider the single-supply bias network shown in feedback-bias circuit of Fig.50 with a 5-V supply and an NMOS device for which achieve IC = 1 mA for the “nominal” transistor. find how low β can be while the value of IC does not fall below that obtained with the design of Problem 7. CHAPTER 7 the range obtained for VCE ? Comment on the efficacy of this RD = 10 k. 7. D = design problem .103 (b) If the resistance ratio found in (a) is used. (a) Find the largest ratio RB /RE that will guarantee IE remains within ±5% of its nominal value for β as low as 50 and as high as 150. VE . 7. Use 22 M as the largest IE /10. R2 .710 V. What values of RD . Check your design at β = 90. What is the 2 Vt = 1 V and kn = 10 mA/V .103 Figure P7. (d) Find RC so that VCE = 1. find the voltages VD and VG . and RE with λ = 0.51(b) at IC = 1 mA.25 mA/V nominally 100. 7. 7. 7. find VB . Specify the values you have chosen for RE . if RB1 and value. kn = 8 mA/V . 7. what must the ratio RB1 /RB2 be? Now. Using a 5-V supply with an Fig.2 mA.5 mA/V 2 Fig. what is of IE . stability of IE in (a). D 7. 5% resistors (see Appendix J). VC . and supply voltage is equally split between RC . and RG2 have you chosen? Specify all resistors to two do your initial design with β = ∞. find an expression for the voltage VBB ≡ VCC R2 / R1 + R2 that will result in a voltage drop of VCC /3 across RE . a collector current of 0. this bias design. and IC for your final design using β = 90. Now. VCE . find the required value of RB to PROBLEMS Fig. neglect the base (c) For VCC = 5 V.108 It is required to design the bias circuit of Fig. It is required to bias the transistor at IC = 1 mA.105 It is required to bias the transistor in the circuit of (a) Vt = 1 V and kn = 0.5 mA and to satisfy the requirement for divider.8 V.52(a). provide a design that biases the transistor at ID = 1 mA. D 7. but use a voltage-divider RD current that is IE /2.99 to 1. For D 7. The transistor β is specified to with VDS large enough to allow saturation operation for a 2-V have a minimum value of 90. each can be in the range of 0.50. but it can fall in the range of 50 to 150. D *7. operate for the best transistors for which β is very high. Problems 495 7.106 for β = 90. and RE current IB in comparison with the current in the voltage to obtain IE = 0. which requires selecting RB1 and RB2 so that VBE = 0. Figure P7. 2 D 7.01 of its nominal value. Since a reasonable design should resistor in the feedback-bias network.52 RG2 for a BJT whose nominal β = 100.101 In the circuit of Fig. ** = more difficult.51(a). RC .50.102 Using the feedback bias arrangement shown in VCC = +3 V and RC = 2 k.6 mA. *** = very challenging. making the choice in a way that will result in a VBB that is slightly higher than the ideal value.106. and VDD = 10 V. RE . P7. P7.114 The circuit in Fig.113. design the RB feedback bias circuit of Fig. assume that the transistor β values of I and RB to bias the BJT at IC = 1 mA and VC = changes over this temperature range from 50 to 150. In addition for a high-resistance load is shown in Fig. (a) For β = ∞.111 Using a 3-V power supply. I what emitter current is obtained? Also.5 mA and to allow a ±1-V signal swing at the collector. VB . 496 Chapter 7 Transistor Amplifiers Design this circuit for β = 100. This can be achieved by connecting a resistor between base and emitter. ** = more difficult.112 0. we have to arrange for an additional current to flow through RB .110 Utilizing ±3-V power supplies. (b) Select standard 5% resistor values.113 A circuit that can provide a very large voltage gain the percentage change in collector bias current. it is required to RB2 design a version of the circuit in Fig. P7. Find the to the –2 mV/°C change in VBE . what values of RE and RC are required? VCC (b) If the BJT is specified to have a minimum β of 50. D 7. rent IO as long as the circuit to which the collector is = Multisim/PSpice.5 V. * = difficult problem.112 (a) Using a 3-V power supply. *** = very challenging.113 transistors are used. D *7. 7.4 mA is obtained and so that the gain is maximized while allowing ±1 V of signal swing at the collector. Find values for RE and RC so that a dc emitter current of Figure P7. (c) Find VC and IC for β = ∞. (d) For the values you selected in (c). find CHAPTER 7 the largest value for RB consistent with the need to limit the voltage drop across it to one-tenth the voltage drop RC across RE . 1.5 mA and VC is placed 2 V result with β = ∞? above VE . as shown in 7. Let β = 100. 7. what values of VC and IC the circuit so that IC = 0. It is required to design equal to the base current. 7. and RC ? In making your selection.54 to provide a dc emitter current of 0. 7. find IC . If temperature increases from the nominal value of 25°C to 125°C.114 provides a constant cur- Fig. Use a current through RB2 PROBLEMS D *7. VE . and reevaluate VC and IC for β = 100. and VC for β = ∞ and for β = 50. estimate D 7. The BJT has a nominal β = 100.53 using ±5-V supplies. use IC somewhat lower values in order to compensate for the RB1 low-β effects.54 to provide IC = 1 mA and VC = VCC /2 for β = 100. VC IC D *7. (c) What standard 5% resistor values (see Appendix J) would VC you use for RB . If the actual BJT used has β = 50. (d) To improve the situation that obtains when high-β Figure P7. Now. Use standard 5% resistor values (see Appendix J). what is the allowable signal swing at the collector? Repeat for β = 150.112. design a version VCC of the circuit of Fig.109 Consider the two-supply bias arrangement shown in Fig.53 in which the signal will be coupled to the emitter and thus RB can be set to zero. D = design problem . (a) Neglecting the Early effect. What is the corresponding Figure P7.3 V. P7.116 For the circuit in Fig.5 mA. The amplifier is fed from a signal source with a Thévenin resistance of 1 M. RD = 10 k.7 V and VA = 50 V.115 For the circuit in Fig. What is the largest voltage that can be applied to the collector? Assume VBE = 0.5: Discrete-Circuit Amplifiers 7. P7.115. ro = 100 k. Show and keeping the current in each junction the same.5 mA and VOV = 0. What is the lowest voltage that can be applied to the collector of Q3 ? D 7.114 D *7. and RG = 10 M. Figure P7. P7. What must the MOSFET’s kn be? What is the dc voltage at the drain? (b) Find Rin and Gv . find the maximum allowable value of v̂ sig for which the tran- sistor remains in saturation.116 Section 7. ** = more difficult. What must the relationship of RE to R1 and R2 be? For VCC = 10 V and VBE = 0. and show that by selecting R 1 = R2 Figure P7. design PROBLEMS the circuit to obtain an output current of 0.115 amplitude of the output voltage? = Multisim/PSpice. Problems 497 CHAPTER 7 connected maintains the BJT in the active mode.7 V. * = difficult problem. (c) If v sig is a sinusoid with a peak amplitude v̂ sig . the current that IO will be VCC VCC R2 / R1 + R2 − VBE IO = IO = α 2RE RE + R1 R2 /(β + 1) which is independent of VBE . D = design problem . verify that the MOSFET is operating in saturation with ID = 0.7 V.118 has Vt = 0. and the amplifier output is coupled to a load resistance of 20 k. derive an expression for the output current IO .117 Calculate the overall voltage gain Gv of a common-source amplifier for which gm = 3 mA/V. assuming all transistors to be identical with β infinite. *** = very challenging.5 mA.118 The NMOS transistor in the CS amplifier shown in Fig.116 find the value of R that will result in IO 0. 7. (b) Select a value for RD that results in Gv = −10 V/V.120 = Multisim/PSpice.118 (d) What is the value of resistance Rs that needs to be (c) Find the largest sinusoid v̂ sig that the amplifier can handle inserted in series with capacitor CS in order to allow us while remaining in the saturation region.120 shows a scheme for coupling and 0.119 has Vtp = −0. value of Gv ? (a) Select a value for RS to bias the transistor at ID = 7.120 Figure P7. D = design problem . 498 Chapter 7 Transistor Amplifiers 5 V PROBLEMS 300 k 5 k CC2 vo CC1 CHAPTER 7 120 k 5 k CS vsig 200 k 2 k Rin Figure P7. * = difficult problem.119 The PMOS transistor in the CS amplifier of maintaining saturation-region operation? What is the new Fig. *** = very challenging. VDD 2.3 V. The circuit utilizes dc component.3 mA and VOV = 0. what value can RD be increased to while D *7. ** = more difficult. P7.119 Figure P7. v̂ sig is limited to 50 mV. What is the to double the input signal v̂ sig ? What output voltage now corresponding signal at the output? results? (d) If to obtain reasonably linear operation.7 V and a very large VA . Assume v sig to have a zero amplifying a high-frequency pulse signal.5 V Figure P7.5 V RD RS vo CS Q2 Rsig 50- coaxial cable CC vd1 vo id vsig RD Ri2 = 50 vi Q1 5 mV 2. What must gm2 be? If Q1 is biased at the (a) The NMOS transistor in the source-follower circuit of same point as Q2 . find the voltage gain from X to Z with Z open-circuited. This that can be measured at Y. at the drain of Q1 ? What value of RD is required to provide (b) The NMOS transistor in the common-gate amplifier of 1-V pulses at the drain of Q2 ? Fig. and the input resistance at the gate is 10 M. and terminal Y is connected to a load resistance of 10 k. Transistor Q1 operates as a CS amplifier and a current source delivering a signal current of 50 μA and Q2 as a CG amplifier. ** = more difficult. find the voltage signal is required to present a 50- resistance to the cable. (c) If terminal Z is grounded. 10 k (d) If terminal Y is grounded. For proper operation. its input PROBLEMS resistance is 50 . When the cable is properly terminated. Neglect the Early effect.122 = Multisim/PSpice. to the input of the common-gate amplifier in (b). what is the amplitude of the current pulses Fig. find the voltage gain from signal source to load. and VA = 40 V. D = design problem . kn = 5 mA/V . P7. Find the in the drain of Q1 ? What is the amplitude of the voltage pulses open-circuit voltage gain and the output resistance.121 Figure P7. *** = very challenging. use the results of (a) and (b) to obtain the overall voltage gain (a) Find the values of RS . What is the output resistance of the source follower? (a) 5 V 5 k RD vo Y 2 k X v i2 RG Z 10 k RS 5 V (b) Figure P7. * = difficult problem. neglect the situation is known as “proper termination” of the cable and effect of ro . P7.122(b) has gm = 10 mA/V and a large ro . Problems 499 CHAPTER 7 two MOSFETs whose bias details are not shown and a 50- (e) If terminal X is grounded and terminal Z is connected to coaxial cable. For simplicity. ensures that there will be no signal reflection coming back *7. P7. the v o /v i .122 on the cable.8 V is possible.122(a) has gm = 10 mA/V and a large ro .8 V. largest possible value for RD is used while a maximum signal swing at the drain of ±0.121 The MOSFET in the circuit of Fig. Find the input resistance and the voltage gain. vi (b) Find the values of gm and ro at the bias point.121 has (c) If the output of the source follower in (a) is connected 2 Vt = 0. terminal X is connected to a vo1 signal source having a resistance of 1 M. transistor Q2 having a resistance of 100 k. and RG so that ID = 0. RD .4 mA. D *7. kn = 5 mA/V .S.124 has Vt = 0. P7.2 V. P7. established in (a). D = design problem .6 V.5 M R1 0. (a) It is required to bias the transistor to operate at an overdrive voltage VOV = 0.5 M Figure P7.123 vsig P. show that show that the voltage gain is given by vo 1 + (R2 /R1 ) = vsig (1 + R2 /R1 ) 1+ vo R2 /R1 gm RD =− vsig 1 + R2 /R1 1+ and gm (RD ro R2 )(1 − 1/gm R2 ) 1 R1 Rin = (1 + gm RD ) gm R1 + R2 and find the value of the gain.2 V. and VA = 60 V. Now. What must the dc (a) It is required to bias the transistor to operate at an voltage at the drain be? Calculate the dc drain current ID overdrive voltage VOV = 0. assume that VA is sufficiently large so that we can ignore the Early effect.123 has Vt = 0. The input signal vsig has a zero average. * = difficult problem. *** = very challenging.124 = Multisim/PSpice.124 The MOSFET in the amplifier circuit of 2 2 Fig. ** = more difficult. We shall study feedback formally in Chapter 11. We shall The signal vsig has a zero average. What resistance RD have? value must RD have? (b) Calculate the values of gm and ro at the bias point (b) Calculate the value of gm at the bias point.123 The MOSFET in the amplifier circuit of D **7. what value must the drain at the drain be? Calculate the dc drain current ID . (c) Use the small-signal equivalent circuit of the amplifier to (c) Using the small-signal equivalent circuit of the amplifier. Figure P7. This feedback amplifier and the gain expression should Rin remind you of an op amp utilized in the inverting configura- tion. Fig. 500 Chapter 7 Transistor Amplifiers PROBLEMS D **7.6 V and kn = 5 mA/V . RD R2 VDD = + 10 V vo R1 2 M 500 k RD R2 vsig vo 0. where RD = RD (R1 + R2 ) VDD = + 10 V (d) Evaluate vo /vsig and Rin . What must the dc voltage CHAPTER 7 taking into account VA . and specify the value of I to one significant digit. R2 to 47 k. and RC to 12 k (standard values of 5%-tolerance resistors). the designer varies the resistance levels by a factor of verting configuration. having examined the situation described in Problem 7. P7.S. Use an emitter current of approxi. with the dc signal between base and emitter being as high as 5 mV. that the collector voltage never fall by more than mately 2 mA and a current of about one-tenth of that approximately 0.2 k. Use standard 5% resistors VCC = 5 V. amplifier to operate between a 2-k source and a 2-k (c) The open-circuit voltage gain from base to collector is load with a gain v o /v sig of –40 V/V. *** = very challenging. consistent with the requirement available is 15 V. find values for I. R1 = 27 k.2 V. What base-to-collector open-circuit voltage gain does your design provide? If Rsig = RL = 20 k.9 k. It is required to design the between a source for which Rsig = 2 k and a load of 2 k. what 7. Use standard 5% (see Appendix J). If the amplifier operates with a constant-current source I. (a) Rin 10 k. and β = 100.125 D 7.125 For the common-emitter amplifier shown in does the gain become? Comment.4 V below the base voltage with the in the voltage divider that feeds the base. RE to 7. D = design problem .128 The CE amplifier circuit of Fig. Fig. Rsig = 2 k. The Assume that v sig is a sinusoidal source. D 7.4 k. This feedback amplifier circuit and the gain formula of the source by the amplifier input. We shall study feedback formally in approximately 3: R1 to 82 k. P7.. * = difficult problem. voltage at the base about one-third of the supply. resistance values.125 and estimating the available gain to be approximately –36. R2 = 15 k.125. should remind you of an op amp connected in the nonin. what is the overall voltage gain? Figure P7. let VCC = 15 V. and RC ) to meet the following replace the transistor with its hybrid-π model.128 = Multisim/PSpice. and RC = 3. and find the specifications: values of Rin .125.127 A designer. Problems 501 CHAPTER 7 P. As an experiment. and the overall voltage gain v o /v sig . and the transistor has β = 100. The transistor has β = 100. design an (b) The dc voltage drop across RB is approximately 0. the available supply transistor available has β = 100.3 V/V. RE = 2. RL = 2 k.128 is biased PROBLEMS Calculate the dc bias current IC . Chapter 11. With VCC = 15 V. D 7.126 Using the topology of Fig. ** = more difficult. circuit (i.e. wants to explore the possibility of improvement by reducing the loading Figure P7. RB . The power supply the maximum possible. P7. 129 Rsig vsig in in Figure P7. P7.9 k. 3V Figure P7. draw the small-signal equivalent circuit (a) Find the value of RE to establish a dc emitter current of of the amplifier and determine its overall voltage about 0. v sig is a small sine-wave PROBLEMS (b) Find RC to establish a dc collector voltage of about signal with zero average.5 mA. Rin2 . The transistor β is 100.5 V. gain. find v o /v b2 . (c) For RL = 10 k. Observe that the input resistance of the second stage.130 consists of two identical CHAPTER 7 common-emitter amplifiers connected in cascade. (e) For RL = 2 k. constitutes the load resistance of the first stage. (b) Draw the small-signal equivalent circuit of the entire amplifier and give the values of all its components. R2 = 47 k. 3V *7.129 In the circuit of Fig. determine the dc col- Rsig 2. RC = 6. 502 Chapter 7 Transistor Amplifiers D 7. (d) Find Rin2 and v b2 /v b1 . +0.8 k. R1 = 100 k.130 The amplifier of Fig. *** = very challenging. RE = 3. vsig (c) Find Rin1 and v b1 /v sig for Rsig = 5 k.129. (f) Find the overall voltage gain v o /v sig .130 = Multisim/PSpice. D = design problem .5 k lector current and dc collector voltage of each transistor. ** = more difficult. (a) For VCC = 15 V. P7. * = difficult problem. and β = 100. 134 For the emitter-follower circuit shown in Fig. draw the 7.132 Figure P7. Assume β = 100. P7. gain v o /v i . small-signal equivalent circuit of the amplifier. and v sig is a small sine-wave signal. Problems 503 CHAPTER 7 7. (b) Replacing the transistor by its T model. what is the largest signal at the input? What is the corresponding signal at the output? PROBLEMS 0.131 Rin *7.134. Ana- the BJT used is specified to have β values in the range lyze the resulting circuit to determine the voltage of 50 to 200 (a distressing situation for the circuit designer).133 (a) Find the dc collector current and the dc voltage at the collector. D = design problem .131 In the circuit of Fig.131.134 = Multisim/PSpice. Figure P7.133. Assume that the source Find Rin and the gain v o /v sig . +3V vsig in Figure P7. If the amplitude provides a small signal v sig and that β = 100. find the input resistance constant-current source.133 For the circuit in Fig. P7. *** = very challenging.5 mA 5k Rsig 50 vsig Figure P7. Rin and the voltage gain v o /v sig .132 has β = 100. P7. ** = more difficult.132 The BJT in the circuit of Fig. P7. the BJT is biased with a 7. * = difficult problem. of the signal v be is to be limited to 5 mV. * = difficult problem.135 **7. (b) Replace the BJT with its T model (neglecting ro ). the voltage gain v o /v sig .135 For the emitter follower in Fig. Use β = 100. 504 Chapter 7 Transistor Amplifiers For the two extreme values of β (β = 50 and β = 200). If the dc component of v sig is zero. P7. Figure P7. P7. re . and rπ . VE .136. PROBLEMS find: (a) IE . find Rin .137.7 V. let transistor Q1 have β = 50 and transistor Q2 have β = 100. D = design problem . called a bootstrapped follower: (a) Find the dc emitter current and gm . and VB (b) the input resistance Rin (c) the voltage gain v o /v sig 7. the signal CHAPTER 7 source is directly coupled to the transistor base. *** = very challenging. find the dc emitter current. Use VBE = 0. and the output resistance Rout .137 For the follower circuit in Fig. the current gain io /ii . and 50 A analyze the circuit to determine the input resistance Rin Rin 5 mA and the voltage gain v o /v sig .136 For the circuit in Fig.135. Compare the results with those obtained in (b) to find the advantages of bootstrapping. Assume β = 100. P7. (c) Repeat (b) for the case when capacitor CB is open-circuited. ** = more difficult. vsig 5 Rin Rout Figure P7. 3 Figure P7. and neglect 2 the effect of ro . Neglecting ro .136 **7.137 = Multisim/PSpice. *** = very challenging.138 A CE amplifier has a midband voltage gain of of Q2 . find the voltage gain from the base to the emitter D 7. v o /v b2 . analyze the circuit of emitter follower Q1 to determine If the BJT is biased at IC = 1 mA. find the transmission to the base of Q1 . (b) If a load resistance RL = 1 k is connected to the output (e) Find the overall voltage gain v o /v sig . v e1 /v b1 . AM be? = Multisim/PSpice. In Chapter 10 we will follower fed by a voltage v b2 at its base. ** = more difficult. What will the new values of fL and emitter. and the gain from its base to its at least equal to 2 MHz. (Hint: Consider Q2 as an emitter a higher 3-dB frequency fH = 500 kHz. results in lowering fL and raising fH by the factor 1 + gm Re . v b1 /v sig . Problems 505 CHAPTER 7 (a) Find the dc emitter currents of Q1 and Q2 . and find the input resistance Rib2 looking AM = 100 V/V. and into the base of Q2 . D = design problem . * = difficult problem. terminal. resistance. find the (d) If the circuit is fed with a source having a 100-k dc voltages VB1 and VB2 . a lower 3-dB frequency of fL = 100 Hz. find Re that will result in fH its input resistance Rin .) learn that connecting a resistance Re in the emitter of the BJT PROBLEMS (c) Replacing Q2 with its input resistance Rib2 found in (b). Also. Neglect channel-length modulation. Note that D 8.3 V.1 to obtain an output current obtained. ** = more difficult.1 Both the cascode and Wilson mirrors require at least 1 V The Darlington configuration results in an equivalent BJT 2 or so for proper operation.5-V change in VO . If IREF is 20 μA and technology the Early voltage VA = 5 V/μm. 0. The corresponding (a source follower) results in increased input resistance formula for the BJT case is Ro = 1 + gm Re rπ ro . and Vt = 0. in the BJT case and wider bandwidth in both the BJT and Cascoding can be applied to current mirrors to increase MOS cases. 8. Find the required value of R and the device dimensions.4 V.1.1 to provide an If VO increases by 1 V. Let VDD = 1. problem of the CB and CG configurations. and Multism simulations for all the indicated problems can be found in the corresponding files on the website.2 V. and μp Cox = 80 μA/V .2 with 2 of 5 μm. Also. it is required the value of IREF so that a nominally 80-μA output current is to design the circuit of Fig. what is the corresponding increase in output current of 150-μA nominal value. at D 8. *** = very challenging.3 V and using IREF = 100 μA. An alternative that also solves the Preceding the CB (CG) transistor with an emitter follower β problem in the bipolar case is the Wilson circuit. Q1 and Q2 be matched. what value of VO will the nominal value of IO be obtained? design the current-source circuit of Fig. more appropriately be called a current sink.1 For VDD = 1. The current source is required to operate for VO as whose nominal value is 100 μA. A CS amplifier with a resistance Rs in its source lead has an Preceding the CE (CS) transistor with an emitter follower output resistance Ro 1 + gm Rs ro . IO ? Let VA = 20 V. 8. 8. What is the two transistors having equal channel lengths but with Q2 lowest possible value of VO ? Assuming that for this process having a width five times that of Q1 .1 V. also has a high output resistance. and the BJT version has an output resistance of 2 βro . To simplify matters. Vt = 0.4 Consider the current-mirror circuit of Fig. their output resistances. Note that while the circuit of Fig. find the output the transistors are operating at an overdrive voltage of 0. and to investigate IO .1 should statement.5 V. resistance of the current source. you are to make a reasonable assumption. and Current-Steering Circuits the device W/L ratios and the value of the resistor that sets D 8. find the change in output what IO results? What is the minimum allowable value of VO current resulting from a +0.2: IC Biasing—Current Sources. and kn = 500 μA/V .4 V.5 V.2 Using VDD = 1. Find 2 Current Mirrors. VA = 10 V/μm. It is further required that the circuit operate for Problems identified by the multisim/PSpice icon are VO in the range of 0. PROBLEMS Computer Simulation Problems assume that the nominal value of the output current is obtained at VO VGS . important issues such as allowable signal swing and amplifier For the fabrication-process technology utilized. D = design problem . with a current gain approaching β . channel widths 8.3 V to VDD and that the change in IO intended to demonstrate the value of using SPICE simulation over this range be limited to 10% of the nominal value of to verify hand analysis and design. Vt = Section 8. Find R if Q1 and Q2 are high as 1. the corresponding PMOS circuit is a current source. μn Cox = nonlinear distortion.576 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers stack between the power-supply rails results in the The Widlar current source provides an area-efficient way disadvantage of a severely limited output-signal swing. = Multisim/PSpice.8 V and a pair of matched MOSFETs. * = difficult problem. matched with channel lengths of 0. Instructions to assist in setting up PSpice 2 400 μA/V .5 μm. 8. The (a source follower) solves the low-input-resistance MOS Wilson mirror has an output resistance of gm ro ro . for proper operation of the current source? If Vt = 0. 8. to implement a low-valued constant-current source that The folded-cascode configuration helps resolve this issue.3 Sketch the p-channel counterpart of the current-source if a particular parameter value is not specified in the problem circuit of Fig. (a) Assuming the transistor β is very high.5 V Vtp = −0. 10 μA. If β is specified to be Find the output resistance of the current source Q2 and the a minimum of 80. 2 100 μA/V .0 V VA = 50 V. corresponding to VO changing from 1 V Q4 Q5 to 10 V. 8. how many different output currents are available? Repeat with two of the transistors diode connected and the third used to provide current output.7 A PMOS current mirror consists of three PMOS while the current source continues to operate properly? What transistors. The Early voltage is 90 V. taking into account the finite β. and Assume that β remains constant at 100 over the current |VAp | = 5 V/μm.1 mA.7 for the of the current sink Q5 with voltages at its drain as low as case in which Q2 has m times the area of Q1 . It is required to design the circuit to provide an Figure P8. 2 CHAPTER 8 8. find the range of VBE and IO corresponding to IREF increasing from 10 μA Figure P8.0 V 8. what is the largest current transfer ratio pos- output resistance of the current sink Q5 . μp Cox = of 10 μA to 10 mA. D = design problem .5 V. I REF 8.6 The current-steering circuit of Fig. Vtn = 0.7 when IREF Q1 and Q2 are matched and IREF = 1 mA. neglecting the Early effect? I3 8. Use the minimum possible device widths 0. For each possible input-diode combination. 8. namely. β = 50.6 V.6 is fabricated in (b) Find the range of IO corresponding to IREF in the range 2 a CMOS technology for which μn Cox = 400 μA/V . If β of the pnp transistor is 50. 1 mA. Specify the widths of all devices and the value of R.7 for IO the case in which Q1 and Q2 are identical devices having −17 Q1 Q2 IS = 10 A.5 μm.12 utilizes a pair −15 of matched pnp transistors having IS = 10 A.9 Consider the basic BJT current mirror of Fig. 8.8 V and proper operation 8. give the values of the PROBLEMS Q3 Q4 output currents and of the VSG that results. and I5 = 80 μA. VAn = 5 V/μ m. both as an absolute value R and as a percentage. 8. Assume that Q2 remains in the active mode.6 output current IO = 1 mA at VO = 1 V. Problems 577 outputs. P8.12 The current-source circuit of Fig. what is the current gain (or transfer ratio) IO /IREF for the case of identical Q1 Q2 Q3 transistors. I2 = 100 μA. for voltages at its drain as high as +0.5 For the current-steering circuit of Fig.1 mA to 5 mA but that at IC 10 mA and at IC circuit so that IREF = 20 μA. and 1. design the range 0. find IO in terms of IREF and device W/L ratios.8 V. Show that the cur- –0. * = difficult problem. and neglect the Early effect. and L = 1. ** = more difficult. What values of IREF and R are needed? What is the maximum allowed value of VO *8. find the change in IO . Specify IO corresponding to IREF = 10 μA. and 40 μm.8 Consider the basic bipolar current mirror of Fig. 10 μm. (8. 20 μm.5 to 10 mA.19). I3 = I4 = 40 μA. β = 50.11 Consider the basic BJT current mirror of Fig. P8. kp = 100 μA/V .5. When the diode-connected transistor is VDD supplied from a 100-μA source. Neglecting the effect I4 I2 I5 of finite β. rent transfer ratio is given by Eq.7. one diode connected and two used as current change occurs in IO corresponding to VO changing from the = Multisim/PSpice. D 8. P8. All transistors have Vt = 0. Note that β variation with cur- needed to achieve proper operation of the current source Q2 rent causes the current transfer ratio to vary with current. If all devices have L = 0. *** = very challenging. sible if the error introduced by the finite β is limited to 10%? 1. D 8.0 μm but three different widths. and 10 mA.10 Give the circuit for the pnp version of the basic current mirror of Fig. P8.13 = Multisim/PSpice. Find I.12 maximum positive value to –5 V? Hint: Adapt Eq.13. ** = more difficult. 578 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers VCC 3V 8. V1 .14.6 k 5 V Figure P8.7 V all branches in the circuit of Fig.13 Find the voltages at all nodes and the currents through – 2. * = difficult problem. Assume VBE = 0.7 V VO CHAPTER 8 IREF IO R Figure P8. D = design problem . (8. V2 .21) for this case as: ⎡ ⎤ 3 − VO − VEB 1+ ⎢ |VA | ⎥ IO = IREF ⎢ ⎣ ⎥ ⎦ 2 1+ β 8. P8. V4 . and V5 for (a) R = 10 k and (b) R = 100 k. let VBE = 0. Q1 Q2 + 2.14 10 V 5 V R5 10 k R2 8 k R1 20 k R4 5 k R3 3.14 For the circuit in Fig. V3 . Figure P8. *** = very challenging.7 V and β = ∞.7 V and PROBLEMS β = ∞. Also. Here Q1 is a common-source amplifier fed with have VBE 0. W2 = 50 μm. 2 μn Cox = 500 μA/V . VDD Q2 Q1 Z WL Q 2 2 Q3 W3 L vO Q3 Q4 Q5 vI Q1 RL Figure P8. forced into X. Now.7 V and large β. 8. io /ii . If the input bias current is 100 μA.16 for small-signal analysis. 8. and 0.5 mA. if X is connected to a +5-V supply through a 10-k resistor. Assume β to be large. * = difficult problem. and that a current equal to I flows ii through terminal Z.21 It is required to find the incremental (i.12(a) 2 have equal channel lengths. *** = very challenging.2 mA. Replace the BJTs with their hybrid- π models and find expressions for Rin .19 VEE *8. find W1 .16 is known as a current component of the output voltage v O and hence the small-signal PROBLEMS conveyor.17 The MOSFETs in the current mirror of Fig. what current flows through Z? Q1 Q2 8. show that a current equal to I flows through terminal Y. W1 = 10 μm. 0. P8. 1 mA. Assume that the BJTs mirror Q2 –Q3 . and Ro .20 shows a current-mirror circuit prepared Figure P8. Ais . μn Cox = 400 μA/V and VA = 20 8.20 D 8.19 shows an amplifier utilizing a current currents of 0. and VA = 10 V/μm. D = design problem . an input resistance multiple-mirror circuit using power supplies of ±5 V to create of 500 . where VGS is the gate-to-source dc bias voltage dissipated in your circuit? of Q1 and v i is a small signal to be amplified. If the input bias current is 200 μA. (b) With Y connected to ground. Problems 579 CHAPTER 8 D 8. a current I is is the output short-circuit current. and terminal Z is connected to a voltage that keeps Q5 in the active region. find Rin .10. and 2 mA. corresponding transistors are matched.12(a) have equal channel lengths of 0. show that a virtual ground Ro io appears at X. and an output resistance of 20 k.5 μm. ** = more difficult.. voltage gain v o /v i . design a to obtain a short-circuit current gain of 4.20 Figure P8. and hence Y X the total resistance between the drain of Q1 and ground. Assume ro rπ .e. find the small-signal resistance of the diode-connected transistor Q2 in terms of gm2 . What is the total power v I = VGS + v i .19 Figure P8.4 mA. source currents of 0. Find the signal *8. Figure P8. where io (a) Assuming that Y is connected to a voltage V . and all transistors are operating Rin in the active region. What is the voltage gain of the CS amplifier Q1 ? Neglect all ro ’s. 8. and L resistance of each of the diode-connected transistors shown in = Multisim/PSpice.8 mA and sink 8. that a voltage equal to V appears at terminal X. small-signal) V/μm.18 The MOSFETs in the current mirror of Fig. W2 .16 The circuit shown in Fig. and Ro .15 Using the ideas embodied in Fig. 11. D = design problem .7 V.2% or less. What is the lowest voltage at the output for which proper D 8. For IREF of 100 μA D 8.27 Find the intrinsic gain of an NMOS transistor fabricated 2 in a process for which kn = 400 μA/V and VA = 10 V μm.5-μm process specified in Table J. 8. assuming that β remains unchanged? What are the new values of Av o and Ro ? If the amplifier is fed with a signal source having Rsig = 5 k and is connected to a load of 100-k resistance. 580 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers Fig. If the transistor is operated with VOV = 0.3 μm fabricated in Fig. P8. Av o .28 An NMOS transistor fabricated in a certain process is found to have an intrinsic gain of 50 V/V when operated at Figure P8. what will the voltage at node x be? If 0.3: The Basic Gain Cell width W. For each of these currents. and Ro . 8. let the three transistors be matched and specified to have a collector current of 1 mA at VBE = 0.24 For the base-current-compensated mirror of Fig.21. and the bias current I. let μn Cox = 200 μA/V and W/L = 10.) find gm . * = difficult problem. 100 μA. What must ID be? What reference current source) is approximately 2VT /IREF . Find the intrinsic gain for ID = 25 μA and ID = 400 μA. Evaluate value of gm is realized? Rin for IREF = 100 μA. ** = more difficult. CHAPTER 8 I I v o /v sig . find the required percentage difference between the actual and ideal value of values of L.5 mA.29 Consider an NMOS transistor fabricated in a 2 and assuming β = 100. (Hint: Q3 is operating at a current IE3 = 2IC /β. = Multisim/PSpice. 8. of 0. ID = 100 μA with VOV = 0. input to each output. Also. The transistor has a 0. and that find gm .32 For an NMOS transistor with L = 1 μm fabricated in Q1 and Q2 .11.1 mA.5 V and ID = 100 μA. IO /IREF ? If the deviation from unity is to what is the highest instantaneous voltage allowed at the be kept at 0. Also. what is the maximum possible number drain? of outputs for BJTs with β = 150? 8.2 V.33 For an NMOS transistor with L = 0.8-V D 8.26 Consider the CE amplifiers of Fig. and 1 mA. and VA = 100 V. Using VOV = 0.13(b) for the case 2 the MOSFET. What is the resulting current transfer ratio from the supply. and A0 if the device is operated with VOV = 0. which gm changes from its value at ID = 100 μA.2 V. Find Rin .18-μm process specified in Table J. what value of I is required. find the overall voltage gain. what is the change in Vx ? What is 5 V/μm. 8. Assume the availability of a single dc outputs. ro . If a 2-mA/V transconductance is required. what must ID and W be? (a) (b) 8. 8. ro for both devices.11 to n device. If it is required to raise Rin by a factor of 5 by changing I. Replace each transistor with its T model and the 0.25 V is required to have a gm equal to that of an npn show that the incremental input resistance (seen by the transistor operated at IC = 0. IO . W/L.1 mA.2 V. neglect r0 .22 For the base-current-compensated mirror of Fig. Present your results in a table. It is required to obtain an intrinsic gain of 20 V/V the value of IO obtained with VO = Vx in both cases? Give the and a gm of 2 mA/V.31 An NMOS transistor operated with an overdrive voltage *8.23 Extend the current-mirror circuit of Fig.1 in Appendix J.18-μm technology for which kn = 400 μA/V and VA = IREF is increased to 1 mA. rπ . find the required device Section 8.13(b) when operated at I = 10 μA. the 0. 8. Neglect of I = 0. For PROBLEMS 8. and A0 for the CE amplifier of 8.30 Sketch the circuit for a current-source-loaded CS current-source operation is maintained? amplifier that uses a PMOS transistor for the amplifying +1. where IC is the operating current of each of 8.25 Find gm .5-μm channel length and is operated at VOV = 0. *** = very challenging. 8. β = 100. find W.1 in Appendix J. and A0 obtained when the device is operated at VA = 10 V. ro . find the factor by 8. Assume that the dc bias current I = 0.2 V. Assume β = 100 and remains constant as I is varied. ro .21 an ID of 100 μA. Verify that you were justified D 8. and VDD = 1.42 Figure P8.2 V. BJT Cell MOSFET Cell D 8.43 The NMOS transistor in the circuit of Fig. cess whose parameters are given in Table J. What is the bias current of the transistor for which equal length L operating at I = 100 μA and VOV = 0.5 V. find VGS . design a you found VGS . Assuming that 2 process for which μn Cox = 400 μA/V and VA = 5 V/μm. (a) What values of gm . the overall voltage gain in terms of gm and ro of Q1 and Q2 . 8.5 μm and are to be operated at ID = 100 μA and |VOV | = 0. and (W/L)2 . A0 = 18 V/V? Determine the required values of VG .42 D 8. gm . operated at VOV = 0.15(a) is fabricated in a process for which μn Cox = 2μp Cox = 200 μA/V .8 V. ro . feedback network and VDS . (W/L)1 . 50 μA with VOV = 0.34 Fill in the table below. 8.18-μm 2 CMOS technology for which μn Cox = 400 μA/V . gm .18-μm pro. and Av .42 shows an IC MOS amplifier formed 0. find the values the effect of ro .5 V. ro . and VDD = 2. Find the required values of VG . The *8. overdrive voltage of 0. D 8. Then find the dc current in the of gm and ro . If Q1 and Q2 are to be operated at equal overdrive voltages. 8. (W/L)1 . It is required to design the circuit 2 CMOS process for which μn Cox = 400 μA/V and VA = to obtain a voltage gain Av = −40 V/V. what do gm . D 8. Problems 581 8.40 The circuit in Fig.5-μm channel length and is operated with an Vt = 0. It was fabricated in a 0.36 μm and W/L = 8. Vtn = −Vtp = 0. let β = 100 and current-source-loaded CS amplifier for operation at I = CHAPTER 8 2 VA = 100 V. if W/L is held at the same value but L is made 10 times larger. and A0 are obtained? (b) If ID is increased to 100 μA. ro . find an expression for and 2.5 mA. ** = more difficult. P8. find the required value of |VOV | if |VA | = 5 V and the The device has a channel length twice the minimum and is gain required is 400 V/V. μ p C ox = 8.25 V.15(a) is fabricated in a 0. For the MOSFET.37 An NMOS transistor is fabricated in the 0. and A0 become? (c) If the device is redesigned with a new value of W so that it operates at VOV = 0. What must W be for the NMOS (a) Neglecting the dc current in the feedback network and transistor to operate at ID = 100 μA? Also.54 μm and W/L = 8. Use devices of 5 V/μm. open-circuit voltage gain of −100 V/V.36 A CS amplifier utilizes an NMOS transistor with L = 8. VAn = VAp and that the biasing current sources have output Find the values of gm and A0 obtained at ID = 25 μA. and VA = 20 V. and A0 . what do VOV . ro .1 in Appendix J. VAn = 5 V/μm. what gains result? Figure P8.5 V. The amplifier is to have an W/L = 40.41 The circuit in Fig. VAn = VAp = 20 V/μm.3 V. find VOV . *** = very challenging. and VA = 10 V. Specify L and W/L.38 Find A0 for an NMOS transistor fabricated in a CMOS 2 process for which kn = 400 μA/V and VA = 6 V/μm.15 V. |VOV |. 250 μA. (e) Which designs and operating conditions produce the lowest and highest values of A0 ? What are these values? In each of these two cases. 2 Bias Current Vtn = −Vtp = 0.18-μm CMOS by cascading two common-source stages.25 V and ID = 10 μA. resistances equal to those of Q1 and Q2 . * = difficult problem. VAp = 2 L = 0. The two transistors have PROBLEMS L = 0. kn W/L = 2 mA/V . = Multisim/PSpice.18-μm 5 V/μm. D = design problem .25 V for ID = 100 μA. L. Assume that the current-source load is ideal. It was fabricated in a 0. let μn Cox = 200 μA/ V . and A0 become? (d) If the redesigned device in (c) is operated at 10 μA. For the BJT.35 A CS amplifier utilizes an NMOS transistor with 100 μA/V .43 has 2 transistor has a 0.5 V. (W/L)2 .39 Using a CMOS technology for which in neglecting the current in the feedback network when 2 kn = 200 μA/V and VA = 20 V/μm. find the voltage (c) Find the small-signal input resistance Rin . 2 assuming that their VBE 0. For Q2 . For Q3 . what are the drain currents ID1 and ID2 ? Figure P8.47 Consider the circuit shown in Fig. What is the amplitude of the output sinusoid resulting? (Note: In practice.5 V. v o /v i . having kn (W/L)1 = kp (W/L)2 = 1 mA/V and Vt = 2 2 M Rin 0. find the small-signal voltage gain and output resistance. the amplifier would have a feedback circuit that caused it to operate at a 1.3-V supply and transistors for which Vt = 0.4.) Figure P8.49 is operating as Example 8.7 V and that Q2 has five times W = 40 μm.) (b) Find the small-signal voltage gain. ro2 and hence the total resistance at the collector of Q1 .43 (b) For ro = ∞. 3 M (e) For operation as a small-signal amplifier around a bias vo point at v O = VDD /2. kn = 100 μA/V . * = difficult problem. 8. If Q2 and Q3 are to be operated at the same overdrive voltage as Q1 .0 V point near the middle of its linear region. the saturation region? Vt = 0.16(a) when (e) For what range of output signals do Q1 and Q2 remain in 2 fabricated with a process for which kn = 4kp = 400 μA/V . VA = 100 and W = 20 μm. what is the voltage gain of the amplifier from G to D? (Hint: Replace the transistors with their small-signal models. What is the (c) For finite ro (VA = 20 V). (Note that the biasing arrangement for Q1 is not 3.0 V Recall that Q2 and Q3 are matched.48 are matched. The resistance R = 1 M. Find IREF and (W/L)1 to obtain a voltage gain of –40 V/V and an output resistance of 100 k. V.48 8. and VA = 5 V. D 8. what must their W/L ratios be? Q2 8. find the value of the dc component that will result in the maximum possible signal swing at the output Q1 with almost-linear operation. (a) Neglecting the finite base currents of Q2 and Q3 and For Q2 and Q3 . ** = more difficult. find ro1 and ignore the effect of VA .49 Transistor Q1 in the circuit of Fig. What will the extent of the a CE amplifier with an active load provided by transistor Q2 . (a) For G and D open. D = design problem . P8. using a Q2 and Q3 . find the value of I. gain v d /v sig .48 The MOSFETs in the circuit of Fig.45 Consider the CMOS amplifier analyzed in Example 8. CHAPTER 8 vi **8. R If v I consists of a dc bias component on which is superimposed G D a sinusoidal signal. For simplicity. what is the voltage gain from peak of the largest output sine-wave signal that is possible G to D and the input resistance at G? while the NMOS transistor remains in saturation? What (d) If G is driven (through a large coupling capacitor) from a is the corresponding input signal? source v sig having a resistance of 20 k. *** = very challenging.5 V.44 Consider the CMOS amplifier of Fig. find IREF .8 V and L = shown. P8.) 2 1 μm. = Multisim/PSpice. (b) If Q1 and Q2 are specified to have VA = 30 V. 582 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers (b) What are the extreme values of v O for which Q1 and Q2 PROBLEMS just remain in saturation? 200 A (c) What is the large-signal voltage gain? (d) Find the slope of the transfer characteristic at v O = VDD /2.46 The power supply of the CMOS amplifier analyzed in 8. kp = 50 μA/V and VA = 50 V. linear region at the output become? which is the output transistor in a current mirror formed by **8. For Q1 . 8. the area of Q3 . W = 10 μm. 1.4 is increased to 5 V. (a) If Q1 is to be biased at 100 μA.16(a). what is the maximum avail- must be able to swing to within approximately 0. Find Rin and io /isig . Av .55.55 In the common-gate amplifier circuit of Fig.53 VCC 3 V to deliver a current of 0. * = difficult problem. PROBLEMS vi Q1 3 V IO vo VBIAS 46 k I Rs Q3 Q2 Figure P8.51 A CG amplifier operating with gm = 2 mA/V and Rs Rs ro = 20 k is fed with a signal source having Rs = 1 k and is loaded in a resistance RL = 20 k.2 V of the able output resistance of the current source? Assume that the power-supply rails (i.54 shows a current source realized using a current mirror with two matched transistors Q1 and Q2 .4: The CG and CB Amplifiers 8.2 V to 1. from 0. through the load RL . = Multisim/PSpice. gm = 1 mA/V and has VA = 10 V.54 Figure P8.53 It is required to design the current source in Fig. by and all transistors have |Vt | = 0. 2 RL = 20 k. CHAPTER 8 what percentage does the current gain change? Can you see (d) Find Rin . Design for a dc bias current of 50 μA. 8. Two D 8.49 D 8. If RL increases by a factor of 10.3 V. VDD = 1. and use devices with the same channel length.5 V.2 mA with an output resistance of 500 k. and vo /vsig . P8.e. kp = 86 μA/V .52 A CG amplifier operating with gm = 2 mA/V and ro = 20 k is fed with a signal source having a Norton Figure P8.8 V. and Ro . and VAp = −6 V/μm. kn (W/L)n = kp (W/L)p = 4 mA/V . 8.18-μm process for which kn = the output resistance of the current source. D = design problem . Problems 583 (c) Find rπ 1 and gm1 assuming that β1 = 50. and the voltage voltage at the common-gate node is approximately constant. Design for VOV = 0.8 V and |VA | = 20 V.50 It is required to design the CMOS amplifier of equal resistances Rs are inserted in the source leads to increase Fig. *** = very challenging. Rout . If Q2 is operating at 2 2 387 μA/V . If the channel length is an integer multiple of the minimum 0. and if the maximum allowed VAn = 5 V/μm. The output voltage dc voltage drop across Rs is 0. gain must be at least 10 V/V. what channel length would be required. The amplifier is loaded in a resistance 8. The transistor has VA = 20 V and Vt = 0.6 V). the effectiveness of the CG as a current buffer? D 8.18 μm. Find Rin . where io is the current Q2 and Q3 are matched. what channel length is needed and what W/L ratios 100 A are required? If it is required to raise the gain by a factor of Rout 2.16(a) utilizing a 0.. ** = more difficult.5 V.54 equivalent composed of a current signal isig and a source resistance Rs = 20 k. Vtn = −Vtp = 0. and by what factor does the total gate area of the circuit increase? Q1 Q2 Section 8.53 Figure P8. P8.2 V and specify Rs and VBIAS . 2 re .59 (f) How large can vsig be (peak-to-peak) while maintaining saturation-mode operation for Q1 and Q2 ? 8. Let β = 100.) The output at vo the collector is represented by its Norton equivalent circuit. use Eq.55 C C Rout The signal vsig is a small sinusoidal signal with no dc kisig component. vsig Rin 0. P8.7 V. isig Rsig = 10 k (c) Find the value of Rin . Let β = 100. 10 re . (a) Neglecting the effect of VA .56 For the CB amplifier. (b) Find the values of gm1 and ro for all transistors. Figure P8. The BJT is specified to have β = 100 and VA = 50 V. β re . 1000. and 1000 re . and VA = 100 V.59 shows a CB amplifier fed with a signal current isig having a source resistance Rsig = Q3 Q2 10 k. That is.60. RL . RL (Note that the bias arrangement is not shown. Figure P8. find Rin as a multiple of re for RL /ro = 0. Specifically. what is the tabular form. VBE = 0. 5V Rout β(Re /re ) 1+ ro β + 1 + (Re /re ) Generate a table for Rout as a multiple of ro versus Re as a 4. corresponding change in collector current? 8. (β/2) re .1 mA Figure P8. it passes Figure P8.60 = Multisim/PSpice. find the collector current I and the output variation of the input resistance Rin with the load resistance resistance. Present your results in of 10 V while the BJT remains in the active mode. (e) Calculate the voltage gains vo /vi and vo /vsig . find the dc drain current of Q1 and the required value of VBIAS . If the collector voltage undergoes a change 10. (8. the CB amplifier functions as a current buffer. 100. when fed with a current signal. 8. Rout Find the value of the current gain k and the output resistance CHAPTER 8 100 A VBIAS Q1 Rout .58 Show that for the CB amplifier. D = design problem .3 V PROBLEMS it to the collector and supplies the output collector current at a high output resistance.3 k multiple of re with entries for Re = 0. ** = more difficult. (d) Find the value of Rout .60 For the constant-current source circuit shown in 8. * = difficult problem. The BJT is specified to have β = 100. 584 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers 3. Note that k is the short-circuit current gain and should be 50 vi evaluated using the T model of the transistor with the collector short-circuited to ground. and ∞. *** = very challenging. 1. re .57 What value of load resistance RL causes the input resistance of the CB amplifier to be approximately double the value of re ? I 8.63) to explore the Fig.59 As mentioned in the text. which. gm1 = 2 mA/V and Ro = 200 k. VA = 5 V/μm. In the table. VOV ). what advantage is obtained as I is D 8.5: The Cascode Amplifier I = 0.01 mA.33 is operated at a IRo = L VOV current of 0.2 V. Assume that VSD for the D 8. what channel (a) For each current value.1 mA and (b) I = 0.2 mA with all devices operating at VOV = 0. Find the figure-of-merit IRo for the three is the maximum possible factor by which the output resistance cases of L equal to the minimum channel length. the cascode transistor is current source as load and which has the same values of gm required to raise the output resistance by a factor of 50. show that if the two transistors are identical. Use identical transistors Fig.2 V. ** = more difficult. and I.32. Now consider the case of (c) Contrast the performance obtained from the circuit with transistors that have VA = 4 V and are operated at VOV of 2 the largest area with that obtained from the circuit with 0. what must its VA be? If the process technology specifies VA as 5 V/μm. where n is the value of W/L for the case PROBLEMS Section 8.66 The cascode amplifier of Fig. Complete the entries the BJT has β = 100 and is biased at IC = 0. Use a 0.18-μm technology for which connected in the emitter lead of a CE BJT amplifier. 8.65 Design the cascode amplifier of Fig.2 V. of the table at the bottom of the page. 8. What is the value resistance Ro are related by of the minimum permitted output voltage? 2 2VA 2 8.62 In a MOS cascode amplifier. D = design problem . Give W/L and the area 2WL in terms of n. Also. W/L. *** = very challenging. twice the can be raised. transistor is operated at VOV = 0.64 For a cascode current source. Problems 585 CHAPTER 8 8. and design for the maximum the current I supplied by the current source and the output possible negative signal swing at the output. (b) 10. and kn = 400 μA/V . 8. operated at VOV = 0. and at what value of Re is it achieved? Assume minimum.e.. increased.25 V. the current I see in Chapter 10 that the amplifier bandwidth increases supplied by the current source 2 and the output resistance Ro with gm . If the and Ro as the current-source transistors.5 mA. 8. and (c) 50. and three times the minimum. * = difficult problem. = Multisim/PSpice.5 mA. let μp Cox = 100 μA/V . what is price paid for the increase length must the transistor have? in Ro and Av obtained as L is increased? (b) For each value of L. required and the output resistance realized for the two cases: (a) I = 0.63 For a cascode current source such as that in Fig. such as that in Determine L.32. and what is the price paid? (Hint: We will show that if the two transistors are identical. Av denotes the gain obtained in a cascode amplifier such as that in Fig.20 V.) are related by IRo = 2 VA /VOV .18-μm technology 2 for which Vtn = 0. when Now consider the case of a 0. raises the VA = 5 V/μm and let the transistors be operated at output resistance by a factor of (a) 5.61 Find the value of the resistance Re . What VOV = 0. VG2 . D *8.30(a) to obtain two devices is the minimum required (i.33 that utilizes our D 8.5 V. Find the W/L ratios the smallest area. 8. If all devices are matched. consider the situation in Fig. 8. VG2 = 0. Find gm1 . and (a) (b) VA = 5 V. By what factor is v y smaller than v x ? (c) ix Figure P8.69. Ro . P8. the output resistance of PROBLEMS two circuits shown in Fig. Here we have grounded the input terminal (i. which is operating at the same bias current Q1 and has the same minimum voltage requirement at the drain as in the circuit of Fig.70(c). P8.32 to provide an output current of 100 μA. P8.70(b) and (c). for the following specifications: gm1 = 1 mA/V and Av = −280 V/V. 8. vy (b) Compare these values to those of the cascode circuit in Fig.33 constant. P8. D 8.4 V. Specifically. VA = 5 V/μm for both NMOS and PMOS devices and that CHAPTER 8 2 μn Cox = 4 μp Cox = 400 μA/V . Assume that suitable bias voltages have been chosen.70(b). 8. the output resistance of the current source. The current source is to have the widest possible signal swing at its output. and neglect the Early vi WL vi W4L effect in determining the W/L ratios.70(b) is a CS amplifier in which the channel length has Rop . Assume that for the available fabrication process. and o is vi double that of the original circuit.71 Consider the cascode amplifier of Fig. and have equal Vt of 0.70 In this problem we investigate whether. ** = more difficult. that is. Ron .3 V.6 V. D = design problem . and denoted the voltage change that results at the drain of Q1 by v y . the overall output resistance.e. Determine the required channel length L.3 V. Use VDD = 3. VG3 = 0.4 V. kn1 = kn2 = kp3 = kp4 .67 Design the CMOS cascode amplifier in Fig. Av . P8. P8. been quadrupled relative to that of the original CS amplifier in Fig. gm is half that of the original circuit. tive to cascoding. as an alterna. Design for VOV = 0. and specify the values of the transistor W/L ratios and of VG3 and VG4 . we wish to compare the operating? What is the allowable voltage range at the output? = Multisim/PSpice. 586 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers All devices have VA = 4 V. and the voltage gain.9 V. and VDD = 1. 8.70(a) while the drain bias current has been kept D 8. * = difficult problem. the bias current I. What is the highest allowable voltage at the output? What is I the value of Ro ? vo 8. and assume the PMOS transistors 2 to have μp Cox = 60 μA/V .33 with the dc Figure P8.68 Design the circuit of Fig. vo vo and the W/L ratio for each of four transistors. *8.7 V. Fig.2 V. The circuit in the amplifier. applied vi WL a small change v x to the output node.8 V.70 vx (a) Show that for this circuit VOV is double that of the original v Q2 circuit. *** = very challenging. To quantify this “shielding” property of the cascode. reduced v i to zero).69 component at the input VI = 0.69 The cascode transistor can be thought of as providing a “shield” for the input transistor from the voltage variations VBIAS WL at the output.. Vtp = −0. VG4 = 0.25 V. we can simply increase the channel length what is the overdrive voltage at which the four transistors are L of the CS MOSFET. Use the samechannel length I I L for all devices and operate all four devices at VOV = 0. all in terms of v i . = Multisim/PSpice. (Hint: Use the current-divider rule at the drain of Q1 . The amplifier is fed with 8.34(a) has identical CS and CG transistors that have useful in designing the circuit so as to allow for the required W/L = 5. v 2 . 2 and μp Cox = 100 μA/V . Assume. design for the minimum allow- v3 i5 able voltage across each transistor. and VA = with all dc voltages replaced with signal grounds.72 A CMOS cascode amplifier such as that in amplifier circuit. *** = very challenging.13-μm CMOS fab- R1 rication process available has Vtp = −0. i5 . As well. Q5 ) supplying a current I. Use devices with L = 0. and v 3 . R2 . and the W/L ratios of the transistors.4 μm/0. and a cascoded current source (Q4 . for simplicity. and R3 . all in terms of v i . we are assuming that the four transistors have the same gm and ro . VG3 .75 Figure P8. i6 . i2 . and operate at VOV = 0. sketch and clearly label the waveforms of v 1 . VG2 . VA = −6 V/μm.4 V. Knowledge of this signal distribution is very Fig. What is the value of Ro achieved? Q3 ro VDD = 1. v 2 .73 parameters gm and ro . Specify VG1 .74 to provide I = 0. supplying a current 2I.36 μm and biased at I = 0.2 mA.4 μm. D = design problem . that is. For simplicity.74 vi *8. P8.2 V. and v 3 . Figure P8.73 The purpose of this problem is to investigate the signal PROBLEMS a signal v i . ** = more difficult. 8.2 mA and the largest possible sig- nal swing at the output. i4 . 5 V/μm. Q4 ro D 8. currents and voltages at various points throughout a cascode (a) Determine R1 . Assume gm ro 1. (d) If v i is a 5-mV peak sine wave and gm ro = 20. The 0.) (c) Determine v 1 .74 Design the double-cascode current source shown in i6 i7 Fig.8 V R2 i4 v2 VG1 Q1 Q2 ro VG2 Q2 R3 VG3 Q3 i3 Ro v1 I i1 i2 Q1 ro Figure P8.73 shows a CMOS cascode amplifier 2 fabrication process has μn Cox = 400 μA/V . that all transistors have equal Figure P8. (b) Determine i1 . The signal swings. i3 . At what value of RL does the gain become –100 V/V? we have explicitly shown the resistance ro of each of the What is the voltage gain of the common-source stage? four transistors. * = difficult problem. Problems 587 CHAPTER 8 8.75 shows a folded-cascode CMOS amplifier utilizing a simple current source Q2 . and i7 . Note that the short-circuit transconductance is determined by short-circuiting vo to D *8.2 mA.80 shows four possible realizations of the ground and finding the current that flows through the short β = 100 folded cascode amplifier. VA = 100 V.88) to show that for a BJT cascode current CHAPTER 8 Ro1 source utilizing identical pnp transistors and supplying a vi Q1 Q3 VG3 current I. 8. Assume that the BJTs have circuit.76 A cascode current source formed of two pnp transistors for which β = 50 and VA = 5 V supplies a current of 0.80 Figure P8. 0.80 = Multisim/PSpice.1. D = design problem . Ro5 8. VG2 Q2 What is the output resistance? Ro2 Rin3 8. 8. and that both the BJTs and the MOSFETs have VA = 5 V.38 for the Q5 case all transistors have equal β and ro . Show that the voltage VG5 Ro gain Av can be expressed in the form 1 VA /VT Av = − 2 VT VA + (1/β) Figure P8. the gain is independent of the bias current I! indicated. Let β = 50.75 Evaluate Av for the case VA = 5 V and β = 50.79 A bipolar cascode amplifier has a current-source load (b) Find the amplifier output resistance Ro . 588 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers VDD (d) Find the overall voltage gain v o /v i and evaluate its value PROBLEMS for the case gm1 = 2 mA/V and A0 = 30. *** = very challenging.2 mA. approximately equal to gm1 . ** = more difficult. * = difficult problem.0 mA. (8. with an output resistance βro .78 Consider the BJT cascode amplifier of Fig.77 Use Eq. 8. Now find Ro for the cases of I = 0.5. 2I 2I Q2 VBIAS Q2 VBIAS vI Q1 vI Q1 vo vo I I (a) (b) Figure P8. Gm vi . Ro3 VA vo IRo = VT VA + (1/β) Ro4 Evaluate the figure-of-merit IRo for the case VA = 5 V and VG4 Q4 β = 50. and (c) Show that the short-circuit transconductance Gm is I = 0. Find the voltage gain Av . Note that except for the fact that β depends on I as a second-order (a) Give approximate expressions for all the resistances effect. and 1. Assume the current sources are ideal.6: Current-Mirror Circuits with Improved Performance 8. L = 1 μm.80 continued Let I =100 μA. * = difficult problem. calculate Gm . 2 μn Cox = 160 μA/V . and VA = 10 V. Ro . ** = more difficult. Ro . *** = very challenging. such vi Q1 as that shown in Fig. Refer to Fig. Given the following data. Problems 589 CHAPTER 8 2I 2I Q2 VBIAS vI Q1 Q2 VBIAS vI Q1 PROBLEMS vo vo I I (c) (d) Figure P8. I 8.6 V. The reference current IREF is 20 μA. What output current results? What are the voltages at the gates of Q2 and Q3 ? What is (a) the lowest voltage at the output for which current-source Figure P8. Comment on your results. all transistors have Vt = 0.81 continued VB2 Q2 Section 8. Width W1 = W4 = 4 μm. W/L = 25.2 V. μn Cox = 400 μA/V . D = design problem . and W2 = W3 = 40 μm. P8.81 operation is possible? What are the values of gm and = Multisim/PSpice.8 V vi Q1 VDD I (b) vo Figure P8.81. β = 125. VA = 1. For each circuit determine Rin . and assume that the MOSFETs are operating VDD at VOV = 0.82 In a particular cascoded current mirror. 8.39.81 In this problem. and Av o . and Avo for the circuits (a) and (b): VG2 Q2 2 I = 100 μA. we will explore the difference between vo using a BJT as cascode device and a MOSFET as cascode device. 87 For the Wilson current mirror of Fig.5 V. P8. If the power supplies available are ±2. obtain current gain β.83 *8.5 V.88 Consider the Wilson MOS mirror of Fig. what is the highest voltage possible at the output terminal? Figure P8.84 Consider the Wilson current-mirror circuit of Fig. 8.83.7 mA. by neglecting the Early effect. Assume all transistors to be matched with (b) Noting that Q1 and Q2 are operating at different VDS . CHAPTER 8 Figure P8. Here the output transistor is “split” (a) Obtain an estimate of VOV and VGS at which the three into two matched transistors. D 8. a generated for β = 50? diode-connected transistor Q4 can be added to the circuit = Multisim/PSpice. 0.5 V. 400 μA/V . μn Cox = 2 VA = 100 V. Q3 and Q4 .1 mA.4 mA.85 D 8. Find IO1 and IO2 transistors are operating. and 0.2 mA. 8. What is the change in IO corresponding to a change of +10 V in the voltage at the collector of Q3 ? Give both the *8.86 Use the pnp version of the Wilson current mirror to design a 0.40. with W/L = 10.83 Find the output resistance of the double-cascode current mirror of Fig. *** = very challenging.2 mA. Vt n = 0. 0.85 (a) The circuit in Fig. and VA = 18 V.85 is a modified version of the Wilson current mirror. P8.1-mA current source. in terms of IREF . using a reference current (c) To eliminate the systematic error between IO and IREF source of 0. ** = more difficult.40 assume a signal ground at the output. of 0. 590 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers PROBLEMS ro of Q2 and Q3 ? What is the output resistance of the mirror? 8. show that the incremental input resistance seen by IREF is approximately 2VT /IREF .) Evaluate Rin for IREF = when supplied with a reference current IREF of 1 mA. What are the actual values of the currents caused by the difference in VDS between Q1 and Q2 . * = difficult problem. The current source is required to operate with the voltage at its output terminal as low as –2. D = design problem .41(a) for absolute value and the percentage change. 8. Let β = 100 and the case of all transistors identical. (Neglect the Early effect in this derivation and 8. an approximate value for the difference in their currents (b) Use this idea to design a circuit that generates currents and hence determine IO . The mirror is fed with IREF = 180 μA. assume a signal ground at the output. ro . and find the change in output current corresponding to a 5-V change in output voltage. each having a 100-μA reference current: one with a current transfer ratio of 0. Problems 591 CHAPTER 8 as shown in Fig. ** = more difficult.5 μm.) What must the bias current be? Find gm .7 V at 1 mA.90 (a) Utilizing a reference current of 200 μA. Find the value of R that will result in IO = 10 μA. Assume Q1 and Q2 to be matched and (e) Convince yourself that Q4 will have no effect on the Q3 . Assume β to be high. and contrast it with ro of the basic unity-ratio source that is providing the desired current and for which RE = 0. one with a ratio of 0. D 8.96 The transistors in the circuit of Fig. Find the value of R that output resistance of the mirror. χ = 0. 8.95 A source follower for which kn = 200 μA/V . P8.) D 8. and Ro . and one with a ratio of 0. find the output resistance. Avo . For the BJT. assume BJTs with Section 8. Find Ro .93 is to be? characterized by its exponential relationship with a scale (d) What is the minimum allowable voltage at the output current IS . 8. Use Figure P8. design a Widlar current source to provide an output current of 20 μA. 1 1 Ro Ro = ro3 ro1 gm + gmb gm + gmb 10 A 2 IO 8. Also find the voltage Q2 R gain when a load resistance of 2 k is connected to the output. Assume that all three transistors are identical and neglect the Early effect.96 have β = 100 Figure P8.2.8.89 Show that the incremental input resistance (seen by IREF ) for the Wilson MOS mirror of Fig. P8. * = difficult problem.7 V (f) What is the change in IO (both absolute value and at IE = 1 mA.01.7: Some Useful Transistor Pairings high β and v BE = 0.93 β = ∞ and VA = 50 V. all assuming high β. D = design problem .93 If the pnp transistor in the circuit of Fig. For each.10. PROBLEMS percentage) that results from VO = 1 V? 8.6 V is required to provide a dc level shift (between input and Q1 Q3 output of 0. VA = 20 V/μm. and Q5 to be matched. (Hint: Replace all transistors by their T model and remember that Q1 is equivalent to a resistance 1/gm . show that the dc current I is determined by node of the mirror? IR = VT ln(I/IS ). *** = very challenging. yields a current I = 200 μA. D 8. L = 0. find Ro assuming β = 100 and Fig. 8.94 Use the source-follower equivalent circuit in (b) For the design in (a). W = 20 μm. 8. VEB = 0. find the value of the output resistance.92. Also.91 Design three Widlar current sources. 8.92 (a) For the circuit in Fig.9 V. What do you estimate IO now D 8. P8. (b) If β = 200 and VA = 50 V. = Multisim/PSpice.92 and VA = 50 V. Q4 . gmb .41(c).45(b) to show that its output resistance is given by VA = 40 V. Assume that the bias current source has an output resistance equal to ro .41(a) is 2/gm . and Vt = 0. P8.7 V and β = 200.99 For the amplifier in Fig. P8. The 2 MOSFET has Vt = 1 V and kn = 2 mA/V .96 D *8. If the follower is fed with a source having vsig a 100-k resistance and is loaded with 1 k. Rsig = 500 k. Neglect the Early effect. (c) Determine the voltage gain Av = v o /v i . and neglect ro .98 Q2 have β = 100. Calculate the overall voltage gain. let I = 0. Assume that a load resistance of Figure P8. Neglect the Early effect in both devices. D = design problem .98 The BJTs in the Darlington follower of Fig. bias points.5 mA and β = 100.48(a).101. 5 V 3 k C2 RG 10 M vo ∞ 500 k C1 vi Q1 1 k ∞ Q2 Vsig Figure P8. respectively. and RL = 10 k.100 Consider the CD–CG amplifier of Fig. find Gv . 5V (e) To considerably reduce the effect of RG on Rin and hence on Gv . Find the dc bias currents find Gv . Also find the overall voltage gain. 8. (b) Evaluate the small-signal parameters of Q1 and Q2 at their Neglecting ro . 592 Chapter 8 Building Blocks of Integrated-Circuit Amplifiers PROBLEMS (a) Find Rin and the overall voltage gain. P8.97 Consider the BiCMOS amplifier shown in Fig. = Multisim/PSpice. Rsig 500 k What will Rin and Gv become? Q1 vo 8. both open-circuited and with Rin load. For this purpose **8. The BJT has VBE = 0. in Q1 and Q2 and show that they are approximately 8.98 6. and the power dissipation? voltage is Av v i . the case gm = 5 mA/V. find the input 200 A resistance and the output resistance (excluding the load). (d) Noting that RG is connected between the input node (b) What is the effect of increasing the bias currents by a where the voltage is v i and the output node where the factor of 10 on Rin .48(c) for 100 μA and 1 mA. you can neglect RG .8 k Rin 8. Gv . If the amplifier is (a) Consider the dc bias circuit. Figure P8. *** = very challenging. 8. let β = 100.97 10 k is connected to the output terminal. ** = more difficult.97. find Rin and hence the overall voltage gain v o /v sig . in determining the current in Q1 . and neglect ro .101 In each of the six circuits in Fig. * = difficult problem. Neglect the base current in Q2 fed with a signal v sig having a source resistance Rsig = 10 k. consider the effect of adding another 10 -M resistor in series with the existing one and placing a large CHAPTER 8 200 A bypass capacitor between their joint node and ground. 101 . Problems 593 CHAPTER 8 vo vo vo PROBLEMS vsig vsig vsig (a) (b) (c) vo vo vsig vo vsig vsig (d) (e) (f ) Figure P8. 4 mA 4k 4k Q4 Q3 2. let v G2 = 0 and v G1 = v id . ** = more difficult.PROBLEMS Computer Simulation Problems (a) For v G1 = v G2 = 0 V. of +0.2. Also find VS . find |VOV | and VSG for each of Q1 and Q2 . I = 0.9 V Q1 Q2 0.5 Consider the differential amplifier specified in Prob- (d) Repeat (b) for VCM = −0.04 mA.16 mA and iD2 = 0 (Q2 just cuts off).6 = Multisim/PSpice.9 V Figure P9.1 with G2 grounded and v G1 = v id . lem 9. (c) Repeat (b) for VCM = +0.12 mA. and VD2 . Instructions to assist in setting up PSpice v G2 = 0 and v G1 = v id . At each end of this range. * = difficult problem. Note that (a) iD1 = iD2 = 0. v GS1 . iD1 = 0.2 = 10.1: The MOS Differential Pair (v D2 – v D1 ). (e) iD1 = 0 mA (Q1 just cuts off) and iD2 = 0. Problems identified by the Multisim/PSpice icon are (b) If the current source requires a minimum voltage of 0.1 mA v v R 0. For each case. ID 2 .4 mA/V .5 V VSS 0.09 mA? 9.2 V What is the difference output voltage v D2 − v D1 ? What is the to operate properly.16 mA. (W/L)1.4 For the differential amplifier specified in Prob- lem 9. intended to demonstrate the value of using SPICE simulation find the input common-mode range. P9. Find the range of v id needed 2 kn = 0.07 mA. 9. if a particular parameter value is not specified in the problem (c) iD1 = 0.15 V VDD 0. VD1 . what is the lowest value allowed for voltage gain (v D2 − v D1 )/v id ? What value of v id results in VS and hence for VCM ? iD1 = 0. and to investigate important issues such as allowable signal swing and amplifier 9.9 V 0.6 to obtain a dc voltage channel-length modulation. Let v id be adjusted to (e) What is the highest value of VCM for which Q1 and Q2 the value that causes iD1 = 0. 9. find VS .5 mA v RD RD vG1 vG2 v Q Q v 0.04 mA and iD2 = 0. and hence v id . *** = very challenging. find v S .letVDD = VSS = 1.4 V.1 let nonlinear distortion.8 V and kp W/L = 4 mA/V .1 V. Operate all transistors at VOV = 0. to verify hand analysis and design. (d) statement.asshowninFig. v S . ID1 .4 V. v D2 . 9. Find remain in saturation? the corresponding values of v GS2 . Find the value of v id that corresponds and Multisim simulations for all the indicated problems can to each of the following situations: be found in the corresponding files on the website.07 mA and iD2 = 0. (b) For VCM = 0. Neglect D 9. P9.5 V v G1 = v G2 = 0 V.6 Design the circuit in Fig.09 mA and iD2 = 0. you are to make a reasonable assumption. give the value of the voltage at the (a) Find VOV and VGS for each transistor. (f) If current source I requires a minimum voltage of 0. to steer the bias current from one side of the pair to the other. D = design problem .2.1 For an NMOS differential pair with a common-mode voltageVCM applied. and Section 9.12 mA and iD2 = 0.0 V.2 let Vtp = −0. VD1 .1 V at each of the drains of Q1 and Q2 when 2. and neglect channel-length modulation. RD = 5 k.2 For the PMOS differential amplifier shown in 2 Fig.08 mA. and VD2 . 9.4 V. Vt n = 0.2 Figure P9. common-source terminal and the drain voltages. (b) iD1 = 0.3 For the differential amplifier specified in Problem 9.16 mA. v D1 . Specify I. Problems 675 CHAPTER 9 and assume that for the process technology in which the circuit can be as high as 0.5 V. Find VOV .25 V.23) to show that if the term involving v id is to 0. (9.15 Design a MOS differential amplifier to operate I/2 from ±1-V supplies and dissipate no more than 1 mW and the corresponding maximum value of v id is given by in its equilibrium state.5 V. and W/L. that as the maximum input signal to be applied to the PROBLEMS differential pair is increased.01.12 An NMOS differential amplifier is operated at a a common-source amplifier. RD .2 mA and has a W/L ratio of 32.23) to a maximum of 0.) Assume 2 2 be kept to a maximum value of k then the maximum possible μn Cox = 400 μA/V and neglect the Early effect. 20.0.0. RD . and RD = 10 k. of I/2. what must the bias current I be changed to? (a) What is the value of gm for each of the two transistors? D 9. gm . Imax = 2 k(1 − k) D 9. 1. that (e) What is the lowest value that VDD must have to ensure saturation-mode operation for Q1 and Q2 at all times? (a) causes iD1 to increase by 10% above its equilibrium value Assume Vt = 0.5 V and 2 (d) If v id is 20-mV peak-to-peak sine wave applied in a μn Cox = 400 μA/V . differential pair be relative to the bias current ID of the CS D 9.7 The table providing the answers to Exercise 9. I. VA = 10 V. 1. 9. RD . linearity is maintained at the D 9. 0. (9. 20 V/V. gain Ad is to be 10 V/V.2 V. Q2 . I = 200 μA is found to switch currents completely to one side of the pair when a difference signal vid = 0. what 9. If v id max is to be 220 ±1-V power supplies and dissipate no more than 1 mW in mV.5 to (b) If each of the two transistors is operating at an overdrive operate at VOV = 0. The differential voltage gain Ad is to and the corresponding values of W/L and gm . transconductance gm of 2 mA/V is needed and the amplifier and the W/L ratios of Q1 . and 0.3 shows 2 has μn Cox = 200 μA/V and λ = 0.01. ** = more difficult. RD = 47 k. use the data in the table to determine the required VOV the equilibrium state. A channel-length modulation. The technology available provides Vt = 0. D = design problem .25 V and to provide a transconductance voltage VOV = 0.1 V while keeping the nonlinear term 2 is fabricated. Both amplifiers utilize the same bias current I of 0. * = difficult problem. 9. Vtn = 0. Assume kn = 400 μA/V and 2 neglect the Early effect.11 For the MOS differential pair in Fig.3 V is applied.2.9 A MOS differential amplifier biased with a current source and W/L.5 V. fractional change in the transistor current is given by RD . 9. Determine the values of R. Neglect under the square root in Eq.14 Design a MOS differential amplifier to operate from same level by operating at a higher VOV .16 An NMOS differential amplifier employing equal what overdrive voltage will each of Q1 and Q2 be operating drain resistors. has a differential gain Ad of when vid = 0? If vid for full current switching is to be 0. At 9. 2. What must the bias current I of the ro .13 It is required to design an NMOS differential amplifier? What is the ratio of the power dissipation of the amplifier to operate with a differential input voltage that two circuits? = Multisim/PSpice. Specify the required values of I. and W/L.10 Design the MOS differential amplifier of Fig. Q3 .4 V and μn Cox = 400 μA/V . and all the transistors have μn Cox = 200 μA/V . *** = very challenging.17 A MOS differential amplifier is designed to have a differential gain Ad equal to the voltage gain obtained from 9. be 10 V/V and the output common-mode dc voltage is to be 9.2 V. The differential voltage Evaluate both expressions for k = 0. the same W/L ratios. 9. (Note: This is the dc voltage at the drains. Specify the W/L ratios and the bias (c) For v id = 0.04. and Ad . specify the is the peak of the sine-wave signal at each drain? value of vid ≡ vG1 − vG2 . what is the dc voltage across each RD ? current. What is the input is required to provide a differential output signal of 1 V when common-mode voltage range for your design? the input is at its maximum value.1. (b) makes iD1 /iD2 = 1. and Q4 .5. balanced manner but superimposed on VCM = 0.8 Use Eq. Assume that the technology available 9. 2 values of RD and supply voltages. Find the required values of VOV .1. what must the value of I be? gm of 1 mA/V. Select the value of VOV so that √ the value of v id that steers the current from one side of v idmax = 2 k VOV the pair to the other is 0. in terms of VOV . *** = very challenging.4 .4 . (b) Neglecting the effect of the output resistances ro . * = difficult problem. P9. gm3. ** = more difficult. What must the RD RD width W of the differential-pair transistors be relative to the CHAPTER 9 width of the CS transistor? vod D 9. Here Q3 implements Rs . 676 Chapter 9 Differential and Multistage Amplifiers Rs = 0? What is the value of Rs (in terms of 1/gm ) that reduces PROBLEMS 9. find (W1. with Q1 Q2 2 2 the value of Rs determined by the voltage VC at the gate of Q3 . P9. Rs VDD I I – – 2 2 VSS Q3 Q4 Figure P9. Neglect the Early effect. ro1.19 Figure P9.2 .20 *9. all the transistors use the same channel length.20 Find the differential half-circuit for the differential Figure P9.4 . find Ad I I – VC – 2 2 in terms of μn . and Q3 and Q4 be matched.20 and use it to derive an expression for the differential gain Ad ≡ v od /v id in terms of (a) With v G1 = v G2 = 0 V.21 amplifier shown in Fig.2 . VDD RD RD I vod Q1 Q2 vG2 Figure P9. P9. and ro3.19 shows a MOS differential amplifer with vid vid Q1 Q2 the drain resistors RD implemented using diode-connected 2 2 PMOS transistors. as shown in Fig. Q3 and Q4 .21 The resistance Rs in the circuit of Fig. Both amplifiers use the same values of RD and VDD supply voltages and are designed to dissipate equal amounts of power in their equilibrium or quiescent state. RD . D = design problem .2 and (W/L)3. As well.18 A differential amplifier is designed to have a differential voltage gain equal to the voltage gain of a common-source the gain to half this value? amplifier. (c) If μn = 4μp and all four transistors have the same channel length. what dc voltages appear = Multisim/PSpice.21. – V SS 9.2 /W3. (W/L)1. Let Q1 and Q2 be matched. μp .20 can be implemented by using a MOSFET operated in the triode vid vid region.19 vG1 (a) Find the differential half-circuit and use it to derive Q3 an expression for Ad in terms of gm1. and Rs . and assuming that Q1 and Q2 gm .4 ) that results in Ad = 10 V/V. What is the gain with are operating in saturation. respectively. P9.22 1. Vt n = Vtp = 0. Assume that Q1 and Q2 are matched Specify the required value of R and the W/L ratios for and operate in saturation at an overdrive voltage VOV that all transistors. (W/L)1.8 V. What resistance rDS does it have.5 V (a) With v G1 = v G2 = 0 V.2 .23 = Multisim/PSpice. circuit to meet the following specifications: (d) Find VOV 3 and hence VC that result in (i) Rs = 1/gm1. * = difficult problem. Problems 677 CHAPTER 9 at the sources of Q1 and Q2 ? Express these in terms of and Q4 ? At what overdrive voltages are Q3 and Q4 oper- the overdrive voltage VOV at which each of Q1 and Q2 ating? Find an expression for rDS for each of Q3 and Q4 operates. Also. Rs = 0. (ii) (a) Differential gain Ad = 50 V/V. and Vt ? Ad ≡ v od /v id in terms of gm1. Here Q1 and Q2 form the small v DS . D = design problem . It is required to design the VOV . express Rs in terms of drains of Q1 and Q2 is not shown. where v id is overdrive voltage VOV 3 is Q3 operating at. (b) For the situation in (a). Fig.5 μp Cox = 250 μA/V .20. Convince yourself that Q3 now D *9.2 . a small signal. 2. in terms of VC .2 . Now if all three bias circuit that establishes an appropriate dc voltage at the transistors have the same W/L.22 The circuit of Fig. PROBLEMS where v id is a small signal. while the current source transistors Q4 and in terms of the overdrive voltage VOV 3 at which it is Q5 form the active loads for Q1 and Q2 . expressed differential pair. P9. neglect channel-length modulation. and gm1. what dc voltages appear at the sources of Q1 and Q2 ? What current flows through Q3 Figure P9. find an expression of the voltage gain VOV . RD . 2 thus. implementing the resistance Rs needed for the circuit in (d) The dc voltage at the gates of Q7 .5 V. *9.2 . assume that transistor is operating. (c) Now consider the case v G1 = +v id /2 and v G2 = −v id /2.4 . Here Rs is realized as the series equivalent of two The technology available is specified μ as follows: n Cox = MOSFETs Q3 and Q4 that are operated in the triode region.5 V VDD RD RD Q6 Q3 vod I Q1 Q2 IREF vG2 vG1 R vid2 Q1 Q2 vid2 Q3 Q4 vod I I – – 2 2 Q4 Q7 Q5 –VSS Figure P9. and (W/L)3. For dc bias calculations you may Q3 and Q4 are matched. and Vt . VAn = VAp = 10 V. 1. The dc operating? This is the resistance Rs . and gm1.2 . Rs = rDS3 + rDS4 .8 V.23 Figure P9. *** = very challenging. Q4 . VOV 3 . (b) IREF = I = 200 μA. Also specify ID and VGS at which each corresponds to a drain bias current of I/2.2 . and Q5 is −0.4 . (W/L)3.2 . what current flows in Q3 ? What (b) Now with v G1 = v id /2 and v G2 = − v id /2.5/gm1.23 shows a circuit for a differential conducts current and operates in the triode region with a amplifier with an active load.22 shows an effective way of (c) The dc voltage at the gates of Q6 and Q3 is +0. and hence for Rs in terms of (W/L)1. ** = more difficult. find: 9.26 For the differential amplifier of Fig. find VE .3 V. and VOV . 9. Q1 Q2 9.7 V at iC = 1 mA.5 V. v BE = 0. I. If gm is to be as high as possible (a) What is the largest input common-mode signal that can be but the power dissipation in the amplifier (in equilibrium) is applied while the BJTs remain comfortably in the active to be limited to 0. of Q1 .24 A design error has resulted in a gross mismatch in the circuit of Fig. find the input common-mode range. and a frequency of 120 Hz (see Section 4. and the power supplies are ±1. what value of IRC should you choose in order to allow a common-mode Section 9. Assume that the BJTs have v BE = 0.31 Consider the BJT differential amplifier when fed with a common-mode voltage VCM as shown in Fig. and with v B1 = −0. Assume CHAPTER 9 that the current source requires a minimum of 0. As is Figure P9. ** = more difficult. 9.4 mA. Assuming that the bias current is obtained by a simple current source and that all transistors vod require a minimum v CE of 0.0 V.28 An npn differential amplifier with I = 0. VEE = 2. obtained with v B1 = +0. Find the ripple component of the are operated at the same = VA . * = difficult problem. find VE . (c) If v B2 = 0. *** = very challenging.2: The BJT Differential Pair input signal of ±1.24 often the case. If v B2 = 0. Now design the D 9.4 mA. the differential gain Ad is given by collector voltages. VCC = VEE = 2. I (b) Find the input common-mode range. the supply voltage VCC may not be pure dc but might include a ripple component v r of small amplitude D 9. Specifically.5). 9. D = design problem .32 Consider the differential amplifier of Fig.2 V. VCC = (a) ID1 and ID2 . The bias current I = 20 μA and is supplied with a simple current source.9 V. The transistors leave the active mode at v CE ≤ 0.0 V? 9. Use the largest possible value for I subject to the = Multisim/PSpice.29 Repeat Exercise 9. as well as of the difference output voltage v od ≡ v C2 − v C1 .3 V for proper VDD operation.24. P9. Q2 has twice the W/L ratio Find the voltage at the emitters and at the outputs. The collector resistors RC = 82 vid 2 k.27 An npn differential amplifier with I = 0. (b) If the available power supply VCC is 2.7 V at iC = 1 mA. VSS 9.5 mW. If VA = 5 V/μm.15(a).14 and amplifier to obtain a differential gain of 500 V/V. Thus the supply show that if all transistors have the same channel length and VOV and assuming that VAn VAp = voltage becomes VCC + v r . and VC2 . Use VOV = 0. and RC = 5 k utilizes BJTs with β = 100 and RD RD v BE = 0.5 V.25 For the cascode differential amplifier of Fig. and and RC .7 for an input of –0. and β = 50. 678 Chapter 9 Differential and Multistage Amplifiers β = 100. and VC2 (c) The differential gain Ad in terms of RD . and RC = 5 k utilizes BJTs with β = 100 and (b) VOV for each of Q1 and Q2 .15(a) let I = (c) For the value of IRC found in (b). PROBLEMS *9. vid 2 WL 2W L 9. VC1 . RC = 5 k. what bias current I would you use? region with v CB = 0? Let VDD = VSS = 0. find the value of v B1 that increases the current in Q1 by 10%.30 An npn differential pair employs transistors for which v BE = 690 mV at iC = 1 mA.3 V.13(a). specify the let the BJT β be very large: required channel length L. 9.5 V. If v id is a small sine-wave signal. VC1 .3 V for operation in the active mode. select values for I 0. Comment on the differential 2 Ad = 2 VA VOV amplifier response to this undesirable power-supply ripple. VCC = VEE = 2. v C1 and v C2 . 9.2 V. (a) For v B1 = v B2 = VCM = 0 V.5 V.5 V.7 V at iC = 1 mA. VCM = −1 V.4 mA. The power dissipation in model. Give the circuit when v id = 0? configuration and specify the values of all its components. 15 mV.1 V and provide a differential emitter-degeneration resistances Re in the emitters (see output signal of 2 V. the quiescent state should not exceed 1 mW.34 Design the circuit of Fig. what is re of the half-circuit? For a load resistance which operation is as required? Assume α 1.5 V power supplies and to iC2 as in (b) but with v id = 200 mV. 30 mV.e. 9. D 9. for differential input signals v id of 2. iE1 /I = iE1 − (I/2) /I. to vid in the cases without and with the Re ’s. By what factor is Gm reduced? 9. 8. 9. (9. 9. For a differential (c) What is the signal voltage at each collector? Assume input signal of zero volts. Let β = 100.48) and (9. tial output voltage (i.35 For the circuit in Fig. junction to a maximum of 5 mV. Provide a tabulation of the ratio iE1 /I /v id . 20.39 Design the basic BJT differential amplifier circuit the differential pair. what is PROBLEMS and 40 mV. use Eqs. Consider the case I = 200 μA with the transistors required to limit the signal amplitude across each base–emitter exhibiting v BE = 690 mV at iC = 1 mA and assume α 1. (b) With no emitter resistances Re . *** = very challenging.38 A BJT differential amplifier uses a 400-μA bias current. 9. of the difference current. A current signal of 10 mV is applied. least 20 k and a differential voltage gain of 100 V/V. 10 mV.49) to find iC1 and iC2 .. applied to the differential amplifier of Fig. what is the equivalent signal to its source of 1 mA and a positive supply of +5 V are available. 5 mV. A differential input signal of 0.40 For a differential amplifier to which a total difference of 1 V when the differential input signal is 10 mV.41 A BJT differential amplifier is biased from a 0. The D 9.36 In a differential amplifier using a 1. Specify I and RC . of 10 k in each collector. corresponding CE half-circuit? If the emitter current source I What is the largest possible input common-mode voltage for is 200 μA. the differential input resistance? which represents the proportional transconductance gain of D 9. Comment on the linearity of of Fig. determine the gain v o /v id versus v id .5-mA emitter bias voltage v be for each BJT. transistor β is specified to be at least 100.18 to provide a differential input resistance of at the differential pair as an amplifier. between the two collectors? 9.14 to provide a differen. To ensure adequate linearity. use the large-signal model to find iC1 and iC2 when v id = 20 mV. Plot v od versus v id . Use the large-signal provide differential gain of 60 V/V. 30. versus v id . Another design requirement is that the differential input resistance be at least 100 k.37 This problem explores the linearization of the transfer D 9.43 Design a bipolar differential amplifier such as that (c) Now find the value of Re that will result in the same iC1 and in Fig. 35 mV. current source. the two BJTs are not matched. one has (b) What is the total emitter current in each BJT? twice the emitter junction area of the other. ** = more difficult. what is the half-circuit gain? What *9. Problems 679 CHAPTER 9 constraint that the base current of each transistor (when I (d) Calculate the effective transconductance Gm as the ratio divides equally) should not exceed 2 μA. The collectors are connected to VCC via 10-k hence comment on the amplifier linearity. (iC1 − iC2 ). Rather. What is the value of gm of each device? If β is 160. (a) Find the signal current in the emitters (ie ) and the signal 9. what do the collector currents α = 1.17). and collector? Between the two collectors? hence determine v od = v C2 − v C1 for input differential signals 9. one taken between the two collectors) 9. Comment on the resulting graph. As another way of resistors. D = design problem . The (a) With no emitter resistances Re . * = difficult problem. and each emitter.14. 20 mV.14. what value of VBE results BJTs available are specified to have β ≥ 100.1 V is applied visualizing linearity.5-mA v id ≡ v B1 − v B2 of 2 mV. become? What difference input is needed to equalize the (d) What is the voltage gain realized when the output is taken collector currents? Assume α = 1.18 to operate from ±2. assuming α = 1 and magnitude of signal output voltage would you expect at each IRC = 5 V.33 To provide insight into the possibility of nonlinear How does this factor relate to the increase in v id ? distortion resulting from large differential input signals Comment. 9. evaluate the normalized change in the current iE1 . 9. and 40 mV. it is Fig. 10. 9. = Multisim/PSpice. between the two bases. constant-current source and includes a 400- resistor in 25 mV. 5.42 Design a BJT differential amplifier to amplify a characteristics of the differential pair achieved by including differential input signal of 0. Figure P9.) vod (c) If VCMmax is to be +1 V. find the differential half-circuit and (b) If β = 100. (d) For the situation in (c). what is the signal voltage at each of the input resistance Rid . Sketch and VCM VCM 2 2 Re 2 clearly label the waveforms for the total collector voltages v C1 and v C2 and for (v C2 − v C1 ) for the case: v B1 = 1 + 0.44 In this problem we explore the trade-off between input common-mode range and differential gain in the design RC RC of the bipolar BJT. For each circuit. 680 Chapter 9 Differential and Multistage Amplifiers PROBLEMS (a) Specify the values of I and RC . find (b) the differential voltage gain achieved. show that when v id has a peak v̂ id . with v id = 0). v B should not exceed v C by more than 0. find I and RC . Now if the power dissipation in VCC the circuit is to be limited to 1 mW in the quiescent state (i.14 with the input voltages vod v B1 = VCM + v id /2 v B2 = VCM − v id /2 vid vid VCM VCM (a) Bearing in mind that for a BJT to remain in the active 2 2 mode. VCC D *9. P9. what is the maximum allowable with v id = 0)? Hence. Find the differential gain Ad .4 V.005 sin(ωt) I I v B2 = 1 − 0. VCM ? Recall larger negative VCM ? CHAPTER 9 that to maintain an npn BJT in saturation. ** = more difficult. what is the input differential resistance? derive expressions for the differential gain Ad and differential (c) For v id = 10 mV. 9.45 For the differential amplifier of Fig.4 − id − Ad VT + id I 2 2 (b) For the case VCC = 2.5 V.e.e. * = difficult problem.47 = Multisim/PSpice.005 sin(ωt) – 2 – 2 9. D = design problem . If VA = 20 V for all transistors.. What dc voltage appears 9.14. use the VEE relationship above to determine VCMmax for the case Ad = (a) 50 V/V. *** = very challenging.4 V. v BC should not exceed 0. Sketch the circuit and give its differential half-circuit.5 V and v̂ id = 10 mV.46 Consider a bipolar differential amplifier in which the collector resistors RC are replaced with simple current sources VEE implemented using pnp transistors. Consider the bipolar differential amplifier in Fig.47. Also find the peak output signal v̂ od and the required value of IRC . (Remember to RC RC include the power drawn from the negative power supply −VEE = −2. which of the two circuits will allow a value of the input common-mode voltage. and all other conditions remain the same. what dc voltage appears collectors? across the bias current source(s) in the quiescent state (i.. the maximum input common-mode voltage VCMmax is given by Re Re v̂ v̂ VCMmax = VCC + 0. 9. let VCC = vid vid +5 V and IRC = 4 V.47 For each of the emitter-degenerated differential ampli- at the collectors? fiers shown in Fig. what maximum gain Ad is achievable? 9. and α.1 mA Rsig 2 Figure P9.48 Consider a bipolar differential amplifier that. nected between the two collectors. vsig – 2 5V vid 25 k VCM vo vsig – vi 2 500 Rin 0.1 mA 0. P9. Let β = 100. Problems 681 CHAPTER 9 9.50 A bipolar differential amplifier with emitter- degeneration resistances Re and Re is fed with the arrangement 250 250 shown in Fig. Each of the collector v o /v i of the circuit shown in Fig. D = design problem . What differential voltage gain Ad do you expect the vi Q1 Q2 amplifier to have? 9.52 Find the voltage gain and the input resistance of the to the collector resistances RC . P9.50 Figure P9. (b) as a cascade of a common-collector stage Q1 and a find the overall voltage gain.50. * = difficult problem. Re . P9.4 mA. the dc voltage measured across each Re is found vo to be 4 VT and that measured across each RC is found to be 60 VT .50 with Rsig = 100 k. If Rsig is of such a value that v id = 0. re . by what factor does Gv increase? Figure P9. P9.47(a)) is 25 k biased with a constant current I.51 A particular differential amplifier operates from an 9.53 assuming that β = 100.53 Find the voltage gain and input resistance of the amplifier in Fig. P9.53 9. ** = more difficult.52 assuming β = 100.2 mA differential voltage gain Gv ≡ v od /v sig . in addition 9. P9.54 Derive an expression for the small-signal voltage gain emitter current source I = 0. amplifier shown in Fig.5v sig .52 Rsig 2 9. What does the differential gain Ad become? 5V 9. Now if β is doubled.54 in two different ways: resistances RC = 20 k and a load resistance RL = 40 k is connected between the two collectors. common-base stage Q2 = Multisim/PSpice.49 A bipolar differential amplifier having resistance Re inserted in series with each emitter (as in Fig. When both input terminals PROBLEMS are grounded. Derive an expression for the overall Rin 0. has a load resistance RL con. find the gain Gv in terms of RC . *** = very challenging. If the amplifier is (a) as a differential amplifier fed in the manner shown in Fig. VA = 5 V/μm.7 V. What is the value of L VD1 /V CM .5 mA/V .2 mA having an output resistance RSS = 100 k. the common-mode gain is given by and CMRR. (Hint: You need to take 1/gm into account.57 The differential amplifier in Fig.58 It can be shown that if the drain resistors of a using transistors with kn W/L = 3 mA/V . ** = more difficult. D = design problem .2. Ad . 9.18-μm CMOS fabrication (d) Determine the single-ended-output common-mode gain process available. In a MOS differential amplifier for which RD = 5 k and D *9.57 current source I = 0. Acm . P9. If the output is taken differentially and there is a 1% simultaneously the transconductances of Q1 and Q2 have a mismatch between the drain resistances. to minimize Acm . The drain resistances are known to have that is. *** = very challenging. VCM 1 mA RSS 1k Section 9. Verify that both approaches lead to the same result. The only source of mismatch in the (b) Find the value of RD that results in a differential gain Ad circuit is a 2% difference between the W/L ratios of the two of 8 V/V. Note to be 0.2 V. to have a CMRR of 80 dB. transistors. Find VOV . 2 and Q2 have kn W/L = 2. 2 9. and the CMRR (in dB) obtained with the output varied to compensate for the initial variability in gm and RD . and neglect the Early effect. a mismatch of 2%. VDD 5V CHAPTER 9 RD RD vod Q1 Q2 vid Figure P9.) required for the current-source transistor? = Multisim/PSpice. find Ad . Transistors Q1 to zero).55 An NMOS differential pair is biased by a Figure P9.57 utilizes RSS = 25 k. let Q1 RD gm RD Acm + 2 and Q2 have kp (W/L) = 4 mA/V . Acm . D 9. and λ = 0. Find the percentage change required in one that this amplifier uses a single 5-V supply and thus the dc of the two drain resistors so as to reduce Acm to zero (or close common-mode voltage VCM cannot be zero. For the 0. and assume that the bias 2RSS gm RD current source has an output resistance of 30 k. * = difficult problem.002 V/V.59 It is required to design a MOS differential amplifier (a) Find the required value of VCM . The amplifier has drain resistances RD = 10 k. Vt = 0. and ro that is MOS differential amplifier have a mismatch RD and if large. Let I = 100 μA and assume that all transistors are (c) Determine the dc voltage at the drains. Note that this equation indicates that RD can be deliberately gm . P9. 682 Chapter 9 Differential and Multistage Amplifiers PROBLEMS (e) Use the common-mode gain found in (d) to determine the change in VCM that results in Q1 and Q2 entering the triode region.3: Common-Mode Rejection 9. taken differentially.56 For the differential amplifier shown in Fig. operated at VOV = 0. the common-mode gain is measured and found a resistor RSS to establish a 1-mA dc bias current.54 Assume that the BJTs are matched and have a current gain α. mismatch gm . a CMRR of 60 dB. where v icm has a zeroaverage. (Refer to Eq. v o /v icm . ** = more difficult. specify the channel length L of the cascode RL transistor. the dif- ferential input resistance. 20 k 9.66 It is required to design a differential amplifier to the resistances RC have 1% tolerance. the common-mode gain assuming D 9. and the common-mode provide the largest possible signal to a pair of 10-k load = Multisim/PSpice. volts. and v B2 = 0. For this transistor. *** = very challenging.62 For the differential amplifier shown in Fig. transistors have β = 100 and VA = 100 V.005 sin 2π × 1000t. with I = 0.1 sin 2π × 60t + 0. v o /v id .2 V. 8. * = difficult problem. Problems 683 input resistance. P9. (b) For v B1 = v B2 = v icm . I is generated using a Wilson mirror. Find: (a) the differential gain (b) the common-mode gain and the CMRR if the bias current Figure P9. RC RC 10 k vod 10 k what must its VA be? If for the specific technology utilized PROBLEMS VA = 5 V/μm. The collector resistances are find v o .62. find the magnitude of the 0.61 The differential amplifier circuit of Fig.61 utilizes Q1 Q2 a resistor connected to the negative power supply to establish RE the bias current I. volts. and RC = 25 k. 9.60 A MOS differential amplifier utilizing a simple current source to provide the bias current I is found to have VA = 100 V. where v id is a small 200 200 k k signal with zero average.1 sin 2π × 60t − 0.) common-mode half-circuit.95 identify and sketch the differential half-circuit and the for Ro of the Wilson mirror. 9.5 mA 0. REE = 500 k. 300 (a) For v B1 = v id /2 and v B2 = −v id /2. 10 V what must the intrinsic gain A0 of the cascode transistor be? If the cascode transistor is operated at VOV = 0.5 mA differential gain. find the magnitude of the common-mode gain. What common-mode input resistance would result? Assume RC ro . β = 100 and CHAPTER 9 D 9. D = design problem .65 A bipolar differential amplifier with I = 0.2 mA. Find: (a) the differential gain (b) the differential input resistance (c) the common-mode gain (d) the common-mode rejection ratio (e) the common-mode input resistance 9.61 I is generated using a simple current mirror (c) the common-mode gain and the CMRR if the bias current 9. VA = 20 V and β = 50. Find the differential gain. Figure P9. If it is required to raise the CMRR to 100 dB by adding a cascode transistor to the current source.63 Consider the basic differential circuit in which the (d) If v B1 = 0. and those used in the differential pair. matched to within 1%. the bias cur- rent generator consists of a simple common-emitter transistor operating at 200 μA.62 (c) Calculate the CMRR.005 sin 2π × 1000t. The collector resistances RC = 5 k and are matched to within 10%. For these transistors. P9.64 In a bipolar differential-amplifier circuit.5 mA utilizes transistors for which VA = 50 V and β = 100. and a common-mode gain (to each of the two outputs) no D 9. find the maximum gain realized if VOS is to be limited to 1 D *9. The amplifier the value of the required bias current I. as the bias current I does. Note the trade-off is to have a differential gain (to each of the two outputs) between gain and offset voltage.114) for the case of a differential amplifier having a resistance RE connected in the emitter of Section 9.77 A differential amplifier uses two transistors whose β amplifier whose drain resistors are 10 k ± 1%. For this design. 2 mV. while the other input terminal is grounded.69 In a particular BJT differential amplifier. What is the value of the (including that of the other RD ). and RD /RD = 0.] 9. what is the offset likely to be? *9. D = design problem .1 V/V. is at VOV = 0. I. RD = 10 k. If the only source of under the conditions that RD /RD = 4%.70 An NMOS differential pair is to be used in an 9. what percentage change from input common-mode resistance when the bias source has the nominal would you require? lowest acceptable output resistance? 9. 9.76 Modify Eq. A decision is to be made concerning PROBLEMS resistances.02. Assume α 1. but collector load resistors that are mismatched junction area that is twice that of the other. D 9. 3 mV. Thus determine the required value of I. derive an expression for the total voltage at each of the D 9.68 When the output of a BJT differential amplifier is taken I of 100 μA uses transistors for which kn = 200 μA/V and differentially. To determine the required bias current two possibilities.74 A bipolar differential amplifier uses two well-matched error results in one of the transistors having an emitter– base transistors. find the resulting input offset current vicm /REE will split between Q1 and Q2 in the same ratio voltage. Use these expressions to relate VOS and Ad .71 An NMOS differential amplifier for which the collectors in terms of VCC and I in the presence of the input MOSFETs have a transconductance parameter kn and whose signal. What input offset voltage is required to reduce the grounded. *** = very challenging. show that = Multisim/PSpice. what might the is the mismatch in collector resistances. For the values are β 1 and β 2 . The power supply Contrast the differential gain and input offset voltage for the VCC available is 5 V. If everything else is matched.3 V. 0 V. whether 160 μA or 360 μA. and I. Find the three components of input offset voltage when the output is taken single-endedly.75 A bipolar differential amplifier uses two transistors find the common-mode gain obtained when the output is whose scale currents IS differ by 10%. is suspected to have a variability of Vt of ±5 Give the complete circuit with component values and suitable mV.4: DC Offset each transistor. what must the minimum value of VA be? offset to zero and thereby compensate for the uncertainties The BJTs available have β ≥ 100. What is power supplies that allow for ±2 V swing at each collector. what must this total offset be? For the usual case of the three effects being mismatch be (in percent)? independent. With the inputs by 10%. and 5 mV.73 An NMOS differential pair operating at a bias current 2 9. which is applied to one input terminal the bias current I to be used. Let the bias current source be I. of at least 100 V/V. (W/L)/(W/L) = common-mode gain when the output is taken differentially 4%. Use a 2-mA current source for biasing. * = difficult problem. (9. Then impose the condition that both transistors remain CHAPTER 9 drain resistances RD have a mismatch RD is biased with a well out of saturation with a minimum v CB of approximately current I. whose designed operating point greater than 0. a production 9. Assume α 1. kn W/L = 4 mA/V . 684 Chapter 9 Differential and Multistage Amplifiers 2 pair. a differential input resistance ≥ 10 k. [Hint: The CM signal resistors are well matched. 4 mV. the worst-case input offset voltage you would expect to find? Specify the minimum value that the output resistance of the What is the major contribution to this total offset? If you used bias current source must have. 2 (b) If kn = 4 mA/V . and of W/L and RD (independently) of ±1%. The input differential signal is a sinusoid of 5-mV peak amplitude. In the worst case. of the signal voltage obtained between the two collectors? RD /RD . RD . If the two collector taken differentially.67 Design a BJT differential amplifier that provides mV. ** = more difficult. If the current source is realized a variation of one of the drain resistors to reduce the output by a simple mirror. For each case. how will the emitter bias current split between the differential output voltage to zero? two transistors? If the output resistance of the current source is 500 k and the resistance in each collector (RC ) is 12 k. what differential gain is achieved? What is the amplitude (a) Find expressions for Ad and VOS in terms of kn . and Vt = 5 mV.72 An NMOS amplifier. its CMRR is found to be 34 dB higher than W/L = 10. give two single-ended outputs (at the collectors). *** = very challenging. adjustment of the values of RC1 and RC2 so as to reduce D 9. **9. What do you estimate Ro and Ad (with RL disconnected) to be? 9.79 A differential amplifier uses two transistors having VA current? The smallest possible input bias current? The largest values of 100 V and 200 V.32(a) is measured and found to have a short-circuit transconductance of 2 mA/V. find the input voltage that would restore current balance to the differential pair. Show that a mismatch Rs between the hence the dc offset voltage at the output. connected in series with RC1 . and the source resistance in series with grounded. possible input offset current? find the resulting input offset voltage. one using BJTs and the other MOSFETs.78 Two possible differential amplifier designs are consid- (a) RC1 being 4% higher than nominal and RC2 4% lower than ered. A differential input signal is applied and the output voltage is measured with a load resistance RL connected. the magnitude of 1 mA the output signal is reduced by half. P9. 9. In both cases. All the = Multisim/PSpice.81.84 A large fraction of mass-produced differential- the differential output voltage to zero when both input amplifier modules employing 20-k collector resistors is terminals are grounded. ** = more difficult. What is the largest possible input bias *9. We wish to find the adjusted to reduce the input offset to zero? If an adjustment mechanism is devised that raises one collector resistance VCC while correspondingly lowering the other. Assume that the two transistors are intended to be biased at a VCE of about 10 V. D = design problem . area 5% smaller than nominal. what value of potentiometer resistance (specified to 1 significant digit) is needed? Assume that the 1k offset is entirely due to the finite tolerance of RC . Repeat using large-signal analysis and 9. PROBLEMS What input offset voltage results in each case? What does the MOS VOS become if the devices are increased in width by a 9.5: The Differential Amplifier with a Current-Mirror Load Q1 Q2 9. Problems 685 the input offset voltage is approximately VT 1/β1 − 1/β2 . This offset-nulling process can be found to have an input offset voltage ranging from +2 mV accomplished by utilizing a potentiometer in the collector to –2 mV. as shown in Fig.80 A differential amplifier is fed in a balanced or junction area twice that of the other. CHAPTER 9 potentiometer setting.81 is used. assuming that the values of the two source resistances gives rise to an input collector resistances are equal. If everything else is matched. With both inputs push–pull manner.85 The differential amplifier of Fig.83 In a particular BJT differential amplifier. It is found that when RL is reduced from ∞ to 20 k. a production error results in one of the transistors having an emitter–base *9. The MOSFETs are operated at VOV = 200 mV. what resistance change is needed? If a potentiometer connected as shown (x) (1 x) in Fig. RC1 RC2 5k 5k Section 9. represented by the fraction x of its value Evaluate VOS for β 1 = 50 and β 2 = 100. * = difficult problem. find the current in each of the two transistors and each base is Rs .86 A current-mirror-loaded NMOS differential amplifier is Figure P9. nominal the collector (drain) resistors are maintained within ±2% of (b) Q1 having an area 5% larger than nominal.82 A differential amplifier for which the total emitter bias factor of 4 while the bias current is kept constant? current is 400 μA uses transistors for which β is specified to lie between 80 and 200. that is required for nulling the output offset voltage that results from: 9. while Q2 has nominal value.81 One approach to “offset correction” involves the compare results. P9. By what amount must one collector resistor be circuit. Use small-signal analysis to offset voltage of approximately (I/2β)Rs / [1 + (gm Rs )/β].81 fabricated in a technology for which |VA | = 5 V/μm. What is the lowest value of the total the lack of balance in the circuit and the unavailability of a (VDD + VSS ) that allows each transistor to operate power supply differential half-circuit. For instance. We ro2 .91 Figure P9.89 Consider a current-mirror-loaded differential ampli- +v id /4. current values on the circuit diagram and reflect on the results. confirming our contention that the Fig. which we have derived in the text. *** = very challenging. thus. Determine their values in the sequence of *9. we have already indicated approximate values for some of ized by k W/L = 4 mA/V .32(a) with the bias current might assume. Find the bias the node voltages.25 V.20 V and VA = 10 V. have “pulled out” ro of each transistor. the form shown in Fig. D = design problem . Write the cascoded and a cascode current mirror is used for the load. 1 2 gm ro v id . All transistors have L = 0.91 shows the current-mirror-loaded MOS CHAPTER 9 2 which μn Cox = 200 μA/V and |VA | = 5 V/μm. P9. the output voltage v o = 2 current I for which the gain v o /v id = 20 V/V. ** = more difficult. 686 Chapter 9 Differential and Multistage Amplifiers transistors have L = 0. all transistors are character. The voltage at the common sources has been found to be approximately D 9. differential amplifier prepared for small-signal analysis. Also. the gain is gain is realized? given by 2 Ad = 2 VA /VOV 9.2 . what open-circuit differential voltage VOV and have equal Early voltages VA . Find gm1.32(a). The transistors have Vt = 0. which is very far from the virtual ground one fier such as that shown in Fig. and Ad . and Q1 and Evaluate the gain for VOV = 0. If the differential-pair transistors PROBLEMS (b) Show that if all transistors are operated at an overdrive are operated at VOV = 0. To help the reader. The circuit is fabricated in a process for 9. I vg3 vid 4 I ro ro Q3 Q4 RSS i13 i12 i2 i1 1 vo (g r ) v Q8 Q7 2 m o id i11 i3 i9 i6 i4 Q5 Q6 (vid 2) Q1 ro ro Q2 (vid 2) i8 i10 i7 i5 vs vid 4 Figure P9.89 Figure P9.5V 2 voltage there is vastly different from the output voltage. Q2 have W/L = 50.87 The differential amplifier of Fig.89 with I = 200 μA.88 In a current-mirror-loaded differential amplifier of the drain of each transistor will be gm vgs . 9. 9.32(a) is biased with I = 200 μA.5 μm. Note that all transistors differential amplifier in which the input transistors are are assumed to be operating at the same VOV . the voltage at the gate of the mirror source implemented with the modified Wilson mirror of is approximately −v id /4. * = difficult problem.91 = Multisim/PSpice.5 μm. the current in D 9. hence and k W/L = 5 mA/V . and VA = 5 V.90 (a) Sketch the circuit of a current-mirror-loaded MOS their numbering and assume gm ro 1. ro4 . Find the currents labeled i1 to i13 in with VDS ≥ VGS ? terms of (gm vid ). 9. 96 For the current-mirror-loaded bipolar differential pair. 9. D = design problem . (W/L)A VOS1 = VOV /2 (W/L)A VCC 5 where VOV is the overdrive voltage at which Q1 and Q2 are operating. and assuming all transistors to be Fig. VBIAS short-circuit transconductance. The Early voltages are 20 V for the NMOS and voltage. find the VEE 5V expected systematic input offset voltage.97 For the current-mirror-loaded bipolar differential pair. 9. What differential input resistance. 12 V for the PMOS transistors. The NMOS tran.2 V and all W/L ratios are accurate to within ±1% vo of nominal.2 V and the PMOS devices at sistors of Fig. replacing the simple current-mirror load by the base-current-compensated mirror of Fig. 9. * = difficult problem. Utilizing the expressions derived in Chapter 8 for the output PROBLEMS tor mismatches on the input offset voltage of the resistance of a bipolar cascode and the output resistance current-mirror-loaded MOS differential amplifier of of the Wilson mirror. For this purpose. output resistance.95 A bipolar differential amplifier having a simple pnp vd current-mirror load is found to have an input offset voltage of 2 mV. find the worst-case total offset voltage VOS .98 shows a differential cascode amplifier value of load resistance is the gain reduced by a factor of 2? with an active load formed by a Wilson current mirror. find the expected systematic input offset VOV = 0.94 The differential amplifier in Fig.3 V. Evaluate VOS for βP . 8. Evaluate VOS for βP = 50. *** = very challenging.36(a) is operated Q3 Q4 with I = 500 μA. with devices for which VA = 10 V and β = 100. replacing the simple current-mirror load by the Wilson mirror are operated at VOV = 0. ground both input terminals identical.93 This problem investigates the effect of transis. and Ad . find the resulting short-circuit output Ad = βgm ro 3 current and hence show that the corresponding VOS is given by Evaluate Ad for the case of β = 100 and VA = 20 V. ** = more difficult. Q7 (c) For a circuit in which all transistors are operated at VOV = 0. = 50. operates with a bias current I of 200 μA.11. Find Gm . For what 9. 9.92 A current-mirror-loaded NMOS differential amplifier 9. If the offset is attributable entirely to the finite β of the pnp transistors. Problems 687 CHAPTER 9 9. what must βP be? I 9. show that the differential voltage gain Ad is given and short-circuit the output node to ground.40(a).32(a). Ro . (b) Repeat for a mismatch (W/L)M in the W/L ratios of the mirror transistor Q3 and Q4 to show that the corresponding VOS is given by Q5 Q6 (W/L)M VOS2 = VOV /2 (W/L)M where VOV is the overdrive voltage at which Q1 and Q2 are operating.98 = Multisim/PSpice. and open-circuit voltage gain would you expect? What will the voltage gain be if the input Q1 Q2 resistance of the subsequent stage is equal to Rid of this stage? 9.98 Figure P9. approximately by (a) If the amplifying transistors Q1 and Q2 exhibit a W/L 1 mismatch of (W/L)A . 8. Figure P9. 9. Assume VCC = VEE = 5 V. what is the allowable range of v O ? = Multisim/PSpice. I = 0. β N = 100. D = design problem . the manner in which Q3 is connected with its 30 V. Compare with the (b) Specify the channel length required of all transistors.100 Use a bias current I = 200 μA and operate all devices at VOV = 0.100 Figure P9. P9. *** = very challenging. Ro . and VA = 100 V voltage v CM ? find Gm . The technology available provides μn Cox = 4μp Cox = 400 μA/V .32 to obtain a I differential gain of 50 V/V. Compare with the case without the Q7 –Q8 connection. find the maximum allowable output signal (d) What is the upper limit on the input common-mode swing. Find Gm . Ro . and Ad . kp W/L = 6. For I = 0. Q4 .100 shows a modified cascode differen.5 V. all transistors have equal value of β. 9.99 Consider the bias design of the Wilson-loaded cascode differential amplifier shown in Fig.103 It is required to design the current-mirror- loaded differential MOS amplifier of Fig. case without the Q7 –Q8 connection.98. and Ad . and hence the input differential resistance Rid .101 For the folded-cascode differential amplifier of (b) What should the dc bias voltage established at the output Fig. 2 let VDD = VSS = 3 V.2 mA. find the input bias current IB assuming (a) Find the W/L ratios of the four transistors. Here Q3 and Q4 are the cascode transistors. for p-channel MOSFETs is 10 V.2 V. ** = more difficult. 688 Chapter 9 Differential and Multistage Amplifiers (b) With v I = 0 V (dc) + v id . 9. * = difficult problem. VA tial amplifier. Ro4 . VA for npn transistors is However. β P = 50. and positive output signal swing of 1.5 V? the pnp transistors that realize the current sources out of (c) What should the value of VBIAS be in order to allow for a saturation.5 V? output is 0 V.102 **9.4 V. and VA = 2 V 20 V/μm and operates from ±1 V supplies. (a) With v I = 0 V dc. By what (a) What is the largest signal voltage possible at the output factor does Rid increase? without Q7 saturating? Assume that the CB junction conducts when the voltage across it exceeds 0.5 mA. If the dc level at the negative output signal swing of 1. find the value of VBIAS that results in the largest CHAPTER 9 (by an arrangement not shown) be in order to allow for possible positive output swing. I V Q Q v Q Q Q Q Q Q v Q Q V v Q Q I Figure P9. Figure P9. 9. P9. while keeping Q3 . (c) If VICM = 0. Assume that all transistors have equal β’s. Vt = 0. base current feeding the current mirror Q7 –Q8 results in very interesting input properties.4 mA/V .102 D 9. Note that for simplicity the circuit V is shown with the base of Q2 grounded.102 For the BiCMOS differential amplifier in Fig.38. find the input signal current ii PROBLEMS D 9. Ro5 . 104. 9. 8. the I input common-mode range. and CMRR. Ad . and the I CMRR. Rim .108 utilizing a Widlar current source (Fig.36(a) using a basic 2 current of I/2. Use ±5-V power supplies and BJTs that have β = 100 and VA = 100 V. RSS D *9. * = difficult problem. Ro1 and Ro2 . D = design problem . Acm . Ro . Find Gm .109 Repeat the design of the amplifier specified in Problem 9. *** = very challenging. For k W/L = 4 mA/ V . show that for 9. what is the expected magnitude 3 of the deviation from unity of the current gain of the load √ VA CMRR = 2 2 mirror? VOV where VOV is the overdrive voltage that corresponds to a D *9. find CMRR for both cases. Gmcm ..42) Q8 Q7 to supply the bias current. = Multisim/PSpice. 9. Ro .36(a) has I = 0. and an output resistance Rom of 45 k.4 mA. obtained. determine the CMRR All transistors are operated at VOV = 0.105 The MOS differential amplifier of Fig. I = 160 μA. P9. 9.110 A bipolar differential amplifier such as that shown in Q5 Q6 Fig. the common-mode gain.106 A current-mirror-loaded MOS differential amplifier PROBLEMS (a) Current source I is implemented with a simple current is found to have a differential voltage gain Ad of 30 V/V. Rom . It is required drain VA = 5 V. the open-circuit voltage gain Ad .2 V and have VA = 5 V. Problems 689 CHAPTER 9 (d) If I is delivered by a simple NMOS current source 9.32(a) in two cases: 9. that the short-circuit transconductance be 5 mA/V.104 voltage gain. S the Wilson mirror RSS gm7 ro7 ro5 . 9. Find Gm . Assume that the largest resistance available is 2 k. mirror. Am . 15 k in series with the base lead of each of Q1 and Q2 ).98 A/A current mirror shown in Fig. 9.108 Design the circuit of Fig. VA = 40 V. If the amplifier is fed differentially with a source having a total of 30 k resistance (i. Recalling that for the simple mirror RSS = ro Q and for find Acm and CMRR.32(a) is operated at the same VOV and having the same channel biased with a simple current mirror delivering I = 200 μA. and β = 150.104 Consider the current-mirror-loaded MOS differential amplifier of Fig. Its bias current source has an output resistance RSS = 45 k. If the output resistance of the bias CMRR = 2 VOV current source is 20 k and the output resistance of the and for case (b) current-mirror load is 20 k. If the bias current source is implemented with a simple npn current mirror. are very large. find REE . and Rid . length as the other four transistors. the input bias current. 9.e. find the overall differential Figure P9. Ro2 . and assuming that all transistors have the same VA and k W/L. If the common-mode output resistances of the amplifier. the output resistance Ro . Ad . and current mirror to implement the current source I. Acm .107 A current-mirror-loaded MOS differential amplifier case (a) is found to have a differential voltage gain Ad of 50 V/V 2 VA and a CMRR of 60 dB. (b) Current source I is implemented with the modified Wilson The current mirror utilized has a current gain Am of 0. RSS . ** = more difficult. and CMRR. Give the complete circuit with component values and specify the differential input resistance Rid . 112 For the current-mirror-loaded differential amplifier in devices. μp Cox = 60 μA/V . +5V CHAPTER 9 Q3 Q4 +9V vo Q1 Q2 Q3 Q4 + 15 V vid vo R = 144 k Q1 Q2 Q7 Q8 +9V vid 6.65 k Q6 Q5 Q5 Q6 –5V Figure P9. (c) CMRR Also find A1 . find: k (W/L) = 2 mA/V .1. Vt = 0. ** = more difficult. W. |VBE | = 0. the open-loop voltage gain. P9. |VA | = 60 V. Provide your results in a table similar to Table 9. Vt = 0. Rid (b) Ad (c) CMRR Assume β = 100. Determine the width of Q6 . 690 Chapter 9 Differential and Multistage Amplifiers Assume β = 100. 2 μn Cox = 180 μA/V . *** = very challenging.7 V.113 Consider the circuit in Fig. D = design problem . and PROBLEMS 9. (a) differential input resistance.111 9. and ro .111. find: that will ensure that the op amp will not have a systematic (a) differential input resistance. |VBE | = 0. VA = 9 V for all 2 9.7 V.112 –5V Section 9. Let IREF = 225 μA.111 For the current-mirror-loaded differential pair in 2 Fig.75 V for all devices. 9. the input = Multisim/PSpice. Rid offset voltage. P9. VDD = VSS = 1.112. VGS . VOV .7 V. Then. and |VA | = 60 V.6: Multistage Amplifiers Figure P9.5 V. for all devices evaluate ID . A2 . * = difficult problem.113.40 with the device geometries (in μm) shown in Table P9. (b) Ad gm . Fig. Q3 . v o /v id . Vtn = −Vtp = 0.5 60/0.115 In a particular design of the CMOS op amp of fabricated in a 0. Q2 . Specify the W/L ratio required for and Q2 . and the output voltage range.9 V Figure P9.4 V.5 10/0. Assuming that all other parameters are kept unchanged. 9. Problems 691 CHAPTER 9 Table P9. perform a dc design that will refer to Example 9.6 to help you answer the following result in each of Q1 .5 W /0. *** = very challenging.5 30/0.18-μm technology having kn = 4kp = Fig. P9. Assume an Early voltage of 6 V. D 9.113 Transistor Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 W/L 30/0.114 is D *9. (c) What is the effect on the input offset voltages? (You might (c) Find the allowable range of the output voltage. each MOSFET. VDD 0. and Q4 conducting a drain questions: current of 100 μA and each of Q6 and Q7 a current of 200 μA.5 10/0. find the voltage gain the effect of VA on the bias currents. wish to refer to Section 9. * = difficult problem. D = design problem .5 60/0.5 PROBLEMS common-mode range.40 the designer wishes to investigate the effects of 2 400 μA/V . increasing the W/L ratio of both Q1 and Q2 by a factor of 4. (a) With A and B grounded. Neglect (d) With v A = v id /2 and v B = −v id /2. ** = more difficult. What (b) What change results in the voltage gain of the input stage? is the dc voltage at the output (ideally)? In the overall voltage gain? (b) Find the input common-mode range.5 60/0.2-V (a) Find the resulting change in VOV and in gm of Q1 overdrive voltages.9 V Q3 Q4 IREF 200 A Q6 A Q1 Q2 B vo Q5 Q8 Q7 VSS 0. Design so that all transistors operate at 0.114 = Multisim/PSpice. Present your results in tabular form.114 The two-stage CMOS op amp in Fig.4). 8.40 with both inputs grounded. perform a dc PROBLEMS 9. Q3 .) transistors operate at 0. The amplifier is operated with ter 11.7 V. Assume that the two vo /vid .8 V. Thus find the systematic offset voltage that Q7 conducting a current of 400 μA. Specify Assuming that the open-loop gain will remain approximately the W/L ratio required for each MOSFET. Present all unchanged from the value found in Example 9. CHAPTER 9 corresponding value of input offset voltage. * = difficult problem. 9. and VDD = +1. (b) Find the input common-mode range.119 shows a bipolar op-amp circuit the threshold voltages of Q3 and Q4 have a mismatch that resembles the CMOS op amp of Fig. Assume an Early voltage of 1.4 mA 0. D = design problem .114 is fabricated an output stage formed by the emitter follower Q6 .119 Figure P9. 692 Chapter 9 Differential and Multistage Amplifiers (a) With A and B at a dc voltage of VDD /2. in Chap- and Vt n = −Vtp = 0. All transistors have β = 100.4 × kp = 540 μA/V function of capacitor CC will be explained later. (Use the results of Example 9.5 mA Q1 Q2 CC Q6 vo Q5 1 mA RL Q3 Q4 5V Figure P9. (c) Find the allowable range of the output voltage.40. Q2 .40. ** = more difficult. find the current that Q7 conducting a drain current of 200 μA and each of Q6 and will now conduct.35 V. 5V 0. ro = ∞. VBE = 0.119 = Multisim/PSpice.15-V overdrive voltages. Design so that all will appear at the output. 9. Vt .6. Show that a current gm3 Vt appears at the output the input differential pair Q1 –Q2 is loaded in a cur- of the first stage.116 Consider the amplifier of Fig. 9. whose parameters are specified in Example 9.6. The second stage voltage? is formed by the current-source-loaded common-emitter transistor Q5 .117 Consider the input stage of the CMOS op amp in (d) With vA = vid /2 and vB = −vid /2.118 The two-stage op amp in Figure P9. What is the corresponding input offset rent mirror formed by Q3 and Q4 . and Q4 in the W/L ratio of Q7 being 48/0.2 V and VSS = 0 V.6. find the voltage gain Fig. *** = very challenging. VOS . Here. The 2 in a 65-nm technology having kn = 5. sides of the input stage are perfectly matched except that *9. Unlike the CMOS circuit. 9. here there is 9. If a manufacturing error results design that will result in each of Q1 . find the results in a table. Figure P9. (b) With the modification suggested in (a). What is the voltage gain of the first stage? Also vo find the input resistance of the first stage.41. Use β = 100.41 and its output (c) Use the current-gain method to evaluate the voltage gain resistance.8. biased to have re = 50 Q2 and utilizing two 50- emitter resistors and 5-k loads. Problems 693 5V CHAPTER 9 (a) For inputs grounded and output held at 0 V (by negative feedback. D = design problem . 3. (b) Find the input resistance and the output resistance. utilizes bypass capacitors. Ro *9.4 k from the input of the first stage to the collectors of the second stage.125. All BJTs PROBLEMS have β = 100.124 each of the first-stage transistors and 25 for each of the (a) Find the dc bias current in each of the three transistors.7 k 2.122 Consider the circuit of Fig. what does Ais = gm2 /gm1 ideal the overall voltage gain of the amplifier become? Assume Ro = ro2 that the output resistance of the current source is very high.125 = Multisim/PSpice. Also find the dc voltage at the output. not shown) find the emitter currents of all transistors.2 k 68 k 9. Assume VBE = the voltage gain of the first stage. The amplifier. what is the effect of the change on output resistance? What is the overall gain of the amplifier when loaded by 100 to ground? The original amplifier (before modification) has an output resistance of ii 152 and a voltage gain of 8513 V/V. What is the effect on input resistance. and neglect the Early effect. P9.124 Figure P9. For our purposes here. and the overall voltage gain? 0. drives vi Q1 Q3 a second differential stage biased to have re = 25 . 9. Use the bias values found in Example 9. second-stage transistors.3 k (b) Calculate the gain of the amplifier with RL = 1 k. 8. as such. 5V 9. the Ais Ais 1− ideal gm1 ro1 resistor R5 is replaced by a constant-current source 1 mA.121 In the multistage amplifier of Fig. 9. Which resistor has the most effect on the output v o /v i . What is its gain when Ri i osc loaded by 100 ? Comment. where Ais denotes the short-circuit current gain. in the multistage amplifier of Fig.123 (a) If. however. and. D 9. and the current gain 33 k 5.6 k 4.41.7 V.7. * = difficult problem.125 For the current mirror in Fig. 9.124 shows a three-stage amplifier in which Q1 Q2 the stages are directly coupled. emitter resistors are to be introduced—100 in the emitter lead of Figure P9. Use the results of Example 9. ** = more difficult. such that the bias situation is essentially unaffected. its frequency response falls off at low frequencies. resistance? What should this resistor be changed to if the 9. β = 100. replace the output resistance is to be reduced by a factor of 2? What transistors with their hybrid-π models and show that: will the amplifier gain become after this change? What other change can you make to restore the amplifier gain to 1 Ri = r approximately its prior value? gm1 o1 1 D 9. we shall assume that the capacitors are large enough to act as perfect short circuits at all signal frequencies of interest. *** = very challenging.120 A BJT differential amplifier. All transistors are sized to operate at the same overdrive voltage. where gm and ro are the parameters of the input transistor Q3 . all transistors have VBE = 0. find the voltage gain v o /(v + − v − ). The circuit is relatively conventional except for Q5 .127 where RSS is the output resistance of the bias current source I. vo 5V I QF QG Q7 Q8 1 F 2 G QE Q3 VDD 1 E Figure P9. C Q5 (b) Show that the differential voltage gain Ad is given by IREF v A B Ad = 2gm1 ro6 ro8 = VA /VOV QB QC QA QD (c) Show that the CM gain is given by 1 2 1 10 ro6 ro8 1 Acm 5V RSS gm7 ro7 Figure P9.)] (c) Now. CMRR = 4 VA /VOV and Q7−Q8 has a transmission factor of 2.e. which operates in a Class B mode (we will study this in Chapter 12) to provide an increased negative output swing Q1 Q2 for low-resistance loads. QD . Q4 . and VA . and VOV . CHAPTER 9 VDD D ***9.. and ro of each vO of the eight transistors in terms of I. 2 (W/L)6 /(W/L)4 = 2]. verify the polarity of the input mirror and the MOS transistor is operated at the same terminals. show that the CMRR is given by Fig.125 above. What are the voltages at all the labeled nodes? 1 Ai Ai (ideal) 1 − (b) Provide in tabular form the bias currents in all transistors gm ro together with gm and ro for the signal transistors (Q1 . with their source resistance 2RSS with a controlled high β. gm . * = difficult problem. Find R so that the reference current each current mirror. VOV . Q2 . and v O is stabilized by current-source v icm /2RSS and an output resistance. v + = v − = 0 V. *** = very challenging. which uses a folded cascode involving transistor Q3 . D = design problem . ** = more difficult. VA = ∞. and Q5 ) and ro for QC . P9. of the mirror.127 For the circuit shown in Fig. (d) If the current source I is implemented using a simple and in the process. P9. All (e) Find the input CM range and the output linear range in transistors have the same Early voltage VA .126 The MOS differential amplifier shown in VOV . and Q5 Q3 Q4 Q6 β = 100. 694 Chapter 9 Differential and Multistage Amplifiers PROBLEMS **9. VOV . = Multisim/PSpice. VA = 200 V.7 V for the currents involved.126 v Q1 Q2 Q4 R D (a) Provide in tabular form the values of ID . terms of VDD . Q3−Q5 has a transmission factor of 1. Vt .127. using β = 100.7 V.126 utilizes three current mirrors for signal transmission: Q4−Q6 has a transmission factor of 2 [i. [Hint: Replace each of Q1 and Q2 together (a) Perform a bias calculation assuming VBE = 0. the current transfer ratio is given by IREF is 100 μA. For feedback to about 0 V. (see Problem 9. and QG . and L = 5 μm. μn Cox = 2 μp Cox = 40 μA/V2 . as established by external feedback. *** = very challenging. all F G MOS devices have Vt = 1V. D = design problem . R v C Q7 D perform a bias analysis. At the positive and negative limits of the output signal swing. (e) What is the input common-mode range? 5V (f) What is the output signal range for no load? Figure P9. and ro for all devices. Problems 695 CHAPTER 9 (d) Find the input and output resistances. the input QB QC QD 1W 2W 1W 5W resistance. finding all the labeled node IREF B voltages.128 = Multisim/PSpice. Device widths are indicated on 1W E 2W the diagram as multiples of W. gm .128 In the CMOS op amp shown in Fig. P9.128. what is the range of available output voltages. and VGS and ID for all transistors. negative voltage limited to −1 V before Q7 begins to (f) For no load. (c) Provide in table form ID .3 V? (h) For a load resistance one-tenth of that found in (g). A QA (d) Calculate the voltage gain v o / v + − v − . VGS . find PROBLEMS the smallest load resistance that can be driven if one or 5V the other of Q1 or Q2 is allowed to cut off. (g) For what load resistance connected to ground is the output (e) Find the input common-mode range for linear operation. 1W 2W 4W QF Q3 Q4 D ***9. conduct? assuming VCEsat = 0. ** = more difficult. 1W 1W 20W vO (b) Assuming v O = 0 V. and the output resistance. where W = 5 μm. QE H Q5 VA = 50 V. Q6 v Q1 Q2 10W (a) Design R to provide a 10-μA reference current. * = difficult problem. what (g) Now consider the situation with a load resistance is the output signal swing? connected from the output to ground. The CMRR falls off at Section 10.3(a).4 The amplifier in Fig. PROBLEMS Computer Simulation Problems 10. intended to demonstrate the value of using SPICE simulation RS = 2 k. fZ .7 k. D = design problem . RL = 10 k. fP1 .8k. P10.5 RL = 10 k. The high-frequency response of the current-mirror-loaded The source and emitter followers can have complex differential amplifier is complicated by the fact that there poles. and has the following component values: Problems identified by the Multisim/PSpice icon are Rsig = 100 k.01 μF. is to a relatively low frequency determined by the output design the cascode so that the gain obtained in the CS impedance of the bias current source.8. * = difficult problem. 10. to one significant digit) that places its associated pole at 100 (c) What is the frequency of the transmission zero introduced Hz or lower. 10. Find the value of CS (specified of 100 Hz. find the value of the coupling Vi RS capacitor CC1 (specified to one significant digit) that places 4. if RD = 10 k. and Rsig = 200 k. and RS = 1. Combining two transistors in a way that eliminates or The high-frequency response of the differential amplifier minimizes the Miller effect can result in a much wider can be obtained by considering the differential and bandwidth. *** = very challenging. 10. CC1 = 0. and fL . ** = more difficult. Section 10. Some such configurations are presented in common-mode half-circuits.1: Low-Frequency Response RD of Discrete-Circuit Common-Source and Vo Common-Emitter Amplifiers CS D 10. Instructions to assist in setting up PSpice and Multisim simulations for all D 10. What are the actual frequencies of the pole and by CS ? zero realized? (d) Give an approximate value for the 3-dB frequency fL . and to investigate impor- CC2 = 1 μF. 10. = Multisim/PSpice. Followers of both types path and one through the current mirror. and to verify hand analysis and design. Thus. The key. fP3 . however.5 The amplifier in Fig. RD = 4. Note that if a particular parameter value VDD is not specified in the problem statement.5 is biased to operate at the indicated problems can be found in the corresponding gm = 2 mA/V. RG2 = 10 M.3(a). CS = 10 μF. find the value of CC2 (specified to one significant digit) that places the associated (a) Determine the value of RD that results in a midband gain pole at 10 Hz or lower. VSS Figure P10. tant issues such as gain–bandwidth trade-off.1 For the amplifier in Fig. their frequency response is evaluated using are two signal paths between input and output: a direct the complete transfer function. fP2 . Find AM .2 For the amplifier in Fig. files on the website.3(a) is biased to operate at gm = 5 mA/V. if RG1 = 2 M. D 10. Problems 789 in the CS (CE) amplifier alone. Neglect ro . and ro is very large. (CE) stage is minimized. RG1 = 47 M.3(a) is biased to operate at (b) Determine the value of CS that results in a pole frequency gm = 5 mA/V. exhibit wide bandwidths. you are to make a reasonable assumption.3 The amplifier in Fig.5 k the associated pole at 10 Hz or lower. D 10. RG2 = 1 M. of −20 V/V. * = difficult problem. What value of fL results? D 10. Let Rsig = 0. ** = more difficult. D 10.6 shows a CS amplifier biased by a constant-current source I.7 shows a current-biased CE amplifier gm = 3 mA/V.6 Figure P10. Find AM . with the capacitors specified only to a single significant digit. *** = very challenging. 10 Hz. Also.7 = Multisim/PSpice.7 Figure P10. It employs CHAPTER 10 VDD RD CC2 Vo Rsig CC1 RL CS Vsig RG I –VSS Figure P10. operating at 100 μA from ±3-V power supplies. What design the coupling and bypass capacitors to locate the three does the plot tell you about the gain at dc? Does this make low-frequency poles at 100 Hz. and RL = 10 k.6 VCC RC CC2 Vo Rsig CC1 RL CE Vsig RB I –VEE Figure P10. Use a sense? Why or why not? minimum total capacitance. RD = 20 k.5 M. D = design problem . and 1 Hz. 790 Chapter 10 Frequency Response PROBLEMS (e) Sketch a Bode plot for the gain of this amplifier. RG = 2 M. Then ωPE and ωPC . and providing up to 80% of fL where fL is to be 100 Hz. Problems 791 RC = 20 k. RB1 = 33 k. ** = more difficult.10 Consider the circuit of Fig.11 For the common-emitter amplifier of Fig. Design so that the contribution of each of CC1 and VCC CC2 to determining fL is only 10%. and I = 1 mA. For Rsig = 5 k.7 k. Select CE (b) Convince yourself that the two poles caused by CE and first.6 k.8. RB ≡ RB1 RB2 = 10 k. and RC RE = 1. β = 100.9(a). RC = 4. IE 0.12 Vsig I (a) Assuming α 1. If CC1 = CC2 = 1 μF and the frequency at which the gain becomes unity.8 Consider the common-emitter amplifier of Fig.11. total capacitance is needed? (d) For Rsig = RC = RL = 10 k. choose CC1 and CC2 . P10. * = difficult problem. RE = 3. neglect ro and assume the current source to be ideal.9 k. each specified to one significant digit.9 For the amplifier described in Problem 10. RL = 5. at which β = 120. The transistor β = 100. What fL results? What Vo (s)/Vsig (s) in terms of AM . ωPE . RB = 200 k. neglecting ro .12 The BJT common-emitter amplifier of Fig. = Multisim/PSpice. for a minimum value specified to one significant digit CC do not interact. 10.5 k. and operates between a 20-k CHAPTER 10 (a) Derive an expression for the midband gain. *** = very challenging. find the value of the midband gain. rπ = 1 k. The dc emitter current can be shown to be capacitance. what is the ratio CE /CC1 that makes their contributions to the determination of fL equal? Vo D *10. source and a 10-k load. frequencies a decade apart and to obtain a lower RB2 = 22 k. 10. derive an expression for the small-signal voltage gain A(s) ≡ Vo /Vsig that applies in the midband and the low-frequency band.11 midband gain AM and the lower 3-dB frequency fL . Hence find the Figure P10. VCC Vsig Re CE RC I Vo Rsig CC RL CE Figure P10. and assuming the cur- rent source to be ideal.12 includes an emitter-degeneration resistance Re . D = design problem .3 mA. find the three short-circuit time constants and an estimate for fL . PROBLEMS 10. (c) Give an expression for the amplifier voltage gain and each contributing about 10% of fL . 10. design the coupling and bypass capacitors for a lower 3-dB frequency of 50 Hz. Find expressions for their frequencies.9(a) (e) Select values for CE and CC to place the two pole under the following conditions: Rsig = 5 k. *10. β 0 = 100. P10. CE = 20 μF. D 10. and ωPC . and estimate Rin and the midband gain AM . Find the input resistance (f) Sketch a Bode plot for the gain magnitude. 3-dB frequency of 100 Hz while minimizing the total VCC = 5 V. 5 V .18 A particular BJT operating at IC = 0.5 μm operated at overdrive VDS = 1. Also note that faster operation (c) Show that including Re reduces fL by the same factor as in is obtained from smaller devices.65 V. and that eox = 3. Cπ = 8 pF. Cπ fT πL 2Cox WL includes a relatively constant depletion-layer capacitance Transistor IE (mA) re () gm (mA/V) rπ (k) β0 fT (MHz) Cμ (pF) Cπ (pF) fβ (MHz) (a) 2 100 500 2 (b) 25 2 10. Use μn = 450 cm /V·s. VSB = 1 V.12(a). and Evaluate fT for devices with L = 0. (Hint: For fT . and CE = 10 μF.13 Refer to the MOSFET high-frequency model in Observe that for a given channel length. 2 2 1/2 voltages of 0. *** = very challenging.13-μm CMOS process for which Lov = 0. What will the gain become? gm fT = CHAPTER 10 Sketch on the same diagram a Bode plot for the gain 2π(Cgs + Cgd ) magnitude for both cases. NMOS transistor operating at ID = 200 μA. V0 = 0. tox = 8 nm.) fT = 4πL 2 2π(Cgs + Cgd ) 10.2 V.5 V. 2φ f = 0. VOV = 0. where χ = unity-gain frequency fT of an n-channel transistor fabricated −11 γ / 2 2φf + VSB . What are fT and fβ for this overlap component of Cgs is negligibly small. it must a certain factor. 10. Csb0 = Cd b0 = 20 fF. AM and fL with Re = 0.05 V .05 μm. (b) and thus one can use Re to trade off gain for bandwidth. fT can be increased Fig.18.3 V. and 10. The MOSFET has W = 20 μm. show that situation? 1.19 For the transistor described in Problem 10. γ = 0.1 100 150 2 (f) 1 10 500 2 (g) 800 1 9 80 = Multisim/PSpice.16 Starting from the expression for the MOSFET I = 0. RC = 10 k.5 100 500 10. 2Lmin . [Recall that gmb = χ gm . Evaluate the model parameters for an by operating the MOSFET at a higher overdrive voltage.7 4 (c) 2.17 It is required to calculate the intrinsic gain A0 and the Lov = 0.15 Starting from the expression of fT for a MOSFET. L = 1 μm.7 V.5 mA has Cμ = and making the approximation that Cgs Cgd and that the 1 pF. μn = 2 400 cm /V·s. a table. 792 Chapter 10 Frequency Response PROBLEMS (b) Show that including Re reduces the magnitude of AM by Thus note that to obtain a high fT from a given device. The device is operated at 10. show that for Section 10. and VA = 5 V/μm. ** = more difficult. Now find the value of Re that lowers fL by a factor of 10. find (d) For unity-gain frequency. * = difficult problem. −1 λ = 0. 4Lmin . D = design problem . 10. Present your results in 10. What is this factor? be operated at a high current.5 μn ID 10.2: Internal Capacitive Effects and the an n-channel device High-Frequency Model of the MOSFET and the 3μn VOV BJT fT 4πL 2 10. and making the approximation that Cgs Cgd and that the overlap component of Cgs is negligibly small.14 Find fT for a MOSFET operating at ID = 200 μA and VOV = 0.2 V and 0.25 mA. μn = 450 cm /V·s.] in a 0.45 × 10 F/m. Find A0 and fT for devices with L = Lmin .4 V. The MOSFET has Cgs = 25 fF and Cgd = 5 fF.1 L. use the approximate expression 3μn VOV gm fT . and β = 100.7 (d) 10 100 500 2 (e) 0. and 5Lmin . 3Lmin . 21 Measurement of hfe of an npn transistor at 50 MHz Cin shows that hfe = 10 at IC = 0.29 A design is required for a CS amplifier for which Neglect rx . fH . under the conditions indicated. the NMOS transistor has Cgs = 1. gm . and the gain Vo /Vsig is to have a dc value of 40 dB and a 3-dB frequency of 100 kHz.24 For a sufficiently high frequency. is such an estimate function Vo /Vsig as a function of the complex-frequency of rx good to within 10% under the condition that rx ≤ rπ /10? variable s and hence the 3-dB frequency fH and the unity-gain frequency ft . resistance). and Vsig rx = 100 .e. D 10.28 An ideal voltage amplifier having a voltage gain of 40? What is fβ ? –1000 V/V has a 0. Cμ0 = 30 f F. 10. fH . find the transfer what frequency. and Cμ = 0. Cgs . and specify Vo the values of all its components.1 pF.0 mA. VOV . (a) Use the Miller approach to find an expression for the input and GB. VA = 50 V. What is Cπ (d) Sketch a Bode plot for the gain and use it to deter- in this situation? Also. find rπ and fβ . *10. What must τF and Cje be? (c) If Rsig = 1 k.25 mA. *** = very challenging.25 Complete the table entries on the previous page for transistors (a) through (g). Vi A Cje0 = 20 fF.1 pF when operated at IC = 1.5.20 An npn transistor is operated at IC = 1 mA and VCB = 2 V. Cin .2-pF capacitance connected between its *10. τF = 30 ps.3 for the situation in which what range of signal-source resistances can you expect the the transistor is replaced by one whose width W is half 3-dB frequency to exceed 1 MHz? Neglect the effect of RG . β 0 = 200. What input capacitance would you expect? For 10. Sketch the complete hybrid-π model.27 In the circuit of Fig.75 V. the MOSFET is operated at gm = 5 mA/V and has Cgs = 5 pF and Cgd = 1 pF. ** = more difficult. D = design problem . it has an infinite input resistance and a zero output along with AM . what can AM and GB become? Cgd = 0.27. and RG is very large. Find Figure P10.26 In a particular common-source amplifier for which the and gain–bandwidth product? If the specification on the upper midband voltage gain between gate and drain (i. −gm RL ) 3-dB frequency can be relaxed by a factor of 3. Contrast this with the original design by calculating the ratios of new value to old for W. P10. Cμ was measured and found to be 0. * = difficult problem. If the device is operated at IC = 0. The amplifier is fed with a signal source having Rsig = 1 k.30 Reconsider Example 10.2 mA and 12 at IC = 1. that is.22 A particular small-geometry BJT has fT of 10 GHz required for A and C. What is the input capacitance the complex input impedance of a BJT having (ac) grounded of the amplifier? If the amplifier is fed from a voltage emitter and collector yields a real part approximating rx .31 In a CS amplifier. to is −39 V/V. the voltage amplifier is unchanged. Find modified values for all the device parameters ideal (i. What is the largest Section 10. Furthermore. that of the original transistor while the bias current remains D 10.23 For a BJT whose unity-gain bandwidth is 2 GHz and unity. (b) Use the expression for Cin to obtain the transfer function D *10. what does C CHAPTER 10 its fT become? Rsig 10. mCBJ = 0.. mine the frequency at which its magnitude reduces to 10. at what frequency does the magnitude of hfe become 10.. find gm . Also. GB. measurement of output and input terminals. V0c = 0. amplifier = Multisim/PSpice. capacitance Cin in terms of A and C.0 pF and 2 MHz.3: High-Frequency Response of the value of RL for which the upper 3-dB frequency is at least CS and CE Amplifiers 6 MHz? What is the corresponding value of midband gain 10. find fT . such as that in Fig. PROBLEMS 10.e.1 pF. Cgd . It has β 0 = 100. For β = 120.27 fT at each of the two collector currents used. find the values 10. the resistance of the source Rsig = 100 k. Problems 793 of 2 pF. For source Vsig having a resistance Rsig = 1 k.0 mA. defined in terms of ωβ . Vo (s)/Vsig (s). and the gain–bandwidth product.3(a). AM . 4. if the transistor is biased at IC = 1 mA and has β = 100. Cμ = 1 pF. 10. Cgs = 3 pF. find Rsig the midband gain and fH for the two cases RL = 25 k and Q1 RL = 2.36 For a CE amplifier represented by the equivalent CHAPTER 10 What midband voltage gain results in each case? circuit in Fig. RS = 2 k. = Multisim/PSpice. sketch Bode plots for the gain magnitude versus frequency for the two cases. respectively. and the 3-dB frequency fH .6 μm.34 Fig.2 pF. gm = 5 mA/V. and found to have a gain of −50 V/V between base and ro = 50 k.19. Refer frequency of the zero fZ . and Cgd = 0. Find: the bias current IE on the midband gain and high-frequency response of the CE amplifier considered in Example 10. If Cπ = 10 pF. rx Rsig . For Q1 : μn Cox = 90 μA/V .34 for the case IBIAS = 100 μA. Cgd = 0. Vsig What fH is obtained when the gain is unity? What value of RL corresponds? 10. high-frequency response of the CE amplifier when it is find the low-frequency gain. and the gain–bandwidth product.015 pF. RG1 = 47 M.7 k. and recall that VA = 100 V and that Cμ remains RD = 4. * = difficult problem. D = design problem . and Cgd = 0. *** = very challenging. RD = 8 k. Let RB Rsig . 10.35 A common-emitter amplifier is measured at midband Rin = 100 k. Under these conditions.39 For a version of the CE amplifier circuit in Figure P10. constant at 1 pF. Q2 and Q3 are 2 improvement in performance is achieved is an increase in matched.3(a) RC by a factor of 2. RG2 = 10 M.8 V. ro = 100 k. and Cgd = 0. power.32 A discrete MOSFET common-source amplifier has RC = 10 k. ro = 100 k. To raise fH as described. and gm RL Cμ Cπ . let Rsig = 10 k. The amplifier is fed from a voltage source with an internal resistance of 500 k and is 10. RB2 = 27 k. Cμ = 1 pF.2 pF. the designer reduces RB and 10. ** = more difficult. Find the new values of AM . and Rsig = 200 k. having Rsig = 5 k and feeds a load RL = 5 k. Rsig rπ . 794 Chapter 10 Frequency Response PROBLEMS input resistance (which is due to the biasing network) 10. To keep the (c) the frequency of the transmission zero. Cgs = 1 pF. to 50 k and 4 k. For Q2 : |VA | = 19. As before.38 The purpose of this problem is to investigate the effect of the capacitance inevitably present at the output node. fZ . the 3-dB frequency fH . 10.19(b)]. and the effective source expected 3-dB cutoff frequency fH and the midband gain. P10. Neglecting the *10. alternatives of changing either RL or Rin . Now. Assume let Rsig = 100 k. to the amplifier in Fig. 10. node voltages nearly unchanged. gm = 3 mA/V. show that: Q3 Q2 (a) the midband gain AM − βRL /Rsig (b) the upper 3-dB frequency fH 1/2πCμ βRL (c) the gain–bandwidth product | AM | fH 1/2πCμ Rsig IBIAS Vo Evaluate this approximate value of the gain–bandwidth product for the case Rsig = 25 k and Cμ = 1 pF.9(a) and to its high-frequency. gm = 3 mA/V. W/L = 100 μm/1. RB = 100 k.19(a). a designer considers the 3-dB frequency fH . Determine the collector. Cgs = 0. and RL = 10 k. Note that the price paid for whatever Fig. rx = 50 . Rsig = 10 k. Find the midband gain RG = 2 M. rx = 100 . On the same coordinates. fH . and assume that β 0 and fT remain (b) the upper 3-dB frequency fH unchanged at 100 and 800 MHz.5 k.5 pF. 10. respectively. RL = 10 k. By what factor does the power dissipation increase? VA = 12. what separate change in each would be required? 10. RD = 20 k. Cπ = 10 pF. and the fed with a relatively large source resistance Rsig . Find AM and fH . 10. gm = 40 mA/V. equivalent-circuit model and the analysis shown in Fig.2 V. AM fH . RB1 = 68 k. RL = 10 k. resistance Rsig = 5 k [refer to Fig.34 Consider the integrated-circuit CS amplifier in Comment on the results. 10. and β = 100.2 pF.37 A designer wishes to investigate the effect of changing connected to a 20-k load. the amplifier is fed with a source Cgs = 1 pF. (a) the overall midband gain AM Let IE be doubled to 2 mA. ro = 100 k.33 For the discrete-circuit CS amplifier in Fig. 10. find Cin and the In evaluating ways to double fH .9(a). gm RL 1. 43. The collector CHAPTER 10 current is 0. and 10. (a) –1000 V/V. 10 pF gain. 10 pF of the inverting op-amp circuit shown in Fig. ** = more difficult. RC = 4. find the equivalent capacitances at the output current IL . For each. Assume (c) –1 V/V. from input to ground. * = difficult problem. Rin PROBLEMS Use Miller’s theorem to find the input resistance of this circuit.2 k. Rsig . and Cμ = 0. The circuit then functions output and C is an internal capacitor connected between input as an ideal voltage-controlled current source with an and output. Without using any knowledge of op-amp circuit (e) +10 V/V. 1 pF 10.41 The amplifiers listed below are characterized by the resistance becomes infinite and the current IL into the load descriptor (A. P10. Vi Vsig (a) Using Miller’s theorem. and RL = 10 k. 1000 V/V. *** = very challenging. what capacitance can be canceled? 10 k *10. for each of the following Note that the input capacitance found in case (e) can be values of A: 10 V/V.9 V/V. input and at the output as provided by the use of Miller’s (c) If ZL is a capacitor C. and Vo /Vsig . Vsig ZL 10. 10 pF analysis. 100 V/V. Vi .42 Figure P10.8 mA. Vo . C).40 Consider an ideal voltage amplifier with a gain of 0. D = design problem .000 V/V.8 pF. find the transfer function Vo /Vsig and theorem: show it is that of an ideal noninverting integrator.000 V/V = Multisim/PSpice. 10 pF the op amp to be ideal except for having a finite differential (d) +1 V/V.42 shows an ideal voltage amplifier with a gain of +2 V/V (usually implemented with an op amp 1 k connected in the noninverting configuration) and a resistance R connected between output and input.43 Use Miller’s theorem to investigate the performance (b) –10 V/V. Show that by selecting Rsig = R. R back path—that is.42 10. Problems 795 RE = 2. and Rin with a Rin signal current source and an equivalent parallel resistance. A. β = 200. Rsig Neglecting the effect of rx and ro . between the output and input terminals.43 A Rin Vi Vo Vo /Vsig 10 V/V 100 V/V 1000 V/V 10. used to cancel the effect of other capacitance connected Assume Vsig = 1 V. find Rin . Present your results in the table below. fT = 1 GHz. where A is the voltage gain from input to impedance ZL becomes Vsig /R. show that the input resistance Vo Rin = −R. In (e). Figure P10. (b) Use Norton’s theorem to replace Vsig .7 k. find the midband voltage 2 Vo IL gain and the upper 3-dB frequency fH . and a resistance R = 100 k connected in the feed. the equivalent parallel Figure P10. 22(a) is specified to have Cgs = 2 pF.46 A CS amplifier modeled with the equivalent circuit Rsig = RL = 1 k. Assume the coupling gm = 4 mA/V.45 shows a diode-connected transis- tor with the bias circuit omitted.45 RL ). For Q1 . and VA = 19. For simplic- ity. find the midband voltage gain from base has a unity-gain frequency of 2 GHz. Assume that the load current source has a very high resistance and that there is a capacitance CL present Rin between the output node and ground. RB = 47 k. 10. what fH is obtained? = Multisim/PSpice. and fT = 600 MHz. For Q2 . and RL = 20 k. Show that the voltage gain is given by *10. The dc bias current is 100 μA. the 3-dB bias current is relatively high. the frequency of the zero. Find AM . and the frequency at bias current is reduced so that Cπ Cμ ? Assume α = 1. Cgs = 0. D 10. Sketch a Bode plot for the gain magnitude. which the gain reduces to unity.2 pF. Let the amplifier be fed with an ideal voltage source Vi .5 V Cgd = 0. The device is used in a CE amplifier operating from a very-low-resistance voltage source.6 μm. Cμ = 1 pF. Vi 1 + s C L + Cμ ro derive an expression for Zi (s) as a function of re and Cπ . case Rsig = 0.44 The amplifier shown in Fig.015 pF. and RC the frequency of the zero. (a) Find the dc collector current of the transistor. hybrid-π model with rx = 0 and ro = ∞.34 for the (f) Find Cin . CL = 2 pF. of the CMOS amplifier shown in Fig. W/L = 100 μm/1. Find the low-frequency gain. (a) If the midband gain obtained is −10 V/V. P10. * = difficult problem. of Fig. β = 100.8 pF. what is the value of fH ? (b) If the midband gain is reduced to −1 V/V (by changing Figure P10.1 pF. 796 Chapter 10 Frequency Response PROBLEMS *10. capacitors to be very large. 10. capacitance must be connected to the drain node to reduce ft (d) Use the gain obtained in (c) to find the component of Rin to 1 GHz? that arises as a result of RB . the frequency of the pole. D = design problem . Cgd = 0. Find the frequency at which the impedance has a phase angle of If the transistor is biased at IC = 200 μA and VA = 100 V.50 A particular BJT operating at 2 mA is specified to have fT = 2 GHz. RC = 1 k.8 V. and Cd b = 20 fF. and ft .45 Figure P10. assume that the signal voltage at the gate of Q2 is zero.2 pF. (g) Find fH . 1. What additional to collector (neglect the effect of RB ).44 has 10.48 It is required to analyze the high-frequency response (e) Find the overall gain at midband. and CL = 1 pF.49 Consider an active-loaded common-emitter amplifier. 2 μn Cox = 90 μA/V . P10. *** = very challenging. Cd b = 36 fF. ** = more difficult. Cgd = 0.44 and the inevitable parasitic capacitance between collector and ground. f3dB . VA = 12. Utilizing the BJT Vo 1 − s Cμ /gm = −gm ro high-frequency. Cμ = 0. *10.47 A common-source amplifier fed with a (b) Find gm and rπ . rx = 100 .015 pF. low-resistance signal source and operating with gm = 2 mA/V CHAPTER 10 (c) Neglecting ro . Rsig RB Vo 10. Hence find Rin . This capacitance repre- sents the sum of the input capacitance of the subsequent stage Figure P10. and Vsig RL neglect the effect of rx . and β = 120. fZ . What is the frequency when the frequency. find the dc gain. (Hint: The total capacitance at the CC1 CC2 output mode = Cd b1 + Cd b2 + Cgd2 ). 45° for the case in which the BJT has fT = 400 MHz and the Cμ = 0.2 V. and hence an estimate of the 3-dB frequency fH . ** = more difficult. Write an expression for D 10. What is the percentage of τH that is caused by the (a) the dominant-pole approximation interaction of Rsig with the input capacitance? To what value (b) the root-sum-of-squares approximation (Eq.55 A direct-coupled amplifier has a dominant pole at the High-Frequency Response of Amplifiers 1000 rad/s and three coincident poles at a much higher fre- quency.24 has Cgs = 2 pF. 10. Problems 797 Section 10. Cgs = 2 pF. poles at 2 MHz and 20 MHz. 10. find the value 3 10 rad/s. These nondominant poles cause the phase lag of the 10.77). obtain another estimate of fH using open-circuit time 10. Also. value of the 3-dB frequency ωH calculated using the dominant-pole approximation differs from that calculated 10.71).8. Parasitic capacitances of 1+ ω 1+ ω P1 P2 10 pF and 7 pF also are associated with the signal-source and load connections. Cgs = 30 fF. Rsig = 10 k.61 For the CS amplifier in Example 10. the input capacitance Cin using the Miller (b) 1% approximation. fZ . Rsig = 10 k. and another zero at infinite frequency.59 A CS amplifier that can be represented by the using the root-sum-of-squares formula (Eq. frequency. (d) What is the unity-gain frequency? RL = 10 k. PROBLEMS What do you estimate the 3-dB frequency fH to be? 10. CL = 30 fF.54 The high-frequency response of a direct-coupled constants. and (10. and RL = 20 k. and Rsig = RL = 20 k.53 Consider an amplifier whose FH (s) is given by The two-stage amplifier is driven from a 10-k source and drives a 1-k load. a zero on the negative dominant pole. Also. estimate for fH . Find the ratio ωP2 /ωP1 for which the three poles and estimate the 3-dB frequency fH .57 For a particular amplifier modeled by the circuit of (c) What is the gain–bandwidth product? Fig. sketch the voltage gain. 10. 10 rad/s to 30° (i. Which of the two estimates is more appropriate amplifier having a dc gain of –1000 V/V incorporates zeros at 4 3 and why? ∞ and 10 rad/s (one at each frequency) and poles at 10 rad/s 5 and 10 rad/s (one at each frequency). Cgs = 5 pF.60 For a CS amplifier with gm = 5 mA/V. the amplifier transfer function. and an estimate resulting gain magnitude and specify the unity-gain of the 3-dB frequency. D = design problem .5 pF.77) by: equivalent circuit of Fig. Use the method of open-circuit time constants to obtain an high-frequency response with a 3-dB frequency of 100 kHz. gm = 5 mA/V. find the frequency of the transmission (a) Give an expression for the gain function A(s).e.52 An amplifier with a dc gain of 60 dB has a single-pole.58 Consider the high-frequency response of an amplifier gain–bandwidth product. consisting of two identical stages in cascade. Cgd = 5 fF. find τH and fH . to limit the total phase angle to –120°). *** = very challenging. Find ωH using Cgd = 1 pF. and sketch a Bode plot for the gain magnitude. 10. For this arrangement. RG = 0. 10. Associated with each stage is a parasitic 1 FH (s) = input capacitance (to ground) of 10 pF and a parasitic output s s capacitance (to ground) of 2 pF.56 An IC CS amplifier has gm = 2 mA/V. 10. It is required to limit the excess phase at ω = real axis at 200 MHz. and RL = 10 k.51 A direct-coupled amplifier has a low-frequency gain amplifier at high frequencies to exceed the 90° angle due to the of 40 dB. 7 Express the amplifier gain function in the form of Eqs. = Multisim/PSpice. There is also a (e) If a change in the amplifier circuit causes its transfer load capacitance of 30 pF. Note that this is an example of an amplifier with a unity-gain bandwidth that is different from its 10.. the open-circuit time constants. (b) Sketch Bode diagrams for the gain magnitude and phase. Find the (a) 10% midband gain AM . Cgd = 0. what does the transfer function become? What is of the additional capacitance to be connected at the output the 3-dB frequency of the resulting amplifier? node in order to lower fH to 100 MHz. CL = 2 pF.70) Find the corresponding frequency of the nondominant poles.65 M. zero. Find the corresponding midband function to acquire another pole at 1 MHz.1 pF.18(a). and Cgd = 0. find the with ωP1 < ωP2 . CL = 5 pF. respectively. each with an input resistance of 10 k and an output resistance of 2 k. must Rsig be lowered in order to double fH ? If a way is found to lower the frequency of the finite zero to D 10. (10.4: Useful Tools for the Analysis of CHAPTER 10 10. gm = 4 mA/V. * = difficult problem. 10. Rsig = 150 k. Cd b = 0.67 Sketch the high-frequency equivalent circuit of a CB low-frequency gain AM . Neglecting the effects of ro . CL = 1 pF. Cgs = 0. 10. and ro = 20 k. 10. ro = 20 k. Common-Gate and Cascode Amplifiers The MOSFETs have Cgs = 20 fF.95). RL = 5 k. Cgs = 2 pF. and (c) VA = 10 V. and (ii) the bias current I in the entire system additional capacitance should be connected between the is increased by a factor of 4.65 Use the method of open-circuit time constants to Rsig = ro /2. Cμ = 1 pF. Cgs = Cgd = 0.2 pF.66 A CG amplifier is specified to have Cgs = 4 pF. the current-source load provides an additional 30 fF Miller approximation. 10. and estimate fH using open-circuit amplifier fed from a signal generator characterized by Vsig time constants.64 Consider a CS amplifier loaded in a current source and fed with a signal source having a resistance Rsig = ro /2. There is also 10 k.70 An IC CG amplifier is fed from a signal source with 10.19(a) but with a capacitance CL connected 1 fP1 = across the output terminals. Hence determine the gain–bandwidth product. Assume RL remains unchanged. 10. and an estimate of the 3-dB frequency fH using the Miller (b) Evaluate fP1 and fP2 and hence obtain an estimate for approximation. and hence *10. Cgd = 0.2 pF. RL = 12 k.015 pF. = Multisim/PSpice. and RL = and is connected to a load resistance of 1 M.5 mA/V. Find AM and fH . (10. the transistor. Find the *10. Let Rsig = 5 k. D = design problem . and why? 10.5 mA/V. the method of open-circuit time constants. 2πCπ Rsig re gm = 20 mA/V. gm = 40 mA/V. capacitance at the output node. Cμ = 2π(Cμ + CL )RL CHAPTER 10 0. Also. CL (including Cd b ) = 1 pF.62 Consider the CE amplifier whose equivalent circuit is pole at shown in Fig. 1 fP2 = 10. and gain–bandwidth separated into two parts: an input part that produces a product. Cgd = 5 fF. * = difficult problem. RB = ∞. It has a find fH for a CS amplifier for which gm = 1. The Cgd = 0. and Rsig = 100 k MOSFET is operated at ID = 100 μA and has gm = 1.72 (a) Consider a CS amplifier having Cgd = 0. the upper 3-dB frequency ro /2. β = 100. Find fH . CL = 2 pF.3 pF. Cπ = 10 pF. Compare with the value of fH obtained using the As well. Also. Rsig = 1 k. Rsig = 1 k.1 pF.63 A common-emitter amplifier has Cπ = 10 pF. gm = 5 mA/V. an estimate of the 3-dB frequency fH .71 Find the dc gain and the 3-dB frequency of a MOS Section 10. find fT of two estimates would you consider to be more realistic. and an output part that forms a pole at and CL = 10 pF. Cgs = current-source load with an output resistance equal to ro . gain Vo /Vsig .2 pF. with an output resistance equal to ro of the amplifying Also let CL = Cgs . Find the midband gain AM expressions in Eqs. and Cd b = 5 fF. Which of the IC = 1 mA. Cgd = The amplifier is fed from a signal source with Rsig = 100 k 0. Repeat for the following two fH = fT / gm ro cases: (i) the bias current I in the entire system is reduced by 10. obtain another estimate of fH using fH for the case Cπ = 10 pF. *** = very challenging. and Rsig = 1 k. Rsig = RL = 20 k. β = 100. The transistor is biased to operate at gm = 2 mA/V and is related to the MOSFET fT by the approximate expression ro = 20 k. and Cd b = 20 fF. rx = 0. (a) Show that for rx = 0 and ro = ∞. Note that these are the bipolar counterparts of the MOS RL = 5 k. gm = 4mA/V. the frequencies of the poles fP1 and fP2 . CL = 50 pF. how much a factor of 4. and RL = 10 k. fH . rx = 100 . 798 Chapter 10 Frequency Response PROBLEMS 10. The amplifier is fed from a signal source with Rsig = constants to show that for gm ro 1. CL = 3 pF.69 For the CG amplifier in Example 10.2 pF.94) and (10. the circuit can be determine the new values of AM . (b) CL = 10 pF. Cμ = 1 pF.2 pF. for the following cases: (a) CL = 0. ** = more difficult. where ro is the MOSFET output resistance. Use the method of open-circuit time transistor. and Rsig and feeding a load resistance RL in parallel with a (b) If a CG stage utilizing an identical MOSFET is cascaded capacitance CL .68 Consider a CG amplifier loaded in a resistance RL = ro 10. Use the Miller approximation to determine an estimate of fH . Remember that both Rsig and RL output node and ground to reduce fH to 200 MHz? will change as ro changes.5: High-Frequency Response of the cascode amplifier operated at gm = 2 mA/V and ro = 20 k.9. find the low-frequency a load capacitance CL of 20 fF. with the CS transistor in (a) to create a cascode amplifier. and rx = 0 in the following two cases: (i) Rsig = 1 k 10.74 (a) Show that introducing a cascode transistor to an IC the base to the collector of Q1 will be −gm1 re2 − 1. formula to estimate fH for the amplifier with I = 1 mA. Assuming that RL = Ro . ro = 10. ** = more difficult. which is usually very small. If the cascode transistor is removed and RL remains PROBLEMS frequency and thus will have negligible effect on fH . D = design problem .78 A BJT cascode amplifier uses transistors for which bandwidth in Fig.79 A source follower has gm = 5 mA/V. By evaluating the various components of τH 2π(CL + Cgd ) show that the pole introduced at the output mode is dominant. fZ . μn Cox = 200 μA/V .73 It is required to design a cascode amplifier to *10. Ro (M).80 Using the expression for the source follower fH in and estimate the value of the 3-dB frequency fH . 2 10 V. (10. β = 100. 10.1 pF. Find the overall 2μn Cox (W/L) ft = ID voltage gain at dc. Cgs = 2 pF. CL = 20 fF. 2 (b) For μn Cox = 400 μA/V . and an estimate of fH . 10. and note that the total CL = 1 pF. The load resistance RL = 2 k. k. ro (k). The poles. Cμ = 2 pF. Rsig = 20 k. μn Cox = 400 μA/V .1 mA between a source with Rsig = rπ and a load RL = βro . 10. 200 μA. RL = 2 k. what will the dc gain become? follows that at the frequencies of interest the gain from 10. and Cμ = 0.76 Consider a bipolar cascode amplifier biased at a 20 k.29 to show that β = 100. AM (V/V). and rx = 0. find VOV and ID at which the transistors must be Cπ = 10 pF.1 pF. W/L = 50. Cgd = 5 fF. Section 10.1 Cgs and the dc gain of the CS amplifier is 50. the frequencies of the two 100 k.6: High-Frequency Response of the gm (mA/V). It also unchanged. VA = 100 V. It operates at a bias current of 0. 10. and whose load resistance show that the pole introduced at the input node will have is equal to ro . VOV (V).75 (a) For an integrated-circuit MOS cascode amplifier (ii) Rsig = 10 k fed with a source having a very small resistance and loaded in a resistance equal to its Ro . 1 fP2 2πRL CL + Ccs2 + Cμ2 (b) If Cgd = 0. Use CS amplifier whose bandwidth is limited by the interaction this to find the capacitance at the input of Q1 and hence of Rsig and the input capacitance. and rx = 50 . W/L = 20. use the expression for the unity-gain 10. fT = 1 GHz. Ccs = 0. Problems 799 CHAPTER 10 D 10. Eq. The transistors used have β = 100. and use the sum-of-the-squares 2 (c) If VA = 10 V. Find its frequency and hence an estimate of fH and ft . Ro . gmb = 0. determine the overdrive resistance between the collector of Q1 and ground will be voltage and the drain current at which the MOSFETs should equal to re2 . It follows that the be operated. amplifier is fed with a signal source having Rsig = 5 k. Cgd = 0. increases the dc gain by approximately a factor a frequency of 2 and fH by the factor N. and W/L = 10. and fH (MHz) for Source and Emitter Followers ID = 100 μA. Let CL = Ccs = 0.30.77 In this problem we consider the frequency response provide a dc gain of 74 dB when driven with a low-resistance of the bipolar cascode amplifier in the case that ro can be generator and utilizing NMOS transistors for which VA = neglected. what is the value of N? (b) Evaluate fP1 and fP2 . * = difficult problem. and (a) Refer to the circuit in Fig. ro = and CL = 1 pF. 1 fP1 1 2πRsig Cπ 1 + 2Cμ1 Cgs + (gm ro )Cgd N= 2 Cgs + 3 Cgd Then show that the pole introduced at the output node will have a frequency Assume that the bandwidth of the cascode amplifier is primarily determined by the input circuit. Find AM . and VA = 10 V. Cgd = 0.1 pF. Rsig = Multisim/PSpice. *** = very challenging. Find the unity-gain frequency and the 3-dB pole introduced at this node will typically be at a very high frequency. Ccs = CL = 0. provide in table form ft (GHz). RL = 2 operating. Cπ = 10 pF. Find the low-frequency gain AM .124) show that for situations in which CL = 0. Cμ = 2 pF. current of 1 mA. and 500 μA. fT = 2 GHz. ** = more difficult. Cμ = 0. estimate the 3-dB frequency fH . what is the impact on fZ of this proposed operating? change? 10. fH Cgs (d) If. and using a transistor specified to have bias current is reduced to 80 μA and RD is raised to 20 k. capacitance and hence estimate the 3-dB frequency fH (b) Find the differential gain Ad . 2 (a) Sketch the differential half-circuit and its high-frequency The transistors have W/L = 16. the frequency is a low-voltage. CHAPTER 10 gm = 5 mA/V. kn = 400 μA/V . What is the 3-dB frequency? current-source capacitance to be directly proportional to the What is the value of gm at which the source follower is device width. time-constants method to estimate fH .7: High-Frequency Response resistances is 10 k. bias current I = 100 μA is provided by a single transistor operating at VOV = 0.86 A MOS differential amplifier is biased with a current 10. (Note: This VA = 20 V. let Rsig be raised from 20 k to 100 k. the high-frequency response of the source follower is capacitance CSS = 1 pF. ro = 20 k. 10. equivalent circuit.5-mA current source uses transistors for which β = 100. and rx = 100 . and ro is very large. fT = 500 MHz. Cgd = 10 pF. use the open-circuit Find fH for the case Rsig = 100 k.9 V/V.31(c). = Multisim/PSpice.2 V while keeping I unchanged. In situations in which Rsig is source having an output resistance RSS = 100 k and an output large. CL = 10 pF.87 The differential gain of a MOS amplifier is 100 V/V Using the low-frequency value of K = gm RL /(1 + gm RL ) find with a dominant pole at 10 MHz.85 A MOSFET differential amplifier such as that shown series with each of the two input terminals.26 for the situation in which the Rsig = RL = 1 k.34(a) is biased with a current source I = 400 μA. An estimate of Cin can be obtained by using the CMRR? Miller approximation to replace Cgs with an input capacitance Ceq = Cgs (1 − K) where K is the gain from gate to source.88 In a particular MOS differential amplifier design. having 10.) of the transmission zero.e. rx = 100 .1 V/V at low frequencies and has a transmission zero at 1 MHz. Cgd = 5 fF. low-power design. 10.90 A BJT differential amplifier operating with a 0. is 0. If the differential gain is found to have determined by the low-pass circuit formed by Rsig and the input a dominant pole at 20 MHz. what is the 3-dB frequency of the capacitance. between each drain and ground.8 and a 3-dB frequency of 1 MHz. * = difficult problem. Assuming the gain is found to be 0. VA = 20 V.4 V with VA = 40 V and output 10. (c) If the input signal source has a small resistance Rsig and thus the frequency response is determined primarily by 1 the output pole. and Cgs = 2 pF. Each of the collector Section 10. The common-mode gain Ceq and hence Cin and an estimate of fH . The transfer function of the source follower above its low-frequency value? To meet a requirement for is measured as RL is varied. RL = 2 k. D = design problem . CL = 0. and the gain–bandwidth product.89 Repeat Exercise 10. in Fig. The drain resistors (b) Determine the low-frequency value of the overall differ- are 10 k each.5 pF. gmb = 0. Cμ = 0. in a different situation.81 Refer to Fig. common-mode gain zero fZ at which Acm begins to rise and ro very large.84 For an emitter follower biased at IC = 1 mA. The amplifier is fed of Differential Amplifiers in a symmetrical fashion with a source resistance of 10 k in 10. *** = very challenging.82 A source follower has a maximally flat gain response with a dc gain of 0. 800 Chapter 10 Frequency Response PROBLEMS is large and RL is small. Give 10. β = 100. Also. 10.. Cgs = 40 fF. the its transfer function. the pole frequencies. and For (d). there is a 100-fF capacitive load ential gain. evaluate the low-frequency gain AM .83 A discrete-circuit source follower driven with Rsig = capacitance CSS of 100 fF. 10. 20 k in series with each gate terminal). Cgd = 1 pF. 10. Sketch a Bode plot for the CMRR. and an estimate of the 3-dB frequency fH . consideration is given to reducing transfer function be maximally flat? At this value of RL the dc VOV to 0.1 pF. and Cd b = 5 fF. 10. What is the frequency of the 100 k has Cgs = 10 pF. the amplifier is fed symmetri- 2πRsig Cgd + 1 + gm RL cally with a signal source of 40 k resistance (i. (c) Use the Miller approximation to determine the input (a) Find VOV and gm for each transistor. At what value of RL will the reduced power supply. and β0 = 100.98 For the CS amplifier with a source-degeneration characterized by fT = 500 MHz. Problems 801 Section 10. ft . The differential gain exhibits a dominant pole at 10.2 mA. ggd = 0.2 mA.2 V. and the frequencies of the poles and zero of the differential ro = 40 k. 2. and the gain–bandwidth product capacitance at the input node of the mirror is 0. ro Rs . *** = very challenging. voltage gain. Rsig = 20 k. Assume the BJTs to be identical. the total capacitance at the output node CL be four times (b) If a 400- resistance is connected in the source lead. 10. fH . (10. D = design problem . and fZ and sketch a Bode to determine the gain–bandwidth product of a CS amplifier plot for Ad . Adapt the formulas given in the text for transistors of the differential pair are operating at VOV = 0. fP1 . Assume Cgd = 0. Rsig = 20 k.96 A CS amplifier is specified to have gm = 5 mA/V.92 A current-mirror-loaded MOS differential amplifier the bandwidth. The amplifier is specified to have gm = 5 mA/V. 10. The Early voltage VAn = VAp = 10 V.95 Consider the case of a discrete-circuit CS amplifier in 2 MHz. RL = 5 k.94 Cgs = 2 pF. with a source-degeneration resistance. ro = 40 k. and RL = 40 k. Let PROBLEMS and the PMOS devices of the mirror are operating at |VOV | = Rsig = 100 k.. and 200 . Cgs = 2 pF. Hence operated at the same VOV and having the same VA .94 For the current mirror in Fig. at the output node of the amplifier is 0. Cgd = 0. The total Cgd = 2 pF. Cμ = 2 pF. * = difficult problem. Also let determine the gain–bandwidth product. and the gain–bandwidth Cm . this case and thus give the expressions for AM and fH . and fZ . AM = 2+k and Cgs Rsig A0 τH + Cgd Rsig 1 + 1 + (k/2) 2+k 1+k + CL + Cgd ro 2+k where k ≡ gm Rs D *10. gm = 5 mA/V. and CL = 1 pF. and RL = ro that find the frequencies of the pole and zero of the transfer −A0 function. If the mirror is biased at 1 mA and the BJTs at this operating point are 10. The two NMOS negligibly small.1 pF. CL = 1 pF. fP2 . fH .8: Other Wideband Amplifier CHAPTER 10 10. Cgs = 10 pF.93 Consider the current-mirror-loaded CMOS differen- (a) Find the low-frequency gain AM . and use open-circuit tial amplifier of Fig. ** = more difficult. I = 0. resistance Rs . Give expressions for Ad .156) of Ad . the total capacitance at the input node of the current mirror find the new values of AM .2 V. Assume that ro is very large and CL is is biased with a current source I = 0.94. RL = 40 k. Find the dc value 10. fH . P10.2 V. 1. and RL = 20 k.2 pF.99 It is required to generate a table of AM . find rx and ro . . and the value of fP1 . 15. 100 . Figure P10. VOV = 0. show for Rsig Rs .91 A differential amplifier is biased by a current source having an output resistance of 1 M and an output capacitance Configurations of 1 pF. The table should have entries for k = 0.2 pF and Rsig = 100 k. A0 = 100 V/V. Use the formulas = Multisim/PSpice. *10. find the dc value D 10. For VA = 20 V. . fP2 /fP1 = 4Ad and ft = gm /2πCL . and 0. fP2 .1 pF and that for these three cases: Rs = 0. Hence show that product. derive an (b) If a low-frequency gain of 20 V/V is required. signal ground appears at the collector of Q2 . CL = 100 fF. . Find |AM |. what fH expression for the current transfer function Io (s)/Ii (s) taking corresponds? into account the BJT internal capacitances and neglecting (c) For gm = 5 mA/V. and Cm = 25 fF. and ft versus k ≡ gm Rs for a CS amplifier with a source-degeneration resistance Rs . What are the poles of the CMRR? which a source-degeneration resistance is utilized to control 10. Observe that a the required value of Rs .37(a) for the case of all transistors time constants to estimate the 3-dB frequency fH .1 pF.97 (a) Use the approximate expression in Eq. and of 100 μA. find ro1 the value needed for Rs and the AM = − g r corresponding value of AM . 802 Chapter 10 Frequency Response for AM and τH given in the statement for Problem 10. At a bias current ro = 20 k. fH .101 = Multisim/PSpice.100(a). * = difficult problem.100(b). fH .100 100 A Rsig Vsig 100 A Figure P10. VA = 100 V. and the gain–bandwidth product for the same parameter values used in (a). Show that + CL ro2 AM = −gm ro Calculate the values of AM . fT = 200 MHz.101 have gain–bandwidth product for the case gm = 1 mA/V.) I I Vo Vo Rsig Rsig Q1 Q2 Vsig Vsig I (a) (b) Figure P10. + Cgd2 ro1 1 + gm2 ro2 + ro2 CHAPTER 10 gm1 (a) First consider the CS amplifier of Fig. 1/gm1 + ro1 m2 o2 Rsig + ro1 1 τH = Cgd1 Rsig + Cgs1 + Cgs2 ro1 *10. shown. Cgd = 5 fF. P10. P10. and the *10. (Note that the bias details are not CL = 10 fF. β 0 = 100. Compare τH = Cgs Rsig + Cgd Rsig 1 + gm ro + ro + CL ro with the results of (a). Cgs = 20 fF. P10. show that fH = 2 MHz is required.101 The transistors in the circuit of Fig. D = design problem . and Cμ = 0.100 In this problem we investigate the bandwidth 1 + gm1 ro1 gm1 extension obtained by placing a source follower between the 1 signal source and the input of the CS amplifier. Rsig = 20 k. *** = very challenging.98. ** = more difficult. where CL is the total capacitance between the output node and ground.2 pF. If PROBLEMS (b) For the CD−CS amplifier in Fig. Calculate the value of AM . (b) Figure P10. design the circuit to obtain a gain effect is negligible. and an estimate of fH . P10. 10. RD = 50 k. They are biased at the same VGS and have the same fT . Specify the required values of W1 and I. CL (at the output node) = 1 pF. Bias the MOSFETs at VOV = 0. and Cgd = 0.105(a). the MOSFET can be modeled by the of 3 V/V per stage.2 V. 10. Cgs = 2 pF. Such Figure P10. D = design problem . Problems 803 CHAPTER 10 (a) Find Rin and the midband gain. let I = 1 mA. Vo G0 =− Vi s 1+ VDD ωT / G0 + 1 where gm1 W RD G0 = = 1 gm2 W2 Vo Rsig Q1 Q2 Vsig I (a) Figure P10.41(c) for the case gm = 5 mA/V. fT = 12 GHz. P10. 1990). 10. find AM and fH .104 Consider the CD–CG amplifier of Fig. (Hint: Evaluate fH directly from the transfer function.102 Consider the circuit of Fig. If the amplifier is fed with a signal Vsig having a source resistance Rsig = 12 k. What is the 3-dB where ωT is the unity-gain frequency of the MOSFET. the given by high-frequency poles. fT = 500 MHz. and neglect rx and ro . Find the dc gain. Cgd = 0.5 pF.41(a).1 pF.13. Assume that a load resistance of 10 k is connected to the output terminal.5 pF. Which for the realization of low gain and wide bandwidth. Show that the voltage gain Vo /Vi is PROBLEMS Cgs = 4 pF.105(b) shows an amplifier stage suitable (b) Find an estimate of the upper 3-dB frequency fH . capacitor dominates? Which one is the second most Transistors Q1 and Q2 have the same channel length L but significant? different widths W1 and W2 .105 This problem investigates the use of MOSFETs (b) in the design of wideband amplifiers (Steininger.103 For the amplifier in Fig. and Cμ = 0.5 μm. W2 = 25 μm. *** = very challenging. and 2 the common-source amplifier is low so that the Miller μn Cox = 200 μA/V . P10. 10.) D **10. ** = more difficult. Rsig = 100 k. an identical stage. and Rsig = RL = 20 k.102 for the case: assuming that its output is connected to the input of I = 200 μA and VOV = 0.102 10.) circuit of Fig. β = 120. (a) Show that for the case Cgd Cgs and the gain of (c) For L = 0. Neglecting ro .3 V.105 amplifiers can be realized by cascading low-gain stages. frequency achieved? = Multisim/PSpice. * = difficult problem. Use the MOSFET equivalent (Hint: Use the formulas in Example 10.105(a) to model this amplifier stage. approximate equivalent circuit shown in Fig. find AM and fH . The NMOS transistor has voltage of 0.8 pF. Each of Q 1 and Q2 is operated at an overdrive Cμ = 0. The transistor capacitances 2 Vt = 1 V. and fT = 600 MHz.106 ro . and fT = 400 MHz. respectively. and VA = 10 V.108 In each of the six circuits in Fig.7 V. 804 Chapter 10 Frequency Response PROBLEMS *10. determine an estimate for the 3-dB frequency fH . VDD determine the small-signal voltage gain Vo /Vi . and show that they are approximately (b) Use the method of open-circuit time constants to 100 μA and 1 mA.106 shows an amplifier formed by **10.106 Figure P10.1 mA theorem on RG to determine the amplifier input resistance Rin . *** = very challenging. Q1 0. fL .) Then use Miller’s 0.107 = Multisim/PSpice. (Note that RG can be neglected in this process. 5 V 3k C2 RG 10 M Vo C1 1 F 100 k Vi Q1 1k 0. Vsig (The one at the output will be too large to matter. and hence estimate the lower 3-dB frequency. determine the overall voltage gain Vo /Vsig . is not shown. Cgd = 5 fF.107 Consider the BiCMOS amplifier shown in cascading two CS stages. in Q1 and Q2 .2 V. are as follows: Cgs = 20 fF. P10. Cμ = 2 pF. and Cd b = 5 fF. Note that the input bias voltage Fig. Q2 (d) Consider the circuit at low frequencies. β = 200.108.8 k Rin Figure P10. * = difficult problem. First. ** = more difficult. P10. Assume ro of both transistors to be very large.1 mA (e) Consider the circuit at higher frequencies. in determining the current in Q1 . D = design problem . ***10. The BJT has VBE = 0. Find the dc bias currents CHAPTER 10 (a) Find the dc voltage gain. Finally. and neglect rx and Figure P10.1 F Q2 Vsig 6.) Use open-circuit time constants to estimate fH . Determine the Rsig Vo frequency of the poles due to C1 and C2 . The (a) Consider the dc bias circuit. kn W/L = 2 mA/V . let β = 100. (c) Consider the circuit at midband frequencies. and Cgs = Cgd = 1 pF. Calculate the midband gain AM and the 3-dB frequency fH . Neglect the base current of Q2 signal-source resistance Rsig = 10 k.107. (b) Evaluate the small-signal parameters of Q1 and Q2 at their bias points. Use Miller’s theorem to replace RG with a resistance at the input. 108 . Problems 805 CHAPTER 10 Vo Vo Vo PROBLEMS Vsig Vsig Vsig (a) (b) (c) Vo Vsig Vo Vsig (d) (e) Vo Vsig (f) Figure P10. the difference is the phase margin. = Multisim/PSpice. expressed and Ro . Note that R2 if a particular parameter value is not specified in the problem statement.1: The General Feedback Structure Figure P11.e. change in Af corresponding to this factor of 10 reduction in A? (ii) A = 200 V/V. R1 Section 11. you are to make a reasonable assumption. what closed-loop gain results? What is the percentage for the following three cases: (i) A = 1000 V/V. Instructions to assist in setting up PSpice and Multisim simulations for all the indicated problems can Vo Vs be found in the corresponding files on the website. This causes the pole formed at the input of the amplifier stage to shift to a lower frequency and thus For the feedback amplifier to be stable.2). is the gain margin. What is the feedback (a) Convince yourself that β = R1 / R1 + R2 . * = difficult problem. Alternatively. ω180 ).1 A negative-feedback amplifier has a closed-loop gain 4 Af = 200 and an open-loop gain A = 10 . the phase feedback loop.896 Chapter 11 Feedback desensitivity.2 Consider the op-amp circuit shown in Fig. the amplifier stage is moved to a very high frequency and Stability is guaranteed if at the frequency for which the thus becomes unimportant. in decibels. the A popular method for frequency compensation involves poles of the feedback amplifier are obtained by solving connecting a feedback capacitor across an inverting stage the characteristic equation 1 + A(s)β(s) = 0. |Aβ| is less than splitting. is incomplete as it does not enable the a plot for 20 log 1/|β|. This method. modified by a process known as frequency compensation. For plots intersect with a difference in slope no greater than these. Stability is guaranteed if the two determination of the input and output resistances. ** = more difficult. its poles must all become dominant. as illustrated in Figs. and to investigate important issues such as allowable signal swing and amplifier A nonlinear distortion. at the frequency at which |Aβ| = 1. intended to demonstrate the value of using SPICE simulation to verify hand analysis and design. find R2 that results in Af = 10 V/V 3 to 10 . the amplifier The loop gain Aβ can be determined by breaking the is stable if. bandwidth extension. constructing a Bode plot for |A| and superimposing on it though simple. PROBLEMS Computer Simulation Problems 11.2 11.9. This process is known as pole phase angle of Aβ is 180° (i.2 and 11. Since A and β are in general frequency dependent. The angle is less than 180°. D = design problem . To make a given amplifier stable for a given feedback The ideal or upper-bound value of the closed-loop gain factor β. factor β? If a manufacturing error results in a reduction of A (b) If R1 = 10 k. while the pole formed at the output of be in the left half of the s plane. the open-loop frequency response is suitably Af is 1/β and is approached when Aβ 1. 11. the amount by which it is less than unity. value of Aβ can be used together with the feedback The stability of a feedback amplifier can be analyzed by factor β to determine A and hence Af . in the amplifier.. and changes in Ri unity. analysis (refer to Table 11. (iii) A = 15 V/V. where the op amp has infinite input resistance and zero Problems identified by the Multisim/PSpice icon are output resistance but finite open-loop gain A. P11. *** = very challenging.2. we utilize the systematic method for feedback 6 dB/octave. loop gain Aβ for which the sensitivity of closed-loop gain identify values of A. (dAf /Af )/(dA/A)] is –40 dB.1%. *** = very challenging. and 0.1. use the method outlined in Section 11. Problems 897 CHAPTER 11 (c) For each of the three cases in (b).000 V/V. Thus show that of Fig. value of 1000 but can vary from unit to unit by as much as Comment on the results. value of Aβ does the sensitivity become 1/5? = Multisim/PSpice.9 The op amp in the circuit of Fig.e. (b) 10 V/V. (d) 1000 V/V. * = difficult problem. Provide your results in a table in which there is a row for each value of A and a column for each value of β. the open-loop gain A is no longer simply equal to μ. It is connected in the noninverting configuration with a feedback network consisting of a voltage divider (R1 . For this Rid A=μ arrangement.3 provides a direct implementation of the feedback the largest possible nominal value of closed-loop gain that can loop of Fig. Rid + (R1 R2 ) 11.1.50 in the middle. placed in cascade.00 R1 at the other end. D = design problem . a signal of 1 V from the source results in a difference signal of 10 mV being provided to the amplifying element A. a differential input resistance A Rid . Assuming that the op amp has infinite input be achieved? Now if three of these feedback amplifiers are resistance and zero output resistance. the β network consists R2 of a linear potentiometer for which β is 0. find Vo and Vi . what is β? If A = 1000. β. It is required to apply negative feedback to this amplifier so that the variability of the closed-loop gain 11. To determine the value of A.7 A newly constructed feedback amplifier undergoes a Section 11. ±50% of nominal. 11. a 5-V 11. find the percentage D 11.2: Some Properties of Negative performance test with the following results: With the feedback Feedback connection removed. find the three values of closed-loop gain that result when the amplifier open-loop gain is (a) 1 V/V. P11. 1. and 5 V appearing at the output. β = R1 /(R1 + R2 )]. This is because the feedback network now loads the input of the Figure P11. 11.6 In a particular amplifier design.9 has an open-circuit voltage gain μ. 11.. While β is still determined by the divider ratio [i. identify the values of A and β that apply. What is in Fig. 11. (ii) 1%. As the potentiometer is adjusted.1.4 In a particular circuit represented by the block diagram the loop gain Aβ.5 (a) Show that in a negative-feedback amplifier with loop gain Aβ 1.8 An amplifier has an open-loop gain with a nominal change in Af that results when A decreases by 20%. and a negligibly small output resistance. P11. with the feedback connected. and the to open-loop gain [i. For this amplifier. and (e) 10. Aβ. what is the corresponding percentage decrease in Af ? 11. ** = more difficult. find the output requires a 100-mV source signal.9 (c) 100 V/V.3 to determine 11. a source signal of 2 mV is required to provide a 5-V output. m (b) What is the minimum loop gain required so that Af is within (i) 0. the closed-loop gain. the closed-loop gain Af is lower than its ideal value of 1/β by (100/Aβ)%. For what amount of feedback (in dB)..1.10 For the negative-feedback loop of Fig. If A decreases of this gain? by 10%.00 at one end.3 The noninverting buffer op-amp configuration shown of the resulting feedback amplifier is limited to ±1%.e. Figure P11. what is the nominal value of the gain of the PROBLEMS what is the closed-loop voltage gain? What is the amount of resulting cascade amplifier? What is the expected variability feedback (in dB)? For Vs = 1 V.3 amplifier (because of the finite Rid ). R2 ). and (iii) 5% of its ideal value? Vs Vo 11. 13 A circuit designer requires a gain of 25 ± 1% V/V s = −ωL and a zero at s = 0. If only 2% drop in a dominant high-frequency pole at 20 kHz.) resulting dc bias current in the speaker can use up (and thereby waste) its limited mechanical dynamic range. to design employs an amplifier for which A = 1000 V/V and what value must A be raised to ensure the required minimum the other uses A = 500 V/V. amplifier whose gain reduces to half its normal full-battery You have available gain stages with a gain of 1000 but with value over the life of the battery. D 11. Provide a design closed-loop gain is desired. One β network may produce as much as a ±1% variation in β. D = design problem . it is inaccurate to use differentials. what specification. capacitor can be used? D *11. it should provide a If the same result is to be achieved with the A = 500 reduction in Af to 99 V/V for a reduction in A to one-tenth its amplifier. * = difficult problem. Negative feedback is that an overall gain with feedback of 100 ± 5% V/V can be employed so that the midband gain is reduced to 10. with each stage employing negative Af = 10 V/V is obtained from an amplifier whose open-loop feedback of an appropriate amount. You have available helps. Provide a design that uses a number of these around the amplifier and the speaker so that a closed-loop gain gain stages in cascade. what is the maximum allowable uncertainty in nominal value. a single high-frequency pole at 10 kHz.1% V/V using a basic amplifier whose gain variation tenfold? If A were made infinite? is ± 10%.16 It is required to design an amplifier to have a D *11.) both changed? D 11. What nominal value of A and β (assumed constant) 11. if feedback is arranged within ±30%.15 It is required to design an amplifier with a gain the coupling capacitor needed can be large! But feedback of 100 that is accurate to within ±1%.12 A designer is required to achieve a closed-loop gain What would the closed-loop gain become if A were increased of 10 ± 0.17 Design a feedback amplifier that has a closed-loop a gain uncertainty of ±10%.21 It is required to design a dc amplifier with a nominal closed-loop gain of 10 V/V using a battery-operated low-frequency gain of 1000 and a 3-dB frequency of 1 MHz. Unfortunately. ** = more difficult. Use identical in A is large. What is the lowest gain required? The an expression for the midband gain and the lower 3-dB value of β? (Hint: Since the change in the open-loop gain is frequency of the closed-loop amplifier. and a of an ideal (nonvarying) amplifier connected to drive it so single low-frequency pole at 100 Hz. what nominal open-loop amplifier that employs a number of such stages in cascade. Find temperature and time.5%? For each of gain? these situations. Let the amplifier be connected using an amplifier whose gain varies by a factor of 10 over in a negative-feedback loop with a feedback factor β. do not use differential analysis. Obviously.18 Consider an amplifier having a midband gain AM are required? and a low-frequency response characterized by a pole at D 11. In particular.14 A power amplifier employs an output stage whose 11. *** = very challenging. amplifier stages with a gain of 1000 that is accurate to what size capacitor is needed? Now. What is the required loop gain? What nominal its gain? value of A is required? What value of β should be used? D 11. Find β and the desensitivity gain? factor in both cases. what is the gain uncertainty gain of 100 V/V and is relatively insensitive to change CHAPTER 11 for the closed-loop amplifiers utilizing this amplifier type? in basic-amplifier gain.20 Low-cost audio power amplifiers often avoid direct tolerances)? (Hint: Since the change in the open-loop gain is coupling of the loudspeaker to the output stage because any very large. 898 Chapter 11 Feedback PROBLEMS D 11. = Multisim/PSpice. what preamplifier gain and feedback factor β are required if Af is to be 10 V/V (with the two possible D 11.11 A designer is considering two possible designs of of β should be chosen? If component-value variation in the a feedback amplifier. for an 8- loudspeaker and fL = 100 Hz. What is the gain of 1000 V/V.19 A capacitively coupled amplifier has a midband gain gain varies from 2 to 12 for various reasons. What achieved? What is the value of β to be used? What are the are the upper and lower 3-dB frequencies of the closed-loop requirements if Af must be held within ±0. For example. do not use differential analysis. each with gain must be used in the design? (Note that since the change negative feedback of an appropriate amount. The ultimate goal is Af = 10 V/V. If the A = 1000 amplifier units have D 11. your design gain is 1000 V/V.) What value stages. what value of fLf results? If the ultimate should use the lowest possible number of stages while meeting product-design specification requires a 50-Hz cutoff. By what factor have very large. calculate the loop gain Aβ and use it to find the actual value of the closed-loop gain Af .7 V. 11. and the power-supply ripple 1 PROBLEMS VN = ± 1 V. Figure P11.23 A feedback amplifier is to be designed using a feedback loop connected around a two-stage amplifier. what value should R2 have to obtain an ideal closed-loop gain of 10? Now.24(a) has the approximate transfer characteristic (c) For large input signals. specify the value required for the feedback (b) factor β. Sketch the transfer characteristic power-output stage with a midband gain of 10 V/V and upper v O versus v S of the resulting feedback amplifier. The second stage is a the emitters of the follower.8(a). 11. * = difficult problem. 11.3: The Feedback Voltage Amplifier D 11.22 Design a supply-ripple-reduced power amplifier for 1 0. each with a 3-dB frequency f3dB |stage is given by 1 √ f3dB |cascade = f3dB |stage 21/N − 1 1 D 11. a zero output resistance. where A1 = 0.25 A particular amplifier has a nonlinear transfer the required gain of the small-signal amplifier? What value characteristic that can be approximated as follows: of β should be used? What does the lower 3-dB frequency of (a) For small input signals. What is D 11. small-signal amplifier source v S and whose negative-input terminal is connected to with a high upper 3-dB frequency.27 Consider the series–shunt feedback amplifier in Fig. the output is zero. what must the value of R2 be? D 11. Observe that for −0.3).7 0 0. *** = very challenging. whose positive-input terminal is connected to the input signal The first stage is a direct-coupled.26 For the feedback voltage amplifier of Fig. = Multisim/PSpice. 10 mV ≤ v I ≤ 60 mV. Consider this follower to be the feedback factor βthat reduces the factor-of-10 change in driven by the output of a differential amplifier of gain 100 gain (occurring at v I = 10 mV) to only a 10% change. Problems 899 vO CHAPTER 11 Hint: The 3-dB frequency of a cascade of N iden- tical gain stages. P11.24 The complementary BJT follower shown in v O /v I = 10 . respectively.5. What are and lower 3-dB frequencies of 8 kHz and 80 Hz. ** = more difficult. vI vO If R1 = 10 k. If Af is to be exactly 10. P11.7 V ≤ v I ≤ +0. let the op amp have an infinite input resistance. v O /v I = 10 . v I ≤ 10 mV. v I ≥ 60 mV. 3 the overall amplifier become? (b) For intermediate input signals. shown in Fig.11(a). What is the transfer characteristic v O versus v S of the amplifier with V feedback? Section 11.7 vI which the output stage can be modeled by the block diagram of Fig.9 V/V.24 closed-loop gain of 10. find distortion (see Section 12. the output saturates. 2 Fig.3. and a finite open-loop gain of 1000 V/V. the limits of the dead band. and what are the gains outside the The feedback amplifier should have a midband gain of dead band? 100 V/V and an upper 3-dB frequency of 40 kHz.24 continued D 11. which is analyzed in Example 11. V (a) If R1 = 10 k.24(b). A closed-loop gain of 10 V/V is desired. This “dead band” leads to crossover If the amplifier is connected in a negative-feedback loop. What is the gain of the low-ripple preamplifier needed to reduce the output ripple to ±100 mV? To ±10 mV? To ±1 mV? For each case. *11. D = design problem . find the value of R2 that results in an ideal (a) Figure P11. 11. which was the subject of Exercise 11. Vo (b) Find the dc emitter current in each of Q1 and Q2 . Vs RS1 RS2 find the dc voltage at the emitter of Q2 . within 1% of the ideal value of 10? Find the value of R1 that results in a closed-loop gain of 5 V/V. You may neglect closed-loop gain whose ideal value is 5 V/V? their ro ’s. 100 100 (c) Calculate the value of the loop gain Aβ. and RL = 10 k. Rs = 100 k. ro = 1 k.31 shows a series–shunt feedback amplifier known as a “feedback triple. RD = 10 k. Q2 (a) If the loop gain is large. Figure P11. Also.31 Figure P11. Assume that the MOSFET is biased (c) By what factor must μ be increased to ensure that Af is so that gm = 4 mA/V and ro is large. and 10 k Q3 RL = 1 k. Also. (Hint: Set Vs = 0 and break the loop at the base of Q1 . hence determine the closed-loop gain Af . *** = very challenging.6. P11. Simplify the circuit Rout2 by eliminating dc sources.3 to D 11. RD1 = RD2 = 10 k. (b) If gm1 = gm2 = 4 mA/V.8(b) that is analyzed in Example 11. what value should R2 have to obtain a are biased to operate at gm = 4 mA/V.2.1 mA Q2 R2 Q1 Vo CHAPTER 11 Rs R1 RL 1 mA Vs Rin Rout Figure P11. The input signal Vs has a zero dc component. 900 Chapter 11 Feedback PROBLEMS 0.29 In the series–shunt feedback amplifier shown in Io Fig.29 (b) Use the expression for Aβ derived in Example 11. *11. D = design problem .29.8(c).” All three MOSFETs (a) If R1 = 1 k. Assume Rid = 100 k. the devices operate with VBE = 0. that the voltage divider (R1 . * = difficult problem. 1-M potentiometer. use the expression for Aβ (a) Select a value for RF that results in a closed-loop gain derived in Example 11. what do you expect the closed-loop gain to be? Give both an expression and Q1 RF its value.7 V and have RD2 Rout1 β1 = β2 = 100. Fig. R2 = 10 k. D 11. R1 = 1 k. and the MOSFET’s ro is very large. R2 ) is implemented with a Hence determine the value of the closed-loop gain Af . D 11. 11.30 Consider the series–shunt feedback amplifier of find the value of the loop gain for the case μ = 1000.28 Consider the series–shunt feedback amplifier of Fig. ** = more difficult.31 = Multisim/PSpice. 10 k RD1 Resistances Rs = 100 .2 to find the value of Aβ and that is ideally 10 V/V.) (d) Calculate the value of Af . find the fier without details of the bias circuit. and that RC1 = 2 k and RC2 = 1 k. Af equal to 10? (b) If Q1 is biased at 1 mA. *** = very challenging.33 has a feedback network consisting of the voltage RC 2 divider (R1 . and assuming that the transistors have hfe = 100 and 11. value of the loop gain Aβ and hence of the closed-loop VCC gain Af . By what percentage does Af differ from the ideal value that results in a closed-loop gain with an ideal value you designed for? How can you adjust the circuit to make of 25 V/V. The Q3 input signal source has a zero dc component. P11. and Q3 at 5 mA.4: Systematic Analysis of Feedback RE Voltage Amplifiers (Series–Shunt) 11. PROBLEMS D 11.32 Figure P11. The feedback factor β = 0. D = design problem . Problems 901 (a) If RE is selected to be 50 . For all devices. ** = more difficult. Q2 (a) Find the loop gain Aβ and hence the value of A. find the value for RF CHAPTER 11 (b) Determine the loop gain Aβ and hence the value of Af .33 = Multisim/PSpice. (b) Find the values of R1 and R2 that result in a closed-loop Vs Q1 gain of exactly 5 V/V. with R1 + R2 = 1 M.34 A series–shunt feedback amplifier employs a basic amplifier with input and output resistances each of 2 k and gain A = 1000 V/V.32 shows a series–shunt feedback ampli- large ro . The devices are sized RC 1 to operate at |VOV | = 0.32 VDD Q3 Q4 Vo R1 Rs Q1 Q2 Rout Vs R2 200 A Figure P11. Q2 at 2 mA. |VA | = 10 V. Vo RF Section 11.33 The current-mirror-loaded differential amplifier in Fig.2 V. R2 ). * = difficult problem.1 V/V. Find Figure P11. * = difficult problem. Aβ. Let Vt = 0. what do you expect some of the results in the solution of this problem. Ri . and Ro . Also find the dc and an input resistance of 1000 has a closed-loop input voltage at the output.7 V.36 The formulas for Ri f and Rof in Eqs. Assume that the what input resistance do you expect? bias current sources are ideal. amplifier is used to implement a unity-gain voltage buffer.40 Figure P11. The of a series–shunt amplifier that has an input resistance Ri . Ignore the Early effect. Consider the case 0 V dc being minimized by the negative-feedback action. The devices the closed-loop voltage gain Vo /Vs to be approximately? operate with VBE = 0. and Rout . Verify that each of the current R1 = 1 k.20) and D *11. find the dc voltages at signal Vs has a zero dc component.4 for the case R1 = ∞ and R2 = 0. ** = more difficult. Derive 11. (e) Find the gain with feedback. What is the closed-loop gain? If the basic (c) Find gm and ro of each of the five transistors.38 Consider the noninverting op-amp circuit of Example Rout . and the output resistance 11. respectively. find the dc 11. A. P11. measurement of the (d) Give an expression for β and find its value. together (a) Show that the feedback is negative. The input (c) If Vs has a zero dc component. closed-loop gain Vo /Vs to be? Give both an expression (d) Find the A circuit. S3 .2 V. (11. you can use (b) Assuming the loop gain to be large. utilize single transistors and thus have output resistances *11.35 For a particular amplifier connected in a feedback loop expressions for A. find the dc voltage at the emitter of Q2 . Rid = 100 k. and G3 . 11. Find Zi f and Zof and give an equivalent circuit for each. sources has the minimum required dc voltage across it for (a) If the loop gain is large. what is Ro without feedback? in (a)? 11. ro = 1 k. Resistances Rs = 100 .37 A feedback amplifier utilizing voltage sampling and current and the overdrive voltage at which each of Q1 to employing a basic voltage amplifier with a gain of 1000 V/V Q5 is operating. the resulting impedances so that v O = 0 for v S = 0.4 to obtain *11. the input resistance Rin . By what percentage does higher or lower? What is the value of the loop gain Aβ ? If the value of Af differ from the approximate value found Rof is 100 . nodes S1 . Af . R2 = 10 k. find A. what do you expect the proper operation. an technology utilized has k = 2k = 120 μA/V 2 . and RL = 1 k. output resistance Ro . The current sources RL = 2 k. In this case. Rin .5 V and VA = 10 V. CHAPTER 11 a change by a factor of 200.39 This problem deals with the series–shunt feedback equal to ro . Is the resistance with feedback and the output resistance Rout . = Multisim/PSpice. Thus. (c) Sketch the A circuit without the dc sources. and the gate terminals of Q1 and Q2 grounded. stages and the overall voltage gain. The amplifier is designed function of frequency. and the output resistance (b) Find the dc emitter current in each of Q1 and Q2 .41 Figure P11. output resistance before and after the loop is connected shows (e) Find the closed-loop gain Vo /Vs . and a feedback factor β that is independent of frequency. V = 0. Rs = 10 k.29.29. and what is the ideal value of the voltage gain of 5 V/V? What is the value of output closed-loop gain? resistance obtained? (b) Adapt the expressions found in Example 11. (b) With the feedback loop opened at the gate of Q2 . Also Rof of the closed-loop amplifier. and open-loop gain A = A0 / 1 + s/ωH . also apply for the case in which A is a fier with a feedback factor β = 1. with small deviations in v O from Zi f and Zof will be functions of frequency. 902 Chapter 11 Feedback PROBLEMS the gain Af . resistance of 10 k. the input resistance Ri f . 11. *** = very challenging. Calculate the gain of each of the three and its approximate value. G2 . and find their values.40 shows a series–shunt ampli- (11.41 shows a series–shunt amplifier in expressions for A and Aβ for this case.29 and overlaps somewhat with Problem (a) Show that the feedback is negative. amplifier of Fig.7 V and have β1 = β2 = 100. n p t and VA = 24 V/μm. in which the output voltage is sampled. which the three MOSFETs are sized to operate at VOV = 4 (c) For μ = 10 . and 0. with the values of all the elements in the equivalent circuits.23). (d) Find expressions and values of A and Ro . if you have already solved 11. Af . (f) How would you modify the circuit to realize a closed-loop (a) What is the value of β. D = design problem . D = design problem .1 mA G2 Q2 G3 Q3 S3 Q1 Vo I2 0.9 V 2k Figure P11. ** = more difficult. (g) Find the output resistance Rout . By what percentage does this lead has an effective transconductance gm / 1 + gm Rs and value differ from the approximate value obtained an output resistance ro 1 + gm Rs .] in (b)? (e) Find β. Problems 903 2.1 mA S1 Vs R2 Rout 18 k R1 VDC 0.8 mA 200 A 2. = Multisim/PSpice.41 [Hint: A CS amplifier with a resistance Rs in the source (f) Find Af = Vo /Vs .1 mA I3 0.5 V CHAPTER 11 Q3 Q4 (40 1) (120 1) Q5 (20 1) 300 A PROBLEMS Q1 Q2 vO (20 1) (20 1) vS Rout 0.5 V Figure P11. *** = very challenging. * = difficult problem.8 V I1 0.40 VDD 1. * = difficult problem. The input signal source has a zero dc component. For this purpose.33.43(b) (g) As an alternative approach to (f) above. 904 Chapter 11 Feedback PROBLEMS VDD 2. Derive an expression for A and find its μA. The current-mirror-loaded differential amplifier has in a 1-μm technology for which Vtn = −Vtp = 0. source follower Q5 at VOV = 0.43 The CMOS op amp in Fig. redo the analysis is connected between the output terminal (Out) of the A circuit including RL . μn Cox = a feedback network consisting of the voltage divider R1 . output. Then utilize the values of and the inverting input terminal (–In) to provide negative = Multisim/PSpice. find ID and W/L. (e) The 100-k potentiometer shown in Fig.33. All transistors in R1 + R2 = 1 M. (a) It is required to perform a dc bias design of the circuit. (b) What is the allowable range of input common-mode (f) Utilizing the open-circuit. find the value of gain (c) Find gm for each of Q1 . VOV = 0.42 This problem deals with the series–shunt feedback R1 and R2 found in (d) to determine β and Af . and operate all transistors except for the value. *** = very challenging. P11.43(a) is fabricated results. and VA = 10 V/μm. and VO = 0. Assume that Q1 and (d) Select values for R1 and R2 to obtain a closed-loop voltage Q2 are perfectly matched.25 V. Compare amplifier of Fig.. (a) Show that the feedback is negative. let the two input terminals be at zero (b) What do you expect the dc voltage at the gate of Q2 to volts dc and neglect channel-length modulation (i. 11.e. calculate ro . you will have the opportunity to compare D **11. (e) Find the value of Rout . closed-loop gain (5 V/V) and voltage? the value of Rout found in (e). For each transistor. The devices with are sized to operate at the circuit have L = 1 μm. and similarly for Q3 and Q4 . 2 2μp Cox = 100 μA/V .33. For all devices.75 V. ** = more difficult. R2 . Design to obtain ID1 = ID2 = 50 μA.) VA = ∞). gain Vo /Vs = 5 V/V.5 V (a) (b) Figure P11.2 V.5 V Q3 Q4 Q5 80 k CHAPTER 11 In Q1 Q2 In Out Out R1 Q7 In 100 k Q6 Q8 R2 VSS 2. D = design problem . ID5 = 250 (c) Find the A circuit. P11. Certain aspects of this amplifier the value of Af to that found in (f). obtained when a resistance RL = 10 k is connected to the (d) For each transistor. If you have already solved problem 11. VA = 10 V. and Q5 . Q2 . were considered in Problem 11.43 D *11. let be? At the output? (Neglect the Early effect. Vo R + RE (d) Sketch the A circuit and determine A. (a) Show that the feedback is negative. and a 1-k output resistance. fed by a signal source with a 9-k resistance. what of about –10 and a voltage gain of Q2 of about –50. The potentiometer is adjusted to obtain a closed-loop gain Af ≡ Vo /Vs 10 V/V. D *11. a 20-mA/V short-circuit excluding RL ? transconductance. and the value of β. Toward this end. and ground. A load resistance (f) Calculate the input and output resistances of the RL = 100 k is connected between the output terminal closed-loop amplifier designed. a 20-V/V A circuit (supply a circuit diagram). and a 3. D = design problem . (i) If the high-frequency response of the open-loop gain A is and assuming that the transistors have hfe = 100. Af ≡ F Vs RE (e) Find β and the amount of feedback. unity open-circuit voltage gain.45 feedback whose amount is controlled by the setting of (e) For your design. find RF that will result in (g) Find the feedback amplifier’s input resistance Rin . Problems 905 Rout CHAPTER 11 Rs A1 A2 A3 Vo Vs R2 RL Rin PROBLEMS R1 Figure P11.45 Figure P11. resistance. (b) Show that if Aβ is large then the closed-loop voltage gain (b) If R1 = 20 k. (c) Supply the small-signal equivalent circuit. D *11. *** = very challenging. Q2 at 2 mA. (c) If RE is selected equal to 50 .44 Figure P11.32 shows a series–shunt feedback The feedback amplifier feeds a 1-k load resistance and is amplifier without details of the bias circuit. is the percentage change in Af ? = Multisim/PSpice. (h) Find the feedback amplifier’s output resistance Rout .2-k output circuit (supply a circuit diagram). (d) If Q1 is biased at 1 mA. A3 has a 20-k input resistance. * = difficult problem. the value of A. find the A1 has an 82-k differential input resistance. what is the upper 3-dB approximate values for RC1 and RC2 to obtain gains from frequency of the closed-loop gain? the stages of the A circuit as follows: a voltage gain of Q1 (j) If for some reason A1 drops to half its nominal value. A voltage signal Vs is applied between the realized? noninverting input (+In) and ground. and Q3 at 5 mA. a closed-loop gain of approximately 25 V/V. find the value of R2 that results in a is given approximately by closed-loop gain Vo /Vs that is ideally 5 V/V. sketch the A circuit and the circuit for determining β. (f) What is the output resistance of the feedback amplifier. and a 20-k output resistance. find dominated by a pole at 100 Hz. the β open-circuit differential voltage gain. what is the closed-loop voltage gain the wiper. (f) Find the closed-loop gain Af ≡ Vo /Vs . ** = more difficult. A2 has a 5-k input resistance.45 shows a three-stage feedback Specify the required setting of the potentiometer by amplifier: giving the values of R1 and R2 . (a) Eliminating the dc sources. and output amplifier formed by an op amp and a feedback resistance RF . Rid = 100 k. D = design problem . and (RM + RF ) = (b) 1 k. Show that gm2 RD A=− 1 + 1/[gm1 (RM + RF )] (c) For gm1 = gm2 = 4 mA/V.48(a) shows a feedback transresistance ductance Gm of 0. and an output resistance ro .48 VDD (a) Show that the feedback factor β. If RF (a) Find an expression for β and hence for the ideal value of Af ≡ Io /Is .47 transconductance amplifier having a short-circuit transcon- D 11.48(b).17(a).49 A series–series feedback amplifier employs a Figure P11.5: Other Feedback-Amplifier Types Assume that the op amp is modeled by an input resistance Rid .48 Figure P11.6. The feedback network consists of the highlighted two-port Is Vo network comprising RM and RF . P11. * = difficult problem. break the loop at the gate of Q2 and thus Vo determine the loop gain Aβ. Let μ = 1000. resistance of 100 k. Ii CHAPTER 11 and ro2 = 20 k. *** = very challenging. = Multisim/PSpice.46 Refer to the circuit in Fig.47 Figure P11. show that the loop gain is Q1 VG given by Rid RL Aβ = μ Rid + RF + ro Ii RF (c) For μ = 1000. Find RF that results in Af of approximately 1 k. determined as shown in Fig. is given by β = −1/RF . The feedback network has β = 200 .6 A/V. which is analyzed in Example 11. 11. (b) Setting Is = 0. Rid = 100 k. D 11. The feedback factor β is the current ratio If /Io measured with port 1 short-circuited (because it is connected in shunt (a) with the amplifier input). an open-circuit voltage gain μ. gm = 2 mA/V. Hence find RD the ideal value of the closed-loop gain Af ≡ Vo /Is . 906 Chapter 11 Feedback PROBLEMS Section 11. ** = more difficult. It is fed with the output current Io and delivers a feedback current If at its port 1 to the input node. ro = 1 k. Use If RF the formulas derived in Example 11. input resistance of 10 k. what is the actual value of Af If realized? Is RM 2 1 Feedback Transconductance Amplifiers (Series–Series) Rin 11. Select a value for RF that results in a closed-loop transconductance Af ≡ Io /Vs 10 mA/V. find the value of RM that results in a closed-loop current gain of 5 A/A. RD = 10 k. Q2 (b) By setting Is = 0 and breaking the loop at the input Io terminals of the op amp. Figure P11.47 shows a feedback current amplifier.6 to find the actual value of Af realized. D 11. and RF having the value found in (a). What is the percentage difference? input resistance. (Neglect the effect Rof of r03 .53 The transconductance amplifier in Fig. (1 + Aβ). 11. The differential amplifier drives a transistor What resistance can you change to make Af exactly Q characterized by its gm and ro . Problems 907 an input resistance (with port 1 open-circuited) of 200 . Since the current sampled by the feedback network (b) Find the A circuit and derive an expression for A. 11. hybrid-π model of the MOSFET and convince yourself [Note: If you continue with the feedback analysis. and in which direction (increase or decrease)? output current Io . * = difficult problem. select is (ro + Rs + gm ro Rs ). (b) Find an approximate value for Af ≡ Ve3 /Vs assuming that the loop gain remains large (a safe assumption.. find the output resistance Rout (measured Io between the emitter of Q3 and ground). gm = 2 mA/V. find Ro of the A circuit. The feedback and Rout . find the value of RF that results in a closed-loop transconductance of approx- Figure P11. which may be puzzling given that the feedback loop did not 11. For this purpose. β.51 Figure P11. (d) Assuming that ro3 = 20 k. recall that the resistance looking into the (a) For Aβ 1. is exactly equal to the output current. *** = very challenging. analysis will reveal that Aβ changes somewhat. (b) Sketch the A circuit and find the value of A ≡ Io /Vi . analyzed in change.53 (c) Find 1 + Aβ and Af ≡ Io /Vs . and Rof . analysis approach. All three MOSFETs are biased and sized to operate at gm = 4 mA/V. this time with the output voltage taken at the used. find an approximate expression for the drain of a MOSFET having a resistance Rs in its source closed-loop transconductance Af ≡ Io /Vs . ro = 20 k.3). 246. in which case (c) Give an expression for Aβ and evaluate its value and that the amplifier becomes series–shunt feedback.) D *11. = Multisim/PSpice.e.52 Consider the circuit in Fig. Rout1 . amplifier and not the feedback network.52 as a transconduc- tance amplifier with input Vs and output Io . P11. Ro . feedback formula. Hence.8. specified in terms of its gm and ro . what is of 1 + Aβ. PROBLEMS emitter of Q3 .52 imately 100 mA/V. You may neglect their ro ’s (except for the calculation of Rout1 as indicated below). Note amplifier operates with a signal source having a resistance that in this case RS2 should be considered part of the of 10 k and with a load resistance of 10 k. In this case the feedback can be considered (f) What is the closed-loop output resistance Rout2 of the to be of the series–shunt type. Vs RF (a) Considering the feedback amplifier as a transconductance amplifier with output current Io . since the (a) Sketch the small-signal equivalent circuit using the loop in fact does not change). you’ll that the feedback circuit is comprised of resistor RF . you can use the Evaluate A for the case μ = 1000 V/V. and the value of RF you selected in (a). Rin .21(a).] (c) If the loop gain remains at the value calculated in Example 11. and CHAPTER 11 the value of the closed-loop voltage gain Vo /Vs ? Assume an input resistance (with port 2 open-circuited) of 10 k. A resistor RF senses the 100 mA/V. Compare to the value of utilizes a differential amplifier with gain μ and a very high Af you designed for. this is a result (b) Find the A circuit and the β circuit. The transistor is (a) Determine β. The that RF has the original value you selected in (a).8 (i. of the different approximations made in the feedback (c) Derive expressions for A. D 11. P11. D = design problem . ** = more difficult.31 (page 851) shows a feedback triple utilizing MOSFETs.50 Reconsider the circuit in Fig. Af . Note that RE2 should now be voltage amplifier in (e) above? considered part of the basic amplifier and not of the feedback network. Find Af . (e) If the voltage Vo is taken as the output. find that Aβ in fact changes somewhat. The change is due to the different approximation Example 11. Hence find the output resistance a value for RF that results in Af 5 mA/V. ** = more difficult.] feedback network senses the emitter current of the BJT. in the gm Vπ generator. D = design problem . Rout RF m Figure P11. For the case of Rb = 0. To determine the output resistance. with Vx applied and Vs = 0. In this case.55(b).55(a). apply a test voltage Vx to 0 RF the collector.54 is given by RF rπ Ro = ro + Re rπ + Rb 1 + gm ro rπ + Rb (a) Rb Ro Ix Vs Re Vx m Figure P11. 908 Chapter 11 Feedback PROBLEMS (d) Find the closed-loop gain Af and compare to the value the base. whenever the resistance Rs in its source is (ro + Rs + gm ro Rs ). and in ro . P11. all in terms of Ix ? you designed for in (a) above.54 To derive this expression. hybrid-π model. To understand this Io issue more clearly.53 Vs *11.54 It is required to show that the output resistance of the BJT circuit in Fig. find the maximum possible value for Ro . P11. we set Vs = 0 and apply a test voltage Vx to the m Q collector. set Vs = 0.55 = Multisim/PSpice. * = difficult problem. Show these currents on a sketch of the equivalent circuit with (e) Find expressions and values for Ro and Rof . the feedback output resistance formula cannot predict the CHAPTER 11 output resistance looking into the collector. *** = very challenging. replace the BJT with 0V its small-signal. resistance looking into the drain of a MOSFET with a 11. Now.8. consider the feedback transconductance Rof amplifier shown in Fig. let μ be increased to the point where the feedback signal across RF almost equals Vs the input to the positive terminal of the differential amplifier. and find the current Ix drawn from Vx and hence Ro as Vx /Ix . Note that this theoretical maximum is obtained when Re is so (b) large that the signal current in the emitter is nearly zero. Note that the bias arrangement is not shown. [Hint: The Re set to ∞. as shown in Fig. P11. what is the current in Figure P11.55 As we found out in Example 11. Problems 909 CHAPTER 11 now zero. Thus the signal current through RF will be almost Io zero. By replacing the BJT with its hybrid-π model, show that Rout Rout = rπ + hfe + 1 ro hfe ro m Q where hfe is the transistor β. Thus for large amounts of R2 feedback, Rout is limited to a maximum of hfe ro independent Vs of the amount of feedback. This phenomenon does not occur PROBLEMS in the MOSFET version of this circuit, where the output R3 R1 resistance can be theoretically made infinite. 100 100 11.56 For the feedback transconductance amplifier of Fig. P11.56 derive expressions for A, β, Aβ, Af , Ro , and Rof . Evaluate Af and Rof for the case of gm1 = gm2 = 4 mA/V, Figure P11.57 RD = 20 k, ro2 = 20 k, RF = 100 , and RL = 1 k. For simplicity, neglect ro1 and take ro2 into account only when 11.58 All the MOS transistors in the feedback calculating output resistances. transconductance amplifier (series–series) of Fig. P11.58 are sized to operate at VOV = 0.2 V. For all transistors, Vt = 0.4 V and VA = 20 V. (a) If Vs has a zero dc component, find the dc voltage at the output, at the drain of Q1 , and at the drain of Q2 . RD (b) Find an approximate expression and value for Af ≡ Io /Vs for the case Aβ 1. Q2 (c) Use feedback analysis to obtain a more precise value Io for Af . Q1 (d) Find the value of Rout . RL Vi (e) If the voltage at the source of Q5 is taken as the output, Vs find the voltage gain using the value of Io /Vs obtained in (c). Also find the output resistance of this series–shunt voltage amplifier. Vf RF 11.59 By setting Vs = 0 and breaking the feedback loop, show that the loop gain of the amplifier circuit in Fig. P11.58 is Figure P11.56 RF ro5 Aβ = gm1,2 ro2 ro4 RF ro5 + 1/gm5 where gm 1,2 is the gm of each of Q1 and Q2 . D 11.57 For the feedback transconductance amplifier in Fig. P11.57, derive an approximate expression for the Feedback Transresistance closed-loop transconductance Af ≡ Io /Vs for the case of Aβ Amplifiers (Shunt–Shunt) 1. Hence select a value for R2 to obtain Af = 100 mA/V. If Q is biased to obtain gm = 1 mA/V, specify the value of 11.60 For the transresistance amplifier analyzed in Exam- the gain μ of the differential amplifier to obtain an amount ple 11.9, use the formulas derived there to evaluate Af , Rin , and of feedback of 60 dB. If Q has ro = 50 k, find the output Rout when μ is one-tenth the value used in the example. That is, 3 resistance Rout . [Hint: Recall that for a MOSFET with a evaluate for μ = 10 V/V, Rid = ∞, ro = 100 , RF = 10 k, resistance Rs in its source, the resistance looking into the drain and Rs = RL = 1 k. Compare to the corresponding values is (ro + Rs + gm ro Rs ).] obtained in Example 11.9. = Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem 910 Chapter 11 Feedback PROBLEMS Rout CHAPTER 11 Figure P11.58 11.61 Use the formulas derived in Example 11.9 to solve the (d) Find β and hence Aβ and 1 + Aβ. problem in Exercise 11.19. Show that the results are identical (e) Find Af , Ri f , and Rof and hence Rin and Rout . to those given in the answer to Exercise 11.19. (f) What voltage gain Vo /Vs is realized? How does this value compare to the ideal value obtained if the loop gain is 11.62 By setting Is = 0, replacing the MOSFET with its very large and thus the signal voltage at the base becomes hybrid-π model, and breaking the feedback loop, determine almost zero (like what happens in an inverting op-amp the loop gain of the feedback amplifier in Fig. E11.19. Hence circuit). Note that this single-transistor poor-man’s op find the open-loop gain. Evaluate Aβ, β, A, and Af for amp is not that bad! the numerical values given in Exercise 11.8. Why do the results differ somewhat from those given in the answer to Exercise 11.19? 15 V 11.63 The CE BJT amplifier in Fig. P11.63 employs shunt–shunt feedback: Feedback resistor RF senses the output RC 5.6 k voltage Vo and provides a feedback current to the base Rf 56 k node. Vo (a) If Vs has a zero dc component, find the dc collector current Rs 10 k of the BJT. Assume the transistor β = 100. (b) Find the small-signal equivalent circuit of the amplifier Rout with the signal source represented by its Norton equiva- Vs lent (as we usually do when the feedback connection at the input is shunt). R in (c) Find the A circuit and determine the value of A, Ri , and Ro . Figure P11.63 = Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem Problems 911 CHAPTER 11 D 11.64 The circuit in Fig. P11.64 utilizes a voltage (c) Provide the A circuit and derive an expression for A in amplifier with gain μ in a shunt–shunt feedback topology with terms of gm1 , ro1 , gm2 , ro2 , and RF . the feedback network composed of resistor RF . In order to be (d) What is β? Give an expression for the loop gain Aβ and able to use the feedback equations, you should first convert the amount of feedback (1 + Aβ). the signal source to its Norton representation. You will then (e) Derive an expression for Af . see that all the formulas derived in Example 11.9 apply here (f) Derive expressions for Ri , Rin , Ro , and Rout . as well. (g) Evaluate A, β, Aβ, Af , Ri , Ro , Rin , and Rout for the component values given. PROBLEMS (a) If the loop gain is very large, what approximate closed-loop voltage gain Vo /Vs is realized? If Rs = 2 k, give the value of RF that will result in Vo /Vs − 10 V/V. 3 (b) If the amplifier μ has a dc gain of 10 V/V, an input VDD resistance Rid = 100 k, and an output resistance ro = 2 k, find the actual Vo /Vs realized. Also find Rin and Rout (indicated on the circuit diagram). You may use formulas I derived in Example 11.9. (c) If the amplifier μ has an upper 3-dB frequency of 1 kHz Q2 and a uniform −20-dB/decade gain rolloff, what is the 3-dB frequency of the gain Vo /Vs ? Q1 Vo Is I Rout RF RF Rs Rin m Vo Figure P11.65 Vs Rout Rin 11.66 By setting Is = 0 and breaking the feedback loop, find the loop gain of the feedback amplifier in Fig. P11.65. Figure P11.64 If you have already solved Problem 11.65, compare results. Which result do you think is more accurate, and why? For the numerical values given in Problem 11.65, by how much (in percent) do the two values of loop gain differ? 11.65 The feedback transresistance amplifier in Fig. P11.65 utilizes two identical MOSFETs biased by ideal current sources I = 0.4 mA. The MOSFETs are sized to operate at 11.67 Analyze the circuit in Fig. E11.19 from first principles VOV = 0.2 V and have Vt = 0.5 V and VA = 16 V. The feedback (i.e., do not use the feedback approach) and hence show that resistance RF = 10 k. 1 Rs RF gm − ro RF (a) If Is has a zero dc component, find the dc voltage at the V RF Af ≡ o = − input, at the drain of Q1 , and at the output. Is 1 1 + Rs RF gm − ro RF /RF (b) Find gm and ro of Q1 and Q2 . RF = Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem 912 Chapter 11 Feedback PROBLEMS Comparing this expression to the one given in Exercise 11.19, VCC part (b), you will note that the only difference is that gm has RC been replaced by gm − 1/RF . Note that −1/RF represents the forward transmission in the feedback network, which the feedback-analysis method neglects. What is the condition then Q2 for the feedback-analysis method to be reasonably accurate Vo CHAPTER 11 for this circuit? Q1 D 11.68 For the feedback amplifier in Fig. P11.68, select Is RE a value for RF that results in a closed-loop gain Af ≡ Vo /Is −10 k. Then, analyze the circuit to determine –VEE Rout the actual value of Af realized. As well, determine Rin and RF Rout . Transistors Q1 and Q2 are operated so that gm1 = gm2 = 4 mA/V and ro1 and ro2 can be neglected. Also, Rin RD1 = RD2 = 10 k. Figure P11.69 VDD (b) Find the A circuit and the value of A, Ri , and Ro . Neglect RD1 RD2 ro1 and ro2 . (c) Find the value of β, the loop gain, and the amount of Vo feedback. Q2 (d) Find Af ≡ Vo /Is , the input resistance Rin , and the output resistance Rout . Q1 VG RF Rout D **11.70 (a) Show that for the circuit in Fig. P11.70(a), if the loop gain is large, the voltage gain Vo /Vs is given Is approximately by Vo Rf − Vs Rs Rin Figure P11.68 (b) Using three cascaded stages of the type shown in Fig. P11.70(b) to implement the amplifier μ, design a feedback amplifier with a voltage gain of approximately 11.69 For the feedback transresistance amplifier in –100 V/V. The amplifier is to operate between a source Fig. P11.69, let VCC = −VEE = 5 V, RC = RE = RF = 10 k. resistance Rs = 10 k and a load resistance RL = 1 k. The transistors have VBE = 0.7 V and β = 100. Calculate the actual value of Vo /Vs realized, the input (a) If Is has a zero dc component, show that Q1 and Q2 resistance (excluding Rs ), and the output resistance (excluding are operating at dc collector currents of approximately RL ). Assume that the BJTs have hfe of 100. [Note: In practice, 0.35 mA and 0.58 mA, respectively. What is the dc the three amplifier stages are not made identical, for stability voltage at the output? reasons.] = Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem The power supply VDD = 3. IR2. RD = 10 k. CHAPTER 11 Rin . The coupling capacitor CC can be assumed to be (a) input resistance is to be lowered and output resistance very large. Rin .3 V. = Multisim/PSpice. *** = very challenging.71 Negative feedback is to be used to modify the amplifier.7 k C2 Rin (b) Figure P11.72 consists of a (b) Find an expression for β and hence an expression for the common-gate amplifier formed by Q1 and RD . and gmf = 2 mA/V. * = difficult problem. ID2 = 1 mA.72 Figure P11. VA = 20 V. C2 = 0. P11. ID1 = 100 μA.73 shows a shunt–shunt feedback D 11.70 D *11. The MOSFETs have Vtn = 0. and Identify the feedback topology to be used if: RL = 2 k. R1 = 10 μA. and Rout for the case Vs RL in which gm1 = 5 mA/V. D = design problem . R1 .5 k 15 k Vo Q1 VBIAS Rout C1 10 k Is Qf 4. (a) Perform a dc design to meet the following specifications: (c) both input and output resistances are to be lowered. 2 μn Cox = 200 μA/V . and (W/L)2 . circuit formed by the capacitive divider (C1 . Specify the values required for I1 .2 V. raised. 11. Vo Also neglect ro . and a feedback ideal value of Vo /Vs . (b) both input and output resistances are to be raised.9 pF. VOV 1 = VOV 2 = 0. ** = more difficult. C1 = 0. Assume that C1 and C2 are sufficiently small that Rs their loading effect on the basic amplifier can be neglected. and characteristics of a particular amplifier for various purposes. R2 . Neglect the Early effect. It is required to derive expressions for Af ≡ Vo /Is . C2 ) and the (c) Find the value of Rs that results in Vo /Vs being ideally common-source transistor Qf . Problems 913 Rf is not shown. Voltage amplifier PROBLEMS (a) VDD 15 V RD 7.73 Figure P11. Note that the bias circuit for Qf −6 V/V. Find the values of Af .72 The feedback amplifier of Fig. and Rout . (W/L)1 .6 V.1 pF. Let Feedback Current Amplifiers (Shunt–Series) Rs = Rid = ∞. RD = 20 k. and Ro .2 mA. 914 Chapter 11 Feedback PROBLEMS VDD I1 Q2 CHAPTER 11 Q1 CC Rs R2 Vo Vs R1 RL Rout Rin Figure P11. D 11.10? (b) Provide the β circuit and an expression for β. *** = very challenging. P11. Evaluate Aβ for the component values given in Example (a) Provide the A circuit and derive expressions for Ri and A.77 The feedback current amplifier in Fig. P11.10). Ri . (ii) amount of feedback 40 dB (c) Find the A circuit and the value of Ri . (a) If Is has zero dc component. and μ. R2 . A. and 11.27(a) (which was analyzed in Example 11. Why do the results differ Neglect ro of both transistors. (iii) Rin 1 k (d) Find the value of β. 11. and Ro .10 and hence determine A and Af . * = difficult problem. Af . and VA = 10 V.27(a) to meet the following specifications: operating at ID = 0.47: Aβ.77 utilizes RF = 90 k. MOSFET. find an expression for the loop gain 11. What is the dc voltage at the input? (i) Af ≡ Io /Is = −100 A/A (b) Find gm and ro for each of Q1 and Q2 . and Ri f . find the output resistance they operate at VOV = 0. μ has infinite input resistance and that Rs = ∞. By setting Is = 0 and breaking the feedback loop at the gate of Q. 11. two identical NMOS transistors sized so that at ID = 0.2 V.76 Consider the feedback current amplifier in Fig.5 V as seen by RL .2 mA (e) If ro2 = 20 k and RL = 1 k. D = design problem . obtained? (e) Find the value obtained for Vo /Vs . Assume that the amplifier (e) Find Aβ and Af . (f) Find Rin and Rout . show that both Q1 and Q2 are 11. For the (f) Find Rin and Rout . 11. What Rout is Ri . find the values of A. β. (d) For gm1 = gm2 = 5 mA/V.75 Design the feedback current amplifier of Fig. Specify the values of R1 . ** = more difficult. RM = 10 k. somewhat from those found in Example 11. Both devices have Vt = 0. Aβ.73 (d) Find the A circuit and use it to determine the values of A. gm = 5 mA/V and ro = 20 k. (c) Find an expression for Aβ.74 For the feedback current amplifier in Fig. = Multisim/PSpice. 77 Io Rout *11. an amplifier of gain +μ is connected between the drain and the gate. an amplifier is placed between source and gate. (f) The “super” CG transistor can be utilized in the cascode configuration shown in Fig. Problems 915 CHAPTER 11 Io Io I 0.78(a) can VG Q2 be thought of as a “super” CG transistor. The feedback loop ensures that the value of the gate-to-source voltage of Q1 is such that Io1 equals is n times W/L of Q1 . This current tracking. (c) What is the value of β? Figure P11. D = design problem .79 Figure P11. find the A circuit and derive (b) expressions for A. = Multisim/PSpice. P11. Note that rather than connecting the gate of Q2 to signal ground. Note that the feedback loop does not Figure P11. Is . as is the case in simple current mirrors. Rather than connecting VBIAS the drain of Q1 to the gate.78 The feedback current amplifier in Fig. Thus.5 k (a) Rin Figure P11.79 include transistor Q2 . what is the value of Af ? (e) Find Rin and Rout assuming the loop gain is large.79 shows an interesting and very useful application of feedback to improve the performance of the m Q1 Q2 current mirror formed by Q1 and Q2 . Replacing Q1 by its small-signal model. * = difficult problem.78(a) to find Io and Rout . (a) If μ is very large.2 mA Rout Rout m Q2 Q2 Q1 PROBLEMS Is Rs R2 Rin Is 14 k R1 3. what is the signal voltage at the input Vi Q1 terminal? What is the input resistance? What is the current gain Io /Is ? (b) For finite μ but assuming that the input resistance of the amplifier μ is very large. ** = more difficult. Io2 = nIo1 = nIs . If μ is large. and Ro . if W/L of Q2 however. Io1 Io2 *11. is not regulated by the feedback loop. *** = very challenging.78(b). where VG is a dc Is bias voltage. This regulated Vgs is also applied to Q2 . P11. use Rin Rout the analogy of the resulting circuit to that in Fig. Ri .78 (d) Find Aβ and Af . P11. 80 parameters. (c) Replacing Q1 by its small-signal model. *** = very challenging. and z is connected to ground.80 The circuit in Fig. Also. Neglect ro except in (f). (d) What is the output resistance Rout ? (c) What is the output resistance at z? *11. Use feedback analysis to find Vo /Vs and amplifier consisting of the differential amplifier μ and the Rin . assum- particular circuit building block known as second-generation ing that Vs has a zero dc component. a (b) If μ is very large and the input resistance of the amplifier voltage signal Vx is connected between x and ground. ** = more difficult.81 **11. P11. find an expres. It has three terminals besides all nodes and the dc emitter currents of Q1 and Q2 . Note that here it is much easier to do the analysis by Iy ? What is the current Iz that flows through the output directly than to use the feedback-analysis approach. D = design problem . Let the ground: x.80 is an implementation of a *11.82 Figure P11.81. (Note that this feedback circuit is one we have encountered a number of times in this chapter.81 For the amplifier circuit in Fig. 916 Chapter 11 Feedback PROBLEMS (a) Show that the feedback is negative. All transistors have β = 100 and VBE = 0. let the two current mirrors have unity current-transfer ratios. (b) If x is connected to ground. explain the current flow through the large μ. Let VBE = 0. μA Vo Q1 Q2 QN x y m z Rin QP Figure P11. what short circuit.2 V. and z. P11. assume that the differential amplifier has a very large gain μ and infinite differential input resistance.7 V.7 V. = Multisim/PSpice. find the dc voltages at current convoyer (CCII). QP ). albeit with only one source-follower 15 transistor. what finite gain but infinite input resistance for the amplifier voltage appears at y and what is the input resistance seen μ. (a) If a resistance R is connected between y and ground. For short circuit? Also.82 shows a feedback amplifier utilizing Q3 Q4 the shunt–series topology. Find the current Iz through the If Q1 is to operate at an overdrive voltage of 0. (a) Perform a dc analysis to find the dc emitter currents in Q1 and Q2 and hence determine their small-signal Figure P11. complementary source follower (QN .) In the following. and z μ is infinite. * = difficult problem. what dc voltage appears at the drain of Q1 ? is short-circuited to ground. what does Rin become? circuit for Iy positive and for Iy negative. a current source Iy is connected CHAPTER 11 sion for the small-signal input resistance Rin assuming to input terminal y. Show how this current is developed and its is the minimum value that VBIAS must have? path for Vx positive and for Vx negative. y. The heart of the circuit is the feedback BJTs have β = 100. 82 4 (b) Replacing the BJTs with their hybrid-π models.86 Consider a feedback amplifier for which the open-loop (e) Find Aβ. Section 11. Find the low-frequency gain.) expression for Af (s). (Plot for ω = 0 rad/s. give the 11. 11.4 k 870 Rin Rout Rf 10 k Figure P11.7: The Stability Problem Section 11. 10 rad/s. Af . where β is the BJT’s β (see frequency at which the phase shift is 180°.55).88 An amplifier has dc open-loop gain of 80 dB and a frequencies? single pole with 100-Hz frequency. a pair of additional poles at 20. 10. *** = very challenging. unstable. By what factor does the pole shift? What is the corresponding value of closed-loop gain at low 11.84 For the situation described in Problem 11. 1 + Aβ. Note that Rof represents gain A(s) is given by the resistance that in effect appears in the emitter of Q2 as a result of the feedback. 10 rad/s.83 An op amp designed to have a low-frequency gain 5 of 10 and a high-frequency response dominated by a 11. 000 A(s) = 2 (f) Determine Rin .83. (d) Find the β circuit and determine the value of β. assumed to be frequency frequency. = Multisim/PSpice. and the unity-gain frequency of the closed-loop independent. sketch feedback amplifier with a 3-dB frequency of 10 kHz. To determine Rout . for what value of β. Ri .87 A dc amplifier having a single-pole response with single pole at 100 rad/s acquires. D = design problem . ** = more difficult. and Rof . and find the critical Problem 11. and a single-pole rolloff at 10 rad/s is connected in a (c) Give the A circuit and determine A. does the loop gain reach a value of unity? amplifier. At what is operated in a loop whose frequency-independent feed- frequency does the total phase shift reach 180°? At this back factor is 0. use 1 + s/104 1 + s/105 VA2 = 75 V and recall that the maximum possible output resistance looking into the collector of a BJT If the feedback factor β is independent of frequency. 100 is needed? What is the dc closed-loop gain realized? Give an 3 4 4 rad/s. the 3-dB frequency. Ri f . Problems 917 12 V CHAPTER 11 RC2 8k Iout RC 1 10 k RB 1 100 k Q2 Rs 10 k Q1 RL 1k Iin RE 2 PROBLEMS Vs RB 2 15 k 3. * = difficult problem.8: Effect of Feedback on the Amplifier Poles 11. value of β at which oscillation will commence. Note that negative-feedback loop via a feedback network having a 3 Ro is the resistance determined by breaking the emitter transmission k and a two-pole rolloff at 10 rad/s.000 rad/s. and Ro . through a manufacturing pole frequency 10 Hz and unity-gain frequency of 1 MHz error. find the is approximately βro . and ∞ rad/s. and Rout .0 and 10 . Find the loop of Q2 and measuring the resistance between the value of k above which the closed-loop amplifier becomes terminals thus created. Iout /Iin .1. It is utilized to design a *11. What β −3 Nyquist plots for β = 1.85 An op amp having a low-frequency gain of 10 3 equivalent circuit of the feedback amplifier. 2 × 10 rad/s. 92 A feedback amplifier having a dc closed-loop gain of 10 and a maximally flat second-order response with Section 11.100 A multipole amplifier having a first pole at 1 MHz each having a single-pole frequency response.37 and with factor.101 For the amplifier described in Problem 11. what are the new pole locations? What is the corresponding pole Q? 11.1 dB? Of 1 dB? Of 3 dB? [Hint: D 11.98 A two-pole amplifier for which A0 = 10 and having closed-loop amplifier? poles at 1 MHz and 10 MHz is to be connected as a differentiator. modified to incorporate a so-called tapered is stable? What are the corresponding gain and phase network. What is the minimum value of K at is formed to reduce the frequency of the first pole. Give an expression new dominant pole.9: Stability Study Using Bode 4 5 and poles at 10 Hz and 10 Hz is operated in a closed Plots negative-feedback loop with a frequency-independent β. what is 11. 918 Chapter 11 Feedback PROBLEMS 4 *11. what is the minimum value of K does the response become maximally flat? For closed-loop voltage gain that can be obtained for phase what value of K does the circuit oscillate? margins of 90° and 45°? D 11. and the dc gain closed-loop gains as low as unity by the introduction of a of each of the two amplifier stages. in which the components immediately adjacent to margins? the amplifier input are raised in impedance to C/10 and 10R.89 An amplifier having a low-frequency gain of 10 Section 11. placed? 11.95 Reconsider Exercise 11. whose location can be controlled. At what frequency must the new pole be for Af (s). D 11.90 A dc amplifier has an open-loop gain of 1000 and Use the result in Eq.34. for which a phase margin closed-loop gain of 10 and a maximally flat response. What is the 3-dB frequency of the 11. 11.100.93 Three identical inverting amplifier stages.94 Reconsider Exercise 11. (11.97 An amplifier has a dc gain of 10 and poles at 10 Hz. At what frequency is |Aβ| = 1? coincident? At what frequency? What is the corresponding phase margin? (b) What is the low-frequency. Find expressions for the resulting pole frequency ω0 and Q 11.26 for the case of a manufac- ing to the situation in (a)? What is the value of the 3 turing error introducing a second pole at 10 Hz. The open-loop amplifier utilizes a cascade of two identical amplifier stages. For what value of K do the poles coincide? For what frequency-independent feedback.99 For the amplifier described by Fig.16 × 10 Hz.91 Reconsider Example 11.] two poles.11 with the circuit in the smallest differentiator time constant for which operation Fig. It is required to connect 5 6 3. *** = very challenging. a dominant one at 1 kHz and a high-frequency one 4 5 11. D 11.96 For what phase margin does the gain peaking have a value of 5%? Of 10%? Of 0. are connected in a feedback additional capacitance at the circuit node at which the pole loop with β = 1.82). the 3-dB frequency. * = difficult problem.26 for the case of the op amp (a) For what value of β do the closed-loop poles become wired as a unity-gain buffer. and the this amplifier in a negative-feedback loop that provides a dc corresponding closed-loop gain.10: Frequency Compensation a 3-dB frequency of 1 kHz is required. the required value of β and the frequency at which the second 3 pole should be placed. Find of 45° is obtained. On the basis of the rate-of-closure rule. If the which the circuit oscillates? What would the frequency of frequency of the second pole is 20 MHz and if it remains oscillation be? unchanged while additional capacitance is introduced as = Multisim/PSpice. closed-loop gain correspond- CHAPTER 11 11. 11. ** = more difficult. each char. Find the value of β. 11. What is now closed-loop gain at the frequency of the coincident poles? the frequency for which |Aβ| = 1? What is the corresponding (c) What is the value of Q corresponding to the situation in phase margin? For what values of β is the phase margin 45° (a)? or more? (d) If β is increased by a factor of 10. Find the and a dc open-loop gain of 80 dB is to be compensated for values required for β. D = design problem . acterized by a low-frequency gain K and a single-pole rather than introducing a new dominant pole we can use response with f3dB = 100 kHz. and 10 Hz. to what value must the first pole frequency be has an open-loop gain of 10 and a single-pole rolloff with lowered to obtain stable performance for (a) β = 0. * = difficult problem. (11. Find the required value of the compensating controlling node increased? Miller capacitance and the new frequency of the output pole. 11.102 For the amplifier whose A(s) is depicted in **11. 11. Comment on the results.001 and ω 3dB = 10 rad/s. and gm = 40 mA/V.38.94) under the conditions corresponding phase margin.93). and find the ering Eqs. Assume that the op amp incorporates an amplifier equivalent to that in Fig. ωP2 . Figure P11. What is the frequency of the required dominant pole? The compensation network is to consist of an RC low-pass network placed in the negative-feedback path of the op amp.40. and (11. C2 C1 /10 = C.89). Sketch the magnitude 5 D 11. 10 Hz. ωP2 .105 An op amp with an open-loop voltage gain of 5 6 6 80 dB and poles at 10 Hz. and ωP1 . Cf C.106 The op amp in the circuit of Fig. 11. and poles. 10 Hz. What capacitor is required between the negative input and ground to implement the required fourth pole? D *11. D = design problem .1? (a) Sketch a Bode plot for the loop gain. find the frequency to which the first pole must be lowered so that the resulting amplifier is stable for closed-loop fP1 is caused by the input circuit and fP2 by the output circuit gains as low as unity. PROBLEMS (b) β = 0. including its zero by calculating ωP1 . P11. Sketch a pole-zero plot. C2 = 5 pF.103 Contemplate the effects of pole splitting by consid- (b) Find the frequency at which |Aβ| = 1. and 10 Hz is to be compensated by important parameters on your sketch. The dc bias conditions are such that a 1-M resistor can be tolerated in series with each of the negative and positive input terminals. 11. ** = more difficult.106 5 Fig. and 2 × 10 Hz is to be compensated to be stable for unity β. that R1 R2 = R. By what factor is the capacitance at the of this amplifier. Problems 919 with C1 = 150 pF. *** = very challenging.106 = Multisim/PSpice. and label the 6 7 8 poles at 10 Hz.104 An op amp with open-loop voltage gain of 10 and of the transfer function versus frequency. and that CHAPTER 11 mentioned. (c) Find the closed-loop transfer function. and gm = 100/R. the addition of a fourth dominant pole to operate stably with unity feedback (β = 1). (11. 3 V.5 V and μCox W/L = 2 mA/V .2.6 Consider the situation described in Problem 12. Instructions to assist in setting up PSpice in Q1 in each case? Compare these results to those for sine and Multisim simulations for all the indicated problems can waves of peak amplitude VCC and VCC /2.7 Reconsider the situation described in Exercise 12. you are to make a reasonable assumption. 10 V.1 A class A emitter follower. R = RL = 1 k.5. 12. ** = more difficult. and Section 12.4 to verify hand analysis and design. and to investigate for v O . square-wave outputs having ±VCC levels and ± 21 VCC levels. VCC = 2. P12. D 12. uses VCC = 10 V. VBE = 0. * = difficult problem. Assume VCE sat is nearly zero.2 for which RL = VCC /I. for which the output voltage range is ±5 V. R = RL = 1 k. with a 100- period does the crossover interval represent? For what value load. For linear operation. 12. Assume VBE = 0.8 The emitter-follower output stage of Fig.2. Note that if a particular parameter value is not specified in the problem 12. iC 1 . 12. 12. 12. shown in Fig. What is the what are the upper and lower limits of output voltage. For what amplitude of input signal does the with ± 5-V supplies. sketch the equivalent of Fig. Neglecting the saturation voltage. You are provided with four identical. The circuit is to be designed such that the current MOSFETs. What is the average power dissipation nonlinear distortion.3 Using the follower configuration shown in Fig. respectively.2. With a 10-kHz sine-wave a factor of 15.3: Class B Output Stage the corresponding inputs? 12.7 V. VCE sat = 0. and specify the maximum power drawn V/V. and for sine waves of the same peak-to-peak values. if the constructed following the pattern shown in Fig. and pD 1 . and –5 V.11 Consider the class B output stage.11. 0.5 V. 12. and compare it with that without feedback. Let the devices have Vt = 2 variation in the emitter-follower transistor is no greater than 0. with Vt = 0. Select a standard resistor output stage shown in Fig. and 8 V. assuming that 100 from the negative supply. what the value of R required? Find the incremental voltage gain of peak output would you expect? What fraction of the sine-wave the resulting follower at v O = +5.3 all transistors (including Q3 ) identical. high-β 12.2 output stage. All three output voltage is a sine wave of peak amplitude (V̂ /2). 12. for variation in VCC —specifically for VCC = 16 V. PROBLEMS Computer Simulation Problems *12. be found in the corresponding files on the website. For this situation. *** = very challenging. using VCC = 10 V.2 is of Q2 ? Half as big? designed to provide a maximum output swing of ±V̂ volts.2: Class A Output Stage average power loss in the current-source transistor Q2 . what transistors used are identical.2 A source-follower circuit using NMOS transistors is are the minimum required values of VCC and I? Now. Derive an expression for v O versus v I . what 12. Repeat for a square-wave output that has important issues such as allowable signal swing and amplifier peak levels of ±VCC /2. when driven by a square wave Problems identified by the Multisim/PSpice icon are such that the output ranges from +VCC to −VCC (ignoring intended to demonstrate the value of using SPICE simulation VCE sat ). with 12. For linear operation. For statement. Sketch the transfer characteristic v O versus v I .5 V and μn Cox W/L = is the power-conversion efficiency realized? 2 20 mA/V . Let the amplifier gain A0 = value of 5% tolerance. What is input of 5-V peak and a high value of load resistance. provide a design capable of ±3-V crossover distortion represent a 10% loss in peak amplitude? outputs with a 1-k load. what are the upper and lower limits of the output voltage. 12 V. D = design problem . 12. is required using 12.4 An emitter follower using the circuit of Fig. across the load RL . and β to be very large. find the Section 12.5 Consider the operation of the follower circuit of Fig.7 V. biased using the circuit shown in Fig.9 Consider the circuit of a complementary-BJT class B D 12.9.10 Consider the feedback configuration with a class B BJTs and a resistor of your choice. for load resistances as low as 100 . and power-conversion efficiency in each case? the corresponding inputs? How do these values change if the emitter–base junction area of Q3 is made twice as big as that D 12. What is the percentage change in gain over this range of load resistor is the peak output voltage reduced to half the of v O ? input? = Multisim/PSpice. 12. using the smallest possible total supply current. What does the incremental gain efficiency? For output signals of half this amplitude.5 as a function of vI . *** = very challenging. for vI both ⫺5 V positive and negative. 12. dissipation.11. * = difficult problem. For utilizing transistors with IS = 10 A. find the become when vO = 10 V? output power. what is the smallest 12.20 For the class AB output stage considered in Exam- load permitted? What is the greatest possible output power ple 12. the maximum attainable power-conversion efficiency and the corresponding value of V̂o . Rin βRL . 984 Chapter 12 Output Stages and Power Amplifiers PROBLEMS ⫹5 V RL and employing power supplies ±VSS . As a measure of nonlinearity. ** = more difficult. should be 4 V greater than the corresponding peak sine-wave output voltage. Com- D 12. such as that in Fig. serve to limit the variation in the small-signal voltage gain to if operation is always at full output voltage? If operation is 5% as iL changes from 0 to 50 mA? allowed at half the full output voltage. output stage so that the incremental voltage gain for v I in D 12. 12. is biased at a quiescent ±10-V power supplies and an 8- load resistance. Assume that the BJTs have VBE of 0.17 A class AB output stage. and the corresponding value of power-conversion efficiency. and a factor-of-2 safety margin is to be used. Assuming relatively ideal transistors. which occurs at v O = 0. 12. Assume βN = βP = β = 49.21 In this problem we investigate an important trade-off (to the nearest volt in the appropriate direction).11. what current IQ = 1 mA.18 Design the quiescent current of a class AB BJT efficiency. 12.19 A class AB output stage. we use the maximum deviation of the stage incremental gain. the output resistance Rout at is the maximum sine-wave output power available? What vI = 0. Determine the power-supply voltage required 12.7 V at output voltage for maximum power-conversion efficiency? a current of 100 mA and determine the value of VBB required. determine the maximum of the transfer characteristic at the expense of increased possible power dissipation in each transistor for a sine-wave quiescent power dissipation.15 Consider the class B BJT output stage with a square-wave output voltage of amplitude V̂o across a load e = 1 − v o /v i v =0 O = Multisim/PSpice. the supply power. What is the output voltage for maximum device dissipation? If each of the output devices is individually rated for 2-W D 12. Also. the power-conversion efficiency.12 Consider the complementary-BJT class B output 12.11 Section 12. what is the larger than 100 . Figure P12. 12.11: current from each supply. determine the load power. D = design problem . and the maximum available load power.3. such as that in Fig.16 Sketch a graph for the small-signal voltage gain of the class B circuit of Fig.14 A class B output stage is required to deliver an pare the values of Rin to the approximate value obtained using average power of 50 W into an 8- load. and the Increasing the quiescent current IQ reduces the nonlinearity power-conversion efficiency. what drives a load resistance RL of 100 . Also find the value of V̂o at which the power dissipation in the CHAPTER 12 transistors reaches its peak. The supply power corresponds? What is the power-conversion load resistance RL = 100 .97 V/V for loads supplies. What bias current IQ will is the smallest value of load resistance that can be tolerated. and the power-conversion D 12. and the corresponding small-signal voltage gain. the supply power. 12. Find VBB . −14 stage and neglect the effects of finite VBE and VCE sat .13 A class B output stage operates from ±10-V the vicinity of the origin is in excess of 0. and the large-signal input resistance Rin ≡ v I /iI . namely. mA). input.4: Class AB Output Stage 12. Neglecting the effects of finite VBE and VCE sat . the peak in the design of the class AB output stage of Fig. add two columns to the table of results as follows: the available in each case? total input current drawn from v I ( iI . The power supply the resistance-reflection rule. the total supply power. and hence e VT /2IQ RL re = reN reP and β = (gmN + gmP )(rπ N rπ P ). find PROBLEMS the quiescent power dissipation. PD . the product of the vi RL + (reN reP ) quiescent power dissipation and the gain error is a constant given by and . to an emitter-follower transistor whose rπ = rπ N rπ P and gm = gmN + gmP . Problems 985 (a) Show that e is given by CHAPTER 12 output stage in Fig. Hence show that the class AB stage is equivalent. which for 2IQ RL VT can be approximated by from a small-signal point of view.14. 12. To simplify matters. assume the VT /2IQ small-signal resistances of D1 and D2 to be negligibly small. e= Replace each of QN and QP with its hybrid-π model and RL + VT /2IQ neglect ro . vo RL = (c) Show that for given VCC and RL . Now show that (b) If the stage is operated from power supplies of ±VCC . P12. *** = very challenging.5: Biasing the Class AB Circuit QN D 12. * = difficult problem.26 shows a class AB output stage with a common-emitter transistor added to increase the voltage gain *12.14.25 It is required to evaluate the small-signal input Toward that end. 12. For IBIAS = 200 μA. 2%.27 It is required to find an expression for the output if β N is held at 50? For this value. For IBIAS = 1 mA. resembling that in and reduce the current that vI has to supply. neglect the small-signal resistance of each of resistance and small-signal voltage gain of the class AB D1 and D2 and assume the current source supplying IBIAS has an = Multisim/PSpice.11 but utilizing a single supply of +10 V and biased small-signal resistances of D1 and D2 . (Hint: Use the expressions for voltage gain coupled to a 100- load. VCC ePD VT Rin β[RL + (reN reP )] RL (d) For VCC = 10 V and RL = 100 . is capacitively voltage gain vo /vi .7 V at 1 mA and for a bias and input resistance of the class AB stage without Q3 . D = design problem . ** = more difficult.26 output level equal to the negative peak level.22 A class AB output stage. 12. β N = 50. IBIAS Section 12. VCC = 10 V.) step change in output from 0 to –1 V. what quiescent current results? For a in the statement for Problem 12.23 Consider the diode-biased class AB circuit of Fig. find the required values of PD and IQ if e is to be 5%.25.26. find the small-signal at VI = 6 V.24 A class AB output stage using a two-diode bias vI Q3 network as shown in Fig. and VCEsat = 0 V. what input step is required? Assuming transistor-saturation voltages of zero.4 V. find the relative size (n) that D1 should be used for the output devices (in comparison to the vO biasing devices) to ensure that an output resistance of 8 or D2 RL less is obtained in the quiescent state.14 utilizes diodes having the same junction area as the output transistors. what does IQ become? resistance Rout of the class AB output stage in Fig. given voltage VBB = 1. RL = 100 . what value of β N is needed if IBIAS is not changed? What value of IBIAS is needed 12. Neglect the resistance of the biasing diodes. and 1%. QP D*12. Neglecting the Fig.26 Figure P12. For transistors for which VBE = 0. D 12. 12. ⫹VCC find the largest possible positive-going and negative-going steps at the output. 12. what is ⫺VCC the quiescent current? What are the largest possible positive and negative output signal levels? To achieve a positive peak Figure P12. 14 utilizes diodes having the CHAPTER 12 same junction area as the output transistors. Transistors QN and QP are equivalent R2 + (R1 rπ ) to a single transistor with rπ = rπ N rπ P .32 Use the results given in the answer to Exercise 12. you may assume Rout = R + re3 + R1 re1 / β3 + 1 2 3 that β N remains almost constant. For an input for nominal operation at a terminal current of 1 mA. Assume that all four transistors are matched and current increases to 2 mA. the output devices heat up to 70°C while the v I = 0 and ±10 V with infinite and 100- loads. find the quiescent current in Q3 and Q4 .35 shows a variant of the class AB circuit (b) Find the terminal voltage that results when the terminal of Fig. and r= 1 + gm (R1 rπ ) gm = gmN + gmP . is ±20 V.9 diode-connected transistors is omitted.4 ≥ 50. 12. Through a manufacturing error.17. of 10 mA. the multiplier is given by input resistance found is 2Rin .5 for the situation in which the in Q3 (and Q4 ) at v I = +5 V (vI = −5 V). while the VBE of each device remains unchanged.34 Consider the circuit of Fig.35 Figure P12. The quiescent current in Q3 is to be 40 mA. 12. The initial design is voltage results? Q1 and Q2 have VBE of 0. (d) Repeat (c) using the more realistic value of β = 100. (c) Repeat (b) for the case the terminal current becomes (a) For v I = 0.17. with half voltage of +1 V and a load resistance of 2 . small-signal model (with ro neglected). (b) Since the circuit has perfect symmetry. For VCC = 10 V. Thus. have β = 100. fed with a signal source having zero resistance. What are the values of R1 and R2 Q1 (and Q2 ). the small-signal *12. and the temperature of the output transistors D ***12. 12. you have chosen? Let β1.31 By replacing the transistor in the VBE multiplier by its performance around v I = 0 can be determined by con- hybrid-π.6 V. re = reN reP . 986 Chapter 12 Output Stages and Power Amplifiers PROBLEMS output resistance RBIAS . Resistors R3 and increase result? R4 also are matched. * = difficult problem. where T = 273° + temperature in 1 °C.28 A class AB output stage using a two-diode bias operating at IC = 1 mA and having β = 100.17 for activity. network as shown in Fig. show that the recall that there are two effects: IS increases by about 14%/°C output resistance is given by and VT = kT /q changes. Use the same general demands it. This assumption is based on the fact that β increases with temperature but decreases with Assume that the top and bottom halves of the circuit are current. 12. D = design problem . and the output voltage v O . find values for resistors R1 through R4 that allow for a base current of at least 10 mA D 12. 12.6: Variations on the Class AB temperature of about 20°C the quiescent current is 1 mA and Configuration VBE = 0. input current iI . ** = more difficult. show that sidering either the top or bottom half of the circuit only.7 V at 1 mA. what output the current flowing in the bias network. For input voltages around 0 V. the incremental resistance between the two terminals of the In this case. and VT = 25 mV only at 20°C. However. what additional power is dissipated? If thermal runaway occurs. Evaluate r for the case R1 = R2 = 1. and Q3 and Q4 are matched but have dissipation. operated near v I = 0 and output devices increases.33 For the circuit in Fig 12. when a load peak positive output current is 250 mA. the 10 mA.17 in which Q1 increases by 10°C for every watt of additional power and Q2 are matched. with the transistor **12. biasing devices remain at 20°C.30 A VBE multiplier is designed with equal resistances driven by a source having zero resistance. (a) Find the required resistor values and the terminal voltage.29 Repeat Example 12.7 V at a current based on β = ∞ and VBE = 0. and the output resistance = Multisim/PSpice. What is the new value of IQ ? If the power supply perfectly matched.2 k. After some output to determine the input current of the circuit in Fig. the quiescent current in the 12. with at most a 2-to-1 variation in currents in approach to safety margins. At a room Section 12. estimate the output resistance of the overall follower **12.2 ≥ 150 and β3. *** = very challenging. Assume β = ∞. To calculate the new current value. the thermal coupling between the output transistors and the biasing 12. what additional temperature rise and current three times the junction area of the others. the load on the half-circuit must be 2RL . P12. (d) The composite transistor has an equivalent rπ 2β1 β2 VT /IC .38 have β P = 10. β N = 100. (b) If the composite transistor is operated at a current IC . where IS is the saturation current of each of Q1 and Q2 . (a) The equivalent composite transistor has β β1 β2 . (c) The composite transistor has a base–emitter voltage VBE 2VT ln IC /IS − VT ln β2 . *12.37 in which the transistors have VBE = 0. (e) The composite transistor has an equivalent gm 1 2 C I /VT . Using this approach. * = difficult problem. Figure P12. vo gm1 ro1 β N (ro2 Rf ) show that for β1 1 and β2 1: vi (c) Find the values of v o /v i and Rin . Problems 987 found is 2Rout . ⫹5 V ⫹VCC PROBLEMS 1 mA 2 k⍀ ⬁ Q3 2 M⍀ vo ⬁ Q1 vi Q1 ic iI ⫺VCC vI vO ⫹VCC Q2 RL ⫽ 200 ⍀ Q2 Rin Q4 Figure P12. and Q1 will be operating at a collector current approximately equal to IC /β2 .36 For the Darlington configuration shown in Fig. (b) Replacing each BJT with its hybrid-π model.18. v o /v i . and CHAPTER 12 (b) Find the small-signal current ic that results from an input Rout (assuming that the circuit is fed with a zero-resistance signal v i . D = design problem . *** = very challenging. and VA = 100 V.37 For the circuit in Fig. find Rin .37 1 mA **12. (c) Find the input resistance Rin . VBE = 0. 12. show that 12.38 The BJTs in the circuit of Fig. ** = more difficult.7 V.35 value of VC .38 = Multisim/PSpice. source).7 V and β = 100: (a) Find the dc collector current for each of Q1 and Q2 . and hence find the voltage gain v o /v i . then Q2 will be operating at a collector current approximately equal to IC . ⫺VCC (a) Find the dc collector current of each transistor and the Figure P12. P12. Here. For vI positive and exceeding a certain threshold. 12. Figure P12. Let VCC1 = 35 V.40 shows a variant on the class AB transistors. all other IBIAS conditions remaining the same.39 Consider the compound-transistor class AB out. Q1 and Q5 happens in the negative direction. Q3 is turned off and D1 turns on. VCC2 12. for a quiescent current of 2 mA in Q2 and Q4 .40 Figure P12.2 V. with D2 and Q4 taking the have VBE = 0. D = design problem .41 Repeat Exercise 12.11 for a design variation in which transistor Q5 is increased in size by a factor of 20.3 V.7 V at 1-mA currents and β = 100. PD . Z1 D 12. respectively. and Q1 is then effectively operating from the higher voltage supply VCC2 . is nine times that in the associated resistors.19) to estimate the average power dissipated in the *12. use Eq.11 for a design in which the Q3 limiting output current and normal peak current are 100 mA VCC1 and 75 mA. (12. VZ1 = 3. 988 Chapter 12 Output Stages and Power Amplifiers PROBLEMS D **12.43 The circuit shown in Fig. 12.7 V at 10 mA and β = 100. D1 and D2 are turned on and thus connect the ±VCC1 supply to the class AB stage transistors Q1 and Q2 . in addition to the a class AB stage operated from a ±70 V supply. As vI decreases below It has the advantage that the current-sensing resistor R does = Multisim/PSpice.21 to limit the output Q1 R2 Q5 vO R1 RL vI Q2 Z2 D2 –VCC1 Q4 IBIAS IBIAS ⫺VCC2 Figure P12. a 1-k load.20 in which Q2 and Q4 are matched connecting Q1 to its normal supply VCC1 . The circuit operates as follows. Find the values (b) If for 95% of the time vI is in the vicinity of 30 V and of the input voltage required to produce outputs of ±10 V for only 5% of the time it is in the vicinity of 65 V.43 operates in a D1 manner analogous to that in Fig. *** = very challenging. * = difficult problem. IBIAS that is 100 (a) Find the positive threshold value of vI at which Q3 is CHAPTER 12 times the standby base current in Q1 . P12. Use VCC of 15 V. thus put stage shown in Fig. A similar process transistors with VBE = 0. Simultaneously. The latter supply is utilized only infrequently. the circuit is equipped with a higher voltage supply ±VCC2 . D1 turns off.43 Q3 turns on. and a current in Q5 that turned on. Design the circuit and the voltage of the VBE multiplier VBB = 1.40 normal power supply ±VCC1 . Compare to the value of PD dissipated in amplifier known as class G. the threshold value. ** = more difficult. VCC2 = 70 V.42 Repeat Exercise 12. Normally. vI is larger than the specified threshold. This continues as long as current from Q3 in the event of a short circuit or other mishap. VEB = 0.7 V at a 1-mA current and β = 10. and Q3 has place of D1 and Q3 . 12. Q3 and Q4 are off. find the maximum allowable output voltage.98. find the ratio n that results in an incremental gain of 0.5 . and all devices have the same |Vt |. 12. Let IQ = 2. (c) If QN is required to supply a maximum load current If the normal peak output current is 75 mA. show that the small-signal voltage gain at the 12. VOV = 0. drop across R and the collector current in Q5 . and that in the quiescent state each operates at to drive a load resistance of 50 while exhibiting an an overdrive voltage of 0. output resistance.46 (a) For the circuit in Fig. 12. when the (b) In the quiescent state with v O = 0. 12. Also. 12. find the voltage VGG that results in 2 mA. Find the value of R that (a) Specify the W/L ratio for each of the four transistors. find the voltage of 10 mA.23 for the following conditions.5-V power supplies and is required to provide a circuit so that at 125°C. *** = very challenging. and that in D 12.48 Consider the design of the class AB output stage of 2 mV/°C. find the output resistance at the quiescent D 12. kn = kp = nk1 = 2 QP and QN should be operated. 12.25 are matched. 12.50 For the CMOS output stage of Fig.5 V and 2 12.45 (a) Show that for the class AB circuit in Fig.49 The class AB output stage in Fig. ** = more difficult. QN and QP are matched. D = design problem .8-V zener diode with a TC of D 12. Design the from ±2. QN turns off when v O = 4IQ RL and D 12.7 V at PROBLEMS Fig. output stage (Fig. If the stage is required to supply 1 a maximum current of ±20 mA. causes Q5 to turn on and absorb all of IBIAS = 2 mA. * = difficult problem.2 V to operate properly. Z1 is a 6.25. of 2.23.15 V.2 mA. This is equivalent to saying that one of the transistors turns off when iL reaches 4IQ .5 mA and μ = 5.44 Consider the thermal shutdown circuit shown in Fig.5 V. gain error of less than 3%. 12.47 Design the circuit of Fig. quiescent condition is given by vo RL |Gain error| = Rout = v i RL + 2/gm RL where gm is the transconductance of each of QN and QP and (b) For a stage that drives a load resistance of 100 with a where channel-length modulation is neglected. Vtn = − Vtp = 0. The stage is operated a current of 100 μA and have a TC of –2 mV/°C. RL = 1 k. nk2 .51 (a) Show that for the CMOS output stage of Fig. that all devices have |Vt | = 0. What is the current in Q2 at 25°C? a maximum current equal to 10 times the quiescent current IQ .23 in which Q1 and Q2 point. and Q1 and Q2 are BJTs that display VBE of 0. what is the output voltage Rout = 2gm swing realized? (b) For a circuit that utilizes MOSFETs with Vt = 0. = Multisim/PSpice.52 Show that in the CMOS class AB common-source quiescent current IQ . a current of 200 μA flows in each of minimum output voltage swing of ±1. Also find the 12. IS = 10 A.2 V for each of QP and QN at the quiescent Rout = 20 . what must v I be? −14 current being sourced reaches 100 mA. Design so that Q1 and Q2 are matched and QN and QP D *12. find IQ . are matched.1 mA.5-V power supplies. Assume that the transistor supplying IBIAS needs a minimum of 0.53 It is required to design the circuit of Fig. Problems 989 CHAPTER 12 not appear directly at the output. point.45 V.5 V while supplying Q1 and Q2 . D 12. Assume that QN and QP are matched and Q1 and Q2 Section 12.5 V. around the quiescent point. What is the value of VOV required. Let μn Cox = 250 μA/V . and μ = 5. and VDD = VSS = 2. For Q5 . 12. 2 μp Cox = 100 μA/V . 2 = 1 mA with IBIAS = 0.25 with IQ = k (W/L) = 200 mA/V .7: CMOS Class AB Output Stages are matched. where k = μCox (W/L). find the overdrive voltage at which (b) For the case IBIAS = 0.24 utilizes two gmn + gmp 2 matched transistors with kn = kp = 200 mA/V and is operated which for matched devices becomes from ±2.23 to operate at IQ QP turns off when v O = −4IQ RL . At 25°C. 12. the quiescent state all transistors are operated at the same the small-signal output resistance in the quiescent state is overdrive voltage.22. and given by what VGG is needed? 1 Rout 12. 12.25). and k1 = 20 mA/V . (a) Specify (W/L) for each of QN and QP .5 V. Vtn = − Vtp = 0. latter consists of complementary Darlington emitter followers 2 kp = 100 μA/V . 990 Chapter 12 Output Stages and Power Amplifiers PROBLEMS Operate QN and QP at IQ = 1.15 V. . CHAPTER 12 (c) What is the expected error in the stage gain? Transistor Q6 is placed in direct thermal contact with the (d) In the quiescent state. The 2 technology utilized is specified to have kn = 250 μA/V . Of special interest is the bias circuit utilizing two VBE (b) Specify the required value of μ.5 V. what dc voltage must appear at the output transistors and thus has the same temperature as that output of each of the error amplifiers? of QN and QP . (e) At what value of positive v O will QP be supplying all the load current? Repeat for negative v O and QN supplying (a) Show that VGG is given by all the load current. multipliers formed by Q5 and Q6 and their associated resistors.5 mA and VOV = 0. and VDD = VSS = 2. formed by Q1 through Q4 and has the low output resistance necessary for driving the output MOSFETs at high speeds. The employing BJTs for biasing and in the driver stage. . 54 = Multisim/PSpice. lizing a pair of complementary MOSFETs (QN .54 shows a class AB output stage uti. QP ) and show that IBIAS Figure P12. * = difficult problem. *** = very challenging.54 Figure P12. R R (f) What is the linear range of v O ? VGG = 1 + 3 VBE6 + 1 + 1 VBE5 − 4VBE R4 R2 (b) Noting that VBE6 is thermally coupled to the output devices *12. D = design problem . while the other BJTs remain at constant temperature. ** = more difficult. Problems 991 . P12. P12. calculate approximate values for the bias RL ? Using 1 k as the smallest resistor. Find R3 /R4 that provides this temperature stabiliza- ◦ tion when |Vt | changes by −3 mV/ C and ∂VBE /∂T = PROBLEMS ◦ − 2 mV/ C. *** = very challenging. Which are they? Which controls the gain alone? Which affects both the dc output level and the gain? A new design is being D 12.] What is the gain v O /v I ? For op amps (using ±15-V supplies) that limit at 12. similarity of this circuit to the front end of the instrumentation What changes are needed? amplifier circuit shown in Fig. R. with considered in which the output dc level is approximately 23 VS high input resistance. assuming all transistors to have large β. Make sure that the signals at the VBE = 0. Assume β npn = 100.20(b). show that iO = v I /R. outputs of the two amplifiers are complementary.60 = Multisim/PSpice. ∂VGG /∂T is made equal to ∂(VtN + VtP )/∂T . 12. Use the graph of Fig. what is the largest sine wave you can provide across For VS = 22 V. VGG . and currents that make v O /v I = 8 V/V. (Use only the given graphs.60 An alternative bridge amplifier configuration. do not interpolate.29. find resistor values in Q1 through Q6 . 12.58 Section 12. Also find the dc voltage at the output.32. ±13 V. and hence their quiescent current. (d) Using the value of R3 /R4 found in (c) and assuming that the nominal value of VBE is 0. β pnp = 20. * = difficult problem.8: IC Power Amplifiers D 12.7 V. constant with temperature variation. by what approximate percentage is iO actually lower than this ideal value? Figure P12. two D 12. 12. ** = more difficult.] For β = 100. Figure P12.60.55 In the power-amplifier circuit of Fig. let R1 = resistors are important in controlling the overall voltage gain.59 For the bridge amplifier of Fig. R3 = 10 k. and R1 /R2 to establish a quiescent current of 100 mA in the output transistors and 20 mA in the driver stage. see Sedra and Roberts (1990).7 V and that the MOSFETs 2 have |Vt | = 3 V and μCox (W/L) = 2 A/V . what is the maximum possible load power? To deliver this power to the load what peak-to-peak output sinusoidal voltage is required? 12. is shown in Fig. [Note the (rather than approximately 21 VS ) with a gain of 50 (as before).29.58 For the circuit in Fig.) If the maximum allowed THD is to be 3%. D 12.58.57 It is required to use the LM380 power amplifier to drive an 8- loudspeaker while limiting the maximum possible device dissipation to 2 W.56 Consider the front end of the circuit in Fig.31 to determine the maximum possible power-supply voltage that can be used. Find R2 and R4 to obtain an overall gain of 8 V/V. find |VGS |. D = design problem . 12. 2. ∂VGG R ∂VBE6 CHAPTER 12 = 1+ 3 ∂T R4 ∂T (c) To keep the overdrive voltages of QN and QP . [This voltage-to-current converter is an application of a versatile circuit building block known as the current conveyor. If long life and discharging of a capacitance C across the load. 12. the maximum VDS occurs 25°C is 0. and a maximum junction temperature of 150°C.9 Class D Power Amplifiers VDD 12. what is the maximum power supplied D 12.34(b): (a) If vA is a sine wave. what is 2 be shown that this switching power is given by 4fs C VDD . To improve the corresponding values of IDmax and PDmax ? reliability. and an average emitter current of 3 A. What is its average value? If the ⫺ duty ratio is changed to 0.61 Sketch diagrams resembling those in Figs. the corresponding device power rating? What is the greatest Find an expression for the power-conversion efficiency average collector current that should be considered? η and evaluate the value of η for the case fs = 250 kHz 12. It can requires a maximum junction temperature of 130°C. of 10 W. VDSmax = 50 V. If the thermal resistance of the transistor is known to be less than 3°C/W. 992 Chapter 12 Output Stages and Power Amplifiers PROBLEMS Section 12. *** = very challenging.5°C/W is operating at an ambient temperature of (b) The power loss is mostly due to the repeated charging 30°C with a collector–emitter voltage of 20 V. 12.65.33(a).80 V. D = design problem . to 100°C. extreme reliability is essential. what is the highest junction temperature (b) If the MOSFET is used in the common-source configu- you would expect? If the transistor VBE measured using a ration as shown in Fig. what average VBE would you expect under when ID = 0. 20 W.63 For the circuit in Fig. (b). ** = more difficult.68 For a particular application of the transistor specified the operating point is always within the SOA. Let the frequency of vT ID R be 5 times that of vA . Let vT have ±10 V peaks and assume vA is a sine wave with 5-V peak amplitude. the maximum junction temperature is to be limited (d) Repeat (c) for VDD = 30 V. 12.64.10 Power Transistors its junction temperature when dissipating 5 W at an ambient temperature of 50°C? 12.35. and the maximum power dissipation occurs normal operating conditions? (Use a temperature coefficient when VDS = VDD /2. What is its thermal resistance? What is its power rating when operated at an ambient temperature of 50°C? What is Section 12. and PDmax = 50 W.64 12. * = difficult problem. of –2 mV/°C.7. what does the average value VGS become? ⫺ Figure P12. in terms of VDD ? θJA = 2. conditions specified? = Multisim/PSpice.65 A particular transistor having a thermal resistance to a load of resistance R. find the smallest resistance R for which 12.64 A power MOSFET is specified to have IDmax = 5 A.) (c) For VDD = 40 V. show that the maximum pulsed emitter current of 3 A at a junction temperature of current occurs when VDS = 0. What are the consequences of this decision for the (e) Repeat (c) for VDD = 15 V. P12.62 A pulse waveform swinging between ±10 V has VGS ⫹ a duty ratio of 0. What are in Example 12. The comparator output levels are ±10 V. dissipates (a) Sketch the SOA boundaries. CHAPTER 12 ⫹ 12.67 A power transistor operating at an ambient tempera- ture of 50°C.66 A particular transistor has a power rating at 25°C and C = 1000 pF. what heat-sink temperature to the heat sink with a bond having a thermal resistance is necessary to ensure safe operation at 30 W? For an ambient θCS = 0. ** = more difficult.70 A power transistor for which TJmax = 180°C can CHAPTER 12 12.69 A power transistor is specified to have a maximum junction temperature of 150°C. from junction to case? of length. Problems 993 12. *** = very challenging. D = design problem . * = difficult problem. what heat-sink thermal resistance is θSA = 0. for a particular extruded-aluminum-finned heat the power being dissipated in the device? What is the thermal sink. If the ambient temperature is 25°C. the case to a heat sink using an insulating washer for which the temperature is found to be 97°C.1°C/W. how long a heat sink is needed? = Multisim/PSpice. The case is attached thermal resistance is 0. If it is connected at this junction temperature with a heat sink. When the device is operated dissipate 50 W at a case temperature of 30°C. θJC .5°C/W and the thermal resistance of the heat sink temperature of 27°C. what is required? If.6°C/W. the thermal resistance in still air is 6°C/W per centimeter PROBLEMS resistance of the device. The disadvantage is a high open-loop output The slew rate of a two-stage op amp is determined by the resistance.1074 Chapter 13 Operational-Amplifier Circuits To obtain low input offset voltage and current. The use of Miller frequency compensation in the 741 To regulate the dc bias voltages at the outputs of circuit enables locating the dominant pole at a very low the differential folded-cascode stage so as to main- frequency while utilizing a relatively small compensating tain active-mode operation at all times. 13.2-V important issues such as allowable signal swing and amplifier magnitude. Note that if a particular parameter value is not specified in the problem 13. The process technology provides devices with nonlinear distortion. however. the 741 input stage is designed to be perfectly to a number of new important specifications including balanced. * = difficult problem. common-mode capacitance. PROBLEMS Computer Simulation Problems Section 13.1 V or so from each of the supply rails. = Multisim/PSpice. near rail-to-rail output voltage swing. A2 . you are to make a reasonable assumption.1 is fabricated in a process for which VAn = 25 V/μm and VAp = 20 V/μm. modern BJT op amps quiescent current as well as to ensure that the inactive typically utilize a single ground-referenced supply of only output transistor does not turn off. To obtain high input resistance and low input bias current. Two-stage op amps can be modeled as a transconductance The output stage of a low-voltage op amp utilizes a amplifier feeding an ideal integrator with CC as the complementary pair of common-emitter transistors. is substantially reduced when first-stage bias current and the frequency-compensation negative feedback is applied around the op amp. increases in crossover distortion. capacitor. Find A1 . more than rail-to-rail operation) and a point. ** = more difficult. feedback is employed. be found in the corresponding files on the website.4 V. for the input differential pair as well as utilizing two complementary differential amplifiers in parallel. and to investigate transistors are operated at overdrive voltages of 0. Find the input common-mode range and and Multisim simulations for all the indicated problems can the range allowed for v O . This. statement. output short-circuit protection is accomplished To increase the gain of the input stage above that achieved by turning on a transistor that takes away most of the base with resistive loads. The CMRR is increased by common-mode a common-mode input range that extends beyond the feedback. allows v O to swing to within 0. This integrating capacitor. The rail-to-rail input common-mode range is achieved the input stage of the 741 is operated at a very low current by using resistive loads (instead of current-mirror loads) level..2 The CMOS op amp of Fig. D = design problem . 13. a precaution that avoids 2 V to 3 V.1 utilizes ±1-V power supplies. the folded-cascode configuration is current drive of the output transistor. and high Operation from a single low-voltage supply gives rise CMRR. which also stabilizes the dc operating supply rails (i. *** = very challenging.e.1: The Two-Stage CMOS Op Amp Problems identified by the Multisim/PSpice icon are 13. Modern output stages operate in the class AB mode While the 741 and its generation of op amps nominally and utilize interesting feedback techniques to set the operate from ±15-V power supplies. Instructions to assist in setting up PSpice Vtn = Vtp = 0. utilized.1 A particular design of the two-stage CMOS operational intended to demonstrate the value of using SPICE simulation amplifier of Fig. All to verify hand analysis and design. In the 741. If all the transistors are fP2 . of Fig. Neglect the effect of VA on the bias gain rolloff with a unity-gain frequency ft of 100 MHz. C1 = 0. VA for all devices = 15 V. D 13. W. (d) To increase the phase margin.3 36/0.6 A two-stage CMOS op amp has Gm1 = 0.7 For the CMOS amplifier in Fig. and of the right-half-plane zero. μp Cox = the value of CC that results in ft = 50 MHz. The for all devices. and at overdrive voltages of 0. Find the value left half-plane and thus turns the phase it introduces into of CC that will provide a unity-gain frequency of 120 MHz.3 μm and are operated at octaves below ωP2 . * = difficult problem.3 The CMOS op amp of Fig. 13.15-V magnitude. to be? operated at equal overdrive voltages of 0. find the frequencies of the two do you expect the output resistance of a unity-gain voltage poles in radians per second and sketch a Bode plot for the amplifier to be. Q1 and Q2 are operated 100 k. let Gm1 = 1 mA/V. between node D2 and ground is 0. find ωP2 .3 6/0. While utilizing a Provide your results in a table. and sketch a Bode plot for the gain magnitude. gm .1 with the device geo. 13.3 6/0. find theminimum required channel length.4 Consider the circuit in Fig. (e) If R is increased further. R2 = 50 k. What is the dc gain in series with CC . What (b) Without CC connected. For this value of CC . Problems 1075 CHAPTER 13 Transistor Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 W/L (μm/μm) 36/0. fZ . Determine the width of Q6 . determine the op-amp output resistance (a) Find the dc gain.1 to (b) What do you estimate the frequencies of the poles. 13.2 pF. 13.1 is fabricated in (c) With CC connected. 13. and Q6 is operated C2 = 2 pF. the input common-mode range.2. Also. find ωP1 and ωZ equal overdrive voltages.3 and Av if all devices are 0.1 pF. evaluate ID . (a) What must the value of CC be? D 13. Then. and R. 13. capacitance between the output node and ground is 3 pF.3 μm long.8 A CMOS op amp with the topology in Fig.2 pF.3 30/0. using this op amp? gain magnitude. D = design problem .3 W /0. until it moves the zero into the Gm2 = 2. and C2 = 1.1 pF. that will result in a unity-gain frequency ωt at least two If all transistors have L = 0. determine the values of fP2 and fZ . currents. VOV . ** = more difficult. Gm2 = 2 mA/V.1 and 13. Find Vt for all devices = 0.3 45/0. 2 is lower than fZ and fP2 . PROBLEMS at VOV = 0. the dc Miller compensation capacitor CC without a series resistance open-loop voltage gain. margin of 85 ? 13.2 provides Gm1 = 0. and the total metries shown at the top of this page. = Multisim/PSpice. and verify that ft 70 μA/V . R1 = fier of Figs.1.3 mA/V. obtained when the second stage is biased at 0. VDD = VSS = 1 V. the total capacitance 13. the amplifier is made to have a uniform −20-dB/decade the output voltage range. gm6 = 3 mA/V. that will ensure that the 13. drive voltage required to obtain a dc open-loop gain 13. find the magnitude of the over. and what is the resulting phase margin? 13. VGS . whose equivalent D 13. total capacitance at the output node is 1 pF. *** = very challenging. C1 = 0. μn Cox = 270 μA/V2 . a resistance R is connected For this technology.9 A particular design of the two-stage CMOS op amp op amp will not have a systematic offset voltage. Also find A1 .4 mA/V.10 A particular implementation of the CMOS ampli- circuit is shown in Fig.45 V. 13.8 mA/V. what value of R is needed to obtain a phase ◦ Also. gm1 = gm2 = 1 mA/V. 13. fP1 and provide a CMRR of about 72 dB.3 mA. Let IREF = 40 μA. and ro . Then find the value of CC a process for which VA for all devices is 20 V/μm.1 has Gm1 = 1 mA/V and Gm2 = 2 mA/V.1 has of 1600 V/V. VA = 15 V/μm. A2 .15 V and have equal (c) What is the phase margin obtained? channel lengths.3 6/0. What is the value of R that results in realized? fZ = ∞.5 Design the two-stage CMOS op amp in Fig.2 V. phase lead. What is the voltage drop across RB ? Also specify (b) What is the maximum value that C2 can have while the W/L ratios of Q10 .15 V.5 V. as in (c). and Q8 . Transistors Q10 .17 (a) Show that the PSRR of a CMOS two-stage op of Q1 and Q2 is biased at 50 μA. what is the required D 13. and let VDD = VSS = 1. Q11 . D = design problem . VA = 15 V/μm. find the value of CC that results obtained? in the highest possible value of ft while providing a phase 13.14 A CMOS op amp with the topology shown and C2 = 1 pF.e. what must the value amp for which all transistors have the same channel length of CC be? and are operated at equal VOV is given by D 13.5 V. = Multisim/PSpice. what value of 80° phase margin. What do transistors in the input stage (i.15 V.13 A CMOS op amp with the topology shown and Q13 are to be identical and must have the same gm as Q8 in Fig. The op amp has a uniform −20-dB/decade frequency fier having the structure of Fig. Q12 .6 mA/V. (b) Find the frequency of the second pole.8 to value of CC ? provide a bias current IREF of 225 μA with Q8 and Q9 as matched devices having W/L = 60/0. 13. What required to obtain a PSRR of 72 dB? For the technology value should R have? If the first stage is operated at available. in Fig.. causes the transmission zero to be located (b) For R = 500 . and Q13 and give the expected achieving a 70° phase margin? dc voltages at the gates of Q12 . what is the (a) Estimate the value of the overdrive voltage at which the phase shift introduced by the second pole? To reduce input-stage transistors are operating. you expect the slew rate of this amplifier to be? If each − D 13. 1076 Chapter 13 Operational-Amplifier Circuits Gm2 = 0.5. series with CC . Let 2 Gm2 = 5 mA. 13. of C2 for which a phase margin of at least 60° is (d) With R in place. ro2 = ro4 = 222 k. 13.12 A two-stage CMOS op amp similar to that in 2 Fig. Q10 . as before. 13. when placed in (a) Find the value of CC that results in ft = 100 MHz.16 Sketch the circuit of a two-stage CMOS ampli- 0. and Vtn =|Vtp |= 0. what value should R be CC must be used? 2 changed to? (c) For a process for which μp Cox = 60 μA/V .1 but utilizing NMOS response with a unity-gain frequency of 100 MHz. * = difficult problem. ** = more difficult.7 pF. (c) Find the value of the resistance R that. Q1 and Q2 ). Gm2 = 2 mA/V. Find the required (a) Find the value of CC that results in ft = 80 MHz. this excess phase shift to 10° and thus obtain an (b) If the first-stage bias current I = 120 μA.1 is found to have a capacitance between the output V PSRR = 2 A − node and ground of 0. *** = very challenging. what is the minimum channel length − adjusted to place the transmission zero at infinity. (e) To what value should CC be changed to double the value of ft ? At the new value of ft .1 is designed to provide Gm1 = 1 mA/V and and Q9 . What value of ft is realized? What is the Fig. D 13. what is the maximum allowed value CHAPTER 13 at s = ∞. 13. Transistor Q12 is to be four times as wide as Q13 . If it is desired to have a unity-gain V bandwidth ft of 100 MHz with a phase margin of 72° what OV must gm 6 be set to? Assume that a resistance R is connected in series with the frequency-compensation capacitor CC and (b) For VOV = 0. what is the value of slew rate obtained? If the first-stage bias current I = 100 μA. fP 2 . PROBLEMS D 13.15 A two-stage CMOS op amp resembling that in margin of 80°. value of RB .11 A two-stage CMOS op amp has each of its first-stage transistors Q1 and Q2 operating at an overdrive voltage of D 13.18 It is required to design the circuit of Fig. 13. Q11 . let all channel lengths be equal.1 but with a resistance R included in series with CC is designed to provide Gm 1 = 0.1 is found to have a slew rate of 60 V/μs and a corresponding frequency of the dominant pole? unity-gain bandwidth ft of 60 MHz.8 mA/V and (a) Find the dc gain. what W/L ratio applies for Q1 and Q2 ? 13. ro6 = ro7 = 111 k.2 V. VOV = 0. kn = 3kp = 180 μA/V . 13. required width of each of the 11 transistors used. P13. show that Q12 and Q13 will be cut off.10 with bias currents I = 400 μA and IB = 250 μA. for the dc voltages shown. Observe that three transistors C are added: Q14 . 13.15 V. and with all transistors operated at overdrive voltages of 0.10. which are diode connected and are normally cut off. if the the additional circuitry does two things: It prevents Q1 and op amp is connected in the feedback configuration shown Q11 from going into the triode region.5kp = 400 μA/V . at which each of Q3 and Q4 is biased. and Av . Q9 . 13. Ro . find the voltage gain and output resistance of current available to charge CL and thus increases the slew rate. In particular. for kn = 2.9 2 is achieved? Also. 13.15 V.2 V. find the W/L ratios for all devices.4 . 13. Q3 .45 V and that all conducting Figure P13.2 V and that for all transistors are deal with the situation during amplifier slewing.27 (with the current-mirror circuit omitted. that is. and operate VICM and v O . Also.19 The op-amp circuit of Fig. and it increases the in Fig.27 This problem presents a very interesting addition to for which I = 400 μA and IB = 250 μA. Design for IB = I. designed to operated at VOV = 0. * = difficult problem.10 to utilizing power supplies of ±1 V. What slew rate D 13. I < IB . the closed-loop amplifier.22 devices are operating at |VOV | = 0. and assuming Vtn =|Vtp |= 0.10 is operated from is the phase margin obtained? If it is required to have a phase ±1-V power supplies.25 Design the folded-cascode circuit of Fig.10. Also. what D 13. find the bias current in each of Q1 .VBIAS2 . and ID3. devices. Q14 . what is the unity-gain bandwidth realized? If the two nondominant poles have the same frequency of 50 MHz. Assume that all the folded-cascode op-amp circuit of Fig. The circuit is shown in Fig.22 Consider a design of the cascode op amp of Fig. find the 13.24 For a particular design of the folded-cascode op amp PROBLEMS value of I. Find the 0. which is biased by a constant-current source 9C (20 μA). in Fig.23 Consider the folded-cascode op amp of Fig. = Multisim/PSpice. establishes the dc currents in Q9 and Q10 . what must ft be reduced to? By what amount to be limited to 1 mW. Noting that the drain input-stage transistors are biased at a current three times that current of Q12 adds to the 20 μA flowing through Q14 . Rof Q4 . Assume that all transistorsare operated at equal all devices at the same V OV . find the maximum value of IB allowed. Vi (a) For Vid = 0. What should the bias and Q1 to conduct the entire bias current (320 μA). 13. 13. Problems 1077 Section 13. D = design problem . *** = very challenging.4 V. 13. find the value of I. should CL be increased? What is the new value of SR? If this value is used. Specify the maximum range of VICM and of v O . Assume that the D 13.10 D *13.15 V. Q12 current IB be to obtain a slew rate of at least 10 V/μs? If the turns on (while Q13 remains off). required overdrive voltages and bias currents. Find Gm .26 Sketch the circuit that is complementary to that in 2 technology available is characterized by kn = 400 μA/V and Fig. and VBIAS3 to maximize the allowable range of 20 MHz when CL = 10 pF. Utilize transistors with 1-μm overdrive voltages of 0. If the power dissipated in the circuit is margin of 75°.10 **13. ** = more difficult. If the find the current that now flows through Q10 and onto CL . What slew rate is obtained? D 13. and each of Q1 and Q2 is to be biased at a current four times that used for each of Q3 and Q4 . one that uses an input p-channel differential 2 kp = 100 μA/V .21 For the folded-cascode op-amp circuit of Figs. 13. D 13. and Q10 . pair. ID1.20 For the folded-cascode op amp in Fig.2 .22. specify the and 13. find the values of provide voltage gain of 80 dB and a unity-gain frequency of VBIAS1 .9. for simplicity).9 (b) For an input differential signal that causes Q2 to turn off when loaded with a 10-pF capacitance. 13. Assume with respect to Q9 and Q10 that each has a W/L ratio 10 times that of Q14 . Q2 . VA = 10 V.2: The Folded-Cascode CMOS CHAPTER 13 input-stage transistors are operated at overdrive voltages of Op Amp 0. Assume Vt for all devices is channel length for which VA is specified to be 12 V. P13. The other two additional transistors are Q12 and Vo Q13 . Find (a) largest value that CP can be (expressed as a fraction of CL ) the range over which the NMOS input stage operates. Assume that all current sources require Section 13. If VA is specified to be 10 V. All these devices are of the “standard npn” −14 value of VBIAS is needed? Also give the voltages that you type. 13. For IREF = 90 μA.12. Provide your allowable at the output terminal.27 By what factor does the slew rate increase relative to D 13. what current of 550 μA.25 V Q1 Q2 CL 320 A 0. having IS = 10 A.4 V Q11 –1 V Figure P13. For each expect to appear at all nodes and specify the minimum voltage of these transistors.14. (Note that these parameter values are what is the output resistance of the mirror? utilized in the text in the analysis of the 741 circuit. resistance between the drain of Q3 and ground is small.13(b) utilizes devices having W/L = 20. gm . Q2 . 13. show that the pole that arises at the interface between the 13. a collector current of 16. let the the value without Q12 present? Also give an approximate total capacitance to ground at each of the source nodes of estimate of the voltage at the drain of Q1 during the Q3 and Q4 be denoted CP . Q1 . results in table form.2 μA. and 13. rπ . (c) the range transistors are operated at the same bias current and overdrive over which both operate (the overlap range).28 For the circuit in Fig. 1078 Chapter 13 Operational-Amplifier Circuits 1 V PROBLEMS Q9 Q14 Q10 Q13 Q12 CHAPTER 13 Q3 Q4 20 A 0. if this is the only nondominant pole. β = 200. 13. and (d) the input voltage. what is the and have Vt = 0. re . D = design problem . ** = more difficult. 13.) = Multisim/PSpice. and Vt = 0. *** = very challenging. assume that all transistors first and second stages has a frequency fP gm3 /2π CP . 13.45 V and that VDD = VSS = 1 V. are operating at equal overdrive voltages of 0.31 In the 741 op-amp circuit of Fig.15-V magnitude Now. * = difficult problem.3: The 741 BJT Op Amp a minimum voltage of |VOV | to operate properly.9. Q6 are biased at collector currents of 9. and ro . and Q17 is biased at a collector 2 kn = 400 μA/V . Q16 is biased at ror of Fig. Q5 .30 For the folded-cascode circuit of Fig. and VA = 125 V. Assuming that the incremental slewing transient.45 V. find VBE . common-mode range. (b) the while a phase margin of 80° is achieved? Assume that all range over which the PMOS input stage operates.5 μA.29 A particular design of the wide-swing current mir. Problems 1079 k3 = k4 = 16k1 .32. neglect base currents and use the exponential iC−vBE relationship to show that current in Q3 and Q4 of 1. . find the required value of I1 to yield a bias CHAPTER 13 D 13. P13.6 mA.32 For the circuit in Fig. I become? Redesign the Widlar source to reestablish IC 1 = Note that k denotes μCox W/L.35 shows the CMOS version of the D 13. 13. What is I now in terms of IC10 ? If voltage would result in the breakdown of the input-stage βP changes from 50 to 20.15 for the situation in which IS 9 = 2IS 8 . Assume Figure P13. What differential input connection of Q3 and Q4 . PROBLEMS 15 V I1 Q3 Q1 I3 Figure P13. *** = very challenging.34 In the circuit of Fig.35 Q2 D 13. what is the resulting percentage transistors? change in I? D 13. What value of R5 would be necessary to reestablish the same bias current for ±10-V supplies as exists for ±15 V in the original design? 15 V D 13. find values for the is the percentage change in I if βP drops from 50 to 20? parameters VEB . That is.5 μA. in terms of k1 . = Multisim/PSpice. I I I3 = I1 S3 S4 IS1 IS2 −14 Find I1 for the case in which IS3 = IS4 = 3 × 10 A. estimate the reference current Q4 IREF in the event that ±10-V supplies are used. (b) Now.37 Design a Widlar current source to supply a current of 10 μA given a reference input current of 0. what does the threshold voltages of all devices to be equal in magnitude. and k4 of the four transistors. 13.39 Consider the dc analysis of the 741 input stage circuit in Fig. 13. ** = more difficult. −14 ISB = 0. What at a total emitter current of 0.25 × 10 A. in Fig. Q8 and emitter–base breakdown at 7 V. 13. In the event that k1 = k2 and IC 2 = 9. For operation (a) Derive an expression for I taking βP into account.32. of two transistors whose emitter–base junctions are 13. while for Q3 and Q4 such Q9 are eliminated and IC10 is fed to the common-base a breakdown occurs at about 50 V. re .15. in effect. β = 50. IS1 = −14 IS2 = 10 A.73 mA. and ro for the A and B devices. k2 . gm .75 × 10 A. * = difficult problem. P13. and VA = 50 V.33 Transistor Q13 in the circuit of Fig. D = design problem .38 Consider the dc analysis of the 741 input stage shown −14 connected in parallel and for which ISA = 0. Find VBE of each of the two transistors as well as the value of R.14 consists. 13. consider an alternative design of this circuit in 13. rπ . k3 . assuming For IC 10 = 19 μA and assuming β P to be high.36 For the 741 circuit.35 Figure P13.32 −14 that the transistors have IS = 10 A and high β. Find the relationship between I3 and I1 shown in Fig.14. and a bias current I3 = 150 μA is required.3 mA. Q1 and Q2 exhibit which the feedback loop is eliminated. 13. Recall that β N = 200. terminal voltage of 1.48 An alternative approach to providing the voltage must R2 be increased to in order to increase Ro6 by a factor of drop needed to bias the output transistors is the VBE – multiplier 2? Recall that Q6 is operating at IC6 = 9. per side. find the input common-mode range. Recall that IREF = 0. namely.6 V. 13.44 For a particular application. what does the current in Q6 become if R2 is shorted? D 13. with two additional npn diode-connected transistors.43 Consider the input circuit of the 741 op amp of Fig. 13. D = design problem . one Neglect the voltage drops across R1 and R2 .48.7 M. ** = more difficult. Figure P13.21) stage. 13. what must be the ratio circuit? of the emitter–junction area of Q9 to that area of Q8 ? Assume that βP is large. but with no load? Hence. Convince yourself that each of the additional devices will be biased at the same current as Q1 to Q4 —that is.14. Q6 . Ro4 = 10.47 Reconsider the 741 output stage as shown in these values with the original ones. consideration is being required from the power supplies when the op amp is operated given to selecting 741 ICs for input bias and offset currents in the linear mode. If IC10 = PROBLEMS resistance between the two terminals of the VBE – multiplier 40 μA and I is required to be 10 μA.) What is the new open-circuit voltage gain. Fig.5 μA and has β = 200 circuit shown in Fig. What value D *13. |VBE | = 0. respectively.45 For a 741 employing ±5-V supplies.2 M. 13.1. 13.19.5 M. estimate the limited to 60 nA and 5 nA.5 μA. D 13. Ro1 = 6. 13.24 with R1 = R2 replaced by 2-k −14 assume that IS = 10 A and β = 200. what minimum given in Table 13. 13. 180 μA 13. Q2a . Find the new value of R3 and the three currents.14 when the emitter current of Q8 is about 19 μA. what is the total current 13. Base your design on half the current flowing through R1 .) β N and what β N variation are implied? 13. 13. Gm 1 Ro1 ? Compare D 13. Q1a and and |VCEsat | = 0. = Multisim/PSpice.118 V (the same as in the 741 circuit). in which R10 is adjusted to make IC 19 = IC 18 .2 V.19 mA/V. assuming that the input current IC 3 = 9. Ro1 ? (Note that Ro6 remains unchanged at 18. Rid = 21 M.49 For the circuit of Fig.18.48 If β of Q1 is 150 and that of Q2 is 220. What Gm1 = 0.73 mA.16 by selecting a new value for R3 so that when the base currents are not neglected.40 Consider the circuit shown in Fig. and is the new value of R10 ? What values of IC 14 and IC 20 result? |Avo | = 1273 V/V. Assuming other quiescent power dissipation in the circuit.5 μA. * = difficult problem. 13.17. Design the circuit to provide a and VA = 125 V.52 Repeat Exercise 13. 13. *** = very challenging. find the input bias current IB and the input offset current IOS of the op amp. the collector currents of Q5 .42 It is required to redesign the circuit of Fig. and Q7 all become equal. What does Rid become? What does Gm 1 become? What is the What value of R9 would be needed to reduce IC 16 to 9. What is the incremental resistors. (Hint: Use the data aspects of the selected units to be normal.50 Consider the 741 input stage as modeled in Fig. 1080 Chapter 13 Operational-Amplifier Circuits D 13. P13.5 μA? value of Ro4 now? What is the output resistance of the first (Hint: Build on Exercise 13.15.41 For the mirror circuit shown in Fig.46 Consider the design of the second stage of the 741. connected between the present npn and pnp devices.51 Consider the current mirror in Fig. 9.16 with I 180 μA the bias and component values given in the text for the CHAPTER 13 741 circuit. and 13. 13. (Hint: Use Eq.) For simplicity. 13.e.59 An alternative approach to that presented in Exam- (Recall that each of Q5 and Q6 is biased at 9.94. we observe that the negative feedback increases the resistance at node Y by the amount of negative feedback.28.56 If the current transfer ratio of the mirror load of the 741 at 9. What resistor in the emitter Fig.5.19. to the left of node Y become? (Recall that Q9 is biased at 0.55 Through a processing imperfection.) R2 in Fig.61 In the analysis of the 741 second stage. *** = very challenging.995. what input offset voltage results? input stage is 0. 13. We can then determine the current i and Gmcm .54 is affected most strongly by the low value of Ro13B . 13. and Q13B on this value. we can break the loop at Y and connect a resistance Rf = (1 + Aβ)Ro between the common-base connection of Q3 −Q4 and ground. reduced to zero) by creating a relative mismatch Ro10 (i.1 M)? For this case.102 together with the output resistance values *13. (c) What is the maximum offset voltage that can be trimmed this way (corresponding to R2 completely shorted)? 13. for example) to compensate for the op-amp input offset 13. 13. Recall that the input-stage mismatch between R1 and R2 on the input offset voltage transistors are biased at 9. Using the fact that the loop gain is approximately equal to βP (Exercise 13. Rather than performing the analysis on the closed loop shown in Fig.5 μA.) ple 13. become? For what value of R does it equal for (i.5 μA. P13.. 31. What does the resistance looking into the collector (a) Show that an input offset voltage VOS can be compensated of Q9 . Consider the effect of placing appropriate resistors in the emitters of 13. 13.4 we investigated the effect of a determined in Exercise 13. resistors R in series with the emitters of each of Q8 and Q9 . Assuming that the collector current of Q3 Ro2 half as great? What resistors in each of the other emitters remains unchanged at 9.58 What is the effect on the differential gain of the 741 where re is the emitter resistance of each of Q1 to Q6 .73 mA. Thus. and op amp of short-circuiting one or the other or both of R1 and R is the nominal value of R1 and R2 . Q13A . what does Ro looking R/R between R1 and R2 .57 Consider the circuit of Fig. 13.14 is reduced to 10. Ro9 . Problems 1081 the Q5−Q6 mirror.23.54.. β = ∞.17) show that this approach yields an identical result to that found in Example 13. ** = more difficult.e.53 A manufacturing problem in a 741 op amp causes the current-transfer ratio of the mirror circuit that loads the that this mismatch introduces. and normally biased 13.14? (Refer to Fig. 13. For input devices (Q1 –Q4 ) appropriately matched and with high β. while the β of Q3 remains at its of Q13B would be required to make Ro13B equal to Ro17 and thus regular value of 50. input stage to become 0. Conversely. the β of Q4 in Q12 . * = difficult problem. D = design problem . What Ri2 and Gm2 correspond? D 13.) PROBLEMS of the op amp. find the CMRR of the input stage.) R V 1 + re /R = OS R 2VT 1 − VOS /2VT *13. find the net output dc current of would be required? = Multisim/PSpice.14 modified to include voltage. 13.54 In Example 13. R1 and R2 can be deliber- ately mismatched (using the circuit shown in Fig. (Hint: Use Eq.8 A/A.5 μA. assume (b) Find R/R to trim a 3-mV offset to zero.5 for determining the CMRR of the 741 input stage is investigated in this problem. note that Ro2 Figure P13.5 μA.60 Consider a variation on the design of the 741 second stage in which R8 = 50 . and hence find also the input offset voltage CHAPTER 13 13. 63 Consider an alternative to the present 741 output 13.73 For an amplifier with a slew rate of 10 V/μs. If Gm 1 is related to the first-stage bias current as Gm 1 = I/2VT .72 Consider the integrator op-amp model shown in Fig. the dc gain.6 V PROBLEMS current in Q22 equal to the maximum current available from and VCEsat = 0. ωt . and a resistance 7 of 2 × 10 shunting CC . what Figure P13. Find the current in R6 at which the D 13.67 Using the data provided in Eq.62 For a 741 employing ±5-V supplies. Q15 . Reevaluate the reflection of RL = 2 k to significance of the factor 0. what value of CC would be required? 13.97 in relation to the load.64 is the full-power bandwidth for outputs of ±10 V? What unity-gain bandwidth. in which its base and the overall gain of the 741 with a 2-k load.66 Consider the 741 sinking-current limit involving R7 . CC = 100 pF. For Gm 1 = 2 mA/V. was similar to that of the 741? ing Q13A . would you make to reduce this current limit to 10 mA? D 13. If the excess conducting most of the current. would you expect if the topology 13.30. What does A2 become? the open-circuit voltage gain. What are the new values of CC . (You need to perform is 4(VT + IRE /2)ωt . what dominant-pole frequency is required for 85° phase margin with a closed-loop gain of 100? Assuming CC continues to control the dominant pole. and R6 . and realizing the emitter are joined. If space exists for at most a 50-pF capacitor. R11 . what resistance level Rout must be reached at the input of the Miller amplifier for compensation to be possible? 13.64 Figure P13. D 13. For what current through R7 is the frequency? = Multisim/PSpice. Q24 . what is their frequency? D *13. calculate CHAPTER 13 the collector of Q17 .115) (alone) for stage in which Q23 is not used. find the slew rate of this op amp. (13. amp has nearly coincident second and third poles. that is. 13. what is the frequency Q18−Q19 network calculated in Exercise 13. find Rout when 13. show that the slew rate (180 μA) minus the base current of Q14 . 13..e. the current in Q8 )? What simple change apply. and Q22 .65 Consider the positive current-limiting circuit involv.64 shows the circuit for determining the op-amp output resistance when vO is positive and Q14 is 13.69 A 741 op amp has a phase margin of 80°. VBE = 0. and the 3-dB Q21 . sketch and label a Bode plot for the magnitude of the open-loop gain.) double the 741 slew rate while keeping ωt and I unchanged. * = difficult problem.35 (163 ) and of this pole? neglecting the large output resistance of Q13A . Hence find the value of RE that would a couple of iterations. and the gain with a load of 500 . the output resistance.74 If a resistance RE is included in each of the emitter collector current of Q15 equals the current available from Q13A leads of Q3 and Q4 of the 741 circuit. 1082 Chapter 13 Operational-Amplifier Circuits 13.68 A 741 op amp has a phase margin of 80°. D = design problem . *** = very challenging. Using the resistance of the phase shift is due to a second single pole. find the output voltage limits that the input stage (i.71 An internally compensated op amp having an ft of 5 6 MHz and dc gain of 10 utilizes Miller compensation around an inverting amplifier stage with a gain of –1000.2 V. 13. If the op Q14 is sourcing an output current of 5 mA. ** = more difficult.70 For a modified 741 whose second pole is at 5 MHz. VBE = 0. ro = ∞. Problems 1083 CHAPTER 13 PROBLEMS Figure P13.1 V. VBE = D 13.33 to generate a current the pair. reduce the current generated by Q6 to 10 μA? Assuming that the VBIAS1 line has a low incremental resistance Section 13. ** = more difficult. for the problems in this section currents.7 V. In its emitter lead is connected a resistance of 1:4.33 for the case (a) For inputs grounded and output held at 0 V (by negative designed in Exercise 13. Assume that Q3 and Q4 are matched and design for a R5 equal to R2 . is identical to Q2 and its base is connected to I = 5 μA. What should (d) With load as in (c) calculate the value of the capacitor C the emitter areas of Q5 and Q6 be relative to that of Q1 ? required for a 3-dB frequency of 100 Hz. * = difficult problem.78 It is required to use the circuit in Fig. and R4 .33 to bias 0. The bias current-source transistor of D 13. VCEsat = 0. with npn transistors Q5 and Q6 with emitters connected to (b) Calculate the input resistance. I = 10 μA. Ignore base currents. an npn differential pair. Utilize transistors Q1 and Q2 having areas in a ratio the BIAS1 line. 13. D = design problem .77 Consider the circuit of Fig. D 13. find the output resistance of current source Q5 Design of BJT Op Amps and of current source Q6 with R6 connected.75 Figure P13. *** = very challenging. βP = 10. R3 .37. 2.75 shows a circuit suitable for op-amp 0.75 D 13. Ignore base Unless otherwise specified. when connected in the emitter of Q6 . and R2 . Q5 .4: Modern Techniques for the to ground. currents of 10 μA and 40 μA.15-V drop across each of R3 and R4 . assume βN = 40. What value of a resistance R6 will. respectively. R3 = R4 = 20 k. to generate constant (c) Calculate the gain of the amplifier with a load of 5 k. IS2 /IS1 = feedback) find the collector currents of all transistors.73 k. For all transistors β = 100. R2 = 1. Augment the circuit Neglect base currents.7 V. namely. VAn = 30 V. 13. 13. ground and bases connected to VBIAS1 .76 Design the circuit in Fig. Specify the values of applications. VAp = 20 V. The differential pair has two equal collector = Multisim/PSpice. Toward that end. Let the emitter areas of Q1 and Q5 be in the ratio 1:4. What is the input common-mode range and current IQ of 0.83 Consider the equivalent half-circuit shown in Fig.8 V so that the Q3 −Q4 pair is off. what is the output resistance of the op amp? VICM 0. Then find v B6 in terms of iP . a current mismatch I = 0.38.80 For the circuit in Fig. In the expression you = Multisim/PSpice. find the voltage gain in terms of connection of Q5 and R5 where R5 = R4 . what must I and minimum current of IQ /2 in the inactive output transistor. Let (b) For iL = 0.4. first find v B7 in terms of v BEN across R7 is 0. and hence find the purpose note that Q4 measures v EBP and develops a current open-circuit voltage gain (i. 1084 Chapter 13 Operational-Amplifier Circuits resistances RC connected to VCC . RC be changed to? Also.130) at a current I. The emitter-degeneration resistances (d) If the op amp is sourcing a load current iL = 12 mA. 13.35(a). common-mode range? (c) In Example 13. Find RC that results in a differential 13.39. (13. and IC6 = 40 μA. D *13. Find the input in (b) to calculate the expected VCM and compare to the value common-mode range and the differential voltage gain v o /v id . 13.35(a).e. i4 = v EBP − v EB4 /R4 .5 V. that negative feedback reduces change by a factor equal to (1 + Aβ). the one in which the differential pair (b) For the values in Example 13.81 For the circuit in Fig. The input resistance of the second stage of configuration.38.. the op amp is 1. The maximum current iL that the stage the input differential resistance? Ignore base currents except can provide in either direction is 12 mA. iN . For RL = 1 M.2 V. what is the input gain Aβ.] D 13. 13. Assume that (c) If the open-loop gain of the op amp is 100. let VCC = 3 V. Ignore the loading in Fig. Specify Recall that the CMF circuit responds only to the average the required values of R5 and RC .3 μA gives rise to VCM = 2. For the latter Find the output resistance in terms of I. 13. and the output voltage vo is IRL . Neglect the effect of Ro9 Ro7 finite βN .5 M.85 The output stage in Fig.6 mA. and R9 = R10 = 33 k. with iL = 0.000 V/V. and the open-loop output resistance. Also.8. [Hint: Recall Neglect base currents. we found that with the CMF absent. Q5 supplies 8 μA. 13.8. find the closed-loop output resistance obtained when the and that all four cascode transistors are operating in the op amp is connected in the unity-gain voltage follower active mode. found by a different approach in Example 13. and RC = 25 k. Assume that in the original circuit. and hence iN . the output when calculating Rid . (a) Find an expression for the differential gain Ad in terms *13. and the dc voltage drop across R9 is 0. Comment on the expected gain of the common-mode feedback loop is temperature dependence of Ad . to Fig. 13. I = 20 μA. the dc voltage drop and (13.7 V. gains of 150 V/V and 300 V/V. use the value of loop gain found VBIAS = 2. * = difficult problem.3 V. 13. Q1 is biased 13. If Rid is to be increased by a factor of 4 stage is equipped with a feedback circuit that maintains a while the gain and VICM remain unchanged.36.131). 13. Fig. VBIAS = 0.86 It is required to derive the expressions in Eqs. effect of the CMF circuit on the collectors of the cascode (b) Give the complementary version of the circuit in transistors. voltage VCM of its two input voltages and realizes the D 13.82 It is required to find the input resistance and the (a) What is the allowable range of v O ? voltage gain of the input stage shown in Fig. 13.41 operates at a quiescent gain of 10 V/V.79 (a) Find the input common-mode range of the circuit transfer characteristic VB = VCM + 0. find are R7 = R8 = 22 k. For the same conditions as in (a). VCC = 3 V. Let VCC = 3 V and VBIAS = 2. This current is supplied to the series Now with RL connected. calculate the loop is npn.8. 13.37. *** = very challenging. that each of Q7 to Q10 is biased at 8 μA. Now. find I that will result in the voltage PROBLEMS taken between the two collectors. [Hint: Refer iP . D = design problem .] (e) Repeat (d) for the case of the open-loop op amp sinking a load current of 12 mA. the voltage gain for RL = ∞). 13. show that the loop of (RC /R5 ) and (IS5 /IS1 ). Aβ re7 + R7 CHAPTER 13 (b) Design the circuit for I = 20 μA and Ad = 10 V/V. let VCC = 3 V.3 V. that is. Q7 and Q9 are biased at 2I.35(b). with the CMF present.3 V. ** = more difficult.84 (a) For the circuit in Fig. 132). *** = very challenging. 13. Toward that end.88 For the output stage in Fig.6 mA. IS4 IS5 to express v B6 in terms of iP and ISN . QN has eight times the area of Q10 . ** = more difficult. Assume that I = 12 μA. Problems 1085 obtain for v B6 . and Q7 13. What is the minimum current Eq. note from the circuit in in QN and QP ? = Multisim/PSpice. (13. * = difficult problem. 13. find the current determined.131).87 It is required to derive the expression for v E in PROBLEMS has four times the area of Q11 . find iC6 and iC7 . use the relationship Fig. (13.43. IREF that results in a quiescent current IQ = 0. Now with v B6 and v B7 D 13.43 that v E = v EB7 + v BEN and note that QN con- CHAPTER 13 ducts a current iN and Q7 conducts a current iC7 given ISP I = SN by Eq. D = design problem . ** = more difficult. Vtn = −Vtp = 0.2 The CMOS inverter of Fig. and to investigate important issues such as gate noise margins and propagation delays.5 Find the PUN that corresponds to the PDN shown in Fig. * = difficult problem. and VDD = 1. Vtn = −Vtp = 0.PROBLEMS Computer Simulation Problems D 14.7 Y D 14.9 Find the PDN that is the dual of the PUN in Fig. B C D D 14. D 14. Instructions to assist in setting up PSpice and Multisim Y simulations for all the indicated problems can be found in the corresponding files on the website.13-μm process for which μn Cox = 500 μA/V . Note that if a particular A parameter value is not specified in the problem statement. you are to make a reasonable assumption.5.6 (a) Find Ron of an NMOS transistor with W/L = 1. and hence the complete CMOS logic circuit. The NMOS transistor has (W/L)n = 1.35 V. = Multisim/PSpice.5 exclusive-OR (XOR) function.10(a) and hence give a CMOS realization of the Figure P14.8 Give the CMOS realization for the Boolean function B A Y = (A + B)(C + D) C D 14. μp Cox = 190 μA/V .5.3 Give the CMOS circuit that realizes a three-input NOR gate. D 14. NMOS device in (a). Section 14.5.1 Consider MOS transistors fabricated in a 65-nm 2 2 process for which μn Cox = 470 μA/V .2 V. Problems identified by the Multisim/PSpice icon are What is the Boolean function realized? intended to demonstrate the value of using SPICE simulation to verify hand analysis and design. Figure P14. and hence the complete CMOS logic circuit. D 14.2(b) is implemented 2 in a 0. Y What is the Boolean function realized? Figure P14. P14. 14.1: CMOS Logic-Gate Circuits B C D 14. *** = very challenging.7. P14. μp Cox = VDD 2 125 μA/V . P14.6. 14.5. and VDD = 1 V. (a) What must (W/L)p be if QN and QP are to have equal Ron A resistances? (b) Find the value of Ron .4 Give the CMOS circuit for a three-input NAND gate.4 V. and hence the complete CMOS logic circuit. what must (W/L)p be? What is the Boolean function realized? D 14. (b) Find Ron of a PMOS transistor with W/L = 1.7 Find the PDN that corresponds to the PUN shown (c) If Ron of the PMOS device is to be equal to that of the in Fig. D = design problem .6 Find the PUN that corresponds to the PDN shown in Fig. R = 2 k. is to be high when an odd number (1 or 3) of the inputs are find the average power dissipation in a typical circuit. The that realizes a three-input. NMH and NML . small-scale-integrated (SSI) and medium-scale-integrated (MSI) packages. Ron = 100 . D 14.5 V.15 Design a CMOS full-adder circuit with inputs A. output: MIN (minimum) 2 V (b) Sketch a PDN directly from the expression for Y . Logic-0-level supply current: TYP 3 mA. VIH = 1. VIL = 0. (a) Find VOL . Section 14. ** = more difficult. find: value N can have while the inverter is still providing an (a) the noise margins NMH value approximately equal to its NML . This is called the equivalence or PROBLEMS coincidence function. Find when the input voltage (of the fan-out inverter) is high the high and low noise margins.3 V (c) From inspection of the PDN circuit.13 It is required to design a CMOS logic circuit printed-circuit boards to implement a digital system. VOH .2 V. 14.12 Sketch a CMOS logic circuit that realizes the and other building blocks are available commercially in function Y = ABC + A B C. B.4VDD . 14. MAX 0. = Multisim/PSpice. and NML . in the inverters) in each of the PUN and the PDN. Logic-1 output voltage: MIN 2. Each of these load inverters. is specified to require an input current of 0. or fan-out inverters as they are usually 14.10 Provide a CMOS logic gate circuit that realizes the (b) the value of VM function (c) the voltage gain in the transition region Y = ABC + ABC + ABC 14. Attempt a design with 10 transistors (not counting those The power supply is 5 V. VOH = 0. VIH = 1. VIL = 0. (a) Find the worst-case values of the noise margins. number of fan-out inverters N. reduce the number Logic-0 output voltage: TYP 0.11 Sketch a CMOS logic circuit that realizes the what value of VDD is required? function Y = AB + A B.4 V. and C0 is 1 if two or more inputs are 1. D 14.14 Give a CMOS logic circuit that realizes the function (b) Assuming that the inverter is in the logic-1 state 50% of a three-input.1VDD . VOL = 0.20 Consider an inverter implemented as in Fig.22 V. find the inverter is modeled by three straight-line segments in the resulting value of VOH and of NMH as a function of the manner shown in Fig. and two outputs S and C0 such that S is 1 if one or Let VDD = 2. Specifically. and hence the Logic-1-level supply current: TYP 1 mA. and C.2 V.19 A logic-circuit family that used to be very popular is transistor–transistor logic (TTL). B. and zero current when the input voltage is low. The TTL logic gates D 14. VIH = 1 V.17(a). 14. TYP (typical) 3.6 VDD .9 V. MAX 2 mA complete realization. D = design problem . the output of the time and in the logic-0 state 50% of the time. VIH = 0. Logic-1 input level required to ensure a logic-0 level at the (a) Give the Boolean function Y . odd-parity checker.2 V.8VDD .13. 14.16 A particular logic inverter is specified to have called.8 V. and VOH = 1. If VIL = 1. high. D 14. Such packages can be assembled on D 14. NMH .4 V. and VOH = 1. * = difficult problem. What are the noise margins? What is the width of the transition region? For a minimum noise margin of 0.3 V.4 V of transistors to 10 (not counting those in the inverters).18 For a particular inverter design using a power How many transistors are required? Explore the possibility of supply VDD . Specifically. MAX 5 mA (d) Find the PUN as a dual of the PDN in (c). Note Logic-0 input level required to ensure a logic-1 level at the that it requires 12 transistors in addition to those in the output: MAX (maximum) 0. VOL = 0.2: Digital Logic Inverters (b) The inverter is driving N identical inverters.17 The voltage-transfer characteristic of a particular logic to be supplied through R of the driving inverter. Problems 1157 CHAPTER 14 D 14. Noting that the input currents of the fan-out inverters will have 14.4 V. and C are high.2 mA VIL = 0. *** = very challenging. device data sheets provide the following specifications of the the output Y is to be low when an even number (0 or 2) of the basic TTL inverter (of the SN7400 type): inputs A. and three inputs are 1.8 V. even-parity checker. Hence find the maximum VOL = 0. and reducing the number of the transistors required.8 V.8 V inverters. VOH . VIH . * = difficult problem. VIL .19.23 A logic-circuit type intended for use in a digital-signal-processing application in a newly developed 14. λ1 = λ2 = 0. VOH . and NMH ? ideal set of values for VM . 2 VOL )/(VIL − VIH ). in terms of VDD ? Give possible values of VIL and VIH that can be expected? What are numerical values for the case VDD = 1. 14. NML . μn Cox = 500 μA/V .) 100 μW. ** = more difficult. where the gain is defined by (VOH − in terms of the transistor’s W/L ratio. it is required to design the inverter provides an inherent limit to the small-signal. the values of value of the design parameter Vx ? What values are obtained VOL and VOH are ideal. Observe that Q2 operates in saturation at all times. find the values of RC1 and RC2 to obtain a voltage swing of 0. and (ii) the output is high and driving state = 60 μW.4VDD .2 V. and denote kn1 /kn2 by kr . Design the cir- cuit to satisfy the following requirements: VOH = 1.28 An earlier form of logic circuits. VIH . How much i power is drawn from the supply when the output is high? When the output is low? Q2 14. NMH .5 mA. connected as a diode. In terms of VDD . now obsolete.4 V.28. RD . and λ = 0. VOL . and the power dissipation in the low-output PROBLEMS (c) Find the power dissipation in the inverter in the two cases: (i) the output is low.2 V. and λ = 0. What value of voltage gain in the transition D 14. express the best possible noise margins you could expect? Find the the power dissipated in the inverter in its low-output state large-signal voltage gain. (Hint: Use straight-line approximations for If the power dissipation is to be limited to approximately the VTC.24 Design the inverter circuit in Fig. Specify the required values of VDD . If. and the noise margins are within 30% of one Q2 . For a technology 14. 14. utilizes an 0 and VDD . The basic inverter. what W/L ratio is needed and what value of RD corresponds? *14. but VM = 0. what is the required voltage gain of 50 V/V. VIH . IEE = 0. Figure P14. utilized hearing aid can operate down to single-cell supply voltages NMOS transistors only and was appropriately called NMOS of 1. The transistor available has Vt = 0. sketch the VTC. Specify the required values of VDD . and so that the current drawn from the supply in the low-output state is 30 μA. The VDD 2 transistor has Vt = 0. NMH .27 Refer to the analysis of the resistive-load MOS CHAPTER 14 region does your ideal specification imply? inverter in Example 14. and NML . the basic technology used for which Vt = 0.4 V.3VDD .2 V. VM . Also supply? neglect the body effect in Q2 (note that the body of Q2 . NML . Also. forms the load of the inverter. and W/L. Let kn = 500 μA/V . and W/L.2 and utilize the expressions derived there for the various inverter parameters. D = design problem . Assume and NMH can you expect for the lowest possible battery Vt1 = Vt2 = Vt . another.12(a) to provide VOH = 1. P14. μn Cox = 500 μA/V . VOL . If for its inverter. 14. low-frequency to obtain VM = VDD /2. what are the best for VOH . with a 2-V supply. suggest an VIH . what ranges of values of VIL . VIL .28 = Multisim/PSpice. D 14. is connected to ground). shown in Fig.21 For an inverter employing a 2-V supply. VCC = 2 V. RD .26 Refer to the analysis of the resistive-load MOS vI inverter in Example 14. What are the values realized for VOH and VOL ? Q1 D 14. the “gain-of-one” points are separated by less NMOS driver transistor Q1 and another NMOS transistor than 13 VDD . not shown. 1158 Chapter 14 CMOS Digital Logic Circuits VOL = 50 mV. NML .2 V. *** = very challenging. VOL = 50 mV.25 For the current-steering circuit in Fig. Now. VOL .5 V at each output. What are the values obtained for VIL .2 and utilize the expressions derived there for the various inverter parameters.22 For a particular inverter. 2 the maximum fan-out found in (b). the output signals swing between logic. 30 Repeat Example 14.35 There are situations in which QN and QP of the (a) Find Wp that results in VM = VDD /2. the output voltage will be VOH = VDD −Vt .1 VDD is 2 2 hence the average power dissipation in the inverter. and the average power dissipation Pav . (14.3 V.5 V? With ple 14. Vtn = −Vtp = 0.29 For the pseudo-NMOS inverter analyzed in Exam.5. Show that the value required (b) For the matched case in (a). find VIL .8 V. find the current IDD drawn from VDD and while its low-output level does not exceed 0. NML .4 V. IDD .5. find assuming that it spends half the time in each of its two (W/L)n that permits this maximum current to be 0. Figure P14. show relationship is linear and find its slope. (c) For the matched case in (a). In addition. QN and QP have L = 65 nm and (W/L)n = 1.) (the minimum-size case).34 2 and μn Cox = 2.3 and in Exercise 14.5.34 to a 2 (W/L)2 = 15 . A QN 100-mV signal Section 14. estimate the approximate and vO begins to fall.25 μm and (W/L)n = 1. use the vI expression given in Exercise 14. P14.31 Consider a CMOS inverter fabricated in a 65-nm CMOS process for which VDD = 1 V.40) is given by VIH . What is the silicon CMOS inverter are deliberately mismatched to realize a area utilized by the inverter in this case? certain desired value for VM .9 V? 14. and kn = 500 μA/V . Specifically. Find VOH . kn = 500 μA/V .5 V. find the values of VOH .5W n (the matched case). Also. Vt = 0.1-V peak amplitude and resistance of 100 k.2 V.3: The CMOS Inverter 14. region. states. and Vt = 0. reduction in NML and silicon area relative to the matched (c) Find the relationship between vO and vI in the transition case (a). that the maximum current that the inverter can sink (d) If VOL 0 V. and QP have L = 0.. kn /kp = 5. This is the region for which vI > Vt and both PROBLEMS Q1 and Q2 are operating in saturation.3 for a pseudo-NMOS inverter fabricated in a 0. and NMH . VIL . of the parameter r of Eq. For VDD = 1. and (c) Wp = 2W n (a compromise (b) Taking VIL as the value of vI at which Q1 begins to conduct case). Problems 1159 (a) Sketch i–v for Q2 and hence show that for vI low (i.5 V? in VM = VDD /2 = 0. 2 (e) Find numerical values for all the parameters asked for 14.1 mA. and μn Cox = 300 μA/V . sinusoidal signal source having a Thévenin equivalent voltage of 0. what is the value of r that results v I = –1. (b) Wp = Wn a voltage drop of Vt .3VDD .13-μm CMOS technology for which VDD = QP 2 1.e. What 14.5 V is connected as shown in Fig.33 For a technology in which Vtn = 0. For cases (b) and (c). 100 k VOL . Investigate the CHAPTER 14 vI < Vtn ).5 to evaluate VM . D 14. calculate Although Q2 will be conducting zero current.35 V. it will have VM for (a) Wp = 3.5μp Cox = 470 μA/V . (Hint: variation of VM with the ratio Wp /Wn . VOL . Show that the 14.34 A CMOS inverter for which kn = 5kp = 200 μA/V above for the case VDD = 1. (W/L)1 = 5. 0. signal voltage appears at node A with v I = +1. find the output resistance of VM − Vtn r= . |Vt |= 0.065 kn (W/L)n VDD . . VDD − . the inverter in each of its two states. Vtp . 6VDD . In addition.25-μm CMOS process for which VDD = 2. = Multisim/PSpice. 0. QN obtain VM = 0.32 Consider a CMOS inverter fabricated in a For a 0. D = design problem . * = difficult problem.5 μp Cox = 115 μA/V . − VM 14. Vtn = −Vtp = VDD = 1. *** = very challenging. ** = more difficult.4 V.5 V.3 V. find the ratio Wp /Wn required to 2 0. and μn Cox = 3.5 V.13-μm process characterized by Vtn = −Vtp = 0. and μn = 4μp . 39 For the circuit in Fig.8 V. 14.38. let the on-resistance of PU be 2 k and that of PD be 1 k. For kn = 500 μA/V .42 A logic inverter is implemented using the arrangement of Fig. and tP .65 V. At t = 0+. tPHL . V and switch S closes at t = 0. the output node and ground. NML . If the C S capacitance C = 50 fF. PU opens and PD closes—find an expression for (a) Give the expression for vO (t).40.8 V and 14. ** = more difficult. *** = very challenging. 2 C R neglecting λn and λp . let C be charged to 10 assuming the switches operate instantaneously—that is. find the time at which vO vI reaches 1 V. P14. vO = VOL .3 V. at t = 0. C Figure P14.39. 14. (a) Give the expression for vO (t). find tPLH .41 For the inverter of Fig. * = difficult problem.4 V. VOH . 14. 1160 Chapter 14 CMOS Digital Logic Circuits S PROBLEMS 14.4 for a CMOS inverter fabricated in a 0. D = design problem . (b) For I = 1 mA and C = 10 pF.13-μm process for which VDD = 1. In addition. let switch S open R at t = 0. (b) If v I rises instantaneously from 0 V to +1.39 14. P14. P14.40 I 14. find tPHL and tf . VDD = 1. CHAPTER 14 Figure P14. and tPLH .4 V.13 μm and (W/L)n = 1. and NMH . find the value of the peak current. VDD = 1. assuming that a capacitance C is connected between (b) For C = 100 pF and R = 1 k.36 Consider the CMOS inverter of Fig. and μn Cox = 500 μA/V . Hence find the high-to-low = Multisim/PSpice. Find expressions for and QP have L = 0. let vI go from 0. and Vtn = 0.5. (a) Find VOL .18(a) with a capacitance C connected between the output and ground. 14.40 For the inverter circuit in Fig. QN VDD to 0 V at t = 0. of C that ensures that tPLH is at most 100 ps? VDD Section 14.3 V. If R = 10 k. Vtn =| Vtp | = 2 14.4: Dynamic Operation of the CMOS Inverter 14. (W/L)n = 1.5. For part (a) use VOH .38 and VIL = VIH = VDD /2.37 Repeat Example 14. v O (t).22 with QN and QP matched and with the input v I rising slowly from 0 to VDD . Figure P14. vO (t).38 For the circuit shown in Fig. what is the largest value VM = VDD /2 = 0. At what value of v I does the current flowing through QN and QP reach its peak? Give an expression for the peak current. μn = 4μp .18 with switches having Ron = 2 k. tPLH .45. It is (b) If when an external capacitive load of 0. the velocity saturation reduces the current significantly. VDD = 1. one? Use the method of average current. tPLH = tPHL . = Multisim/PSpice.5 pF is added required that for C = 10 fF. and the capacitance is roughly 4 fF/μm of device width plus 2 f F/device. by what factor do you estimate parasitics. Calculate the V.8 V to 0 V. * = difficult problem. Also. 14. Two such inverters are connected in tandem and driven 65-nm process for which Vtn = |Vtp | = 0. tPLH does not change. What is the capacitance at the inverter output node is 10 fF. kn = 4kp = 14.52 Find the propagation delay for a minimum-size 2 2 430 μA/V .2 V. tPHL . and tP ≤ 50 ps. and having (W/L)n = 1. to be 0. and the component due to the input of the load the current reduction to be in the NMOS transistor? Since inverter.4 V. (a) If the current available to charge a load capacitance is half as large as that available to discharge the capacitance. (W/L) ratios so that tP ≤ 80 ps. tPLH .13-μm technology. find inverter for which kn = 4kp = 380 μA/V and (W/L)n = tPHL .48 Use the method of equivalent resistance to determine PROBLEMS loaded by a similar circuit.2. 30 ns.44 Consider an inverter for which tPLH .45 For a CMOS inverter fabricated in a 0. 14. 10 ns. D 14. its propagation delays increase by 50%. and μp Cox = 190 μA/V . and the total for (a) a rising input and (b) a falling input. *** = very challenging.1 pF. As will be seen in Section 15. fF. that is.35 V.47 For the CMOS inverter in Exercise 14. If C = 30 fF. and hence method of equivalent resistance to determine tPHL . the standard inverter. The time taken for the output voltage to complete its excursion inverter has (W/L)n = 1. and similarly for tPHL . what do you conclude about the *14. Most of this discrepancy is due to the load inverter is removed and the propagation delays fact that the formula we derived for Iav does not take into were observed to decrease by 40%.27 μm/0.6. estimate the two account velocity saturation. and tP of a CMOS inverter fabricated in a tTHL . μn Cox = 470 μA/V .13-μm process specified in Problem 14. and 15 ns. and tP . what do you estimate the normal combined 14. Using component due to the inverter output and other associated the results in Example 14. (c) Repeat (b) for v I falling instantaneously from +1. find the propagation delay for the inverter? theoretical maximum frequency at which this inverter can be operated.13-μm technology. find tPLH and tTLH . tPLH . has a propagation delay specified the propagation delay of a minimum-size inverter.43 In a particular logic family.1. tTLH . D 14. The equivalent load capacitance C = 20 fF.9 ns: one for which (W/L)n = (W/L)p = 1. for simplicity. Find an expression for v O (t). Problems 1161 propagation delay (tPHL ) for C = 0. at the inverter output. 14.5 V. when 14. respectively. and effect of velocity saturation on the PMOS transistor in this tTHL are 20 ns.5 and (W/L)p = 3.5-pF load connected. and tP when the equivalent load capacitance C = 10 (W/L)p = 0. D = design problem . The rising technology? and falling edges of the inverter output can be approximated by linear ramps. Also find tTHL CHAPTER 14 use the method of average currents to determine the required (see Fig. Vtn = −Vtp = 0. Again assume that PD opens and PU closes 14.13-μm process with VDD = 1. we define tTLH to be 0% 14. designed in a 0.50 The method of average currents yields smaller values capacitance of inverter output and input to be? for tPHL and tPLH than those obtained by the method of (c) If without the additional 0. components of the capacitance found in (b): that is.8 V. Vtn = –Vtp = 0. There is an additional load capacitance of 5 fF. ** = more difficult. Also.49 Use the method of equivalent resistance to design what do you expect tPLH and tPHL to be? an inverter to be fabricated in a 0. Use the method of average currents.51 Use the method of average currents to estimate to 100% (rather than 10% to 90%) rise time.46 Consider a matched CMOS inverter fabricated in What does tP become if the design is changed to a matched the 0.18 μm.29).5 and (W/L)p = 3. the equivalent resistances. VDD = 1 2 2 by an ideal input having zero rise and fall times.11 use the instantaneously. and VDD = 3. though it uses additional transistors. to the values obtained when all n-channel devices have W/L = n and all p-channel devices have Wp C = Cn 1 + + Cw W/L = p. including that of selection of the ratio Wp /Wn on the propagation delay of an the required inverters? inverter driving an identical inverter.58 Consider a four-input CMOS NAND gate for which (a) Noting that except for Cw each of the capacitances in the transient response is dominated by a fixed-size capacitance Eqs. μp Cox = 45 μA/V. For how much additional capacitance load What do you conclude about the selection of Wp /Wn ? does the propagation delay increase by 50%? D 14.20 μm/0. The circuit in (W/L)n = 1.7 f F/μm. μn Cox = 180 μA/V.56 Consider the CMOS gate shown in Fig. Fig. 14.10(b). has in fact less total area and lower propagation delay because 3 it uses NOR gates with lower fan-in. has been found to have a propagation delay of 80 ps. If the inverter is driving another identical inverter.59) is proportional to the width of between the output node and ground.60 Consider the two-input CMOS NOR gate of Fig. as in Fig. 14.59 Figure P14. ** = more difficult.9. Section 14. Wn where Cn is determined by the NMOS transistors. find the number of transistors and Wp /Wn the total area of each circuit. 14. show that for the OR function of six input variables. Assume all transistors have the same L. 14. tPHL . 14. and inverter. respectively.13 μm and a (W/L)p ratio of (c) Use the results of (a) and (b) to determine tP in the case 0. 14.40 μm/0. By what D 14.59(b).40 μm/0. Compare the values the relevant transistor. show that C can be expressed as of tPLH and tPHL . (14.32. *** = very challenging.0 f F.35. such that the worst-case 14.55 In this problem we investigate the effect of the 0. and tP .13 μm and (W/L)p = D *14. 14.7 × 10 tPLH = C basic matched inverter.4 (ii) Cw Cn f F and 1.75 μm and (i) Cw = 0 Ln = Lp = 0. Assume the basic inverter to have a (W/L)n ratio of 0.20 μm/0. The overlap capacitance and the effective drain–body capacitance per micrometer of gate width are 0. uses Wn = 0. whose transistors are properly sized so that the current-driving = Multisim/PSpice.58) and (14.5 μm.5: Transistor Sizing Specify W/L ratios for all transistors in terms of the ratios n and p of the basic inverter. P14.3 V.57 Find appropriate sizes for the transistors used in factor must (W/L)n and (W/L)p be increased so as to reduce the exclusive-OR circuit of Fig. in terms of Cn and Cw . when Wp /Wn is selected to yield tPHL = t PLH .13 μm. The wiring capacitance is Cw = 2 f F. 1162 Chapter 14 CMOS Digital Logic Circuits PROBLEMS 14. find CHAPTER 14 tPLH . * = difficult problem. D = design problem . 45 fF contributed by the wiring and other external circuitry. Assuming that the tPHL = 8.54 An inverter whose equivalent load capacitance C is tPHL and tPLH of the gate are equal to those of the basic composed of 15 fF contributed by the inverter transistors. What is the total area.7 case: that is. Wp = Wn .625 × 10 C transistors in both circuits are properly sized to provide each 3 gate with a current-driving capability equal to that of the 20. cases: Vtn = – Vtp = 0.13 μm. (d) Use the results of (a) and (b) to determine tP in the matched *14. obtained when the devices are sized as in Fig.53 A matched CMOS inverter fabricated in a process for (e) Compare the tP values in (c) and (d) for the two extreme 2 2 2 which Cox = 3.59 shows two approaches to realizing (b) Using the equivalent resistances RN and RP .7 V. Assume that the tP to 40 ps? By what factor is the inverter area increased? basic inverter has (W/L)n = 0. 59 capability in. Problems 1163 A1 CHAPTER 14 Y A1 A2 … A6 … A6 (a) A1 A2 PROBLEMS A3 Y A1 A2 … A6 A4 A5 A6 (b) Figure P14. each . For . direction is equal to that of a matched (b) Differentiate the expression for tP in (a) relative to x inverter. Vt . to charge and discharge the load capacitance. = 1 V and VDD = 5 V.62 The purpose of this problem is to find the values of is found to have a load capacitance of 10 fF. Thus show that the second C is the input capacitance of the standard inverter (which is condition for optimality is the first in the chain).37(c). n CL Neglect the body effect in QPB . If the IC chip has 2 million of these inverters operating at an average switching (a) Show that frequency of 1 GHz.8-V power supply. where set the derivative to zero. what is the number of inverters and the value of x that result in minimizing the total path delay tP ? What Section 14. *** = very challenging. find the gate threshold and set the derivative to zero. what is the power dissipated in the 1 chip? What is the average current drawn from the power tP = τtotal = (n − 1)xRC + n−1 RCL x supply? = Multisim/PSpice. If the inverter is n and x that result in minimum path delay tP for the inverter operated from a 1. D = design problem . x = C 14. Thus show that the first in the cases for which (a) input terminal A is connected to condition for optimality is ground and (b) the two input terminals are tied together. (a) Without increasing the number of inverters in the chain. find the energy needed chain in Fig. where R is the output resistance value of x for minimum overall delay is of the standard inverter.18-μm CMOS process 14.61 A chain of four inverters whose sizes are scaled by a (c) Differentiate the expression for tP in (a) relative to n and factor x is used to drive a load capacitance CL = 1200 C.6: Power Dissipation is the value of tP achieved? 14.63 An IC inverter fabricated in a 0. ** = more difficult. (b) If you are allowed to increase the number of inverters in x=e the chain. n C x = ln x find the optimum value of x that results in minimizing the CL overall delay tP and find the resulting value of tP in terms (d) Combine the expressions in (b) and (c) to show that the of the time constant CR. * = difficult problem. 14. . It is found.64 Consider a logic inverter of the type shown in Fig. * = difficult problem. By what tP 0.66 A collection of logic gates for which the static power tPHL as dissipation is zero. (a) Show that if v I changes instantaneously from high to low and assuming that the switch opens instantaneously. ** = more difficult. to obtain a D *14. 14.5 V. If current is (a) 2 where τ1 = CR. R should be in a value for R.69 A logic-circuit family with zero static power the output voltage obtained across a load capacitance dissipation normally operates at VDD = 2.65 In a particular logic-circuit technology.67 A particular logic gate has tPLH and tPHL of 30 ns and 2 1 VDD 50 ns. show that. Hence show that the time required for proportional to VDD or (b) proportional to VDD . 1164 Chapter 14 CMOS Digital Logic Circuits (b) Following a steady state. and the dynamic power dissipation is 10 mW is operating at 50 MHz with a 5-V supply.17(c). (e) Now that the trade-offs in selecting R should be clear. Let VDD = 1 V. Estimate the equivalent capacitance at the output node of the inverter. Hence show a 3. Then determine the resulting values of tP and P.3/5). value for R.6 mW with output high.8 V is considered. determine the dynamic power exponentially according to dissipation. however. D = design problem . we wish to determine the dissipation no greater than 15 mW.69CR in each case? = Multisim/PSpice. operating with where τ2 = C R Ron CRon for Ron R. operation at 1.35CR for Ron R fraction could the power dissipation be reduced if operation at 3. what logic-0 state and half the time in the logic-1 state. is in maximum operating frequency do you expect in each case? What fractional change in delay–power product do you expect tPLH = 0. what reductions v O (t) to reach the 50% point.18. Selection of a suitable value for R is determined by specific range. If the inverter circuit in Fig. the additional power can be saved? average static power dissipation is 14. Find that range and select an appropriate two considerations: propagation delay and power dissipation. the basic inverter draws (from the supply) a that the time for v O (t) to reach the 50% point is current of 60 μA in one state and 0 μA in the other. 21 VOH + VOL . 14.69CRon current becomes 150 μA. 14.3-V supply. In particular. *** = very challenging. When the inverter is switched at the rate of 100 MHz. for VDD = 5 V and C = 10 pF. and let a 5-fF capacitance be that the switch closes immediately and has the equivalent connected between the output node and ground.3 V were possible? If the frequency of operation is reduced (d) Show that for an inverter that spends half the time in the by the same factor as the supply voltage (i. (c) Use the results of (a) and (b) to obtain the inverter propagation delay. show that the output falls is switched at the rate of 2 GHz. What is the average current drawn from the dc power supply? v O (t) = VOL + VOH − VOL e−t/τ2 CHAPTER 14 14. that the currents available to charge and v O (t) = VOH − VOH − VOL e−t/τ1 discharge load capacitances also decrease. the average supply tPHL = 0. defined as the average of tPLH and 14. respectively. and dissipates 1 mW with output low P= 2 R and 0. 3. Calculate the corresponding delay–power product (under the assumption of a 50% duty-cycle signal and neglecting dynamic power dissipation).17(a). if v I goes high and assuming PROBLEMS 14. D 14.e.68 We wish to investigate the design of the inverter propagation delay no greater than 5 ns and a power shown in Fig. To reduce its C will be dynamic power dissipation. ** = more difficult. *** = very challenging. PROBLEMS = Multisim/PSpice. Let the input rising and falling edges be the height equal to Ipeak . Refer approximated by a triangle with a base corresponding to the to Fig. 14. D = design problem . Problems 1165 CHAPTER 14 14.39 and let Vtn = −Vtp = 0. and time for the rising or falling edge to go from Vt to VDD −Vt . assume that the current pulse can be and QP when the input pulse has finite rise and fall times. and 2 kn = kp = 450 μA/V . * = difficult problem. determine the power dissipation linear ramps with the 0-to-VDD and VDD -to-0 transitions taking that results when the inverter is switched at 100 MHz.8 V. Also. VDD = 1. To determine the energy drawn from the dissipation resulting from the current pulse that flows in QN supply per transition. Find Ipeak .5 V.70 In this problem we estimate the CMOS inverter power 1 ns each. D = design problem . and depending on the The ECL gate provides two complementary outputs. If the effective values of μn and μp are 350 cm /V · s and = Multisim/PSpice.13-μm process to a 65-nm values of Ecr for both device polarities. 0 to VDD . It achieves its high speed Pseudo-NMOS has the disadvantage of dissipating static of operation by avoiding transistor saturation and by power when the output of the logic gate is low. Static utilizing small logic-signal swings. pseudo-NMOS is a ratioed Domino logic. allows the cascading of dynamic logic form of logic in which VOL is determined by the ratio r of gates. ** = more difficult. known as the precharge pation. it Pseudo-NMOS utilizes the same PDN as in standard has an almost constant on-resistance over the full output CMOS logic but replaces the PUN with a single PMOS range. What do you esti- mate the effective values of μn and μp to be? Also find the 15. 2 device dimensions (S = 2). to charge the capacitance at the output node to applications.45 V. pseudo-NMOS and pass-transistor logic connection of an NMOS and a PMOS transistor. are employed in special applications as supple. find the factor by which tP . PROBLEMS Section 15. process.13-μm CMOS process. which limits its application to highly specialized interval. namely. This is the essence of gates can be wired together to realize the OR function of dynamic logic. passes the entire input signal swing. 15. the output node either remains high realizing the OR and NOR functions. limited its use to specialized applications. two other forms of static The CMOS transmission gate. power density. The outputs of ECL or is discharged through the PDN.2 Consider the scaling from a 0. It ments to standard CMOS. result in the reduction of VOH processing complexity (over that required for CMOS) has from VDD to VDD – Vt . known as on. process of the late 1970s contains 20.4 Consider NMOS and PMOS transistors with minimum (a) Assuming VDD and Vt are scaled by the same factor as the channel length fabricated in a 0. Normally.25 V and that for 2013? minimum-length PMOS devices 0.3 For a 65-nm technology. What does Moore’s law predict the number of transistors to be on 15. r is selected in the range of 4 to 10 Emitter-coupled logic (ECL) is the fastest commercially and its value determines the noise margins. VDD . Then the inputs are applied. is a very (PTL). kn to kp . Its high speed of power can be eliminated by turning the PMOS load operation is achieved at the expense of large power dissi- on for only a brief interval. though simple. However. transistor whose gate is grounded and thus is permanently A particular form of dynamic logic circuits.1: Implications of Technology the maximum operating speed. VDSsat for minimum-length a chip of equal area fabricated using the 32-nm process of NMOS devices is measured to be 0. the individual output variables. Pass-transistor logic utilizes either single NMOS tran- sistors or CMOS transmission gates to implement a BiCMOS combines the low power and wide noise margins network of switches that are controlled by the input of CMOS with the high current-driving capability (and logic variables.1 A chip with a certain area designed using the 5-μm unchanged. * = difficult problem.000 transistors. As well. available logic-circuit family. Pdyn . *** = very challenging. and Scaling: Issues in Deep-Submicron Design PDP decrease (or increase)? (b) Repeat (a) for the situation in which VDD and Vt remain 15. input combination. effective switch in both analog and digital applications. the added transistors. composed of the parallel CMOS. Problems 1227 To reduce the device count. Unlike standard CMOS. Switches implemented by single NMOS thus the short gate delays) of BJTs. λ = 0.25 V.9 Measurements on a MOSFET operating in the sub- obtained if velocity saturation were absent is given by threshold conduction region indicate that the current changes by a factor of 10 for every 80-mV change in vGS and that CHAPTER 15 1 2VDSsat VDD − Vt − VDSsat iD = 20 nA at vGS = 0.35 V.8 The current IS in the subthreshold conduction −V /nV (b) Eq. as ohms/square or / (refer to Fig. capacitance. Vt = 0.25 V. The quantity ρ/T is called the sheet resistance and technology characterized by VDD = 1.5 × 10 L tPHL = 0. what is the expected variation in delay time.69C R=ρ = (W/L)n A TW (c) If the formulas in (a) and (b) are to yield the same where ρ is the resistivity of the material of which the wire result. a width W.16 V. for a reduction in Vt by 0. *** = very challenging. VDD = 1.6 (a) Consider a CMOS inverter fabricated in a 2 deep-submicron technology utilizing transistors with the 15. This canbe achieved by making IDsat of QN equal W to IDsat of QP at v GS = VDD . load capacitance C. VDSsatn = 0. range of ID obtained? Ignoring channel-length modulation. and a thickness T has a resistance R given by (b) Using the equivalent resistance of QN show that ρL 3 12. by what factor will Figure P15. and drawn from the 1-V supply VDD as a result of subthreshold VDD = 1.11a). conduction. Show that Wp /Wn is given by T L 1 Wp μn VDSsatn VDD − Vtn − 2 VDSsatn (a) = Wn μp VDSsatp 1 VDD − Vtp − VDSsatp R 2 (b) Find the required Wp /Wn for a 65-nm technology for which μn /μp = 4.0 V. Hence.4 mA/V and a minimum allowed channel length and having an equivalent nominal Vtn of 0.2 mA. and (b) If the transistor is used to discharge a 100-fF load assuming QN operates in the velocity-saturation region. Let v I rise instantaneously to VDD and (a) If Vtn can vary by as much as ±10%. * = difficult problem. Vtn = −Vtp = 0. the ratio of the current IDsat obtained at v GS = VDD to the current 15.7 (a) For a CMOS inverter fabricated in a deep-submicron technology with Ln = Lp = the minimum W Square allowed channel length. Repeat for both device polarities.11 = Multisim/PSpice.4 V.1 V? CVDD tPHL = 2IDsat 15.2 V.1 V. respectively. that is. C and VDSsatp = 0. Vt = 0. D 15. ** = more difficult.0 V.5 (a) Show that for a short-channel NMOS transistor.13) is proportional to e t T . D 15.45 V. 15.2 V. (15. find the expected values of VDSsat the static power dissipation increase? Assume n = 2. find the current process with L = 65-nm. find VDSsat for the NMOS transistor for a 0. P15. show that assuming that the output voltage is to change by 0. What do you conclude about the selection of a value of Vt in process design? 15. estimate the resulting static power dissipation. (b) Find the ratio in (a) for a transistor fabricated in a 65-nm (b) For a chip having 1 billion transistors.13-μm is made. 1228 Chapter 15 Advanced Topics in Digital Integrated-Circuit Design PROBLEMS 2 150 cm /V · s. VDSsat = 0. D = design problem . and 2 has the dimension of ohms.35 V. If the threshold voltage of an NMOS transistor is reduced by 0.4 V is to operate in saturation at ID = 0.11 An interconnect wire with a length L. it is required to select Wp /Wn so that tPHL = tPLH . what is the expected assume that QP turns off and QN turns on immediately.10 An NMOS transistor with kn = 0. IDsat 2 = 2 ID VDD − Vt (a) Find the value of iD at vGS = 0. although it is usually expressed μn Cox = 325 μA/V . and VDD = 1. For a fair comparison. kn = 4kp = 400 μA/V .5 μm wide. Use your percentage reduction obtained when a current-source load is table and iteration to determine the value of r that results in used. 2 2 process and having kn = 5kp = 500 μA/V .13. which 15.17 Use Eq.15 Find tPLH .13 For a pseudo-NMOS inverter fabricated in a 0. Hence. ** = more difficult. tPHL .1 V.) (P. P15.S. if the sheet resistance is specified to be 15. VOH . and NMH . VIL .13 when loaded with C = 10 fF. VOH .5 V.13-μm D 15. What is the value of (W/L)n ? Calculate the the static power dissipation in the low-output state. and Isat . find VOL . P15. Only PROBLEMS 2 2 a small fraction of the interconnect on an IC would be this 115 μA/V . Vtn = −Vtp = 0. values of NML and the static power dissipation.4 V. obtained with a current-source load [see Fig. and NML ? *15. VM . let the current source I = VDD /RD . Let VDD = 1.3 V and Vt = 0. and hence the r. VIL . Problems 1229 CHAPTER 15 (a) Find the resistance of an aluminum wire that is 5 mm long 15. NML .5 V.12(a)] to that and 10.12 The purpose of this problem is to compare the value of not change very much with r by evaluating NML for r = 2. D = design problem . Let VDD = 1. and (W/L)n = 1. NMH . Vt = 0. * = difficult problem.4 V. tPLH obtained with a resistive load [see Fig. 27 m /. VM .18 For what value of r does NMH of a pseudo-NMOS is the initial current available to charge the capacitor in the inverter become zero? Prepare a table of NMH and NML versus case of a resistive load.5. 5. find and (W/L)p = 1. *** = very challenging. specified in Problem 15. NML = NMH . What is the resulting margin? 15.8 V.16 Design a pseudo-NMOS inverter that has equal circuit as shown in Fig.26) to find the value of r for which NML Section 15. VOL . VOL . kn = introduced by the wire. for r = 2 to 10. 15. What are the long!) values of (W/L)p .5 V.3: Pseudo-NMOS Logic Circuits is maximized. VIH .12 = Multisim/PSpice.1 fF/μm length. What is the corresponding value of NML for the case VDD = 1.3 V and Vt = 0. Vt = 0. find the delay time capacitive charging and discharging currents at v O = VDD /4 for use in a system with VDD = 2. (15. VIH .19 Design a pseudo-NMOS inverter that has VOL = 0. kp = 30 μA/V . find VOH . (Hint: tdelay = 0.14 For the pseudo-NMOS inverter specified in Problem and 0. Find tPLH for each case.3 V. P15.4 V ? Show that NML does 15.69RC. what is the total wire capacitance? (c) If we can model the wire very approximately as an RC D *15.12(b)].11(b). VDD VDD RD I vO vO vI vI vI QN C vI QN C VDD VDD 0 0 0 t 0 t (a) (b) Figure P15. and tP for the pseudo-NMOS inverter (b) If the wire capacitance to ground is 0. 24 This problem investigates the effect of velocity satu- pseudo-NMOS inverter with equal high and low noise ration (Section 15. tPHL . Let for their values. ** = more difficult.13-μm CMOS process for which 2 2 0. P15. Consider the case with v I = VDD and v O = Specify the values of (W/L)n and (W/L)p . What is the static VOL . At what frequency of operation would the static and dynamic Section 15. find tPLH . voltage is the drain. Note that QP will be operating in the velocity-saturation CHAPTER 15 power dissipated in this gate? What is the ratio of propagation region. 1230 Chapter 15 Advanced Topics in Digital Integrated-Circuit Design PROBLEMS D *15. and give expressions find (W/L)p so that the worst-case value of VOL is 0. D = design problem .4 V.5.25 = Multisim/PSpice.3 V.22 Sketch a pseudo-NMOS realization of the voltage is the source. exclusive-OR function Y = AB + A B. For each of the circuits in Fig. the terminal with the higher D 15. and tP . It is required to |Vtp | are determined by the body effect. and |Vtp |. delays for low-to-high and high-to-low transitions? For an equivalent load capacitance of 100 fF. and kn = 4kp = 500 μA/V .7 and show that NML NMH . Use r = 5. Vt = 0.4: Pass-Transistor-Logic Circuits power levels be equal? Is this speed of operation possible in 15. Vt = 0. the terminal with the higher Y = A + B(C + D).1. Note that Vtn and which the NMOS devices have (W/L)n = 1. Note that VO is the value reached after the VDD = 1.4 V.25 Recall that MOS transistors are symmetrical and that view of the tP value you found? what distinguishes the source from the drain is their relative D 15.3) on the operation of a pseudo-NMOS margins using a 1. |VDSsatp = 0.3 V.1 V. for PMOS.4 V. * = difficult problem. and the minimum-size device VDD = 1.23 Consider a four-input pseudo-NMOS NOR gate in voltage VO in terms of VDD . kn = 5kp = 500 μA/V .21 Sketch a pseudo-NMOS realization of the function voltage levels: For NMOS.3-V supply and devices for which Vt = inverter fabricated in a 0.6 V. label the source and drain terminals and give the output D 15. and has (W/L) = 1.25.20 It is required to design a minimum-area 15. kn = 4kp = 500 μA/V . Find its current IDsat and use it to determine VOL . Vtn . 2 capacitor charging/discharging interval has come to an end. *** = very challenging. VDD 0V VO VDD VO C C (a) (b) VDD VDD VO 0V VO C C (c) (d) Figure P15. For this value of Y VOH .31 Figure P15. what is the final value VOH reached at the output? A B VDD Y X vI vO A B Q C (b) Figure P15. VDD = 1. and do complex logic functions. If the output of the switch is connected to the input of a CMOS Correspondingly.2 μm/0. VDD = 1. *15.8. express Y as a function of A and B.32 = Multisim/PSpice. what is the final value VOL reached at the output? (c) For the situation in (a).5 and fabricated in a CMOS process 1/2 for which Vt0 = 0. transistor having W/L = 1. Determine tPHL for the case C = 10 fF. Let kp = 125 μA/V . Find tPLH for the case C = 10 fF. v I is raised to VDD .26 Let the NMOS transistor switch in Fig.32 A designer. 2φf = 0.13-μm (a) that a string of minimum-size single MOS transistors can CMOS process for which Vt0 = 0. ** = more difficult.17 with the NMOS |Vtp = 0. 2 μn Cox = 500 μA/V . * = difficult problem. D = design problem .5 V .4 V. γ = 0. Let μn Cox = 4 μp Cox = look familiar? If in each case the terminal connected to VDD 2 300 μA/V . CHAPTER 15 15.27 Consider the circuit in Fig. Problems 1231 (b) If initially v O = VDD and at t = 0.17 be fabricated in a 0. 2 0 to VDD /2. 15. v I is lowered to 0 V. what inverter static current results? Estimate tPLH and tPHL for this arrangement as measured from the input to the A B output of the switch itself. (a) (a) If initially v O = 0 and at t = 0.4 V. respectively. For each. (b) but that there must always be a path between output and a supply terminal.6V. what can be said about general operation? About when the inverter input is at the value found in Exercise 15. μn Cox = 3μp Cox = 75 μA/V . evaluate the switch VOH and X VOL for inputs at VDD and 0 V. A B drives a 100-f F load capacitance at the input of a matched standard CMOS inverter using (W/L)n = 1.2 μm/0. 2φf = 0. find tPLH for v O to rise from 1/2 γ = 0.88 V. pass-transistor logic. 2φf = 0.8 V. beginning to experiment with the idea of 2 and μn Cox = 500 μA/V .31 Figure P15.28 Consider the circuit in Fig.31 shows a PMOS transistor operating as a switch in the on position.2 V.8 μm. 15. what does the function Y 15.8 μm.3-V system for which Vt0 = 0.2 V. 1/2 2 γ = 0.2 V . 15. 15.5 and fabricated in a 0. VDD = 1.2 V .29 Consider the case specified in Exercise 15. P15. Determine VOH .2 V. find Fig.18 μm.54 μm/0. In the static current of the inverter and its static power dissipation each case. *** = very challenging.18 with the NMOS transistor having W/L = 1. For VDD the switch gate terminal at VDD . the logic levels at Y ? About node X ? Do either of these circuits Also find the inverter output voltage.13-μm CMOS process for which Vt0 = 0. and 15.30 An NMOS pass-transistor switch with W/L = become? 1. is instead connected to the output of a CMOS inverter whose input is connected to a signal C. seizes upon what he sees as two good PROBLEMS ideas: 15.88 V. used in a 3. he first considers two circuits (shown in inverter having (W/L)p = 2(W/L)n = 0.32).4 V.2 V. 15. and VDD = 1.4 V.8. 15.4 for the capacitor-charging case. its current subtracts from the current of Q1 .8 μm. iDP tPHL . 15. vO1 rises to VDD . find iDN (0).40 = Multisim/PSpice. and with ground and VDD connections interchanged.33 Consider the circuits in Fig. |Vt0 |= 0. Use the average of those values the capacitor-charging current available at this time (i.8 V. Consider the case when all the transmission that Q1 conducts at this value of vO1 . (15. iDP tPLH . reducing the current available to 15. For this purpose consider the circuit of RTG and use it to determine tPHL for the case C = 15 fF. on.69 kCRTG is fabricated in a CMOS process technology for which kn = k=0 1 2 3 n vI vO C C C C VDD 0 t Figure P15.21(b).6 μm/0.19 is determined. Let QN and QP have (W/L)n = (W/L)p = 1. This is VIH = 18 (5VDD − 2Vt ). Vt0 = 0. show that the value of vO1 that causes vO2 to drop by a threshold voltage below VDD (i.21(a) and 15. as specified in Problem 15. iDP (0). Meanwhile. (W/L)1 = (W/L)n = 1. 1232 Chapter 15 Advanced Topics in Digital Integrated-Circuit Design 2 PROBLEMS 4kp = 500 μA/V . and all NMOS by PMOS. 15.2 μm/0. What do The total capacitance at the output node is 15 fF. and Q1 charging C and causing vO1 to (d) Find tP . As QR conducts. Now. (c) For the situation depicted in Fig.19. and C = 20 fF.3 V. find the current multiplexers.4 V..40 shows a chain of transmission gates. and tPHL . discharge C. γ = 0. prior to QR turning on)? What is it at vO1 = 0? What is the average current available for charging C? Estimate the time *15. What is find RTG at v O = 0 and 0.. CHAPTER 15 2 1/2 3kp = 75 μA/V .5 V .5 V) so that QR turns 15.e. and VDD = 1.36 The transmission gate in Fig. iDN tPHL . * = difficult problem.8 μm.32 with all PMOS transistors replaced with NMOS.36. (W/L)p = iDP (0). Evaluate the D *15. *** = very challenging. consider the situation when vA is brought down to 0 V and Q1 conducts 15. Then. Find the value of vO1 at which the inverter begins This situation often occurs in circuits such as adders and to switch.e. VDD = 3.40 Figure P15.2 V.38 Refer to the situation in Fig. find iDN (0). Find the average value Fig.37 For the transmission gate specified in Problem 15.88 V. vO2 is still low and QR is conducting circuit for which C = 10 fF.4. The propagation delay tP can be determined from the value of the current in Q1 . to 2. rise.5. Calculate the estimate of RTG and hence of the propagation delay tP . and tPLH .34 For the level-restoring circuit of Fig. 2φf = 0. just to determine tPLH for the situation in which C = 15 fF.21(b). 15. At what value of v O 3.) sions for RNeq .34 and let vB = VDD .6 V. Also let vB = VDD . P15. discharge current at t = 0. Derive expres- tPLH .13-μm CMOS technology and used in a from VDD .35 The purpose of this problem is to illustrate how value of RTG for v O = VDD and v O = VDD /2 for the process W/L of the level-restoring transistor QR in the circuit of technology specified in Problem 15. What is the W/L you have chosen? Elmore delay formula as follows: Estimate tPHL as the time for vO1 to drop from VDD to VIH . 15. 15. and RTG following the approach used in Section 15. the current in QR is zero). 1/2 15. Use Eq. 15.5 and begins to discharge C.39 A transmission gate for which (W/L)n = (W/L)p = 1.21(b) n tP = 0. 15. RPeq . (Note that after QR turns on. let k = n iDN tPLH .21(a).36. is approximately VDD /2 and thus occurs at t tLH . γ = 0.49) to obtain an (though at t = 0. the output functions Y become? (a) What are the values of VOH and VOL ? (b) For the situation in Fig.2 V . D = design problem . 2φf = 0. ** = more difficult. The voltage vO1 will begin to drop is fabricated in a 0. Now will QP turn off? for vA rising to VDD .6 V. Choose W/L for QR so gates are turned on and a step voltage VDD is applied to the that the maximum current it conducts is limited to one-half the input. and VDD = 1. That is.5 V. the latter two with two inputs. D = design problem . Fig. 15. turning Q1 on.9 n(n + 1) tP = 0. 15.26 to realize Y = AB + A B. and simultaneously the voltage at the gate D 15. If the precharge interval is much shorter than the (b) Now combine the circuit obtained in (a) with the circuit maximum allowable evaluation time. Calculate the rise time of vO . and D 15. Note that Z is a *15. Also.4. What does the value of tP become 15. and n is the VDD = 1. even if the PDN is not conducting. Assume that the allowed.46 For the gate specified in Problem 15. v Y = VDD . 15.27. For CL = 10 f F. and neglecting NMOS devices are used for which W/L = 1. defined as the time for v Y to rise from 10% to 90% 0.2 V. Transistor Q1 will to form Z = ABC and Z = ABC = A + B + C. from 0. and assume that at t = 0.45 In this and the following problem. minimum-size (d) For Vtn = 0.8 V. capacitance CL is found to be 15 f F. the dynamic logic form and fabricated in a CMOS process (c) Find an expression for the maximum ratio (C1 /CL ) for 2 technology for which kn = 4kp = 500 μA/V . Sketch the complete 12-transistor circuit realization of Z.2 V. The PMOS precharge transistor Qp has W/L = 3.30(a). Vt = 0. ** = more difficult. we investigate the (b) For each of the two situations. NAND.49 In this problem.51 For the four-input dynamic logic NAND gate analyzed 15. Derive an expression for the drop in the output voltage. find time if the decay in output voltage is to be limited to a realization for Y using two transmission gates. we wish to calculate the reduction in three-input exclusive-OR. = Multisim/PSpice.28. tPHL . 0.47 Consider a two-input NOR gate realized in the in Example 15.5 (this includes the body effect in Q1 . number of transmission gates in the chain. *** = very challenging. * = difficult problem. In Section 15.45. 15. Calculate the rise time of the output Qeq1 and Qeq2 to be identical with threshold voltages Vtn = voltage. Vtn = −Vtp = which v Y ≤ Vtn .2 V. Y C + Y C where C is a third input.2VDD and transconductance parameters kn .4 V. by equating the charge gained by C1 to D 15. v Y ≤ Vtn . E15. CL = 15 f F.41 (a) Use the idea embodied in the exclusive-OR −12 Ileakage = 2 × 10 A. sketch a that at t = 0−. Now evaluate tP for the case of 16 transmission gates with PROBLEMS RTG = 10 k and C = 10 fF. The total capacitance at the output is found to be 15 fF. 15. The in the two cases: (a) C1 = 4 f F and (b) C1 = 7.1 VDD to 0.15 and assume CL is fully discharged. calculate the worst-case 2 value of tPHL . find the drop in voltage at the output Qe ). derive an expression for dynamic operation of a two-input NAND gate realized in v Y . the final value of v Y can be found using charge conservation: that is. VDD = 1. and v C1 = 0.15 symbolically operation with the gate of Qp at 0 V. high-to-low propagation delay. Also. remain conducting until either the voltage at its source (v C 1 ) reaches VDD – Vtn or until v Y = v C1 .44 Based on the basic dynamic logic circuit of the charge lost by CL . φ goes high CPL circuit whose outputs are Y = AB+AB and Y = AB+A B.5. Refer to the circuit in Fig. Consider the precharge 15. and the PMOS transistor of the series in this formula is given by has W/L = 3. and a circuit for (a) Convince yourself that the first situation obtains when which Y = AB + CD. and μn Cox = 4 μp Cox = 500 μA/V . Refer to Fig. in the precharge interval. 15. 15. 15. 15.27 to three variables of Q1 goes high (to VDD ). and assume D *15. find the longest allowable evaluation realization in Fig. the output voltage of a dynamic logic gate as a result of charge redistribution. evaluate the v Y2 . 0.5: Dynamic MOS Logic Circuits both cases. CL2 .28. (rather than numerically).42 Using the idea presented in Fig. and NOR gates. Note that the sum The NMOS devices have W/L = 1. C is gate is fabricated in a 0. estimate the maximum clocking frequency dynamic logic form illustrated in Fig.13-μm CMOS technology for which 2 the capacitance between each node and ground. sketch complete circuits for NOT.4 V.50 Solve the problem in Exercise 15. whichever comes first. find the minimum in Fig. 15.43 Extend the CPL idea in Fig. and QP turns off. At t = 0. To keep CL small.5 f F.2 V. let CL1 = of the final value of 1. Problems 1233 CHAPTER 15 where RTG is the resistance of each transmission gate.26 to obtain a realization of the function Z = clocking frequency required.48 The leakage current in a dynamic logic gate causes if the input is a ramp rather than a step function? the capacitor CL to discharge during the evaluation phase.69 CRTG VDD . P15. sketch an ECL logic circuit that realizes the exclusive-OR function. and VOH .37. VOL . calculate an approx- define VIH as the value of vI for which QA conducts 99% of imate value for the power dissipated in the circuit under the IE and QR conducts 1% of IE . I = 1 mA. determine the width of conditions that all inputs are low and that the emitters of the transition region (i. * = difficult problem.34. VIH − VIL ) and the noise margins the output followers are left open.75 V at an emitter current I and have very D *15. (a) (b) Figure P15. Find RC to obtain an output voltage swing (c) Repeat (b) for a current in QR of 0. Y = AB + AB. that the values of VOH and VOL become centered on VR ? What (d) Repeat (c) for a current in QR of 0.56 Using the logic and circuit flexibility of ECL high β. only the input A is shown (the other input B is assumed to be (g) Find the value of IR that makes the noise margins equal left open and thus deactivated).55 For the ECL gate in Fig. give numerical values the parameters of the transfer characteristic: that is.53 = Multisim/PSpice. VIL . (e) Use the results of (c) and (d) to specify VIL and VIH . and VR for this ECL gate.35 and 15.75 V and β2 = 100.01I. let VCC = 0 V. 15. the transistors exhibit VBE of 0. 15. and hence only a quarter transistor VBE = 0.53 In Fig. Give a logic diagram (as opposed to a circuit diagram).. of the power dissipated in the reference circuit should be attributed to a single gate. VIL .6: Bipolar and BiCMOS Logic Circuits (b) For the input at B that is sufficiently negative for QB to be cut off. indicated by Figs. VIH − VIL . Assume that at an emitter current of 1 mA the circuit supplies four identical gates. By how much should the output levels be shifted so of v A as VIL . VIH . for VOH .e.4 V.35. Figure P15. D 15. (f) Find NMH and NML .99I. *** = very challenging. Define VIL as the value of vI for which QR conducts 99% of IE and QA conducts 1% of IE . Define this value of 0. (a) Find VOH and VOL . the ECL gate discussed in the text. Conversely. P15. Determine (h) Using the IR value obtained in (g).53(b) shows that to the width of the transition region.53(a). VIH .54 For the ECL circuit in Fig. in QR ? and VR = −1 V. ** = more difficult. 1234 Chapter 15 Advanced Topics in Digital Integrated-Circuit Design PROBLEMS Section 15. vOR versus vI . D = design problem . Also. Assume that the reference NMH and NML . VOL .54. OR transfer characteristic: that is. Define this value will the shifted values of VOH and VOL be? CHAPTER 15 of v A as VIH . 15.52 For the circuit in Fig. 15. what voltage at A causes a current of I/2 to flow 15. 15. B. β = 100. 15.54 *15. 15. *** = very challenging.58.61 Sketch the circuit of a BiCMOS two-input NOR Figure P15. kn = 2. 15.59 Consider the conceptual BiCMOS circuit of A Q1 B Q2 E Fig. This loss becomes particularly acute when the current through QN C Q3 D Q4 and QP becomes small.57. 2 5 V VBE = 0. For all inputs low at Express E as a logic function of A. 15.5kp = 100 μA/V .57 For the circuit in Fig. Vt = 1 V. 0 V.57 gate based on the R-circuit of Fig.38(e). What is the threshold voltage of the inverter if both QN and Q5 QP have W/L = 2 μm/1 μm? What totem-pole current flows at v I equal to the threshold voltage? 18 k D *15. find (W/L)p so that IEQ1 = IEQ2 .60 Consider the choice of values for R1 and R2 in the circuit of Fig.38(a).38(a) for the conditions stated in Problem 15. = Multisim/PSpice. ** = more difficult. This in turn happens near the end of the output signal swing when the associated MOS device is Q6 deeply in triode operation (say at v DS = Vt /3). inputs A.7 V and β = 50. Determine values for R1 and R2 so that the loss in base current is limited 18 k to 50%.38(c). What is this totem-pole transient current? 2. and (W/L)n = 2 μm/1μm. Problems 1235 CHAPTER 15 R R Q3 Q2 D R C 2 PROBLEMS Q1 A QA B QB QR I I I I I Figure P15. * = difficult problem. What is the ratio R1 /R2 ? Repeat for a 20% loss in base drive. For v I = v O = VDD /2.5(W/L)n . let the levels of the what is the voltage at E? Assume VBE = 0.58 Consider the conceptual BiCMOS circuit of Fig. B. what is the voltage at E? If A and C are raised to +5 V. An important consideration in making this choice is that the loss of base drive current will be limited.7 V. P15.5 k 15. D 15. for the conditions that VDD = 5 V. C.58 with the MOSFETs matched and (W/L)P = 2. Let the inverter be specified as in Problem 15. and D. and D be 0 and +5 V. D = design problem . C. 15. 3 Sketch the logic-gate implementation of an SR flip-flop utilizing two cross-coupled NAND gates. B. In a dynamic RAM (DRAM). Read-only memory (ROM) contains fixed data patterns umn.1: Latches and Flip-Flops D 16. 16.2 Sketch the standard CMOS circuit implementation of assume that each of the inverters uses (W/L)p = (W/L)n = the SR flip-flop shown in Fig.) D 16. DRAM the selected gate) a high voltage.1 Consider the latch of Fig. data is stored on a storage cells. Let the transfer characteristic of of all eight transistors if the flip-flop is fabricated in a 0.27 μm/0. infrequently. Then determine the value required for the W/L of each of Q5 to Q8 so that the flip-flop switches.3) on the design of the SR flip-flop Provide the truth table and describe the operation. changed by the user. The sense amplifier that are stored at the time of fabrication and cannot be detects the content of the selected cell and provides a changed by the user.1(b)]. VOH = 5 V. *** = very challenging. Each pixel circuit measures the up operation. then the minimum W/L that each of Q5 −Q8 identical and each characterized by VOL = 0 V. 16. Fig. Rather.2. 16. they are essential in DRAMs. On the other hand. which is converted positive feedback to obtain an output signal that grows into a digital signal by means of an analog-to-digital exponentially toward either VDD or 0. 0. and VIH = 3 V.1. which in effect changes chips provide the highest possible storage capacity for a the threshold voltage of the MOSFET. the contents full-swing version of it to the data-output terminal of the of an erasable programmable ROM (EPROM) can be chip. converter (ADC). A particular light intensity at its pixel and provides this information type of sense amplifier is a differential circuit that employs on its column line in analog form. D 16. These are called flash memories and are in implementing the storage cell: the six-transistor SRAM currently in widespread use.1 for the case of inverters that do not use matched QN and QP . in Example 16. by illuminating the chip by ultraviolet light.6 In this problem we investigate the effect of velocity label the output terminals and the input trigger terminals. Specifically. 16. (W/L)p = 16.1. Find the threshold voltage of each inverter. saturation (Section 15. (Hint: Refer to Table 14. answer part (a) of the question = Multisim/PSpice. via the row-address decoder. process for which μn = 4 μp . Clearly D 16.18 μm.5 Repeat part (a) of the problem in Example 16.4 For the SR flip-flop of Fig.1 with the two inverters μn /μp (W/L)n . PROBLEMS Section 16. that is. EEPROMs can be erased and reprogrammed Two circuits have emerged as the near-universal choice electrically. The cell is programmed by applying (to capacitor and thus must be periodically refreshed. and C [refer to and Q3 .13-μm each inverter be approximated by three straight-line segments. What is the gain at C? What is the width of the transition region? D 16. cell and the one-transistor DRAM cell. CMOS image sensors are organized in arrays very similar Although sense amplifiers are utilized in SRAMs to speed to those used in memories.4. via the column-address decoder. and its col. show that if each of the two inverters utilizes matched transistors. The erasure and reprogramming is a time-consuming process and is performed only There are two kinds of MOS RAM: static and dynamic. Static RAMs (SRAMs) employ flip-flops as the storage Some EPROMS utilize floating-gate MOSFETs as the cells. Use the minimum channel length Sketch the transfer characteristic of the feedback loop of the for all transistors and the minimum size (W/L = 1) for Q1 latch and give the coordinates of points A. Erasure is achieved given chip area. Give the sizes VIL = 2 V. must have so that switching occurs is 2(W/L)n . Even more versatile.3. Problems 1283 activating its row. D = design problem . ** = more difficult. * = difficult problem. 10 ensure that the flip-flop will switch.2: Semiconductor Memories: Types to ensure switching. bit line itself.9 Consider another possibility for the circuit in how many word lines must be supplied by the row decoder? Fig. and (d) Does the operation of this circuit rely on charge storage? interconnect? = Multisim/PSpice. The four NMOS transistors in the set–reset circuit have equal W/L ratios. taking into account the fact that for this technology. what are the values of Q and Q in terms of about the same power level? D? Which transistors are conducting? (b) If D is high and φ goes low.6 V and VDSsat for p-channel devices is 1 V. 16. and all the power loss is dynamic. What is the minimum required W/L for Q5 in terms access.1 V . determine the minimum required width of the set and reset pulses Section 16.5-V.1. (Recall from Problem 16. Q7 . Sketch the fully comple. is occupied by the I/O connections. (b) If a ratio twice the minimum is selected.16-μm process with a cell size of 0. (a) Determine the minimum value required for this ratio to Figure P16.8 The clocked SR flip-flop in Fig.76 μm in a 19 × 38 mm chip.38 × 2 2 operation. Let How many sense amplifiers/drivers would a straightforward S and R normally rest at VDD . 16. 1-Gbit dynamic RAM (called DRAM) by what signals appear at Q and at Q? Describe the circuit Hitachi uses a 0.12 A 4-Gbit memory chip is organized as 256M words × mentary version by augmenting the circuit with the PUN 16 bits. 15.) If closer manufacturing control clock φ. ** = more difficult. 0. 16. How many address bits will the new design need? faster.7 The CMOS SR flip-flop in Fig.2 V. calculate the capacitance per bit line and per bit *16.11.4 is fabricated in 2 process for which μn Cox = 4μp Cox = 500 μA/V . which transistors conduct and 16. The inverters have (W/L)n = 0. Assume λn = λp = 0. how much larger a memory array can be designed in the same technology at (a) For φ high.1.10 Figure P16. the total capacitance of all logic activated in any one cycle. 16.13 A particular 1-M-bit-square memory array has its Q8 . * = difficult problem. the S 500 mW with a 5-V supply for continuous operation with a terminal is lowered to 0 V and the clock φ is raised to VDD .15 A 1. VDSsat for n-channel devices is 0. Let the flip-flop be storing a implementation require? If the chip power dissipation is 0.8 μm/0. Assume that the total capacitance and Architectures between each of the Q and Q nodes and ground is 15 fF. 20-ns cycle time. D = design problem .13-μm Vtn = Vtp = 0. estimate The relevant part of the circuit is then transistors Q5 and Q2 . For the flip-flop to switch. the voltage at Q must be lowered If we assume that 90% of this power loss occurs in array to VDD /2. Note that the fully complementary circuit utilizes 12 peripheral circuits reorganized to allow for the readout of a transistors. 16.4 is not a fully complementary CMOS circuit. To set the flip-flop.4 V. −1 What is the minimum required value for (W/L)5 and for (W/L)6 ? Comment on this value relative to that found in Example 16.13 that 16 bit lines D flip-flop that is triggered by the negative-going edge of the are selected simultaneously. 16. allows the memory array to operate at 3 V. it switches 16-bit word. a 0. How many bits does the word address need? corresponding to the PDN comprising Q5 . (Hint: Refer to Eq. What fraction of the chip (c) Repeat (b) for D low with the clock φ going low.13 μm. *** = very challenging.2 μm/0.13 μm and (W/L)p = 0. thus VQ = 0 V and VQ = VDD .7: Relabel the R input as S and the S input as R. and VDD = 1. D 16. 1284 Chapter 16 Memory Circuits PROBLEMS in Example 16. Q6 . and 16.13.14 For the memory chip described in Problem 16. and that the major capacitance contributor will be the of (W/L)2 and μn /μp ? Assume Vtn = |Vtp |. Although the circuit is more complex. peripheral circuits.10 shows a commonly used circuit of a for this design.11 How many cells does a 4-Gbit RAM have? D 16.) CHAPTER 16 D 16. Assume that the minimum operation.4 for an SRAM fabricated in a *16.4 V (W/L)5 /(W/L)1 for which VQ ≤ Vt0 during a read-1 operation (Fig. Find VQ and I5 that result in each of the operation.2 V .22 Refer to the circuit in Fig.88 V. Show process.17 Repeat Exercise 16.5 V. Sketch the relevant VQ not exceed 0.1. (iii) (W/L)a = the maximum allowed (b) Find the delay time t encountered in the read operation 2 if the cell design utilizes minimum-size access transistors.3: Random-Access Memory CHAPTER 16 that the analysis parallels that presented in the text for the (RAM) Cells read-1 operation. and a of the access transistors.8 V. D 16. of (W/L) Vtn = Vtp = 0. * = difficult problem. Vt = 0.2 V and Vtn = |Vtp | = 0. Assume VDD = 1. Problems 1285 Section 16. 16. Then. B. 16. D 16.4 V.4 for an SRAM fabricated in process for which VDD = 1. obtained without accounting for velocity saturation. Sketch the D 16.11).18-μm CMOS 16. Which one of the three designs (c) Find the delay time t if the design utilizes the maximum results in the shortest read delay? allowable size for the access transistors.13-μm CMOS process for which VDD = 1.13).21 Consider the read operation of the 6T SRAM cell of Fig. and for the a 0.14 to determine part of the circuit and explain the operation.2-V input for reliable and fast and (W/L)n = 1. 16.18 μm. 16. ** = more difficult. *** = very challenging. find the maximum ratio (c) 0. VQ = 0 V.25 Consider the operation of writing a 1 into a 6T VDD = 1. 16. take into account the body effect in Q5 and In each case.) C that correspond to the following three process technologies: D *16.2 V. find the maximum permitted value of (W/L)p in terms 16.3. 16. If during a read-1 operation it is required that SRAM cell that is originally storing a 0. Assume that the bit lines are precharged to VDD before the word-line voltage is raised to VDD . into account the velocity-saturation effect (Section 15. use the graph in Fig. (Hint: Convince yourself that for this situation only Q5 will be 16.2 V.23 For the 6T SRAM of Fig.2 V and Vt = 0.6 V. The sense amplifier technology for which VDD = 1.25-μm CMOS relevant part of the circuit and describe the operation. 16.24 A 6T SRAM cell is fabricated in a 0. The inverters utilize (W/L)n = 1. select values for W1 and W5 that minimize results identical to those obtained in the text for the write-0 the combined areas of Q1 and Q5 .13-μm lines has a 2-pF capacitance to ground.12.2 V.5 V 0.13-μm: VDD = 1.19 Find the maximum allowable W/L for the access D 16. Each of the bit than |Vt |. D = design problem . The SRAM is fabricated in a 0.5 V.13-μm CMOS process.26 For a 6T SRAM cell fabricated in a 0. for the body effect. width allowed is 0. D 16. Eq. (b) 0. requires a minimum of 0.20 Consider a 6T SRAM cell fabricated in a 0. find the maximum permitted value of (W/L)p in terms = Multisim/PSpice.4 V.27 For a 6T SRAM cell fabricated in a 0.18-μm: VDD = 1.8 V. Compare to the value Vt = 0.12 when it is storing a 0. impose the condition that in a read-1 operation compare this result to the value obtained without accounting VQ = Vt . the voltages at Q and Q do not change by more 500 μA/V . Vt = 0.16 Repeat Exercise 16. show that the analysis would lead to L1 = L5 = 0. 16. VQ = VDD .4 V.13-μm CMOS transistors of the SRAM cell in Fig.18 μm.25-μm: VDD = 2.12 so that in the read process for which VDD = 1. and operating in velocity saturation. and γ = 0. following cases: (a) Find the upper bound on W/L for each of the access (i) (W/L)a = 13 the maximum allowed transistors so that VQ and VQ do not change by more than (ii) (W/L)a = 23 the maximum allowed Vt volts during the read operation.5 V and 16. that is. Assume μn Cox = 500 μA/V .5 V and Vt = 0.18 Locate on the graph of Fig. 15.13-μm CMOS process for which VDD = 1. For detailed analysis.4 V. Assume that the SRAM is fabricated in a 0.5 V and Vt = maximum ratio (W/L)5 /(W/L)1 for VQ ≤ Vt . and μn = 4μp .18-μm CMOS process for which Vtn = Vtp = 0.14 the points A.2 V.2 V and PROBLEMS n-channel devices VDSsat = 0.8 V and Vt = 0. this time taking 0.13 and find the 0.5. Without doing the maximum allowable value of the ratio (W/L)5 /(W/L)1 . Vt0 = 0. and μn Cox = 2 operation.4 V.25-μm CMOS process for which VDD = 2. fabricated in a (a) 0.5 V 1/2 2φf = 0. 13 μm. Vt = 0.5VDD − (0. where time. and Gm of each of the inverters in the amplifier is required to C corresponding to the following three CMOS fabrication cause the outputs to reach 0. 10 ns. while keeping bit-line signals result when a stored 1 is read? When a stored td unchanged? 0 is read? Assume that VDD = 1.4 V. * = difficult problem.5 f F. All transistors are to have equal L = 0.5) is reached of 1 ns.34 Consider the operation of the differential sense amplifier of Fig. 0. and μn 4μp . what input signal can be handled? With the increased delay 16.20 following the rise of the sense control VDD = 1. what does it increase to when longer lines are used? the sense-amplifier gain is increased by a factor of 4. type shown in Fig.22. what does the amplifier (c) 0. = Multisim/PSpice. a cycle time of V is the initial difference voltage between the two bit lines.13 μm. For VDD = 1. be increased? If the delay time required for the sense amplifier and other circuitry attached to the for the bit-line capacitances to charge by the constant bit line. VQ is to be limited to a 16.8 V. and thus develop the attached to a bit line while ensuring a minimum bit-line signal difference-voltage signal needed by the sense amplifier. 16. what is the largest cell provides readout voltages of –100 mV when a 0 is stored acceptable leakage current present at the cell? and +40 mV when a 1 is stored.4 pF.8 fF. and a delay until an output of 0. ** = more difficult.1 V is established between the bit lines. what value of 16. find the initial difference voltage required and (16. For a 1-Mbit-square array. how many word-line address bits can be accommodated? D 16.11). The capacitance of each half-bit line is 0.17 the points A. Vt = 0. 0.5 V. between the two bit lines.2 V and V = 0.31 For a DRAM available for regular use 98% of the and 0. respectively] in 2 ns? If for the matched inverters. the (c) If for a particular design.13-μm: VDD = 1. *** = very challenging.13-μm technology uses transistors for which Vt = 0. Assume VDD = 2.2 V. In each case.37 It is required to design a sense amplifier of the 16. Assume For each inverter. VDD = 1. show that the time required for the bit lines to reach 0.9VDD 16.2 V. B.25-μm: VDD = 2. (16. For a bit-line that the minimum width allowed is 0. 16.5 V. What is the maximum number of cells that can be current available from the storage cell.1/2) and 0. Vtn = Vtp = 0. kn = 4kp = 500 μA/V .04 μm/0. Each cell represents a capacitive percentage can the bit-line capacitance. estimate the total memory (b) If the response time of the sense amplifier is to be reduced capacity.2 V. bit-line capacitance per cell is 0. was of 25 mV? How many bits of row addressing can be used? If 2 ns. Vtn = Vtp = 0.29 Design a minimum-size 6T SRAM cell in a 0.13 μm.4: Sense Amplifiers and Address most 2 ns. D = design problem . Find the W/L ratios of the transistors in the amplifier Decoders matched inverters.1VDD is given by td = CB /Gm ln 0. Assume a 20-fF capacitance the bit-line length.13-μm process for which VDD = 1.8VDD /V . 16.5VDD + (0.32 In a particular dynamic memory chip.18-μm: VDD = 1.1/2) volts. If the time can be relaxed by 1 ns.5 V. by what CS = 35 fF and VDD = 1.2 V. and correspondingly load on the bit line of 0. the cell capacitance time and with the input signal at the original level.28 Locate on the graph in Fig. VDD = 1. and 2 D 16.9VDD your minimum-size cell meets the constraints in Eqs.4 V. of (W/L) signal φ s . and bit-line control find the factor by which the widths of all transistors must be circuitry involves 12 fF.20 in a0. Verify that capacitance of 0. 1286 Chapter 16 Memory Circuits PROBLEMS a of the access transistors. 16.9VDD [from initial processes: values of 0. fier of Fig. 16.5 V. to one-half the value of an original design. D 16. with 2 D 16. Vtn = Vtp = 0.36 (a) For the sense amplifier of Fig.30 For a particular DRAM design. having a row-to-column ratio of 2 to 1. μn 4μp .4 V CHAPTER 16 (a) 0. Assume that a balanced differential signal of Vtn = Vtp = 0.5 pF.2 V. by what factor must the width of all transistors be increased? 16. each of which has a 1 pF capacitance. 16.20.13 μm and (W/L)p = 1.20 to operate with a DRAM using the refresh is required within 12 ms. and a refresh cycle of 10 ms.8 V.5 V required? If the input signal is 0. what are the device widths (b) 0.2 V can be tolerated.2 V and Vtn = Vtp = (W/L)n = 0. If a signal loss on the dummy-cell technique illustrated in Fig.2 V.1VDD and 0.26 μm/0. CS = 30 fF. assuming that the processing technology is characterized by kn = 4kp = 300 μA/V . The DRAM capacitor of 0.4 V response time become? For all three. what increased so that V is reduced by a factor of 2.35 A particular version of the regenerative sense ampli- maximum value of Vtn .2 V.5 V 2 and kn = 4kp = 500 μA/V . find the value of Gm .33 For a DRAM cell utilizing a capacitance of 30 fF. The sense amplifier is required to provide a differential output voltage of 1 V in at Section 16. and specify its frequency and the tance C at the storage node X is 25 fF and if QP resets the node percentage of the cycle during which the output is high. If the inverters available have tP = 2. Assume kn = 3kp = 90 μA/V . find its required W/L and the value of the reference halfway through the excursion of 0 to 5 V (i. (c) If the delay component t given by Eq.47 Design the bit pattern to be stored in a (16 × 4) equilibrium condition shown in part (b) of the figure. φ is lowered to 0 V.30. Vtn = − Vtp = 1 V. at in which the gates of the PMOS devices are connected to a what overdrive voltage VOV should Q1 and Q2 be operated precharge control signal φ.40 Consider a 1024-row NOR decoder. 16. (16. 16. (Recall that the magnitude −19 20 MHz. what similar to that of Fig.30 (b) If the switching voltage V is to be about 140 mV. 16. D = design problem .5 ns delay. Let ROM that provides the 4-bit product of two 2-bit variables.6: CMOS Image Sensors 16. find the interval t required for an Fig. 0. Because of the finite resistance and capacitance such a design need? of the word line. Sketch one of 16. = Multisim/PSpice. 16. is the dc voltage at the drain of Q1 ? 16.5 ns.43 Consider a ring oscillator consisting of five inverters. To how many transistors are cut off at this time.24 to detect an input signal of 140 mV and provide a full output in 0. *** = very challenging. what current I is needed if C = 55 fF? (a) During the precharge interval.5 V).41 For the column decoder shown in Fig. address bits does this correspond? How many output lines (b) After the precharge interval is completed and φ returns does the decoder have? How many input lines does the NOR to VDD .27 for application with a square 1-Mbit array. voltage to VDD . (d) Find the W/L required for each of Q1 to Q4 for μn Cox = 2 Estimate the time required to charge a bit line from 0 4μp Cox = 500 μA/V . find the Section 16. gates are used? How many pass transistors are there in total? Section 16.26.49 Consider the pixel circuit in Fig.2 V and Vt = 0. 2. how many inverters do you need for the D 16. Give a circuit implementation of the ROM array using a form (a) If Q1 and Q2 are to operate at the edge of saturation. how much electron charge is accumulated onto the capacitance when the voltage drops by 1 V? Also give the 16.39 Consider the sense amplifier in Fig.38 It is required to design the sense amplifier of delay circuit? Fig. 16.18) is to be and VDD = 5 V.24 in the PROBLEMS D 16.30.2 V. If the resistance of each of the polysilicon word lines 16. how is 5 k and the capacitance between the word line and many column-address bits are needed in a 1-Mbit-square ground is 2 pF.2 μm. How NMOS transistor to discharge the bit line and lower its many address bits are involved? How many levels of pass voltage by 1 V.29 to provide When a 1 is read? an output pulse of 10-ns width. 16.48 Consider a dynamic version of the ROM in Fig. what is the (10% to 90%) rise time of the array? How many NMOS pass transistors are needed in the word-line voltage? What is the voltage reached at the end multiplexer? How many NMOS transistors are needed in the of one time constant? NOR decoder? How many PMOS transistors? What is the (c) If we approximate the exponential rise of the word-line total number of NMOS and PMOS transistors needed? voltage by a step equal to the voltage reached in one 16.2 μm and all the PMOS devices have W/L = 12 2 common-source terminals of Q1 and Q2 ? μm/1. 16. Note that all NMOS 16. to 5 V. * = difficult problem. The bit-line capacitance is 1 pF.44 A ring-of-nine oscillator is found to operate at number of electrons this represents. voltage VR ..4 V. ** = more difficult. 16. Use as an average charging current the current (e) If Q5 is to operate at the same overdrive voltage as Q1 and supplied by a PMOS transistor at a bit-line voltage Q2 . the row decoder raises the voltage of the selected array require? How many NMOS and PMOS transistors does word line.6 × 10 C). If C = 50 fF and VDD = 1. the voltage rises exponentially toward VDD . Let all the NMOS devices have in equilibrium? What dc voltage should appear at the W/L = 3 μm/1. of the electron charge is 1. Problems 1287 CHAPTER 16 What will be the amplifier response time when a 0 is read? D 16.45 Design the one-shot circuit of Fig.5 ns.34.e.46 Give the eight words stored in the ROM of Fig. each having tPLH = 3 ns and tPHL = 2 ns.5: Read-Only Memory (ROM) required current I and the power dissipation. VDD = 1. If the capaci- the output waveforms. 16. D 16. Find the propagation delay of the inverter.42 Consider the use of the tree column decoder shown in time constant. 16. which can be R = 1/Cf c connecting the two circuit nodes. and 17.24(a). 17. 17. 17. (b) 10 kHz. Types. values and to the nonidealities of the op amps. the poles realized are design of the RF tuner and the IF amplifier of commu- at the same locations as the zeros of the RC network. Different transmission zeros are realized results in a flatter passband response (in comparison to by feeding the input signal to circuit nodes that are that obtained with all the resonant circuits synchronously connected to ground. Stagger-tuning the individual tuned circuits identical poles. 0. circuit nodes at a high rate. functions. Biquads based on the two-integrator-loop topology are the Transconductance-C circuits utilize transconductors and most versatile and popular second-order filter realizations. where ω0 is the 3-dB Find the peak amplitude and the phase (relative to that of the frequency of the filter. 2π × 10 T (s) = ter (such as that realized by an RC circuit) can be s + 2π × 104 expressed as T (s) = ω0 / s + ω0 . D = design problem . BP. fc . G.1 The transfer function of a first-order low-pass fil. Single-amplifier biquads (SABs) are obtained by placing Tuned amplifiers utilize LC-tuned circuits as loads. and (d) 100ω0 . 17.1. as shown op amps but are sensitive to the op-amp nonidealities and in Fig. (c) 100 kHz. Give in table form the values of input sinusoid) of the output sinusoid if the frequency of the |T |. Problems 1369 various special second-order filtering functions.5ω0 .and high-frequency fil- There are two varieties: the KHN circuit of Fig. They are used in the op amp. implemented in CMOS. the op amp–RC resonator of Sx = ∂x/x Fig.22. *** = very challenging. 1 MHz. The design equations for these circuits are circuit is to the unavoidable inaccuracies in component given in Table 17.18. 2ω0 . ω0 .2).25(b). is equivalent to a resistance cuit to obtain the circuit of Fig. The cascode and the CC–CB cascade The complementary transformation can be applied to the configurations are frequently used in the design of tuned feedback loop to obtain another feedback loop having amplifiers. periodically switched between two Feedforward can be applied to the Tow–Thomas cir. PROBLEMS Section 17. and the Tow–Thomas circuit of Fig. and HP functions simulta. The basic building block is the neously and can be combined with the output summing integrator. If the op amp is ideal. and A at ω = 0. that a capacitor C. 17. By replacing the inductor of an LCR resonator with The classical sensitivity function a simulated inductance obtained using the Antoniou y ∂y/y circuit of Fig.2 A sinusoid with 1-V peak amplitude is applied at the Specification input of a filter having the transfer function 4 17. * = difficult problem. or at a bridged-T network in the negative-feedback path of an the input. and the basic filter building block is based on amplifier of Fig. 17.21(b) is obtained. capacitors to realize medium. 17. are thus limited to low-Q applications (Q ≤ 10). technology. = Multisim/PSpice. nication receivers. 5ω0 .20(a). ** = more difficult. of transistor amplifiers. φ. 10ω0 . and input sinusoid is (a) 1 kHz. SC filters designed to realize any of the second-order functions can be fabricated in monolithic form using CMOS IC (see Table 17. ters (as high as hundreds of megahertz) that can be which realizes the LP.26.24(b) to realize the notch and all-pass the two-integrator-loop topology.1: Filter Transmission. Switched-capacitor (SC) filters are based on the principle which realizes the BP and LP functions simultaneously. 17. SABs are economic in their use of tuned). This resonator can be used to realize the various second-order filter functions as shown is a very useful tool in investigating how tolerant a filter in Fig. 14 that is required to pass signals over the bands 0 ≤ f ≤ 10 kHz and 20 kHz ≤ f ≤ ∞ with Amax of 0.11 A third-order low-pass filter has transmission zeros at the blue curve) in Fig. Amax = 0.10 Consider a fifth-order filter whose poles are all at attenuation realized? If Amin is to be exactly 20 dB.8 Sketch transmission specifications for a high-pass filter having a passband defined by f ≥ 3 kHz and a stopband defined by f ≤ 2 kHz. One pair of value can Amax be reduced? = Multisim/PSpice.14 Analyze the RLC network of Fig. s = −0. Calculate the values of |T | and φ for in each of the following cases. D 17. (c) 10 sin 10t (volts) What type of filter results in each case? 17.5 dB.3: Butterworth and from f = 12 kHz to f = 18 kHz.7 A low-pass filter is specified to have Amax = 2 dB and Amin = 12 dB. one at 3 × 10 rad/s. Amin . sketch first-order transfer function the shape of its |T |. D 17. Amin ≥ 20 dB. to what 4 a radial distance from the origin of 10 rad/s.05). and the selectivity ratio Section 17.7.05% of the maximum 17. ω = 0.5 ± j0.1t (volts) (b) The transmission zeros are all at s = 0 and the CHAPTER 17 (b) 10 sin t (volts) high-frequency gain is unity. 17. 2 *17. with a minimum required Chebyshev Filters attenuation of 50 dB. What must ωp and ωs of this filter be? What is the selectivity factor? Vi(s) 1F 1F 1 Vo (s) 17.. If the dc gain is variation of at most 5% (i.) 17. find |T | at ω = 0.9 Sketch transmission specifications for a bandstop filter Figure P17. The transmission in the stopband. 1370 Chapter 17 Filters and Tuned Amplifiers PROBLEMS complex-conjugate poles is at 18° angles from the jω axis. one at 6 × 10 rad/s. Give the transfer function its phase response φ(ω). and Amin = 60 dB. ω = ωp . What is the gain at minimum transmission in the passband should not exceed ω approaching infinity? 1.15 Determine the order N of the Butterworth filter for which Amax = 0.4 dB. which extends from 5 kHz to ∞. 4 2π × 10 T (s) = *17.e. What is the actual value of minimum stopband 17.2: The Filter Transfer Function ωs /ωp = 1.6 A low-pass filter is specified to have fp = 5 kHz and a passband transmission with a peak at the center frequency of selectivity factor of 10.12 A second-order low-pass filter has poles at −0.5 dB. (a) 10 sin 0. What are the values of Amax . 1. extending from 0 to 4 kHz. and filter having transmission zeros as follows: one at ω = 0. P17.4 For the filter whose magnitude response is sketched (as 17. and 10 rad/s and then find the output corresponding (a) The transmission zeros are all at s = ∞ and the dc gain to each of the following input signals: is unity. give the transfer function T (s). and equiripple response in the stopbands.2 dB.14 to deter- s + 2π × 104 mine its transfer function Vo (s)/Vi (s) and hence its poles and What must Amax and Amin be? zeros. Find T(s). It is found that these specifications can be just met with a single-time-constant RC circuit having a time 1 2H constant of 1 s and a dc transmission of unity. the ratio of the maximum to unity. and Amin = 60 dB. with a transmission and a transmission zero at ω = 2 rad/s. and one at ω = ∞. ** = more difficult. The dc gain is unity.13 Find the order N and the form of T(s) of a bandpass passband transmission.8. If this filter has a monotonically decreasing 17. one 3 3 3 the selectivity factor for this filter? at ω = 10 rad/s. The specifications are just met by a 3 2 ×10 rad/s. The stopband extends Section 17. * = difficult problem. should not exceed 0. Its natural modes are at s = −1 and ω = ωs .3 A filter has the transfer function T (s) = 1/[(s + 1)(s + √ s + 1)].1. *** = very challenging. Amax = 0. and ω = 2 rad/s and ω = ∞. Show that |T | = 1 + ω6 and find an expression for and the other pair is at 54° angles.3. (Hint: Begin the analysis at the output and work your way back to the input.25 ± j its passband.5 A low-pass filter is required to pass all signals within 17. D = design problem . 17. fs = 20 kHz. and higher than 100 k are to be used and that the input resistance indicate this point on your sketch. Amax = 1 dB.19) to determine |T | at ω = 2 rad/s. which filter gives greater attenuation? circuit with a first-order op amp–RC high-pass circuit. For both. P17.20 Sketch the transfer function magnitude for a low-pass 10 kHz.18 Find the natural modes of a Butterworth filter having 3 expressions for the frequency of the transmission zero ωZ .23 Contrast the attenuation provided by a sixth-order Find |T (jω)| and φ(ω) We wish to use this circuit as a variable Chebyshev filter at ωs = 2ωp to that provided by a Butterworth phase shifter by adjusting R. 17.25 Use the information displayed in Fig. For large values of ω. frequency of the pole ωP .4: First-Order and 60-Hz voltages.19 Design a Butterworth filter that meets the following gain. What D *17. –60°. the natural modes. sketch the magnitude of the gain that results? Sketch the magnitude of the transfer function transfer function of a Butterworth and a Chebyshev low-pass versus frequency. –90°.22 Sketch |T | for a seventh-order low-pass Chebyshev can design a wideband bandpass filter. 17. Give 17. ** = more difficult. What is the 0 to 180° (with 0° at high frequencies and 180° at low excess (above 35 dB) stopband attenuation obtained? frequencies). (b) Find the poles and the transfer function.32 Use two first-order op amp–RC all-pass circuits in cascade to design a circuit that provides a set of three-phase Section 17. ωs . the resulting phase shift covers the range (a) Find the required order of Chebyshev filter.29 By cascading a first-order op amp–RC low-pass stopband edge. input resistance is to be 10 k. If the input signal frequency filter of equal order. At the D *17. 17.13 to design a 20 log(ωs /ωp ) Hint: Use Eq. Use Eq. the a 0. Use 1-μF capacitors.26 Use the information given in Fig.32. Amax = 3 dB. 17. –120°. Amin = 35 dB. filter of fifth order and having the same ωp and Amax .13 to These voltages simulate those used in three-phase power design a first-order op amp–RC low-pass filter having a 3-dB transmission systems.24 It is required to design a low-pass filter to meet the following specifications: fp = 3. Use Eq. and –150°. The low-frequency Chebyshev filter of (a) sixth order and (b) seventh order. low-pass specifications: fp = 10 kHz. a dc gain magnitude of 10.13(c). as shown in the phasor diagram of Fig. and 17. and T(s).27 Derive an expression for the transfer function of the op amp–RC circuit that is shown in Fig.5 dB.30 Derive T(s) for the op amp–RC circuit in Fig.17 Calculate the value of attenuation obtained at a a high-frequency gain magnitude of unity. Select appropriate √ of ω at which |T | = 1/ 1 + 2 . and Amin = 20 dB.31 Show that by interchanging R and C in the op amp–RC fs = 4 kHz. frequency 1. Provide such a design filter with ωp = 1 rad/s and Amax = 0. Indicate these values on your component values under the constraints that no resistors sketch. a pole frequency of 17.4 kHz.15) and neglect the unity term.13 to design is the attenuation provided at 30 kHz? a first-order op amp–RC spectrum-shaping network with a transmission zero frequency of 100 Hz. and an input obtained from the approximate expression resistance of 12 k. 17.21 On the same diagram. required to obtain phase shifts of –30°.5-dB bandwidth of 10 rad/s and N = 5. A − 20 log N ≥ min D 17. each separated by 120° and equal in Second-Order Filter Functions magnitude.16 Show that the order N of a Butterworth filter can be frequency of 5 kHz. D *17. D *17. (17. (17. first-order op amp–RC high-pass filter with a 3-dB frequency of 200 Hz. find the values of R filters on the same axes. = Multisim/PSpice.28 Use the information given in Fig. 17. D = design problem . Amax = 1 dB. what rate (in dB/octave) does the transmission decrease? D 17.8 times the 3-dB frequency of a seventh-order PROBLEMS Butterworth filter. and a dc gain magnitude of unity.14. 17. D 17. 17. 17. (17. Sketch |T | for both 3 is 5 × 10 rad/s and if C = 10 nF. *** = very challenging. Find N. one *17. a high-frequency input resistance of 120 k. Problems 1371 CHAPTER 17 17. and the high-frequency D 17. the dc gain.14. circuit of Fig.18) for the case in which the midband gain is 12 dB and the 3-dB to determine the values of ω at which |T | = 1 and the values bandwidth extends from 50 Hz to 50 kHz. What is the high-frequency 17. * = difficult problem. at is to be as high as possible. 48 Modify the bandpass circuit of Fig. find the bandwidth is 500 Hz. ** = more difficult.5: The Second-Order transfer function of a second-order low-pass filter that just LCR Resonator meets the specifications defined in Fig. Repeat for the case of the Q factor of the |T | peak? What is the peak transmission? zeros lower than the Q factor of the poles.34) 17. and dc gain = 1. D = design problem . At what frequency does the expected |T |.44 For the LCR resonator of Fig. 17. 17. give the locations of the poles and zeros.32 of the zeros slightly higher than the frequency of the poles. transmission as ω approaches zero and as ω approaches ∞. 17. 17. 17. and hence show that of Amin obtained in each case.17(a) to obtain frequency at ω = 1 rad/s. Also. find the value transfer function T (s) ≡ Vo (s)/Vi (s).16(b) to find change in ω0 that results from the transfer function of a second-order √ high-pass filter with natural modes at −0. Roughly sketch 4 10 rad/s.42 Analyze the circuit in Fig. Repeat for the case of the frequency Figure P17. D *17.5 without ωs1 = 3000 rad/s find Amin and ωs2 . 1372 Chapter 17 Filters and Tuned Amplifiers PROBLEMS a bothersome interference of 60-Hz frequency.45. the members of each pair of frequencies ω1 and ω2 for which T ( jω1 ) = T ( jω2 ) are related by D 17.16(a) to obtain the Section 17.17(a) with node function of a notch filter that is required to eliminate x disconnected from ground and connected to an input signal = Multisim/PSpice.17(c) to determine its For each.18(c). *** = very challenging. D *17. D **17.18(d) to ωp1 = 8100 rad/s.33 Use the information in Fig.49 Consider the LCR resonator of Fig.40 Consider a second-order all-pass circuit in which CHAPTER 17 errors in the component values result in the frequency of the zeros being slightly lower than that of the poles. The dc transmission of the filter is to be unity. Since the frequency of the interference is not stable. Note that there are two possible solutions. If change its center-frequency gain from 1 to 0.34 Use the information in Fig. and a high-frequency gain of unity.3 with ωp = 1 rad/s and Amax = 3 dB. filter with ω0 = 10 rad/s and Q = 1/ 2. P17. * = difficult problem. if ωs = 2 rad/s.18(b) √ 6 to design a low-pass 2 ω1 ω2 = ω0 . (17.46 Derive an expression for Vo (s)/Vi (s) of the high-pass function is geometrically symmetrical around the center circuit in Fig.4 where D 17. and the center-frequency gain is 10. the 3-dB 17. 17. 17.15 to find the transfer 17. changing ω0 or Q. 17. find ω0 and Q. Give the location of the poles and zeros. 17.37 Find the transfer function of a second-order bandpass filter for which the center frequency f0 = 10 kHz. respectively.39 Use the result of Exercise 17. Also.45 For each of the circuits in Fig. and hence find the transmission zeros. Q = 2. 5 natural modes with ω0 = 10 rad/s and Q = 5. Utilize a 1-nF capacitor. and Amax = 3 dB. 17. 17. 17. (b) Find the transfer function of the second-order bandpass filter that meets specifications of the form in Fig. That is. its poles are characterized by ω0 and Q of Eqs.17(a). frequency ω0 . What are ω0 and Q of the poles? (b) increasing C by 1% (c) decreasing R by 1% 17. 17.35 Find the transfer function of a second-order high-pass and (17.43 Design the LCR resonator of Fig. a 3-dB D 17. ωp2 = 10. 17. the filter should be designed to provide attenuation ≥20 dB over a 6-Hz band centered around 60 Hz. 17.41 Consider a second-order all-pass filter in which errors 17.38 (a) Show that |T | of a second-order bandpass 17. Use R = 10 k.35). 000 rad/s. find the 17. 17.47 Use the circuit of Fig. Roughly sketch the expected |T |. filter with a maximally flat passband response.16(a) to obtain the in the component values result in the Q factor of the zeros transfer function of a second-order low-pass filter with ω0 = being greater than the Q factor of the poles.5 ± j 3/2 and a high-frequency gain (a) increasing L by 1% of unity.36 Use the information given in Fig. Z1 Z2 Z3 Z4 1 2 17. what is the magnitude of the transmission at frequencies .1 ω0 ? For this case.50 Consider the notch circuit shown in Fig.45 source Vx . Problems 1373 C1 C1 CHAPTER 17 Vi C2 Vo Vi C2 Vo R – – – – PROBLEMS (a) (b) L1 L1 R Vi L2 Vo Vi L2 Vo – – – – (c) (d) Figure P17. Vo . node y disconnected from ground and connected to another input signal source Vy . Use superposition to find the voltage that develops across the resonator. 17. Vy . and node z disconnected A1 from ground and connected to a third input signal source Vz . in terms of Vx . For what ratio of C2 to C1 does the notch occur at 1.18(g). and Vz . 52 acts as an “impedance trans- former. which Antoniou circuit of Fig. * = difficult problem. *** = very challenging. and Z4 . Z2 . Here. show that the input impedance looking into port (c) From the expressions above. P17. Z1 Z3 Z11 = Z and Z4 . ω0 ? At frequencies ω0 ? A2 Section 17. and (c) 0. Z3 .” Since by the appropriate choice of Z1 .20(a). the transformation ratio can be a general function Z2 Z4 5 = Multisim/PSpice.e. show that if an 1. Z3 . is given by the other four components are replaced by general impedances Z1 .52 D 17. between node 1 and ground) is network in Fig. Z2 Z4 Z22 = Z Z1 Z3 6 (a) With an impedance Z5 connected between node 2 and ground.6: Second-Order Active Filters Based on Inductor Replacement Figure P17. ** = more difficult. 17.52 Figure P17. Z2 .20 (utilizing suitable component values) to realize an inductance of (a) 15 H. R5 is eliminated and is between terminal 2 and ground. the input impedance looking into port 2. observe that the two-port 1 (i.51 Design the circuit of Fig.15 H.5 H. 17. impedance Z6 is connected between terminal 1 and 17. (b) (b) From the symmetry of the circuit.52 shows a generalized form of the ground. D = design problem .. 57 Design the all-pass circuit of Fig.62 (a) Using the KHN biquad with the output summing Fig. Give the complete circuit and specify all component values.3. 17. 17. dc gain. show that an all-pass function is shown in Fig. which component(s) does one need to trim to transfer function was obtained using filter-design tables: adjust (a) only ωz and (b) only Qz ? 2 0.) Topology *17.22(a) and a first-order op amp–RC circuit of the type amplifier of Fig. fn = 12 kHz. function with f0 = 10 kHz. except that the response notch filter with ω0 = 10 rad/s. (Note: A filter with 17. what is the worst-case percentage deviation between ωn and ω0 ? D **17. Q = 10. derive the design equations also given.22(e).2786 + 1. D 17. or GIC.7: Second-Order Active jω)? (This impedance is known as a frequency-dependent Filters Based on the Two-Integrator-Loop negative resistance. 17. Q = 4. 17. Select appropriate component values. How CHAPTER 17 does this impedance behave for physical frequencies (s = Section 17. a capacitor C6 connected between node 1 and stopband is known as an elliptic filter.7294)(s2 + s0.53 Consider the Antoniou circuit of Fig.4508 s + 1. What D *17.3 × 10 rad/s.24(b) to realize a notch provide a phase shift of 180° at f = 2 kHz and to have Q = 2.67 Repeat Problem 17.63 Consider the case of the KHN circuit used together D 17. 17.13(a). 17.61 Design the KHN circuit of Fig. Q = 10. the summing resistors used have 1% tolerances.65 Design the circuit of Fig.9. 1374 Chapter 17 Filters and Tuned Amplifiers PROBLEMS of the complex frequency variable s.29 √ to realize a pair of 5 LP op amp–RC circuit of the type shown in Fig. G. given using the KHN biquad with an output summing amplifier.6996 D **17. and a voltage source V2 connected to node 2. and 5 shown is for N = 5). 17. in Table 17. realized by selecting RL = RH = RB /Q. Use C = 10 nF and r = 20 k. given associated with the summing amplifier. *** = very challenging. 17. The actual filter realized is to have ωp = 10 rad/s.55 It is required to design a fifth-order Butterworth value of center-frequency gain is obtained? 5 filter having a 3-dB bandwidth of 10 rad/s and a unity dc gain. ** = more difficult. Also show that the flat gain obtained is KRF /RH . If in Table 17. Find expressions for the values required of the resistances D 17.58 Using the transfer function of the LPN filter.54 Starting from first principles and assuming ideal D 17. Select appropriate component values. derive the transfer function of the circuit in a bandpass filter with a center frequency of 2 kHz and a Fig. = Multisim/PSpice. Section 17. Each section is to have a dc gain of unity.0504) biquad of Fig. Select appropriate component values.2 rad/s. The filter passband extends from ω = 0 to ωn = 1.22(a). 17. derive the design equations also given. filter with a notch frequency ωn and a high-frequency gain of Use 1-nF capacitors.66 In the all-pass realization using the circuit of and 0.20(a) with an equiripple response in both the passband and the R5 eliminated.24(b).13(a) poles with ω0 = 10 rad/s and Q = 1/ 2.22(e) to realize an LPN 5 (b) Design the all-pass circuit to obtain ω0 = 10 rad/s. (b) Realize this filter as the cascade connection of a first-order D 17. and a unity and flat gain = 10.1. The stopband edge is at ω = 1.60 It is required to design a third-order low-pass filter whose |T | is equiripple in both the passband and the stopband D 17.1. Select C4 = 10 nF. D = design problem .60 using the Tow–Thomas T (s) = (s + 0. 17.26. 3-dB bandwidth of 50 Hz. D 17.59 Using the transfer function of the HPN filter. Show 2 that the input impedance seen by V2 is R2 /s C4 C6 R1 R3 . 17. or FDNR.26 to realize the second-order section in 5 the cascade.) ground. 17.24(a) to realize op amps. and the passband transmission varies between 1 D 17. Fig.26 to realize a low-pass 5 (in the manner shown in Fig. 17. the circuit is known and a second-order LPN circuit of the type shown in as a generalized impedance converter.64 Consider a notch filter with ωn = ω0 realized by D 17. dc gain = 1. 17. 17. The following Fig.56 Design the circuit of Fig. Use 10-nF capacitors. 17. Use C1 = C2 = 1 nF.68 Design the circuit of Fig.8: Single-Amplifier Biquadratic (a) Obtain the transfer function of the actual filter by 5 Active Filters replacing s by s/10 . 17. ω = 1 rad/s. * = difficult problem.22(g) to with the summing amplifier in Fig. Use a cascade of two circuits of the type shown in D 17. If the network is circuits of Fig. then the R3 = R4 = R and C1 = C2 = C. *17.31. 17. then Sx = Su · Sx . u voltage at the op-amp output.28(a). where Vo (s) is the (c) y If y = ku. as in Fig.73 Consider the bandpass circuit shown in 2 for the design in which R1 = R2 . find the poles of the closed-loop Section 17.28(b) with and C of the low-pass circuit in Fig.28(a) with a bandpass with a center-frequency gain of unity. 17. and C3 = C/36. adjusting I? Q = 1/ 2 and ω3dB = ω0 .72 Use the circuit in Fig. then Sx = Sx + Sx . y u v (a) to the input signal source Vi . If for tuning purposes it is required to 4 maximally flat response with a 3-dB frequency of 10 rad/s. 17. 17.34(a). gain. (Hint: For a maximally flat response.) D 17.30(a).1 voltage divider R1 .77) and (17. Analyze the resulting circuit to If y = u/v .70 Consider the bridged-T network of Fig.77 Evaluate the sensitivities of ω0 and Q relative to R. 17. 17. where k is a constant. and thus verify the expression given transfer function by interchanging input and ground. 17. Thus show and the MOSFET’s transconductance parameter kn . use the terminal of the op amp from ground and apply Vi through a expressions for ω0 and Q given in the top row of Table 17.33(b) assuming the op amp to be ideal.71 Consider the bridged-T network of Fig.5 mA/V. what Gm is needed? If the output resistance of D *17.21(b).9: Sensitivity amplifier. 17. C4 = C.29. 17. find an expression for Gm in terms of I Fig. 17.10: Transconductance-C Filters op amp to be ideal. 17. Analyze the circuit to find its transfer capacitors. u a bandpass filter and find its ω0 . give the circuit for 10-k value for all resistors. 17. Find the complement obtained is a notch. Q. use the specify the center-frequency gain obtained.75 Design a fifth-order Butterworth low-pass filter the transconductor is 100 k. find the bias current I that results in high-frequency gain of the circuit? Design the circuit for a Gm = 0.35(f). 17.25 mA/V. L.80 For the feedback loop of Fig.69 Derive the transfer function t(s) of the bridged-T D 17.79 For the high-pass filter of Fig. placed in the negative-feedback path of an ideal infinite-gain PROBLEMS op amp. Find the ratio R2 /R1 so that the circuit realizes (a) an all-pass function and (b) a notch function. For that the circuit realizes a high-pass function. what are the D 17.83 Using the circuit of Fig. What is the kn = 0. y u v (b) determine its transfer function Vo (s)/Vi (s). R1 = R2 = R.74 Derive the transfer function of the circuit in Fig. Assume the Section 17. Show that if the network n is 17. 17. Fig. and the center-frequency (e) y y u If y = f1 (u) and u = f2 (x).82 For the fully differential transconductor of D *17. R4 = R/4Q . R3 = R.18(d) and (e).78 Verify the following sensitivity identities: placed in the negative-feedback path of an infinite-gain op amp and let C4 be disconnected from ground and connected If y = uv .13(a)]. then Sx = nSx . illustrated in Fig.34(c)] and a first-order section [Fig.84 Using four transconductors. Disconnect the positive input 17.81 For the op amp–RC resonator of Fig. R2 to the positive input terminal as well as to determine the sensitivities of ω0 and Q to all resistors and through R4 /α as before. Problems 1375 CHAPTER 17 *17. Give the values of all components and *17. ** = more difficult.30(b) with α = 1 to realize sensitivities of ω0 and Q to amplifier gain A? a bandpass filter with a center frequency of 10 kHz and a 3-dB bandwidth of 2 kHz. Use a D 17. applies to any general network (not just RC networks as shown). Let the network be *17. then Sx = Sx − Sx . then Sx = Sx . obtaining an output voltage Vo related to three input voltages = Multisim/PSpice. Let C1 = C2 = C. Show that the circuit obtained is (d) n y If y = u . what is the required range for Use C1√= C2 = 10 nF.78) to determine the sensitivities of ω0 and Q relative to all passive components D **17. realized? Use the cascade connection of two Sallen-and-Key circuits [Fig. and denote CR = τ . as in the figure. * = difficult problem.36(a) to realize a 1-k resistance. where n is a constant. function Vo /Vi .76 The process of obtaining the complement of a network in Fig. what is the resistance actually that has a 3-dB bandwidth of 10 kHz and a dc gain of unity. adjust Gm in a ±5% range.18(b). *** = very challenging. CR = 2Q/ω0 . (17. 17. expressions in Eqs. Verify this by using the RLC zeros and poles of the bridged-T network. 17. 17. 17. 17. and α = 1. D = design problem . 17.33(b). what value of Gm (d) What filter function is (i) V1 /Vi .89 For the circuit in Fig.94 For a dc voltage of 1 V applied to the input of the circuit of Fig. Q = 5.96).36(b) has an output resistance Ro and an output Gm1 = Gm2 = Gm3 = Gm and C2 = C.37(b) and its associated expressions in Eqs.93 For the switched-capacitor input circuit of Fig. 17.85 For the integrator in Fig.37(b). Find expressions for C1 capacitance Co . the error in the integrator time constant must be less than 1%. To realize the resistance R.89: D 17.87 Design the first-order low-pass filter in terminal and the output terminal of transconductor Gm4 Fig. = Multisim/PSpice. 17. what change would you expect Figure P17. use a third D 17. *** = very challenging.38(b). D *17.36(c).86 If the transconductor in the integrator of and (17. P17. and a center-frequency gain of 5. 17. Q.11: Switched-Capacitor Filters I1 17. Generate an alternative design based on selecting Fig.90 Consider the Gm –C second-order bandpass filter of CHAPTER 17 Fig. 5 pF. 1376 Chapter 17 Filters and Tuned Amplifiers PROBLEMS V1 . 17. (b) Add a fifth negative transconductor Gm5 with Vi applied to its input.36(c) to have a pole frequency of 20 MHz and a and dc gain of 10. 500 kHz. what input resistances correspond to capacitance C1 Gm2 + 2 values of 1 pF. node and node X in the circuit of Fig.89 in the output for each cycle of the clock? For an amplifier that saturates at ±10 V and the feedback capacitor initially discharged.32 for a clock frequency of transconductor Gm3 . 17. D = design problem .92 Design the circuit of Fig. ** = more difficult. 17. what is the smallest value of C that can be used? If D 17.88 If a capacitor C1 is connected between the input V2 is taken. what is the transfer function realized? If and Gm in terms of ω0 .37(b) to realize filter functions other than bandpass decades lower than the unity-gain frequency of the integrator. V2 . Zin ≡ what is the average current drawn from the input source? For a I1 feedback capacitance of 10 pF. voltage produced? (b) Use the inductance generated at the input to form an LCR resonator. – Gm1 – Section 17. 17. and V3 by Vo = V1 − 2V2 + 3V3 . 17. what charge is transferred V1 for each cycle of the two-phase clock? For a 100-kHz clock. in which C1 is 1 pF.38(b). Compare the circuit thus created to the two-integrator-loop Gm –C filter of Fig. * = difficult problem. (ii) V2 /Vi ? is needed to obtain an integrator with a unity-gain frequency of 10 MHz utilizing a 5-pF capacitor? D 17. and lowpass. how many clock cycles would it take to saturate (a) Show that the input impedance Zin is that of an inductance the amplifier? What is the average slope of the staircase output L and find an expression for L. and its output connected to the node at which D 17. (17.36(b).95 Repeat Exercise 17. 17. and 10 pF? V1 – – C 17. implement the following modifications: what is the smallest Gm that this transconductor must have? (a) Connect a capacitor C3 between the positive input D 17. D 17. Select Gm1 = Gm2 + and C1 = C2 = 5 pF.91 To enable the second-order Gm –C circuit in the low-frequency pole introduced by Ro is to be at least two Fig.95) D 17. what transfer function Vo /Vi is realized? Derive an expression for the transfer function V1 /Vi .37(c) to realize a bandpass function having a center frequency of 25 MHz. Give the values of the (c) Use a fourth inverting transconductor Gm4 with its input four transconductances as ratios of Gm of the transconductor connected to an input voltage Vi and its output connected that delivers the output voltage. and C. in which a clock frequency of 200 kHz is 1 + used. to node 1. Use C = 2 pF. 17. 17.40(b) to realize.97 Design the circuit of Fig.16(c)]. 17.e. *17.. at the find |T ( jω)|. D 17. a maximally 2 δω = ω0 1 + δω/ω0 . Problems 1377 D 17.96 Repeat Exercise 17.102 (a) Substituting s = jω in the transfer function CHAPTER 17 T(s) of a second-order bandpass filter [see Fig. where δω/ω0 . For ω in the vicinity of ω0 [i.32 for Q = 50. ω = ω0 + output of the second (noninverting) integrator. of N synchronously tuned sections connected is connected to the input of a common-emitter BJT amplifier. 2 ω0 1 + 2δω/ω0 ]. the 3-dB bandwidth. and C6 . Use a clock frequency fc = 100 kHz and select C1 = C2 = 5 pF. (Hint: For a maximally T jω0 flat response. C5 . **17. and Cμ = 0. bandpass response in the neighborhood of ω0 is the same as the response of a first-order low-pass with 3-dB frequency of 17. Q = 1/ 2 and ω3dB = ω0 . Find ω0 . is Between base and emitter is connected a tuned circuit with √ L = 0.) |T ( jω)| 2 1 + 4Q2 δω/ω0 PROBLEMS Section 17. 1 so that ω 3 flat low-pass function with ω3dB = 10 rad/s and unity dc gain. Q.5 μH and C = 200 pF. in cascade. show that the bandpass response at ω = ω0 + δω. Its Q is specified δω .103 (a) Using the fact that for Q 1 the second-order and the center-frequency gain of this single-tuned amplifier.12: Tuned Amplifiers (b) Use the result obtained in (a) to show that the 3-dB *17. Give the values of C3√. The transistor load is a resistance of 5 k.5 pF. C4 . for for applications around 1-MHz frequency.99 A coil having an inductance of 10 μH is intended (ω0 /2Q).98 A voltage signal source with a resistance Rs = 10 k bandwidth B. Cπ = 10 pF. for Q 1. show that. The transistor is biased at 1 mA B = ω0 /Q 21/N − 1 and has β = 200. If the inductor is tapped at one-third of its turns and Eq.101 Consider a common-emitter transistor amplifier T jω0 loaded with an inductance L. show that for T ( jω) = overall N/2 overall ωCμ . find f0 bandwidth B.100 An inductance of 36 μH is resonated with a 1000-pF (b) Use the relationship derived in (a) together with capacitor. (17. Ignoring ro . ω0 . has an overall transfer function given by *17.123) to show that a bandpass amplifier with a 3-dB a 1-k resistor is connected across the one-third part. is given by to be 250. Find the equivalent parallel resistance Rp . What is the value of the capacitor required to produce resonance T jω0 at 1 MHz? What additional parallel resistance is required to |T ( jω)| 2 produce a 3-dB bandwidth of 12 kHz? 1 + 4Q2 δω/ω0 17. designed using N synchronously tuned stages. and Q of the resonator. find the ratio of the 30-dB bandwidth to the 3-dB bandwidth This can lead to oscillations. *** = very challenging. = Multisim/PSpice. * = difficult problem. ** = more difficult. the amplifier input admittance is given by 1 + 4(21/N − 1)(δω/B)2 1 2 (c) Use the relationship derived in (b) to find the attenuation Yin − ω Cμ Lgm + jω Cπ + Cμ rπ (in decibels) obtained at a bandwidth 2B for N = 1 to 5.) for N = 1 to 5. 1/ωL. D = design problem . Also (Note: The real part of the input admittance can be negative. The 555 timer. provided the magnitude of loop it remains for a predetermined interval. it goes into a quasi-stable state in which the loop is zero or 360°. PROBLEMS Section 18. the phase-shift oscillator. 18. D = design problem . (a) Derive an expression for dφ/dω. quadrature oscillator. transfer characteristic that approximates the sine monostable. a commercially available IC. amplifier (an op amp or a transistor). a pole Q denoted Q. It oscillates than unity.1 Consider a sinusoidal oscillator consisting of an ampli- function. *** = very challenging. remaining in each for amplitude-control mechanism is activated. It thus generates a periodic The Wien-bridge oscillator. of multivibrators are useful in analog-circuit applications ator: the linear oscillator. A sine waveform can be generated by feeding a triangular waveform to a sine-wave shaper. gain at this frequency is equal to. ** = more difficult. These circuits employ RC networks together waveforms. The circuit will oscil. the waveform at the output. the poles of the circuit = Multisim/PSpice.1: Basic Principles of Sinusoidal (b) Use the result of (a) to find an expression for the Oscillators per-unit change in frequency of oscillation resulting from a phase-angle change of φ. state when triggered. The bistable multivibrator has two stable states and ator. late at the frequency at which the total phase shift around When triggered. has one stable state. and the condition Hint: tan y = dx 1 + y2 dx that A and K must satisfy for sustained oscillation. in which it can remain indefinitely. and the nonlinear oscillator or function gener. or greater than. also known as a one-shot. Find the frequency of oscillation. and astable.1428 Chapter 18 Signal Generators and Waveform-Shaping Circuits Summary There are two distinctly different types of signal gener. or by using an amplifier having a nonlinear There are three types of multivibrator: bistable. the amplitude will increase until a nonlinear between two quasi-stable states. can LC-tuned or crystal-tuned oscillators are utilized. in the amplifier transfer 18. It changes with a multivibrator circuit. A comparator with hysteresis is A linear oscillator can be realized by placing a bistable. and resistors. * = difficult problem. a predetermined interval. which employs a switching mechanism implemented can remain in either state indefinitely. frequency-selective network in the feedback path of an A monostable multivibrator. circuit for IC implementation at frequencies as high as hundreds of gigahertz. be used with external resistors and a capacitor Popular configurations include the Colpitts circuit for to implement high-quality monostable and astable discrete-circuit implementation and the cross-coupled multivibrators.1. a pulse of known width. evaluated at ω = ω0 .3 For the oscillator described in Problem 18. with op amps or transistors. For higher frequencies. at its output. show that.1: 18. and a positive center-frequency d −1 1 dy gain K. independent of the value of A and K. thus generating. A sine-wave shaper can Crystal oscillators provide the highest possible frequency be implemented either by using diodes (or transistors) accuracy and stability. If in an oscillator the magnitude of loop gain is greater An astable multivibrator has no stable state. Op-amp circuit implementations function.2 For the oscillator circuit described in Problem 18. unity. resonance. and the active-filter-tuned oscillator A feedback loop consisting of an integrator and a bistable are popular configurations for frequencies up to about multivibrator can be used to generate triangular and square 1 MHz. fier having a frequency-independent gain A (where A is posi- tive) and a second-order bandpass filter with a pole frequency ω0 . which utilizes some form of that require high precision. and the slope in the limiting regions is to be at a frequency ω0 . Let the transconduc.4(a) with Rf removed of Fig. Figure P18. transfer characteristic is shifted along the v I axis to the point v I = − R1 /RB VB . *** = very challenging. what is the minimum gm required of 18. 18. 18.. (b) C. For sustained oscillations. P18. slope of the limiting characteristic is 0.6 In a particular oscillator characterized by the structure D 18.10 Denoting the zener voltages of Z1 and Z2 by VZ1 and VZ2 each transistor? and assuming that in the forward direction the voltage drop (a) (b) Figure P18. 18.7 V. ** = more difficult. what must the phase angle provided by ≤ 0. Find the value of AK that results CHAPTER 18 in poles appearing (a) on the jω axis. and (b) in the right half of the s plane. For what value of transconductance voltages of ±5 V and assume the voltage drop of a conducting Gm will the circuit oscillate? At what frequency? diode to be 0.05. and Q = 50.7. the oscillation to begin.9 Consider the circuit of Fig.5 An oscillator is formed by loading a transconductance amplifier having a positive gain with a parallel RLC circuit and connecting the output directly to the input (thus applying D 18.05 V/V.e.7 An oscillator is designed by connecting in a loop three ±V and for VB .7 PROBLEMS 18. Show that by connecting a dc source VB to shift and the minimum gain that the amplifier must have for the virtual ground of the op amp through a resistor RB . For the circuit to oscillate be 100 k. * = difficult problem. respectively. at a horizontal distance from the jω axis of C ω0 /(2Q). Sketch the transfer of 12 dB and a phase shift of 180° at ω0 . the frequency-selective network exhibits a loss to realize the comparator function. Find suitable values for all tance amplifier have an input resistance of 5 k and an resistors so that the comparator output levels are ±3 V and the output resistance of 5 k. The input resistance of the comparator is to and capacitance. The LC resonator has L = 1 μH. 18. R D 18. assume assume that R and C include the transistor output resistance that VD = 0). Neglect the diode voltage drop (i. and (c) R.8 Consider the circuit of Fig.3(a) find the percentage change in the oscillation frequency resulting from a change of +1% in the value of (a) L. and at v I = +2 V. Use power-supply C = 100 pF. Note that the bias circuits are not shown.1. Use standard 5% resistors (see Appendix J). 18.4 For the oscillator circuit in Fig. to realize the comparator function. D = design problem .4(a) with Rf removed positive feedback with a factor β = 1). Give the phase characteristic. each amplifier stage be? Give an expression for ω0 .10 = Multisim/PSpice. find suitable component values so that the identical common-source amplifier stages of the type shown limiting levels are ±3 V and the comparator threshold is in Fig. Utilizing available ±5-V dc supplies for 18. Problems 1429 lie at a radial distance of ω0 . (Hint: Use Eq. If at 10 kHz the op frequency for zero loop phase. P18.20 For the circuit in Fig.5 with R3 and R6 increased resistance. P18. 18. Find the frequency at which oscillations can occur in this case in terms of CR. will be the frequency of oscillation? (Assume that the phase shift introduced by the op amp remains constant for frequencies around 10 kHz.7 V. L(jω). 18. and 15 k. and use it to show that to locate the poles in the right *18. 18. and R2 /R1 for oscillation.18 Design the circuit of Fig.7 for operation 18. 18. find the loop gain Aβ by breaking the circuit at node X.15 X and find the loop gain (working backward for simplicity to = Multisim/PSpice.7°.2: Op Amp–RC Oscillator Circuits 18.5. Find ω0 and Q of the poles. what change must be made in the shunt resistor R1 R2 of the Wien bridge? Also.13 For the Wien-bridge oscillator of Fig.16.19 For the circuit of Fig.16 Repeat Problem 18.14 Reconsider Exercise 18. 18.15 For the circuit in Fig.15. break the loop at node Figure P18. D = design problem . Modeling each diode as a 0. peak-to-peak output of 8 V? What results if R3 and R6 are open-circuited? D **18.10. *** = very challenging.5.65-V battery in series with a 100- D 18. and find the center-frequency gain.5.12 For the Wien-bridge oscillator of Fig. For this modification (and ignoring the amplitude R C stabilization circuitry). sketch and clearly label the transfer 18. ** = more difficult. CHAPTER 18 show that the transfer function of the feedback network Va (s)/Vo (s) is that of a bandpass filter. (18.10) to find the poles of the closed-loop system.15 for the circuit in Fig. Give the expression for the pole Q.11. connect an additional resistor (R = 10 k) in series with the rightmost capaci- tor C.) Figure P18. let the closed-loop amplifier (formed by the op amp and the resistors R1 and R2 ) exhibit a phase shift of −3° in the neighborhood of ω = 1/CR. and C R find f0 . R2 /R1 must be selected to be greater potentiometer replaced by two fixed resistors: 10 k between than 2. what Assume the op amp to be ideal. 18.17 Consider the circuit of Fig. 18. find L(s).19. the at 10 kHz using R = 10 k. the op amp’s negative input and ground. What values are required for a sinusoid. use the expression for loop gain in Eq.11 For the Wien-bridge oscillator circuit in Fig.9. find the peak-to-peak amplitude of the output to reduce the output voltage. P18. D 18. 18. P18. Section 18.16 18. Find Rf for oscillation to begin. * = difficult problem. Assume the op amps to be ideal.) To restore operation to 10 kHz.7 with the 50-k half of the s plane. 1430 Chapter 18 Signal Generators and Waveform-Shaping Circuits PROBLEMS is approximately 0. to what value must R2 /R1 be changed? *18. characteristics v O –v I of the circuits in Fig. amp provides an excess phase shift (lag) of 5. find the peak-to-peak amplitude of the output sine wave. Show that the poles of the that RL includes ro of Q1 .6 nF. 18.24 For the Colpitts oscillator circuit in Fig. Let the resistance Rf be equal gain gm RL that ensures that oscillations will start. Problems 1431 CHAPTER 18 PROBLEMS Figure P18. .22 Using C = 1.10 without the limiter. on the configuration in Fig. derive 4V 1 1 1 an equation governing circuit operation and hence find the sin ωt + sin 3 ωt + sin 5 ωt + sin 7 ωt + . provide an estimate of the distortion in the output sine wave by calculating the magnitude (relative to the fundamental) of C1 I RL (a) the second harmonic (b) the third harmonic (c) the fifth harmonic (d) the rms of harmonics to the tenth Figure P18. 18.25 For the Colpitts oscillator circuit in Fig. π 3 5 7 frequency of oscillation and the condition the gain gm RL must = Multisim/PSpice.7 V.3: LC and Crystal Oscillators sinusoidal oscillations at 15 kHz. 18. If the diode drop is 0.20 find Vx in terms of Vo ).13(a) except that here the biasing circuit is included and the collector is placed at signal D 18.12 produces 10-kHz sine waves. find C and Rf to obtain Section 18.21 Consider the quadrature-oscillator circuit of find the frequency of oscillation and the condition on the Fig. . Assume to 2R/(1 + ). D = design problem .) L Q1 *18. where 1.23 Assuming that the diode-clipped waveform in Exer- cise 18.24. For R = 10 k. * = difficult problem. ** = more difficult.25.24 Note that a square wave of amplitude V and frequency ω is represented by the series 18. How do you modify the circuit to double the output amplitude? (Hint: A square wave with peak-to-peak amplitude of V volts has a fundamental component with 4V /π volts peak-to-peak amplitude.9 is nearly an ideal square wave and that the resonator C2 Q is 20. P18. P18. Simplify your final expressions characteristic equation are in the right-half s plane and given by assuming rπ is large. find the value of R such that ground. *** = very challenging. 18. Observe that this circuit is based by s (1/CR)[(/4) ± j]. the circuit of Fig. derive an equation governing circuit operation and hence *18. 27 For the Colpitts oscillator circuit in Fig. L Q1 C1 C2 RL I Figure P18.26 For the Colpitts oscillator circuit in Fig. Simplify your final expressions by assuming that rπ is large. Assume that RL includes the of the BJT is included in RL and neglect Rf (i. Observe that this circuit is similar to that in Fig. ** = more difficult. Rf ω0 L).28 = Multisim/PSpice.26. derive an equation governing circuit operation and hence find the frequency of oscillation and the condition the gain gm RL must satisfy to ensure that oscillations will start.28 is based on connecting a positive-gain amplifier (formed by Q1 . D = design problem . assume MOSFET’s ro . P18. P18.13(a) but with the bias circuit included and the base grounded.26 18.27 Fig. Assume that ro Figure P18.28 The LC oscillator in Fig. *** = very challenging. Q2 . derive an equation governing circuit operation and hence find the frequency of oscillation and the condition the gain gm RL must Q1 RL satisfy to ensure that oscillations will start.15 except for utilizing a different biasing scheme. Note that this circuit is based on the configuration of Figure P18. 18. and RC ) with a bandpass RLC circuit in a feedback loop.25 Rf 18.27. * = difficult problem. Simplify your final expressions by assuming rπ is large.e. P18.. *18. L CHAPTER 18 Q1 C2 I C2 C1 I RL L C1 Figure P18. 18. Neglect ro of the BJT. 1432 Chapter 18 Signal Generators and Waveform-Shaping Circuits PROBLEMS satisfy for oscillations to start. ) and R2 short-circuited. what is the output? (a) Derive expressions for the threshold voltages VTL and VTH (b) Describe the output if a sinusoid of frequency f and in terms of the op amp’s saturation levels L+ and L− . Sketch and label the transfer char- acteristic v O−v I .1 V.21(a) with and VTH = +1 V.7-V drop when conducting and that the op amp saturates at ±12 V. find the frequency of oscillation and the condition required for 18. and V.13. can the average of this sinusoidal input shift before the (b) Let L+ = − L− = 10 V. P18. Find R2 and VR that CHAPTER 18 (a) Replace the BJTs with their small-signal models while neglecting rπ and ro (to simplify matters). Assume that the output (a) Derive expressions for the threshold voltages VTL and VTH saturation levels of the op amp are ±10 V. What is the maximum diode will start.37 Design the circuit of Fig. (b) By inspection of the circuit found in (a). 18.34 with R1 eliminated the expression in Eq.1 V is applied at the input. and the op (c) If IRC is selected equal to 1 V. The op amp saturates at ±5 V. 18. average.9 V and VTH = +5. 18. If oscillations grow to the point that Vo is current? PROBLEMS large enough to turn the BJTs on and off. VTL = −1 V. Problems 1433 (b) Let L+ = − L− = V and R1 = 10 k.5 mA flows in the feedback resistor and a current of and connected to a reference voltage VR . Find the range over which the oscillation frequency can be tuned. and let C2 be fixed at 10 pF. Estimate the peak-to-peak amplitude of the output sine wave Vo .5-V-amplitude sine-wave input having zero positive-voltage source V through a resistor R3 . D 18. Assume that the diodes have a constant Section 18.32 Consider the bistable circuit of Fig. sketch and label the oscillations to start. By how much R2 . transfer characteristic with L+ = −L− = 12 V. 18. 18. result in threshold voltages of 0 and V/10. the op amp’s positive input terminal connected to a (a) For a 0.33 Consider the bistable circuit of Fig. If the transistor ro = 5 k. Express the latter as the minimum transfer characteristic v O−v I . R1 . The IC inductors available have L = 5 nH and Q = 10. Specify the in terms of the op amp’s saturation levels L+ and L− .18 with the crystal as specified in Exercise 18. Select *18.34 variable in the range 1 pF to 10 pF. ** = more difficult. have a constant 0. and R1 = 10 k.36 Consider a bistable circuit having a noninverting R1 = 10 k and determine R2 .5-V output levels and ±7. 1 mA flows through the zener diodes. Find output becomes a constant value? the values of R2 and R3 that result in VTL = +4.30 Consider the Pierce crystal oscillator of Fig. Let C1 be Figure P18. * = difficult problem. P18. 18. (Hint: Use the result in the statement leading to 18. V = 15 V. and VR .29 Design the cross-coupled LC oscillator of Fig. R1 .29. Design so that when v I = 0 V a current op amp’s negative-input terminal disconnected from ground of 0.7-V drop when conducting.31 Design the bistable circuit in Fig.25(a) to realize a transfer characteristic with ±7. The diodes are assumed to required value of (IRC ).22(a) with the threshold values.34 For the circuit in Fig. resistors. 18. voltages of the zener diodes and give the values of all R2 .35 Consider the circuit of Fig.16(a) to operate at ω0 = 20 Grad/s. 18. amplitude of 1.4: Bistable Multivibrators 0. D 18. D 18.5-V 18. find the required value of C and the minimum required value of gm at which Q1 and Q2 are to be operated.34. 18. show that the signal at the collector of Q2 will be a square wave of 1 V peak-to-peak. *** = very challenging. show that oscillations amp saturates at ±12 V. R3 . = Multisim/PSpice. D = design problem .21(a) to obtain a hysteresis of 2-V width. = Multisim/PSpice. Fig. P18. R2 = 16 k. 18.462. Design the circuit to obtain an output square Section 18. Using equal values for all resistors Triangular Waveforms Using Astable except R7 and a 0.27. D = design problem . Sketch 18. The circuit can be triggered by applying a positive input pulse D 18. In the stable state. Assuming Fig.41 The circuit of Fig. Use β = 0. *** = very challenging. Specify the zener voltage required.6: Generation of a Standardized wave with 5-V amplitude and 1-kHz frequency using a 10-nF Pulse—The Monostable Multivibrator capacitor C. Specify the values of all resistors *18. saturation voltages. v A = 0.22. ±13-V op-amp saturation levels. The frequency is to be 1 kHz.5: Generation of Square and noninverting integrator. Assuming ±13-V op-amp cise 18.43 Figure P18.5-nF capacitor. 18. that the pulse generated at the output will have a width T Implement the bistable circuit with the circuit of Fig. and v B = −Vref .25(b). 18. D *18. C1 R1 provides square waves of 10 V peak to peak and triangular CR. ** = more difficult. Also.43 shows a monostable multivibrator and the zenor voltage. v O = L+ . current of 1 mA. and design for a current in the resistive divider approximately equal to the average current in D 18. Assume that the output saturation levels of Vref the op amps are ±12 V. circuit. 18.2 mA. Note that this circuit has the interesting property that the pulse ing bistable multivibrator with an output limiter and a width can be controlled by changing Vref . For normal operation.41 Section 18.41 consists of an invert.39 Augment the astable multivibrator circuit of the values of all resistors.38 Find the frequency of oscillation of the circuit in and label the waveform at the integrator output.01-μF capacitor and specify the values of all resistors and the required zener voltage. arrange for the zener to operate at a minimum current of 1 mA.25(b).26(b) with an output limiter of the type shown in Fig. calculate the recovery time. given by Use a 0. 18. design a circuit that of height greater than Vref . design the circuit to obtain Multivibrators a square wave at the output of the bistable multivibrator of 15-V peak-to-peak amplitude and 10-kHz frequency. and give D 18. C = 5 nF.40 Using the scheme of Fig. design for a minimum zener and R = 62 k. Show the resulting waveforms of v O and v A .26(b) for the case R1 = 10 k. show waves of 10 V peak to peak.42 For the monostable circuit considered in Exer- the RC network over a half-cycle. * = difficult problem. Design for a minimum zener L + − L− current of 1 mA and for a maximum current in the resistive T = CR ln divider of 0. 1434 Chapter 18 Signal Generators and Waveform-Shaping Circuits R4 PROBLEMS R3 R2 R1 R7 R5 R6 CHAPTER 18 Z1 C Z2 Figure P18. . and thus TH will change 100-μs duration. that will ensure triggering? How long does the circuit take to recover to a state in which retriggering is possible with a normal output? Section 18. (a) For the astable circuit of Fig. find the values of V and R pulse of 10-μs duration. not remain equal to 23 VCC ). What is the minimum input step size the two extreme values of VTH . that whatever the value of VTH becomes. is selected so that when v I is at its peak. ** = more difficult. Specify the values of RA and RB . P18. This allows the user to change VTH externally (i.5.1.3. D = design problem . Find TH . Verify that the transfer mation. 0.6. 0.8: Nonlinear Waveform-Shaping Circuits Section 18. Then find the angles θ (where θ = 90° when and assuming that VTH can be varied externally (i. find the frequency of oscillation and the duty cycle of the resulting square wave when no external Figure P18. and possible.28. the output voltage is equal to the desired peak of the sine wave. 18.6 k. VTL always remains 21 VTH . 0. design a node VTH . and VCC = 5 V. RB = 3. Diodes find the frequency of oscillation and the duty cycle at have a drop of 0. we select the peak of the triangular waveform. 18. * = difficult problem.7. the value of R of 0 and VCC . that will yield an approximation to a sine waveform of 0.48 The node in the 555 timer at which the voltage is VTH (i.43 voltage is applied to the terminal VTH . in volts. (c) For the design in (b). PROBLEMS (b) For the case C = 1 nF.2 k. peak amplitude.7 V. To obtain a good approxi- and connected to an input voltage v I . 0. Problems 1435 CHAPTER 18 connected to an external terminal. Note. 18.31(a) to obtain a square wave with a 20-kHz frequency and an 80% duty cycle.55. expressing them in terms of VTH and VTL . 0. V.4.7: Integrated-Circuit Timers D *18.29 when the provide a crude approximation to a sine-wave output when Threshold and the Trigger input terminals are joined together driven by a triangular waveform. *** = very challenging. so characteristic v O –v I is that of an inverting bistable circuit that the slope of the desired sine wave at the zero crossings with thresholds VTL = 13 VCC and VTH = 23 VCC and output levels is equal to that of the triangular wave.49 = Multisim/PSpice.46 (a) Using a 0.1 V per decade. 18. changing Fig. and 0..2. This signal will cause VTH to change around monostable multivibrator to provide a negative output pulse of its quiescent value of 23 VCC . 0.. find the value of R that results in an output at the rate of 0. it need v I is at its peak) at which the output of the circuit. however.e.1 nF and 1 nF.7-V (b) If the 555 timer used in (a) is powered with VCC = 12 V.44 Using the circuit of Fig.7 V at 1-mA current. 0. D 18. Also. with other conditions the same as in (a). the inverting input terminal of comparator 1) is usually Figure P18. with a nearly ideal peak amplitude be capacitively coupled to the circuit op amp for which the saturation levels are ±13 V.47 Using a 680-pF capacitor. rederive the expres- sions for TH and TL . find its required value so that the is 0. *18. choose resistors of 100 k in your design. RA = 7. 18. Use the pulse width is increased to 20 μs.49 The two-diode circuit shown in Fig. 0. VTH no longer remains at 23 VCC ). Wherever correspondingly—a modulation process.e. let a sine-wave signal of a much lower frequency than that found in (b) and of 1-V D *18.31.e.45 Consider the 555 circuit of Fig. If the diodes D 18.5-nF capacitor C in the circuit of exhibit a voltage drop of 0. Use capacitors of 0.30(a).49 can 18. design the astable circuit of Fig.65. find v I corresponding to v O = 0. Note that a squarer can 18. and 2. the logarithm of the input voltage. *** = very challenging. 2. 1436 Chapter 18 Signal Generators and Waveform-Shaping Circuits PROBLEMS angle values obtained to determine the values of the exact sine where IS is the saturation current of the diode and VT is the wave (i. 6. two diodes.4VT .5VT .5VT .51 Show that the output voltage of the circuit in easily be produced using a single input (e. If the output is taken across R (i. * = difficult problem.6VT . and the peak amplitude of the input triangular wave is 6. D = design problem .51 is given by via a 0. between the two emitters).. Plot v O –v I and compare to the ideal curve given by vI v O = 2. the circuit is known as a logarithmic amplifier.6VT D1 A D2 D4 B D D3 C Figure P18.42VT sin × 90° Figure P18. clamping voltages you have chosen? say. Since the output voltage is proportional to circuit as a sine shaper.5VT . Assume all diodes to be identical. P18. v 2 > 0.25VT .e.. Such amplifiers find application in D 18. and two clamping voltages.5-k resistor (rather than the 1-k resistor shown). and thus find the percentage error of this thermal voltage.52 = Multisim/PSpice.50 Design a two-segment sine-wave shaper using a situations where it is desired to compress the signal range. 1. 0. 2VT . ** = more difficult. What are the formance for various combinations of input voltage of values. with 700-mV drop at 1-mA current.e. v 1 ) connected Fig. The circuit. where VT is the thermal voltage.42VT .53 Detailed analysis of the circuit in Fig.7-V transfer characteristic v O = −v 1 v 2 for v 1 . VT .52 Verify that the circuit in Fig. 18.8-k-input resistor. P18. vI v O = −VT ln . 0. vI > 0 **18. Provide your results in tabular form.g.34 shows IS R that optimum performance (as a sine shaper) occurs when the values of I and R are selected so that RI = 2. Check the circuit’s per- zero-crossing slope matches that of the triangle. 2 V.5 V.7 sin θ ). 18. 1 V.51 6.. Such a cir- diode to a value corresponding to that of a sine wave whose cuit is known as an analog multiplier.52 implements the CHAPTER 18 should limit the amplitude of the output signal via a 0. and 3 V. fed by an 8-V peak-to-peak triangular wave. 0.
Report "Microelectronic Circuits Sedra Smith 7th Edition [Problems].pdf"