Metodos_PCB

Technical InformationSelected Methods for Low-Noise Printed Circuit Board Design Neven Pischl EMC-TI101-R 16215 Alton Parkway • P.O. Box 57013 • Irvine, CA 92619-7013 • Phone: 949-450-8700 • Fax: 949-450-8710 10/07/04 REVISION HISTORY Revision EMC-TI101-R EMC-TI100-R Date 10/07/04 06/05/03 Change Description Update to revision 1 Initial release. Broadcom Corporation P.O. Box 57013 16215 Alton Parkway Irvine, CA 92619-7013 © 2004 by Broadcom Corporation All rights reserved Printed in the U.S.A. Broadcom® and the pulse logo are trademarks of Broadcom Corporation and/or its subsidiaries in the United States and certain other countries. All other trademarks mentioned are the property of their respective owners. Technical Information 10/07/04 TABLE OF CONTENTS Introduction .................................................................................................................................................. 2 Currents, Voltages, EM Field, and Frequency Spectra............................................................................. 3 Currents and EM Fields .......................................................................................................................... 3 Voltages and Currents in Time and Frequency Domains ....................................................................... 5 Effect of Duty-Cycle ......................................................................................................................... 6 Effect of Rise and Fall Time............................................................................................................. 7 Current vs. Voltage Spectrum.......................................................................................................... 8 Intentional Signals ..................................................................................................................................... 11 Single-Ended and True-Differential Signals .......................................................................................... 11 Microstrip Transmission Line and Current Distribution ......................................................................... 12 Differential Mode Radiation and Susceptibility...................................................................................... 15 Discontinuity in the Current Path .......................................................................................................... 16 Routing Across a Slot in the Plane ................................................................................................ 16 Changing PCB Layers ................................................................................................................... 19 Connecting Two or More PCBs ..................................................................................................... 20 Edges of the Planes .............................................................................................................................. 21 Traces Close to the Edges of the Planes ...................................................................................... 21 EM Field Propagation at the Edges of the Planes ......................................................................... 23 Unintentional Currents and Voltages ....................................................................................................... 25 Common Mode Voltage and Current .................................................................................................... 25 Sources.......................................................................................................................................... 25 Radiation from CM Currents .......................................................................................................... 28 Reducing Emission from CM Currents........................................................................................... 29 Crosstalk ............................................................................................................................................... 29 Switching Noise Between Vcc and L0 Planes ...................................................................................... 30 Decoupling and Bypassing ....................................................................................................................... 33 Ideal and Real Capacitors..................................................................................................................... 34 Inductance ............................................................................................................................................ 35 Parallel Capacitors................................................................................................................................ 37 Board Stackup ............................................................................................................................................ 39 12-Layer Example................................................................................................................................. 39 Discussion of the 12-Layer Example Stackup Features ................................................................ 40 Return Paths .......................................................................................................................... 40 B roa dcom Co rpo rat ion Document EMC-TI101-R Page iii Technical Information 10/07/04 Characteristic Impedances .....................................................................................................40 Crosstalk ................................................................................................................................40 Coupling Between Vcc and L0 Planes ...................................................................................41 Coupling Between Signal Currents and Power Supply Currents (Crosstalk Between Signals and Power) .............................................................................................................................41 Split Vcc Planes .....................................................................................................................42 Reducing the Number of PCB Layer Trade-Offs ...................................................................................42 Return Paths ..........................................................................................................................43 Crosstalk ................................................................................................................................43 Coupling Between Vcc and L0 Planes ...................................................................................43 Coupling Between Signal and Power Supply Currents ..........................................................44 References and Literature .........................................................................................................................48 References ............................................................................................................................................48 Literature ...............................................................................................................................................48 B roa dcom Co rpo rat ion Page iv Document EMC-TI101-R Technical Information 10/07/04 LIST OF FIGURES Figure 1: Hertzian Dipole.................................................................................................................................... 3 Figure 2: Trapezoidal Pulse Train in Time Domain ............................................................................................ 5 Figure 3: Slight Deviation from 50% Duty-Cycle Cause Significant Increase of Odd Harmonics....................... 6 Figure 4: Relative Amplitude of Trapezoidal Pulse Train Harmonics with Different Rise Times ........................ 7 Figure 5: Series (Source) and Parallel (Load) Termination of Digital Transmission Lines ................................. 8 Figure 6: Source Voltage (VS) and Load Voltages (VLS and VLP) with Series and Parallel Termination ......... 9 Figure 7: Current with Series and Parallel Termination (IS and IP).................................................................... 9 Figure 8: Frequency Spectra of IS and IP ........................................................................................................ 10 Figure 9: Examples of Intentional Signals Often Referred to as Differential in EMI Context............................ 11 Figure 10: Current Density Distribution in an Infinite Plane Under a Microstrip Trace and Magnetic Field Lines ................................................................................................................................................................. 12 Figure 11: Simplified Model of a Two-Conductor Uniform Transmission Line.................................................. 13 Figure 12: Transmission Line with Elements Assigned to Return Path............................................................ 14 Figure 13: Far-Field Electric Field from a Loop High Above Conductive Plane ............................................... 15 Figure 14: Continuous and Broken Current Paths for a Trace Above a Plane and Approximate Current Density Distribution in the Plane, Across the Slot and Perpendicular to the Trace ....................................................... 16 Figure 15: Model of a Transmission Line Running Across a Slot in Plane....................................................... 17 Figure 16: Routing Traces Across a Slot Significantly Increases Crosstalk Between Them ............................ 18 Figure 17: Cross-Section of a PCB Shows Discontinuous Current Path Due to Change of Layers................. 19 Figure 18: Example of Routing High-Speed or Susceptible Traces ................................................................. 20 B roa dcom Co rpo rat ion Document EMC-TI101-R Page v ...........................21 Figure 20: Dipole Model of Radiation Due to CM Impedance of a Plane.............................................................................1 µF Ceramic (X7R) Capacitor with Different PCB-Layout Inductances...............34 Figure 30: Minimizing Inductance by Arranging Vias for Minimum Loop Area (Shaded)............................................................................47 B roa dcom Co rpo rat ion Page vi Document EMC-TI101-R ...............................................................................................22 Figure 21: Pulling the Vcc Planes and Stitching the L0 Planes with Vias at the Edges...............................................................................................................................................39 Figure 35: High-Frequency Current in Power Distribution and Signal Current Do Not Flow Through Common Impedance in this Arrangement of PCB Layers Due to Skin Effect ...............................................................................................................................................................................................................................................Technical Information 10/07/04 Figure 19: Current Density Distribution in a Finite Plane Under Microstrip when the Trace is Close to the Edge.............................................................................................31 Figure 27: Ferrite Beads in Power Supply of Noisy Components Attenuate Noise Propagation on PCB........... and Parallel RLC Circuits Versus Frequency .....37 Figure 34: 12-Layer PCB Stackup Example ....25 Figure 23: CM Due to Impedance of L0 Lead—Ground Bounce ............ Series..41 Figure 36: 10-Layer Stackup Example for Discussion .......................................................24 Figure 22: CM Current Due to Impedance of Ground Return ...........45 Figure 39: Six-Layer Stackup with Two Internal Routing Layers .....34 Figure 29: Relative Impedance of C.....................................27 Figure 25: CM Currents on Cables Radiate Efficiently.........................26 Figure 24: CM Due to Load Imbalance in True Differential Circuits....35 Figure 32: Measured Impedance of a 0...............28 Figure 26: Signal Current and Cross-Conduction Current Surges Example.. Dimensions in Inches......................................................44 Figure 38: Improving Performance by Adding L0 Fills ..................................................................................................................................................................... L........................................................................................................................................35 Figure 31: Inductance of a Rectangular Loop.................43 Figure 37: Mechanism of High-Frequency Noise Coupling Between Power Distribution System and Routing Layers when Routing is Between Vcc and L0 Planes..46 Figure 40: Six-Layer Stackup with Improved Performance..........................................................................................................................................................................................................36 Figure 33: Impedance of Two Parallel Capacitors and Each Individual Capacitor ..........................................32 Figure 28: Series and Parallel RLC Circuits .......................................... it lived for more than 200 years and generates even nowadays a major problem in EMC. Based on this Franklin developed the lightning protection. a grounded iron rod.Technical Information 10/07/04 “Due to the brilliance of the flash one tends to believe that all current just disappears in the soil.C. Thus an incorrect conception of grounding was firmly rooted. P.T. Van Deursen Seventh International Zurich Symposium on EMC. Van Houten and A.” Grounding Philosophy. March 1987 B roa dcom Co rpo rat ion Document EMC-TI101-R Page 1 .J.P. Van der Laan.A. M. such as current flow and its path. There are many different sources and mechanisms of noise and EMI coupling that are often poorly characterized in a typical electronic system. In that sense. The emphasis within this document is given to the PCB-level design methods. Electromagnetic (EM) field cancellation. From the functional design point of view. and EMI. and associated technologies. it is offered to provide instructions of some of methods of reducing noise. Understanding noise and EMI is a multi-disciplinary field. describing various noise phenomena. involving high-frequency design. analysis of the known and unspecified design parameters. The intention of this document is to: • • • Show how the selected design techniques relate to fundamental concepts (e. Several references used in preparing this text are given. What gives it a complexity is the total number of mutually interacting factors that determine the noise-related performance.g. and EMI in circuit board design.Technical Information 10/07/04 INTRODUCTION This document was originally created as a description of some of the basic concepts in design for electromagnetic compatibility (EMC). because the PCB is often the critical design segment that affects noise. Ultimately. The same concepts that govern the design at the PCB level are also fundamental to designing at the system level. mechanical design. The described techniques apply not only to the EMC-design. current cancellation and inductance) Help readers acquire an intuitive understanding of the principles that define noise and EMI performance of a product Provide a concise reference for the electronic products designers interested in noise suppression at the PCB level The applicable theory needed for understanding the principles behind the described material is highlighted. In most cases. power supply. and application of the fundamental design principles are necessary for successful noise control by design. crosstalk. which makes the analysis or simulation difficult. Because of this. analog. the term Electromagnetic Interference (EMI) is more appropriate. many of them being parasitics. All considerations revolve around a few concepts. A deep and comprehensive theoretical analysis of all related design aspects is beyond the scope of this document. e.. they are often not well-understood and not the subject of study. and lowimpedance current return paths. susceptibility. digital. including emission. successful performance of a product is derived by detailed integration of all of the required parameters. power supply noise. and noise on the power distribution. A combination of the theoretical knowledge. B roa dcom Co rpo rat ion Page 2 Introduction Document EMC-TI101-R .g. While this document cannot assure that the required performance will result. experience. crosstalk. CM and differential-mode (DM) currents. They are generally good practices for noise suppression by careful printed circuit board (PCB) design. crosstalk. each contributor to the overall performance is easy to understand. the combination and interaction of these factors is unintentional. The magnitude of the currents and the paths in which they flow must be properly designed for both intentional and unintentional currents. and used materials. whether or not they are generated by: • • Intentional signals. EM FIELD. It is an infinitesimal current element carrying time-varying current i(t). such as electrostatic discharges (ESD) or nearby radio frequency (RF) fields The most important design consideration is to realize that almost all noise and EMI phenomena and design methods are directly related to the magnitude. EM Field. frequency spectrum. The Hertzian dipole is useful to describe the fundamental relations between the current and the EM field. Noise suppression mostly deals with unintentional currents. causing emissions and interferences Some external source that causes EMI and susceptibility of electronic equipment. the intentional currents generate unintentional results due to non-ideal properties of the real components (some of them called parasitics). voltages. It can be shown that such a short element of current generates a radial EM wave with the maximum in direction perpendicular to its axis. VOLTAGES. at the distance r from the Hertzian dipole. and impedances. and Frequency Spectra Page 3 . Because the element is short.Technical Information 10/07/04 CURRENTS. it can be assumed that the current distribution is constant along its length of dl. and path (size and shape of the loops) of the current. I dl r EMAX = η0 β0 Idl / (4 πr) HMAX = EMAX / η0 Figure 1: Hertzian Dipole I Current in the Hertzian dipole Intrinsic impedance of the propagation medium (η0 = 120π Ω in vacuum) Phase constant Wavelength Distance from the Hertzian dipole η0 β0 = 2π/λ λ r B roa dcom Co rpo rat ion Document EMC-TI101-R Currents. AND FREQUENCY SPECTRA CURRENTS AND EM FIELDS Intentional signals are usually well understood and taken care of during design. PCB. Voltages. Figure 1 describes the far-field EM components EMAX and HMAX in the direction of maximum radiation. Unfortunately. for every current flowing in one direction there must be current flowing in the opposite direction to close the loop. the impedance is dominated by the inductance of the current path. If two elements of the loop are parallel to each other and carry currents of the same amplitude in opposite directions.Technical Information 10/07/04 The time-varying current generates both EM field components. emission and susceptibility to EMI. The resulting EM field in the surrounding space is a superposition of contributions from each of the Hertzian dipoles. The E and H fields are related to each other by the intrinsic impedance η0 of the medium. While crosstalk and noise on the power distribution system are analyzed more often. and all currents must flow in closed loops between the source and the load. Poor transmitting antennas are also poor receiving antennas. if both current elements occupy exactly the same space. this management of current flow is the most effective way of designing for low-noise and EMI. coupling. A current loop can be modeled as a number of Hertzian dipoles that make the entire loop. The field strength increases with the current and length of the current element. As it is shown throughout this document. H=E/η0. and design principles for low noise have something to do with the fact that (again) all currents flow in loops. This leads to another key principle: Two adjacent currents of equal magnitude flowing in opposite directions minimize the total generated EM field. EM Field. the resulting total current is zero and does not produce any EM field. and the EM field cancellation that reduces noise generation. Current sinks do not exist. the E and H components of the EM field are orthogonal to each other and to the direction of the EM-wave propagation. Designing electronic systems for low EMI and low-noise requires recognizing where currents flow and which loops (paths) they take. which does not change the principle that all currents flow in closed loops. From the aforementioned. This explains the next principle for design to minimize EMI: Measures taken to minimize emission usually also minimize susceptibility to external EMI. The Hertzian dipole is useful to describe relations between the current elements and EM fields. EM radiation is proportional to the current and length of the current element. This can be applied to transmission lines. After some distance from the source. The design engineer should always remember the principles about currents flowing in the loops. paths. Nearly all noise. Currents exist as a consequence of a voltage across some impedance (load). and impedances associated with them. Voltages. At the limit case. Antenna theory shows that all passive antennas are reciprocal. the EMI problems often arise because the unintentional currents and these principles are ignored. and EMI generation and coupling mechanisms. and Frequency Spectra Document EMC-TI101-R . decoupling. but such an isolated current-carrying element does not exist. Except for the DC and low frequencies in the audio range. selection of a PCB stackup. crosstalk. The current loop defines the impedance of the current path. they tend to cancel each other’s EM field. in real electrical circuits. The voltage is not explicit in the relations that describe the EM field. and managing the amplitudes. B roa dcom Co rpo rat ion Page 4 Currents. grounding. or some of many other topics and methods of design. Reducing emission by building inefficient radiating structures tends to reduce reception of external interferences as well. and decreases inversely proportional to the distance. The size and shape of the loops can vary. It is also important to remember that the same principles apply to the intentional as well as the unintentional currents. and Frequency Spectra Page 5 . A constant value (DC component) is superimposed to the harmonics. and phase. pulse duration τ. They are defined in the time domain by their amplitude. duration.Technical Information 10/07/04 VOLTAGES AND CURRENTS IN TIME AND FREQUENCY DOMAINS Digital signals are voltage pulses with exponential rise and fall edges. amplitude. = Phase of the n-th harmonic. tR A τ tF t T Figure 2: Trapezoidal Pulse Train in Time Domain A pulse train with the period T. and period or frequency as depicted in Figure 2. Voltages. = Frequency of the n-th harmonic. with their frequency components (harmonics) each having its frequency. amplitude A. and rise time equal to the fall time tR = tF can be described as: ∞ X(t) = c0 + Σ | cn | cos (ωnt + Φn) n=1 = Amplitude of the n-th harmonic. B roa dcom Co rpo rat ion Document EMC-TI101-R Currents. It can be shown that such repetitive signals can also be represented in the frequency domain. cn fn = n/T Φn ωn = 2πfn c0 = A τ/T = DC component of the pulse train. EM Field. rise time. which can be approximated by trapezoidal voltage pulses. fall time. An example of the spectra with T/τ = 0. EM Field. The fn are multiples of the pulse repetition frequency f = 1/T.5 T/τ = 0.01T. for tR=tF =0. If T/τ = 0.49 Harmonic number (~ frequency) 1 2 3 4 56 10 20 30 1 2 3 4 56 10 Harmonic number (~ frequency) 20 30 Figure 3: Slight Deviation from 50% Duty-Cycle Cause Significant Increase of Odd Harmonics B roa dcom Co rpo rat ion Page 6 Currents. Relative Amplitude.5 and T/τ = 0. and Frequency Spectra Document EMC-TI101-R . The pulse train is represented in the frequency domain with a DC-component (c0) and harmonics at every multiple of the pulse fundamental frequency f = 1/T. If not. the even harmonics are present and can be strong for even a small deviation from 50% duty cycle as shown in the following figure. then the even multiples of the fundamental frequency disappear.Technical Information 10/07/04 Effect of Duty-Cycle The harmonics are cosine functions with the amplitude cn and the period ωn = 2πfn.49 is shown in Figure 3. Voltages. 20 dB/div T/τ = 0.5 (50% duty cycle). The spectral content falls off more rapidly at frequencies higher than fC = 1/πtR. bound by a –40 dB/decade slope. The spacing between the spectral lines equals 1/T. which makes them radiate better. EM Field. Increasing tR and tF reduces the higher frequency content of the signals. Openings in non-ideal shields are electrically larger at high frequencies too. Most of the energy is contained in the harmonics below the break frequency fc.05T fc Frequency Frequency Figure 4: Relative Amplitude of Trapezoidal Pulse Train Harmonics with Different Rise Times According to the equations for the E and H field from a current element from Figure 1 on page 3 and observing that βo = 2π/λ. Figure 3 on page 6 shows that faster rise times carry broader high-frequency spectral content. B roa dcom Co rpo rat ion Document EMC-TI101-R Currents. This can be done by not allowing the signal rise and fall times to be faster than necessary. The break frequency is determined by tR and tF.Technical Information 10/07/04 Effect of Rise and Fall Time The most significant (lower) harmonics are bound by a slope of –20 dB/decade. and Frequency Spectra Page 7 . which is the frequency of the pulses. 20 dB/div –20 dB/decade tR=tF =0. as shown in Figure 4. Because the potential for emission and interferences increases with decrease in the rise and fall times of the signal. Voltages. the spectral content of the signals should be limited to the minimum necessary for the operation. high frequencies can radiate more efficiently because the ratio of the wire length and the wavelength increases. –40 dB/decade Relative Amplitude.01T fc=1/2πftR fc tR=tF =0. Voltages. the current is the determining factor for the noise and EMI performance in most PCBs and devices. the terminating resistor is placed at the load side. Even though both schemes can result in acceptable voltage waveform at the load (which is the objective of the functional design). The analyzed circuit in Figure 5 is somewhat simplified and consists of a 50Ω transmission line with 5 ns propagation delay. and spectral content. The voltage waveform often does not disclose much of the current waveform. All clocks and high-speed signals are usually terminated with either series or parallel terminating resistors. In principle. In the other case. pulse voltage source. the series termination is more appropriate for single-load clock distribution. magnitude. transmission line termination also significantly influences the spectral amplitudes of the current in the traces. and a load represented by a 7 pF capacitor.delay= 5 ns VLS ZL= 7 pF IP Parallel termination Z0=50 Ω. IS Series termination VS= 1V tr= tf= 1 ns T= 10 ns 50 Ω Z0=50 Ω. which influences emission from the traces and crosstalk.Technical Information 10/07/04 Current vs. the magnitude of the current and its spectral content are critical to noise coupling. while parallel termination is better suited to multiple loads distributed evenly along the line. Used to reduce reflections. the current waveform and frequency content can be significantly different for these two termination schemes. EM Field. In one case.delay= 5 ns VS= 1V tr= tf= 1 ns T= 10 ns 50 Ω VLP ZL= 7 pF Figure 5: Series (Source) and Parallel (Load) Termination of Digital Transmission Lines B roa dcom Co rpo rat ion Page 8 Currents. The two most frequently used line termination schemes are series (or source) and parallel (or load) termination. Voltage Spectrum As it follows from the relation between the current and the EM field in Figure 1 on page 3. and Frequency Spectra Document EMC-TI101-R . but it is the voltage waveform that is normally of a concern for the system designers. However. the circuit is terminated with a series resistor with R= Z0=50Ω. but with some overshoot. both termination schemes are appropriate. the series-terminating scheme shows somewhat slower edges. EM Field.4V 0V –0.8V 0. the voltage waveforms at the load would be an identical reproduction of the pulse shape at the source after the propagation delay of the transmission line. The voltage waveform at the load with parallel termination has faster edges. which introduces a slight delay of the pulse at the load. as shown in the following Figure 7 and Figure 8 on page 10. These effects due to the non-ideal load can be slightly adjusted by the resistor value.2V VLS VLP 0. and C = 0 pF) and a lossless transmission line.Technical Information 10/07/04 With respect to the voltage at the load. VS 1. Voltages. With a perfect load (ZL = Z0. the amplitude and spectral density of current into the transmission line are considerably different for different termination schemes. Because of the finite load capacitance.4V 15 ns 20 ns 25 ns 30 ns 35 ns Figure 6: Source Voltage (VS) and Load Voltages (VLS and VLP) with Series and Parallel Termination Although the voltage waveforms at the load are similar. and Frequency Spectra Page 9 . Figure 6 shows the voltage waveforms for the two termination schemes. IS IP 30 mA 20 mA dIP dt >> dIS dt !! 10 mA 0 –10 mA 15 ns 20 ns 25 ns 30 ns 35 ns Figure 7: Current with Series and Parallel Termination (IS and IP) B roa dcom Co rpo rat ion Document EMC-TI101-R Currents. 5 0. This simplified analysis shows the importance of limiting fast current transients in reducing emission and noise coupling (crosstalk). the amplitude and spectral density of current are the main factors that determine emission and crosstalk.. Parallel termination can cause much larger spectral content of the current than series termination. As seen from the expressions for the electric and magnetic field in Figure 1 on page 3. When possible. the IP has larger potential for radiation and noise coupling than IS. Voltages.3 1.7 1. the time-derivative of current should be minimized (e. B roa dcom Co rpo rat ion Page 10 Currents.7 0.9 GHz Figure 8: Frequency Spectra of IS and IP Because the IP has much larger amplitude and time derivative than IS.1 0. using series termination resistors and slowest possible switching times in the active circuits) in order to limit the current spectral content and amplitude.5 1. and Frequency Spectra Document EMC-TI101-R .1 1. thus reducing the noise levels (including crosstalk and EMI) on PCB.g. EM Field.3 0.9 1.Technical Information 10/07/04 IS IP 15 mA 10 mA 5 mA 0 0. The other is another trace or a plane.Technical Information 10/07/04 INTENTIONAL SIGNALS SINGLE-ENDED AND TRUE-DIFFERENTIAL SIGNALS When discussing different signal types. Single-ended Trace True-differential Trace 1 Trace 2 Plane or trace at 0V Local reference 1 Local reference 2 Trace Parallel traces 0V plane Figure 9: Examples of Intentional Signals Often Referred to as Differential in EMI Context B roa dcom Co rpo rat ion Document EMC-TI101-R Intentional Signals Page 11 . the power supply planes and traces that are at a DC voltage level relative to L0 will be described as Vcc instead of the commonly used term power planes and traces. The current flows in loops formed by conductors. Similarly. the term L0 (logic zero) is more appropriate for the intentional 0V reference on the PCB. In true differential signals. In single-ended systems. it is worth noticing that in EMI jargon. Ground is one of the paths where the intentional current (as well as the unintentional current) completes its loop. Because the true-differential signal is between the two conductors. the term “differential signal” does not always mean true-differential signal. and the mode of intentional-signal propagation is called differential mode (DM) in either case. true-differential signalling doesn’t require the same local reference at the source and the load. The intended return path in the singleended systems is through the signal traces and reference planes or traces. where two conductors carry a signal with no reference to “ground” or logic 0 Thus. whether single-ended or true-differential. between a signal node and a reference potential (“ground”. in EMI context all intentional signals are often called differential. The term return path is also often used for the same purpose to describe the segment of the current loop other than the signal trace. The term ground is commonly and inappropriately used to describe the conductor with 0V or reference (logic zero) voltage level. Instead of the term ground. the intended conductors are pairs of traces or wires. ideally at the reference voltage (often at 0V). one conductor is typically a signal trace or wire. carrying voltages and currents of opposite polarity (shown in Figure 9). or reference) True-differential or “balanced” signals. In EMI context. logic 0. and not tied to any external reference. differential signals can be intentional signals of two kinds: • • Single-ended or “imbalanced” signals. which is highest under the trace and falls with the square of the distance perpendicular to the trace. This distribution of current results in the minimum inductance in the current path. Practically. numerical methods need to be applied to calculate the inductance of microstrip lines. The figure also shows the approximate magnetic field distribution. H Inductance is a ratio of total magnetic flux linked around a conductor and the current that causes it according to: Φ L I S ∫ BdS I L Φ I B S = Inductance = Magnetic field flux = Current = Magnetic flux density = Surface area of integration Theoretically. = Total current in the trace. = Height of the trace above the reference plane. Approximate magnetic field lines i(D) Trace H Infinite conductive plane –3H 3H D ≈80% of total current flows within ± 3H Figure 10: Current Density Distribution in an Infinite Plane Under a Microstrip Trace and Magnetic Field Lines i(D) ≈ i(D) I0 I0 1 1 + (D / H)2 πH = Current density in the plane at the distance D from the center of the trace [see reference 1]. All magnetic field lines are located above the infinite plane. which means that the inductance of an infinite conductive plane is zero.Technical Information 10/07/04 MICROSTRIP TRANSMISSION LINE AND CURRENT DISTRIBUTION Figure 10 shows the distribution of current density in the infinite plane under microstrip. B roa dcom Co rpo rat ion Page 12 Intentional Signals Document EMC-TI101-R . All magnetic field flux flows through the surface between the trace and the plane. The current that flows in the plane does not create any magnetic flux linkage around it. selecting the surface of integration perpendicular to the plane and between the trace and the plane yields inductance per unit length of a microstrip. and there is no magnetic field that encompasses an infinite plane. with infinite plane of infinite conductivity. these elements equal zero. Any impedance discontinuity causes reflections. Partial inductance can be assigned to the portion of the inductance associated with a segment of the total current loop (such as between the trace and plane. there are no reflections. But they can be considerable in real cases where two non-ideal conductors form the line. or between two traces). which in turn degrades the signal quality. in a uniform transmission line). the more current in the plane is concentrated under the trace and the less it spreads out.g.Technical Information 10/07/04 The closer the trace is to the reference plane. and c in L-shape. r l g c r l g r c l g c r l g c r l g c = per-unit-length resistance = per-unit-length inductance = per-unit-length conductivity = per-unit-length capacitance Ideal return path Figure 11: Simplified Model of a Two-Conductor Uniform Transmission Line The characteristic impedance Z0 of a transmission line is: r + jωl Z0 = g + jωc ( l = c for lossless lines ) When Z0 is constant along the line (e. lumped per-unit-length elements of r. The simplified model from Figure 11 does not show the contribution to the r and l coming from the return path. and can increase emission and crosstalk. B roa dcom Co rpo rat ion Document EMC-TI101-R Intentional Signals Page 13 . For narrow traces. approximately 80% of the total current in the plane is within 6H (±3H) from the center of the trace. l. In ideal case. g. One possible electrical model of a uniform transmission line is a cascade of electrically small.. depicted in Figure 11. and resistance. B roa dcom Co rpo rat ion Page 14 Intentional Signals Document EMC-TI101-R . where the lT and lR are partial inductances with their mutual inductance lM.Technical Information 10/07/04 Figure 12 shows how rT and lT can be assigned to the trace. emission. inductance. Because the real-life planes and traces have finite size. = For return planes made of good conductors. = Total inductance of a line segment. Similarly. = For wide return planes made of good conductors. they have finite impedance. Only for perfectly conducting and infinite planes. and susceptibility. = For true-differential signal paths. “Edges of the Planes” on page 21. crosstalk. rT lT g rT c rR rT lT rR lR g c lT g lR rT c rR lT g lR rT c rR lT g lR c rR lR = per-unit-length resistance of the trace = per-unit-length partial inductance of the trace = per-unit-length resistance of the return = per-unit-length partial inductance of the treturn = per-unit-length conductivity = per-unit-length capacitance Figure 12: Transmission Line with Elements Assigned to Return Path r= rT + rR rT >> rR rT = rR l = lT + lR – 2lM lT >> lR lT = lR = Total resistance of a line segment. = For true-differential signal paths. The resistance rR and the partial inductance lR of the return paths form CM impedances: lR = lCM CM inductance rR = rCM CM resistance Throughout this document (especially in “Discontinuity in the Current Path” on page 16. and “Common Mode Voltage and Current” on page 25) it is shown that CM impedance (especially inductance) can largely affect EMI performance of a system by causing noise. rR = 0 and lR = 0. rR and lR denote the resistances that can be assigned to the return path. 5 x 10–16 f2 AI/r Electric field strength in V/m. it takes less current or loop area to exceed the emission limit.8 in2 (5 cm2) is enough to fail the class B emission limit of 40 dBµV/m (100 µV/m) at the 3m distance. Frequency in Hz.Technical Information 10/07/04 DIFFERENTIAL MODE RADIATION AND SUSCEPTIBILITY The EM radiation from a loop is proportional to the product of the current and the loop area. Currents flowing in larger loops may generate significant radiation. Loop current in amperes. the intentional signal loops are small because the signal and return paths are adjacent to each other. E f A I r The factor of 2 in the equation accounts for constructive interferences due to reflections from the plane. → E = 2 x 131. The following equation shows how a loop high above a conductive plane (shown in Figure 13) generates a maximum far-field electric field at a distance r that is proportional to the loop area. which minimizes the radiating loop area. r r Direct path LOOP above plane E LOOP above plane Reflected path Conductive plane plane Conductive ground Figure 13: Far-Field Electric Field from a Loop High Above Conductive Plane The current of 25 mA at 30 MHz in a loop area of 0. Well-designed intentional signals are poor receiving antennas by the same mechanism. and the square of the frequency [see reference 2]. especially if the radiating structure is exposed (such as on the outer layers of an unshielded PCB or in a ribbon cable). This generally makes such loops poor antennas. At higher frequencies. B roa dcom Co rpo rat ion Document EMC-TI101-R Intentional Signals Page 15 . In a well-designed system. Loop area in m2. so they tend to have fewer problems with susceptibility to external EM fields (such as during ESD events or in vicinity of strong EM field radiators). the radiation from intentional signals is not typically excessive relative to EMI requirements as long as the loop size is very small. Typical loops on multilayer PCBs are formed by traces that are only 5–7 mils high above the adjacent reference plane. current. The DM radiation from electrically large or resonant loops may cause significant radiation. Because of the EM field cancellation by the proximity of two opposing currents. so the loop area may still be small even for the relative large lengths. Distance from the loop in m. and the same principles that govern design for the intentional signals must be considered when designing suppression of the unintentional signals. Across the Slot and Perpendicular to the Trace x B roa dcom Co rpo rat ion Page 16 Intentional Signals Document EMC-TI101-R . The same is true for the unintentional currents. This may be a case when the board traces are running close to the edges of the board in the vicinity of metal mechanical parts such as card guides or board stiffeners. and does not minimize the resulting EM field emission and coupling. Poorly designed current path does not take advantage of current cancellation (see “Currents and EM Fields” on page 3“). but they fall off rapidly with the distance. Routing Across a Slot in the Plane The most obvious example of a poorly designed current path is routing across a slot in the plane as shown in the lower part of Figure 14.Technical Information 10/07/04 The EM fields generated by a poor radiator may still be relatively strong in the close proximity of the radiator. it can be a cause of secondary radiation of much stronger EM field. crosstalk and EMI issues if routing layers are adjacent to such non-continuous layers. the EMI and crosstalk are minimized. The most significant potential for well-designed intentional signals to cause excessive radiation is to couple the near field into an electrically large adjacent structure. where the current cannot flow in such a way that there is always adjacent current of the opposite direction. or if they are close to the I/O area on a PCB and couple with the signals that connect to the cables. which can create considerable noise. If that structure is electrically large. iD Current in plane flows mostly under the trace SLOT D Traces above plane Current in plane flows around the slot Additional magnetic flux increases inductance Figure 14: Continuous and Broken Current Paths for a Trace Above a Plane and Approximate Current Density Distribution in the Plane. Such slots or gaps often exist in Vcc layers that carry multiple voltages. When the minimum-area current path formed by two opposing currents flowing adjacent to each other is provided. DISCONTINUITY IN THE CURRENT PATH The most common source of increased EMI and crosstalk related to the intentional signals is a poorly designed current path. Trace width in inches. LSLOT ≈ 5Dln(D/w) LSLOT D w Inductance in series with the transmission line in nH. If the proper path is not provided.Technical Information 10/07/04 The current cannot cross the gap under the trace. Perpendicular length of current diversion from under the trace in inches. B roa dcom Co rpo rat ion Document EMC-TI101-R Intentional Signals Page 17 . It diverts its flow around the slot instead. because it must flow in a closed loop. rT lT g rT c rP lT g lP c Lslot rT lT g rT c rP lT g lP c rP lP rP lP Figure 15: Model of a Transmission Line Running Across a Slot in Plane The following shows how an approximation for the added inductance can be calculated [see reference 1]. the current still finds a way to close the loop. Increased magnetic flux near the slot increases inductance in the line as shown in Figure 15. The EM field under the trace over a continuous plane is mostly confined to the region adjacent to the trace. the following consequences of routing across a slot in the plane can be seen: • • The current makes much larger loop. trace 1 plane trace 2 Current in plane must go around the slot Mutual inductance between traces increases L due to slot Figure 16: Routing Traces Across a Slot Significantly Increases Crosstalk Between Them By considering the current path around the slot in Figure 14 on page 16 and the equivalent model of the transmission line from Figure 15 on page 17. and depending on its size. can radiate as a dipole antenna. The segment directly over the slot may be viewed as a Hertzian dipole.Technical Information 10/07/04 Another point of view of the same physical structure can be obtained by looking at the EM-field propagation. On the other hand. because at the larger distances the currents in the trace and in the plane tend to cancel each other’s EM field. Increased inductance degrades signal rise and fall times. This generates unintentional signals and causes shift of the reference voltage on different segments of the reference plane. It radiates an EM wave that propagates along the slot. Susceptibility to ESD. This significantly increases mutual inductance and common impedance coupling resulting in significant crosstalk. they couple the maximum amount of the EM field and are exposed to increased crosstalk (shown in Figure 16). Any external EM field (such as generated by ESD or a nearby transmitter) easily couples to the traces across the gap and can cause interferences. Inductance increases in the region of the slot. The current flow through the increased impedance creates a voltage difference across the return plane on the two sides of the gap. in the area above the slot the current in trace does not have adjacent current in opposite direction. The slot is a waveguide that can efficiently guide the EM energy to other areas on the board. If other traces are routed above the same slot. This voltage drop across the reference plane often creates significant signal integrity and EMI problems. • • • B roa dcom Co rpo rat ion Page 18 Intentional Signals Document EMC-TI101-R . A metal structure close to such a slot (such as an I/O section with attached cables or adjacent board) can easily couple the increased EM field energy from the trace that crosses the slot and efficiently radiate. If two or more signal traces are routed across the same slot. Coupling of external fields increases due to increased EM-field pickup by the larger inductance. each will have current in the plane flowing through the same increased inductance. or RF fields can be a major EMI problem in such an example. which increases magnetic flux and emission. electrical fact transients (EFT). which primarily appears as increase in the plane inductance. with equally strong potential to increase noise and crosstalk and decrease EMI performance of a product. If the routing changes from top to the internal layer 1 that is immediately on the other side of the same plane (such as Plane 1 in Figure 17). Such routing is in effect similar to routing a trace across a slot in a plane. If they are not immediately adjacent to the signal vias. It can easily couple with other vias that do not have an adjacent return path. then the current stays within the same return plane adjacent to the signal trace.Technical Information 10/07/04 Changing PCB Layers Discontinuities caused by a slot in the return plane are an obvious example of a poorly designed current path. The current must somehow cross between the planes 1 and 2. planes must find planes to transition between Plane 1 Plane2. This trace is routed adjacent to a single reference Plane 1 Top Plane 1 Inner layer 1 Regions of added inductance Inner layer 2 Plane 2 Bottom Current in planes must close path through nearby capacitors or vias Some segments of of this trace are routed adjacent to Plane and some are adjacent to Plane 2. This via-to-via coupling is one of the strongest noise-coupling mechanisms on most PCBs. The signal vias that do not have adjacent return paths create radial EM waves (similar to Hertzian dipoles) that propagate between the planes. the inductance in the current path can significantly increase. They are equivalents to routing across a slot. Unless a path is intentionally provided. The Some segments this trace are routed adjacent to Plane 1 1. which is again similar to the case of two traces crossing a slot. and some are adjacent current in the The current in thethe path must hop between Plane1 andand Plane 2. especially of noise due to logic switching and current surges in through-hole pins and vias of the active components. the current crosses the planes at the locations of nearby vias and bypass capacitors. to Plane 2. One case is when signal traces change layers as shown in a cross-sectional view of a PCB in Figure 17. and the current path is still continuous in Plane 1. The path of the current in the planes adjacent to the trace that changes layers between bottom and inner layer 2 is not continuous. A trace routed on the top of a board with a return plane in the adjacent layer (Plane 1) has a continuous return path in the adjacent plane. Two other frequently encountered cases of discontinuous current paths are maybe less obvious. Figure 17: Cross-Section of a PCB Shows Discontinuous Current Path Due to Change of Layers B roa dcom Co rpo rat ion Document EMC-TI101-R Intentional Signals Page 19 . 1. B roa dcom Co rpo rat ion Page 20 Intentional Signals Document EMC-TI101-R . the location of such vias or capacitors is critical and must be adjacent to the signal vias. The nearby return current path should be provided through direct connection in the connector pins. inductance of the connection between the planes through the capacitors must be low. For the most critical signals (with high spectral components or the most susceptible ones). preferably without or with minimum layer transitions. as illustrated in Figure 17 on page 19 and Figure 18. It can flow through the nearby decoupling capacitors on either side of the connector if provided.Technical Information 10/07/04 Even if the nearby vias or capacitors are relatively close to the signal transition. Significance for EMI of the concept of return current flow pointed out by W. It is best to keep the current path continuous in the same plane by routing as shown in Figure 181 [see reference 1 and reference 3]. If capacitors are used. The most critical traces should be routed preferably without changing layers. It is critical how the traces change layers between the source and the load. Michael King of Costa Mesa. they add impedance in the return path. To minimize this discontinuity due to the transition between the boards. To minimize the effect of discontinuity in the current path. then the return current in the planes must find a path to flow from one plane to the other at the connector. as in Figure 18) can provide intentional return close to the connector. providing there are decoupling/bypassing capacitors and L0 vias available to facilitate return paths at these locations. Added inductance at the interconnects between the PCBs can seriously degrade signal integrity and EMI performance if: • • • There are not enough designated pins for the return path in the connector They are not arranged to minimize crosstalk and inductive discontinuity (such as spread across the pin field and close to the critical signals instead of being grouped in clusters) The connector pins and leads are not suitable for the application In most PCB designs (especially cost-sensitive ones). the signals on both boards should be routed adjacent to the planes that are at the same DC voltages. Connecting Two or More PCBs Another frequently seen case of discontinuous current path is at the interconnect area between two different PCBs. If the return path on one board is through the reference 0V plane and on the other board the same trace is routed adjacent to a Vcc plane. Location of source Location of receiver Ground stitching vias Reference planes at logic 0 Figure 18: Example of Routing High-Speed or Susceptible Traces Traces can usually be connected to any suitable routing layer at the beginning and the end of traces directly under the source and load. but that can still cause a significant discontinuity in the current path. California. it is not possible to design or provide the continuous return path for all signals. the design goal should be to intentionally provide continuous current paths by careful layout. or changing only between the two sides of the same reference plane. and trade-offs must be made. Capacitors or stitching vias (vias that connect between the reference planes. That partial inductance is the same as the CM inductance of the plane (see explanation in Figure 12 on page 14). This causes shifts in the reference voltage levels. and causes CM currents in the attached cables. the magnetic flux does not link around the plane. The following is a simplified solution for the per-unit length CM inductance lCM in case when W>>H [see reference 5]. This effect also changes the line characteristic impedance. W/2 D Redistributed Re-distributed current current W/2 S trace H plane Figure 19: Current Density Distribution in a Finite Plane Under Microstrip when the Trace is Close to the Edge In the case of an infinite plane (as in Figure 10 on page 12). In the finitesize planes (as in PCBs). The situation is different when considering EMI . but typically does not cause any major signal-integrity issues. as shown in Figure 19. Inductance of the reference plane causes a voltage drop across the reference plane. and more fields can be coupled to nearby secondary radiators (such as the I/O section.Technical Information 10/07/04 EDGES OF THE PLANES Traces Close to the Edges of the Planes A conductor over an infinite (or wide) plane causes current distribution in the plane that resembles the one from Figure 10 on page 12. lCM= µ0 H 1 π W 1–4(1–2H/W)(S/W)2 B roa dcom Co rpo rat ion Document EMC-TI101-R Intentional Signals Page 21 .especially emission. high-speed traces and components should never be placed close to the edges of the reference planes. Linkage of the magnetic field around the finite-size plane has two major EMI-related effects: • • The EM field strength at the edge increases. This increases the partial inductance of the plane. The CM inductance of a plane is normally a small portion of the total inductance in the path between the trace and the plane. Because of this. card guides. generates CM voltages across the planes. and vent holes). Placing a trace close to an edge of a finite-size plane increases current density along the edge of the plane as in the following figure. The current that would have gradually decreased to infinity in an infinite plane is redistributed and concentrated at the edge [see reference 4]. but can be large enough to cause excessive emission (“Radiation from CM Currents” on page 28). some of the magnetic flux links around the plane. The increased CM inductance is a function of the trace distance from the edge D (or offset S from the center) and height H relative to the plane width W. The levels of CM generated through this effect may be orders of magnitude lower than the intentional signals. The DM current in the CM inductance induces the CM voltage of VCM. This model also illustrates why it is not a good practice to place connectors and cables on the opposite sides of a PCB.e. it is also proportional to the CM impedance (inductance).. which feeds the dipole. but it increases significantly as the trace approaches the edge.5) lCM (S/W=0) W ≈ (for H= constant) 2H Because the radiated electric field strength E is proportional to the CM voltage. The maximum increase of the lCM relative to a trace in the center of the plane is when S=W/2 (i.Technical Information 10/07/04 The important result is that the lCM is fairly constant over the wide range of S/W. Attached cables form a dipole antenna LCM= 0 IDM Plane IDM ICM LCM VCM= -LCM dIDM dt ICM DM Currnt IDM (including power switching and surges) generates VCM on the impedance of the plane. when the trace is directly at the edge): lCM (S/W=0. The maximum relative difference in emission ∆dBmaxE from a trace in the center and a trace at the edge can be calculated as: ∆dBmaxE ≈ 20 log ( W 2H )≈ ( ) W 10 log H –3 A model for the worst-case radiation due to CM inductance of the plane is a dipole antenna attached to the CM voltage source (shown in Figure 20). VCM is the source of CM current ICM and radiation from the attached cables Figure 20: Dipole Model of Radiation Due to CM Impedance of a Plane B roa dcom Co rpo rat ion Page 22 Intentional Signals Document EMC-TI101-R . 2 E r f IDMl f l IDM r = frequency = length of trace = DM current in trace = distance The minimum distance from a trace to the edge that does not cause worst-case radiation above a given E field strength can be found from the given expressions. If there is no low-impedance connection between the planes at the edge. Intentional currents (signal and power supply) through the increased inductance cause CM voltage across the plane and radiated emission from the attached wiring. and the attached antenna (cable) that is driven by the CM voltage developed over the total CM inductance LCM. B roa dcom Co rpo rat ion Document EMC-TI101-R Intentional Signals Page 23 . wire. and direct radiation from the edge is rarely a problem. a part of the field reflects and a part propagates to the outside because of the impedance discontinuity at the board edge. and radiation model. A more exact relation for the required distance from the edge should take into account the board and the trace geometry. seam or a PCB guide in a chassis). LCM MAX < E 73 r 60 ω IDMl ~ 0. The radiated electric field strength E is a function of the relative geometry of the trace and plane. In addition and similarly to the example with a trace close to the edge. This electrically large structure may then radiate efficiently and cause emission problems. pulling the L0 planes’ edges back. When the EM waves reach the board edges. The electrical size of PCB cross-sections is small. If there is any electrically large metal structure adjacent to the board edge (such as a cable. Signal and power supply vias and through-hole pins can be approximated by the Hertzian dipoles. Assuming a dipole model from Figure 20 on page 22. EM Field Propagation at the Edges of the Planes Another mechanism of radiation is related to the EM field propagation between the PCB planes and its fringing at the edges.Technical Information 10/07/04 An often used rule of thumb is to space the traces a certain distance away from the edges of the planes. and adding vias (or capacitors) at the edges of the planes shown in the following Figure 21 on page 24 [see reference 3]. where the distance is related to the dielectric thickness H between the trace and the nearest plane-layer. it is possible to find the maximum acceptable LCM MAX for the field strength E at the distance r under worst-case conditions. When the Vcc planes are sandwiched between the L0 planes. current. The PCB planes are low-impedance parallel-plane transmission lines. the magnetic field that links around the edge causes the plane partial inductance to increase. then the voltage between the planes at the discontinuity is increased due to transition from low impedance between the planes to high impedance (free space) medium. The field strength rapidly decreases with the distance from the edge. the fringing EM fields can be decreased by reducing the size of the Vcc planes. the fringing EM field can couple RF energy into this structure. the DM (intentional) current IDM in the trace and the plane. which generate radial EM waves that propagate between the planes. which can cause coupling and secondary radiation. Fields that wrap around the plane increase CM inductance of the planes L0 Vcc1 Cross-section of PCB planes EM waves propagate between planes Vcc2 L0 Stitching vias along the edge and pulling back the Vcc planes terminates the field lines. Pulling back external Vcc planes that are not sandwiched between the L0 planes can redirect the radiation. but not necessarily decrease it. To prevent this energy from radiating by some other mechanism (and to reduce it at the source in the first place). The impedance of the terminating elements should be chosen to minimize reflections by matching the characteristic impedance of the parallel-plate transmission line formed by the planes. interplane impedance. The fringing fields along the edges. are reduced too. B roa dcom Co rpo rat ion Page 24 Intentional Signals Document EMC-TI101-R . The stitching may reflect the EM wave back to the inside of the PCB. reducing the coupling from the edge and plane inductance Figure 21: Pulling the Vcc Planes and Stitching the L0 Planes with Vias at the Edges The stitched edges and pulled-back Vcc planes reduce the partial (CM) inductance of the planes because less of the magnetics field can link around the PCB planes. Just stitching the edges and leaving large areas of the PCB without connection between the planes can cause cavity resonances that increase noise and emission at the resonant frequencies of the PCB. Again. it is necessary to have a uniform low impedance distribution of decoupling and bypassing to reduce this effect. it is necessary to have uniform low impedance between the planes that is provided by bypass and decoupling capacitors.Technical Information 10/07/04 L0 Vcc1 Cross-section of PCB planes EM waves propagate between planes Vcc2 L0 EM field at the edge can couple to adjacent conductors and cause secondary radiation. An array of lousy termination (R or series RC) between the planes along the edges can also reduce reflections from the edges by dissipating (terminating) the RF energy [see reference 6]. and stitching vias close to the signal transitions between different layers. As a consequence of the voltage VCM across ZCABLE. all wires of the cable. Device 1 DM Source Cable Device 2 DM Load IDM ICM ZCABLE Safety Wire ICM VCM VCM = IDM X ZCABLE ICM = VCM / (ZCABLE + ZPLANE + 2ZWIRE) Safety Wire ZWIRE ICM ZWIRE ICM ZPLANE Environment or Ground Figure 22: CM Current Due to Impedance of Ground Return Even without the safety wire. The connection between the logic reference and safety ground in each device (through the safety wire of the power cord in this example) has impedance ZWIRE. The CM currents originate due to imperfect. planes. Because the impedance ZCABLE of the return path is not zero. and chassis. and how to suppress them. and environment (such as reference conductive plane in the environment). and routing. so it is important to understand what they are. how they are generated.Technical Information 10/07/04 UNINTENTIONAL CURRENTS AND VOLTAGES COMMON MODE VOLTAGE AND CURRENT Sources The CM currents are the primary sources of emission from electronic devices. and do not necessarily follow the intended path of the designed DM signal currents. The CM currents take much larger loops and their path is often completed through the chassis. flow in the system return traces. B roa dcom Co rpo rat ion Document EMC-TI101-R Unintentional Currents and Voltages Page 25 . electrical signals. The system reference (shown as a conductive plane in this example) has impedance ZPLANE. cable. Figure 22 shows how the CM current is generated due to the impedance of the return conductor in the cable. and load. This connection is established by the capacitance between the chassis and the environment. The intentional DM current IDM between two devices flows in the loop through its designed path. or system environment outside of the chassis. there is always a connection between the circuits and environment ground (the chassis or a reference plane). I/O cables. and that the same design considerations for continuous current path with opposing currents adjacent to each other (as discussed in “Currents and EM Fields” on page 3 and “Discontinuity in the Current Path” on page 16) must be applied to CM currents as well for efficient EMI design. It flows through the loop consisting of device 1. device 2. It will be shown why CM currents radiate more than DM currents. the unintentional current ICM (shown superimposed to IDM) is generated. non-zero impedance (due to skin effect and inductance) of the current paths (especially in the reference conductors). consisting of the source. and the principal model of the previously described CM generation shown in Figure 22 still applies. The CM currents can still flow outside of the intentional DM path through these impedances. They are also caused by coupling (crosstalk) and imbalances in circuits. The CM currents can be superimposed to the DM currents. there is a voltage drop VCM across ZCABLE. and intra-system and inter-system cables and connectors. Therefore. The power surges and switching current peaks that flow in the L0 lead inductance induce CM voltage Vi on the L0 lead inductance. the same model applies to any circuit. This is usually referred to as ground bounce or power bounce. Figure 23 illustrates how CM currents are generated due to IC L0 lead inductance (package “ground bounce”). Although the drawing shows a differential driver. which can happen at all levels of a device from the silicon die. the intended signals cause voltage drops across these impedances. and there is a difference in voltage levels on each side of the common impedance (e.Technical Information 10/07/04 The ICM can be generated by the same mechanism on the PCB level or in the IC package. such as from: • • Inductance of the PCB reference planes Inductance of the component power supply leads and paths In each case. VCC IDM ICM Ip + L Vi = –L dIp dt Voltage induced by the current IP through L0 lead inductance creates ICM Figure 23: CM Due to Impedance of L0 Lead—Ground Bounce B roa dcom Co rpo rat ion Page 26 Unintentional Currents and Voltages Document EMC-TI101-R . PCB structures. and ICM can be superimposed to any input or output signals of an IC. ZCABLE and ZWIRE in Figure 22 on page 25) as a consequence. when the impedance of the return path is significant.g. through the IC package. all input and output DM signals have superimposed CM currents that is generated by Vi over the L0 lead inductance. B roa dcom Co rpo rat ion Document EMC-TI101-R Unintentional Currents and Voltages Page 27 . Figure 24 illustrates how imbalance dZL of the load impedance ZL creates CM current. Similarly. imbalance. or signal-waveform asymmetry (either in the amplitude or in timing) also generates CM currents. the CM can also be generated by any imbalance or asymmetry in the transmission path. including the source and load. any asymmetry in source output impedances.Technical Information 10/07/04 Particularly in true-DM signaling. or asymmetry of intentional signal waveforms. center-tap asymmetry if transformers are used. ~ ~ VD/2 IDM ZL/2 VD/2 ZL/2 ICM = 0 in ideal case ~ ~ VD/2 IDM dZL ZL/2 VD/2 ZL/2 ICM = VD/2dZL Figure 24: CM Due to Load Imbalance in True Differential Circuits IMPORTANT! All CM currents originate from the intentional DM signals (including power currents and surges) and some imperfection in the transmission path. the CM currents typically radiate considerably more even though their amplitudes are just a small fraction of the amplitude of the DM currents.Technical Information 10/07/04 Radiation from CM Currents The DM current in a well-designed system always has an adjacent return path. PCB in a metal enclosure PCB in a metal anclosure PCB Plane and its CM impedance ZCM VCM ICM ICM CABLE IDM is contained within the cable and total EM field is mostly cancelled ICM flows in a large loop without field cancellation Impedance between PCB and enclosure Figure 25: CM Currents on Cables Radiate Efficiently When the radiation from cables is maximized. B roa dcom Co rpo rat ion Page 28 Unintentional Currents and Voltages Document EMC-TI101-R . the radiation caused by DM currents is usually not a significant contributor to the total radiation from electronic devices. or directly from the PCBs or IC packages. The CM currents can flow in significantly larger loops. Because the EM field cancellation is hard to achieve for the CM currents. without adjacent current of the same magnitude and opposite direction. [V / m] r = Far-field distance from the antenna IMPORTANT! Only 5 µA of RF current in one wire is sufficient to fail the EN55022 class B limit of 40 dBµV/m (which equals 100 µV/m) at the measurement distance of 3m. The maximum electric field of a resonant dipole is: → Emax = → 60 Imax r → Imax = The maximum current along the antenna . Figure 25 is an illustration of a possible difference in the paths of Dm and CM currents. Realizing this. and intentionally providing low-impedance return paths for DM and CM currents and minimizing DM and CM current loop areas at the PCB and system level design is one of the key methods for reducing radiated emission. Lowering the levels of CM noise on a PCB in a system or in the IC package also lowers the level of CM currents that cause radiation from cables and slots in shields. it can be approximated by radiation from the resonant monopoles or dipoles. Because the radiation from two currents of the same magnitude flowing in opposite directions adjacent to each other tends to cancel out. . The DM crosstalk is often evaluated as a part of the functional analysis of circuits. continuous reference planes. Static traces (such as LED traces) do not carry intentional high-speed signals. Common-impedance. which results in field cancellation and much smaller loop and lower return path impedance for ICM. For example.. that about 5 µA on one wire may be enough to exceed the emission limits. which is essentially control of the signal spectrum. as well as routing signals close to the reference and away from the edges of the planes. but usually carry unintentionally coupled high-frequency currents and voltages. The first two bullets show how to reduce CM voltage to reduce CM current. close coupling between the currents in traces and return planes and traces. or plane-to-plane) should also be considered. minimizing the loop area.Technical Information 10/07/04 Reducing Emission from CM Currents Reducing emission from CM currents follows the same basic principles as reducing emission from any currents. It can be achieved by e. plane-to-trace. An example of the commonimpedance coupling is two signals flowing through a common inductance such as L0 lead or a slot in a reference plane. • This last bullet is one of the major factors to consider when designing a metal enclosure (chassis) and providing (or not) intentional contacts between the PCB and the chassis. but crosstalk is rarely well analyzed from the EMI point of view. • Because the CM currents originate from DM currents. Emission from ICM can be reduced by intentionally providing adjacent return paths for ICM. The ICM can radiate much more than IDM (often a couple of orders of magnitude). and also by reducing the amplitude of the intentional DM currents (e. they have the same spectral components and their amplitudes are related. determined by the proximity and the surface area of coupled circuits/traces Inductive. resulting from impedances in series with the common current path. Distance and the area of the current loops determine the amount of inductive coupling. • • • CROSSTALK Crosstalk is always a result of mutual impedances between two or more circuits. internal cabling in a system can be arranged in such a way that it is adjacent to the chassis. The amplitude of CM currents can also be reduced by increasing the impedance in the CM current path (such as by using CM chokes in the path of CM currents). B roa dcom Co rpo rat ion Document EMC-TI101-R Unintentional Currents and Voltages Page 29 . This level can easily couple from signal traces (especially from high-speed signals) and radiate if a trace is located close to the I/O section. This reduces CM voltage and CM currents and applies to all intentional current return paths. impedance of the current path. The crosstalk can be: • • • Capacitive. The DM-to-CM and CMto-CM crosstalk follows the same principles as DM-to-DM crosstalk. because there is no adjacent returncurrent path for ICM. low levels of crosstalk can cause emission failures if coupled to the I/O lines. The CM currents are generated by DM currents flowing through non-zero impedance in their return path. using series termination resistors at the source). Reducing the amplitude and the unwanted spectral components of DM currents by changing the intentional signal voltage spectrum reduces the same components of CM currents. the CM crosstalk (such as trace-totrace. due to the linkage of the magnetic flux between two current loops and the related mutual inductance. A voltage drop over the common impedance caused by one current modulates the other circuit and appears as coupled noise in the other circuit. between two or more traces. whether or not they are at L0 or Vcc levels. Some measures to reduce the impedance of the return path are providing wide. It was previously shown in Figure 25 on page 28.g. For EMI analysis. Even though it may not cause any significant functional problem. amplitude. The same considerations about the unbroken return path. Crosstalk between such traces and the I/O traces may cause major emission problems. especially the CM crosstalk. Crosstalk from the coupling between traces across a gap or between vias when PCB traces change layers has already been discussed in the context of discontinuous current path (see “Discontinuity in the Current Path” on page 16). filtering at the source or not using faster logic families than needed. solid (not perforated). and low impedance of the return path (which apply to the intentional DM currents) also apply to the CM currents.g. and/or the effectiveness of the radiating elements. which is the return path for CM currents within a metal enclosure. Routing signals perpendicular to each other on adjacent routing layers. and routing density on a PCB. This increases DM and CM noise on the PCBs. The interplane capacitance and inductance are the critical part of the total impedance at the higher frequencies. The characteristic impedance of the parallel-plate line depends on dielectric properties and the distance between the planes.Technical Information 10/07/04 Crosstalk between two traces on the same layer follows the same dependence on the height above the plane and distance from the traces as the distribution of current density in the plane under the traces (see Figure 10 on page 12). When the reference planes have RF voltage (‘ripple”) superimposed to their DC levels. K = Crosstalk coefficient H = Height of the trace above the reference plane D = Center-to-center distance between the traces crosstalk∼ K 1 + D2 / H2 [see reference 1] Crosstalk decreases inversely proportionally to the square of distance and increases with the square of height. SWITCHING NOISE BETWEEN VCC AND L0 PLANES High-frequency noise between the Vcc and L0 planes originates from switching current passing through the power supply pins. especially for all high-speed and I/O signals. The discrete capacitors determine the low-frequency impedance between the planes. typically starting at about a hundred or at couple of hundred MHz. Crosstalk is a form of EMI. Using series terminating resistors to terminate backward crosstalk and reduce ringing due to reflections. trace characteristic impedance. aperture arrays) Edges of the planes Skin-effect resistance Decoupling and bypassing capacitors can provide low impedance to minimize the RF voltages between the planes. Vcc and L0 pins of the switching digital devices) and under the transmission lines. Switching currents cause voltage drop on the plane impedance and RF voltages (noise) across the planes. low dielectric height between the traces and the L0 or Vcc plane) Providing a wide and continuous low-impedance return path. The factors that increase the impedance of the planes are: • • • • Inductance due to distance (dielectric thickness) between the planes Holes (slots. thus the same measures decrease EMI as well. and reduces noise merging on all signals. Effective ways to minimize crosstalk are: • • • • • • Using short traces Keeping large separation between traces (especially from the I/O area) and using planes between signals Routing close to the signal return (e. This also includes the return path for CM currents in cases when differential signaling is used.g. which cause induced RF currents and voltages on the planes. Minimizing crosstalk reduces emission and increases immunity and noise margin. Usually a compromise must be made between the sometimes opposing requirements for crosstalk. all circuits will also have these RF voltages superimposed to the signals. and impedance of the PCB power distribution system. Pins and vias are sources of radial waves between the planes. signal vias. Low impedance between the planes helps keeping the RF currents localized near the source (e. typically up to tens of MHz. A part of the total impedance between the planes also comes from the planes themselves..g. and preventing them from spreading throughout the board and system. B roa dcom Co rpo rat ion Page 30 Unintentional Currents and Voltages Document EMC-TI101-R . like the Hertzian dipoles. which form a parallel-plane transmission line with mutual capacitance and inductance. VCC ISURGE ILH CMOS Output IHL ZLOAD Figure 26: Signal Current and Cross-Conduction Current Surges Example B roa dcom Co rpo rat ion Document EMC-TI101-R Unintentional Currents and Voltages Page 31 . These large current spikes then cause a short-duration voltage drop on the power supply due to finite impedance of the power distribution system. this is a source of broadband noise that easily propagates over the entire power distribution system. The current in the power supply pins (shown in Figure 26) is composed of the signal current (ILH and IHL) and cross-conduction current ISURGE between the Vcc and L0 pins of a device.Technical Information 10/07/04 The most significant contributors to noise between the planes are power supply pins of devices that often carry fast and highamplitude current spikes at the transition of logic states. In addition. the ISURGE between the Vcc and L0 pins flows in short durations when both transistors are open (conducting) at the times of logic-state transition. Signal currents from multiple gates in digital devices can add up to significant total switching current in the Vcc and L0 pins. Due to the strong currents over a short period of time. The combination of cross-conduction current surges and signal current (especially when multiple gates switch simultaneously) is one of the most significant sources of noise on the PCBs. the same filter can filter the power supply for the PLL. With this technique. This can create discontinuity in the return-current path if the clock signals are routed adjacent to the Vcc plane and across such a gap. Such discontinuity can create serious EMI and functional crosstalk issues. Bypass capacitors can be used if the planes are not on the same voltage (e. Avoiding routing traces so that they change reference planes (keep them adjacent to the same plane). and reducing noise that propagates between the planes: • • • Placing low-impedance decoupling capacitors adjacent to all power supply pins of active devices. Figure 27 shows an example and measured relative amplitude of the noise voltage on the two sides of a ferrite bead. This protects the rest of the power distribution on the PCB from the noise generated in these circuit’s Vcc and L0 pins. IMPORTANT! A high-impedance gap between the Vcc and the Local Vcc is formed by insertion of the ferrite bead. Because the ferrite bead may present an inappropriate discontinuity in the return path of signals that may flow in the Vcc planes. Choosing the PCB stackups where Vcc and L0 planes are adjacent and close to each other.g. Careful consideration of the current paths as well as of decoupling and bypassing is needed. in addition to and in combination with decoupling capacitors at the power supply pins.. In the areas where many signals change reference planes (due to routing constraints. In the case of PLL circuits (which are also susceptible to the low frequency power supply noise).000000 GHz Figure 27: Ferrite Beads in Power Supply of Noisy Components Attenuate Noise Propagation on PCB The following measures are effective in providing adjacent current path for the currents in power supply pins and signal vias. but they are not as effective because they add more inductance in the current path than L0 vias. dBuV Local Vcc 120 Vcc 110 Local Vcc Vcc 100 90 80 70 33 MHz CLOCK DRIVER 60 50 40 30 20 Start: 1.Technical Information 10/07/04 One effective measure to decrease noise propagation on a PCB is filtering the power supply of high-bandwidth components with ferrite beads and capacitors. some routing is adjacent to a Vcc plane). which is typically done with the PLL and clock devices. caution is required when using this technique. • • B roa dcom Co rpo rat ion Page 32 Unintentional Currents and Voltages Document EMC-TI101-R . it is important to provide sufficient decoupling on the Local Vcc for proper operation of the device. Choosing to route only adjacent to the L0 planes and not adjacent to the Vcc planes allows adding the L0-stitching vias adjacent to the signal vias to provide return path. Providing evenly distributed bypassing capacitors across the board.000000 MHz Stop: 1. The capacitor on the VCC side of the ferrite bead enhances the filtering performance. this helps facilitate a low-impedance nearby return path for the signal currents. or close to connectors). This can be done by placing a number of capacitors between the Vcc and L0. with little ripple or RF noise superimposed. which reduces the discontinuity in signal-current flow in the reference planes and suppresses resonances between the Vcc and L0 planes at higher frequencies when the size of PCB planes is electrically large. f is frequency. A low-noise. To provide the low-impedance source of current at the Vcc and L0 pins. That impedance is a combination of total capacitance and series inductance in power distribution system on a PCB. bypassing. The maximum (rather conservative worst-case) allowable impedance of the power distribution can be calculated from the surge current Isurge and allowable ripple in the percentage of the Vcc. low impedance provided by capacitors and planes must be spread evenly across the board and close to the areas where the signals change reference layers or go through connectors. The power supply voltages on the board must be constant. In both cases. Zmax = VCC • x% Isurge •100 Impedance of capacitors and inductors is frequency-dependant. low-impedance power distribution system can be designed with proper decoupling. The total of switching currents and cross-conduction currents can exceed several amperes (even several tens of amperes) peak value for larger ICs. One is providing the low impedance source of current at the power supply pins of the components during logic transitions. and by spacing the Vcc and L0 planes closely together in the board stackup. the low impedance can be achieved by high capacitance and low inductance between the PCB planes or traces. the low-impedance capacitor must be located close to the pins of the active components and must be able to provide the charge to support the transitions of the logic states. and selecting appropriate PCB stackup. which reduces noise due to current surges through the impedance in the power distribution. The capacitors that provide the second function have to be placed in addition to the capacitors that provide source of current at the devices’ Vcc and L0 pins. To reduce discontinuities in the current paths and resonances between the planes. ω = 2πf B roa dcom Co rpo rat ion Document EMC-TI101-R Decoupling and Bypassing Page 33 . Decoupling and bypassing provide two functions. The other function is to provide distributed low-impedance between the planes. ZC= ωC ZL= ωL C and L Impedance of ideal capacitor Impedance of ideal inductor Capacitance and inductance. Ripple and high-frequency noise on DC levels caused by the current surges over the power distribution impedance may cause severe functional and EMI problems.Technical Information 10/07/04 DECOUPLING AND BYPASSING Designing a low-noise and low-impedance power supply system on a PCB is important for functional and EMI performance. Maintaining the DC power supply voltage Vcc constant within ∆V (allowable ripple) can be achieved by keeping the total impedance of the power distribution system low in the entire frequency range of interest. They have capacitance C.1 Ffres== res 11 2π LC 2π LC ZS ZP ZC ZL 0. Series. the impedance only depends on the inductance associated with the capacitor. and associated inductance L. as in Figure 28a. the low impedance is provided by the capacitance. equivalent series resistance ESR.1/ωC)2 C b) L |ZP| = 1/RP2 + (ωC . and it increases with the frequency. These three elements can form series or parallel resonant circuits (shown in Figure 28) with impedances ZS and ZP. the inductance must be kept low.001 0.Technical Information 10/07/04 IDEAL AND REAL CAPACITORS Capacitors used for decoupling are not ideal components. L. To minimize the high-frequency voltage ripple (noise) on the power distribution. as depicted by the graph in Figure 29.1/ωL)2 Figure 28: Series and Parallel RLC Circuits 1000 100 Impedance 10 1 0.01 0. Below the resonant frequency fres. B roa dcom Co rpo rat ion Page 34 Decoupling and Bypassing Document EMC-TI101-R . and Parallel RLC Circuits Versus Frequency Each capacitor is best described as a series resonant circuit. Above fres.1 1 10 100 1000 Frequency Figure 29: Relative Impedance of C. a) RS RP L C |ZS| = RS2 + (ωL . The vias that connect to the PCB layers can be placed close to each other and to the capacitor pads to reduce the inductance in series with a capacitor. Largest L Lowest L Figure 30: Minimizing Inductance by Arranging Vias for Minimum Loop Area (Shaded) The simplest and the most effective way to reduce the inductance is to reduce the loop area. pads and PCB traces or planes. Dimensions in Inches B roa dcom Co rpo rat ion Document EMC-TI101-R Decoupling and Bypassing Page 35 . It can be seen from the definition of inductance in “Microstrip Transmission Line and Current Distribution” on page 12 that inductance is a ratio between the magnetic flux in a closed surface and the current that causes the flux.16X10-9 [ x ln + y ln ] Figure 31: Inductance of a Rectangular Loop. so using socalled low-inductance capacitors (e. Figure 30 shows how the PCB layout can determine the inductance. which then are connected to the PCB layers. IMPORTANT! Inductance is dominantly affected by the loop area and not by the wire radius or trace thickness. Therefore. The shaded area represents the approximate loop area formed by the current flow. and three different ways to connect a capacitor to vias. with the loop dimensions in inches.g. Connecting the capacitor with wide traces does not significantly lower the inductance. the loop area must be minimized by the PCB layout. the total inductance is not inherent to the capacitor itself. The wire thickness does not significantly influence the inductance. as long as the dimensions of the surface are larger than the conductor thickness. with the capacitor on the PCB side that enables the shortest connection (illustrated in Figure 30).. which can be seen from the relation for the inductance of a rectangular loop in H in Figure 31 [see reference 1]. r 2y r 2x r y x L= 10. which is proportional to the inductance.Technical Information 10/07/04 INDUCTANCE The total inductance in series with the real capacitor depends on the entire loop area of the connection through the capacitor. To achieve the lowest inductance. reverse aspect ratio capacitors) does not provide any benefits if they are connected to the board through large total interconnecting inductance. The partial inductance of the capacitor itself becomes significant only when the total loop area has been minimized. 445 -45 Only L determines Z above resonance.1 µF Ceramic (X7R) Capacitor with Different PCB-Layout Inductances The following shows the relation in dB between the S21 (transfer impedance. Notice that the resonant frequency of 0. dB -15 Z. Ω 4. The impedance above resonance is determined by the inductance. compared with the bandwidth of digital devices.Technical Information 10/07/04 Building a low-inductance configuration of capacitor pads and vias into the PCB-layout shapes is an excellent way to guarantee a low and approximately constant value of inductance of all decoupling and bypass capacitors across the board.5 nH ranges between about 10 MHz and 20 MHz. 0. as measured with a network analyzer) and impedance Z [see reference 7]: 2|Z| |S21| = 20 log 4|Z|2 + Z02 + 4|Z|Z0 cosφZ For low values of S21 and Z.41 2 nH -35 ∆Ζ= 12-18 dB 0.45 Capacitive region -25 Inductive region 1. and not by the capacitance.141 -55 0. Figure 32 shows the measured impedance of a 0.5 nH 0. S21.1 µF capacitor with series inductance between 2 nH and 0.044 1 10 100 1000 MHz Figure 32: Measured Impedance of a 0. It is relatively very low. the following shows how the relation can be simplified: |S21| = 20 log 2|Z| Z0 |S21| = 20 log |Z| in a 50Ω system 25 B roa dcom Co rpo rat ion Page 36 Decoupling and Bypassing Document EMC-TI101-R .1 µF 0603 ceramic capacitor versus frequency and for various total series inductances. the physical layout of the capacitor connected to the PCB is more important than the capacitance. Controlling L is key to reducing impedance. Above the resonance. that may cause functional and EMI problems.1 µF.10 C1||C2 C1 || C2 C1||C1 C1 || C1 0.5 nH Impedance.01 1 1 10 10 Frequency.01 µF in Figure 33.1 uF.01 0. capacitor values that are closer to each other should be selected so that the parallel resonances do not develop. B roa dcom Co rpo rat ion Document EMC-TI101-R Decoupling and Bypassing Page 37 . and ESR.5 nH C 0. Selecting the values of parallel capacitors that differ by an order of magnitude can cause significant impedance increase at some frequencies.01 µF.00 0. C2 does not have any significant impact on the total impedance of the parallel combination at the low frequencies.1 µF and 0.00 10. such as the impedance increase around 30 MHz for the parallel combination of the 0. 1.5 nH 1 C1=0. Only C1 contributes significantly to the capacitive impedance below the series resonance of C1.001 µF).1 µF and 0. .Technical Information 10/07/04 PARALLEL CAPACITORS A power distribution system on a PCB is always created by a parallel combination of many capacitors. This is another reason for keeping the inductance low. 220 m? . Each individual capacitor’s impedance curve is also shown as a thin line. the total impedance between the series resonances exhibits parallel resonance and increase of impedance (see Figure 29 on page 34). as well as the impedance of two identical capacitors C1 in parallel (bold lines).1 µF and C2 = 0. Large L and low ESR result in larger relative impedance increase at the parallel resonance. 220 m? 1. 220 mΩ.1. which is not the best design practice.5 nH C2= 1 = 0. Figure 33 shows the impedance of two parallel capacitors C1 = 0.1 µF. If the inductance is identical for both capacitors. W 10.00 1. Z. MHz Frequency. the total impedance is a combination of two inductances in parallel. L. 1. 1. If the spectrum of the intentional signals contains frequencies that coincide with the increase of impedance. 220 mΩ. Depending on each capacitor’s C.5 nH C2 = 0. To provide low impedance that is free of parallel resonances in the frequency range of interest. This example also illustrates a commonly used decoupling scheme of populating a PCB with the capacitors of 0. Above the series resonance of C2. ? 1.5 nH C 0. the total impedance of the two capacitors is one-half of each individual capacitor’s impedance.01 µF.01 µF.10 0.01 µF (and 0. MHz 100 100 1000 1000 Figure 33: Impedance of Two Parallel Capacitors and Each Individual Capacitor Because C1>>C2. 70 mΩ.00 C2 == 0. 70mΩ.01 µF. 1. The tool should be able to take into account the transmission line properties of the power distribution system and proper RLC elements for the capacitors. A simulation tool can be useful for design of decoupling and bypassing. Figure 33 on page 37 also shows a total impedance of two capacitors with the same C. which results in lower total impedance at the lower frequencies. and impedance of all the other components that are connected to the power distribution system. the PCB planes significantly affect the total impedance of the PCB-level power supply. ESR. The major benefit of spacing the Vcc and L0 planes close together is the decrease of inductance between the planes. the most important effect is that the inductance between the planes decreases. B roa dcom Co rpo rat ion Page 38 Decoupling and Bypassing Document EMC-TI101-R . the key to lowering impedance at high frequencies is lowering the inductance. The likelihood of developing the parallel resonances is reduced and the total capacitance is larger than with mixed capacitor values. to minimize the parallel resonance impedance by using a number of capacitors of the same value. This does not significantly influence the high-frequency impedance. usually the largest capacitance for a given package size. At the frequencies above several hundred MHz. While it is true that the capacitance increases with decrease of the plane spacing. and L (C1||C1). Again. which is determined by the inductance. The significant consequence for EMI is that the CM-mode voltages across the planes are reduced when lowering inductance in the PCB-level power supply.Technical Information 10/07/04 It is also possible. Lowering the inductance of the planes reduces the impedance of the PCBlevel power distribution system. It should be noted that the discussion above illustrates the behavior of the capacitors and importance of minimizing the inductance when laying them out on a PCB. and a good practice. The total impedance of the power distribution system on the typical PCBs is a much more complicated combination of the discrete capacitors. impedance of the PCB planes. Technical Information 10/07/04 BOARD STACKUP PCB-level design should start by selecting the appropriate stackup. 12-LAYER EXAMPLE Figure 34 describes a well-performing 12-layer PCB stackup (assuming the standard PCB thickness of 62 mils). and low impedance path for all currents (see “Return Paths” on page 40) Tight coupling (close proximity and low impedance) between the Vcc and L0 planes (see “Coupling Between Vcc and L0 Planes” on page 41) Low crosstalk between the signals (routing) (see “Crosstalk” on page 40) Low crosstalk (coupling of noise) between the signals and the power distribution system (see “Coupling Between Signal Currents and Power Supply Currents (Crosstalk Between Signals and Power)” on page 41) Selection of characteristic impedances (see “Characteristic Impedances” on page 40) IMPORTANT! Consider the principles described in this section when defining the PCB stackup. continuous. The placement and routing guidelines for low-noise design are dependent upon the PCB stackup. The underlining principles for selecting a well-performing PCB stackup are: • • • • • Provision of solid. TOP ~ 5 mils L0 1 ~ 5 mils INNER 1 ~ 6 mils INNER 2 ~ 5 mils L0 2 Vcc 1 Vcc 2 L0 3 INNER 3 ~ 6 mils INNER 4 ~ 5 mils L0 4 BOTTOM ~ 5 mils ~ 2-3 mils ~ 6 mils ~ 2-3 mils ~ 5 mils Figure 34: 12-Layer PCB Stackup Example B roa dcom Co rpo rat ion Document EMC-TI101-R Board Stackup Page 39 . Various other PCB stackups can be constructed by following the same principle. The closer plane carries more of the return current. Routing the differential pairs as closely spaced traces in each pair and close to the PCB reference planes reduces crosstalk and susceptibility to EMI. The same is true for the signals that are routed only on Inner 4 and Bottom (compare to Figure 18 on page 20). so a portion of the return current flows in each plane. so appropriate measures may be required to avoid the discontinuities. with the reference in the L04 plane. As discussed in “Discontinuity in the Current Path” on page 16. depending on the signal bandwidth. it may be harder to achieve 100Ω differential impedance in the inner layers with the traces of each pair routed close to each other. The return currents are split between the two planes inversely proportional to the distance between the trace and each plane. With this stackup. Although vias can help reduce the inductance in the return path. their inductance may be noticeable. The resulting trace geometry should be a tradeoff between the sometimes opposing requirements for 100Ω differential impedance and for low crosstalk and EMI. Inner 1. Characteristic Impedances The 12-layer stackup from the example allows for easy manufacturing of the usual single-ended trace impedances and differential pairs with the differential impedance of 100Ω in the outer layers. it is relatively easy to add L0 stitching vias adjacent to the signal vias to reduce the discontinuity and inductance in the return paths of such signals. Again. Due to the FR4 dielectric properties. Increasing the dielectric thickness and/or increasing the separation between the traces can help increasing the impedance to achieve 100Ω. the main features of this stackup are: • • • Easy to maintain continuous current paths. Signals that are routed only on Top and Inner 1 have unbroken current paths (assuming no slots in the planes). The inner routing layers are sandwiched between two planes. because their current path closes entirely through the traces and only the L01 plane. B roa dcom Co rpo rat ion Page 40 Board Stackup Document EMC-TI101-R . Inner 4. or Inner 2 layers and any of the Inner 3. Changing the routing between any of the Top.Technical Information 10/07/04 Discussion of the 12-Layer Example Stackup Features Described in the following paragraphs. Any other transitions between the layers can result in a discontinuity of the current paths due to change of the adjacent reference plane (see Figure 17 on page 19). Crosstalk The most dominant crosstalk between the signals on the PCBs is a result of inductances. and “Switching Noise Between Vcc and L0 Planes” on page 30. signals crossing layers (Figure 17 on page 19) without the adjacent current-return path at the location of the signal-via can cause significant via-to-via crosstalk. or Bottom layers creates a similar problem. because all routing layers are adjacent to L0 planes Tight coupling between the adjacent and closely spaced Vcc and L0 layers Minimized crosstalk between the: Intentional signals Intentional signals and the current in the power distribution (switching and cross-conduction surges) Return Paths All routing layers have an adjacent reference plane at L0 voltage to provide the adjacent return path for all signals. and allows for denser routing. it is possible to add a plane stitching via adjacent to the signal via to provide the adjacent current return path (see Figure 18 on page 20). This 12-layer stackup can provide a low-crosstalk environment where it can be easy to maintain continuity of the current paths. Changing layers between Inner 1 and Inner 2 can cause a discontinuity in the current path because there may not be an adjacent path for the current to transition from L01 to L02. formed by either mutual coupling between the intentional current paths or by the discontinuous current path. “Crosstalk” on page 29. g. Because of this skin effect. the separation between these two layers should be maximized. can also be significant if there are parallel traces on the adjacent layers. which provides best decoupling between the Vcc and L0 planes.Technical Information 10/07/04 Layer-to-layer crosstalk between Inner 1 and Inner 2 layers. as shown in Figure 35. Coupling Between Signal Currents and Power Supply Currents (Crosstalk Between Signals and Power) For low crosstalk between the signal lines. the high-frequency (>100 MHz) components of the signal currents and currents that flow in the power distribution between the Vcc and L0 planes do not take the same paths and do not couple (crosstalk) over the common impedance of the planes. 2–3 mils in FR4).4 mils. Most of the Vcc1 current return flows on the Vcc1 side of the L02 plane (due to the skin effect). Minimizing the distance between the Vcc and the L0 planes can be achieved by selecting thin dielectrics (e. while most of the Vcc2 current return flows in the Vcc2 side of the L03 plane. it was shown in “Crosstalk” on page 29 that they should not share common impedances (mutual inductance and capacitance). The layer-to-layer crosstalk can be reduced if routing on any two adjacent layers is orthogonal (X–Y routing).. This mechanism can effectively separate the RF currents on each side of the PCB planes. which helps minimizing the noise on the power distribution system. most of the current (about 63%) is concentrated within one skin depth of the conductor. The standard thickness of the PCB planes is 0. Coupling Between Vcc and L0 Planes In any PCB stackup. Two and three skin depths carry 87% and 95% of the total current respectively. The coupling of noise between the signals and current surges in the power distribution can be significant and cause EMI and functional issues. It was described in “Switching Noise Between Vcc and L0 Planes” on page 30 that the strongest high-frequency currents in a PCB flow due to switching and/or cross-conduction surges between the Vcc and L0 planes (Figure 26 on page 31) and their peak values measure in amperes (of transient current) as opposed to the signal currents that usually have much lower levels. At high frequencies. To reduce the coupling of noise between the Vcc1 and the Vcc2 layers. This helps providing low impedance (high capacitance and low inductance) distribution for high-frequency components of the logic-switching power supply currents (including power surges). Skin depth for copper is 0. the high-frequency components of the currents in the Vcc1 and the Vcc2 do not flow through the same paths. typically above 100 MHz. the Vcc and the L0 layers should be closely spaced.26 mils at 100 MHz and decreases with the square root of the frequency. Trace Trace layer L0 Vcc IS IP L0 L0 IP Vcc Figure 35: High-Frequency Current in Power Distribution and Signal Current Do Not Flow Through Common Impedance in this Arrangement of PCB Layers Due to Skin Effect IS IS IP B roa dcom Co rpo rat ion Document EMC-TI101-R Board Stackup Page 41 .7 mils or 1. and between Inner 3 and Inner 4 layers. and between Vcc2 and L03 close paths on the Vcc side of the L02 and L03 layers. The high-frequency components of the power (surge) currents between Vcc1 and L02. or on the signal-side only of the L02 and L03 planes. This helps minimizing the noise coupling between these two Vcc layers. For the most part. The high-frequency components of the signal current paths in the 12-layer stackup of Figure 34 on page 39 are closed on either side of L01 or L04 planes. All other things being equal. REDUCING THE NUMBER OF PCB LAYER TRADE-OFFS Cost is the driving factor in reducing the number of layers. which is often achieved by reducing the number of planes in the PCB layers. which is a (cost-reduced) derivative of the 12-layer example. Therefore. where one L0 plane is removed and the other is replaced with a Vcc layer. Applying additional measures. thus the Vcc planes can be easily used for multiple voltages. The gaps in the Vcc layers cannot cause any discontinuity in the signal return paths. Because they are used to describe some performance issues that arise from compromising the performance criteria to decrease the cost. The size of the power planes in this stackup should only be large as necessary to encompass the pins that connect to it. they intend to be illustrations of potential issues rather than recommendations. Figure 36 on page 43 shows an example of a 10-layer stackup. Understanding the possible issues is a key to creating a PCB stackup that is still acceptable. Split Vcc Planes The routing layers are not adjacent to the Vcc planes in the 12-layer stackup example (Figure 34 on page 39). Limiting the size of the Vcc planes reduces the edge-effects described in “EM Field Propagation at the Edges of the Planes” on page 23. even though it may not have the best possible performance. Impedance between Vcc and L0.Technical Information 10/07/04 Another consideration is low-frequency noise coupling. sensitive analog and singleended signals should not be routed under the PCB sections containing strong sources of low frequency noise. Paying attention to the following can make a large difference in performance of such (less than ideal) PCB stackups: • • • • Current flow. such as between the switch-mode power supplies and signal traces. and between the signal and the power distribution. The skin effect does not provide isolation by the PCB planes at low frequencies. Coupling/crosstalk between the signals. B roa dcom Co rpo rat ion Page 42 Board Stackup Document EMC-TI101-R . such as: Providing additional intentional return paths Adding L0 fills Designing proper decoupling and bypassing Carefully examining the routing strategy IMPORTANT! The following PCB stackups are not necessarily the best stackups from the performance point of view. this inevitably results in decrease of performance. which significantly increases the high-frequency impedance of the Vcc2 power distribution relative to the Vcc1 power distribution. which can create a serious problem due to possible discontinuity of the current paths. or sensitive (such as reset) signals. it is not possible to add a plane stitching via because the planes are on different DC voltages. Adding capacitors at the locations of the transition may help.Increased noise in Vcc2 power distribution . which can cause noise coupling between them. that noise propagates and couples to all devices connected to Vcc2 and to any via and pin of the signals that change layers between the Vcc2 and L02. This causes these two Vcc planes to share a common impedance. When generated. and because it cannot be remedied by using vias to connect between the reference planes at different DC voltages. Another possible issue is that the Vcc1 and Vcc2 share the same L02 plane for the high-frequency current return path. Inner 1. Using capacitors to improve bypassing between the Vcc and L0 planes can help.Discontinuous current paths and increased crosstalk . or Bottom layers creates a current-path discontinuity. B roa dcom Co rpo rat ion Document EMC-TI101-R Board Stackup Page 43 . Inner 4. All of the high-frequency return current for Vcc1 flows on the Vcc1 side of the L02 plane. and all return current for Vcc2 flows on the same side of the L02 plane. the via-to-via crosstalk can increase because of the strong possibility of discontinuous current paths with the change of layers adjacent to the planes that are at different DC levels. That may cause excessive noise between Vcc2 and L0. The traces in layers Inner 3. but cannot be as effective as using signal-return (L0-stitching) vias. Crosstalk Compared with the 12-layer example.Technical Information 10/07/04 TOP ~ 5-6 mils L0 1 ~ 5-6 mils INNER 1 ~ 10-15 mils INNER 2 L0 2 Vcc 1 ~ 5-6 mils INNER 3 ~ 10-15 mils INNER 4 ~ 5-6 mils Vcc 2 ~ 5-6 mils BOTTOM ~ 5-6 mils Issues: . or Inner 2 layers and any of the Inner 3. Coupling Between Vcc and L0 Planes The Vcc2 does not have an adjacent L0 plane. high-speed. Inner 4. but the capacitors will have larger series impedance than the vias. In this case. and bottom should not run across the splits in the planes if any of the Vcc planes are split to accommodate multiple voltages because that would add another discontinuity to the current paths and further increase noise and crosstalk on the board.Noise coupling between the signals and Vcc2 power distribution Figure 36: 10-Layer Stackup Example for Discussion Return Paths Changing the routing between any of the Top. Such routing should be avoided for any critical. Multiple voltages are required in many PCB designs. Inner 4. which increases CM impedance and noise in the PCB power distribution. L0 IS/2 L0 IS/2 IP IS/2 IP IS/2 IS/2 IP Trace layer Vcc Trace IS/2 Vcc Figure 37: Mechanism of High-Frequency Noise Coupling Between Power Distribution System and Routing Layers when Routing is Between Vcc and L0 Planes Placing any signal layers between the L0 and Vcc layers has two noise-increasing consequences: • • It forces larger separation between L0 and Vcc. The signal routed in the Inner 3. This situation. but the relative coupling of that noise to the signal layers increases as well due to the coupling between the power distribution and the signal layers sandwiched between the Vcc and the L0 layers. At the same time. The signal currents and the power supply currents are closely coupled over both the impedance of the planes and mutual inductance and capacitance between the plane layers and the signal layers. and Bottom layers of the 10-layer example in Figure 36 on page 43 have their current paths closed through the Vcc planes. It is easy to maintain adjacent current return paths. This gives rise to the CM noise on all layers that share common impedance with the power distribution system. is often encountered when the number of the PCB layers is reduced for cost reasons. separated paths (see Figure 35 on page 41). Traces couple more power supply noise because the signal currents IS and the power currents IP (including power surges) flow through the common impedances. It is not only that the noise on the power distribution increases because of the larger separation between the Vcc and the L0 layers. as shown in the Figure 37. B roa dcom Co rpo rat ion Page 44 Board Stackup Document EMC-TI101-R .Technical Information 10/07/04 Coupling Between Signal and Power Supply Currents Two important features of the 12-layer stackup (described in “Discussion of the 12-Layer Example Stackup Features” on page 40) are: • • The high-frequency components of the signal currents and power supply currents flow in physically different. these Vcc planes carry large switching and cross-conduction current components that flow between the Vcc planes and the bottom surface of the L02 plane. which increases noise and crosstalk. connected to L01 and L02 with multiple vias at the edges of L0-fills INNER 4 Vcc 2 BOTTOM Figure 38: Improving Performance by Adding L0 Fills The dielectric thickness between the Vcc1 and the L02 planes is minimized (e.. 2 mils) to decrease the impedance of the Vcc1 power distribution by decreasing the inductance and increasing the capacitance between the Vcc1 and L02.Technical Information 10/07/04 The performance of the 10-layer stackup from Figure 36 on page 43 can be improved if modified as in the Figure 38.g. TOP L0 1 INNER 1 INNER 2 L0 2 Vcc 1 INNER 3 Minimized distance L0 fills. The most significant improvement is lowering the impedance of the Vcc2 power distribution system and reducing its common-impedance coupling with the signal layers Inner 3 and Inner 4. B roa dcom Co rpo rat ion Document EMC-TI101-R Board Stackup Page 45 . Common impedance coupling between the Vcc2 and the Vcc1 power distribution is also reduced by adding the L0 fills adjacent to the Vcc2 layer. Technical Information 10/07/04 Figure 39 shows an example of a six-layer stackup with two internal routing layers. the signal layers adjacent to the Vcc plane can be filled with L0 and connected with many vias to the L0 plane. This stackup is not good if the Vcc layer is used for multiple voltages because of the difficulty in maintaining continuity of the current return paths in the Inner 2 and bottom layers. Without taking these into consideration and carrying out these measures. the L0 fill can mostly be accomplished only in the bottom layer. because traces change routing between Inner 1 and Inner 2 layers. Therefore. special attention must be given to reducing the effects of discontinuous current paths with change of layers and to decoupling and bypassing in this stackup. B roa dcom Co rpo rat ion Page 46 Board Stackup Document EMC-TI101-R . For practical reasons. With the L0 fill on the bottom. the decoupling and bypass capacitors should be placed on the bottom to minimize the inductance (see Figure 30 on page 35). TOP ~ 5-6 mils L0 1 ~ 5-6 mils INNER 1 ~ 35-40 mils INNER 2 ~ 5-6 mils Vcc ~ 5-6 mils BOTTOM L0 fill Figure 39: Six-Layer Stackup with Two Internal Routing Layers To improve performance within the constrains of this relatively low-cost stackup. this stackup is not good for high-speed circuits. Keeping the current paths continuous is not easy. The Vcc current closes its path between the Vcc and the Vcc side surface of the L02 layer. TOP ~ 5-6 mils L0 1 ~ 5-6 mils INNER 1 ~ 35-40 mils Vcc ~ 5-6 mils L0 2 ~ 5-6 mils BOTTOM Figure 40: Six-Layer Stackup with Improved Performance B roa dcom Co rpo rat ion Document EMC-TI101-R Board Stackup Page 47 .Technical Information 10/07/04 Figure 40 shows a better performing six-layer stackup in which the performance is achieved at the expense of one internal routing layer. while the three routing layers have their current return in L01 and bottom side of the L02 layers. and at the same time decreases the noise coupling between the power switching and surge currents and the signals. This lowers the impedance in the power distribution. The significant improvement can be obtained due to the proximity of the L0 and the Vcc planes. Lam.43. T. produced by Elliott Laboratories.TI101 -R . Pavlu. Broadcom Corporation 16215 Alton Parkway P. Paul: Introduction to Electromagnetic Compatibility. AVX Corporation Technical Information LITERATURE • • Clayton R. IEEE Trans. H. Martin Graham: High Speed Digital Design. Broadcom Corporation does not assume any liability arising out of the application or use of this information. and L. Nov. L. John Wiley & Sons. Drewniak. King: EMCT—Electromagnetic Compatibility Tutorial. D ocume nt E M C. Inc. T. John Wiley & Sons. [2] Henry W. Stephen H. Hubing. Box 57013 Irvine.O. 39.M. Information furnished by Broadcom Corporation is believed to be accurate and reliable. IEEE Transaction on EMC. CA and IEEEStandards Information Network [4] D. CA 92619-7013 Phone: 949-450-8700 Fax: 949-450-8710 Broadcom® Corporation reserves the right to make changes without further notice to any products or data herein to improve reliability. Inc.Technical Information 10/07/04 REFERENCES AND LITERATURE REFERENCES [1] Howard W. Garrett W. Van Doren. function. However. Rubin: Quantifying EMI Resulting from Finite-Impedance Reference Planes. Vol. [3] W. James A. M. on EMC. vol. F. Sunnyvale.-W. Sha. Inc. J. 1997 [5] Marco Leone: Design Expressions for the Trace-to-Edge Common-Mode Inductance of a Printed Circuit Board. P. C. no. Ott: Noise Reduction Techniques in Electronic Systems. McCall: High-Speed Digital System Design. Hall. 4. Lockwood. Inc. John Wiley & Sons. Steve Makl: Capacitor Selection and EMI Filtering. Johnson. April 1999 [7] Jeffrey Cain. PTR Prentice-Hall. neither does it convey any license under its patent rights nor the rights of others. E. nor the application or use of any product or circuit described herein. November 2001 [6] J.576 "Printed Circuit Board Including a Terminated Power Plane and Method of Manufacturing the Same". Hall.898. or design. Hockanson. US Patent 5.