Ref: me3241_1112.doc ME3241/ ME3241E Mi cr opr ocessor and Appl i cat i ons Part 1: Digit al Elect ronics BY A/PROF HONG GEOK SOON Control & Mechatronics Group Mechanical Engineering Department NATIONAL UNIVERSITY OF SINGAPORE DECEMBER 2011 ME3241/ME3241E Microprocessor and Applications Page: ii © 2011, ME, NUS ME3241/ME3241E MICROPROCESSOR APPLICATIONS By: A/P GS Hong (Digital Electronics) Dr. Xu Huan (MicroP) Room: EA-05-24 E1-05-17 Phone: 6516 2272 65161604 E-mail:
[email protected] [email protected] ME3241 ME3241E Start Date: 09 Jan 2012 13 Jan 2012 Time: Monday 10:00-012:00 Friday 9:00-11:00 Friday 18:00–21:30 Venue: E1-06-04 (Monday) LT7A Examination Date: 24 April 2012 (pm) Reference books: 1. RL Tokheim, "Digital electronics: Principles and applications", 7th edition, 2008, McGrawHill. 2. RJ Tocci, "Digital systems: Principles and applications", 6th edition, 1995, Prentice-Hall, Inc. 3. S Brown and Z Vranesic, "Fundamentals of digital logic with Verilog design", 2nd edition, 2008, McGrawHill. 4. LD Jones, "Principles and applications of digital electronics", Macmillan, 1986. 5. TF Bogart, Jr., "Introduction to digital circuits", McGraw-Hill International Student Edition, 1992 6. H-W Huang, "PIC microcontroller: an introduction to software and hardware interfacing", Clifton Park, NY: Thomson/Delmar Learning, 2005. © 2011, ME, NUS Page: iii Contents Chapt er 1 Number System and Codes ..................................................................................... 5 1.1 Number Systems .............................................................................................................. 5 1.1.1 Number System Representation .............................................................................. 5 1.2 Conversion between number systems ............................................................................. 7 1.2.1 Binary to Decimal ..................................................................................................... 7 1.2.2 Decimal to Binary ..................................................................................................... 7 1.2.3 Octal to Decimal ....................................................................................................... 9 1.2.4 Decimal to Octal ....................................................................................................... 9 1.2.5 Octal to Binary ........................................................................................................ 10 1.2.6 Binary to Octal ........................................................................................................ 10 1.2.7 Hexadecimal to Decimal ......................................................................................... 11 1.2.8 Decimal to Hexadecimal ......................................................................................... 11 1.2.9 Hexadecimal to Binary ........................................................................................... 11 1.2.10 Binary to Hexadecimal ........................................................................................... 11 1.3 Codes and Coding ......................................................................................................... 12 1.3.1 Binary Coded Decimal Code .................................................................................. 12 1.3.2 Gray Code .............................................................................................................. 13 1.3.3 Alphanumeric Codes - ASCII Code ........................................................................ 16 1.3.4 Error Detection ....................................................................................................... 17 1.3.5 Error Correction ...................................................................................................... 19 1.4 Binary Arithmetic ............................................................................................................ 21 1.4.1 Binary Addition ....................................................................................................... 21 1.4.2 Binary Subtraction .................................................................................................. 21 1.4.3 Binary Multiplication ............................................................................................... 22 1.4.4 Binary Division ....................................................................................................... 22 1.4.5 Representing Signed Numbers .............................................................................. 22 1.5 Numeric Notation Used in Computers ............................................................................ 27 1.5.1 Integer Notation ...................................................................................................... 27 1.5.2 Floating Point Notation ........................................................................................... 27 Chapt er 2 DIGITAL ELECTRONICS ....................................................................................... 31 2.1 Introduction .................................................................................................................... 31 2.2 Boolean algebra ............................................................................................................. 31 2.2.1 Definition ................................................................................................................ 31 2.2.2 Boolean Identities ................................................................................................... 31 2.3 Integrated Circuit Logic .................................................................................................. 32 2.3.1 Digital IC Terminology ............................................................................................ 32 2.3.2 TTL Logic ............................................................................................................... 35 2.4 Logic Gates .................................................................................................................... 39 2.4.1 Some Properties of NAND Gate ............................................................................. 40 2.4.2 Some combinatorial logic examples ....................................................................... 40 2.5 Flip-flops and Latches .................................................................................................... 41 ME3241/ME3241E Microprocessor and Applications Page: iv © 2011, ME, NUS 2.5.1 NAND gate Latch: .................................................................................................. 42 2.5.2 Clocked Flip-Flops: ................................................................................................. 43 2.5.3 Making of Clocked S-C Flip-Flop ............................................................................ 43 2.5.4 Clocked J-K Flip-Flop ............................................................................................. 45 2.5.5 Clocked D Flip-Flop ................................................................................................ 46 2.5.6 D Latch (Transparent Latch) ................................................................................... 47 2.5.7 Timing Consideration for Flip-flop ........................................................................... 47 2.6 Counters and Registers.................................................................................................. 48 2.6.1 Registers ................................................................................................................ 48 2.6.2 Counters ................................................................................................................. 50 2.7 Encoders, Decoders ....................................................................................................... 60 2.7.1 Decoders ................................................................................................................ 60 2.7.2 Encoders ................................................................................................................ 64 2.8 Multiplexers & demultiplexers ......................................................................................... 65 2.8.1 Multiplexers ............................................................................................................ 65 2.8.2 Multiplexer Applications .......................................................................................... 66 2.8.3 Demultiplexers........................................................................................................ 67 2.8.4 Demultiplexer Applications ..................................................................................... 68 Chapt er 3 Microprocessor Architecture ................................................................................... 69 3.1 Making of a microprocessor ........................................................................................... 69 3.1.1 Registers, ROM’s, Ram’s and Buses ..................................................................... 69 3.1.2 Digital Arithmetic Circuits ........................................................................................ 72 3.1.3 A Very Simple microprocessor ............................................................................... 73 © 2011, ME, NUS Page: 5 Chapt er 1 Number System and Codes 1.1 Number Systems A number system is a quantifying system ones adopted for counting. The quantity involved can be the number of people attending this class, the number of elective modules a student has to take, etc.. The study of number systems is not just limited to computers. We apply numbers every day, and knowing how numbers work will give us an insight into how a computer manipulates and stores numbers. Amount many number system, the commonest is the system known as weighted position representation. Human start their ways of counting in many different ways and finally evolved to the current approach of number system representation. For a good appreciation of the historical number system representation, please refer to http://www-groups.dcs.st-andrews.ac.uk/~history/Indexes/Number_Theory.html 1.1.1 Number System Representation Consider the number 6557, we read six thousand five hundred and fifty seven, that is 6 x 1000 + 5 x 100 + 5 x 10 + 7 x 1 The above example demonstrated a common number system we adopted. It is known as weighted position representation. Definition: A number, r N , in a number system with the base r is represented in the form of ¿ ÷ = ÷ ÷ ÷ = = n m i i i m n n r r A A A A A A N 1 0 1 . ( 1.1.1) where i = number of places the digit is relative to the radix point r = radix or the base of the system { } 1 , , 1 , 0 ÷ e r A i This number representation is also known as weighted position number system. The following subsections show a few common examples of such representation. 1.1.1.1 Decimal System (Base 10) The decimal system is the number system we (human being) are familiar with. In this case, the base r = 10, and { } 9 , 8 , 7 , 6 , 5 , 4 , 3 , 2 , 1 , 0 e i A Examples: 825 10 = 8 x 10 2 + 2 x 10 1 + 5 x 10 0 368.49 10 = 3 x 10 2 + 6 x 10 1 + 8 x 10 0 + 4 x 10 -1 + 9 x 10 -2 Decimal system is the current “Universal Standard” used by human being. For convenience, we normally just omit the subscript 10 in our notation. 1.1.1.2 Binary System (Base 2) The binary system is the number system that computer is using. In this case r = 2, and { } 1 , 0 e i A . ME3241/ME3241E Microprocessor and Applications Page: 6 © 2011, ME, NUS In binary system there are only two states (zero and one), these binary states make it easy for Boolean implementation in the computer. Example: The number 1101 2 has the representation Weightage ÷ 3 2 2 2 1 2 0 2 + + + + Number ÷ 1 1 0 1 It has an equivalent decimal value of 1101 2 = 1 x 2 3 + 1 x 2 2 + 0 x 2 1 + 1 x 2 0 = 13 10 Also 110.01 2 = 1 x 2 2 + 1 x 2 1 + 0 x 2 0 + 0 x 2 -1 + 1 x 2 -2 = 4 + 2 + 0 + 0 + 0.25 = 6.25 10 1.1.1.3 Octal System (Base 8) Octal system is a number system that is commonly used by the low level programmer for better visual recognition of the codes. In this case, r = 8 { } 7 , 6 , 5 , 4 , 3 , 2 , 1 , 0 e i A Example: The number 405.3 8 has the representation of Weightage ÷ 2 8 1 8 0 8 1 8 ÷ + + + + Number ÷ 4 0 5. 3 It has an equivalent decimal value of 405.3 8 = 4 x 8 2 + 0 x 8 1 + 5 x 8 0 + 3 x 8 -1 = 4 x 64 + 0 + 5 x 1 + 3 x 0.125 = 261.375 10 Also 102.21 8 = 1 x 8 2 + 0 x 8 1 + 2 x 8 0 + 2 x 8 -1 + 1 x 8 -2 = 64 + 0 + 2 + 2 x 0.125 + 0.015625 = 66. 265625 10 1.1.1.4 Hexadecimal System (Base 16) Like the octal system, hexadecimal system is a number system that is commonly used by the low level programmer for better visual recognition of the codes. In this case, r = 16 { } F E D C B A A i , , , , , , 9 , 8 , 7 , 6 , 5 , 4 , 3 , 2 , 1 , 0 e Noting that, in hexadecimal system, we are running out of symbol to represent the values 10~15. We use the alphabets A~F to represents these values. Example: The number 3B.4 16 has the representation of Weightage ÷ 16 1 16 0 16 -1 + + + Number ÷ 3 B. 4 Number System and Codes © 2011, ME, NUS Page: 7 3B.4 16 = 3 x 16 1 + 11 x 16 0 + 4 x 16 -1 = 3 x 16 + 11 x 1 + 4 x 0.0625 = 59.25 10 Also, 102.2 16 = 1 x 16 2 + 0 x 16 1 + 2 x 16 0 + 2 x 16 -1 = 1 x 256 + 0 x 16 + 2 x 1 + 2 x 0.0625 = 258.125 10 1.2 Conversion between number systems We now see that a numerical value can be represented in many different bases of representation. When you are given with a number in one base, say, r a . What is the equivalent representation in another base, say, r b ? A quick solution to this will be the use of the weighted position representation definition in (1.1.1). Given a number a r N represented by m n n r A A A A A N a ÷ ÷ ÷ = 1 0 1 . . ( 1.2.1 ) Then, this number can be represented in another base of radix value b r N by ¿ ÷ = = a a b n m i i a i r r A N ( 1.2.2) with the arithmetic be computed in base r b . Such formulation implies the requirement of a base that the “computer” is familiar with. For instance, the human being is familiar with the decimal system (i.e. r = 10). We can use this to convert a number of any bases into a decimal system. 1.2.1 Binary to Decimal We use the weighted sum approach as in (1.2.2) with r b = 10. ¿ ÷ = = 2 2 2 10 n m i i i b N ( 1.2.3 ) Example: The number 1010.01 2 can be converted to a decimal as 1010.01 2 = 1 x 2 3 + 0 x 2 2 + 1 x 2 1 + 0 x 2 0 + 0 x 2 -1 + 1 x 2 -2 = 8 + 0 + 2 + 0 + 0 + 0.25 = 10.25 10 1.2.2 Decimal to Binary The above examples showed the conversion from binary system to decimal system. How about the reverse process? To do this, we can also use the same weighted sum approach as in (1.2.3). For instance, the decimal number 34 10 can be converted to its binary equivalence by 10 34 0 1 10 4 10 3 × + × = 0 2 2 1 2 2 1010 100 1010 11 × + × = 2 2 2 100010 110 11110 = + = However the above method involves binary arithmetic. Such approach is not practical as we are not familiar with arithmetic with any bases other than 10. There are two other methods to convert a decimal number to binary number. ME3241/ME3241E Microprocessor and Applications Page: 8 © 2011, ME, NUS 1.2.2.1 Method 1 Express the decimal number as a sum of powers of 2 and then 1’s and 0’s are written in the appropriate bit position. Example: 45.5 10 = 32 + 8 + 4 + 1 + 0.5 = 2 5 + 0 + 2 3 + 2 2 + 0 + 2 0 + 2 -1 = 101101.1 2 76 10 = 64 + 8 + 4 = 2 6 + 0 + 0 + 2 3 + 2 2 + 0 + 0 = 1001100 2 Note: This method require you to be familiar with the various $2^i$ values. 1.2.2.2 Method 2 Consider a 3-digit based-r integer, 0 0 1 1 2 2 r A r A r A N r + + = . Dividing N r by its radix value yields ( ) r A r A r A r r A r A r A r N r 0 0 1 1 2 0 0 1 1 2 2 + + = + + = Or, alternatively, we say 0 0 1 1 2 remainder A r A r A r N r + = Similarly, 1 0 2 0 1 1 2 remainder A r A r r A r A = + Hence, we can use successive division technique to convert a decimal number to a base-r representation. For the case of fractional number, consider a base-r fractional number with 3 radix places 3 3 2 2 1 1 ÷ ÷ ÷ ÷ ÷ ÷ + + = r A r A r A N r . Multiplying N r by its radix r yields ( ) 2 3 1 2 0 1 3 3 2 2 1 1 ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ + + = × + + = × r A r A r A r r A r A r A r N r Noting that, the first radix place of the fractional number becomes the integer part in the result. That is, we can use successive multiplication technique to convert a fractional decimal number into a base-r representation. Example: Convert the decimal number 26.6875 10 to its binary representation. 26.6875 10 = 26 10 + 0.6875 10 For the integer part, we have 26 ÷ 2 = 13 R 0÷ Least significant bit 13 ÷ 2 = 6 R 1 6 ÷ 2 = 3 R 0 3 ÷ 2 = 1 R 1 1 ÷ 2 = 0 R 1÷ Most significant bit Number System and Codes © 2011, ME, NUS Page: 9 For fractional part, we have 0.6875 x 2 = 1.375 0.375 x 2 = 0.750 0.75 x 2 = 1.500 0.5 x 2 = 1.000 Hence, the binary representation is 26.6875 10 = 11010.1011 2 Example: Convert the decimal number 43.6 10 to its binary representation. 43.6 10 = 43 + 0.6 By repeated division by 2 for the integer part and multiplication by 2 for the fractional part. For the integer part, we have 43 ÷ 2 = 21 R 1÷ Least significant bit 21 ÷ 2 = 10 R 1 10 ÷ 2 = 5 R 0 5 ÷ 2 = 2 R 1 2 ÷ 2 = 1 R 0 1 ÷ 2 = 0 R 1÷ Most significant bit For the fractional part, we have 0.6 x 2 = 1.2 0.2 x 2 = 0.4 0.4 x 2 = 0.8 0.8 x 2 = 1.6 0.6 x 2 = 1.2 : : : : : : Noting that the fractional conversion never ends, this implies that 0.6 10 does not has an exact binary representation. Hence, the binary representation with 5 digits approximation is 43.6 10 = 101011.10011 2 (up to 5 digits approx.) 1.2.3 Octal to Decimal Similarly, we use the weighted sum approach to convert Octal number to decimal number. ¿ ÷ = = n m i i i A N 8 10 ( 1.2.4 ) Example: The octal number 326.4 8 can be converted to a decimal number by 326.4 8 = 3 x 8 2 + 2 x 8 1 + 6 x 8 0 + 4 x 8 -1 = 192 + 16 + 6 + 0.5 = 214.5 10 1.2.4 Decimal to Octal For decimal to octal conversion, we use repeated division by 8 for the integer part and repeated multiplication by 8 for the fractional part. MSB LSB MSB Repeated ME3241/ME3241E Microprocessor and Applications Page: 10 © 2011, ME, NUS Example: Consider the decimal number 379.546875 10 , it consists of 379.546875 10 = 379 10 + 0.546875 10 For the integer part, we have 379 ÷ 8 = 47 R 3 ÷Least significant digit 47 ÷ 8 = 5 R 7 5 ÷ 8 = 0 R 5 ÷Most significant digit For the fractional part, we have 0.546875 x 8 = 4.375 0.375 x 8 = 3.000 Hence, the octal representation is 379.546875 10 = 573.43 8 1.2.5 Octal to Binary In general, for conversion from a non-decimal system to decimal system, we use the weighted position method to do the conversion. On the other hand, the conversion from decimal to non- decimal system use the method of successive division and multiplication by the radix value for integer and fractional parts, respectively. How about the conversion between two non-decimal systems? Say, from base-r to base-p, we can first convert the base-r number to its decimal representation by weighted position method and followed by the successive and division by p to base-p number. However, for a special case of p and r that has the relationship of i r p = ( 1.2.5 ) For instance, the octal number has a radix of 8 and binary has a radix of 2 which has the relationship of 8 = 2 3 . Table 1.2.1 shows that, each octal digit is matched to unique 3-bits binary pattern. Hence, we can simplify the conversion process by matching technique. Table 1.2.1Octal digit to binary pattern Octal digit 0 1 2 3 4 5 6 7 Binary pattern 000 001 010 011 100 101 110 111 Example: The octal number 271.65 8 can be converted to its binary presentation by simple pattern matching as show below. 271.658 = 010 111 001.110 1012 1.2.6 Binary to Octal As each octal digit has a unique 3 binary bits code, we can convert the binary number to its octal representation by first grouping the binary number in groups of 3 bits starting from the radix point. Then, for each of the 3 bits pattern, match it with its corresponding octal value. Example: The binary number 1111100101.001110 2 can be converted to its octal representation by 1111100101.001110 2 = 001 111 100 101 . 001 110 2 = 1 7 4 5 . 1 6 8 = 1745.16 8 Most significant digit Least significant digit Number System and Codes © 2011, ME, NUS Page: 11 1.2.7 Hexadecimal to Decimal Similarly, we use the weighted sum approach to convert hexadecimal number to decimal number. ¿ ÷ = = n m i i i A N 16 10 ( 1.2.6 ) Example: The hexadecimal number 3B.4C 16 can be converted to its decimal representation by 3B.4C 16 = 3 x 16 1 + 11 x 16 0 + 4 x 16 -1 + 12 x 16 -2 = 48 + 11 + 0.25 + 0.046875 = 59.296875 10 1.2.8 Decimal to Hexadecimal For decimal to hexadecimal conversion, we use repeated division by 16 for the integer part and repeated multiplication by 16 for the fractional part. Example: Consider the decimal number 379.546875 10 , it consists of 379.546875 10 = 379 10 + 0.546875 10 For the integer part, we have 379 ÷ 16 = 23 remainder 11 = B ÷Least significant digit 23 ÷ 16 = 1 remainder 7 1 ÷ 16 = 0 remainder 1 ÷Most significant digit For the fractional part, we have 0.546875 x 16 = 8.75 0.75 x 16 = 12.00 = C.00 379.546875 10 = 17B.8C 16 1.2.9 Hexadecimal to Binary Similarly, the hexadecimal number has a radix of 16 and binary has a radix of 2. Noting that 16 = 2 4, this implies one hexadecimal digit will map to four binary bits. Table 1.2.2 shows that, each octal digit is matched to unique 3-bits binary pattern. For such case, we can simplify the conversion process by matching technique. Table 1.2.2 Hexadecimal digit to binary pattern Hex digit 0 1 2 3 4 5 6 7 Bin pattern 0000 0001 0010 0011 0100 0101 0110 0111 Hex digit 8 9 A B C D E F Bin pattern 1000 1001 1010 1011 1100 1101 1110 1111 Example: The hexadecimal number A94.65 16 can be converted to its binary representation as follows: A94.6516 = 1010 1001 0100.0110 01012 1.2.10 Binary to Hexadecimal Similarly, each hexadecimal digit has a unique 4 binary bits code; we can convert the binary number to its octal representation by first grouping the binary number in groups of 4 bits starting from the radix point. Then, for each of the 4 bits pattern, match it with its corresponding hexadecimal value. ME3241/ME3241E Microprocessor and Applications Page: 12 © 2011, ME, NUS Example: 1111100101.00111 2 = 0011 1110 0101 . 0011 1000 2 = 3 E 5 . 3 8 16 = 3E5.38 16 1.3 Codes and Coding 1.3.1 Binary Coded Decimal Code While computers work in binary, humans work in decimal. This implies that, when computers interface with people, conversions are needed to/from decimal/binary. In addition, to make thing easier for programmer and to make equipment with read-outs compatible with computer interfaces, numbers, letters or words are represented by group of symbols called code. There are many different internationally accepted standard codes. Among them, binary coded decimal (BCD) is one of the popular codes used in industries. BCD is a code used to represent a decimal digit by its binary equivalent. There are many variances of BCD code, the most common BCD is the 8421-BCD. 1.3.1.1 8-4-2-1 BCD Code In 8421-BCD, each decimal digit is represented by a 4-bit binary number which also has the binary numerical value of the decimal digit as shown in Table 1.3.1. Table 1.3.1 8421-Binary Coded Decimal Decimal Digit BCD 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 Noting that 8421-BCD only used 10 out of the 16 possible combination of 4-bits binary number. Some vendor use these remaining combination for some special characters likes '.', '-', 'E', '+' and other symbols which might be associated with communicating a value. Example: 39 10 0011 1001 107 10 0001 0000 0111 Note that conversion from BCD code to decimal is straight forward. e.g. 0110 1000 0011 1001 (BCD Code) = 6839 10 6 8 3 9 Number System and Codes © 2011, ME, NUS Page: 13 1.3.1.2 Comparison of BCD Code and Binary Number BCD is not another number system like binary, octal or hexadecimal. It is not the same as straight binary number. A straight binary code takes the complete decimal number and represents it in binary. Whereas, the BCD Code converts each individual decimal digit to a set 4 bits binary code. Example: Decimal Number Binary Number BCD Code 137 10 10001001 2 0001 0011 0111 Noting that BCD requires more binary bits than straight binary number. To represent decimal number 137 in BCD we need 12 bits of code (4+4+4). Whereas, for straight binary number representation, an 8-bits binary number has the range of 0~255. 1.3.1.3 Other variance of BCD Code There are many other variance of BCD used for some specific reasons. A few popular variances of it is listed in Table 1.3.2 below. Table 1.3.2 Variance of BCD Codes Decimal Digit BCD 8-4-2-1 Excess-3 Biquinary 5 0 4 3 2 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 0 0 0 1 0 2 0 0 1 0 0 1 0 1 0 1 0 0 1 0 0 3 0 0 1 1 0 1 1 0 0 1 0 1 0 0 0 4 0 1 0 0 0 1 1 1 0 1 1 0 0 0 0 5 0 1 0 1 1 0 0 0 1 0 0 0 0 0 1 6 0 1 1 0 1 0 0 1 1 0 0 0 0 1 0 7 0 1 1 1 1 0 1 0 1 0 0 0 1 0 0 8 1 0 0 0 1 0 1 1 1 0 0 1 0 0 0 9 1 0 0 1 1 1 0 0 1 0 1 0 0 0 0 - 8-4-2-1: Most straightforward BCD representation, with the weight of each digit corresponding to the same value as in the binary system - Excess 3: Each value exceeds the normal binary value by three – simplifies the carry logic in parallel addition - Biquinary: Used in communication the numbers from 0 to 9 are divided into two groups and one position of the code is used to determine in which group a given number is, and a five position code is used to determine the number in the group. 1.3.2 Gray Code Gray code, named after Frank Gray who introduce this code in 1947, is an encoding such that two successive code differ in only one bit. It was originally designed to prevent spurious output from electromechanical switches. It is often used in situations where other codes, such as binary, might produce erroneous or ambiguous results during those transitions in which more than one bit of the code is changing. A popular application of Gray code is in instrumentation and data acquisition systems where absolute linear or angular displacement is measured. For instance, absolute optical shaft encoders used in angular measurement. Table 1.3.3 Example of a 4 bit Gray Code Decimal Binary Gray Code Decimal Binary Gray Code 0 0000 0000 8 1000 1100 1 0001 0001 9 1001 1101 2 0010 0011 10 1010 1111 3 0011 0010 11 1011 1110 4 0100 0110 12 1100 1010 5 0101 0111 13 1101 1011 6 0110 0101 14 1110 1001 7 0111 0100 15 1111 1000 ME3241/ME3241E Microprocessor and Applications Page: 14 © 2011, ME, NUS Gray code is often referred as binary reflected code or cyclic code. Table 1.3.3 shows an example of 4-bits Gray code with its corresponding 4-bit binary representation. A specific property of Gray code is that the difference between two successive pair of number will only have only one bit change only. For instance, a change from 7 10 to 8 10 has all 4 bits changed in the case of binary number. Whereas, the same situation will only has one bit change in the case of Gray code. 1.3.2.1 Advantage of Gray Code This one-bit change feature of the Gray code has been utilized in many applications. For example, it is used in absolute encoder. Figure 1.3.1 Comparison between Gray code and binary code. It shows how the sensor values are read in both binary coded and Gray coded encoders. In position 1, both sensors read the value of 7 (binary=0111 and Gray=0100). Similar, in position 3, both sensors read the value of 8 (binary=1000 and Gray=1100). However, in position 2, the sensor for the binary coded encoder reads the value of 15 (binary=1111). Whereas, the Gray coded encoder reads the value of 8 (Gray=1100). Hence, it can be seen that the binary coded encoder can get an erroneous reading while the Gray coded encoder is more clean and less erroneous. Figure 1.3.1 Comparison between Gray code and binary code. 1.3.2.2 Generation of Gray Code The binary-reflected Gray code for n bits can be generated recursively by reflecting the bits (i.e. lists them in reverse order and concatenates the reverse list onto the original list), prefixing the original bits with a binary 0 and then prefixing the reflected bits with a binary 1. The base case, for n = 1 bit, is the most basic Gray code, G = {0, 1}. The base case can also be thought of as a single zero-bit Gray code (n = 0, G = {" "}), which is made into the one-bit code by the recursive process. Method 1: Gray code construction To generate the Gray Code, we utilize the reflected code properties as follows: Step 1: To generate an n-digit (say, n=4) Gray Code, we start by a 1 digit Gray Code Decimal Gray Code 0 0 1 1 Step 2: For 2 digits Gray Code, we first repeat the 1 digit Gray Code in the reverse order. Then insert 0’s to the left of these codes on the upper half and 1’s on the lower half. Decimal Gray Code 0 0 0 1 0 1 Number System and Codes © 2011, ME, NUS Page: 15 2 1 1 3 1 0 Step 3: For 3 digits Gray Code, repeat Step 2 with 2-digit Gray Code and so on. Decimal Gray Code 0 0 0 0 1 0 0 1 2 0 1 1 3 0 1 0 4 1 1 0 5 1 1 1 6 1 0 1 7 1 0 0 Step 4: For 4 digits Gray Code, repeat Step 2 with 3-digit Gray Code and so on. Decimal Gray Code 0 0 0 0 0 1 0 0 0 1 2 0 0 1 1 3 0 0 1 0 4 0 1 1 0 5 0 1 1 1 6 0 1 0 1 7 0 1 0 0 8 1 1 0 0 9 1 1 0 1 10 1 1 1 1 11 1 1 1 0 12 1 0 1 0 13 1 0 1 1 14 1 0 0 1 15 1 0 0 0 Method 2: Binary to Gray Code Conversion The reflected code properties suggested a simple and fast method of translating a binary value into the corresponding Gray code. Each bit is inverted if the next higher bit of the input value is set to one. This can be interpreted as follows: To convert a Binary number 0 2 1 b b b B n n ÷ ÷ = , to its corresponding Gray code 0 2 1 g g g G n n ÷ ÷ = , we use the formula ¹ ´ ¦ = = ÷ = + + , 0 , 1 , 1 1 1 i i i i i b b b b g for i = 0, 1, …, n-1 with b n = 0 ( 1.3.1 ) Method 3: Gray Code to Binary Conversion To convert from Gray Code 0 2 1 g g g G n n ÷ ÷ = to its corresponding binary number 0 2 1 b b b B n n ÷ ÷ = , we first define ME3241/ME3241E Microprocessor and Applications Page: 16 © 2011, ME, NUS | | . | \ | = ¿ + = 2 , mod 1 n i j j i g S with 0 = n g . ( 1.3.2 ) Then, the binary number B can be calculated from ¹ ´ ¦ = = ÷ = 0 , 1 , 1 i i i i i S g S g b , for i = 0, 1, …, n-1 ( 1.3.3 ) 1.3.3 Alphanumeric Codes - ASCII Code Table 1.3.4 ASCII Table HEX MSD 0 1 2 3 4 5 6 7 LSD Bits 000 001 010 011 100 101 110 111 0 0000 NUL DLE SP 0 @ P ` p 1 0001 SOH DC1 ! 1 A Q a q 2 0010 STX DC2 " 2 B R b r 3 0011 ETX DC3 # 3 C S c s 4 0100 EOT DC4 $ 4 D T d t 5 0101 ENQ NAK % 5 E U e u 6 0110 ACK SYN & 6 F V f v 7 0111 BEL ETB ' 7 G W g w 8 1000 BS CAN ( 8 H X h x 9 1001 HT EM ) 9 I Y i y A 1010 LF SUB * : J Z j z B 1011 VT ESC + ; K | k { C 1100 FF FG , < L \ l | D 1101 CR GS - = M } m } E 1110 SO RS . > N ^ n - F 1111 SI US / ? O _ o DEL Special ASCII Symbols NUL Null VT Vertical Tabulation CAN Cancel SOH Start of heading FF Form feed EM End of medium STX Start of text CR Carriage return SUB Substitute ETX End of text SO Shift out ESC Escape EOT End of transmission SI Shift in FG File separator ENQ Enquiry DLE Data link escape GS Group separator ACK Acknowledge DC Device control RS Record separator BEL Bell NAK negative ac knowledge US Unit separator BS Back space SYN synchronous idle SP Space HT Horizontal tab ETB end of transmission block DEL Delete LF Line feed In addition to numerical data, a computer need to handle non-numerical information. That is, in addition to decimal digits, we also need codes to represent characters of the alphabet, punctuation marks, and other special characters. These codes are called alphanumeric codes. These codes are used primarily for data transfer from computer to input/output devices such as printers, keyboards, modem etc. To standardize on the representation of symbols, international codes are used. The most widely used alphanumeric code is the American Standard Code for Information Interchange (ASCII), it is the normally referred as “askee” code (ASCII). It is a seven-bit code which provides 128 (2 7 =128) representation as shown in Table 1.3.4 ASCII Table. The code covers 26 lowercase alphabet, 26 uppercase alphabet, 10 decimal digits, punctuation marks and a set of special characters which is normally known as control characters. These control characters, as the name calls, are used to control the machine via communication channel. Number System and Codes © 2011, ME, NUS Page: 17 Example 1: The following is a message in ASCII. 100 1000 100 0101 100 1100 101 0000 + + + + H E L P It represents the message HELP. Example 2: An operator is typing in a Basic program at the keyboard of a computer. Determine the ASCII Code that will be entered into memory when the operator types “GOTO 25”. Answer: G ÷ 100 0111 O ÷ 100 1111 T ÷ 101 0100 O ÷ 100 1111 ÷ 010 0000 2 ÷ 011 0010 5 ÷ 011 0101 1.3.4 Error Detection The transfer of binary data and codes from one location to another is the most common operation in digital systems. For examples: - Transmission of digitized voice over a microwave link. - Storage and retrieval data from external memory devices such as magnetic disks and tapes - Transmission of information from a computer to a remote user terminal and another computer. Figure 1.3.2 Noise on transmitted data Whenever information is transmitted from one device (transmitter) to another device (receiver), there is a possibility that errors can occur such that the receiver does not receive the identical information that was sent by transmitter, due to noise disturbance. For instance, a “0” may be read as “1” or vice versa. It would be nice if we can implement some kind of coding such that any transmission error can be detected or corrected. One example is the Biquinary Code in earlier section which has the format of F 5 F 0 U 4 U 3 U 2 U 1 U 0 For a given number, there is only one “1” is each of the groups. That is, one “1” from F 5 F 0 and another one “1” from U 4 U 3 U 2 U 1 U 0 . For instance, the number 7 will have the code “10 00100”. So, any single-bit error will make the code invalid. For example, say, there is an error on U 1 , resulted Exercise: 1. Encode in ASCII, the string “Cost = $72” 2. The following ASCII message is stored in the memory. What is the message? 101 0011 101 0100 100 1111 101 0000 ME3241/ME3241E Microprocessor and Applications Page: 18 © 2011, ME, NUS in the code received as “10 00110”. As there is two “1”’s in U 4 U 3 U 2 U 1 U 0 . This indicated that the Biquinary Code is invalid, hence error is detected. Parity Bit: A common practice used is the introduction of parity bit. A parity bit is an extra parity bit appended to the code group that is being transferred from one location to another. This additional bit can be either “0” or “1”, depends on the number of 1's that are contained in the code group. There are two methods used, that is, - Even Parity: add another 1 or 0 to ensure total number of 1's is even. - Odd parity: add another 1 or 0 to ensure total number of 1's is odd. Example: Suppose that the character 'C' is to be transmitted, the code group is 100 0011. There are three 1's in the ASCII code of 'C'. Case 1:Even Parity The value of the parity bit is chosen such that the total number of 1’s in the code group (including the parity bit) is even. To make it even, “1” is added to the code as follows 1 100 0011 ASCII Code Parity bit is 1 in even parity mode Case 2: Odd Parity The value of the parity bit is chosen such that the total number of 1’s in the code group (including the parity bit) is odd. To make it odd, 0 is added to the code as follows 0 100 0011 ASCII Code Parity bit is 0 in odd parity mode Say, if the receiver actually receives the code 0100 0001, the receiver will know that an error has occurred in the transmission because the received code has even number of 1’s. Note: The parity bit can only detect single-bit error only. 1.3.4.1 Effect of Parity Check Parity checking may be employed at major interfaces in a digital system. Since redundancy is added to each message, parity checks are used only when the probability of errors occurring and the risk associated with an error is high enough to warrant it. Consider a case that we are transmitting a 7-bit ASCII code between two devices. Case I: (Without parity bit) For a given transmission technique, the probability of a bit be transmitted wrongly is p (say, p = 3.1 x 10 -5 ). Transmission rate is r (say, r = 400 bps) Number System and Codes © 2011, ME, NUS Page: 19 By transmitting without parity bit, the probability of transmitting an 7-bits ASCII code is P 7 , P 7 = 1 – (1 - p) 7 = 1- 0.999969 5 = 2.17 x 10 -4 and the transmission rate of R 7 , R 7 = r/7 = 400/7 = 57.14 word per second Alternatively, the average error rate is E 7 is E 7 = 1/ P 7 x 1/ R 7 = 80 sec. Case II: (With parity bit) With the parity bit implemented, the single bit error will always be detected. Therefore we only look at chances that 2 bits or more errors happen together. Hence, by transmitting with parity bit, the probability of transmitting an 8-bits ASCII code is P 8 , P 8 = 1 - (1-p) 8 – 8p(1-p) 7 = 2.69 x 10 -8 and the transmission rate of R 8 , R 8 = r/8 = 50 word per second Alternatively, the average error rate is E 8 is E 8 = 1/ P 8 x 1/ R 8 = 743273 sec. = 8.6 days! Clearly, with an additional bit used as in Case II, the reliability has increased tremendously. 1.3.5 Error Correction Sometime, besides detecting the error, we want to be able to correct the error such that we can save the time for re-sending the message. Or, there may be situation that the message cannot be re-sent. For example, reading a corrupted CD-ROM, no matter how many time you re-read the code, it is still invalid. It will be preferred that an auto-correction can be implemented in this case. A popular error correction technique is the so-called Hamming Code. 1.3.5.1 Hamming Code Hamming code involves the design of a code that combine m message bits ( 0 1 2 1 M M M M m m ÷ ÷ ) with r extra parity bits ( 0 1 2 1 P P P P r r ÷ ÷ ) such that single-bit error in the code can be corrected. r is chosen as the smallest number that satisfy the condition r r m 2 1s + + ( 1.3.4) The r + m bits of code are arranged in the order by the following rules: 1. Add r parity bits to an m-bit message to form an r+m bits Hamming code. 2. Number the bit position from 1 to (r+m). 3. Place parity bit i P in (2 i ) th position, for i = 0,1, ... , r-1. 4. Fill the remaining m positions by the message bits. 5. Performs parity operation for each parity bit with the position correspond to the 2 i positions. The following example illustrate how a BCD code can be Hamming coded. Example: Consider the implementation of the Hamming Code on a 4 bit 8421-BCD code. For 4 bit BCD code m = 4, therefore ME3241/ME3241E Microprocessor and Applications Page: 20 © 2011, ME, NUS r r 2 1 4 s + + . Clearly, a choice of r = 3 will satisfy the above condition. Hence, we need 3 parity bits in position 2 0 =1, 2 1 =2 and 2 2 =4. And the code is arranged as follows: Position 1 2 3 4 5 6 7 Code P0 P1 M3 P2 M2 M1 M0 For parity assignment, we view the parity bits P 2 P 1 P 0 as a 3-bit number, and P i will performs parity operation with the position number with P i =1. In this case, Position Bit P2 P1 P0 1 (001) P0 \ 2 (010) P1 \ 3 (011) M3 \ \ 4 (100) P2 \ 5 (101) M2 \ \ 6 (101) M1 \ \ 7 (111) M0 \ \ \ Hence, the parity bits will check on P 0 checks on {M 3 , M 2 , M 0 } P 1 checks on {M 3 , M 1 , M 0 } P 2 checks on {M 2 , M 1 , M 0 } Say, for even parity and the code is 0110 (BCD “6”) P 0 = even { M 3 , M 2 , M 0 } = even { 0, 1, 0} = 1 P 1 = even { M 3 , M 1 , M 0 } = even { 0, 1, 0} = 1 P 2 = even { M 2 , M 1 , M 0 } = even { 1, 1, 0} = 0 Hence the code is 11 0 0 110 Error Correction Say, during transmission, the code 110 0110 becomes 110 1110. We check for the even parity of each parity bits C 0 = even { M 3 , M 2 , M 0 } = even { 0, 1, 0} = 1 = P 0 ¬ E 0 =0 C 1 = even { M 3 , M 1 , M 0 } = even { 0, 1, 0} = 1 = P 1 ¬ E 1 =0 C 2 = even { M 2 , M 1 , M 0 } = even { 1, 1, 0} = 0 ≠ P 2 ¬ E 2 =1 Hence, the error position E 2 E 1 E 0 = 100 = 4 ¬ Position 4 has error, it should be a 0 instead of 1. ¬ the corrected code should be 110 0110 Graphical interpretation of Hamming Code Effectively, Hamming codes uses the technique of elimination to identify the error bit. Hence the detected error bit can be identified. Figure 1.3.3 shows graphically how each message bit is associated with each parity bit. By simple interception, the error bit can be isolated. Hamming code has strategically arranged the message bits and parity bits in such a way that the error code ( 0 1 2 E E E ) reflect the error bit’s position. Number System and Codes © 2011, ME, NUS Page: 21 Figure 1.3.3 Graphical interpretation of Hamming Code - Homework: Any error in this code? if any, correct them, 10 1 0 011 1.4 Binary Arithmetic 1.4.1 Binary Addition Binary addition works in the similar way as we do our decimal addition. We first has an addition table which give the results of addition of two decimal digits combination. In fact, it is easier to performs binary addition, as binary number has only two elements {0,1}. We first have the binary addition table as shown below 0 + 0 = 0 0 + 1 = 1 1 + 1 = 0 plus carry of 1 1 + 1 + 1 = 1 plus carry of 1 Examples: Consider the addition of two numbers 3 10 and 6 10 , we have 0 1 1 2 = 3 10 + 1 1 0 2 = 6 10 1 0 0 1 2 = 9 10 Similarly, for the numbers 3.375 10 and 2.75 10 , we have 11.011 2 = 3.375 10 + 10.110 2 = 2.75 10 110.001 2 = 6.125 10 - Exercise: Find the sum of 101.01 + 110 + 10.1. 1.4.2 Binary Subtraction Similarly, We first have the binary subtraction table as shown below 0 - 0 = 0 1 - 1 = 0 1 - 0 = 1 0 - 1 = 1 with a borrow of 1 Example: Consider the subtraction of the number 5 10 from 11 10 , we have 1011 2 = 11 10 - 0101 2 = -5 10 0110 2 = 6 10 Similarly, for the subtraction of 6 10 from 9.5 10 , we have 1001.1 2 = 9.5 10 - 0110.0 2 = -6.0 10 ME3241/ME3241E Microprocessor and Applications Page: 22 © 2011, ME, NUS 0011.1 2 = 3.5 10 - Exercise: Find the sum of 101.01 - 10.1. 1.4.3 Binary Multiplication The multiplication of binary numbers is carried out in the similar manner as the multiplication of decimal numbers. It is in fact easier for binary multiplication as the multiplier digits are either 0 or 1 and nothing else. Example: Consider the multiplication of two numbers 45 10 and 5 10 , we have 101101 2 ÷multiplicand 45 10 x 101 2 ÷multiplier x 5 10 101101 2 ÷Partial Products 225 10 000000 2 101101 2 11100001 2 ÷Product 1.4.4 Binary Division The binary division is the same as the decimal numbers except it is simpler in the case of binary number. The following examples illustrate how binary division is carried out. Example: Consider the division of 9 by 3, we have 0011 2 =3 10 11 2 1001 2 011 0011 0011 0000 Similarly, the division of 10 by 4 yields 0010.1 2 =2.5 10 100 2 1010 2 100 0010 0000 0010.0 0010.0 0000.0 1.4.5 Representing Signed Numbers In our daily life, we encounter negative values in many different forms. For instance, over draft in your bank account, when you go to the basement of a building, in an extreme cold (below freezing point) condition, etc.. These are just different forms of negative value representation. In general, negative value can be represented in four forms as follows and is used by the computer in the binary context. - Signed magnitude representation - By pre-pending a sign indicator in the number N N sm ± = ( 1.4.1) - Excess (Offset) representation - By adding a bias to the number B N N xs + = ( 1.4.2) Number System and Codes © 2011, ME, NUS Page: 23 - Radix complement representation - By taking radix complement of an n-digit number is defined as N r N n rc ÷ = ( 1.4.3) - Diminished radix complement representation - By taking diminished radix complement of an n-digit number is defined as N r N n drc ÷ ÷ = 1 ( 1.4.4) Note: radix complement = diminished radix complement + 1. 1.4.5.1 Negative number representation for decimal number system Signed-Magnitude Representation This is by far, the most common way of signed representation that human has used. It is represented by a sign symbol in front of the numeric number. The sign symbol {-.+} tells the sign of the value and the number tells the magnitude of the value. N N sm ± = Example: + 456.4 , -564.4 , 56.3 , etc Excess (Offset) Representation Excess representation is also called biased representation, it uses a pre-specified number B as a biasing value. A value is represented by the unsigned number which is B greater than the intended value. Thus 0 is represented by B, and −B is represented by 0. B N N xs + = Example: A bias of 0.5 for the number in the range of 0 to 1. 0.6 ÷ +0.1, 0.2 ÷ -0.3, etc Radix Complement Representation It is called the ten's complement in the decimal system. Say, for a 2 digit decimal number, its radix complement is N N rc ÷ = 2 10 10 ( 1.4.5) Example: The 10’s complement of a 2-digit decimal number 75 is 10 2 – 75 = 25. Diminished Radix Complement Representation The diminished radix complement in the decimal system is called the nines' complement. Say, for a 2 digit decimal number, its diminished radix complement is N N drc ÷ ÷ = 1 10 2 10 ( 1.4.6) Example: The 9’s complement of a 2-digit number 75 is 10 2 – 1 - 75 = 24. 1.4.5.2 Negative number representation for binary number. Signed-Magnitude Representation ME3241/ME3241E Microprocessor and Applications Page: 24 © 2011, ME, NUS Similarly, it is represented by a sign symbol in front of the numeric number. The sign symbol {-.+} tells the sign of the value and the number tells the magnitude of the value. N N sm ± = ( 1.4.7) For signed-magnitude representation of binary number, one way is to use the MSB of the number as a sign bit. In general, the common convention is that a “0” in the sign bit represents a positive number and a “1” in the sign bit represents a negative number. The Figure below illustrates how the +104 10 and –104 10 are represented by an 8-bit signed magnitude representation. Bit-7 is used as the sign bit to indicate the sign of the number. The magnitude of the number is represented 7-bit binary number (b 6 -b 0 ). b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 1 1 0 1 0 0 0 = + 104 10 Positive number | Magnitude = 104 Sign bit (+) b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 1 1 1 0 1 0 0 0 = - 104 10 Negative number | Magnitude = 104 Sign bit (+) However, such notation requires very complicated logic and not commonly used in computer. Noting that this notation will has a case for “negative zero” when we have the value of 1000 0000! Excess (Offset) Representation In the binary context, the bias value B is usually chosen to be around the middle of the range. Say, for an n-bit binary number, we choose B = 2 n-1 – 1. Hence, Excess representation will have the number 1 2 1 ÷ + = ÷ n xs N N ( 1.4.8) The excess representation will have a range of -(2 n-1 - 1) ~ (2 n-1 ). We call it an excess (2 n-1 – 1) representation. Example: For 8-bit binary number, we have B = 2 7 – 1 = 127 and the number will have the representation of 127 + = N N xs . We call this Excess-127 representation. It will have the range of -127~128. - Diminished Radix Complement Representation In the binary context, it is called 1’s complement form. For an n-bit number, the diminished radix complement is defined as 2 1 2 1 2 N N n ÷ ÷ = . ( 1.4.9) Number System and Codes © 2011, ME, NUS Page: 25 The 1’s complement is also known as the logical complement. This is because, the value 2 n – 1 will all the bits of the binary number equal to ones. The operation of 2 n -1 – N 2 will results in inverting every bits of the binary number N 2 . Example: The 1’s complement of a 4-bit binary number, say, 1001 2 will be ( ) 2 2 2 2 4 1 2 0110 1001 1111 1001 1 2 = ÷ = ÷ ÷ = N Hence, the digital implementation of 1’s complement will be a simple NOT operation on every bits of the number as shown in Figure 1.4.1. Figure 1.4.1 Digital One’s Complement Implementation Radix Complement Representation for binary number In the binary context, it is also called 2’s complement form. For an n-bit number, the radix complement is defined as 2 2 2 2 N N n ÷ = ( 1.4.10) This is sometime known as the arithmetic complement. Noting from (1.4.9) and (1.4.10) that 1 1 1 2 2 1 2 2 2 2 2 + = + ÷ ÷ = ÷ = N N N N n n ( 1.4.11) Hence, the 2’s complement can be computed by first computing its 1’s complement and followed by adding a 1 to the result as shown in the example below. Example: For a 4-bit number N 2 = 0110 2 0110 ÷ 1001 ÷ 1001 + 1 1010 number 1’s complement 2’s complement The 2’s complement has the problem of double representation. For an n-bit binary number N A in the range of 0~2 n -1, there exist another number A n B N N ÷ = 2 also in the range of 0~2 n -1 (Except for the cases of N A =0 or N A =2 n-1 ). Noting that, by definition, N B is the 2’complement of N A and vice versa. This implies that the number N A represents both the value of N A and the 2’complement of N B . Table 1.4.1 illustrates the case of a 3-bits representation. To avoid the duplicated representation, the shaded cells are not used in the representation. That is, the 3 bit-binary with 2’s complement signed representation has the range of -4~3. Table 1.4.1 2’Complement of 3-bit binary number Decimal Binary 2’s Complement 0 000 000 (-0) 1 001 111 (-1) ME3241/ME3241E Microprocessor and Applications Page: 26 © 2011, ME, NUS 2 010 110 (-2) 3 011 101 (-3) 4 100 100 (-4) 5 101 011 (-5) 6 110 010 (-6) 7 111 001 (-7) Table 1.4.2 Shows the various sign representation for a 4-bit binary number. Sign magnitude an 1’s complement notation have the negative zero presentation which is meaningless in practice. Also, without the explicit setting of sign bit like the sign magnitude notation, all representation has the most significant bit reflecting the sign of the number. All representations has “0” indicating a positive number and “1” indicating a negative number except the Except the Excess-7 with the indication reversed. Table 1.4.2 Comparison between various signed representation Decimal Unsigned Sign Magnitude Excess-7 1’s Complement 2’s Complement +15 1111 +14 1110 +13 1101 +12 1100 +11 1011 +10 1010 +9 1001 +8 1000 +7 0111 0111 1110 0111 0111 +6 0110 0110 1101 0110 0110 +5 0101 0101 1100 0101 0101 +4 0100 0100 1011 0100 0100 +3 0011 0011 1010 0011 0011 +2 0010 0010 1001 0010 0010 +1 0001 0001 1000 0001 0001 +0 0000 0000 0 0000 0111 0000 -0 1000 1111 -1 1001 0110 1110 1111 -2 1010 0101 1101 1110 -3 1011 0100 1100 1101 -4 1100 0011 1011 1100 -5 1101 0010 1010 1011 -6 1110 0001 1001 1010 -7 1111 0000 1000 1001 -8 1000 1.4.5.3 Binary Arithmetic with 2’s Complement. Consider the subtraction of an n-bit binary number N B from another n-bit binary number N A , we have ( ) n B A n B n A B A N N N N N N 2 2 2 2 ÷ + = ÷ ÷ + = ÷ where B n B N N ÷ = 2 2 denotes the 2’s complement of N B . The above expression can be re- arranged as n B A B A N N N N 2 2 + ÷ = + . ( 1.4.12) Noting that 2 n is outside the n-bit binary range of 0~2 n -1. Hence, the performance of 2 B A N N + will result in subtracting N B from N A with the value 2 n store in the carry-over bit which will not be reflected in the sum register. Example: Subtracting 4 10 from 12 10 in an 8-bit operation will has the following: Number System and Codes © 2011, ME, NUS Page: 27 12 10 = 0000 1100 2 4 10 = 0000 0100 2 2’s complement of 4 10 = 1111 1100 2 We have 12 10 ÷ 0000 1100 2 - 4 10 ÷ + 1111 1100 2 1 0000 1000 2 | This carry is disregarded. 1.5 Numeric Notation Used in Computers It is known that the computer uses binary arithmetic. That is, numbers are stored in its binary form. Depending on the kind of problem we are solving, we may require values of different range. In computer systems, numbers can be stored in the following notations - Integer Notation - Floating point notation 1.5.1 Integer Notation In computer, integer variable refers to integer representation usually in forms of multiple byte(s) of integer size. It has two forms of representation, i.e., unsigned integer or signed integer. Unsigned Integer This is the weighted position representation for binary number. For an n-bit binary representation will have the range of 0~2 n -1. The size of the integer is usually chosen with n equals to multiple of 4. For examples, 4 (nibble), 8 (byte), 16 (word), etc.. The figure below shows an 8-bit unsigned integer representation with a range from 0 to 255. b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 1 0 1 0 1 0 1 =85 10 8-bit unsigned integer Singed Integer In computer, signed integer uses the 2’s complement representation. Say, for 8-bit signed integer as shown below, it has the range from -128 to 127. As illustrate in earlier section, the most significant bit (b 7 ) will have the properties of a sign bit due to 2’s complement notation used. The figure below shows an 8-bit signed integer representation with a range from -128 to 127. b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 1 0 1 0 1 0 1 1 =-85 10 Sign bit number 1.5.2 Floating Point Notation 1 A floating-point number N f in radix r has the general form E f r F N × ± = ( 1.5.1) 1 Dorf, R. C. (1993). The Electrical Engineering Handbook. CRC Press. ME3241/ME3241E Microprocessor and Applications Page: 28 © 2011, ME, NUS where 1 0 < s F is the fraction (or mantissa) and E is the exponent. For example, electron mass m e = 9.109 x 10 -31 Kg can be represented as follows. m e = .9109 x 10 -30 Kg = .09109 x 10 -29 Kg = .009109 x 10 -28 Kg All these adhere to the form as described by (1.5.1) are correct floating point representation. In order to be more consistent, a further constrain has been imposed on F such that the most significant digit must be a non-zero digit except in the case of F=0. That is, the standard representation is m e = .9109 x 10 -30 Kg and is called the normalised floating point representation. In the computer, binary system is used, an n-bit normalised floating point representation is defined as ( ) 2 2 1 2 E s f F N × ÷ = where { } 1 , 0 e s is the sign bit. 1 1 . 0 2 2 < s F is the mantissa which has the value of m m m m n n n n i i i F b F ÷ ÷ ÷ = × + = × | | . | \ | + = ¿ 2 1 . 0 2 2 1 . 0 , 2 2 2 0 2 2 where n m is the number of significant binary places and m n F , 2 is the n m - 1 bit mantissa value stored in the computer. Noting that, for an m binary places fractional number, only the n m -1 least significant digits are stored. This is because the condition of 1 1 . 0 2 2 < s F implies that the most significant digit is always a one and is there not stored. E 2 is the exponent of the floating point representation which needed to be a signed number. That is E 2 >>0 for large value representation and E 2 <<0 for small value representation. For the convenience of floating point addition and subtraction implementation, E 2 is stored in the computer as an n e -bit signed number in excess representation with the bias value of 1 2 1 ÷ = ÷ e e n n B . That is, the n e -bit signed number, e e n n B E E + = 2 , 2 will have the range of 1~ ( ) 2 2 ÷ e n which corresponds to the exponent E 2 with the range of ( ) 2 2 1 ÷ ÷ ÷ e n ~( ) 1 2 1 ÷ ÷ e n . In computer the floating number are stored by packing { } m e n n F E s , 2 , 2 , , into a m e n n n + = bits memory. Table 1.5.1 shows how nm and ne are distributed for various precisions by IEEE standard for floating point representation. Table 1.5.1 IEEE implementations of floating point number Precision N n m n e E 2 (Min) E 2 (Max) Single 32 23+1 8 -126 127 Double 64 52+1 11 -1022 1023 Quadruple 128 112+1 15 -16382 16383 Number System and Codes © 2011, ME, NUS Page: 29 31 30 thru 23 22 through 0 Sign Bit Exponent Mantissa Assumed position of radix point, with 0.1 2 hidden Figure 1.5.1 32-bit normalised floating point representation Figure 1.5.1 shows the IEEE standard defined for a normalised 32-bit floating representation. The most significant bit, b 31 , is used as the sign bit, s. The mantissa is represented by a 24-bit fractional binary representation with m n F , 2 stored in b 0 to b 22 . The exponent uses an 8-bit Excess-127 representation. It is stored in b 23 -b 30 . It has a range of -126~127. In this representation, s defines the sign of the number, F 2 defines the significant of the number and E 2 tells the order of the number. It can represent a range of 38 127 127 10 70141 . 1 2 2 111 111 . 0 × ± = ± = × ± . The smallest normalised representation it can represents is when E 2 = -126 and F 2 = 0.1 2 . This will gives a value of 39 126 10 5.87747 2 5 . 0 ÷ ÷ × = × . This normalised representation has a problem that the exact zero can not be represented since the most significant binary place of F 2 is always a one. To address this problem, we note that the n e -bit excess form exponent, e n E , 2 , only uses the range of 1~( ) 2 2 ÷ e n . The values 0 and ( ) 1 2 ÷ e n (0 and 255 in this case) have been reserved for special use. The case of 0 , 2 , 2 = = m e n n F E has been used to represent the exact zero. Whereas the case of 255 1 2 , 2 = ÷ = e e n n E and 0 , 2 = m n F is used to represent the infinity (·). In the case of 0 , 2 = m n F , 0 , 2 = e n E indicates a subnormal representation (or floating point underflow situation) and 255 1 2 , 2 = ÷ = e e n n E indicates an invalid floating point representation or NaN (Not a Number). These various cases are summarised in the Table below. e n E , 2 ( 2 E ) m n F , 2 =0 m n F , 2 = 0 0 (-127) ±0 Subnormal numbers 1~254 (-126~127) Normal floating point number 255 (128) ±· Nan Example1: The number 45.78125 10 is stored in the 32-bit normalised floating point number as follows: 45.78125 10 = 101101.11001 2 Shifting the binary places yields 101101.11001 2 = 0.10110111001 2 x 2 6 From the above, we have s = 0 2 E = 6 ¬ e n E , 2 = 6 10 +127 10 = 10000101 2 2 F = 0.10110111001 2 ¬ m n F , 2 = 011 0111 0010 0000 0000 0000 The floating point representation is the packing of { } m e n n F E s , 2 , 2 , , as follows: Floating point number = 0 10000101 01101110010000000000000 ME3241/ME3241E Microprocessor and Applications Page: 30 © 2011, ME, NUS Example2: Determine the decimal value of the normalised 32-bit floating point representation 1 01111101 11000000000000000000000. From the above, the sign bit s = 1. The exponent in excess-127 notation is e n E , 2 = 01111101 2 = 125 10 ¬ 2 E = 125 10 - 127 10 = -2 10 The mantissa with the implied 0.5 removed is m n F , 2 = 11000000000000000000000 2 = 6291456 10 ¬ 2 F = 0.5 + 2 -24 x 6291456 10 = 0.875 10 Hence the floating point representation has the decimal value of ( ) 2 2 1 2 E s f F N × ÷ = = (-1) 1 x 0.875 10 x 2 -2 = -0.21875 ___________________________ ©2011, ME, NUS Page: 31 Chapt er 2 DIGITAL ELECTRONICS 2.1 Introduction Engineers generally classify electronic circuits as being either analogue or digital in nature. A brief guideline to differentiate between analogue and digital is look at the transistor used in circuit. If the transistor is operating in the linear region, it is lightly that the circuit is an analogue circuit. Whereas, if the transistor operator in saturated region, it is lightly that it is a digital circuit. In practical context, the signs of a device contains digital circuitry can be deduce by observing the any existence of alphanumeric display, memory and programmability. 2.2 Boolean algebra In digital systems, the information being processed is usually presented in binary form. Binary quantities can be represented by any device that has only two operating states. In Boolean context, the two states are TRUE and FALSE. Many real life examples can be expressed in these binary states. For example, a creature is either alive or dead, a door is either open or closed, etc. In digital logic circuits, it often uses predefined voltages to represent these binary states. For example, in TTL logic, 5 v represents a true case and 0 v represent a false case. The concept of logical decision has been formalized by the mathematician, George Boole (1854), which expressed logical decision in the form of symbols operated by various logical operators. Such expression is commonly referred as Boolean expression or Boolean algebra. The main purpose of this logical expression is to describe the relationship between a logical circuit’s output (decision) and its input (circumstances). These are summarized as follows: 2.2.1 Definition A Boolean Algebra is an algebra ( { } 1 , 0 = B ; -,+, “ - ”,0,1) consisting of a set B together with three operations, the AND (Boolean product) operation -, the OR operation (Boolean sum) operation +, and the NOT (complement) operation “ - ” defined on the set, such that for any B e y x, , B e - y x (AND operation), B e + y x (OR operation) and B e x (complement operation). For the Boolean algebra, the following Axioms hold: 1. Commutative: x.y = y.x x + y = y + x 2. Associative: x.(y.z) = (x.y).z (x + y) + z = x + (y + z) 3. Distributive: x.(y + z) = x.y + x.z x + (y.z) = (x + y).(x + z) 4. Identity: Identify for - (1) x-1 = x Identify for + (0) x + 0 = x 5. Complement: 0 = - x x 1 = + x x 2.2.2 Boolean Identities With the axioms above, further Boolean identities can be derived as follows. The proofs of these theorems are left to the reader as an exercise. Involution Laws ( ) x x = , B e ¬x Idempotent Laws x x x = + , x x x = - , B e ¬x Bound laws 1 1= + x , 0 0 = - x , B e ¬x Absorption laws x y x x = - + , ( ) x y x x = + - , B e ¬x 0 and 1 laws 1 0 = , 0 1 = DeMogan’s laws ( ) y x y x - = + , y x y x + = - , B e ¬x Chapter 2 DIGITAL ELECTRONICS Page: 32 ©2011, ME, NUS 2.3 Integrated Circuit Logic 2.3.1 Digital IC Terminology The IC technology has advanced rapidly with more and more gates packed within a single chip so that the overall size of all digital system is reduced. These advancements have made digital circuit very easy to implement with user only focus on the functional aspect of the IC modules. However, there are some basic important properties of digital circuits that is important for the user. Some terms are defined and discussed below: 2.3.1.1 Current and Voltage Parameters + VOH - + VIH - IOH IIH + VOL - + VIL - IOL IIL +5V V IH (min) – High-Level Input Voltage - The minimum input voltage level required for a logical 1 to be read. Any voltage below this level will not be guaranteed as a HIGH by the logic circuit. V IL (max) – Low-Level Input Voltage - The maximum input voltage level required for a logical 0 to be read. Any voltage above this level will not be accepted as a LOW by the logic circuit. V OH (min) – High-Level Output Voltage - The minimum output voltage that is generated at a logic circuit output in the HIGH or logical 1 state. Typical output voltage will be higher than V OH . V OL (max) – Low-Level Output Voltage - The maximum voltage that is generated at a logic circuit output in the LOW or logical 0 state. Typical value will be lower than V OL . I IH – High-Level Input Current - The current that flows into an input when a specified high-level voltage is applied to that input. I IL – Low-Level Input Current - The current that flows into an input when a specified low-level voltage is applied to that input. For TTL, it is usually negative indicating that the current flows out of the input (current sourcing). I OH – High-Level Output Current - The current that flows from an output in the logical 1 state under specified load condition. I OL – Low-Level Output Current - The current that flows from an output in the logical 0 state under specified load condition. 2.3.1.2 Fan-out The fan out or sometime referred as loading factor is defined as the maximum number of standard logic inputs that an output can drive reliably. If a logic gate has a fan out of 10, then it can drive 10 standard inputs. If this number is exceed, the output voltage level can not be guaranteed. 2.3.1.3 Transition Times and Propagation Delays While some digital circuits respond to logic levels (level triggered) at their input, others respond to a rapid change in voltage(edge triggered). In the latter type, it is essential that input signals have sufficiently fast level transitions, otherwise, the circuit may not respond properly. For this reason, the RISE TIME (T R ) and the FALL TIME (T F ) of a circuit output is often specified. These values are not always equal, and are both dependent on the output loading. ME3241/ME3241E Microprocessor and Applications ©2011, ME, NUS Page: 33 A logical signal always experiences a delay in traveling through a circuit. The two propagation delay times are defined as: - t PLH : delay time in going from a logical 0 to a logical 1. (i.e. LOW to HIGH) - t PHL : delay time in going from a logical 1 to a logical 0. (i.e. HIGH to LOW) 1 0 1 0 50% 50% Input Output tPHL tPLH Propagation times are used as a measure of the speed of response of logic circuits. Typical values are of the order of 10 to 20 nanoseconds (ns). In general, t PLH and t PLH are not the same value and both will vary depending on capacitive loading conditions. 2.3.1.4 Power Requirements ICCL +VCC ICCL 1 1 1 1 1 1 1 1 1 0 0 0 ICCH +VCC ICCH 0 1 1 0 1 1 0 1 1 1 1 1 Every IC chip needs electrical power to operate. The amount of power supplied to and consumed by an IC is very important because many circuits are made up of very large numbers of IC’s and thus the power requirements could become astronomical. Therefore, it is highly desirable to have IC’s that have extremely low power requirements. The power requirements of an IC are given in the manufacturer’s specifications. Sometimes it is given as average power dissipation (P D ). But, more commonly, it is indirectly specified in terms of the current drain (I CC ) from the power supply. The power dissipation can then be determined by multiplying I CC by the power supply voltage (V CC ). P D = I CC V CC For some IC’s the supply current is different for the two logic states. When this is the case, two values for I CC are specified. I CCH is the supply current when all of the outputs are HIGH; I CCL is the supply current when all of the outputs are LOW. Thus, an average current drain can be expressed as I CC (avg) = 2 CCL CCH I I + or P D = I CC (avg) V CC 2.3.1.5 Noise Immunity In logic systems, noise is any unwanted signal appearing at the input gate. The NOISE MARGIN specifies the allowable magnitude of input noise. If this input is exceeded, the data may be switched spontaneously creating an incorrect output resulting in system failure. Chapter 2 DIGITAL ELECTRONICS Page: 34 ©2011, ME, NUS Input noise can originate from many sources such as arc or spot welding equipment, fluorescent lights, etc. Avoid running cables in “noisy” environments, keep all leads as short as possible, and use shielded cable. Ensure good connections and use well regulated poser supplies. The HIGH STATE NOISE MARGIN is defined as: V NH = V OH (min) - V IH (min) The LOW STATE NOISE MARGIN is defined as: V NL = V OL (max) - V IL (max) Some Typical noise margins are illustrated in the figure below. LOGIC “1” Indeterminate range LOGIC “0” LOGIC “1” Indeterminate range LOGIC “0” V OH (Min) V IH (Min) V NH V IL (Max) V OL (Max) V NL 2.4 0.4 2.0 0.8 Output Voltage Range Input Voltage Range Example: (some typical TTL characteristics) Parameter Min (V) Typical (V) Max (V) V OH 2.4 3.4 V OL 0.2 0.4 V IH 2.0 V IL 0.8 V NH = V OH (min) - V IH (min) = 2.4 – 2.0 = 0.4 V V NL = V OL (max) - V IL (max) = 0.8 – 0.4 = 0.4 V 2.3.1.6 Current Sourcing and Current Sinking Logic Logic families can be categorized according to how current flows from the output of on logic circuit to another. The figures below illustrate the difference between the two types. Low IIH Low VOH High IIL High VOL +VCC Current Sinking receives current from load gate in LOW state Current Sourcing Supplies current to load gate in HIGH state ME3241/ME3241E Microprocessor and Applications ©2011, ME, NUS Page: 35 2.3.2 TTL Logic 2.3.2.1 Operation of TTL Logic Devices (Totem-pole Output Circuits) Since the transistor-transistor logic (TTL) family is widely used, we will examine the operation of a typical TTL NAND gate. Because NAND gate can be used to generate many types of logic functions, an understanding of the operation of this simple gate provides a good insight into the operation of most TTL devices. The figure below shows the circuit diagram for a basic two input TTL NAND gate. The input to the device is a multiple-emitter transistor (Q 1 ). Because of the way in which it is used in the circuit it can be simplified, for analysis purposes, by using its diode equivalent. This equivalent is shown in the shaded box to the right of the figure below. Diodes D 2 and D 3 represent the two E-B junctions of Q 1 , and D 4 is the collector-base (C-B) junctions. Noting that the output of the circuit consist of two transistors Q 3 and Q 4 stacked on top of one another and resemble a “Totem pole”, thus the terminology of a totem pole arrangement for this kind of configuration is used. The job of Q 3 is to connect V cc to the output, making a logic HIGH. Whereas, the job of Q 4 is to connect the output to ground, making a logic LOW. The importance of this output arrangement will be discussed shortly. Case I: Output Low-State When the inputs A and B are both HIGH, the two diodes D 2 and D 3 which represent the two base- emitter diodes will not conduct. Therefore the current from the +5v supply through resistor R 1 will flow through diode D 4 into the base of transistor Q 2 . This base current into Q 2 will turn Q 2 ON. The emitter current from Q 2 will produce a base current into Q 4 which turns Q 4 ON while at the same time the voltage at the collector of Q 2 is kept low enough to ensure that no base current flows into the base of Q 3 . Thus, ensures that Q 3 remains turned OFF. Diode D 1 is the insurance that the output will be very LOW since the emitter of Q 4 is shorted to the ground. Therefore, if both input A and B are HIGH, the output of the gate is LOW. Chapter 2 DIGITAL ELECTRONICS Page: 36 ©2011, ME, NUS Case II: Output HIGH case Consider the case when A is HIGH and B is LOW as shown below. Current will flow from V cc through R 1 and diode D 3 to ground. This will clamp the voltage at point X as shown below too low to generate a base current into Q 2 to turn it ON. Hence, Q 2 is OFF. This will results in no sufficient base current into Q 4 and implies Q 4 will also be turned OFF. Since Q 2 is OFF, the voltage at the collector of Q 2 is now sufficiently high to generate base current into Q 3 to turn Q 3 ON. Since Q 3 is ON, it produces a produces a high voltage via the pull up resistor R 4 and results in turning the Diode D 1 ON. As a result, the output will has the HIGH output voltage. (approx. 3.6v). Further analysis will shows that the above circuit behave like a NAND gate. There are a few points regarding Totem pole output circuit. The circuit would in fact operate if Q 3 and D 1 are eliminated from the circuit and the bottom of the resistor is connected directly to the collector of Q 4 . However, under this circumstance, Q 4 would conduct a fairly high current in its saturation state. Using the totem-pole configuration with Q 3 present, there will be no current through R 4 in the LOW output state. This will reduce the power dissipation of the circuit. Another advantage of totem-pole arrangement occurs in the HIGH output state. Since Q 3 is acting as an emitter-follower, its associated low output impedance (typically 10O) results in a short rise time constant for charging up any capacitive load on the output. This action is called active pull-up and provides very fast rise times at TTL outputs. One disadvantage of totem-pole arrangement occurs during a LOW to HIGH transition. Q 4 turns OFF more slowly than Q 3 turns ON. As a result, there is a period of a few nanoseconds when both transistors are conducting and resulting in a relatively large current surge (30-40mA). It is for this reason that in many IC circuits you will see numerous small capacitors connected from V cc to ground. This is termed power supply decoupling which prevents a voltage spike from occurring on the V cc line. Another important note to take is never tie the outputs of conventional TTL totem-pole output circuitry together. Such connection may cause excessive current draw through the transistor Q 4 (ON) of the gate in the LOW output state while other output are in the HIGH state. 2.3.2.2 TTL loading and Fan-out R4 Q3 Q4 D1 OFF ON IOL IIL IIL R4 Q3 Q4 D1 OFF ON IOH IIH IIH ME3241/ME3241E Microprocessor and Applications ©2011, ME, NUS Page: 37 If a high state output of a driving chip can source X amount of current and the input of the driven chip can sink Y amount of current, then the high state fan-out or the number of inputs the output can drive is simply the integer value of X/Y. i.e. Fan-out (High) = I OH (max) I IH (max) Similarly, the low state fan-out is defined as, Fan-out(Low) = I OL (max) I IL (max) Example: How many 7400 NAND gate inputs can be driven by a 7400 NAND output? Solution: From the data sheet, we can see that I OL (max) = 16 mA, I IL (max) = 1.6 mA I OH (max) = 400 µA, I IH (max) = 40 µA Therefore, Fan-out(Low) = I OL (max) I IL (max) = 16 mA 1.6 mA = 10 Fan-out(High) = I OH (max) I IH (max) = 400 µA 40 µA = 10 i.e. the fan-out is 10 Unit Load: Since all IC’s do not have the same current characteristics or specifications, and the actual fan-out depends on the combination of driving and driven IC’s. It would be impossible to specify an absolute fan-out value. As a result, standardized input and output loading factors have been established which allow the input and output currents been expressed in terms of standard unit loads. Some manufacturers specify the device input and output currents in terms of a unit load (UL), where a unit load is defined as follows: 1 unit load (UL) = ¹ ´ ¦ 40 µA in the HIGH state 1.6 mA in the LOW state These unit load factors are used to express the output drive capability and input loading requirement for TTL circuits. The following examples show how these concepts are used. Example1: Say, if a given IC is specified as having a fan-out of 10 UL in both states, this implies that: I OL (max) = 10 x 1.6 mA = 16 mA I OH (max) = 10 x 40 µA = 400 µA Example2: For the 7400 NAND gate in previous slide we have, I OL (max) = 16 mA, I IL (max) = 1.6 mA, I OH (max) = 400 µA, I IH (max) = 40 µA The output drive capability is drive capability(Low) = I OL (max) 1.6 mA = 16 mA 1.6 mA = 10 UL drive capability (High) = I OH (max) 40 µA = 400 µA 40 µA = 10 UL Chapter 2 DIGITAL ELECTRONICS Page: 38 ©2011, ME, NUS Therefore, in both HIGH and LOW states, the output can drive 10 UL. The input requirement for this IC can be expressed as Loading(Low) = I IL (max) 1.6 mA = 1.6 mA 1.6 mA = 1 UL Loading (High) = I IH (max) 40 µA = 40 µA 40 µA = 1 UL Therefore, in both HIGH and LOW states, the input has a loading factor of 1 UL. That is, if the output of 7400 is connected to identical 7400 IC, the fan-out in both LOW and HIGH states is (10 UL/ 1 UL) = 10. Example3: Consider now the 74S00 IC. The specs are as follows: I OL (max) = 20 mA, I IL (max) = 2 mA, I OH (max) = 1000 µA, I IH (max) = 50 µA The output drive capability is drive capability(Low) = I OL (max) 1.6 mA = 20 mA 1.6 mA = 12.5 UL drive capability (High) = I OH (max) 40 µA = 1000 µA 40 µA = 25 UL Therefore, 74S00 can drive 25 UL in HIGH state and 12.5 UL in LOW state. The input requirement for this IC can be expressed as Loading(Low) = I IL (max) 1.6 mA = 2 mA 1.6 mA = 1.25 UL Loading (High) = I IH (max) 40 µA = 50 µA 40 µA = 1.25 UL Therefore, 74S00 has a loading factor of 1.25 in both HIGH and LOW states. That is, if the output of 74S00 is connected to identical 74S00 IC, the fan-out in the HIGH state will be 25/1.25 = 20 and the fan-out in the LOW state will be 12.5/1.25 = 10. Example4: Consider now the output of 7400 driving the input of 74S00. From the unit load calculated in previous examples, the fan-out of 7400 to drive 74S00 in both HIGH and LOW states will be 10/1.25 = 8. Home work: How about 74S00 driving 7400? 2.3.2.3 Unused and unconnected inputs Sometimes it occurs that not all of the inputs on logic gate are required to perform the required logic function. Any unconnected input will be treated as a HIGH. When an input is left unconnected, it is said to be floating. It is not advisable to let the input floating. Although it behave like a HIGH, but this unconnected input also serve as an antenna which can pick up stray signals causing the gate to operate improperly. Some common method to unconnected inputs is by ME3241/ME3241E Microprocessor and Applications ©2011, ME, NUS Page: 39 Use a pull-up resistor Connect to ground Connect the input together X = A + B A B or 2.3.2.4 Tri-state logic devices Tri-state digital integrated circuit devices are extremely important particularly with respect to their use in computer circuits. As the name implies, these device have three output states. In addition to having the normal HIGH or LOW output state, it has an additional HIGH IMPEDANCE output state. When the output of the device is in this high impedance state, for all intensive purposes, it can be considered that its output is disconnected from the circuit. A tri-sate device has one additional input which is called a control input. If the control input is LOW, the gate operates in exactly the same manner as a conventional TTL gate and the output will have the usual HIGH or LOW depending on the gates input(s) present. The control input is HIGH, the output gate is disabled and no longer depends on the inputs but acts as a high impedance since both transistor Q 3 and Q 4 are both cut off and the output is almost an open circuit. Thus the control input can be thought as a switch which either permits the device to as a normal IC or disconnects its output from the circuit. The logic symbol for a tri-state device is shown in the figure below. Input Enable Output 2.4 Logic Gates The table below shows the logic symbol and their truth table for the common TTL gates. Operators AND NAND OR NOR XOR TTL # 7408 7401 7432 7402 Symbols A B Y Truth Table B A Y · = B A Y · = B A Y + = B A Y + = B A Y © = A B 0 0 0 1 0 1 0 0 1 0 1 1 0 1 1 0 0 1 1 0 1 1 1 1 0 1 0 0 - Three-State Outputs A Y C A Y C Y A Off = ¦ ´ ¹ , , if C is high if C is low Y A Off = ¦ ´ ¹ , , if C is low if C is high 74126 74125 Chapter 2 DIGITAL ELECTRONICS Page: 40 ©2011, ME, NUS 2.4.1 Some Properties of NAND Gate The NAND gate is the most versatile digital logic device. All of the Boolean logic gates we have discussed can be constructed using only NAND gates. The logic diagrams below illustrate the NAND- equivalence of various logic gates. Single Gate NAND Equivalence Inverter AND OR NOR Exclusive OR Exclusive NOR Gate 2.4.2 Some combinatorial logic examples 2.4.2.1 Half Adder We know from previous chapter that binary addition satisfy the following condition: Truth Table A B S C 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 From the truth table above we can derive that the sum, S, and the carry, C, are as follows B A C B A B A B A S · = © = · + · = 2.4.2.2 Full Adder Beside the input A and B, addition usually involves the carry forward from the lesser significant position of the digit. Hence, the truth table of a full adder is as follows: Cn-1 A B S Cn 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 0 1 1 Half Adder A B C S ME3241/ME3241E Microprocessor and Applications ©2011, ME, NUS Page: 41 From the truth table, we have S = 1 1 1 1 ÷ ÷ ÷ ÷ · · + · · + · · + · · n n n n C B A C B A C B A C B A = ( ) ( ) 1 1 1 1 ÷ ÷ ÷ ÷ · + · · + · + · · n n n n C B C B A C B C B A = ( ) ( ) 1 1 ÷ ÷ © · + © · n n C B A C B A = 1 ÷ © © n C B A Also, n C = 1 1 1 1 ÷ ÷ ÷ ÷ · · + · · + · · + · · n n n n C B A C B A C B A C B A = ( ) B A B A C B A n · + · · + · ÷1 = ( ) B A C B A n © · + · ÷1 Therefore, the full adder (FA) can be constructed from two half adder as shown below. Full Adder Half Adder A n B n Half Adder S n C n-1 C n FA B C -1 C S A A 4-bit adder can be constructed by cascading 4 FA’s as shown below. FA 0 A B C -1 C S FA 1 A B C -1 C S FA 2 A B C -1 C S FA 3 A B C -1 C S Carry S 0 S 1 S 2 S 3 B 0 B 1 B 2 B 3 A 3 A 2 A 1 A 0 Note: The parallel adder above performs additions at a relatively high speed. However, its speed is limited by an effect called carry propagation or carry ripple. The carry bits have to propagate from one stage to the next. Hence, the output of each FA is therefore not stable until the carry-in from the previous stage is calculated. Each output stabilize in the order from right to left as the carries ripple through the chain. An commercial example of 4-bit adder is 74283. 2.5 Flip-flops and Latches The logic gates discussed in earlier section are what we called as memory-less devices. Circuits made out of these devices are usually called combinational logic. In general, digital systems are made up of combinational circuits and memory elements as shown in the diagram below. The circuit consists of inputs from external signals and feedback from the outputs of the memory elements. Some of the outputs are stored in the memory elements which outputs are feedback to the circuit. An important memory element is the flip-flop (FF), which is made up of an assembly of logic gates. The most basic FF circuit can be constructed from two NAND gates or two NOR gates. The NAND Chapter 2 DIGITAL ELECTRONICS Page: 42 ©2011, ME, NUS gate version is called a NAND gate latch whereas the NOR gate version is called NOR gate latch. This is sometime referred as latch or bi-stable multi-vibrator. Combinational logic gates Memory elements Combinational outputs Memory outputs External inputs 2.5.1 NAND gate Latch: The figure below shows a NAND gate latch, in which, two NAND gates are cross-coupled so that the output of one NAND gate is connected to the input of the NAND gate and vice versa. The table below shows the truth table of the flip-flop. When both inputs SET and CLEAR are normally set at HIGH such that the output Q retains its pre-stored value. The output can be “set” to HIGH or “clear” to LOW by pulling the SET or CLEAR pin to LOW, respectively. Noting that both SET and CLEAR are not allowed to be pulled to LOW simultaneously! SET Q Q CLEAR Example1: The waveform below shows how the output responses the pins SET and CLEAR . Example2: An application of the SC latch is to use it to prevent phenomena called the contact bounce. V OUT +5V 1 2 Switch to position 2 Switch come to rest in position 2 Bouncing V OUT +5V 1 2 S C Q +5V Switch to position 2 Switch back to position 1 S E T CLEAR Q 1 1 No Change 0 1 1 1 0 0 0 0 Invalid! Q = Q = 1 ME3241/ME3241E Microprocessor and Applications ©2011, ME, NUS Page: 43 2.5.2 Clocked Flip-Flops: Digital systems can operate either asynchronously or synchronously. - Asynchronous systems: outputs can change state at any time. - Synchronous systems: outputs state change determined by clock. NGT Clk PGT Time In synchronous systems, the output changes its state by a signal called clock. It is a square pulse train that is distributed to most part of the system such that the outputs change state only when the clock makes a transition (also called edges). When the clock changes from “0” to “1”, it is called a Positive-going transition (PGT). Similarly, when the clock changes from “1” to “0” it is called a Negative-going transition (NGT). The Synchronizing action of the clock is accomplished by clocked flip-flops that are designed to change states on one of the clock transition. A typical clocked flip-flop consists of: - clock input (CLK or CK or CP) - two outputs usually termed as Q and Q where Q is also a complement of Q. - one or more control inputs which have not have effect on Q until the flip-flop is “clocked”. - 2 initialization input (to be discussed later) to momentarily change the state of Q. Control inputs Clk Q Q Init i/p Control inputs Clk Q Q Init i/p PGT activated flip-flop NGT activated flip-flop 2.5.3 Making of Clocked S-C Flip-Flop The NAND flip-flop in Section 2.5.1 does not have any enable/disable facilities. In order to have some level of control when the inputs can controls the output Q, we add two more NAND gate at the input as shown in the figure below. SET Q Q CLEAR SET E CLEAR *SET CLEAR E/ D Q X X 0 No Change 0 0 1 No Change 0 1 1 0 1 0 1 1 1 1 1 Ambiguous Chapter 2 DIGITAL ELECTRONICS Page: 44 ©2011, ME, NUS The input E acts like an enable/disable switch to control the inputs effect. Noting that when E is LOW, both SET and CLEAR pins will be HIGH. From the truth table in Section 2.5.1, Q will remain unchanged. On the other hand, when E is HIGH, then the state of pins SET and CLEAR will depend on the value of pins SET and CLEAR. It behaves as if an inverter is appended to each of the input SET and CLEAR . The Table above shows the behaviours of the modified flip-flop. To acquire an edge-triggered flip-flop, we insert an edge detector before pin E as shown in the figure below. Clk SET Q Q CLEAR SET CLEAR Edge detector Clk* The figures below show the case for both PGT or NGT triggered edge detector. CLK CLK CLK* CLK CLK CLK* CLK CLK CLK* CLK CLK CLK* Positive-going transition Negative-going transition Positive Edge Triggered SC Flip-Flop S C Q Q Asynchronous Inputs Most clocked flip-flops also have one or more asynchronous inputs which operate independently of the synchronous inputs and clock input. These asynchronous inputs can be used to set the flip-flop to the HIGH state or clear the flip-flop to the LOW state at any time regardless of the condition of the other inputs. It is usually used to override the input to set or clear the flip-flop. S C Clk Q 0 0 | Q 0 1 0 | 1 0 1 | 0 1 1 | Ambiguous ME3241/ME3241E Microprocessor and Applications ©2011, ME, NUS Page: 45 SC Flip-flop Set Clear Q Q S CLK C SET CLEAR Q 1 1 Clocked Mode 1 0 0 0 1 1 0 0 Not Allowed 2.5.4 Clocked J-K Flip-Flop J K Q Q Positive edge going J K Q Q Negative edge going K 1 0 J 1 0 Clk 1 0 Q 1 0 a b c d e f J K Clk Q 0 0 | Q0(no change) 1 0 | 1 0 1 | 0 1 1 | Q 0 (toggles) J K Clk Q 0 0 + Q 0 (no change) 1 0 + 1 0 1 + 0 1 1 + Q 0 (toggles) Chapter 2 DIGITAL ELECTRONICS Page: 46 ©2011, ME, NUS JK Flip-flop with Asynchronous Inputs J K Q Q Preset Clear Example: J K Q Q PRE CLR +5V 2.5.5 Clocked D Flip-Flop D Q Q s S C Q Q D Clk J K Q Q D Clk Equivalent D Flip-flop by SC Flip-Flop Equivalent D Flip-flop by JK Flip-Flop Preset Clear Q 1 1 Clocked mode 0 1 1 1 0 0 0 0 Not used D Clk Q 0 | 0 1 | 1 ME3241/ME3241E Microprocessor and Applications ©2011, ME, NUS Page: 47 2.5.6 D Latch (Transparent Latch) D Q Q EN - The D Latch (74 373) - A latch is a digital device that stores a 1 or a 0 on its output. - The device functions as follows: (See the Truth Table above). - if the enable input EN is low, the logic level present on the input will have no effect on the Q and Q outputs. - if the enable input is high, a high or a low on the D input will be passed to the Q output. - when the enable input is made low again, the state on Q at that time will be latched there. 2.5.7 Timing Consideration for Flip-flop - Setup and Hold Times Synchronous control input Clock input t H Hold time t s Setup time - Two timing requirements must be met if a clocked FF is to respond reliably to its control inputs when the active CLK transition occurs. - Setup time, S t , is the time interval immediately preceding the active transition of the CLK signal during which the synchronous input has to be maintained at the proper level. (Usually specified in S t (min)). - Hold time, H t , is the time interval immediately following the active transition of the CLK signal during which the synchronous input has to be maintained at the proper level. (Usually specified in H t (min)). - Propagation Delay - Whenever a signal is to change the state of a FF’s output, there is a delay from the time the signal is applied to the time when the output makes its change. - Usually referred to as t PLH and t PHL - Maximum Clocking Frequency - The highest frequency that may be applied to the CLK input of a FF. - Usually referred to as f MAX - Clock Pulse HIGH and LOW Times - The minimum time duration that the clock must remain LOW before it goes HIGH, t W (L) - The minimum time duration that the clock must remain HIGH before it goes LOW, t W (H) 0 1 Clock t W (H) t W (L) EN D Q 0 X Q 0 (no change) 1 0 0 1 1 1 Chapter 2 DIGITAL ELECTRONICS Page: 48 ©2011, ME, NUS - Asynchronous Active Pulse Width - The minimum time duration that a PRESET or CLEAR input has to be kept in its active state in order to reliably set or clear the FF. 0 1 PRE or CLR t W (L) 2.5.7.1 Some Flip-Flop Applications 1. Detecting an input Sequence Suppose that we want to generate a high output only if A goes high and then B goes high sometime later. J K Q Q A B X A B X A B X A goes HIGH before B A goes HIGH after B 2. Data Storage and Transfer D A A D B B Transfer K Q Q K K Q Q K Transfer enable Synchronous transfer Asynchronous transfer D Transfer X 1 X 1 X 1 Y 1 Y 1 D Y 1 Y 1 D Y 1 Y 1 Parallel transfer 2.6 Counters and Registers 2.6.1 Registers - A register is a device you use to store some information, in its simplest form, a flip-flop. S D Q Clk Q R Write pulse Storage +5V Input Write pulse Input Storage Q - However, one flip-flop can only store two possible values, i.e. a ONE or a ZERO. - We usually group a few flip-flop to form one set of storage e.g. - 1 nibble ÷ 4 bits ME3241/ME3241E Microprocessor and Applications ©2011, ME, NUS Page: 49 - 1 byte ÷ 8 bits - The most commonly used group is byte (8 flip-flops). Write pulse Storage +5V I 1 I 0 Input S D Q Q R S D Q Q R S D Q Q R S D Q Q R S D Q Q R S D Q Q R S D Q Q R S D Q Q R I 3 I 2 I 5 I 4 I 7 I 6 Q 1 Q 0 Q 3 Q 2 Q 5 Q 4 Q 7 Q 6 2.6.1.1 Transferring of Registers content - Parallel transfer of value in register A to Register B Register B Write Pulse Register A A 1 A 0 D A 3 A 3 A 2 D A 2 D A 1 D A 0 D B 3 D B 2 D B 1 D B 0 B 1 B 0 B 3 B 2 - Serial Transfer of value from Register A to Register B(Shift Register) Register B Register A Write Pulse D A 3 D A 2 D A 1 D A 0 D B 3 D B 2 D B 1 D B 0 B 1 B 0 B 3 B 2 - Asynchronous Shift Register J Q Q K SET CLR Y X I3 J Q Q K SET CLR Y X I2 J Q Q K SET CLR X I1 J Q Q K SET CLR Y X I0 Y Stepping Pulse Parallel Load Serial Input Serial Output Chapter 2 DIGITAL ELECTRONICS Page: 50 ©2011, ME, NUS 2.6.2 Counters - We will consider asynchronous as well as synchronous counters. - In asynchronous counters, circuit elements do not get the clock input simultaneously. - In synchronous counters, circuit elements get the clock input simultaneously. 2.6.2.1 Asynchronous (Ripple) Counters J K A +5V J K B +5V J K C +5V J K D +5V Clk A B C D - FF outputs can only toggle. - Clock connected to first (LSB) FF only. Succeeding FFs get their clock input from output of previous FF. - Each FF A, B, C, and D successively halves the clock input frequency. - Counter counts in sequence from 0000 (0) – 1111 (15) - Counter has 16 distinct count states, and is called a mod-16 counter. - In general, N-FFs connected up this way will have 2 N states – a mod-2 N counter. 2.6.2.2 Counter with mod-X < 2 N - Assume counter starts from 0. - Find which FFs will be in HIGH state when count = X. - Feed those FF outputs to a NAND gate. - Connect NAND gate output to the asynchronous CLR input of all FFs. - Example: A Mod-6 Counter J K A +5V J K B +5V J K C +5V Clr Clr Clr Clk A B C 1 2 3 4 5 6 7 8 9 10 11 12 NAND - More examples J K A J K B J K C Clr Clr Clr J K D Clr J K A J K B J K C Clr Clr Clr J K D Clr Mod-14 Counter Mod-10 Counter ME3241/ME3241E Microprocessor and Applications ©2011, ME, NUS Page: 51 2.6.2.3 Ripple Counter that counts down. - Connect complements of FF outputs to clock inputs of succeeding FFs. J K A +5V J K B +5V J K C +5V J K D +5V A B C D 2.6.2.4 Problems in Ripple Counters. Accumulation of Propagation Delay - Ripple counters are easy to implement – but have one major drawback: - Can’t operate beyond a limiting frequency. So, only used for low freq. applications. - The limitation is due to the propagation delays of the FFs in the chain add up: - Clock input to FF 1 : t 0 (clock transition time) Clock input to FF 2 : t 0 + t pd Clock input to FF 3 : t 0 + 2 t pd .. Clock input to FF n : t 0 + (n-1) t pd - This implies that the n th FF rather than changing state at t 0 it changes state at t pd . - Hence t clock > n t pd or f max s 1 n t pd - The following waveform illustrate propagation delay of a Mod-8 Ripple Counter A 1 2 3 4 5 Clk B C 1000ns 50ns 100ns 150ns - Clock Period = 1 ms - Propagation delay after NGT of the Clock Signal t pd (Max) = 150ns << 1 ms --- OK - Say, we increase the clock frequency to have Clock Period = 100 ns A 1 2 3 4 5 Clk B C 100ns 50ns 100ns 150ns - Note: There is no 100 in the counts!!! Example: A 4-bit ripple counter is constructed using the 74LS112 J-K flip-flop. From the spec., we have t PLH = 16 ns and t PLH = 24 ns. To calculate the maximum allowable clock frequency, we use the worst case (i.e. t pd = 24ns) f max s 1 n t pd = 1 4 x 24ns = 10.4 MHz Chapter 2 DIGITAL ELECTRONICS Page: 52 ©2011, ME, NUS Decoding Glitches - This is another problem encountered with ripple counters if the states have to be decoded. - Again due to propagation delays. - Depending on application, may/may not be a relevant. - Example J K A J K B A B X 0 X 1 X 2 X 3 Clk 1 0 #1 #2 #3 #4 Clk 1 0 A 1 0 B Temporay 00 state Temporay 10 state 1 0 X 0 1 0 X 1 1 0 X 2 1 0 X 3 FF and decoding waveform for a mod-4 ripple Counter showing glitches at X0 and X2 outputs. - These decoding glitches can be eliminated by a strobe signal. X 0 A B X 1 A B X 2 A B X 3 A B Strobe signal 1 0 #1 #2 #3 #4 Clk 1 0 Strobe Decoder disabled t D Decoder enabled - t D is chosen be greater than the total time it takes the counter to reach a stable count (depends on FF delays and number of FFs). - This method need not be used when the decoder drives a display – glitch is not visible. - But must be used when decoder drives other circuitry. 2.6.2.5 IC Asynchronous Counters (74x293) J K Q 1 1 C D J K Q 1 1 C D J K Q 1 1 C D J K Q 1 1 C D Q 1 Q 2 Q 3 (MSB) Q 0 (LSB) CP 0 CP 1 MR 1 MR 2 74293 Q 0 Q 1 Q 2 Q 3 MR 1 MR 2 CP 1 CP 0 - Consist of 4 JK flip-flops with output Q 0 , Q 1 , Q 2 and Q 3 (Q 0 is LSB and Q 3 is MSB) - The clock inputs of Q 0 and Q 1 are externally accessible and labeled 0 CP and 1 CP , respectively. - Each FF has an asynchronous CLEAR input, C D . These are connected together to the output of a 2-input NAND gate with inputs MR 1 and MR 2 – Need MR 1 = MR 2 = 1 to reset the counter to 0000. - Q 1 , Q 2 and Q 3 are already connected as a 3-bit ripple counter. FF Q 0 is not connected to anything internally. (Some flexibility here) ME3241/ME3241E Microprocessor and Applications ©2011, ME, NUS Page: 53 Example 1: Mod-16 Counter 74293 Q 0 Q 1 Q 2 Q 3 MR 1 MR 2 CP 1 CP 0 Example 2: Mod-10 Counter 74293 Q 0 Q 1 Q 2 Q 3 MR 1 MR 2 CP 1 CP 0 Example 3: Mod-50 Counter 74293 Q 0 Q 1 Q 2 Q 3 MR 1 MR 2 CP 1 CP 0 74293 Q 0 Q 1 Q 2 Q 3 MR 1 MR 2 CP 1 CP 0 Not Used f in /10 f in /50 2.6.2.6 Synchronous (Parallel Counters) J K A J K B J K C J K D Input - The propagation delay problem encountered with ripple counters can be overcome by using synchronous or parallel counters. - The diagram above shows a MOD-16 parallel counter with "A" as the LSB and "D" as the MSB. Noting that all clock inputs are triggered simultaneously. - Technique used: - When J=K=0, output does not change on the clock pulse - When J=k=1, output toggles on the clock pulse. - Notice that all FFs are triggered by the same clock. - A toggles at every NGT (J,K=1). - B toggles when A = 1. - C toggles when AB = 1. - D toggles when ABC = 1. - The additional logic gates ensure that the FFs toggle at the right time. - The total delay involved in this sync. counter is t pd = t pd (FF) + t pd (AND) - Hence counter operates at higher frequency than corresp. ripple counter. Example: If t pd (FF) = 50 ns. and t pd (AND) = 20 ns. What is the max operating frequency? t pd (total) = 50 + 20 = 70 ns. Hence, t clock > 70 ns, i.e. f max < 1 70 ns = 14.3 MHz (irrespective of no. of FFs). On the other hand for a 4-bit ripple counter, Chapter 2 DIGITAL ELECTRONICS Page: 54 ©2011, ME, NUS f max < 1 4 x 50 ns = 5 MHz. 2.6.2.7 Synchronous Down and Up Counters J K Q Q A J K Q Q B Count Up/ Down J K Q Q C Input C B A 7 1 1 1 6 1 1 0 5 1 0 1 4 1 0 0 3 0 1 1 2 0 1 0 1 0 0 1 0 0 0 0 - When Counting up - A = 1 to toggle B - A = B = 1 to toggle C - When Counting down - A = 0 to toggle B - A = B = 0 to toggle C - The Count-up and Count-down signal control the counting sequence. - Count sequence is up if Count Up/ Down input = 1. - Here, J(A) = K(A) = 1, J(B) = K(B) = A and J(C) = K(C) = A.B. - Count sequence is down if Count Up/ Down input = 0. - Here, J(A) = K(A) = 1, J(B) = K(B) = A and J(C) = K(C) = A . B . 2.6.2.8 Presettable Counters - Many synchronous counters that are available as ICs are designed to be presettable - Can be pre-set to any desired count asynchronously or synchronously. - Sometime referred as loading the counter. Clock J K Q A Clr Pre J K Q B Clr Pre J K Q C Clr Pre P 2 P 1 P 0 PL ME3241/ME3241E Microprocessor and Applications ©2011, ME, NUS Page: 55 2.6.2.9 IC Presettable Counter (74x193) P 1 P 2 P 3 P 0 PL 74193 Mod-16 up/down counter Q 0 Q 1 Q 2 Q 3 MR + - TC U TC D CP U CP D - Pin Description - CP U – Count-up clock input (active rising edge) - CP D – Count-down clock input (active rising edge) - MR – Asynchronous master reset input (active HIGH) - PL - Asynchronous parallel load input (active LOW) - P 0 -P 3 – Parallel data inputs - Q 0 -Q 3 – flip-flop outputs - TC U – Terminal count-up (carry) output (active LOW) - TC D – Terminal count-down (borrow) output (active LOW) Example1: Up-counter - Parallel data inputs = 1011 - Initial flip-flops output = 0000 1 0 1 1 PL 74193 + - TC U TC D CP U CP D P 0 P 1 P 2 P 3 PL Q 0 Q 1 Q 2 Q 3 MR 1 1 0 CP U 1 0 PL 1 0 MR 1 0 Q 0 1 0 Q 1 1 0 Q 2 1 0 Q 3 1 0 TC U t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 MR PL CP U CP D Mode H X X X Asyn. reset L L X X Asyn. preset L H H H No change L H | H Count up L H H | Count down Chapter 2 DIGITAL ELECTRONICS Page: 56 ©2011, ME, NUS Example2: Down-counter 1 1 0 1 PL 74193 + - TC U TC D CP U CP D P 0 P 1 P 2 P 3 PL Q 0 Q 1 Q 2 Q 3 MR 1 1 0 CP D 1 0 PL 1 0 Q 0 1 0 Q 1 1 0 Q 2 1 0 Q 3 1 0 TC D t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 2.6.2.10 Synchronous Counter Design - A subset of Sequential Circuit Design - Approach: Given the state diagram of a counter realize it using common FFs and combinational logic. Combinational Logic FFs E x t e r n a l I n p u t Clk - All FFs are clocked at the same time. - Must make sure the logic level at every FF’s input pins stabilize to a correct level before each clock pulse. - Choices of flip-flops Transition JK Flip-flop D Flip-flop J K D 0÷0 0 X 0 0÷1 1 X 1 1÷0 X 1 0 1÷1 X 0 1 - Design Steps 1. Determine the desired number of bits and choice of FF used. 2. Draw the state transition diagram showing all possible states. 3. Use the state transition diagram to set up a table that list all PRESENT states and their NEXT states 4. Add the column to this table for each flip-flop input. 5. Design the logic circuits to generate the levels required at each flip-flop input. ME3241/ME3241E Microprocessor and Applications ©2011, ME, NUS Page: 57 - Example 1: Design a 3-bit counter that counts from 000 to 111 and back to 000. - Step 1: Since it is 3 bit counter, we need 3 flip-flops. Say, use D flip-flops. - Step 2: State transition diagram. 000 010 110 100 101 011 001 111 - Step 3&4: Generate the truth table Present State Next State Flip-Flops Q2 Q1 Q0 Q2 Q1 Q0 D2 D1 D0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 - Step 5: Logic Design flip-flops. D0 = Q2 . Q1 . Q0 + Q2 .Q1. Q0 + Q2. Q1 . Q0 + Q2.Q1. Q0 = Q2 . Q0 + Q2. Q0 = Q0 D1 = Q2 . Q1 .Q0 + Q2 .Q1. Q0 + Q2. Q1 .Q0 + Q2.Q1. Q0 = Q2 .( Q1 .Q0 + Q1. Q0 ) + Q2.( Q1 .Q0 + Q1. Q0 ) = ( Q1 .Q0 + Q1. Q0 ) = Q1 © Q0 D2 = Q2 .Q1.Q0 + Q2. Q1 .Q0 + Q2. Q1 . Q0 + Q2.Q1. Q0 = Q2 .Q1.Q0 + Q2. Q1 .(Q0 + Q0 ) + Q2.( Q1 + Q1). Q0 = Q2 .Q1.Q0 + Q2. Q1 + Q2. Q0 Combinational Logic D Q 2 Q 2 D Q 1 Q 1 D Q 0 Q 0 Q 2 Q 1 Q 0 Clk Homework: Repeat this with JK flip-flops. Chapter 2 DIGITAL ELECTRONICS Page: 58 ©2011, ME, NUS Example 2: Design a 3-bit counter that counts from 000÷001÷010÷011÷100÷000 - Step 1: Since it is 3 bit counter, we need 3 flip-flops. Say, use JK flip-flops. - Step 2: State transition diagram. 000 010 100 011 001 Note: There undefined states like 101, 110 and 111 - Step 3&4: Generate the truth table Present State Next State Flip-Flops Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0 0 0 0 0 0 1 0 X 0 X 1 X 0 0 1 0 1 0 0 X 1 X X 1 0 1 0 0 1 1 0 X X 0 1 X 0 1 1 1 0 0 1 X X 1 X 1 1 0 0 0 0 0 X 1 0 X 0 X 1 0 1 X X X X X X X X X 1 1 0 X X X X X X X X X 1 1 1 X X X X X X X X X - Step 5: Logic Design flip-flops. For J0. Present State Flip-Flops Q2 Q1 Q0 J0 0 0 0 1 0 0 1 X 0 1 0 1 0 1 1 X 1 0 0 0 1 0 1 X 1 1 0 X 1 1 1 X J0 = Q2 For K0, it can be seen from the table above that K0= 1. Similarly, for J1, K1, J2 and K2, we have J0 Q0 Q0 Q2 . Q1 1 X Q2. Q1 0 X Q2.Q1 X X Q2 .Q1 1 X J1 Q0 Q0 Q2 . Q1 0 1 Q2. Q1 0 X Q2.Q1 X X Q2 .Q1 X X J1 = Q0 K1 Q0 Q0 Q2 . Q1 X X Q2. Q1 X X Q2.Q1 X X Q2 .Q1 0 1 K1 = Q0 J2 Q0 Q0 Q2 . Q1 0 0 Q2. Q1 X X Q2.Q1 X X Q2 .Q1 0 1 J2 = Q1.Q0 K2 Q0 Q0 Q2 . Q1 X X Q2. Q1 1 X Q2.Q1 X X Q2 .Q1 X X K2 = 1 ME3241/ME3241E Microprocessor and Applications ©2011, ME, NUS Page: 59 Therefore, J0 = Q2 , K0 = 1 J1 = K1 = Q0 J2 = Q1.Q0, K2 =1 J Q Q 2 K J Q Q 1 K J Q Q 0 K Q 0 Q 1 Q 2 1 1 Clk 2.6.2.11 Synchronous vs. asynchronous circuit designs - Sync. operations generally preferred to async. operations, since latter require great care to address problems such as - Races due to unequal path delays. - Transients and glitches which can cause incorrect operation. - Output changes that depend on order of async. input changes. - Synchronous circuits bypass these problems by use of the clock which allows outputs to change only at discrete time instants. - This allows time for transients and glitches to settle down, races to be resolved etc. 2.6.2.12 Counter Applications: Digital Clock Pulse shaper Mod-50 Counter Mod-2 Mod-10 Mod-6 Mod-10 Mod-6 Mod-10 Decoder/ Display Decoder/ Display Decoder/ Display Decoder/ Display Decoder/ Display Decoder/ Display 50 Hz Main 50 pps 1 pps "Seconds" section 0-9 Units 0-9 Units 0-9 Units 0-5 Tens 0-5 Tens 0-1 Tens "Minutes" section "Hours" section - Pulse shaper can be constructed by a transformer and a schmitt trigger - Mod-50 Counter can be constructed by a mod-10 counter cascading a mod-5 counter. - Mod-10 and Mod-6 Counters can be constructed by either a BCD counter or any 16-bit counter with reset capability. - Mod-2 Counter can be constructed by just a JK flip-flop. - Decoder/Display units can be constructed by a BCD to 7-segment display decoder (see tutorial) and a 7-segment display LED. 2.6.2.13 Other Counters Register Based Counters - Ring Counter - A circulating arrangement where a single 1 moves from FF to FF. - In most instances, only a single 1 circulates. Chapter 2 DIGITAL ELECTRONICS Page: 60 ©2011, ME, NUS - Counter is initialized by presetting a 1 into one FF and clearing the rest. - Mod-N counter needs N FFs (more hardware than other counters for same mod-#). - N FFs mod-N counter. - On the other hand, this counter does not need any decoding gates at all (saving). - Example: A Mod-4 ring counter consists of 4 flip-flops. 0001 0010 0100 1000 D Q Q d D Q Q c D Q Q b D Q Q a 0 1 0 1 0 1 0 1 Clk Q d Q c Q b Q a 2.7 Encoders, Decoders 2.7.1 Decoders 2.7.1.1 3-8 Decoders - A decoder is a circuit element that will decode an N-bit code. - It activates an appropriate output line as a function of the applied N-bit input code. - Example: a 3-8 decoder. A2 A1 A0 O0 O1 O2 O3 O4 O5 O6 O7 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1 A 0 A 1 A 2 O 0 O 1 O 2 O 3 O 4 O 5 O 6 O 7 - A decoder can have up to 2 N output lines for N inputs. - MSI decoders are available as 2-4, 3-8, 4-10 decoders, etc. - Example: The 74’138 decoder 3-8 decoder. ME3241/ME3241E Microprocessor and Applications ©2011, ME, NUS Page: 61 74138 1-of-8 decoder A 0 A 1 A 2 O 0 1 2 3 E O 1 O 2 O 3 O 4 O 5 O 6 O 7 E 1 E 3 E 2 1 2 3 E 1 E 3 E 2 A 2 A 0 A 1 O 0 O 1 O 2 O 3 O 4 O 5 O 6 O 7 - It has NAND gate output, i.e. active low. - The decoder can be enabled/disabled by the input pins 1 E , 2 E and 3 E . - The chip is enable only when 1 E = 2 E =0 and 3 E = 1. - The enable pins allow multiple chip to be used together for higher bit decoding. - Example: Use 4 74138 decoders to set up a 1-32 decoder. 74138 A 0 A 1 A 2 1 2 3 E 0 1 2 3 4 5 6 7 74138 A 0 A 1 A 2 1 2 3 E 0 1 2 3 4 5 6 7 74138 A 0 A 1 A 2 1 2 3 E 0 1 2 3 4 5 6 7 74138 A 0 A 1 A 2 1 2 3 E 0 1 2 3 4 5 6 7 A 0 A 1 A 2 A 3 A 4 O 0 - - - - - - -O 7 O 8 -- - - - - - O 15 O 16 -- - - - -- O 23 O 24 -- - - - -- O 31 E 1 E 2 E 3 Output 0 0 1 Respond to input code A 2 A 1 A 0 1 X X Diabled – all HIGH X 1 X Diabled – all HIGH X X 0 Diabled – all HIGH Chapter 2 DIGITAL ELECTRONICS Page: 62 ©2011, ME, NUS a b c d e f g 2.7.1.2 BCD-to-Decimal Decoder - Used whenever an output or group of outputs is to be activated only on the occurrence of a specific combination of input levels. - Commercially available decoders are - 7442 BCD-to-decimal decoder, or - 7445 BCD-to-decimal decoder/driver (Open collector version) - Example: Design a circuit which consists of 5 LED’s arranged in a line such that these LED will lights up in the following sequence. L1 ON for 1 s and OFF for 1s, L2 ON for 1 s and OFF for 1s, L3 ON for 1 s and OFF for 1s, L4 ON for 1 s and OFF for 1s, and L5 ON for 1 s and OFF for 7s. After that L1 start again and repeat itself. Solution: 2.7.1.3 BCD to 7 Segment decoder - Converts a BCD number into signals required to display that number on a 7- segment display. - 7-segment displays are of 2 types: - common anode - all LED anodes connected – active low - common cathode - all LED cathodes connected – active High. - Each segment is an LED which will light when a logic T signal is applied to it. Commercial BCD to 7 Segment decoder - 7447 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7447 BCD to 7 Seg D C B A LT a RBI RBO b c d e f g Active LOW ME3241/ME3241E Microprocessor and Applications ©2011, ME, NUS Page: 63 Func Input BI/ RBO Output LT RBI D C B A a b c d e f G 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 1 1 X 0 0 0 1 1 1 0 0 1 1 1 1 2 1 X 0 0 1 0 1 0 0 1 0 0 1 0 3 1 X 0 0 1 1 1 0 0 0 0 1 1 0 4 1 X 0 1 0 0 1 1 0 0 1 1 0 0 5 1 X 0 1 0 1 1 0 1 0 0 1 0 0 6 1 X 0 1 1 0 1 1 1 0 0 0 0 0 7 1 X 0 1 1 1 1 0 0 0 1 1 1 1 8 1 X 1 0 0 0 1 0 0 0 0 0 0 0 9 1 X 1 0 0 1 1 0 0 0 1 1 0 0 10 1 X 1 0 1 0 1 1 1 1 0 0 1 0 11 1 X 1 0 1 1 1 1 1 0 0 1 1 0 12 1 X 1 1 0 0 1 1 0 1 1 1 0 0 13 1 X 1 1 0 1 1 0 1 1 0 1 0 0 14 1 X 1 1 1 0 1 1 1 1 0 0 0 0 15 1 X 1 1 1 1 1 1 1 1 1 1 1 1 BI X X X X X X 0 1 1 1 1 1 1 1 RBI 1 0 0 0 0 0 0 1 1 1 1 1 1 1 LT 0 X X X X X 1 0 0 0 0 0 0 0 Commercial BCD to 7 Segment decoder - 7448 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 7448 BCD- to- 7Seg a b c d e f g RBO RBI A B C D LT Active HIGH Func Input BI/ RBO Output LT RBI D C B A a b c d e f G 0 1 1 0 0 0 0 1 1 1 1 1 1 1 0 1 1 X 0 0 0 1 1 0 1 1 0 0 0 0 2 1 X 0 0 1 0 1 1 1 0 1 1 0 1 3 1 X 0 0 1 1 1 1 1 1 1 0 0 1 4 1 X 0 1 0 0 1 0 1 1 0 0 1 1 5 1 X 0 1 0 1 1 1 0 1 1 0 1 1 6 1 X 0 1 1 0 1 0 0 1 1 1 1 1 7 1 X 0 1 1 1 1 1 1 1 0 0 0 0 8 1 X 1 0 0 0 1 1 1 1 1 1 1 1 9 1 X 1 0 0 1 1 1 1 1 0 0 1 1 10 1 X 1 0 1 0 1 0 0 0 1 1 0 1 11 1 X 1 0 1 1 1 0 0 1 1 0 0 1 12 1 X 1 1 0 0 1 0 1 0 0 0 1 1 13 1 X 1 1 0 1 1 1 0 0 1 0 1 1 14 1 X 1 1 1 0 1 0 0 0 1 1 1 1 15 1 X 1 1 1 1 1 0 0 0 0 0 0 0 BI X X X X X X 0 0 0 0 0 0 0 0 RBI 1 0 0 0 0 0 0 0 0 0 0 0 0 0 LT 0 X X X X X 1 1 1 1 1 1 1 1 Chapter 2 DIGITAL ELECTRONICS Page: 64 ©2011, ME, NUS - Uses of RBO and RBI 2.7.2 Encoders - Perform the inverse of the decoding function. - For N different inputs, an encoder is a circuit element that generates an M-bit binary code (2 M > N) that uniquely identifies the input. - Example: An 8-3 encoder. O 0 O 1 O 2 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A O2 O1 O0 X 1 1 1 1 1 1 1 0 0 0 X 0 1 1 1 1 1 1 0 0 1 X 1 0 1 1 1 1 1 0 1 0 X 1 1 0 1 1 1 1 0 1 1 X 1 1 1 0 1 1 1 1 0 0 X 1 1 1 1 0 1 1 1 0 1 X 1 1 1 1 1 0 1 1 1 0 X 1 1 1 1 1 1 0 1 1 1 - Commercial Decimal to BCD Priority encoder A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 74147 Decimal to-BCD priority encoder O 1 O 2 O 3 O 0 Inverted BCD I n p u t s 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A O3 O2 O1 O0 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X X X X X X 0 0 1 1 0 X X X X X X X 0 1 0 1 1 1 X X X X X X 0 1 1 1 0 0 0 X X X X X 0 1 1 1 1 0 0 1 X X X X 0 1 1 1 1 1 0 1 0 X X X 0 1 1 1 1 1 1 0 1 1 X X 0 1 1 1 1 1 1 1 1 0 0 X 0 1 1 1 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 ME3241/ME3241E Microprocessor and Applications ©2011, ME, NUS Page: 65 2.8 Multiplexers & demultiplexers 2.8.1 Multiplexers I 0 I 1 I 2 I 3 Output Z S 0 S 1 I 0 Z I 1 I 2 I 3 S 0 S 1 - A multiplexer (MUX) is a combinational circuit element that selects data from one of many inputs and directs it to a single output. - Example: A 4-input multiplexer S 1 S 0 Output 0 0 Z = I 0 0 1 Z = I 1 1 0 Z = I 2 1 1 Z = I 3 - Comercial 8-input multiplexer (74151) - Multiplexer has an ENABLE which is active-low - When E=0, the select inputs S 2 S 1 S 0 will select one data input (I0~I7) for passage to output Z. - When E=1, multiplexer is disabled. - Both normal and inverted output are provided E S2 S1 S0 Z Z 1 X X X 1 0 0 0 0 0 0 I I0 0 0 0 1 1 I I1 0 0 1 0 2 I I2 0 0 1 1 3 I I3 0 1 0 0 4 I I4 0 1 0 1 5 I I5 0 1 1 0 6 I I6 0 1 1 1 7 I I7 74151 MUX I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 S 0 E Z Z S 2 S 1 Chapter 2 DIGITAL ELECTRONICS Page: 66 ©2011, ME, NUS - Commercial Quad Two-input MUX (74157) S Za Zb Zc Zd 1 X 0 0 0 0 0 0 I 0a I 0b I 0c I 0d 0 1 I 1a I 1b I 1c I 1d S E I 1a I 1b I 1c I 1d I 0a I 0b I 0c I 0d Z a Z b Z c Z d 2.8.2 Multiplexer Applications - Logic Function Generation Truth Table C B A Z 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 - Operation Sequencing 74151 MUX I 0 I 1 I 3 I 4 I 5 I 6 I 2 I 7 S 0 S 1 S 2 E Z 1KO 74157 Quad 2 input MUX I0d I0c I0b I0a I1d I1c I1b I1a S E Z d Z c Z b Z a ME3241/ME3241E Microprocessor and Applications ©2011, ME, NUS Page: 67 - Data Routing 7447 BCD to 7 Seg Decoder/Driver 7-Segment Display Units 7447 BCD to 7 Seg Decoder/Driver 7-Segment Display Tens 74157 MUX E S I 1 I 0 Za Zb Zc Zd 74157 MUX E S I 1 I 0 Za Zb Zc Zd Select BCD Counter BCD Counter BCD Counter BCD Counter Counter 1 Counter 2 Tens Tens Units Units Clk #1 Clk #2 (Tens) (Units) 2.8.3 Demultiplexers - Demultiplexer takes a single input and distributes it over several outputs. - The select input code determines to which output the DATA input will be transmitted. O 0 DEMUX O 1 O 2 O 3 Data input S 0 S 1 - 1-line-to-8-line Demultiplexer Select Outputs S2 S1 S0 O7 O6 O5 O4 O3 O2 O1 O0 0 0 0 0 0 0 0 0 0 0 D 0 0 1 0 0 0 0 0 0 D 0 0 1 0 0 0 0 0 0 D 0 0 0 1 1 0 0 0 0 D 0 0 0 1 0 0 0 0 0 D 0 0 0 0 1 0 1 0 0 D 0 0 0 0 0 1 1 0 0 D 0 0 0 0 0 0 1 1 1 D 0 0 0 0 0 0 0 S 0 S 1 S 2 Data O 0 O 1 O 2 O 3 O 4 O 5 O 6 O 7 Chapter 2 DIGITAL ELECTRONICS Page: 68 ©2011, ME, NUS - 74138 decoder as a demultiplexer - Use the enable input E 1 as the data input I. 74138 1-of-8 decoder A 0 A 1 A 2 O 0 1 2 3 E O 1 O 2 O 3 O 4 O 5 O 6 O 7 E 1 E 3 E 2 2.8.4 Demultiplexer Applications - Security Monitoring System 330 O +5 V Mod-8 Counter Q 2 Q 1 Q 0 door 7 door 6 door 0 +5 V +5 V +5 V 74LS151 MUX S 2 S 1 S 0 E I 0 I 6 I 1 I 2 I 3 I 4 I 5 I 7 Z 74LS138 DEMUX O 0 O 1 O 2 O 3 O 4 O 5 O 6 O 7 A 2 A 1 A 0 1 2 3 Clock +5 V ©2011, ME, NUS Page: 69 Chapt er 3 Microprocessor Architecture 3.1 Making of a microprocessor 3.1.1 Registers, ROM’s, Ram’s and Buses 3.1.1.1 Register - A register is a device you use to store some information, in its simplest form, a flip-flop. S D Q Clk Q R Write pulse Storage +5V Input Write pulse Input Storage Q o However, one flip-flop can only store two possible values, i.e. a ONE or a ZERO. o We usually group a few flip-flop to form one set of storage e.g. o 1 nibble ÷ 4 bits o 1 byte ÷ 8 bits o 1 word ÷ 16 bits. - The most commonly used group is byte (8 flip-flops). Q Q SET CLR D Q Q SET CLR D Q Q SET CLR D Q Q SET CLR D Q Q SET CLR D Q Q SET CLR D Q Q SET CLR D Q Q SET CLR D I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 O 7 O 6 O 5 O 4 O 3 O 2 O 1 O 0 Write Pulse - However, we sometime wish to share the input and output line together. This can be achieved by the use of a D – Latch as such. Q Q D L R/W CE Data CE R/ W Data 1 X Not connected 0 0 Writing data to memory 0 1 Reading from memory - Cascading four of these latches form a nibble of register. Q Q D L R/W CE Q Q D L Q Q D L Q Q D L Q 0 Q 1 Q 2 Q 3 - To transfer data between Register A & B Q Q D L R/W a CE a Q Q D L Q Q D L Q Q D L A 0 A 1 A 2 A 3 Reg A Q Q D L R/W b CE b Q Q D L Q Q D L Q Q D L B 0 B 1 B 2 B 3 Reg B - Transferring between accumulator and two other registers Chapter 3 Microprocessor Architecture Page: 70 © 2011, ME, NUS Acc R/W CE D 3 . . D 0 Reg X R/W CE D 3 . . D 0 Reg Y R/W CE D 3 . . D 0 Read/ Write X/Y - Transferring many to one 2-to-4 Decoder Acc R/W CE D 3 . . D 0 Read/ Write R/W CE D 3 . . D 0 R/W CE D 3 . . D 0 R/W CE D 3 . . D 0 R/W CE D 3 . . D 0 0 1 2 3 A 0 A 1 - A 4-Nibble RAM R/W CE D 0 D 3 R/W CE D 0 D 3 R/W CE D 0 D 3 R/W CE D 0 D 3 Decoder A 0 D 0 D 3 A 1 D a t a D 0 D 3 A 0 A 1 R/W CE 3.1.1.2 RAM - As illustrated in previous section, we have constructed a very small size 4-nibble RAM. - Acronym for random access memory, a type of computer memory that can be accessed randomly; that is, any byte of memory can be accessed without touching the preceding bytes. - Most common type of memory found in computers and other devices, such as printers. - It usually consists of the following pins - READ/ WRITE to control read/write status of the memory - A 0 ~A n to select a specific memory cell - D 0 -D 7 to read/write the actual data - CE to enable or disable the chip. - Also now as volatile memory, meaning that they lose their contents when the power is turned off. - There are two basic types of RAM (based on different technology): - dynamic RAM (DRAM) 4 K RAM A 0 A 11 D 0 D 7 C E R / W NUS Logo Microprocessor Architecture ©2011, ME, NUS Page: 71 - Needs to be refreshed. - More commonly used - Some variance of DRAMs are: - EDO DRAM - a type of DRAM that is faster than conventional DRAM. Unlike conventional DRAM which can only access one block of data at a time, EDO RAM can start fetching the next block of memory at the same time that it sends the previous block to the CPU. - BEDO DRAM (Burst EDO DRAM) - a new type of EDO DRAM that can process four memory addresses in one burst. - SDRAM (Synchronous DRAM) - a new type of DRAM that can run at much higher clock speeds than conventional memory. SDRAM actually synchronizes itself with the CPU's bus and is capable of running at about twice as fast EDO DRAM and BEDO DRAM. SDRAM is replacing EDO DRAM in many newer computers - RDRAM (Rambus DRAM) - a type of memory (DRAM) developed by Rambus, Inc. Faster than SDRAM (600 MHz). Being used in place of VRAM in some graphics accelerator boards. Intel and Rambus are also working a new version of RDRAM, called nDRAM, that will support data transfer speeds at up to 1,600 MHz. - static RAM (SRAM) - Static RAM does not need to be refreshed, which makes it faster; - More expensive than dynamic RAM. 3.1.1.3 ROM - Acronym for read-only memory - Computer memory on which data has been prerecorded. Once data has been written onto a ROM chip, it cannot be removed and can only be read. - Unlike RAM, ROM retains its contents even when the computer is turned off. ROM is referred to as being nonvolatile, whereas RAM is volatile. - It usually consists of the following pins - A 0 ~A n to select a specific memory cell - D 0 -D 7 to read the actual data - CE to enable or disable the chip. - PC’s usually contain ROM that stores critical programs such as the program that boots the computer. (e.g. BIOS in your IBM compatible PC) - Also used extensively in calculators and peripheral devices such as laser printers, whose fonts are often stored in ROMs. - Variation of a ROM are - PROM (programmable read-only memory). - PROMs are manufactured as blank chips on which data can be written with a special device called a PROM programmer. - Can be written to only once - EPROM (erasable programmable read-only memory) - A special type of memory that retains its contents until it is exposed to ultraviolet light. - The ultraviolet light clears its contents, making it possible to reprogram the memory. - To write to and erase an EPROM, you need a special device called a PROM programmer or PROM burner. - EEPROM (electrically erasable programmable read-only memory) - A special type of PROM that can be erased by exposing it to an electrical charge. Like other types of PROM, EEPROM retains its contents even when the power is turned off. Also, like other types of ROM, EEPROM is not as fast as RAM. 16 K ROM A 0 A 13 D 0 D 7 C E Chapter 3 Microprocessor Architecture Page: 72 © 2011, ME, NUS 3.1.1.4 Concepts of bus - Some Bus Example 4 nibble RAM D 0 D 3 A 0 A 1 R/W CE 4 nibble RAM D 0 D 3 A 0 A 1 R/W CE 4 nibble RAM D 0 D 3 A 0 A 1 R/W CE 4 nibble RAM D 0 D 3 A 0 A 1 R/W CE MicroP D 0 D 3 A 0 A 3 R/W CE Decoder Data Bus Address Bus Control Bus 3.1.2 Digital Arithmetic Circuits - From previous chapter, we have constructed a full adder A B S C n-1 C n FA B C -1 C S A - 4-Bit Adder 4 Bit Adder FA B C -1 C S A FA B C -1 C S A FA B C -1 C S A FA B C -1 C S A A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0 S 3 S 2 S 1 S 0 C 0 C 4 - Addition with Registers 4 Bit Adder S 0 S 3 C 4 C 0 Reg A Q 0 Q 3 Reg B Q 0 Q 3 Temp Q 0 Q 3 Clk Tri-States NUS Logo Microprocessor Architecture ©2011, ME, NUS Page: 73 - Parallel Add/Subtract using 2’s complement 4 Bit Adder S 0 S 3 C 4 C 0 Reg A Q 0 Q 3 Reg B Q 0 Q 3 Temp Q 0 Q 3 Clk Tri-States Q 0 Q 1 Q 1 Q 2 Q 2 Q 3 Add/ Subtract 3.1.3 A Very Simple microprocessor Microprocessor Accumulaor Tmp Reg 1 Arithmetic Unit Add/ Subtract Tmp Reg 2 Internal Data Bus Tri-state Buf Data Bus Instr Regs Instr Decoder Address Register Address Bus RAM ROM PIO External I/O Control Bus ME3241/ME3241E Microprocessor and Applications ME3241/ME3241E MICROPROCESSOR APPLICATIONS By: A/P GS Hong (Digital Electronics) Room: EA-05-24 Phone: 6516 2272 E-mail:
[email protected] Dr. Xu Huan (MicroP) E1-05-17 65161604
[email protected] ME3241E 13 Jan 2012 Friday 18:00–21:30 LT7A ME3241 Start Date: 09 Jan 2012 Time: Venue: Monday 10:00-012:00 Friday 9:00-11:00 E1-06-04 (Monday) Examination Date: 24 April 2012 (pm) Reference books: 1. RL Tokheim, "Digital electronics: Principles and applications", 7th edition, 2008, McGrawHill. 2. RJ Tocci, "Digital systems: Principles and applications", 6th edition, 1995, Prentice-Hall, Inc. 3. S Brown and Z Vranesic, "Fundamentals of digital logic with Verilog design", 2nd edition, 2008, McGrawHill. 4. LD Jones, "Principles and applications of digital electronics", Macmillan, 1986. 5. TF Bogart, Jr., "Introduction to digital circuits", McGraw-Hill International Student Edition, 1992 6. H-W Huang, "PIC microcontroller: an introduction to software and hardware interfacing", Clifton Park, NY: Thomson/Delmar Learning, 2005. Page: ii © 2011, ME, NUS Contents Chapter 1 1.1 1.2 1.1.1 1.2.1 1.2.2 1.2.3 1.2.4 1.2.5 1.2.6 1.2.7 1.2.8 1.2.9 1.2.10 1.3 1.3.1 1.3.2 1.3.3 1.3.4 1.3.5 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.5 1.5.1 1.5.2 Chapter 2 2.1 2.2 Number System and Codes ..................................................................................... 5 Number System Representation .............................................................................. 5 Binary to Decimal ..................................................................................................... 7 Decimal to Binary ..................................................................................................... 7 Octal to Decimal ....................................................................................................... 9 Decimal to Octal ....................................................................................................... 9 Octal to Binary ........................................................................................................ 10 Binary to Octal ........................................................................................................ 10 Hexadecimal to Decimal ......................................................................................... 11 Decimal to Hexadecimal ......................................................................................... 11 Hexadecimal to Binary ........................................................................................... 11 Binary to Hexadecimal ........................................................................................... 11 Binary Coded Decimal Code .................................................................................. 12 Gray Code .............................................................................................................. 13 Alphanumeric Codes - ASCII Code ........................................................................ 16 Error Detection ....................................................................................................... 17 Error Correction ...................................................................................................... 19 Binary Addition ....................................................................................................... 21 Binary Subtraction .................................................................................................. 21 Binary Multiplication ............................................................................................... 22 Binary Division ....................................................................................................... 22 Representing Signed Numbers .............................................................................. 22 Integer Notation ...................................................................................................... 27 Floating Point Notation ........................................................................................... 27 DIGITAL ELECTRONICS ....................................................................................... 31 Number Systems.............................................................................................................. 5 Conversion between number systems ............................................................................. 7 Codes and Coding ......................................................................................................... 12 Binary Arithmetic ............................................................................................................ 21 Numeric Notation Used in Computers ............................................................................ 27 Introduction .................................................................................................................... 31 Boolean algebra ............................................................................................................. 31 Definition ................................................................................................................ 31 Boolean Identities ................................................................................................... 31 Digital IC Terminology ............................................................................................ 32 TTL Logic ............................................................................................................... 35 Some Properties of NAND Gate ............................................................................. 40 Some combinatorial logic examples ....................................................................... 40 2.2.1 2.2.2 2.3 2.3.1 2.3.2 2.4 2.4.1 2.4.2 2.5 Integrated Circuit Logic .................................................................................................. 32 Logic Gates .................................................................................................................... 39 Flip-flops and Latches .................................................................................................... 41 Page: iii © 2011, ME, NUS .......... 72 A Very Simple microprocessor ............ 69 Registers...4 2.......5. 46 D Latch (Transparent Latch).................. 48 Encoders...................................................................... 64 Multiplexers ......5...................................................................................................................8.............................. 60 Multiplexers & demultiplexers ................................1 2..............4 Chapter 3 3...............1 3................... 60 Encoders ......................................................... 69 Digital Arithmetic Circuits................................................... 65 Making of a microprocessor .....................3 2..............6.5..........................................................................................7 2......................2 2.....................3 2...... Decoders ......................................5.. 68 Microprocessor Architecture .....................................5............................7 2............................................................................. 48 Counters..... 47 Timing Consideration for Flip-flop .............................2 2.........8..2 3................................................................................6..............................................7.................................8...................................2 2............ ROM’s.....1 2................................................ME3241/ME3241E Microprocessor and Applications 2...........................5.......3 NAND gate Latch: ............. 69 Page: iv © 2011................................................................................................................. 65 Multiplexer Applications ...................................1........1 3.....1........... ME......5................................................................. 73 Counters and Registers...........................................1 2.............................................................6 2.. 42 Clocked Flip-Flops: ...........................................1 2.......................................................................................................1............. Ram’s and Buses ............................................ 66 Demultiplexers................................................................................................... NUS ........................... 47 Registers .................................................................................... 50 Decoders ................8..........................................................................2 2.... 43 Clocked J-K Flip-Flop ........8 2........... 45 Clocked D Flip-Flop ....................................7......... 43 Making of Clocked S-C Flip-Flop ....6 2..........5 2.................................................................................. 67 Demultiplexer Applications ................ The study of number systems is not just limited to computers.1. We apply numbers every day. we read six thousand five hundred and fifty seven.1.1. © 2011.2. and 1.9 Examples: 82510 = 8 x 102 + 2 x 101 + 5 x 100 368.1 Decimal System (Base 10) The decimal system is the number system we (human being) are familiar with..6. in a number system with the base r is represented in the form of N r An An1 A0 .1. Amount many number system.1 Number Systems A number system is a quantifying system ones adopted for counting.html 1. r 1 This number representation is also known as weighted position number system.1) where i = number of places the digit is relative to the radix point r = radix or the base of the system Ai 0.1. The following subsections show a few common examples of such representation. Human start their ways of counting in many different ways and finally evolved to the current approach of number system representation. For convenience.4.4910 = 3 x 102 + 6 x 101 + 8 x 100 + 4 x 10-1 + 9 x 10-2 Decimal system is the current “Universal Standard” used by human being.1.1. For a good appreciation of the historical number system representation. 1.8.dcs. NUS Page: 5 .st-andrews.1 . that is 6 x 1000 + 5 x 100 + 5 x 10 + 7 x 1 The above example demonstrated a common number system we adopted. In this case.5.. the commonest is the system known as weighted position representation. It is known as N r . In this case r = 2. A1 Am i m Ar i n i ( 1.3.7.uk/~history/Indexes/Number_Theory.1 Number System Representation Consider the number 6557. and Ai 0.1. please refer to http://www-groups. we normally just omit the subscript 10 in our notation. the base Ai 0. etc. The quantity involved can be the number of people attending this class.Chapter 1 Number System and Codes 1. Definition: A number. weighted position representation. r = 10. ME.ac.2 Binary System (Base 2) The binary system is the number system that computer is using. and knowing how numbers work will give us an insight into how a computer manipulates and stores numbers. the number of elective modules a student has to take. hexadecimal system is a number system that is commonly used by the low level programmer for better visual recognition of the codes.7 Example: The number 405.38 Also 102. we are running out of symbol to represent the values 10~15. 26562510 1.3 Octal System (Base 8) Octal system is a number system that is commonly used by the low level programmer for better visual recognition of the codes.4.125 = 2 1 0 -1 261. these binary states make it easy for Boolean implementation in the computer. Example: The number 11012 has the representation Weightage Number It has an equivalent decimal value of 11012 Also 23 1 22 1 21 2 0 0 1 = 1 x 23 + 1 x 22 + 0 x 21 + 1 x 20 = 1310 110. 3 It has an equivalent decimal value of 405. NUS .2. 0 16 4 -1 Page: 6 © 2011.6. We use the alphabets A~F to represents these values. E .1.3. ME.37510 Ai 0. F Noting that.1.6. A. Ai 0.9.2510 1.218 = 1 x 82 + 0 x 81 + 2 x 80 + 2 x 8-1 + 1 x 8-2 = 64 + 0 + 2 + 2 x 0.8.2. In this case.3. in hexadecimal system.5. B. = 4x8 + 0x8 + 5x8 + 3x8 = 4 x 64 + 0 + 5 x 1 + 3 x 0.1. Example: The number 3B.4 Hexadecimal System (Base 16) Like the octal system. D.25 = 6.7.1.1.416 has the representation of Weightage Number 16 3 1 r = 16 16 B.5.125 + 0.4.012 = 1 x 22 + 1 x 21 + 0 x 20 + 0 x 2-1 + 1 x 2-2 = 4 + 2 + 0 + 0 + 0. In this case. C .015625= 66.1.ME3241/ME3241E Microprocessor and Applications In binary system there are only two states (zero and one).38 has the representation of Weightage Number r=8 82 81 80 8 1 4 0 5. 416 = 3 x 161 + 11 x 160 + 4 x 16-1 = 3 x 16 + 11 x 1 + 4 x 0. this number can be represented in another base of radix value N rb by N rb i ma Ar na i i a ( 1. r = 10). There are two other methods to convert a decimal number to binary number. When you are given with a number in one base. 1. the human being is familiar with the decimal system (i.2. ra. What is the equivalent representation in another base. NUS Page: 7 .1 ) Then.3 ) Example: The number 1010. We can use this to convert a number of any bases into a decimal system.2510 Also. rb? A quick solution to this will be the use of the weighted position representation definition in (1.e. we can also use the same weighted sum approach as in (1.2) with the arithmetic be computed in base rb.25 = 10.12510 1.2. say. For instance.3). N10 i m2 b 2 i n2 i ( 1.012 = 1 x 2 = 8 3 + 0x2 + 0 2 + 1x2 + 2 1 + 0x2 + 0 0 + 0x2 + 0 -1 + 1x2 + 0. © 2011. Given a number N ra represented by N ra An An 1 A0 .216 = 1 x 162 + 0 x 161 + 2 x 160 + 2 x 16-1 = 1 x 256 + 0 x 16 + 2 x 1 + 2 x 0.2) with rb = 10. ( 1.2.2 Decimal to Binary The above examples showed the conversion from binary system to decimal system. A1 A m .2510 -2 1. How about the reverse process? To do this.012 can be converted to a decimal as 1010.2 Conversion between number systems We now see that a numerical value can be represented in many different bases of representation. the decimal number 3410 can be converted to its binary equivalence by 3410 3 101 4 100 112 10101 1002 10100 2 2 111102 1102 100010 2 However the above method involves binary arithmetic.0625 = 258. say.1.2. 102.2. Such approach is not practical as we are not familiar with arithmetic with any bases other than 10.0625 = 59.2.1).1 Binary to Decimal We use the weighted sum approach as in (1. For instance.2. Such formulation implies the requirement of a base that the “computer” is familiar with.Number System and Codes 3B. ME. 1 Method 1 Express the decimal number as a sum of powers of 2 and then 1’s and 0’s are written in the appropriate bit position.687510 26 2 13 2 62 32 12 = 13 R 0 Least significant bit = 6R1 = 3R0 = 1R1 = 0 R 1 Most significant bit For the integer part. alternatively. we can use successive division technique to convert a decimal number to a base-r representation. we say Nr A2 r 1 A1r 0 remainder A0 r Similarly. Multiplying Nr by its radix r yields N r r A1r 1 A2 r 2 A3 r 3 r A1r 0 A2 r 1 A3 r 2 Noting that.ME3241/ME3241E Microprocessor and Applications 1. 26. 1. N r A2 r A1r A0 r .2.510 = 32 + 8 + 4 + 1 + 0.687510 to its binary representation.2.2 Method 2 2 1 0 Consider a 3-digit based-r integer.2.5 = 25 + 0 + 23 + 22 + 0 + 20 + 2-1 = 101101. ME. we can use successive multiplication technique to convert a fractional decimal number into a base-r representation. we have Page: 8 © 2011. Example: 45.2.12 7610 = 64 + 8 + 4 = 26 + 0 + 0 + 23 + 22 + 0 + 0 = 10011002 Note: This method require you to be familiar with the various $2^i$ values. the first radix place of the fractional number becomes the integer part in the result. Dividing Nr by its radix value yields A r 2 A1r 1 A0 r 0 Nr 2 r r A A2 r 1 A1r 0 0 r Or. NUS . That is.687510 = 2610 + 0. consider a base-r fractional number with 3 radix 1 2 3 places N r A1r A 2 r A3 r . Example: Convert the decimal number 26. A2 r 1 A1r 0 A2 r 0 remainder A1 r Hence. For the case of fractional number. 610 to its binary representation. © 2011.) 1.10112 Example: Convert the decimal number 43. this implies that 0.6 0.Number System and Codes For fractional part.4 Decimal to Octal For decimal to octal conversion.610 = 43 + 0.48 can be converted to a decimal number by 326.2 0.6 1.6 : : : x x x x x 2 2 2 2 2 = = = = = 1.750 1. we have 0.6875 0.375 0.510 1.500 1.100112 (up to 5 digits approx.000 MSB LSB By repeated division by 2 for the integer part and multiplication by 2 for the fractional part. 43. the binary representation is 26.5 = 214. Hence.2 : : : MSB Repeated Noting that the fractional conversion never ends. the binary representation with 5 digits approximation is 43.610 = 101011.8 1.48 = 3 x 82 + 2 x 81 + 6 x 80 + 4 x 8-1 = 192 + 16 + 6 + 0. NUS Page: 9 . For the integer part. ME.2.2.5 Hence. we use repeated division by 8 for the integer part and repeated multiplication by 8 for the fractional part.4 0.75 0.2.375 0.4 ) Example: The octal number 326.4 0. we have 43 2 = 21 R 1 Least significant bit 21 2 = 10 R 1 10 2 = 5 R 0 52= 2R1 22= 1R0 1 2 = 0 R 1 Most significant bit For the fractional part.6 x x x x 2 2 2 2 = = = = 1. N10 i m A8 i n i ( 1. we use the weighted sum approach to convert Octal number to decimal number.687510 = 11010.2 0.8 0. we have 0.610 does not has an exact binary representation.3 Octal to Decimal Similarly. 2. Example: The binary number 1111100101. Then.375 Hence.2.5 Octal to Binary In general.168 © 2011. 1 68 = 1745.1 shows that.5 ) For instance. However.54687510. from base-r to base-p. 001 1102 = 1 7 4 5 .54687510 = 37910 + 0. Table 1.2. On the other hand. we can convert the binary number to its octal representation by first grouping the binary number in groups of 3 bits starting from the radix point.0011102 can be converted to its octal representation by 1111100101. we have 0.2. for each of the 3 bits pattern. match it with its corresponding octal value.658 = 010 111 001. we can first convert the base-r number to its decimal representation by weighted position method and followed by the successive and division by p to base-p number. each octal digit is matched to unique 3-bits binary pattern.0011102 = 001 111 100 101 .2.375 0. Table 1. Hence. we have 379 8 = 47 47 8 = 5 5 8 = 0 For the fractional part. the octal representation is 379. How about the conversion between two non-decimal systems? Say. for a special case of p and r that has the relationship of x8 = 3.1Octal digit to binary pattern Octal digit 0 1 2 3 4 5 6 7 Binary pattern 000 001 010 011 100 101 110 111 Example: The octal number 271.54687510 For the integer part.000 Least significant digit R R R 3 7 5 Least significant digit Most significant digit Most significant digit p ri ( 1. NUS Page: 10 .54687510 = 573. ME.438 1.110 1012 1. 271.658 can be converted to its binary presentation by simple pattern matching as show below. the octal number has a radix of 8 and binary has a radix of 2 which has the relationship of 8 = 23. we can simplify the conversion process by matching technique.546875 x 8 = 4. we use the weighted position method to do the conversion.6 Binary to Octal As each octal digit has a unique 3 binary bits code.ME3241/ME3241E Microprocessor and Applications Example: Consider the decimal number 379. respectively. the conversion from decimal to nondecimal system use the method of successive division and multiplication by the radix value for integer and fractional parts. it consists of 379. for conversion from a non-decimal system to decimal system. Table 1.2.54687510 = 17B.54687510. Noting that 16 = 24. it consists of 379. ME. this implies one hexadecimal digit will map to four binary bits.9 Hexadecimal to Binary Similarly. Then. we use repeated division by 16 for the integer part and repeated multiplication by 16 for the fractional part.Number System and Codes 1.75 0.2.6516 can be converted to its binary representation as follows: A94.8C16 1. the hexadecimal number has a radix of 16 and binary has a radix of 2.2.29687510 1.2.10 Binary to Hexadecimal Similarly. Table 1.0110 01012 1.046875 = 59.25 + 0. we have 379 16 = 23 23 16 = 1 1 16 = 0 For the fractional part. we can convert the binary number to its octal representation by first grouping the binary number in groups of 4 bits starting from the radix point. Example: Consider the decimal number 379.546875 x 16 = 8. each octal digit is matched to unique 3-bits binary pattern.00 = C.6 ) Example: The hexadecimal number 3B. match it with its corresponding hexadecimal value.00 379.2 Hexadecimal digit to binary pattern Hex digit 0 1 2 3 4 5 6 7 Bin pattern 0000 0001 0010 0011 0100 0101 0110 0111 Hex digit 8 9 A B C D E F Bin pattern 1000 1001 1010 1011 1100 1101 1110 1111 remainder remainder remainder 11 = B 7 1 Least significant digit Most significant digit Example: The hexadecimal number A94.54687510 For the integer part. © 2011. we have 0.75 x 16 = 12.6516 = 1010 1001 0100. NUS Page: 11 . we use the weighted sum approach to convert hexadecimal number to decimal number.2. each hexadecimal digit has a unique 4 binary bits code. for each of the 4 bits pattern.4C16 can be converted to its decimal representation by 3B.2. we can simplify the conversion process by matching technique.7 Hexadecimal to Decimal Similarly.54687510 = 37910 + 0.8 Decimal to Hexadecimal For decimal to hexadecimal conversion.2 shows that. For such case.2.4C16 = 3 x 161 + 11 x 160 + 4 x 16-1 + 12 x 16-2 = 48 + 11 + 0. N 10 i m A 16 i n i ( 1. conversions are needed to/from decimal/binary. This implies that. binary coded decimal (BCD) is one of the popular codes used in industries. There are many 1. In addition.1 Binary Coded Decimal Code While computers work in binary.3816 1.1. '+' and other symbols which might be associated with communicating a value. BCD is a code used to represent a decimal digit by its binary equivalent. 0110 1000 0011 1001 (BCD Code) = 683910 6 8 3 9 Page: 12 © 2011. There are many different internationally accepted standard codes. e.001112 = 0011 1110 0101 . Table 1. Among them.'. ME.3 Codes and Coding 1. the most common BCD is the 8421-BCD. humans work in decimal. Example: 3910 0011 1001 10710 0001 0000 0111 Note that conversion from BCD code to decimal is straight forward.1 8421-Binary Coded Decimal Decimal Digit BCD 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 Noting that 8421-BCD only used 10 out of the 16 possible combination of 4-bits binary number.3.3. when computers interface with people. 3 816 = 3E5.3. letters or words are represented by group of symbols called code.1 8-4-2-1 BCD Code In 8421-BCD. each decimal digit is represented by a 4-bit binary number which also has the binary numerical value of the decimal digit as shown in Table 1.g. to make thing easier for programmer and to make equipment with read-outs compatible with computer interfaces. 0011 10002 = 3 E 5 .1. '-'.ME3241/ME3241E Microprocessor and Applications Example: 1111100101.3. variances of BCD code. Some vendor use these remaining combination for some special characters likes '. 'E'. numbers. NUS . NUS Table 1. for straight binary number representation. Table 1. It is often used in situations where other codes. might produce erroneous or ambiguous results during those transitions in which more than one bit of the code is changing. For instance.2 Variance of BCD Codes Decimal Digit 0 1 2 3 4 5 6 7 8 9 BCD 8-4-2-1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 Excess-3 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Biquinary 50 43210 01 00001 01 00010 01 00100 01 01000 01 10000 10 00001 10 00010 10 00100 10 01000 10 10000 Most straightforward BCD representation. Whereas. the BCD Code converts each individual decimal digit to a set 4 bits binary code.3. absolute optical shaft encoders used in angular measurement. octal or hexadecimal. Example: Decimal Number 13710 Binary Number 100010012 BCD Code 0001 0011 0111 Noting that BCD requires more binary bits than straight binary number. Decimal 0 1 2 3 4 5 6 7 © 2011. To represent decimal number 137 in BCD we need 12 bits of code (4+4+4).Number System and Codes 1. It is not the same as straight binary number. 8-4-2-1: 1.3.1. with the weight of each digit corresponding to the same value as in the binary system Excess 3: Each value exceeds the normal binary value by three – simplifies the carry logic in parallel addition Biquinary: Used in communication the numbers from 0 to 9 are divided into two groups and one position of the code is used to determine in which group a given number is.3 Other variance of BCD Code There are many other variance of BCD used for some specific reasons. ME.3.3.3. 1.3 Example of a 4 bit Gray Code Binary Gray Code Decimal Binary 0000 0000 8 1000 0001 0001 9 1001 0010 0011 10 1010 0011 0010 11 1011 0100 0110 12 1100 0101 0111 13 1101 0110 0101 14 1110 0111 0100 15 1111 Gray Code 1100 1101 1111 1110 1010 1011 1001 1000 Page: 13 . A popular application of Gray code is in instrumentation and data acquisition systems where absolute linear or angular displacement is measured. It was originally designed to prevent spurious output from electromechanical switches.2 below. is an encoding such that two successive code differ in only one bit.3. named after Frank Gray who introduce this code in 1947.2 Comparison of BCD Code and Binary Number BCD is not another number system like binary.1. an 8-bits binary number has the range of 0~255. A straight binary code takes the complete decimal number and represents it in binary. such as binary.2 Gray Code Gray code. A few popular variances of it is listed in Table 1. Whereas. and a five position code is used to determine the number in the group. The base case.3. G = {" "}). 1. 1}. the same situation will only has one bit change in the case of Gray code. For instance. both sensors read the value of 8 (binary=1000 and Gray=1100).2. The base case can also be thought of as a single zero-bit Gray code (n = 0. in position 3. Method 1: Gray code construction To generate the Gray Code.3. For example. the Gray coded encoder reads the value of 8 (Gray=1100). Then insert 0’s to the left of these codes on the upper half and 1’s on the lower half. Figure 1. prefixing the original bits with a binary 0 and then prefixing the reflected bits with a binary 1.2. is the most basic Gray code. 1.1 Comparison between Gray code and binary code.3. ME. Whereas. the sensor for the binary coded encoder reads the value of 15 (binary=1111). we start by a 1 digit Gray Code Decimal 0 1 Step 2: For 2 digits Gray Code. which is made into the one-bit code by the recursive process. we first repeat the 1 digit Gray Code in the reverse order. Decimal 0 1 Page: 14 Gray Code 0 1 Gray Code 00 01 © 2011. a change from 710 to 810 has all 4 bits changed in the case of binary number. Whereas. it can be seen that the binary coded encoder can get an erroneous reading while the Gray coded encoder is more clean and less erroneous. it is used in absolute encoder. Similar.ME3241/ME3241E Microprocessor and Applications Gray code is often referred as binary reflected code or cyclic code.3. lists them in reverse order and concatenates the reverse list onto the original list).1 Comparison between Gray code and binary code. A specific property of Gray code is that the difference between two successive pair of number will only have only one bit change only. NUS . in position 2. Hence.3. It shows how the sensor values are read in both binary coded and Gray coded encoders.1 Advantage of Gray Code This one-bit change feature of the Gray code has been utilized in many applications.2 Generation of Gray Code The binary-reflected Gray code for n bits can be generated recursively by reflecting the bits (i. we utilize the reflected code properties as follows: Step 1: To generate an n-digit (say.e. G = {0.3 shows an example of 4-bits Gray code with its corresponding 4-bit binary representation. Figure 1. n=4) Gray Code. for n = 1 bit. However. both sensors read the value of 7 (binary=0111 and Gray=0100). Table 1. In position 1. Decimal 0 1 2 3 4 5 6 7 Step 4: For 4 digits Gray Code. repeat Step 2 with 2-digit Gray Code and so on.1 ) Method 3: Gray Code to Binary Conversion To convert from Gray Code number B bn 1bn 2 b0 . n-1 with bn = 0 gi bi 1 0 bi .3. NUS Page: 15 . ME. This can be interpreted as follows: To convert a Binary number G g n 1 g n 2 g 0 . we use the formula B bn 1bn 2 b0 . …. 1. bi 1 1 . repeat Step 2 with 3-digit Gray Code and so on. we first define G g n 1 g n 2 g 0 to its corresponding binary © 2011. ( 1. Each bit is inverted if the next higher bit of the input value is set to one. for i = 0. Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Gray Code 0000 0001 0011 0010 0110 0111 0101 0100 1100 1101 1111 1110 1010 1011 1001 1000 Gray Code 000 001 011 010 110 111 101 100 Method 2: Binary to Gray Code Conversion The reflected code properties suggested a simple and fast method of translating a binary value into the corresponding Gray code.Number System and Codes 2 3 Step 3: 11 10 For 3 digits Gray Code. to its corresponding Gray code 1 bi . The code covers 26 lowercase alphabet. as the name calls. That is.4 ASCII Table HEX LSD 0 1 2 3 4 5 6 7 8 9 A B C D E F MSD Bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 000 NUL SOH STX ETX EOT ENQ ACK BEL BS HT LF VT FF CR SO SI VT FF CR SO SI DLE DC NAK SYN ETB 1 2 3 4 5 6 7 001 010 011 100 101 110 111 DLE SP 0 @ P ` p DC1 ! 1 A Q a q DC2 " 2 B R b r DC3 # 3 C S c s DC4 $ 4 D T d t NAK % 5 E U e u SYN & 6 F V f v ETB ' 7 G W g w CAN ( 8 H X h x EM ) 9 I Y i y SUB * : J Z j z ESC + . keyboards.3. Page: 16 © 2011.4 ASCII Table.3 Alphanumeric Codes . are used to control the machine via communication channel. …. punctuation marks and a set of special characters which is normally known as control characters.2 with g n 0 . the binary number B can be calculated from ( 1. S i 1 bi . modem etc. K | k { FG .ASCII Code Table 1. punctuation marks.ME3241/ME3241E Microprocessor and Applications n S i mod g j . It is a seven-bit code which provides 128 (2 =128) representation as shown in Table 1.3. j i 1 Then. for i = 0. To standardize on the representation of symbols.2 ) 1 g i .3. 1. NUS . international codes are used. These codes are used primarily for data transfer from computer to input/output devices such as printers.3. a computer need to handle non-numerical information. in addition to decimal digits.3. n-1 Si 0 gi . > N ^ n US / ? O _ o DEL Vertical Tabulation Form feed Carriage return Shift out Shift in Data link escape Device control negative ac knowledge synchronous idle end of transmission block CAN EM SUB ESC FG GS RS US SP DEL Cancel End of medium Substitute Escape File separator Group separator Record separator Unit separator Space Delete ( 1. it is 7 the normally referred as “askee” code (ASCII). 1. 10 decimal digits. These control characters. 26 uppercase alphabet. The most widely used alphanumeric code is the American Standard Code for Information Interchange (ASCII).3 ) Special ASCII Symbols NUL SOH STX ETX EOT ENQ ACK BEL BS HT LF Null Start of heading Start of text End of text End of transmission Enquiry Acknowledge Bell Back space Horizontal tab Line feed In addition to numerical data. ME. These codes are called alphanumeric codes. we also need codes to represent characters of the alphabet. < L \ l | GS = M } m } RS . and other special characters. any single-bit error will make the code invalid. a “0” may be read as “1” or vice versa.Number System and Codes Example 1: The following is a message in ASCII.2 Noise on transmitted data Whenever information is transmitted from one device (transmitter) to another device (receiver). It would be nice if we can implement some kind of coding such that any transmission error can be detected or corrected. NUS Page: 17 . For instance. ME. the number 7 will have the code “10 00100”. For instance. The following ASCII message is stored in the memory.3. there is a possibility that errors can occur such that the receiver does not receive the identical information that was sent by transmitter. the string “Cost = $72” 2.3. 100 1000 H 100 0101 E 100 1100 L 101 0000 P It represents the message HELP. For examples: Transmission of digitized voice over a microwave link. there is an error on U1. there is only one “1” is each of the groups. That is. What is the message? 101 0011 101 0100 100 1111 101 0000 1. So. One example is the Biquinary Code in earlier section which has the format of F5F0 U4U3U2U1U0 For a given number. Encode in ASCII. For example. one “1” from F5F0 and another one “1” from U4U3U2U1U0. say. Figure 1. Answer: G O T O 2 5 100 0111 100 1111 101 0100 100 1111 010 0000 011 0010 011 0101 Exercise: 1. Determine the ASCII Code that will be entered into memory when the operator types “GOTO 25”. Example 2: An operator is typing in a Basic program at the keyboard of a computer.4 Error Detection The transfer of binary data and codes from one location to another is the most common operation in digital systems. due to noise disturbance. resulted © 2011. Storage and retrieval data from external memory devices such as magnetic disks and tapes Transmission of information from a computer to a remote user terminal and another computer. To make it even. Case I: (Without parity bit) For a given transmission technique. “1” is added to the code as follows 1 100 0011 ASCII Code Parity bit is 1 in even parity mode Case 2: Odd Parity The value of the parity bit is chosen such that the total number of 1’s in the code group (including the parity bit) is odd. depends on the number of 1's that are contained in the code group. Odd parity: add another 1 or 0 to ensure total number of 1's is odd. p = 3. Example: Suppose that the character 'C' is to be transmitted. if the receiver actually receives the code 0100 0001. 0 is added to the code as follows 0 100 0011 ASCII Code Parity bit is 0 in odd parity mode Say. NUS . r = 400 bps) Page: 18 © 2011.1 x 10-5). To make it odd. Consider a case that we are transmitting a 7-bit ASCII code between two devices. the receiver will know that an error has occurred in the transmission because the received code has even number of 1’s. This indicated that the Biquinary Code is invalid. the code group is 100 0011. Parity Bit: A common practice used is the introduction of parity bit. Even Parity: add another 1 or 0 to ensure total number of 1's is even.3. A parity bit is an extra parity bit appended to the code group that is being transferred from one location to another. Note: The parity bit can only detect single-bit error only. There are three 1's in the ASCII code of 'C'.ME3241/ME3241E Microprocessor and Applications in the code received as “10 00110”. that is. 1. parity checks are used only when the probability of errors occurring and the risk associated with an error is high enough to warrant it. hence error is detected.1 Effect of Parity Check Parity checking may be employed at major interfaces in a digital system.4. Transmission rate is r (say. As there is two “1”’s in U4U3U2U1U0. Case 1:Even Parity The value of the parity bit is chosen such that the total number of 1’s in the code group (including the parity bit) is even. Since redundancy is added to each message. This additional bit can be either “0” or “1”. the probability of a bit be transmitted wrongly is p (say. ME. There are two methods used. 1. i 4. 1 r is chosen as the smallest number that satisfy the condition m r 1 2r The r + m bits of code are arranged in the order by the following rules: 1. the probability of transmitting an 8-bits ASCII code is P8. NUS Page: 19 .1. For 4 bit BCD code m = 4. 2. for i = 0. The following example illustrate how a BCD code can be Hamming coded.p)7 = 1. the average error rate is E7 is E7 = 1/ P7 x 1/ R7 = 80 sec. 5. Place parity bit P in (2i)th position. it is still invalid. For example. = 8. R7 = r/7 = 400/7 = Alternatively.6 days! Clearly. r-1. the single bit error will always be detected. Or. Number the bit position from 1 to (r+m).. Performs parity operation for each parity bit with the position correspond to the 2i positions. A popular error correction technique is the so-called Hamming Code. . 57. ME. 3. reading a corrupted CD-ROM. Case II: (With parity bit) With the parity bit implemented.5. Add r parity bits to an m-bit message to form an r+m bits Hamming code. . Therefore we only look at chances that 2 bits or more errors happen together. with an additional bit used as in Case II. P8 = 1 . the reliability has increased tremendously.(1-p)8 – 8p(1-p)7 = 2. Example: Consider the implementation of the Hamming Code on a 4 bit 8421-BCD code..5 Error Correction Sometime. Fill the remaining m positions by the message bits. therefore ( 1.4) © 2011.0.3. there may be situation that the message cannot be re-sent.69 x 10-8 and the transmission rate of R8. It will be preferred that an auto-correction can be implemented in this case. by transmitting with parity bit. P7 = 1 – (1 . besides detecting the error.3.3.Number System and Codes By transmitting without parity bit. no matter how many time you re-read the code.14 word per second 1. Hence. the probability of transmitting an 7-bits ASCII code is P7. the average error rate is E8 is E8 = 1/ P8 x 1/ R8 = 743273 sec.9999695 = 2. we want to be able to correct the error such that we can save the time for re-sending the message.1 Hamming Code Hamming code involves the design of a code that combine m message bits ( M m 1 M m2 M 1 M 0 ) with r extra parity bits ( Pr 1 Pr 2 P P0 ) such that single-bit error in the code can be corrected. R8 = r/8 = 50 word per second Alternatively.17 x 10-4 and the transmission rate of R7. M0} Say. a choice of r = 3 will satisfy the above condition. M0} = even { 0. 0} = 0 Hence the code is 11 0 0 110 Error Correction Say. 0} = 1 P2 = even { M2. M0} = even { 1. 1. M1. the code 110 0110 becomes 110 1110. In this case. for even parity and the code is 0110 (BCD “6”) P0 = even { M3. we need 3 parity bits in position 20=1. Clearly. Position 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (101) 7 (111) Bit P0 P1 M3 P2 M2 M1 M0 P2 P1 P0 Hence. M1. Hamming codes uses the technique of elimination to identify the error bit. Hamming code has strategically arranged the message bits and parity bits in such a way that the error code ( E2 E1 E0 ) reflect the error bit’s position. M0} = even { 0. Figure 1. M2. 1. it should be a 0 instead of 1. Hence the detected error bit can be identified. NUS . the corrected code should be 110 0110 Graphical interpretation of Hamming Code Effectively. Page: 20 © 2011. M2.ME3241/ME3241E Microprocessor and Applications 4 r 1 2r . And the code is arranged as follows: Position Code 1 P0 2 P1 3 M3 4 P2 5 M2 6 M1 7 M0 For parity assignment. By simple interception. M0} = even { 0. 0} = 1 P1 = even { M3.3. M2. M0} = even { 0. M0} = even { 1. M1. We check for the even parity of each parity bits C0 = even { M3. 1. we view the parity bits P2P1P0 as a 3-bit number. 0} = 1 = P0 E0=0 C1 = even { M3. 1. 21=2 and 22=4. 0} = 0 ≠ P2 E2=1 Hence. 0} = 1 = P1 E1=0 C2 = even { M2. M0} P1 checks on {M3. ME. the parity bits will check on P0 checks on {M3. M0} P2 checks on {M2. during transmission. M1. the error bit can be isolated. and Pi will performs parity operation with the position number with Pi=1.3 shows graphically how each message bit is associated with each parity bit. 1. M1. 1. the error position E2E1E0 = 100 = 4 Position 4 has error. M1. Hence. 1 Binary Addition Binary addition works in the similar way as we do our decimal addition.4.0012 = = = 3.2 Binary Subtraction Similarly. as binary number has only two elements {0. we have 1001. 10 1 0 011 1.0112 10. it is easier to performs binary addition.7510 6. NUS 9.3. for the subtraction of 610 from 9. In fact. We first has an addition table which give the results of addition of two decimal digits combination.510 -6.7510.02 = © 2011.12 = 0110. we have + 11.4. ME. 1.12510 Exercise: Find the sum of 101.510. We first have the binary addition table as shown below 0+0 0+1 1+1 1+1+1 = = = = 0 1 0 plus carry of 1 1 plus carry of 1 Examples: Consider the addition of two numbers 310 and 610. We first have the binary subtraction table as shown below 0-0 1-1 1-0 0-1 = = = = 0 0 1 1 with a borrow of 1 Example: Consider the subtraction of the number 510 from 1110.010 Page: 21 .37510 2.1}. correct them.4 Binary Arithmetic 1.01 + 110 + 10. for the numbers 3.1.1102 110.3 Graphical interpretation of Hamming Code Homework: Any error in this code? if any. we have 10112 = 1110 01012 = -510 01102 = 610 Similarly. we have 0 1 12 1 1 02 1 0 0 12 = = = 310 610 910 + Similarly.Number System and Codes Figure 1.37510 and 2. 4.ME3241/ME3241E Microprocessor and Applications 0011. in an extreme cold (below freezing point) condition. For instance. It is in fact easier for binary multiplication as the multiplier digits are either 0 or 1 and nothing else.510 1. etc. when you go to the basement of a building.1) N xs N B Page: 22 ( 1.0 0000.2) © 2011.4 Binary Division The binary division is the same as the decimal numbers except it is simpler in the case of binary number.1.3 Binary Multiplication The multiplication of binary numbers is carried out in the similar manner as the multiplication of decimal numbers.12 10102 100 0010 0000 0010.4. we have x 1011012 1012 1011012 000000 2 101101 2 111000012 multiplicand multiplier Partial Products Product 4510 x 510 22510 1. Example: Consider the division of 9 by 3.4. we encounter negative values in many different forms.0 0010. we have 112 00112 10012 011 0011 0011 0000 =310 Similarly.4. NUS .4.10.01 . These are just different forms of negative value representation.510 1. over draft in your bank account.12 Exercise: Find the sum of 101. = 3.. The following examples illustrate how binary division is carried out.5 Representing Signed Numbers In our daily life. the division of 10 by 4 yields 1002 0010. In general. negative value can be represented in four forms as follows and is used by the computer in the binary context. Example: Consider the multiplication of two numbers 4510 and 510.0 =2. ME. Signed magnitude representation By pre-pending a sign indicator in the number N sm N Excess (Offset) representation By adding a bias to the number ( 1. 4.6 +0.2 Negative number representation for binary number.4 . 0. for a 2 digit decimal number.3. Diminished Radix Complement Representation The diminished radix complement in the decimal system is called the nines' complement. it uses a pre-specified number B as a biasing value.5) Example: 2 The 10’s complement of a 2-digit decimal number 75 is 10 – 75 = 25.+} tells the sign of the value and the number tells the magnitude of the value.6) Example: The 9’s complement of a 2-digit number 75 is 102 – 1 .5 for the number in the range of 0 to 1. N xs N B Example: A bias of 0. -564. etc Excess (Offset) Representation Excess representation is also called biased representation. It is represented by a sign symbol in front of the numeric number. A value is represented by the unsigned number which is B greater than the intended value.4. N sm N Example: + 456.1 Negative number representation for decimal number system Signed-Magnitude Representation This is by far. its diminished radix complement is drc N 10 10 2 1 N ( 1.4. and −B is represented by 0.4 .4. NUS Page: 23 .4.1. ( 1.5. ME. Thus 0 is represented by B. Signed-Magnitude Representation © 2011. its radix complement is rc N 10 10 2 N ( 1.5. the most common way of signed representation that human has used.4. 1. 0. for a 2 digit decimal number. The sign symbol {-. Say. Say.2 -0.3) N drc r n 1 N Note: radix complement = diminished radix complement + 1. 56.3 . etc Radix Complement Representation It is called the ten's complement in the decimal system.75 = 24.Number System and Codes Radix complement representation By taking radix complement of an n-digit number is defined as N rc r n N Diminished radix complement representation By taking diminished radix complement of an n-digit number is defined as ( 1.4) 1. +} tells the sign of the value and the number tells the magnitude of the value. The magnitude of the number is represented 7-bit binary number (b6-b0). Diminished Radix Complement Representation In the binary context. one way is to use the MSB of the number as a sign bit. For an n-bit number. Example: For 8-bit binary number.10410 Negative number Magnitude = 104 Sign bit (+) However.4. The Figure below illustrates how the +10410 and –10410 are represented by an 8-bit signed magnitude representation. it is called 1’s complement form. b7 0 Sign bit (+) b6 1 b5 1 b4 0 b3 1 b2 0 b1 0 b0 0 = + 10410 Positive number Magnitude = 104 b7 1 b6 1 b5 1 b4 0 b3 1 b2 0 b1 0 b0 0 = . the bias value B is usually chosen to be around the middle of the range. for an n-bit binary number. such notation requires very complicated logic and not commonly used in computer. we choose B = 2n-1 – 1. the common convention is that a “0” in the sign bit represents a positive number and a “1” in the sign bit represents a negative number. Bit-7 is used as the sign bit to indicate the sign of the number.8) The excess representation will have a range of -(2 n-1 . Hence. the diminished radix complement is defined as 1 N 2 2n 1 N 2 . NUS . ME. Excess representation will have the number N xs N 2 n1 1 ( 1. it is represented by a sign symbol in front of the numeric number. It will have the range of -127~128. N sm N ( 1. The sign symbol {-. We call it an excess (2n-1 – 1) representation. In general.7) For signed-magnitude representation of binary number.ME3241/ME3241E Microprocessor and Applications Similarly. We call this Excess-127 representation.9) Page: 24 © 2011.4. Noting that this notation will has a case for “negative zero” when we have the value of 1000 0000! Excess (Offset) Representation In the binary context. ( 1.4.1) ~ (2 n-1). we have B = 2 – 1 = 127 and the number will have the representation of 7 N xs N 127 . Say. 10) N 22 2 n N 2 This is sometime known as the arithmetic complement.4. say.4.10) that N 22 2 n N 2 1 2n 1 N 2 1 N 2 1 ( 1. 10012 will be 1 N 2 2 4 1 10012 11112 10012 0110 2 Hence. This implies that the number NA represents both the value of NA and the 2’complement of NB. by definition.9) and (1. the 2’s complement can be computed by first computing its 1’s complement and followed by adding a 1 to the result as shown in the example below. NB is the 2’complement of NA and vice versa. To avoid the duplicated representation.1. That is.1 2’Complement of 3-bit binary number Decimal 0 1 © 2011.1 illustrates the case of a 3-bits representation. there exist another number N B 2 N A also in the range of 0~2n-1 (Except for the cases of NA=0 or NA=2n-1).Number System and Codes The 1’s complement is also known as the logical complement.4. Noting that. the digital implementation of 1’s complement will be a simple NOT operation on every bits of the number as shown in Figure 1. the 3 bit-binary with 2’s complement signed representation has the range of -4~3.1 Digital One’s Complement Implementation Radix Complement Representation for binary number In the binary context.4. This is because.4.4. For an n-bit binary number NA in the range of 0~2n-1. it is also called 2’s complement form. the value 2n – 1 will all the bits of the binary number equal to ones. ME. Example: For a 4-bit number N2 = 01102 0110 number 1001 1’s complement 1001 1 1010 2’s complement + The 2’s complement has the problem of double representation. the shaded cells are not used in the representation.11) Hence. n Table 1. Example: The 1’s complement of a 4-bit binary number. NUS Binary 000 001 2’s Complement 000 (-0) 111 (-1) Page: 25 .4. Table 1.4. complement is defined as the radix ( 1. Figure 1. For an n-bit number. Noting from (1. The operation of 2n-1 – N2 will results in inverting every bits of the binary number N2. ME3241/ME3241E Microprocessor and Applications 2 010 3 011 4 100 5 101 6 110 7 111 110 (-2) 101 (-3) 100 (-4) 011 (-5) 010 (-6) 001 (-7) Table 1.4.2 Shows the various sign representation for a 4-bit binary number. Sign magnitude an 1’s complement notation have the negative zero presentation which is meaningless in practice. Also, without the explicit setting of sign bit like the sign magnitude notation, all representation has the most significant bit reflecting the sign of the number. All representations has “0” indicating a positive number and “1” indicating a negative number except the Except the Excess-7 with the indication reversed. Table 1.4.2 Comparison between various signed representation Decimal +15 +14 +13 +12 +11 +10 +9 +8 +7 +6 +5 +4 +3 +2 +1 +0 0 -0 -1 -2 -3 -4 -5 -6 -7 -8 Unsigned 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 1000 1001 1010 1011 1100 1101 1110 1111 Sign Magnitude Excess-7 1’s Complement 2’s Complement 0111 0110 0101 0100 0011 0010 0001 0000 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 0111 0110 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 1111 1110 1101 1100 1011 1010 1001 1000 1.4.5.3 Binary Arithmetic with 2’s Complement. Consider the subtraction of an n-bit binary number NB from another n-bit binary number NA, we have N A N B N A 2n N B 2n NA N 2 2 B n where N B 2 arranged as 2 n N B denotes the 2’s complement of NB. The above expression can be re2 N A N B N A N B 2n . 2 ( 1.4.12) Noting that 2n is outside the n-bit binary range of 0~2n-1. Hence, the performance of N A N B will result in subtracting NB from NA with the value 2n store in the carry-over bit which will not be reflected in the sum register. Example: Subtracting 410 from 1210 in an 8-bit operation will has the following: Page: 26 © 2011, ME, NUS Number System and Codes 1210 = 0000 11002 410 = 0000 01002 2’s complement of 410 = 1111 11002 We have 1210 - 410 0000 11002 1111 11002 1 0000 10002 + This carry is disregarded. 1.5 Numeric Notation Used in Computers It is known that the computer uses binary arithmetic. That is, numbers are stored in its binary form. Depending on the kind of problem we are solving, we may require values of different range. In computer systems, numbers can be stored in the following notations Integer Notation Floating point notation 1.5.1 Integer Notation In computer, integer variable refers to integer representation usually in forms of multiple byte(s) of integer size. It has two forms of representation, i.e., unsigned integer or signed integer. Unsigned Integer This is the weighted position representation for binary number. For an n-bit binary representation will have the range of 0~2n-1. The size of the integer is usually chosen with n equals to multiple of 4. For examples, 4 (nibble), 8 (byte), 16 (word), etc.. The figure below shows an 8-bit unsigned integer representation with a range from 0 to 255. b7 0 b6 1 b5 0 b4 1 b3 0 b2 1 b1 0 b0 1 =8510 8-bit unsigned integer Singed Integer In computer, signed integer uses the 2’s complement representation. Say, for 8-bit signed integer as shown below, it has the range from -128 to 127. As illustrate in earlier section, the most significant bit (b7) will have the properties of a sign bit due to 2’s complement notation used. The figure below shows an 8-bit signed integer representation with a range from -128 to 127. b7 1 Sign bit b6 0 b5 1 b4 0 number b3 1 b2 0 b1 1 b0 1 =-8510 1.5.2 Floating Point Notation1 A floating-point number Nf in radix r has the general form N f F r E 1 ( 1.5.1) Dorf, R. C. (1993). The Electrical Engineering Handbook. CRC Press. Page: 27 © 2011, ME, NUS ME3241/ME3241E Microprocessor and Applications where 0 F 1 is the fraction (or mantissa) and E is the exponent. me = .9109 x 10-30 Kg = .09109 x 10-29 Kg = .009109 x 10-28 Kg For example, electron mass me = 9.109 x 10-31 Kg can be represented as follows. All these adhere to the form as described by (1.5.1) are correct floating point representation. In order to be more consistent, a further constrain has been imposed on F such that the most significant digit must be a non-zero digit except in the case of F=0. That is, the standard representation is me = .9109 x 10-30 Kg and is called the normalised floating point representation. In the computer, binary system is used, an n-bit normalised floating point representation is defined as N f 1 F2 2 E2 s where s 0,1 is the sign bit. 0.12 F2 1 is the mantissa which has the value of nm 2 F2 0.12 bi 2 i 2 nm i 0 nm 0.12 F2,nm 2 where nm is the number of significant binary places and F2,nm is the nm - 1 bit mantissa value stored in the computer. Noting that, for an m binary places fractional number, only the nm -1 least significant digits are stored. This is because the condition of 0.12 F2 1 implies that the most significant digit is always a one and is there not stored. E2 is the exponent of the floating point representation which needed to be a signed number. That is E2>>0 for large value representation and E2<<0 for small value representation. For the convenience of floating point addition and subtraction implementation, E2 is stored in the computer as an ne-bit signed number in excess representation with the bias value of the ne-bit signed number, Bne 2 ne 1 1 . That is, E 2,ne E 2 Bne will have the range of 1~ 2 2 ne 1 2 ~ 2 ne 1 1 . ne 2 which corresponds to the exponent E2 with the range of In computer the floating number are stored by packing s, E2 ,ne , F2 ,nm into a n n e nm bits memory. Table 1.5.1 shows how nm and ne are distributed for various precisions by IEEE standard for floating point representation. Table 1.5.1 IEEE implementations of floating point number Precision Single Double Quadruple N 32 64 128 nm 23+1 52+1 112+1 ne 8 11 15 E2(Min) -126 -1022 -16382 E2(Max) 127 1023 16383 Page: 28 © 2011, ME, NUS Whereas the case of used to represent the infinity ().111111 2127 2127 1.7812510 is stored in the 32-bit normalised floating point number as follows: 45.nm = 011 0111 0010 0000 0000 0000 The floating point representation is the packing of s.ne = 610 +12710 = 100001012 F2 = 0.70141 10 38 . F2 defines the significant of the number and E2 tells the order of the number.7812510 = 101101. The mantissa is represented by a 24-bit fractional binary representation with F2. E 2. NUS Page: 29 .ne ( E2 ) 0 (-127) 1~254 (-126~127) 255 (128) F2. To address this problem. It can represent a range of 0. The most significant bit. E 2. ne 2 .5.110012 Shifting the binary places yields 101101. s.nm stored in b0 to b22. F2. It is stored in b23-b30. The values 0 and 2 ne 1 (0 and 255 in this case) have been reserved for special use.1 shows the IEEE standard defined for a normalised 32-bit floating representation.nm 0 is In the case of F2 . we have s=0 E2 = 6 E 2.ne 2 ne 1 255 and F2 .ne .5. only uses the range of 1~ 2 used to represent the exact zero. is used as the sign bit. E 2.Number System and Codes 31 30 thru 23 Exponent 22 through 0 Mantissa Assumed position of radix point.87747 10 .5 2 5.nm 0 .nm 0 Subnormal numbers 0 Normal floating point number Nan Example1: The number 45.ne . The smallest normalised representation it can represents is when E2 = -126 and F2 = 0. It has a range of -126~127. b31.101101110012 F2. ME.1 32-bit normalised floating point representation Figure 1.ne 2 ne 1 255 indicates an invalid floating point representation or NaN (Not a Number). E 2.ne F2. This will gives a value of 126 39 0 .101101110012 x 26 From the above.12. This normalised representation has a problem that the exact zero can not be represented since the most significant binary place of F2 is always a one. with 0. we note that the ne-bit excess form exponent.110012 = 0.nm 0 has been E2. In this representation. The exponent uses an 8-bit Excess-127 representation. s defines the sign of the number. The case of E 2. These various cases are summarised in the Table below.nm as follows: Floating point number = 0 10000101 01101110010000000000000 © 2011.ne 0 indicates a subnormal representation (or floating point underflow situation) and E2.nm =0 F2.12 hidden Sign Bit Figure 1. 87510 x 2-2 = -0.12710 = -210 The mantissa with the implied 0.ME3241/ME3241E Microprocessor and Applications Example2: Determine the decimal value of the normalised 32-bit floating point representation 1 01111101 11000000000000000000000. the sign bit s = 1. From the above. The exponent in excess-127 notation is E 2.21875 s ___________________________ Page: 30 © 2011. ME.5 removed is F2.5 + 2-24 x 629145610 = 0.87510 Hence the floating point representation has the decimal value of N f 1 F2 2 E2 = (-1)1 x 0. NUS .ne = 011111012 = 12510 E2 = 12510 .nm = 110000000000000000000002 = 629145610 F2 = 0. Involution Laws Idempotent Laws Bound laws Absorption laws 0 and 1 laws DeMogan’s laws x x .2. such that for any x. etc. In digital logic circuits. The main purpose of this logical expression is to describe the relationship between a logical circuit’s output (decision) and its input (circumstances). NUS Page: 31 . 2. 5 v represents a true case and 0 v represent a false case.z Identify for (1) x1 = x xx 0 x x 1 2. 4. it is lightly that it is a digital circuit. it is lightly that the circuit is an analogue circuit. . the signs of a device contains digital circuitry can be deduce by observing the any existence of alphanumeric display. For example. the two states are TRUE and FALSE. 1 0 x y x y . x B x 1 1 . In practical context. Such expression is commonly referred as Boolean expression or Boolean algebra. x B x x y x .+.(x + z) Identify for + (0) x+0=x For the Boolean algebra. If the transistor is operating in the linear region.x x.y = y. the OR operation (Boolean sum) operation +. x B 0 1 . 3.y + x.z) = (x + y). “-”.(y. In Boolean context. Whereas. the AND (Boolean product) operation .0. further Boolean identities can be derived as follows.2 Boolean algebra In digital systems. A brief guideline to differentiate between analogue and digital is look at the transistor used in circuit. if the transistor operator in saturated region.2 Boolean Identities With the axioms above. x 0 0 . The concept of logical decision has been formalized by the mathematician. x x y x . ME. and the NOT (complement) operation “ ” defined on the set. the following Axioms hold: 1. a door is either open or closed. For example. Commutative: Associative: Distributive: Identity: Complement: x. George Boole (1854). 2. Binary quantities can be represented by any device that has only two operating states. the information being processed is usually presented in binary form. These are summarized as follows: 2. x B ©2011.1 Definition A Boolean Algebra is an algebra ( B 0. Many real life examples can be expressed in these binary states.z x.Chapter 2 DIGITAL ELECTRONICS 2.1 .1 Introduction Engineers generally classify electronic circuits as being either analogue or digital in nature.1) consisting of a set B together with three operations. in TTL logic.(y + z) = x. memory and programmability. x+y=y+x (x + y) + z = x + (y + z) x + (y.y). x y B (AND operation). a creature is either alive or dead. The proofs of these theorems are left to the reader as an exercise. x y x y . 5. x B x x x .z) = (x. which expressed logical decision in the form of symbols operated by various logical operators.2. x y B (OR operation) and x B (complement operation). y B . x x x . it often uses predefined voltages to represent these binary states. If a logic gate has a fan out of 10. otherwise. there are some basic important properties of digital circuits that is important for the user. IOH – High-Level Output Current The current that flows from an output in the logical 1 state under specified load condition. In the latter type. NUS .3. IIL – Low-Level Input Current The current that flows into an input when a specified low-level voltage is applied to that input. VOL (max) – Low-Level Output Voltage The maximum voltage that is generated at a logic circuit output in the LOW or logical 0 state. 2. ME. For TTL. then it can drive 10 standard inputs. Any voltage below this level will not be guaranteed as a HIGH by the logic circuit.3 Integrated Circuit Logic 2.2 Fan-out The fan out or sometime referred as loading factor is defined as the maximum number of standard logic inputs that an output can drive reliably. IIH – High-Level Input Current The current that flows into an input when a specified high-level voltage is applied to that input.3.1 Digital IC Terminology The IC technology has advanced rapidly with more and more gates packed within a single chip so that the overall size of all digital system is reduced. Typical output voltage will be higher than VOH.3 Transition Times and Propagation Delays While some digital circuits respond to logic levels (level triggered) at their input. These advancements have made digital circuit very easy to implement with user only focus on the functional aspect of the IC modules.3. the output voltage level can not be guaranteed. others respond to a rapid change in voltage(edge triggered). If this number is exceed. VIL (max) – Low-Level Input Voltage The maximum input voltage level required for a logical 0 to be read.3. the circuit may not respond properly. However. Some terms are defined and discussed below: 2. and are both dependent on the output loading. it is essential that input signals have sufficiently fast level transitions. Typical value will be lower than VOL. Page: 32 ©2011.Chapter 2 DIGITAL ELECTRONICS 2. it is usually negative indicating that the current flows out of the input (current sourcing).1 Current and Voltage Parameters IOH + VOH - IIH + VIH - +5V IOL + VOL - IIL + VIL - VIH (min) – High-Level Input Voltage The minimum input voltage level required for a logical 1 to be read. VOH (min) – High-Level Output Voltage The minimum output voltage that is generated at a logic circuit output in the HIGH or logical 1 state.1. 2.1. For this reason.1. Any voltage above this level will not be accepted as a LOW by the logic circuit. IOL – Low-Level Output Current The current that flows from an output in the logical 0 state under specified load condition. the RISE TIME (TR) and the FALL TIME (TF) of a circuit output is often specified. These values are not always equal. 1. The power requirements of an IC are given in the manufacturer’s specifications. When this is the case.e. The two propagation delay times are defined as: tPLH: tPHL: delay time in going from a logical 0 to a logical 1.4 Power Requirements +VCC 1 1 1 1 1 1 1 1 1 ICCL 0 1 1 0 1 1 0 1 1 +VCC ICCH 0 1 0 1 0 1 ICCL ICCH Every IC chip needs electrical power to operate. it is indirectly specified in terms of the current drain (ICC) from the power supply.ME3241/ME3241E Microprocessor and Applications A logical signal always experiences a delay in traveling through a circuit. HIGH to LOW) 1 Input 0 1 Output 0 tPHL tPLH 50% 50% Propagation times are used as a measure of the speed of response of logic circuits. an average current drain can be expressed as ICC(avg) = or PD = ICC(avg) VCC 2. (i. noise is any unwanted signal appearing at the input gate.e. the data may be switched spontaneously creating an incorrect output resulting in system failure. The power dissipation can then be determined by multiplying ICC by the power supply voltage (VCC). PD = ICC VCC For some IC’s the supply current is different for the two logic states. ICCH is the supply current when all of the outputs are HIGH. The amount of power supplied to and consumed by an IC is very important because many circuits are made up of very large numbers of IC’s and thus the power requirements could become astronomical.3. I CCH I CCL 2 ©2011.5 Noise Immunity In logic systems. tPLH and tPLH are not the same value and both will vary depending on capacitive loading conditions. In general. two values for ICC are specified. ICCL is the supply current when all of the outputs are LOW. But.3. Typical values are of the order of 10 to 20 nanoseconds (ns). (i.1. ME. NUS Page: 33 . The NOISE MARGIN specifies the allowable magnitude of input noise. more commonly. LOW to HIGH) delay time in going from a logical 1 to a logical 0. Sometimes it is given as average power dissipation (PD). Therefore. it is highly desirable to have IC’s that have extremely low power requirements. 2. Thus. If this input is exceeded. ME. The HIGH STATE NOISE MARGIN is defined as: VNH = VOH(min) .4 – 2.3. fluorescent lights. etc.4 V = VOL (max) .8 – 0.4 VOL(Max) LOGIC “0” Output Voltage Range Input Voltage Range VIL(Max) VNL LOGIC “0” Indeterminate range 0. 2.0 0.VIH (min) = 2.VIH(min) The LOW STATE NOISE MARGIN is defined as: VNL = VOL(max) .1.6 Current Sourcing and Current Sinking Logic Logic families can be categorized according to how current flows from the output of on logic circuit to another.4 VNL 2.0 VIH(Min) Indeterminate range 0.2 Max (V) 0.4 LOGIC “1” VOH(Min) VNH 2. NUS . Avoid running cables in “noisy” environments. keep all leads as short as possible. The figures below illustrate the difference between the two types.4 2.8 LOGIC “1” Example: (some typical TTL characteristics) Parameter VOH VOL VIH VIL VNH = VOH (min) .4 0. and use shielded cable.VIL(max) Some Typical noise margins are illustrated in the figure below.8 Typical (V) 3. Low Low VOH IIH Current Sourcing Supplies current to load gate in HIGH state +VCC Current Sinking High High VOL IIL receives current from load gate in LOW state Page: 34 ©2011.4 V Min (V) 2. Ensure good connections and use well regulated poser supplies.4 = 0.VIL (max) = 0.0 = 0.Chapter 2 DIGITAL ELECTRONICS Input noise can originate from many sources such as arc or spot welding equipment. The importance of this output arrangement will be discussed shortly. making a logic HIGH.2 TTL Logic 2. Therefore the current from the +5v supply through resistor R1 will flow through diode D4 into the base of transistor Q2.1 Operation of TTL Logic Devices (Totem-pole Output Circuits) Since the transistor-transistor logic (TTL) family is widely used.3. Diode D1 is the insurance that the output will be very LOW since the emitter of Q4 is shorted to the ground. the output of the gate is LOW. the two diodes D2 and D3 which represent the two baseemitter diodes will not conduct. Because of the way in which it is used in the circuit it can be simplified. making a logic LOW. This equivalent is shown in the shaded box to the right of the figure below. Diodes D2 and D3 represent the two E-B junctions of Q1. the job of Q4 is to connect the output to ground. Because NAND gate can be used to generate many types of logic functions. if both input A and B are HIGH. The job of Q3 is to connect Vcc to the output. for analysis purposes. Whereas. NUS Page: 35 . ME. The emitter current from Q2 will produce a base current into Q4 which turns Q4 ON while at the same time the voltage at the collector of Q2 is kept low enough to ensure that no base current flows into the base of Q3.3. Thus. Therefore. and D4 is the collector-base (C-B) junctions. Noting that the output of the circuit consist of two transistors Q3 and Q4 stacked on top of one another and resemble a “Totem pole”. ensures that Q3 remains turned OFF.2. an understanding of the operation of this simple gate provides a good insight into the operation of most TTL devices. we will examine the operation of a typical TTL NAND gate. Case I: Output Low-State When the inputs A and B are both HIGH. ©2011. This base current into Q2 will turn Q2 ON. The input to the device is a multiple-emitter transistor (Q1). thus the terminology of a totem pole arrangement for this kind of configuration is used. The figure below shows the circuit diagram for a basic two input TTL NAND gate. by using its diode equivalent.ME3241/ME3241E Microprocessor and Applications 2. The circuit would in fact operate if Q3 and D1 are eliminated from the circuit and the bottom of the resistor is connected directly to the collector of Q4.3. This will results in no sufficient base current into Q4 and implies Q4 will also be turned OFF. it produces a produces a high voltage via the pull up resistor R4 and results in turning the Diode D1 ON. It is for this reason that in many IC circuits you will see numerous small capacitors connected from Vcc to ground. under this circumstance. However. Current will flow from Vcc through R1 and diode D3 to ground. This will clamp the voltage at point X as shown below too low to generate a base current into Q2 to turn it ON. Hence. Q4 would conduct a fairly high current in its saturation state. This action is called active pull-up and provides very fast rise times at TTL outputs. One disadvantage of totem-pole arrangement occurs during a LOW to HIGH transition. 2. Using the totem-pole configuration with Q3 present. its associated low output impedance (typically 10) results in a short rise time constant for charging up any capacitive load on the output.2. Q2 is OFF. 3.2 TTL loading and Fan-out R4 R4 Q3 OFF IOL D1 IIL IIL Q3 ON IOH D1 IIH IIH Q4 ON Q4 OFF Page: 36 ©2011. the output will has the HIGH output voltage. Q4 turns OFF more slowly than Q3 turns ON. Another advantage of totem-pole arrangement occurs in the HIGH output state. Since Q2 is OFF. the voltage at the collector of Q2 is now sufficiently high to generate base current into Q3 to turn Q3 ON. Such connection may cause excessive current draw through the transistor Q4 (ON) of the gate in the LOW output state while other output are in the HIGH state. NUS . Another important note to take is never tie the outputs of conventional TTL totem-pole output circuitry together. There are a few points regarding Totem pole output circuit. As a result. (approx. Since Q3 is ON. This is termed power supply decoupling which prevents a voltage spike from occurring on the Vcc line.Chapter 2 DIGITAL ELECTRONICS Case II: Output HIGH case Consider the case when A is HIGH and B is LOW as shown below. there is a period of a few nanoseconds when both transistors are conducting and resulting in a relatively large current surge (30-40mA). Since Q3 is acting as an emitter-follower. ME.6v). Further analysis will shows that the above circuit behave like a NAND gate. there will be no current through R4 in the LOW output state. This will reduce the power dissipation of the circuit. As a result. 6 mA = 16 mA IOH(max) = 10 x 40 A = 400 A Example2: For the 7400 NAND gate in previous slide we have. IOL(max) = 16 mA. this implies that: IOL(max) = 10 x 1. the fan-out is 10 Unit Load: Since all IC’s do not have the same current characteristics or specifications. IOL(max) Fan-out(Low) = I (max) IL Example: How many 7400 NAND gate inputs can be driven by a 7400 NAND output? Solution: From the data sheet. where a unit load is defined as follows: 1 unit load (UL) = 40 A in the HIGH state 1. IIL(max) = 1.6 mA = 10 UL drive capability (High) = ©2011. the low state fan-out is defined as. and the actual fan-out depends on the combination of driving and driven IC’s. then the high state fan-out or the number of inputs the output can drive is simply the integer value of X/Y. Some manufacturers specify the device input and output currents in terms of a unit load (UL).6 mA IOH(max) = 400 A. IOH(max) Fan-out (High) = I (max) IH Similarly. As a result.e. if a given IC is specified as having a fan-out of 10 UL in both states.ME3241/ME3241E Microprocessor and Applications If a high state output of a driving chip can source X amount of current and the input of the driven chip can sink Y amount of current. IIL(max) = 1. we can see that IOL(max) = 16 mA. IOH(max) = 400 A. It would be impossible to specify an absolute fan-out value. Example1: Say.6 mA = 10 IL IOH(max) 400 A Fan-out(High) = I (max) = = 10 40 A IH i. standardized input and output loading factors have been established which allow the input and output currents been expressed in terms of standard unit loads. ME. NUS IOH(max) 40 A = 400 A = 10 UL 40 A Page: 37 . I (max) 16 mA OL Fan-out(Low) = I (max) = 1.6 mA = 1. IIH(max) = 40 A Therefore.e. i.6 mA.6 mA in the LOW state These unit load factors are used to express the output drive capability and input loading requirement for TTL circuits. IIH(max) = 40 A The output drive capability is IOL(max) 16 mA drive capability(Low) = 1. The following examples show how these concepts are used. From the unit load calculated in previous examples.5 UL in LOW state. the fan-out in both LOW and HIGH states is (10 UL/ 1 UL) = 10. IIL(max) = 2 mA. the fan-out of 7400 to drive 74S00 in both HIGH and LOW states will be 10/1. it is said to be floating. Any unconnected input will be treated as a HIGH.25 = 20 and the fan-out in the LOW state will be 12. but this unconnected input also serve as an antenna which can pick up stray signals causing the gate to operate improperly. if the output of 7400 is connected to identical 7400 IC. in both HIGH and LOW states. The input requirement for this IC can be expressed as I (max) 1.6 mA = 1 UL Loading (High) = IIH(max) 40 A = 40 A = 1 UL 40 A Therefore.6 mA = 12. It is not advisable to let the input floating. IOH(max) = 1000 A. That is.25 = 10.3.6 mA = 1. in both HIGH and LOW states. Example4: Consider now the output of 7400 driving the input of 74S00.6 mA = 1. IIH(max) = 50 A The output drive capability is IOL(max) 20 mA drive capability(Low) = 1. When an input is left unconnected. Home work: How about 74S00 driving 7400? 2. The input requirement for this IC can be expressed as IIL(max) 2 mA Loading(Low) = 1.6 mA = 1.2. the fan-out in the HIGH state will be 25/1.5/1.25 = 8. the input has a loading factor of 1 UL. Some common method to unconnected inputs is by Page: 38 ©2011. Example3: Consider now the 74S00 IC.25 in both HIGH and LOW states.3 Unused and unconnected inputs Sometimes it occurs that not all of the inputs on logic gate are required to perform the required logic function. the output can drive 10 UL.5 UL drive capability (High) = IOH(max) 40 A = 1000 A = 25 UL 40 A Therefore. if the output of 74S00 is connected to identical 74S00 IC.Chapter 2 DIGITAL ELECTRONICS Therefore. The specs are as follows: IOL(max) = 20 mA.6 mA = 1.25 UL 40 A Therefore. ME.25 UL Loading (High) = IIH(max) 40 A = 50 A = 1. NUS . 74S00 has a loading factor of 1. Although it behave like a HIGH. That is.6 mA IL Loading(Low) = 1. 74S00 can drive 25 UL in HIGH state and 12. for all intensive purposes. NOR 7402 Y XOR Y A B 0 0 0 1 Y A B Y A B Y A B Y A B 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 Three-State Outputs C C A Y A Y A Y Off . Input Output Enable 2. if C is high . these device have three output states. The logic symbol for a tri-state device is shown in the figure below. if C is high 74125 ©2011. ME. it can be considered that its output is disconnected from the circuit. if C is low 74126 A Y Off . A tri-sate device has one additional input which is called a control input. As the name implies. it has an additional HIGH IMPEDANCE output state.3. If the control input is LOW. Thus the control input can be thought as a switch which either permits the device to as a normal IC or disconnects its output from the circuit. the output gate is disabled and no longer depends on the inputs but acts as a high impedance since both transistor Q3 and Q4 are both cut off and the output is almost an open circuit. When the output of the device is in this high impedance state.4 Tri-state logic devices Tri-state digital integrated circuit devices are extremely important particularly with respect to their use in computer circuits.4 Logic Gates Operators TTL # Symbols Truth Table A B 0 0 0 1 1 0 1 1 AND 7408 NAND 7401 OR 7432 A B The table below shows the logic symbol and their truth table for the common TTL gates.ME3241/ME3241E Microprocessor and Applications Use a pull-up resistor Connect to ground Connect the input together A B X=A+B or 2. the gate operates in exactly the same manner as a conventional TTL gate and the output will have the usual HIGH or LOW depending on the gates input(s) present. In addition to having the normal HIGH or LOW output state. if C is low . The control input is HIGH.2. NUS Page: 39 . C. The logic diagrams below illustrate the NANDequivalence of various logic gates.4. are as follows S A B A B A B C A B 2. Hence.2 Full Adder Beside the input A and B. Single Gate Inverter AND NAND Equivalence OR NOR Exclusive OR Exclusive NOR Gate 2.2. ME. S.1 Some Properties of NAND Gate The NAND gate is the most versatile digital logic device.4.1 Half Adder We know from previous chapter that binary addition satisfy the following condition: A 0 0 1 1 Truth Table B S 0 0 1 1 0 1 1 0 C 0 0 0 1 A B C S Half Adder From the truth table above we can derive that the sum. NUS .2 Some combinatorial logic examples 2.4. All of the Boolean logic gates we have discussed can be constructed using only NAND gates. addition usually involves the carry forward from the lesser significant position of the digit.4. and the carry. the truth table of a full adder is as follows: Cn-1 0 0 0 0 1 1 1 1 Page: 40 A 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 0 S 0 1 1 0 1 0 0 1 Cn 0 0 0 1 0 1 1 1 ©2011.Chapter 2 DIGITAL ELECTRONICS 2.2. the output of each FA is therefore not stable until the carry-in from the previous stage is calculated. the full adder (FA) can be constructed from two half adder as shown below. NUS Page: 41 . However. digital systems are made up of combinational circuits and memory elements as shown in the diagram below. An important memory element is the flip-flop (FF). Circuits made out of these devices are usually called combinational logic. which is made up of an assembly of logic gates. The most basic FF circuit can be constructed from two NAND gates or two NOR gates.ME3241/ME3241E Microprocessor and Applications From the truth table. An commercial example of 4-bit adder is 74283. The NAND ©2011. A3 A2 A1 A0 B3 B2 B1 B0 A B S A S B A S B A S B Carry C FA3 C-1 C FA2 C-1 C FA1 C-1 C FA0 C-1 S3 S2 S1 S0 Note: The parallel adder above performs additions at a relatively high speed. Hence. Each output stabilize in the order from right to left as the carries ripple through the chain. ME. An Bn Cn A B Sn Half Adder Cn-1 Full Adder Half Adder C FA C-1 S A 4-bit adder can be constructed by cascading 4 FA’s as shown below. 2. The circuit consists of inputs from external signals and feedback from the outputs of the memory elements. A B Cn 1 A B Cn 1 A B Cn 1 B Cn 1 A B Cn 1 B Cn 1 A B Cn 1 = A B Cn 1 A B Cn 1 A B Cn 1 A B Cn 1 = = Cn A B Cn 1 A B A B Cn 1 A B A B Therefore. we have S = A B Cn 1 A B Cn 1 A B Cn 1 A B Cn 1 = = = Also.5 Flip-flops and Latches The logic gates discussed in earlier section are what we called as memory-less devices. its speed is limited by an effect called carry propagation or carry ripple. The carry bits have to propagate from one stage to the next. Some of the outputs are stored in the memory elements which outputs are feedback to the circuit. In general. This is sometime referred as latch or bi-stable multi-vibrator. ME. The table below shows the truth table of the flip-flop. Noting that both SET and CLEAR are not allowed to be pulled to LOW simultaneously! SET Q SET 1 0 1 CLEAR 1 1 0 0 Q No Change 1 0 Invalid! Q= Q =1 CLEAR Q 0 Example1: The waveform below shows how the output responses the pins SET and CLEAR . respectively. When both inputs SET and CLEAR are normally set at HIGH such that the output Q retains its pre-stored value.5. Bouncing +5V +5V 2 1 VOUT Switch come to rest in position 2 Switch to position 2 2 S C Q VOUT 1 +5V Switch to position 2 Switch back to position 1 Page: 42 ©2011. NUS . two NAND gates are cross-coupled so that the output of one NAND gate is connected to the input of the NAND gate and vice versa. The output can be “set” to HIGH or “clear” to LOW by pulling the SET or CLEAR pin to LOW. in which.Chapter 2 DIGITAL ELECTRONICS gate version is called a NAND gate latch whereas the NOR gate version is called NOR gate latch.1 NAND gate Latch: The figure below shows a NAND gate latch. Example2: An application of the SC latch is to use it to prevent phenomena called the contact bounce. Combinational outputs Memory outputs Combinational logic gates Memory elements External inputs 2. Similarly. Init i/p Control inputs Q Clk Q PGT activated flip-flop Init i/p Control inputs Q Clk Q NGT activated flip-flop 2.5. ME.5. the output changes its state by a signal called clock. Clk PGT NGT Time In synchronous systems. Synchronous systems: outputs state change determined by clock. we add two more NAND gate at the input as shown in the figure below. Asynchronous systems: outputs can change state at any time. one or more control inputs which have not have effect on Q until the flip-flop is “clocked”.5. In order to have some level of control when the inputs can controls the output Q. When the clock changes from “0” to “1”.3 Making of Clocked S-C Flip-Flop The NAND flip-flop in Section 2. it is called a Positive-going transition (PGT). when the clock changes from “1” to “0” it is called a Negative-going transition (NGT).1 does not have any enable/disable facilities.2 Clocked Flip-Flops: Digital systems can operate either asynchronously or synchronously. It is a square pulse train that is distributed to most part of the system such that the outputs change state only when the clock makes a transition (also called edges). 2 initialization input (to be discussed later) to momentarily change the state of Q. A typical clocked flip-flop consists of: clock input (CLK or CK or CP) two outputs usually termed as Q and Q where Q is also a complement of Q. The Synchronizing action of the clock is accomplished by clocked flip-flops that are designed to change states on one of the clock transition.ME3241/ME3241E Microprocessor and Applications 2. SET E SET Q CLEAR CLEAR Q *SET X 0 0 1 1 ©2011. NUS CLEAR X 0 1 0 1 E/ D 0 1 1 1 1 Q No Change No Change 0 1 Ambiguous Page: 43 . These asynchronous inputs can be used to set the flip-flop to the HIGH state or clear the flip-flop to the LOW state at any time regardless of the condition of the other inputs. we insert an edge detector before pin E as shown in the figure below. It is usually used to override the input to set or clear the flip-flop. NUS .Chapter 2 DIGITAL ELECTRONICS The input E acts like an enable/disable switch to control the inputs effect. From the truth table in Section 2. SET SET Edge detector Q Clk CLEAR Clk* CLEAR Q The figures below show the case for both PGT or NGT triggered edge detector. The Table above shows the behaviours of the modified flip-flop. ME. then the state of pins SET and CLEAR will depend on the value of pins SET and CLEAR. It behaves as if an inverter is appended to each of the input SET and CLEAR . On the other hand. Noting that when E is LOW. when E is HIGH.5. Q will remain unchanged.1. To acquire an edge-triggered flip-flop. Page: 44 ©2011. CLK CLK CLK* CLK CLK CLK* CLK CLK CLK* CLK CLK CLK* Positive-going transition Positive Edge Triggered SC Flip-Flop S C Q Q Negative-going transition S 0 1 0 1 C 0 0 1 1 Clk Q Q0 1 0 Ambiguous Asynchronous Inputs Most clocked flip-flops also have one or more asynchronous inputs which operate independently of the synchronous inputs and clock input. both SET and CLEAR pins will be HIGH. ME.4 Clocked J-K Flip-Flop J K Q Q J 0 1 0 1 K 0 0 1 1 Positive edge going Clk Q Q0(no change) 1 0 Q0 (toggles) J K Q Q J 0 1 0 1 K 0 0 1 1 Clk Q Q0(no change) 1 0 Q0 (toggles) Negative edge going 1 J 0 1 K 0 1 Clk 0 a 1 b c d e f Q 0 ©2011.5. NUS Page: 45 .ME3241/ME3241E Microprocessor and Applications Set Q S CLK C Q SC Flip-flop Clear SET 1 1 0 0 CLEAR 1 0 1 0 Q Clocked Mode 0 1 Not Allowed 2. Chapter 2 DIGITAL ELECTRONICS JK Flip-flop with Asynchronous Inputs Preset J K Q Q Clear Preset 1 0 1 0 Clear 1 1 0 0 Q Clocked mode 1 0 Not used Example: +5V J K PRE Q Q CLR 2. ME.5. NUS .5 Clocked D Flip-Flop D Q Q D 0 1 Clk Q 0 1 s D Clk S C Q Q D Clk J K Q Q Equivalent D Flip-flop by SC Flip-Flop Equivalent D Flip-flop by JK Flip-Flop Page: 46 ©2011. 7 Timing Consideration for Flip-flop Setup and Hold Times Synchronous control input Clock input ts Setup time tH Hold time Two timing requirements must be met if a clocked FF is to respond reliably to its control inputs when the active CLK transition occurs. the logic level present on the input will have no effect on the Q and Q outputs. the state on Q at that time will be latched there. when the enable input is made low again. ME. a high or a low on the D input will be passed to the Q output. (Usually specified in t S (min)). Setup time. Hold time. is the time interval immediately preceding the active transition of the CLK signal during which the synchronous input has to be maintained at the proper level. NUS Page: 47 . tW(L) The minimum time duration that the clock must remain HIGH before it goes LOW. t H . Usually referred to as fMAX Clock Pulse HIGH and LOW Times The minimum time duration that the clock must remain LOW before it goes HIGH.ME3241/ME3241E Microprocessor and Applications 2. is the time interval immediately following the active transition of the CLK signal during which the synchronous input has to be maintained at the proper level.6 D Latch (Transparent Latch) EN D X 0 1 Q Q0(no change) 0 1 D EN Q Q 0 1 1 The D Latch (74 373) A latch is a digital device that stores a 1 or a 0 on its output. if the enable input is high. there is a delay from the time the signal is applied to the time when the output makes its change. 2.5. tW(H) 1 Clock 0 tW (H) tW (L) ©2011. if the enable input EN is low. t S .5. The device functions as follows: (See the Truth Table above). Usually referred to as tPLH and tPHL Maximum Clocking Frequency The highest frequency that may be applied to the CLK input of a FF. Propagation Delay Whenever a signal is to change the state of a FF’s output. (Usually specified in t H (min)). 1 Registers A register is a device you use to store some information.5. a ONE or a ZERO. +5V Write pulse Input Write pulse S D R Q Clk Q Storage Input Storage Q Page: 48 However. Detecting an input Sequence Suppose that we want to generate a high output only if A goes high and then B goes high sometime later.Chapter 2 DIGITAL ELECTRONICS Asynchronous Active Pulse Width The minimum time duration that a PRESET or CLEAR input has to be kept in its active state in order to reliably set or clear the FF. 1 nibble 4 bits ©2011. PRE or CLR 1 0 tW (L) 2. ME.1 Some Flip-Flop Applications 1. a flip-flop. one flip-flop can only store two possible values. i. Data Storage and Transfer D A A Transfer D B B K K Transfer enable Q Q A goes HIGH after B K K Q Q Synchronous transfer Asynchronous transfer X1 X1 X1 D Y1 Y1 D Y1 Y1 D Y1 Y1 Transfer Parallel transfer 2. in its simplest form. We usually group a few flip-flop to form one set of storage e.7.g.e. NUS .6 Counters and Registers 2. A B J K Q Q X A A B B X X A goes HIGH before B 2.6. ME.1.ME3241/ME3241E Microprocessor and Applications - 1 byte 8 bits The most commonly used group is byte (8 flip-flops).6. NUS Page: 49 .1 Transferring of Registers content Parallel transfer of value in register A to Register B D A3 D A2 D A1 D A0 Register A A3 D B3 Write Pulse A2 D B2 A1 D B1 A0 D B0 Register B B3 B2 B1 B0 Serial Transfer of value from Register A to Register B(Shift Register) D A3 D A2 D A1 D A0 Register A Write Pulse D B3 D B2 D B1 D B0 Register B B3 B2 B1 B0 Asynchronous Shift Register Serial Input J SET Serial Output Q J SET Q J SET Q J SET Q K CLR Q K CLR Q K CLR Q K CLR Q Stepping Pulse Y Y Y Y X X X X Parallel Load I3 I2 I1 I0 ©2011. Input +5V S D Q Q R Write pulse Storage Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 R S D Q Q R S D Q Q R S D Q Q R S D Q Q R S D Q Q R S D Q Q R S D Q Q I7 I6 I5 I4 I3 I2 I1 I0 2. and is called a mod-16 counter. In general.2 Counter with mod-X < 2N Assume counter starts from 0. N-FFs connected up this way will have 2N states – a mod-2N counter. C. Succeeding FFs get their clock input from output of previous FF.2.6. In synchronous counters.Chapter 2 DIGITAL ELECTRONICS 2. Each FF A.2. Connect NAND gate output to the asynchronous CLR input of all FFs.6. circuit elements get the clock input simultaneously.2 Counters We will consider asynchronous as well as synchronous counters. circuit elements do not get the clock input simultaneously. ME. Counter counts in sequence from 0000 (0) – 1111 (15) Counter has 16 distinct count states. 2. Clock connected to first (LSB) FF only.6. and D successively halves the clock input frequency. NUS .1 Asynchronous (Ripple) Counters +5V D J K Clk A B C D +5V C J K B +5V J K A +5V J K FF outputs can only toggle. 2. In asynchronous counters. B. Find which FFs will be in HIGH state when count = X. Example: A Mod-6 Counter +5V C J B +5V J A +5V J Clk Clr K Clr K Clr K 1 A B C NAND 2 3 4 5 6 7 8 9 10 11 12 More examples D J C J B J A J D J C J B J A J Clr K Clr K Clr K Clr K Clr K Clr K Clr K Clr K Mod-14 Counter Mod-10 Counter Page: 50 ©2011. Feed those FF outputs to a NAND gate. only used for low freq.2. we increase the clock frequency to have Clock Period = 100 ns 1 Clk A B C Example: 100ns 50ns 2 3 4 5 100ns 150ns Note: There is no 100 in the counts!!! A 4-bit ripple counter is constructed using the 74LS112 J-K flip-flop. we use the worst case (i. To calculate the maximum allowable clock frequency. applications. +5V D D J K C C +5V J K B B +5V J K A A +5V J K 2.e.6.4 Problems in Ripple Counters. we have tPLH = 16 ns and tPLH = 24 ns. tpd = 24ns) 1 1 = 4 x 24ns = 10.2.OK Say.. The limitation is due to the propagation delays of the FFs in the chain add up: Clock input to FF1: t0 (clock transition time) Clock input to FF2: t0 + tpd Clock input to FF3: t0 + 2 tpd .. ME. Hence tclock n tpd or fmax 1 n tpd The following waveform illustrate propagation delay of a Mod-8 Ripple Counter 1 Clk A B C 1000ns 50ns 2 3 4 5 100ns 150ns Clock Period = 1 ms Propagation delay after NGT of the Clock Signal tpd (Max) = 150ns << 1 ms --. Clock input to FFn: t0 + (n-1) tpd This implies that the nth FF rather than changing state at t0 it changes state at tpd. Connect complements of FF outputs to clock inputs of succeeding FFs.3 Ripple Counter that counts down. Accumulation of Propagation Delay Ripple counters are easy to implement – but have one major drawback: Can’t operate beyond a limiting frequency.ME3241/ME3241E Microprocessor and Applications 2.6. NUS Page: 51 .4 MHz fmax n t pd ©2011. From the spec. So. Q1. These are connected together to the output of a 2-input NAND gate with inputs MR1 and MR2 – Need MR1 = MR2 = 1 to reset the counter to 0000.5 Q 1 J 1 Q 1 J 1 Q 1 J 1 Q CP0 1 K CD K CD K CD K CD CP1 MR1 MR2 74293 CP1 CP0 Q0 (LSB) Q1 Q2 Q3 (MSB) MR1 MR2 Q3 Q2 Q1 Q0 Consist of 4 JK flip-flops with output Q0. Q2 and Q3 (Q0 is LSB and Q3 is MSB) The clock inputs of Q0 and Q1 are externally accessible and labeled CP 0 and CP1 . These decoding glitches can be eliminated by a strobe signal. Depending on application. (Some flexibility here) Page: 52 ©2011. Q2 and Q3 are already connected as a 3-bit ripple counter. FF Q0 is not connected to anything internally. This method need not be used when the decoder drives a display – glitch is not visible. But must be used when decoder drives other circuitry. A B X0 A B X1 A B X2 A B X3 Strobe signal 1 0 1 0 #1 #2 #3 #4 Clk Strobe Decoder disabled tD Decoder enabled tD is chosen be greater than the total time it takes the counter to reach a stable count (depends on FF delays and number of FFs). CD.2. respectively. Again due to propagation delays. Each FF has an asynchronous CLEAR input. IC Asynchronous Counters (74x293) 1 J 2. NUS .Chapter 2 DIGITAL ELECTRONICS Decoding Glitches This is another problem encountered with ripple counters if the states have to be decoded.6. Example Clk J Clk K A A J K B B X0 X1 X2 X3 A B X0 X1 X2 X3 1 0 1 0 1 0 1 0 1 0 1 0 1 0 #1 #2 #3 #4 Temporay 00 state Temporay 10 state FF and decoding waveform for a mod-4 ripple Counter showing glitches at X0 and X2 outputs. may/may not be a relevant. Q1. ME. i. fmax < 70 ns = 14. and tpd (AND) = 20 ns. C toggles when AB = 1. Notice that all FFs are triggered by the same clock. NUS Page: 53 .3 MHz (irrespective of no. On the other hand for a 4-bit ripple counter. ripple counter. output does not change on the clock pulse When J=k=1. B toggles when A = 1.K=1). Technique used: When J=K=0.ME3241/ME3241E Microprocessor and Applications Example 1: Mod-16 Counter CP1 74293 MR1 MR2 Q3 Q2 Q1 Q0 CP0 Example 2: Mod-10 Counter CP1 74293 MR1 MR2 Q3 Q2 Q1 Q0 CP0 Example 3: Mod-50 Counter CP1 74293 MR1 MR2 CP0 MR1MR2 Not Used CP1 74293 Q3 Q2 Q1 Q0 CP0 Q3 Q2 Q1Q0 fin/50 fin/10 2. output toggles on the clock pulse. 1 tclock > 70 ns. The total delay involved in this sync.2. counter is tpd = tpd (FF) + tpd (AND) (total) = 50 + 20 = 70 ns. ME. What is the max operating frequency? t pd The propagation delay problem encountered with ripple counters can be overcome by using synchronous or parallel counters. A toggles at every NGT (J.6 Synchronous (Parallel Counters) D J K Input C J K B J K A J K Hence counter operates at higher frequency than corresp. The additional logic gates ensure that the FFs toggle at the right time. ©2011. Noting that all clock inputs are triggered simultaneously.e. of FFs). D toggles when ABC = 1. Example: If tpd (FF) = 50 ns.6. The diagram above shows a MOD-16 parallel counter with "A" as the LSB and "D" as the MSB. Hence. 7 Synchronous Down and Up Counters Count Up/ Down Q C Q J K Q B Q J K Q A Q J K Input 7 6 5 4 3 2 1 0 C 1 1 1 1 0 0 0 0 B 1 1 0 0 1 1 0 0 A 1 0 1 0 1 0 1 0 When Counting up A = 1 to toggle B A = B = 1 to toggle C When Counting down A = 0 to toggle B A = B = 0 to toggle C The Count-up and Count-down signal control the counting sequence.2. Sometime referred as loading the counter. 2.2. B . Count sequence is up if Count Up/ Down input = 1. J(B) = K(B) = A and J(C) = K(C) = A.6. J(A) = K(A) = 1.Chapter 2 DIGITAL ELECTRONICS 1 fmax < 4 x 50 ns = 5 MHz. J(A) = K(A) = 1. ME. J(B) = K(B) = A and J(C) = K(C) = A . NUS .B.6. Here. 2. P2 P1 P0 PL Q Pre J C Clr K Q Pre J B Clr K Q Pre J A Clr K Clock Page: 54 ©2011.8 Presettable Counters Many synchronous counters that are available as ICs are designed to be presettable Can be pre-set to any desired count asynchronously or synchronously. Count sequence is down if Count Up/ Down input = 0. Here. ME. reset Asyn.9 IC Presettable Counter (74x193) PL P3 P2 P1 P0 CPU CPD + 74193 TCU TCD MR H L L L L PL X L H H H CPU X X H H CPD X X H H Mode Asyn. preset No change Count up Count down Mod-16 up/down counter - MR Q3 Q2 Q1 Q0 Pin Description CP – Count-up clock input (active rising edge) U D CP – Count-down clock input (active rising edge) MR – Asynchronous master reset input (active HIGH) PL .ME3241/ME3241E Microprocessor and Applications 2.2.Asynchronous parallel load input (active LOW) P -P – Parallel data inputs 0 3 Q -Q – flip-flop outputs 0 3 TC TC U – Terminal count-up (carry) output (active LOW) D – Terminal count-down (borrow) output (active LOW) Example1: Up-counter Parallel data inputs = 1011 Initial flip-flops output = 0000 PL CPU 1 1 0 1 1 P3 P2 P1 P0 + - PL TCU TCD CPD 74193 MR Q3 Q2 Q 1 Q0 CPU PL MR Q0 Q1 Q2 Q3 TCU 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 ©2011. NUS Page: 55 .6. Draw the state transition diagram showing all possible states. Page: 56 ©2011. Choices of flip-flops Transition 00 01 10 11 JK Flip-flop J K 0 X 1 X X 1 X 0 D Flip-flop D 0 1 0 1 Design Steps 1.2. Design the logic circuits to generate the levels required at each flip-flop input.Chapter 2 DIGITAL ELECTRONICS Example2: Down-counter PL 1 0 1 1 1 P3 P2 P1 P0 CPU CPD + - PL TCU TCD 74193 MR Q3 Q 2 Q1 Q0 CPD 1 0 1 PL 0 1 Q0 0 1 Q1 0 1 Q2 0 1 Q3 0 1 TCD 0 t 0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 2. ME. Must make sure the logic level at every FF’s input pins stabilize to a correct level before each clock pulse. Use the state transition diagram to set up a table that list all PRESENT states and their NEXT states 4.10 Synchronous Counter Design A subset of Sequential Circuit Design Approach: Given the state diagram of a counter realize it using common FFs and combinational logic. Add the column to this table for each flip-flop input. Combinational Logic FFs External Input Clk All FFs are clocked at the same time. 3. 5. 2. NUS .6. Determine the desired number of bits and choice of FF used. Q1 . ©2011. D0 = Q2 .( Q1 . Q1 . Step 1: Since it is 3 bit counter. Q0 ) + Q2. Q1 . NUS Page: 57 .Q1.Q1. Q0 = Q2 . ME.Q0 + Q2 .( Q1 . Q0 + Q2. Q1 . Q0 = Q0 D1 = Q2 . Q1 .Q1.ME3241/ME3241E Microprocessor and Applications Example 1: Design a 3-bit counter that counts from 000 to 111 and back to 000.Q0 + Q1.(Q0 + Q0 ) + Q2. Q1 .Q0 + Q2. Q1 + Q2. Q0 = Q2 . we need 3 flip-flops.Q0 + Q1.Q0 + Q2.Q0 + Q2. Say.Q1. Q0 + Q2.Q0 + Q2.( Q1 + Q1).Q1. Q0 + Q2. Q0 + Q2. Q0 = Q2 .Q1. Q0 = Q2 . Q0 ) = Q1 Q0 D2 = Q2 .Q0 + Q1. Q1 .Q1. Q0 + Q2.Q1. Step 2: State transition diagram. use D flip-flops. Q0 + Q2 . 000 001 010 011 100 111 110 101 Step 3&4: Generate the truth table Present State Q2 Q1 Q0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Q2 0 0 0 1 1 1 1 0 Next State Q1 Q0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 D2 0 0 0 1 1 1 1 0 Flip-Flops D1 D0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 Step 5: Logic Design flip-flops.Q0 + Q2. Q0 ) = ( Q1 . Q0 D Q2 Q2 D Q1 Q1 D Q0 Q0 Clk Q2 Q1 Q0 Combinational Logic Homework: Repeat this with JK flip-flops. Q1 Q2. it can be seen from the table above that K0= 1. Q1 Q2.Q1 Q0 0 X X 0 Q0 0 X X 1 K1 = Q0 K2 Q2 . ME. 110 and 111 Step 3&4: Generate the truth table Present State Q2 Q1 Q0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Q2 0 0 0 1 0 X X X Next State Q1 Q0 0 1 1 0 1 1 0 0 0 0 X X X X X X J2 0 0 0 1 X X X X K2 X X X X 1 X X X Flip-Flops J1 K1 0 X 1 X X 0 X 1 0 X X X X X X X J0 1 X 1 X 0 X X X K0 X 1 X 1 X X X X Step 5: Logic Design flip-flops. Q1 Q2.Chapter 2 DIGITAL ELECTRONICS Example Design a 3-bit counter that counts from 000001010011100000 2: Step 1: Since it is 3 bit counter.Q1 Q0 0 0 X X Q0 1 X X X K1 Q2 .Q1 Q2 .Q1 Q2 . Q1 Q2. we have J1 Q2 . Q1 Q2. Step 2: State transition diagram.Q1 Q0 X X X 0 Q0 X X X 1 J1 = Q0 J2 Q2 . Q1 Q2.Q1 Q0 1 0 X 1 Q0 X X X X J0 = Q2 For K0. K1. Q1 Q2.Q1 Q0 X 1 X X K2 = 1 ©2011.Q1 Q2 . Similarly. Present State Q2 Q1 Q0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Flip-Flops J0 1 X 1 X 0 X X X J0 Q2 . for J1. Say. J2 and K2.Q1 Q2 . NUS Q0 X X X X J2 = Q1. Q1 Q2. use JK flip-flops.Q0 Page: 58 . For J0. 000 001 100 010 011 Note: There undefined states like 101. we need 3 flip-flops. Q1 Q2.Q1 Q2 . Q1 Q2. Mod-10 and Mod-6 Counters can be constructed by either a BCD counter or any 16-bit counter with reset capability. NUS .2. since latter require great care to address problems such as Races due to unequal path delays. races to be resolved etc. K0 = 1 J1 = K1 = Q0 J2 = Q1. 2. In most instances. 2. K2 =1 Q2 Q1 Q0 J 2 1 Q J 1 Q J 0 1 Q K Q K Q K Q Clk 2.2. operations. This allows time for transients and glitches to settle down.ME3241/ME3241E Microprocessor and Applications Therefore.6. Synchronous circuits bypass these problems by use of the clock which allows outputs to change only at discrete time instants. input changes. Decoder/Display units can be constructed by a BCD to 7-segment display decoder (see tutorial) and a 7-segment display LED.Q0. J0 = Q2 .11 Synchronous vs. operations generally preferred to async. asynchronous circuit designs Sync. Mod-2 Counter can be constructed by just a JK flip-flop.2. Page: 59 ©2011.6.6.Ring Counter A circulating arrangement where a single 1 moves from FF to FF. Transients and glitches which can cause incorrect operation.13 Other Counters Register Based Counters . ME. only a single 1 circulates. Output changes that depend on order of async.12 Counter Applications: Digital Clock 50 Hz Main Mod-2 Pulse shaper 50 pps Mod-50 Counter 1 pps Mod-10 Mod-6 Mod-10 Mod-6 Mod-10 Decoder/ Display 0-1 Tens Decoder/ Display 0-9 Units Decoder/ Display 0-5 Tens Decoder/ Display 0-9 Units Decoder/ Display 0-5 Tens Decoder/ Display 0-9 Units "Hours" section "Minutes" section "Seconds" section Pulse shaper can be constructed by a transformer and a schmitt trigger Mod-50 Counter can be constructed by a mod-10 counter cascading a mod-5 counter. Mod-N counter needs N FFs (more hardware than other counters for same mod-#).1 3-8 Decoders A decoder is a circuit element that will decode an N-bit code. 4-10 decoders. 0001 0010 0100 Clk 1 0 1 Qc 0 1 Qb 0 1 Qa 0 Qd 1000 D Q d Q D Q c Q D Q b Q D Q a Q 2.7.7. this counter does not need any decoding gates at all (saving). Example: A Mod-4 ring counter consists of 4 flip-flops.Chapter 2 DIGITAL ELECTRONICS Counter is initialized by presetting a 1 into one FF and clearing the rest. 3-8. Example: a 3-8 decoder. NUS Page: 60 . MSI decoders are available as 2-4. On the other hand. It activates an appropriate output line as a function of the applied N-bit input code. Decoders 2.1 Decoders 2. etc. Example: The 74’138 decoder 3-8 decoder. ©2011. ME. A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 O0 1 0 0 0 0 0 0 0 O1 0 1 0 0 0 0 0 0 O2 0 0 1 0 0 0 0 0 O3 0 0 0 1 0 0 0 0 O4 0 0 0 0 1 0 0 0 O5 0 0 0 0 0 1 0 0 O6 0 0 0 0 0 0 1 0 O7 0 0 0 0 0 0 0 1 O0 A0 O1 O2 O3 A2 O4 O5 O6 O7 A1 A decoder can have up to 2N output lines for N inputs.1.7 Encoders. N FFs mod-N counter. The decoder can be enabled/disabled by the input pins E1 . E2 and E3 ...... The chip is enable only when E1 = E2 =0 and E3 = 1.O15 74138 01234567 O16 -... NUS Page: 61 . active low.. ME. The enable pins allow multiple chip to be used together for higher bit decoding..O31 ©2011. i..ME3241/ME3241E Microprocessor and Applications E1 E2 E3 A0 A1 A2 123 E1 0 1 X X E2 0 X 1 X E3 1 X X 0 Output Respond to input code A2A1A0 Diabled – all HIGH Diabled – all HIGH Diabled – all HIGH E 74138 1-of-8 decoder O 0 O1 O2 O3 O4 O5 O6 O7 E1 E2 E3 A2 A1 A0 123 O7 O6 O5 O4 O3 O2 O1 O0 It has NAND gate output.O23 74138 01234567 O24 -... A0 A1 A2 A3 A4 123 A0 A1 A2 123 A0 A1 A2 123 A0 A1 A2 123 A0 A1 A2 E E E E 74138 01234567 O0 ... Example: Use 4 74138 decoders to set up a 1-32 decoder.-O7 74138 01234567 O8 -.e.-...-. Each segment is an LED which will light when a logic T signal is applied to it.all LED anodes connected – active low common cathode .1.all LED cathodes connected – active High. 7-segment displays are of 2 types: common anode .7447 a f e d g b c 0 1 2 3 4 5 D C B A 6 7 8 a b c 9 10 11 12 13 14 15 7447 BCD to 7 Seg LT RBI d e f g RBO Active LOW ©2011. L4 ON for 1 s and OFF for 1s.1. L2 ON for 1 s and OFF for 1s. and L5 ON for 1 s and OFF for 7s.7. or 7445 BCD-to-decimal decoder/driver (Open collector version) Example: Design a circuit which consists of 5 LED’s arranged in a line such that these LED will lights up in the following sequence.2 BCD-to-Decimal Decoder Used whenever an output or group of outputs is to be activated only on the occurrence of a specific combination of input levels. Commercially available decoders are 7442 BCD-to-decimal decoder.7. L1 ON for 1 s and OFF for 1s. Solution: 2.Chapter 2 DIGITAL ELECTRONICS 2. ME. NUS Page: 62 .3 BCD to 7 Segment decoder Converts a BCD number into signals required to display that number on a 7segment display. Commercial BCD to 7 Segment decoder . L3 ON for 1 s and OFF for 1s. After that L1 start again and repeat itself. NUS Page: 63 . ME.7448 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 A B C D 7448 BCDto7Seg a b c d e f g RBO LT RBI Active HIGH Func 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BI RBI LT LT RBI 1 1 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X X X 1 0 0 X Input D C 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 X X 0 0 X X B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X 0 X A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X 0 X BI/ RBO 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 a 1 0 1 1 0 1 0 1 1 1 0 0 0 1 0 0 0 0 1 b 1 1 1 1 1 0 0 1 1 1 0 0 1 0 0 0 0 0 1 c 1 1 0 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 1 Output d e 1 1 0 0 1 1 1 0 0 0 1 0 1 1 0 0 1 1 0 0 1 1 1 0 0 0 1 0 1 1 0 0 0 0 0 0 1 1 f 1 0 0 0 1 1 1 0 1 1 0 0 1 1 1 0 0 0 1 G 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 ©2011.ME3241/ME3241E Microprocessor and Applications Func 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BI RBI LT LT RBI 1 1 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X X X 1 0 0 X Input D C 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 X X 0 0 X X B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X 0 X A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X 0 X BI/ RBO 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 a 0 1 0 0 1 0 1 0 0 0 1 1 1 0 1 1 1 1 0 b 0 0 0 0 0 1 1 0 0 0 1 1 0 1 1 1 1 1 0 c 0 0 1 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 0 Output d e 0 0 1 1 0 0 0 1 1 1 0 1 0 0 1 1 0 0 1 1 0 0 0 1 1 1 0 1 0 0 1 1 1 1 1 1 0 0 f 0 1 1 1 0 0 0 1 0 0 1 1 0 0 0 1 1 1 0 G 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 Commercial BCD to 7 Segment decoder . ME. O0 A0 A1 A2 A3 A4 A5 A6 A7 O1 O2 A0 X X X X X X X X A1 1 0 1 1 1 1 1 1 A2 1 1 0 1 1 1 1 1 A3 1 1 1 0 1 1 1 1 A4 1 1 1 1 0 1 1 1 A5 1 1 1 1 1 0 1 1 A6 1 1 1 1 1 1 0 1 A7 1 1 1 1 1 1 1 0 O2 0 0 0 0 1 1 1 1 O1 0 0 1 1 0 0 1 1 O0 0 1 0 1 0 1 0 1 Commercial Decimal to BCD Priority encoder A1 A2 A3 A4 A5 A6 A7 A8 A9 O0 O1 O2 O3 74147 Decimal to-BCD priority encoder Inputs Inverted BCD A1 1 X X X X X X X X 0 A2 1 X X X X X X X 0 1 A3 1 X X X X X X 0 1 1 A4 1 X X X X X 0 1 1 1 A5 1 X X X X 0 1 1 1 1 A6 1 X X X 0 1 1 1 1 1 A7 1 X X 0 1 1 1 1 1 1 A8 1 X 0 1 1 1 1 1 1 1 A9 1 0 1 1 1 1 1 1 1 1 O3 O2 O1 O 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 Page: 64 ©2011. an encoder is a circuit element that generates an M-bit binary code (2M > N) that uniquely identifies the input.2 Encoders Perform the inverse of the decoding function. NUS . For N different inputs.7.Chapter 2 DIGITAL ELECTRONICS Uses of RBO and RBI 2. Example: An 8-3 encoder. the select inputs S2S1S0 will select one data input (I0~I7) for passage to output Z.1 Multiplexers I0 I1 I0 I1 I2 I3 S1 S0 Output Z I2 Z I3 S1 S0 A multiplexer (MUX) is a combinational circuit element that selects data from one of many inputs and directs it to a single output.8 Multiplexers & demultiplexers 2.ME3241/ME3241E Microprocessor and Applications 2. NUS Page: 65 . ME. Both normal and inverted output are provided E 1 0 0 0 0 0 0 0 0 S2 X 0 0 0 0 1 1 1 1 S1 X 0 0 1 1 0 0 1 1 S0 X 0 1 0 1 0 1 0 1 Z 1 Z 0 I0 I1 I2 I3 I4 I5 I6 I7 I0 I1 I2 I3 I4 I5 I6 I7 S0 S1 S2 E I0 I1 I2 I3 I4 I5 I6 I7 74151 MUX Z Z ©2011. multiplexer is disabled. Example: A 4-input multiplexer S1 S0 Output 0 0 Z = I0 0 1 Z = I1 1 0 Z = I2 1 1 Z = I3 Comercial 8-input multiplexer (74151) Multiplexer has an ENABLE which is active-low When E=0.8. When E=1. 2 Multiplexer Applications Logic Function Generation Truth Table C B A Z 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 Operation Sequencing 1K E S0 S1 S2 I0 I1 I2 I3 I4 I5 I6 I7 74151 MUX Z Page: 66 ©2011.Chapter 2 DIGITAL ELECTRONICS Commercial Quad Two-input MUX (74157) S 1 0 0 X 0 1 Za 0 I0a I1a Zb 0 I0b I1b Zc 0 I0c I1c Zd 0 I0d I1d I1a S E I0a I1b I0b I1c I1a I1b I1c I1d S E I0a I0b I0c I0d 74157 Quad 2 input MUX Za Zb Zc Zd I0c I1d I0d Za Zb Zc Zd 2. NUS . ME.8. 8. NUS Page: 67 . ME. The select input code determines to which output the DATA input will be transmitted.3 Demultiplexers Demultiplexer takes a single input and distributes it over several outputs.ME3241/ME3241E Microprocessor and Applications Data Routing Counter 1 Tens Units BCD Counter BCD Counter Clk #1 Counter 2 Tens Units BCD Counter BCD Counter Clk #2 Select I1 S E 74157 MUX (Tens) Z I0 a Zb Zc Zd I1 S E 74157 MUX (Units) Z I0 a Zb Zc Zd 7447 BCD to 7 Seg Decoder/Driver 7447 BCD to 7 Seg Decoder/Driver Tens Units 7-Segment Display 7-Segment Display 2. DEMUX Data input O0 O1 O2 O3 S0 S1 1-line-to-8-line Demultiplexer Select S2 S1 S0 O7 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 D O6 0 0 0 0 0 0 D 0 O5 0 0 0 0 0 D 0 0 Outputs O4 O3 O2 0 0 0 0 0 0 0 0 D 0 D 0 D 0 0 0 0 0 0 0 0 0 0 0 O1 0 D 0 0 0 0 0 0 O0 D 0 0 0 0 0 0 0 S0 S1 S2 O0 O1 O2 O3 O4 O5 O6 Data O7 ©2011. Chapter 2 DIGITAL ELECTRONICS 74138 decoder as a demultiplexer Use the enable input E1 as the data input I.8.4 Demultiplexer Applications Security Monitoring System 330 I0 O0 I1 I2 I3 I4 I5 74LS151 door 0 +5 V I6 +5 V I7 E S2 S1 S0 A2 A1 Z O6 O7 A0 O5 MUX 3 2 1 74LS138 DEMUX O1 +5 V O2 O3 O4 +5 V +5 V Q2 Q1 Q0 Clock door 6 door 7 Mod-8 Counter Page: 68 ©2011. E1 E2 E3 A0 A1 A2 123 E 74138 1-of-8 decoder O 0 O1 O2 O 3 O 4 O5 O6 O 7 2. NUS . ME. 1 Register A register is a device you use to store some information. a flip-flop. D Q R/W L Q CE Data CE 1 0 0 R/ W X 0 1 D Q Data Not connected Writing data to memory Reading from memory D Q L Q D Q L Q D Q L Q Cascading four of these latches form a nibble of register.1 Making of a microprocessor Registers. o 1 nibble 4 bits o 1 byte 8 bits o 1 word 16 bits.1. Ram’s and Buses 3.1.Chapter 3 Microprocessor Architecture 3. a ONE or a ZERO. NUS Page: 69 . This can be achieved by the use of a D – Latch as such.e. L Q R/W CE Q3 Q2 Q1 Q0 To transfer data between Register A & B Reg A R/Wa D Q L Q D Q L Q D Q L Q D Q L Q CEa A3 A2 A1 A0 B3 B2 D Q L Q D Q L Q B1 D Q L Q B0 D Q L Q Reg B R/Wb CEb Transferring between accumulator and two other registers ©2011. The most commonly used group is byte (8 flip-flops). i. ROM’s.1 3. one flip-flop can only store two possible values.1. we sometime wish to share the input and output line together. I7 D SET I6 Q D SET I5 Q D SET I4 Q D SET I3 Q D SET I2 Q D SET I1 Q D SET I0 Q D SET Q CLR Q CLR Q CLR Q CLR Q CLR Q CLR Q CLR Q CLR Q Write Pulse O7 O6 O5 O4 O3 O2 O1 O0 However. o We usually group a few flip-flop to form one set of storage e.g. +5V Write pulse Input Write pulse S D R Q Clk Q Storage Input Storage Q o However. ME. in its simplest form. D0 R/W CE D3 . Most common type of memory found in computers and other devices. D0 Reg X R/W CE D3 . There are two basic types of RAM (based on different technology): . Data D0 A0 Decoder A1 D3 CE R/W D0 A0 4K RAM A11 D0 D7 Also now as volatile memory.1. meaning that they lose their contents when the power is turned off. a type of computer memory that can be accessed randomly. D0 R/W CE D3 . D0 A 4-Nibble RAM R/W D0 D3 D0 D3 D0 D3 D0 D3 A0 A1 CE R/W R/W CE R/W CE D3 CE 3. such as printers. D0 Acc R/W CE D3 . we have constructed a very small size 4-nibble RAM. . . ME.1. D0 Acc A1 1 2 3 R/W CE D3 . . D0 Reg Y X/Y Transferring many to one Read/ Write 2-to-4 Decoder A0 0 R/W CE D3 . .2 RAM As illustrated in previous section. . any byte of memory can be accessed without touching the preceding bytes.dynamic RAM (DRAM) © 2011.Chapter 3 Microprocessor Architecture Read/ Write R/W CE D3 . that is. . . Acronym for random access memory. . It usually consists of the following pins READ/ WRITE to control read/write status of the memory A0~An to select a specific memory cell D0-D7 to read/write the actual data CE to enable or disable the chip. D0 R/W CE D3 . NUS Page: 70 R/W CE . 1. which makes it faster. Intel and Rambus are also working a new version of RDRAM. Being used in place of VRAM in some graphics accelerator boards. SDRAM is replacing EDO DRAM in many newer computers . like other types of ROM. Variation of a ROM are PROM (programmable read-only memory). Like other types of PROM. you need a special device called a PROM programmer or PROM burner.RDRAM (Rambus DRAM) . that will support data transfer speeds at up to 1. . BIOS in your IBM compatible PC) Also used extensively in calculators and peripheral devices such as laser printers. it cannot be removed and can only be read.a type of DRAM that is faster than conventional DRAM. . More commonly used Some variance of DRAMs are: .g.3 ROM Acronym for read-only memory Computer memory on which data has been prerecorded.Static RAM does not need to be refreshed. PC’s usually contain ROM that stores critical programs such as the program that boots the computer. ROM retains its contents even when the computer is turned off.600 MHz.EDO DRAM . Faster than SDRAM (600 MHz). ROM is referred to as being nonvolatile. whose fonts are often stored in ROMs. EEPROM retains its contents even when the power is turned off. EEPROM (electrically erasable programmable read-only memory) A special type of PROM that can be erased by exposing it to an electrical charge. static RAM (SRAM) . 3. Can be written to only once EPROM (erasable programmable read-only memory) A special type of memory that retains its contents until it is exposed to ultraviolet light. called nDRAM. Unlike conventional DRAM which can only access one block of data at a time. making it possible to reprogram the memory.a new type of DRAM that can run at much higher clock speeds than conventional memory. Also. EEPROM is not as fast as RAM.BEDO DRAM (Burst EDO DRAM) . Unlike RAM. EDO RAM can start fetching the next block of memory at the same time that it sends the previous block to the CPU. . To write to and erase an EPROM.More expensive than dynamic RAM. ©2011. Inc.SDRAM (Synchronous DRAM) . whereas RAM is volatile. It usually consists of the following pins A0~An to select a specific memory cell D0-D7 to read the actual data A0 D0 16 K ROM D7 A13 CE to enable or disable the chip. SDRAM actually synchronizes itself with the CPU's bus and is capable of running at about twice as fast EDO DRAM and BEDO DRAM. The ultraviolet light clears its contents.NUS Logo Microprocessor Architecture - - Needs to be refreshed.a type of memory (DRAM) developed by Rambus.a new type of EDO DRAM that can process four memory addresses in one burst. PROMs are manufactured as blank chips on which data can be written with a special device called a PROM programmer.1. Once data has been written onto a ROM chip. ME. NUS Page: 71 CE . (e. 1.2 Digital Arithmetic Circuits From previous chapter.1.1. NUS .Chapter 3 Microprocessor Architecture 3. we have constructed a full adder Cn-1 A B S Cn C A B FA C-1 S 4-Bit Adder A3 A2 A1 A0 B3 B2 B1 B0 4 Bit Adder A C4 C B A C B A C B A C B FA C-1 S FA C-1 S FA C-1 S FA C-1 S C0 S3 S2 S1 S0 Addition with Registers Q3 Reg A Q0 Q3 Reg B Q0 C4 S3 S0 4 Bit Adder C0 Clk Q3 Temp Q0 Tri-States Page: 72 © 2011. ME.4 Concepts of bus Some Bus Example Data Bus D3 D0 MicroP D3 D0 D3 D0 D3 D0 D3 D0 4 nibble RAM A0 A1 CE R/W 4 nibble RAM A0 A1 CE R/W 4 nibble RAM A0 A1 CE R/W 4 nibble RAM A0 A1 CE R/W A0 A3 CE R/W Address Bus Decoder Control Bus 3. NUS Page: 73 .NUS Logo Microprocessor Architecture Parallel Add/Subtract using 2’s complement Q3 Reg A Reg B Q0 Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 Add/ Subtract C4 S3 S0 4 Bit Adder C0 Clk Q3 Temp Q0 Tri-States 3.3 A Very Simple microprocessor Control Bus Address Bus External I/O PIO ROM RAM Data Bus Tri-state Buf Instr Regs Accumulaor Tmp Reg 1 Add/ Subtract Address Register Instr Decoder Arithmetic Unit Tmp Reg 2 Internal Data Bus Microprocessor ©2011. ME.1.