Mcs-012 Solved Assignment Ignou 2012

Course Code Course Title Assignment Number Maximum Marks Weightage Last Dates for Submission: : : : : : MCS-012 Computer Organisation and Assembly Language Programming MCA(1)/012/Assign/2011 100 25% 15th April, 2011 (For January Session) 15th October, 2011 (For July Session) There are four questions in this assignment, which carries 80 marks. Rest 20 marks are for viva voce. You may use illustrations and diagrams to enhance the explanations. Please go through the guidelines regarding assignments given in the Programme Guide for the format of presentation. Answer to each part of the question should be confined to about 300 words. Question 1: (a) Perform the following arithmetic operations using binary signed 2’s complement notation for integers. You may assume that the maximum size of integers is of 10 bits including the sign bit. (Please note that the numbers given here are in decimal notation) (3 Marks) i) Ans: Add – 498 and 260 Decimal -498 260 -238 ii) Ans: ww Carry bit Carry bit 1 .d w Sign bit 1 0 1 Sign bit 1 1 1 ge ar e et k.n e 2’s Complement mantissa 000001110 100000100 100010010 Subtract 456 from – 56 Decimal -456 -56 -512 2’s Complement mantissa 000111000 111001000 000000000 Overflow, cannot accumulate carry bit iii) Ans: Add 256 and 255 Decimal Carry bit Sign bit 2’s Complement mantissa 256 0 100000000 255 0 111111111 511 1 011111111 Overflow, as carry bit moved in place of sign bit, thus making it a negative number. Page 1 (b) Convert the hexadecimal number: FA BB C9 into binary, octal and decimal. Ans1: (FA BB C9)16 = (0110011001001011000111)2 Ans2: (FA BB C9)16 = (77735711)8 Ans3: (FA BB C9)16 = (16759753)10 (1 Mark) (c) Convert the following string into equivalent ASCII code – “Copyright © 2001 - 2011”. Include ASCII code of spaces between words in the resultant ASCII. Are these codes same as that used in Unicode? (2 Marks) Ans: 43h6fh70h79h72h69h67h68h74h20h28h43h29h20h32h30h30h30h20h32h30h31h31h Character C o p y r i g h t space ( c ) space 2 0 0 0 space 2 0 1 1 ASCII 43H 6FH 70H 79H 72H 69H 67H 68H 74H 20H 28H 43H 29H 20H 32H 30H 30H 30H 20H 32H 30H 31H 31H ww .d w ge ar e et k.n e UNICODE 0043 006F 0070 0079 0072 0069 0067 0068 0074 0020 0028 0043 0029 0020 0032 0030 0030 0030 0020 0032 0030 0031 0031 Yes the codes are same in ASCII & UNICODE (d) Design a logic circuit that accepts a four digit binary input and creates an odd parity bit, a sign check bit and a more than two zero value test bit. The odd parity bit is created for the four bit data. The sign bit is set to 1 if the left most bit of the data is 1. Zero value bit is set to 1 if three of the input bits are Page 2 (5 Marks) Ans: ww . Flip flops input equations and the circuit output are as follows: (5 Marks) DA = x B’ DB = y A + x’ A’ z=A+B (i) Draw the circuit diagram for the above. two inputs x and y and one output z.zero. Draw the truth table and use K-map to design the Boolean expressions for each of the output bits.n e (e ) A sequential circuit has two D flip flops A and B.d w ge ar e et k. Page 3 . Draw the resulting circuit diagram using AND – OR – NOT gates. d w ge ar e D B B’ et k. You may assume that the mantissa is in normalised Page 4 .Clock X Y CxB’ CyA’ D A A’ A Z Cx’A’ CyA+x’A’ (ii) x 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ww Tabulate the state table for the flip flops. Present State Next State y A B A B 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 .n e B (f) Design a floating point representation of 32 bits closer to IEEE 754 format except that the exponent of the representation should be of 4 bits only. (4 Marks) Ans: 0 S 1 Biased exponent (E) 8 9 Significant (N) 31 Question 2: (a) A RAM has a capacity of 64 K × 64. Data Word Size = 32) Fig : Address Relationship Page 5 . there are 65536 memory addresses. Since 65536 = 16 2 it requires 16 bits address code to specify one of 65536 addresses. if direct memory to cache mapping scheme is used.d w ge ar e et k. Assume that this memory have a cache memory of 8 Blocks with block size of 32 bits. Hence. the exponent bias of 7.form. draw a diagram to show the address mapping of RAM and Cache. (i) Ans: How many data input and data output lines does this RAM need to have? 64.n e (2 Marks) Octal 00 Address 00 000 001 Size = 16 x 256 bits Octal 000 Address 001 Size = 32 x 8 bits 77 77 776 777 Main Memory 776 777 Cache Memory (Address = 16.125) 10 using this format . (ii) Ans: How many address lines will be needed for this RAM? 64K = 64 × 1024 = 65536 words. (4 Marks) Ans: Address = 16 bits 6 bits Tag 10 bits Index ww . Represent the number (89. since the word size is 64. and one bit is used for the sign bit. For the given memory and Cache in the statements as above. (b) Consider a RAM of 256 words with a word size of 16 bits. Explain how the I/O will be performed if (i) Ans: Interrupt Driven Input/ Output Scheme is used. both in the processor hardware and software. Now CPU saves the important register and processor status of the executing program in a stack and requests the I/O device to provide its data. The interrupt-driven I/O mechanism for transferring a block of data is shown in Figure. the CPU checks for interrupts (which will occur when data is in data register of I/O interface and it now needs CPU’s attention).n e (4 Marks) Page 6 . which is placed on the data bus by the I/O device.Memory Data Memory Address 00000 1456 Index Address 000 00 1456 Octal 777 02 2222 Cache Memory 2222 02777 Fig : Direct Mapping Cache Organisation (c) You want to read a file from a disk. the CPU can go back to the program it was executing before the interrupt. With interrupt driven I/O. Upon detecting the external interrupt signal. Please note that after issuing a read command (for input) the CPU goes off to do other useful work while I/O interface proceeds to read data from the associated device. After taking the required action with the data. Interrupt-Processing The occurrence of an interrupt fires a numbers of events.d ge r et k. it generates an interrupt request to the computer. the processor stops the task it is processing. when the interface determines that the device is ready for data transfer. branches to a service program to process the I/O transfer. ww w ea . On the completion of an instruction cycle. and then returns to the task it was originally performing which results in the waiting time by the processor being reduced. which is contained in the register called program status word (PSW). The processor now loads the PC with the entry location of the interrupt-handling program that will respond to this interrupting condition. In addition. the processor proceeds to execute the next instruction. The execution results in the following operations: 6. Once the PC has been loaded.d w ge ar e et k. ww . before the CPU starts executing the interrupt routine (using its registers) are: (a) The status of the processor. the following sequence of hardware events occurs: 1. The processor finishes execution of the current instruction before responding to the interrupt. Because the instruction fetch is determined by the contents of the PC. which begins with an instruction fetch. When an I/O device completes an I/O operation. The PC & PSW relating to the interrupted program have already been saved on the system stack.Figure 8 shows a sequence. Page 7 . When interrupt processing is complete. that is the next instruction cycle. the result is that control is transferred to the interrupt-handler program. the saved register values are retrieved from the stack and restored to the registers. As a result. which is contained in the program counter (PC). 3. 2. of the currently executing program. 4. The interrupt handler next processes the interrupt. The final step is to restore the values of PSW and PC from the stack. 8. which are shown in Figure . This includes determining of the event that caused the interrupt and also the status information relating to the I/O operation. the instruction to be executed will be from the previously interrupted program. The contents of all of the registers plus the address of the next instruction (N+1) are pushed on to the stack. 7. The device issues an interrupt signal to the processor. Figure shows a simple example. 9. Here a user program is interrupted after the instruction at location N. and (b) The location of the next instruction to be executed. The minimum information required to be stored for the task being currently executed.n e 5. The processor tests for the interrupts and sends an acknowledgement signal to the device that issued the interrupt. the contents of the processor registers are also needed to be saved on the stack that are used by the called Interrupt Servicing Routine because these registers may be modified by the interrupt-handler. • The number of words to be read or written is communicated on the data lines and is stored in the data count register. • The address of I/O devices. When an I/O is requested. which is to be used. ww . A technique called cycle stealing allows the DMA interface to transfer one data word at a time. • The starting location on the memory where the information will be read or written to be communicated on the data lines and is stored by the DMA interface in its address register. after which it must return control of the bus to the processor. In both interrupt-driven and programmed I/O. the processor is busy with executing input/output instructions and the I/O transfer rate is limited by the speed with which the processor can test and service a device. The processor merely delays its operation for one memory cycle to allow the directly memory I/O transfer to “steal” one memory cycle. Hence. DMA involves an additional interface on the system bus. Page 8 . which acts as if it has taken over control from the processor. yet it must use the path between interfaces that is the system bus.(ii) Direct Memory Access is used.n e DMA Function Although the CPU intervention in DMA is minimised. the processor issues a command to the DMA interface by sending to the DMA interface the following information (Figure 10): • Which operations (read or write) to be performed.d w ge ar e et k. communicated on the data lines. Thus. using the read or write control lines. What about a technique that requires minimal intervention of the CPU for input/output? These two types of drawbacks can be overcome with a more efficient technique known as DMA. the question is: why do we use DMA interface? It is used primarily when a large amount of data is to be transferred from the I/O device to the Memory. Figure 11 below shows the five cycles for an instruction execution. (Please calculate data transfer time for the disk in addition to the seek time and latency time).d w ge ar e et k. the DMA interface sends an interrupt signal to the processor. The Figure also shows the five points where a DMA request can be responded to and a point where the interrupt request can be responded to. in DMA the processor involvement can be restricted at the beginning and end of the transfer. (d) Find the average disk access time that reads or writes a 512 byte sector.n e Page 9 . directly to or from memory.The DMA interface transfers the entire block of data. When the transfer is complete. which can be shown as in the figure above. Thus. without going through the processor. each track of the disk has 100 sectors and data transfer rate of the disk is 100 MB/second. Please note that an interrupt request is acknowledged only at one point of an instruction cycle. But the question is when should the DMA take control of the bus? For this we will recall the phenomenon of execution of an instruction by the processor. and that is at the interrupt cycle. Also find out what is meant by the controller overhead in the context of disk access time. Assume that the disk rotates at 12000 rpm. (2 Marks) Ans: ww . one word at a time. d w ge ar e et k.txt uses three clusters.the basic unit of logical storage on a disk at the operating system level .(Word Limit for answer of each part is 50 words ONLY) (6 Marks) (i) DIMM Ans: Dual Inline Memory Module or DIMM is a series of Random Access Memory (RAM) chips mounted on a small printed circuit board. The DIMM makes physical contact with the data bus of the computer through teeth like connectors that fit into a socket on the mother board.txt is a fragmented file that requires three clusters and File3. They were developed by the company RCA in the 1960s. For example. which indicates that this cluster is the end of the file. LCDs function simply by blocking available light so as to render display patterns. The diagram shows three files: File1.the form of addressing used by the drive's hardware controller.n e (iii) Ans: Page 10 . It is the part of the processor that actually performs the reading and executing of instructions. File2.txt fits in one cluster. The purpose of the File Allocation Table is to provide the mapping between clusters . They consume very little electricity and have advanced technologically to quite good resolutions and colour support. DIMMs use a 64-bit data path. or an end-offile indicator at (0xFFFF). Core of a processor The "core" in a processor is the microprocessor inside of the CPU (Central Processing Unit). In each case. since processors used in personal computers including the Intel Pentium have a 64-bit data width.and the physical location of data in terms of cylinders. (ii) Ans: LCD monitors LIQUID CRYSTAL DISPLAYS (LCD) LCDs are the screens of choice for portable computers and lightweight screens. The entire circuit collectively forms a memory module.(e) What is the purpose of FAT? Explain. Explain the main purpose / use / advantage of the term. servers and high-end workstations. tracks and sectors . The FAT contains an entry for every file stored on the volume that contains the address of the file's starting cluster. Each cluster contains a pointer to the next cluster in the file. the file allocation table entry points to the first cluster of the file (f) Define each of the following term. if we have a Dual Core CPU then we have 2 microprocessors inside of the ww . (Word limit for the answer is 200 words ONLY) Ans: (2 Marks) The FAT file system was first introduced in the days of MS-DOS way back in 1981. DIMMs are commonly used in personal computers. and more efficient transfer through an (optional) I/O queuing protocol.CPU. (iv) SATA Ans: Serial ATA (SATA or Serial Advanced Technology Attachment) is a computer bus interface for connecting host bus adapters to mass storage devices such as hard disk drives and optical drives. native hot swapping. data lookup applications .n e (vi) Ans: Zone Bit Recording (ZBR) in the context of disks Zone Bit Recording (ZBR) is used by disk drives to store more sectors per track on outer tracks than on inner tracks. On a disk consisting of concentric tracks.d w ge ar e et k. SATA host-adapters and devices communicate via a high-speed serial cable over two pairs of conductors. this allows us to do two things at once. but has very slow seek times) and CAV (which has faster seek times. Hard disk controllers implement ZBR by varying the rate at which it reads and writes .faster on outer tracks. but its not as fast as having multiple cores. ZBR is a compromise between CLV (which packs the most bits onto a disk. SATA uses the same basic ATA and ATAPI command-set as legacy ATA devices. all operating at much lower frequency. In contrast. offering several advantages over the older parallel ATA (PATA) interface: reduced cable-bulk and cost (7 conductors versus 40). as a microprocessor can only do one thing at a time the only exception to this is Multi-Threading which allows one core to do the work of multiple cores. b) The distribution of parity strips across all drives avoids the potential input/output bottleneck found in level 4. (v) Ans: RAID level 5 This level belongs to independent access category. Its main features are: a) Employs independent access as that of level 4 and distributes the parity strips across all disks. Page 11 . Therefore. holding storage density constant. such as the 3. faster data transfer through higher signaling rates. spin the medium faster when reading or writing inner tracks. It is also called Zone Constant Angular Velocity (Zone CAV or Z-CAV or ZCAV). Some other ZBR drives. Serial ATA was designed to replace the older ATA (AT Attachment) standard (also known as EIDE). parallel ATA (the redesignation for the legacy ATA specifications) used a 16-bit wide data bus with many additional support and control signals. ww I/O Request Rate Read is Excellent while write is fair Data Transfer Rate Read is fair while write is poor It is used in High request rate read intensive. the physical track length may or may not be increased with distance from the center hub.5" floppy drives in the Apple IIGS and older Macintosh computers. but stores fewer bits on a disk). the track storage capacity likewise increases with distance from the center. To ensure backward compatibility with legacy ATA software and applications. One side effect of ZBR is the raw data transfer rate of the disk when reading the outside tracks is much higher -.d w ge ar e et k. Page 12 . The are various ways of specifying address of the data to be operated on. Question 3: (a) Assume that a new programming language has been developed that have an extensive use of data and instruction arrays. The value of the mode field determines which addressing mode is to be used. b) One or more bits in the instruction format can be used as mode field. The most common addressing modes are: • • • • • • • ww . Such a programming language requires efficient handling of arrays. The language does not support recursion. Give justification of the selection of each of the addressing modes. This language supports call by reference as arrays are being passed by reference.the data transfer rate of the same disk when reading the "inner" (closest to the hub) tracks. List four addressing mode that must be supported by such a machine. The effective address will be either main memory address of a register. You have been assigned the task to design the addressing modes for a machine that supports this new programming language. Most often used are : a) Different operands will use different addressing modes.n e (4 Marks) Immediate addressing mode Direct addressing mode Indirect addressing mode Register addressing mode Register indirect addressing mode Displacement addressing mode Stack addressing mode To specify the addressing mode of an instruction several methods are used. These different ways of specifying data are called the addressing modes. Ans: Types of Addressing Modes Each instruction of a computer specifies an operation on certain data. about double -.in some disks. INSTRUCTION OPERAND Direct Addressing: In direct addressing mode. Register Indirect Addressing: This mode is similar to indirect addressing. the address field of the instruction refers to the address of a word in memory.d w ge ar e et k. effective address of the operand is given in the address field of the instruction. He disadvantage is that instruction execution requires two memory reference to fetch the operand Multilevel or cascaded indirect addressing can also be used. Ro. The register contains the effective address of the operand. Add Q. The advantage of this mode is that no memory reference other than instruction fetch is required to obtain operand. an address space of 2N can be addressed. The address field of the instruction refers to a register. which in turn contains the full length address of the operand. which most instruction sets is small compared to word length. Length of the address field is usually less than the word length. Displacement Addressing: In displacement addressing mode there are 3 types of addressing mode. Ex : Move P. The only difference is that the address field of the instruction refers to a register rather than a memory location 3 or 4 bits are used as address field to reference 8 to 16 generate purpose registers. This mode is used to define a constant or set initial values of variables.n e . The address space is limited to the width of the registers available to store the effective address. This mode uses one memory reference to obtain the operand. The disadvantage is that the size of the number is limited to the size of the address field. Indirect Addressing: Indirect addressing mode. Register Addressing: Register addressing mode is similar to direct addressing. Here. The advantages of register addressing are Small address field is needed in the instruction. It requires one memory reference to read the operand from the given location and provides only a limited address space. They are : Page 13 ww . Ro P and Q are the address of operand. the operand is given in the instruction itself. The advantage of this mode is that for the word length of N.Immediate Addressing: This is the simplest form of addressing. MAR. or instruction address register.d w ge ar e et k. the PC holds either the address of the instruction being executed. jumps and subroutine calls and returns. In most processors. or just part of the instruction sequencer in some computers) is a processor register that indicates where the computer is in its instruction sequence. so that instructions are normally retrieved sequentially from memory. Stack Addressing: Stack is a linear array of locations referred to as last-in first out queue. (5 Marks) Ans: Program counter or PC: ww .n e The program counter. This is a combination of direct addressing and register indirect addressing. (you may assume the roles of these registers same as that are defined in general for a von Neumann machine) The instruction of this machine can take only one direct operand. // increments the operand stored at location X. The value contained in one address field. Make and state suitable assumptions. Show the steps for fetch and execute operations of the instructions using suitable microoperations. AC. such as the 8080 or 4004. or PC (also called the instruction pointer to a seminal Intel instruction set. such as branches. IR. (b) Assume a hypothetical machine that has only PC. DR and Flag registers. A subroutine call is achieved simply by reading the old Page 14 . or the address of the next instruction to be executed. interrupting the sequence by placing a new value in the program counter. The result of increment is left in AC. This mode of addressing is also known as implicit addressing. appended or deleted only at the top of the stack. The stack is a reserved block of location. They allow new values to be loaded (written) into the program counter register. A is used directly and the other address refers to a register whose contents are added to A to produce the effective address. It has an instruction: INC X. Depending on the details of the particular computer. the program counter is incremented automatically after fetching a program instruction. if any. Stack pointer is a register which stores the address of top of stack location.1) Relative addressing 2) Base register addressing 3) Indexing addressing. with certain instructions. Such jump instructions allow a new address to be chosen as the start of the next part of the flow of instructions from the memory. Historically almost all early computers were accumulator machines. a CPU might have an instruction like: ADD memaddress This instruction would add the value read from the memory location at memaddress to the value from the accumulator. Only when all numbers have been added is the result held in the accumulator written to main memory or to another. etc. also called a 1-operand machine. and saving them somewhere in memory or in another register. but other instructions use register numbers for explicit operand specification. The accumulator is initially set to zero. non-accumulator. MAR: Page 15 . The accumulator is not identified in the instruction by a register number. These CPUs are not considered "accumulator machines". For instance. An accumulator machine. A subroutine return is then achieved by writing the saved value back in to the program counter again. placing the result in the accumulator. the PIC micro. the 8051 and several others) are basically accumulator machines. multiplication. Without a register like an accumulator.contents of the program counter. it is implicit in the instruction and no other register can be specified in the instruction. Access to main memory is slower than access to a register like the accumulator because the technology used for the large main memory is slower (but cheaper) than that used for a register.n e Modern CPUs are typically 2-operand or 3-operand machines—the additional operands specify which one of many general purpose registers (also called "general purpose accumulators"[1]) are used as the source and destination for calculations. perhaps only to be read right back again for use in the next operation. The characteristic which distinguishes one register as being the accumulator of a computer architecture is that the accumulator (if the architecture were to have one) would be used as an implicit operand for arithmetic instructions. Accumulator (AC): In a computer's central processing unit (CPU). and many microcontrollers still popular as of 2010 (such as the 68HC12.d w ge ar e et k. before they are overwritten by a new value. then each number in turn is added to the value in the accumulator. an accumulator is a register in which intermediate arithmetic and logic results are stored.) to main memory. it would be necessary to write the result of each calculation (addition. is a kind of CPU in which—although it may have several registers— the CPU always stores the results of most calculations in one special register—typically called "the" accumulator of that CPU. shift. or a CPU with accumulatorbased architecture. ww . The canonical example for accumulator use is summing a list of numbers. Some architectures use a particular register as an accumulator in some instructions. CPU register. In some older and low end CPUs. a special data register. Modern processors can even do some of the steps of out of order as decoding on several instructions is done in parallel. This register is 16-bits wide. the EFLAGS and RFLAGS registers are 32-bits and 64-bits wide. determining where its operands are in memory. allocating processor resources to execute the command (in superscalar processors). In simple processors each instruction to be executed is loaded into the instruction register which holds it while it is decoded. Far more complex memory interfaces exist. Decoding the opcode in the instruction register includes determining the instruction. etc DR: Data registers are used to hold numeric values such as integer and floating-point values. data addressed by MAR is fed into the MDR (memory data register) and then used by the CPU. ww . Its successors. preparation or execution and then passes it to the next stage for its step. When writing to memory. More complicated processors use a pipeline of instruction registers where each stage of the pipeline does part of the decoding. The Memory Address Register is half of a minimal interface between a microprogram and computer storage. retrieving the operands from memory. In other words. prepared and ultimately executed. When reading from memory.n e Flag Registers: The FLAGS register is the status register in Intel x86 microprocessors that contains the current state of the processor. the CPU writes data from MDR to the memory location whose address is stored in MAR. known as the accumulator. MAR holds the memory location of data that needs to be accessed. but this is the least that can work. which can take several steps.d w ge ar e et k. The other half is a memory data register. respectively. is used implicitly for many operations. IR (Instruction register): Instruction register is the part of a CPU's control unit that stores the instruction currently being executed or decoded. The wider registers retain compatibility with their smaller predecessors Steps for instruction execution Step 1: Page 16 .The Memory Address Register (MAR) is a CPU register that either stores the memory address from which data will be fetched to the CPU or the address to which data will be sent and stored. ADD Memory location B with general purpose register R1 and store result in R1. • For addressing a register. In Step 2: • The IR is decoded. and transfers the instruction to Instruction Register (IR). for addressing 256 registers you just need 8 bits. if so needed let us say R2 • • Now. • Now this address is converted to physical machine address and put on address bus with the help of a buffer register sometimes called Memory Address Register (MAR). To do so we require: • Address of the “instruction to be fetched”. For example. • Memory-buffer register (MBR) holds the content of memory operation (load or store). fetches the instruction on the data bus. For example.d w ge ar e et k. which is a register that contains the address of the next instruction to be executed. whereas. ALU will perform addition of R1 & R2 under the command of control unit and the result will be put back in R1. a difference of 60%. Some of the basic registers in a machine are: • All von-Neumann machines have a program counter (PC) (or instruction counter IC). a computer would be able to execute programs. the common memory size of 1MB requires 20 address bits. the other instructions are fetched and executed using ALU and register under the control of the Control Unit The number and the nature of registers is a key factor that differentiates among computers. coupled with a request from control unit for reading. • Other types of registers: • Memory-address register (MAR) holds the address of next memory operation (load or store). • Processor status bits indicate the current status of the processor. Some of these registers are special registers and others are generalpurpose registers. With these three kinds of registers. Page 17 ww . • On completion of fetch PC is incremented to point to the next instruction. • There are a number of general-purpose registers. • This data may be stored in a general purpose register. overflow/no overflow etc.n e . is recorded in the status register. Intel Pentium has about 32 registers. The status of ALU operation for example result in zero/non zero. Normally Program counter (PC) register stores this information. A few factors to consider when choosing the number of registers in a CPU are: • CPU can access registers faster then it can access main memory. Sometimes it is combined with the other processor status bits and is called the program status word (PSW). They are called instruction register (IR). • Most computers use special registers to hold the instruction(s) currently being executed. depending on the number of addressable registers a few bit addresses is needed in an instruction. let us assume that Instruction Register contains an instruction.The first step of instruction execution is to fetch the instruction that is to be executed. Similarly. These address bits are definetly quite less in comparison to a memory address. • This. then control unit will first instruct to: • Get the data of memory location B to buffer register for data (DR) using buffer address register (MAR) by issuing Memory read operation. n e (2 Marks) 11110101 01011010 01001111 11110101 00000001 11110110 Sign Bit Sign Bit 11110101 1 11101010 4) Add R1.2. Programmer Visible Registers: These registers can be used by machine or assembly language programmers to minimize the references to main memory. carry-in input and result of operation if the following micro-operations are performed? (For each micro-operation you may assume the initial value of R1 and R2 as defined above) 1) Subtract R1 from R2 Ans: Number Carry Bit R1 Input R2 Output 1 2) Increment R1 Ans: Number R1 Input Output 3) Shift Left R1 Ans: Number R1 Input Output ww . What will be the values of select inputs. A general good number of registers is 32 in a general machine.• Compilers tend to use a small number of registers because large numbers of registers are very difficult to use effectively. Consider that R1 and R2 both are 8 bit registers and contains 11110101 and 01011010 respectively. From a user’s point of view the register set can be classified under two basic categories. Status Control and Registers: These registers cannot be used by the programmers but are used to control the CPU or the execution of a program.2 of Block 3 having the micro-operations as given in Figure 10 on page 62 of Block 3. (c) Assume that you have a machine as shown in section 3. • Registers are more expensive than memory but far less in number.d w Carry Bit Carry Bit Sign Bit 0 0 ge ar e et k. R2 with an initial input carry bit as 1 Ans: Number Carry Bit Sign Bit R1 1 Input R2 Output 1 11110101 01011010 01010000 Page 18 . Hardwired control organization 2. Hardwired control units can be optimized for fast operations. The control unit uses the opcode of instruction stored in the IR register to perform different actions for different instructions. The clock portion of the control unit issues a repetitive sequence of pulses for the SS duration of micro-operation(s). decoder and other digital circuits.n e The block diagram of control unit is shown in Figure . Most of them fall into two major categories: 1. This simplifies the control logic. This control line selection can be performed by a decoder. (Word limit is 150 words) (3 Marks) A variety of techniques have been used to organize a control unit. Page 19 . In the hardwired organization. the control unit is implemented by gates. flip-flops. The major inputs to the circuit are instruction register. The control unit logic has a unique logic input for each opcode. That is.d w ge ar e et k. Micro programmed control organization. the control unit is designed as a combinational circuit. Each of these 2 different input patterns will activate a single unique output line. Ans: ww .(d) What are the different types of Control Units? Explain the hardwired control unit with the hep of a diagram. n n A decoder will have n binary inputs and 2 binary outputs. These timing signals control the sequence of execution of instruction and determine what control signal needs to applied at what time for instruction execution. and the flags. the clock. The instruction latency in a non-pipelined processor is slightly lower than in a pipelined equivalent. This prevents branch delays (in effect. Like all other instruction pipelines RISC pipeline suffer from the problems of data dependencies and branching instructions. A non-pipelined processor executes only a single instruction at a time. One of the common techniques used to avoid branch penalty is to pre-fetch the branch destination also. 3. This allows the computer's control circuitry to issue instructions at the processing rate of the slowest step. with storage at the end of each step. ww . A non-pipelined processor will have a stable instruction bandwidth. which is much faster than the time needed to perform all steps at once. The fundamental idea is to split the processing of a computer instruction into a series of independent steps. 2. RISC follows a branch optimization technique called delayed jump as shown in the example given below: Page 20 .n e Optimization of Pipelining in RISC Processors RISC machines can employ a very efficient pipeline scheme because of the simple and regular instructions. The term pipeline refers to the fact that each step is carrying data at once (like water). Consequently the design is simpler and cheaper to manufacture.d w ge ar e et k. This is because extra flip flops must be added to the data path of a pipelined processor.) The origin of pipelining is thought to be either the ILLIAC II project or the IBM Stretch project though a simple version was used earlier in the Z1 in 1939 and the Z3 in 1941 Disadvantages of Pipelining: 1. and each step is connected to the next (like the links of a pipe. The performance of a pipelined processor is much harder to predict and may vary more widely between different programs.(e) What is an instruction pipeline? What are the problems of an instruction pipeline? How can you optimise the instruction pipeline in RISC processors? (3 Marks) (Word limit 150 words) Ans: An instruction pipeline is a technique used in the design of computers and other digital electronic devices to increase their instruction throughput (the number of instructions that can be executed in a unit of time). every branch is delayed) and problems with serial instructions being executed concurrently. RISC optimizes this problem by using a technique called delayed branching. allow the most frequently accessed operands to be kept in registers in order to minimize registermemory operations. On return. the numbers of registers in a machine are less as generally the same chip contains the ALU and control unit. from Page 21 ww . Since most operand references are to local variables of a function in C they are the obvious choice for storing in registers. The hardware approach will require the use of more registers so that more variables can be held in registers for longer periods of time.return so the local variables are related to most recent local function. This also requires parameter passing on call.d w ge ar e et k.n e Ans: . a strategy is needed that will optimize the register use and. However. This technique is used in RISC machines. however in general about 32 registers were considered optimum. which requires techniques for program analysis. On the face of it the use of a large set of registers should lead to fewer memory accesses. in addition this call . Also the register addressing uses much shorter addresses than the addresses for main memory and the cache. Such optimisation can either be entrusted to an optimising complier. thus. the problem here is that the program follows function call . However. How will these registers be used for parameter passing for subroutine calls? Explain with the help of diagram ` (3 Marks) In general. Thus. the register storage is faster than the main memory and the cache.(f) Why do you use large numbers of registers in RISC processors? Assume that a RISC machine has 64 registers out of which 8 are reserved for the Global variables.return expects saving the context of calling program and return address. Some registers can also be used for global variables. or we can follow some hardware related techniques. Windows for adjacent procedures are overlapped. Let them be called by register number 0 – 64. rather than saving registers in memory as done in CISC.n e Function C Temporary variables of function C Local variables of function C Parameters of function C Temporary variables of function B Local variables of function B Parameters of function B 48 – 57 (10 Registers) 58 – 64 (6 Registers) Local variable of fA Parameter passed to fA Page 22 . The use from one fixed size window of registers to another. This feature allows parameter passing without moving the variables at all. 0–7 8-9 10 – 15 (6 Registers) 16 – 25 (10 Registers) 26 – 31 (6 Registers) 32 – 41 (10 Registers) 42 – 47 (6 Registers) Used for Global variables required by fA.returns with the help of register windows.a call the variables of the calling program must be restored and the results must be passed back to the calling program. Register files are broken into multiple small sets of registers and assigned to a different function. The diagram shows the use of registers: when there is call to function A (fA) which calls function B (fB) and function B calls function C (fC). RISC register file provides a support for such call. The following figure tries to explain this concept: Assumptions: Register file contains 64 registers.d w ge ar e Temporary variables of function A Local variables of function A Parameters of function A et k. fB. Registers Nos. A function call automatically changes each of these sets. and fC Unused Used by parameters of fC that may be passed to next call Used for local variable of fC Used by parameters that were passed from fB -> fC Local variables of fB Function A Function B Parameters that were passed from fA to fB ww . STR1 INT 21H MOV AH.13.NEWLINE INT 21H MOV AH."$" DATA ENDS CODE SEGMENT ASSUME DS:DATA. if any.09H LEA DX. You may assume that the end of a string character is ‘$’. The concatenated string is stored in memory location different from the two strings.AX LEA SI.n e Page 23 .Question 4: (a) Write an 8086 assembly Language Program with proper comments to concatenate two strings that are available in the memory.CS:CODE START: MOV AX.09H LEA DX.SI INT 21H MOV AH.INSTR1 LEA DI.d w ge ar e et k.0AH MOV DX.INSTR2 .DATA MOV DS.GET STRING MOV AH. Make suitable assumptions.09H LEA DX. (8 Marks) Ans : DATA SEGMENT STR1 DB "ENTER FIRST STRING HERE ->$" STR2 DB "ENTER SECOND STRING HERE ->$" STR3 DB "CONCATED STRING :->$" STR11 DB "FIRST STRING : ->$" STR22 DB "SECOND STRING: ->$" INSTR1 DB 20 DUP("$") INSTR2 DB 20 DUP("$") N DB ? N1 DB ? NEWLINE DB 10.STR2 ww . 09H LEA DX.09H LEA DX.09H LEA DX.09H LEA DX.2 Page 24 .DI INT 21H MOV AH.09H LEA DX.PRINT THE STRING MOV AH.INSTR1+2 INT 21H MOV AH."$" JNE L1 ADD DI.CONCATINATION OF THE STRING LEA SI.0AH MOV DX.INT 21H MOV AH.NEWLINE INT 21H MOV AH.09H LEA DX.STR11 INT 21H MOV AH.NEWLINE INT 21H .00 INC SI L1:INC SI CMP BYTE PTR[SI].d w ge ar e et k.n e MOV AH.NEWLINE INT 21H .09H LEA DX.INSTR2 MOV CX.INSTR1 LEA DI.INSTR2+2 INT 21H MOV AH.STR22 INT 21H ww . NEWLINE INT 21H MOV AH. INT 21 MOV AH."$" JNE L2 L8:DEC SI CMP SI.09H LEA DX.BYTE PTR[DI] MOV BYTE PTR[SI].09H LEA DX. MOV AH. BL INT 21H INC SI CMP BYTE PTR[SI].2 JNE L8 MOV AH.09H LEA DX.NEWLINE INT 21H ww . INSTR1+2 ."$" JNE L6 .4CH INT 21H Page 25 .n e L6: MOV BL.MOV BX.BL INC SI INC DI CMP BYTE PTR[DI].0 L2: MOV BL. 09H . LEA DX.d w ge ar e et k. BYTE PTR[SI] MOV AH.STR3 INT 21H MOV AH. 02H MOV DL. . 4 ascii digits. output: . org 100h jmp start ww . subroutine written in 8086 assembly language .d w ge ar e et k. to see results click "vars". packed_bcd call pack_to_bcd_and_binary ret . . (max of 4 ascii digit) to equivalent packed bcd digits. if the two memory locations contain characters ‘4’ and ‘5’ respectively. that can be used for converting a string of number . two bytes (word) to store 4 digits.n e string db '1234' . input parameters: . . start: lea bx. The BCD number should be left in the AL register. the program will output 0100 0101 in the AL register. return to operating system. bcd is binary coded decimal. this program does no screen output. which is stored in the memory as ASCII digits in two consecutive bytes. .address of source string (4 ascii digits). (6 Marks) Ans : name "convert" . di . this program uses a subroutine written in 8086 assembly language . bx . . For example. . into an equivalent packed BCD number. packed_bcd dw ? . Page 26 .CODE ENDS END START (b) Write a program in 8086 assembly language to convert a two digit number.must be set to address for packed bcd (2 bytes). (max of 4 ascii digit) to equivalent packed . that can be used for converting a string of number . bcd digits. string lea di. ah . move first digit to upper nibble: shl ah. point to 2 upper digits of packed bcd: .9) to digit we need . 1 . 0 . read 2 digits. reset packed bcd: mov word ptr [di]. next packed bcd: sub di. ah . 2 . store 2 digits: mov [di]. significant byte at lower address. xchg al.. 4 . . and ah. mask: 00001111b (0fh) next_digit: mov ax. 00001111b and al. to convert a char (0. loop only for 2 because every time we . next word (2 digits): add bx. [bx] .n e . read 2 digits (2 x 2 = 4 digits) mov cx.d w ge ar e et k. . 1 . to subtract 48 (30h) from its ascii code. or just clear the upper nibble of a byte. 2 loop next_digit popa ret pack_to_bcd_and_binary endp Page 27 ww . pack bcd: or ah. 8086 and all other Intel's microprocessors store less . al .pack_to_bcd_and_binary proc near pusha . 00001111b . (assumed that we have 4 digits) add di. printf("A Program to divide 89 by any number supplied\nPlease enter divisor:").(c) Write a simple subroutine that accepts a parameter value.d w ge ar e et k. if(flg==0) { printf("%d divided by %d =%f\n".flg.n e -------------- Page 28 . (6 Marks) Ans: /* ****************************************************************************** A simple subroutine thet accepts a parameter value and checks if the passed parameter value is Zero(0). exit(1). /* terminate Program*/ } else { return(0). /* continue execution*/ } } void main() { int i=89. If the value is ZERO the subroutines output a string “Divide Overflow” and terminates the execution.in. The subroutine checks if the passed parameter value is Zero (0). other wise it allows the calling program to continue.i. scanf("%d". otherwise it allows the calling program to continue ********************************************************************************/ #include<stdio.h> #include<stdlib.h> int chk_input(int in) { if(in==0) { printf("Divide Overflow\n"). flg=chk_input(in). If the value is ZERO the subroutine outputs a string "Divide Overflow" and terminates the execution.in. } } /* End of Program */ ww .&in).float(i/in)).