MC1310P.pdf

Order this document by MC13110A/DAdvance Information Universal Cordless Telephone Subsystem IC The MC13110A/B and MC13111A/B integrates several of the functions required for a cordless telephone into a single integrated circuit. This significantly reduces component count, board space requirements, external adjustments, and lowers overall costs. It is designed for use in both the handset and the base. • MC13110A and MC13111A: Fully Programmable in all Power Modes MC13110A/B MC13111A/B UNIVERSAL NARROWBAND FM RECEIVER INTEGRATED CIRCUIT • • • • • • • • MC13110B and MC13111B: MPU Clk Out and Second Local Oscillator are “Always On”. There is No Inactive Mode Dual Conversion FM Receiver – Complete Dual Conversion Receiver – Antenna Input to Audio Out 80 MHz Maximum Carrier Frequency – RSSI Output – Carrier Detect Output with Programmable Threshold – Comparator for Data Recovery – Operates with Either a Quad Coil or Ceramic Discriminator Compander – Expander Includes Mute, Digital Volume Control, Speaker Driver, Programmable Low Pass Filter, and Gain Block – Compressor Includes Mute, Programmable Low Pass Filter, Limiter, and Gain Block MC13110A/B only: Frequency Inversion Scrambler – Function Controlled via MPU Interface – Programmable Carrier Modulation Frequency Dual Universal Programmable PLL – Supports New 25 Channel U.S. Standard with No External Switches – Universal Design for Domestic and Foreign Cordless Telephone Standards – Digitally Controlled Via a Serial Interface Port – Receive Side Includes 1st LO VCO, Phase Detector, and 14–Bit Programmable Counter and 2nd LO with 12–Bit Counter – Transmit Section Contains Phase Detector and 14–Bit Counter – MPU Clock Outputs Eliminates Need for MPU Crystal Low Battery Detect – Provides Two Levels of Monitoring with Separate Outputs – Separate, Adjustable Trip Points 2.7 to 5.5 V Operation (15 µA Current Consumption in Inactive Mode) AN1575: Refer to this Application Note for a List of the “Worldwide Cordless Telephone Frequencies Simplified Block Diagram Rx In Rx PD In 1st LO Rx Phase Detector Tx Phase Detector Scrambler Compressor 2nd LO µP Serial Interface Expander 1st Mixer 2nd Mixer Limiting IF Amplifier RSSI Scrambler 52 1 FB SUFFIX PLASTIC PACKAGE CASE 848B (QFP–52) 48 1 FTA SUFFIX PLASTIC PACKAGE CASE 932 (LQFP–48) ORDERING INFORMATION Device MC13110AFB MC13110AFTA MC13110BFB MC13110BFTA MC13111AFB MC13111AFTA MC13111BFB MC13111BFTA TA = – 40° to +85°C Tested Operating Temperature Range Package QFP–52 LQFP–48 QFP–52 LQFP–48 QFP–52 LQFP–48 QFP–52 LQFP–48 2nd LO Detector MPU Clock Out RSSI Carrier Detect Out Data Out Rx PD Out Tx PD Out Tx Out Low Battery Detect Low Battery Indicator Rx Out SPI Tx In NOTE: = MC13110A/B Only This device contains 8262 active transistors. © Motorola, Inc. 1997 Rev 0 This document contains information on a new product. Specifications and information herein are subject to change without notice. MOTOROLA ANALOG IC DEVICE DATA 1 MC13110A/B MC13111A/B PIN CONNECTIONS QFP–52 33 SGnd RF 37 Mix1 Out 35 Mix2 Out 36 Gnd RF 28 Lim Out 38 Mix1 In2 29 VCC RF 39 Mix1 In1 31 Lim C1 30 Lim C2 34 Mix2 In 27 Q Coil Detector RSSI Scrambler LPF Rx Gain Adjust Rx Mute 2nd LO 6 b Prog SC Clk Ctr Expander E Out 46 Vol Control Ecap 47 E In 48 Scr Out 49 Ref 2 50 Ref1 51 VB 52 2nd LO 10.240 Rx Phase Detect 2nd LO 12 b Prog Ref Ctr ÷25 ÷4 ÷1 ALC Tx Mute Limiter LPF Compressor C Cap 1st LO 14 b Prog Rx Ctr Vref VB Reg 2.5 V 14 b Prog Tx Ctr Tx Phase Detect EN 10 Clk 11 4.129 kHz Bypass ÷2 ÷40 SC Filter Clock Scrambler Modulating Clock 4.129 kHz LPF Bypass 17 Tx Out Ref2 Ref1 µP Serial Interface Prog Clk Ctr Clk Out 12 CD Out 13 TxVCO 8 Data 9 Low Battery Detect Data Amp Carrier Detect 16 BD2 Out 15 DA Out 14 BD1 Out Tx Gain Adjust LPF AALPF 24 Rx Audio In 23 VCC Audio 22 DA In Mic Amp 21 Tx In 20 Amp Out 19 C In 18 C Cap 26 RSSI 25 Det Out 32 Lim In 1st Mix LO1In 40 LO1Out 41 V capCtrl 42 Gnd Audio 43 SA Out 44 SA In 45 Speaker Mute Speaker Amp 1st LO VCO 2nd Mix 2nd LO 1st LO IF Amp/ Limiter LO2 In 1 LO2 Out 2 Vag 3 Rx PD 4 PLL V ref 5 Tx PD 6 Gnd PLL 7 LQFP–48 34 Mix1 Out 32 Mix2 Out 33 Gnd RF 25 Lim Out 35 Mix1 In2 26 VCC RF 36 Mix1 In1 28 Lim C1 27 Lim C2 31 Mix2 In 29 Lim In 30 RSSI NOTE: = MC13110A/B Only 1st Mix LO1In 37 LO1Out 38 V capCtrl 39 Gnd Audio 40 SA Out 41 Speaker Mute SA In 42 E Out 43 Ecap 44 E In 45 Scr Out 46 VB 47 LO2In 48 2nd LO 12 b Prog Ref Ctr 2nd LO 10.240 1st LO ÷25 ÷4 ÷1 Rx Phase Detect Vol Control ALC Speaker Amp 1st LO VCO 2nd Mix 2nd LO 1st LO Rx Gain Adjust Rx Mute 2nd LO 6 b Prog SC Clk Ctr Scrambler LPF 4.129 kHz Bypass ÷2 ÷40 Tx Mute IF Amp/ Limiter RSSI Detector 24 Q Coil 23 Det Out LPF AALPF 22 Rx Audio In 21 VCC Audio SC Filter Clock Scrambler Modulating Clock 4.129 kHz LPF LPF Bypass 20 DA In Mic Amp 19 Tx In 18 Amp Out Tx Gain Adjust 17 C In 16 C Cap 15 Tx Out Expander Limiter Compressor C Cap 14 b Prog Rx Ctr Vref VB Reg 2.5 V 14 b Prog Tx Ctr Tx Phase Detect VCC Audio Programmable Low Battery Detect Data Amp 14 BD Out 13 DA Out µP Serial Interface Prog Clk Ctr Clk 10 CD Out 12 Clk Out 11 TxVCO 7 Data 8 EN 9 Carrier Detect LO2Out 1 Vag 2 Rx PD 3 PLL V ref 4 Tx PD 5 2 Gnd PLL 6 MOTOROLA ANALOG IC DEVICE DATA MC13110A/B MC13111A/B ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁ Characteristic Symbol VCC TJ Value Unit Vdc °C Power Supply Voltage Junction Temperature – 0.5 to +6.0 – 65 to +150 70 Maximum Power Dissipation, TA = 25°C PD mW NOTES: 1. Devices should not be operated at these limits. The “Recommended Operating Conditions” provide for actual device operation. 2. ESD data available upon request. MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS Characteristic Supply Voltage Operating Ambient Temperature Input Voltage Low (Data, Clk, EN) Input Voltage High (Data, Clk, EN) Bandgap Reference Voltage NOTE: 3. All limits are not necessarily functional concurrently. Symbol VCC TA VIL VIH VB Min 2.7 –40 – PLL Vref – 0.3 – Typ 3.6 – – – 1.5 Max 5.5 85 0.3 – – Unit Vdc °C V V V DC ELECTRICAL CHARACTERISTICS (VCC = 3.6 V, TA = 25°C, unless otherwise specified, IP3 = 0; Test Circuit Figure 1.) Characteristic Static Current Active Mode Receive Mode Standby Mode Inactive Mode [Note 4] Current Increase When IP3 = 1 (Active and Receive Modes) NOTE: Symbol ACT ICC Rx ICC STD ICC INACT ICC IIP3 Figure 1 Min 5.5 3.1 – – Typ 8.5 4.1 465 15 1.4 Max 10.5 5.3 560 30 1.8 Unit mA mA µA µA mA 1 – 4. MC13110B/MC13111B versions have no inactive mode. MOTOROLA ANALOG IC DEVICE DATA 3 with CFI Removed) Total Harmonic Distortion (Vin = 3. with CF1 Filter as Load) 1. TA = 25°C.4 112 48 48 – – – – – – – – 2.0 mVrms.0 150 – – dB dB % mVrms dB dB FIRST MIXER (No Modulation.4 –115 29 60 1.0 kHz.16 mVrms. fin = USA Ch21.5 V. 50 Ω Termination at Inputs) Input Impedance Single–Ended Differential – 16 16 Mix1 In1 or In2 Mix1 In1/In2 – Mix1 In1 or In2 Mix1 In1 or In2 Mix1 Out Mix1 Out Mix1 Out RPS1 CPS1 RPD1 CPD1 RP1 Out CP1 Out MXgain1 VO Mix1 1 dB – – – – – – – 1.4 –115 0. 21 22 Mix1 In1 or In2 Mix1 Out TOImix1 – – – – mVrms dBm Mix1 In1 or In2 Mix1 Out Mix1 BW – MHz 5. 21 – – – – 20 –21 56 –12 64 –11 178 –2.) Characteristic Figure Input Pin Measure Pin Symbol Min Typ Max Unit µVrms dBm FM RECEIVER (fRF = 46.0 mVrms. @ 1. 21 20. 30% AM. Third order intercept calculated for input levels 10 dB below 1.7 1.MC13110A/B MC13111A/B ELECTRICAL CHARACTERISTICS (VCC = 3.77 MHz [USA Ch 21].16 mVrms) AM Rejection Ratio (Vin = 3. 46. 18 19.6 V.6 3.77 MHz.2 –100 0.0 dB compression point.16 mVrms. VB = 1.0 13 – – – – – – – – – 19.0 kHz. fdev = ± 3. 21 20.0 dB IF Bandwidth NOTE: 14 17.0 mVrms. Matched Input. Test Circuit Figure 1.0 kHz) Signal to Noise Ratio (Vin = 3. with CF1 and CF2 Load) Isolation of First Mixer Output and Second Mixer Input (Vin = 1. 69 Mix1 In1/In2 Det Out VSIN – – – – – – 24 – – 80 30 – 2. 4 MOTOROLA ANALOG IC DEVICE DATA . Generator Referred First and Second Mixer Voltage Gain Total (Vin = 1. Matched Input.0 dB Voltage Compression Level (Input Referred) IP3 Bit Set to 0 IP3 Bit Set to 1 Third Order Intercept (Input Referred) [Note 5] IP3 Bit Set to 0 IP3 Bit Set to 1 –3. Active or Rx Mode. fmod = 1.2 V) Input Sensitivity (for 12 dB SINAD at Det Out Using C–Message Weighting Filter) 50 Ω Termination.16 mVrms) Recovered Audio (Vin = 3. Generator Referred Single–Ended. Vcap ctrl = 1.6 1.7 12 – – – – – – – Ω pF dB mVrms dBm kΩ pF Output Impedance Voltage Conversion Gain (Vin = 1. Generator Referred Differential. unless otherwise specified.8 300 3. No Modulation) 1 – 1 1 1 – Mix1 In1 or In2 Mix1 In1 or In2 Mix1 In1 or In2 Mix1 In1 or In2 Mix1 In1 or In2 Mix1 In1 or In2 Mix2 Out Mix2 In Det Out Det Out Det Out Det Out MXgainT Mix–Iso THD AFO AMR SNR 68. 2 to 1.0 dB Voltage Compression Level (Input Referred) IP3 Bit Set 0 IP3 Bit Set 1 Third Order Intercept (Input Referred) [Note 6] IP3 Bit Set 0 IP3 Bit Set 1 –3.1 20 – – – – – – – – – 32 –17 45 –14 – – – – mVrms dBm LIMITER/DEMODULATOR (fin = 455 kHz.9 V Carrier Detect Threshold Adjustment Range (Programmable through MPU Interface) Carrier Detect Threshold – Number of Programmable Levels NOTE: 56 56 57 Mix1 In Mix1 In Mix1 In RSSI RSSI CD Out RSSI DC RSSI VT – – – 80 0. CD = (10100) (Threshold Relative to Mix1 In Level) Output High Voltage CD = (00000). VB = 1.5 16 1.0 2. fmod = 1. 50 Ω Termination at Inputs) Input Impedance Output Impedance Voltage Conversion Gain (Vin = 1.) Characteristic Figure Input Pin Measure Pin Symbol Min Typ Max Unit kΩ pF kΩ pF dB mVrms dBm SECOND MIXER (No Modulation. RSSI = 0. 30 Mix2 In 28.5 V.6 1. Active or Rx Mode.02 –20 to 11 32 – – 0. RSSI = 0.6 V.0 3.0 dB Limiting Sensitivity ā 49 – 1 – Lim In – Lim In Lim In Lim In Det Out Det Out Det Out RPLim CPLim RO IF Sens BW – – – – – 1.6 0. fin = 10.0 mVrms. Test Circuit Figure 1.7 MHz. 30 29.MC13110A/B MC13111A/B ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.0 dB compression point. 27 Mix2 In – Mix2 In Mix2 In 28.2 V Output Low Voltage CD = (11111). TA = 25°C. fdev = ±3.0 dB IF Bandwidth 24 24 26. 30 31 Mix2 In Mix2 Out Mix2 BW Mix2 Out TOImix2 – – – – – 136 –4.0 kHz. MOTOROLA ANALOG IC DEVICE DATA 5 . 30 29.5 6.1 71 20 – – – 100 – Demodulator Bandwidth RSSI/CARRIER DETECT (No Modulation) RSSI Output Dynamic Range DC Voltage Range Carrier Detect Threshold CD Threshold Adjust = (10100) (Threshold Relative to Mix1 In Level) Hysteresis.8 3.5 15 – – – dB Vdc µVrms 57 1 1 126 126 Mix1 In RSSI RSSI – – CD Out CD Out CD Out – – Hys VOH VOL VT Range VTn – VCC – 0. with CF2 Filter as Load) 1.4 – – dB V V dB – 6.3 158 –3. Third order intercept calculated for input levels 10 dB below 1.0 kHz) Input Impedance Detector Output Impedance IF – 3.1 – – – 2. unless otherwise specified.5 – – – – – MHz kΩ pF kΩ µVrms kHz Mix2 In Mix2 Out Mix2 Out Mix2 Out RP2 In CP2 In RP2 Out CP2 Out MXgain2 VO Mix2 1 dB – – – – – 2. Active or Rx Mode.0 dB dB – – – 1 1 1 1. VB = 1. RL = 130 Ω 1.MC13110A/B MC13111A/B ELECTRICAL CHARACTERISTICS (continued) (VCC = 3. scrambler bypassed) Absolute Gain (Vin = – 20 dBV) Gain Tracking (Referenced to E Out for Vin = –20 dBV) Vin = – 30 dBV Vin = – 40 dBV Total Harmonic Distortion (Vin = – 20 dBV) Maximum Input Voltage (VCC = 2.0 to 10 20 –85 <–95 <–95 –14 to 16 16 – – – – –70 –60 3. 79 SA In SA Out VOmax 2.7 –11.779 – – – – – – – 600 75 7. Rfilt = 40 k (See Appendix B) Release Time Ecap = 0. Rfilt = 40 k (See Appendix B) Compressor to Expander Crosstalk Vin = –10 dBV. Vin = 4.4 Vpp RL = 130 Ω. V(E In) = AC Gnd Rx Muting (∆ Gain) Vin = –20 dBV.0 – – % dBV dBV –4.5 µF.5 0 –19 –38 1.0 13. Vin = 3. unless otherwise specified.6 V.0 kHz.6 3.4 –9. then measure output voltage) Input p Impedance p Attack Time Ecap = 0. Test Circuit Figure 1. TA = 25°C.0 – 1 SA In SA Out Msp – 3.5 µF.0%. C–Message Weighting (Input AC–Grounded) Volume Control Adjust Range Volume Control – Number of Programmable Levels SPEAKER AMP/SP MUTE (Active Mode) Maximum Output Swing RL = No Load. 76 76 1 Rx Audio In Rx Audio In E In SA Out – E Out THD – VOmax – – –2.879 0.0 –20 –40 0.8 2.0 0 4.8 Vpp RL = 620 Ω.5 3.4 –92 – – – –60 dB Vpp 1.5 –90 –84 3. 73 125 125 70 Rx Audio In E In I E In E In C In Rx Audio In Rx Audio In Rx Audio In Rx Audio In Rx Audio In Rx Audio In – E Out E Out E Out E Out Scr Out Scr Out Scr Out Scr Out Scr Out E Out SA Out E Out E Out Zin ta tr CT Me Rx fch Ripple Rx Range Rx n EN – – – – – – 3.5 V. Active Mode. Rx Gain Adj = (01111) Rx High Frequency Corner Rx Path.2 2.979 0.) Characteristic Figure Input Pin Measure Pin Symbol Min Typ Max Unit Rx AUDIO PATH (fin = 1. V Rx Audio In = –20 dBV Low Pass Filter Passband Ripple (Vin = –20 dBV) Rx Gain Adjust Range (Programmable through MPU Interface) Rx Gain Adjust Steps – Number of Programmable Levels Audio Path Noise.7 V) Maximum Output Voltage (Increase input voltage until output voltage THD = 5.0 Vpp Speaker Amp Muting Vin = –20 dBV. Vin = 2.6 – – – – – – kΩ ms ms dB dB kHz dB dB dB dBV 123 123 E In E In Vcn Range Vcn dB – 6 MOTOROLA ANALOG IC DEVICE DATA . 72 1. 76 Rx Audio In E In SA Out E Out G Gt –21 –42 1. 0 kHz. Rfilt = 40 k (See Appendix B)) Expander to Compressor Crosstalk (Vin = –20 dBV.25 – – – –40 –60 –8.5 µF. Limiter.6 V.0 V.5 dBv ALC Input Dynamic Range Limiter Output Level (Vin = – 2. unless otherwise specified.6 0. V(C In) = AC Gnd) Tx Muting (Vin – 10 dBV) ALC Output Level (ALC enabled) Vin = –10 dBV Vin = –2.8 0 –9. scrambler bypassed) Absolute Gain (Vin = –10 dBV) 1.4 – mV V kΩ kΩ V V kHz Figure Input Pin Measure Pin Symbol Min Typ Max Unit MIC AMP (fin = 1.1 10 50 – 280 – – 0.0 3. Active or Rx Mode.5 dBV.7 250 100 3. 87 1 Tx In Tx In Tx Out Tx Out THD VOmax – –2. IOL = 0 mA Maximum Frequency 1 – 1 – 1 1 – DA In DA In – – DA In DA In DA In DA Out DA Out DA In DA Out DA Out DA Out DA Out Hys VT ZI ZO VOH VOL Fmax 30 – 200 – VCC – 0.000 100 3. External resistors set to gain of 1.0 –13 1.5 –60 –88 –13 –11 0.0 –6. 83 Tx In Tx Out G –4.5 –8.5 dBV ALC Slope (ALC enabled) Vin = –10 dBv Vin = –2. If other 2nd LO frequencies and/or SC filter counter divider ratios are used.4 V.2 – – – V/V kHz Vpp Tx AUDIO PATH (fin = 1. then measure output voltage.0 13. IOH = 0 mA Output Low Voltage Vin = VCC – 0. Test Circuit Figure 1. VB = 1.7 – – 3.0%. 87. Tx Gain Adjust = 8 dB) Input Impedance Attack Time (Ccap = 0.) Characteristic DATA AMP COMPARATOR Hysteresis Threshold Voltage Input Impedance Output Impedance Output High Voltage Vin = VCC – 1. Active Mode) Open Loop Gain Gain Bandwidth Maximum Output Swing (RL = 10 kΩ) – – – Tx In Tx In Tx In Amp Out Amp Out Amp Out AVOL GBW VOmax – – – 100.24 MHz 2nd LO. The filter specification is based on a 10.0 % dBV – – – 1 1 1. and a switched–capacitor (SC) filter counter divider ratio of 31.0 0. ALC. 90 1 – C In C In E In Tx In Tx In C In Tx Out Tx Out Tx Out Tx Out Tx Out Zin ta tr CT Mc ALCout – – – – – –15 –13 10 3.1 – – 42 VCC – 0. and Mutes Disabled. the filter corner frequency will be proportional to the resulting SC filter clock frequency. Limiter enabled) Tx High Frequency Corner [Note 7] (VTx In = –10 dBV. Speaker Amp No Load. Tx Gain Adj = (01111).8 dBV dBV kHz 7.6 –16 to –2.5 µF.MC13110A/B MC13111A/B ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.0 Gain Tracking (Referenced to Tx Out for Vin = –10 dBV) Vin = – 30 dBV Vin = – 40 dBV Total Harmonic Distortion (Vin = – 10 dBV) Maximum Output Voltage (Increase input voltage until output voltage THD = 5.8 – 1. 87 Tx In Tx Out Gt –11 –17 –10 –15 0.0 kHz. TA = 25°C.0 0 4. MOTOROLA ANALOG IC DEVICE DATA 7 . Rfilt = 40 k (See Appendix B)) Release Time (Ccap = 0.1 dB/dB – 1 1 C In Tx In Tx In Tx Out Tx Out Tx Out DR Vlim Tx fc – –10 3. Active Mode.4 kΩ ms ms dB dB dBV Tx In Tx Out Slope p 0. Mic Amp = Unity Gain) NOTE: dB dB 1.5 V. 0 kHz.525 V – 1 1 Hys Iin VOH – –50 VCC – 0.0 µF from Tx Out to Rx Audio In Baseband Breakthrough Rx + Tx Path – 1.0 kHz. f = 479 Hz.7 1. the filter corner frequency will be proportional to the resulting SC filter clock frequency.192 kHz LOW BATTERY DETECT Average Threshold Voltage Before Electronic Adjustment (Vref_Adj = (0111)) Average Threshold Voltage After Electronic Adjustment (Vref_Adj = (adjusted value)) Hysteresis Input Current (Vin = 1.24 MHz 2nd LO. scrambler bypassed) Low Pass Filter Passband Ripple (Vin = –10 dBV) 1. and Mutes Disabled. Tx Gain Adj = (01111). 8 MOTOROLA ANALOG IC DEVICE DATA .4 –1. and a switch–capacitor (SC) filter counter divider ratio of 31. V Tx In = –10 dBV. unless otherwise specified.58 V 1 VTf 1.0 4.475 1.5 V.55 3. Active Mode.0 to 10 20 – – – dB dB dB – Rx AND Tx SCRAMBLER (2nd LO = 10. 131 Ref1 Ref2 Ref1 Ref2 Ref1 Ref2 – Ref1 Ref2 BD1 Out BD2 Out BD1 Out BD2 Out BD1 Out BD2 Out Ref1 Ref2 BD1 Out BD2 Out VTi 1. Rx Gain Adj = (01111).0 V) NOTE: – – Rx Audio In Tx In Scr Out Tx Out Rx fch Tx fch 3. Mic Amp = Unity Gain Absolute Gain Rx: Vin = –20 dBV Tx: Vin = –10 dBV.0 – 0.) Characteristic Figure Input Pin Measure Pin Symbol Min Typ Max Unit Tx AUDIO PATH (fin = 1. SCF Clock Divider = 31.5 1.139 kHz ms E Out E Out E Out GD GD CBT – – – 1.0 – 3.65 3.0 µF from Tx Out to Rx Audio In.0 2.0 4.24 MHz. Limiter disabled Pass Band Ripple Rx + Tx Path – 1. If other 2nd LO frequencies and/or SC filter counter divider ratios are used.1 4.879 3. Tx Gain Adj = (01111). fin = 1. Test Circuit Figure 1.929 kHz kHz AV – – – Rx Audio In Tx In C In E Out Tx Out E Out Ripple –4.129 4.0 –4.0 V) Output High Voltage (Vin = 2.0 µF from Tx Out to Rx Audio In. Total is divide by 62 for SCF clock frequency of 165. Limiter.0 kHz Rx Audio In. fin = low corner frequency to high corner frequency Carrier Breakthrough Rx + Tx Path – 1. fin = 1.9 4.0 µF from Tx Out to . f = 300 Hz.0 and 2. The filter specification is based on a 10. ALC. 84 Tx In Tx Out Ripple – 0.MC13110A/B MC13111A/B ELECTRICAL CHARACTERISTICS (continued) (VCC = 3.829 3. Active or Rx Mode. VB = 1.38 1.0 1.48 1.0 –60 – – – dB – C In E Out BBT – –50 – dB 1. V Rx Audio In = –20 dBV Tx High Frequency Corner (Note 8) Tx Path.6 – 50 – mV nA V 8.75 3.16 kHz) Rx High Frequency Corner (Note 8) Rx Path.119 4.6 V. fmeas = 3. Volume Control = (0 dB Default Levels). TA = 25°C.2 Maximum Compressor Gain (Vin = –70 dBV) Tx Gain Adjust Range (Programmable through MPU Interface) Tx Gain Adjust Steps – Number of Programmable Levels – 125 125 C In C In C In Tx Out Tx Out Tx Out AVmax Tx Range Tx n – – – 23 –9. fin = low corner frequency to high corner frequency Scrambler Modulation Frequency Rx: 100 mV (–20 dBV) Tx: 316 mV (–10 dBV) Group Delay Rx + Tx Path – 1.5 dB dB fmod – – – – – Rx Audio In C In C In C In C In E Out Tx Out 4. 5 V) Output Sink Current (VPD = Gnd + 0.0 – – – – – – – – – – 0.) Characteristic LOW BATTERY DETECT Output Low Voltage (Vin = 1. Clk. Clk Data.134 2.442 3.4 – –20 2.034 2. VB = 1.4 1.381 3.970 2. 128 VCC Audio BD2 Out IBS7 IBS6 IBS5 IBS4 IBS3 IBS2 IBS1 3.2 0.0 mA) MICROPROCESSOR SERIAL INTERFACE Input Current Low (Vin = 0. after Vref Adjustment) Line Regulation (IL = 0 mA. EN – – EN.862 3. Standby Mode) Input Current High (Vin = 3.5 V to PLL Vref – 0.370 3.922 V 1 Ref1 Ref2 BD1 Out BD2 Out VOL – 0. Clk EN. EN Data.Clk.6 40 – V mV mV – – – LO2 In – – – LO2 In LO2 Out Tx VCO f2ext f2ext ftxmax – – – 12 12 80 – – – MHz MHz MHz – – – – Rx PD Tx PD Rx PD Tx PD IOH IOL – – 1.0 2.5 V) PLL LOOP CHARACTERISTICS Maximum 2nd LO Frequency (No Crystal) Maximum 2nd LO Frequency (With Crystal) Maximum Tx VCO (Input Frequency).0 – – – – – – – – – µA µA V MHz pF ns ns ns ns ns µs 1 1 1 – VCC Audio VCC Audio PLL Vref PLL Vref PLL Vref VO VRegLine VReg Load 2. Clk.5 V) Load Regulation (IL = 1.8 –1.5 V. EN – – – – – – Data.3 V.6 V.MC13110A/B MC13111A/B ELECTRICAL CHARACTERISTICS (continued) (VCC = 3. Clk. EN) 1 1 – – – 106 105 105 106 – 108 – – – Data.948 2.217 3. EN.5 11.4 2.287 3.455 3. unless otherwise specified.0 V) BATTERY DETECT INTERNAL THRESHOLD After Electronic Adjustment of VB Voltage BD Select = (111) BD Select = (110) BD Select = (101) BD Select = (100) BD Select = (011) BD Select = (010) BD Select = (001) PLL PHASE DETECTOR Output Source Current (VPD = Gnd + 0.4 V Figure Input Pin Measure Pin Symbol Min Typ Max Unit MOTOROLA ANALOG IC DEVICE DATA 9 . Clk EN. Clk Data. EN Data.270 3.886 2.0 1.357 3.802 3.6 1.202 3.010 2. Test Circuit Figure 1.3 V. TA = 25°C. VCC = 3.0 8.0 200 100 90 90 100 100 – 5.529 3.298 3. Clk Data.0 – – mA mA 1.0 to 5. Vin = 200 mVpp PLL VOLTAGE REGULATOR Regulated Output Level (IL = 0 mA.098 3. Active or Rx Mode. Clk – IIL IIH Vhys – Cin tsuEC tsuDC th trec tw tpuMPU –5.5 V to PLL Vref – 0. Standby Mode) Hysteresis Voltage Maximum Clock Frequency Input Capacitance EN to Clk Setup Time Data to Clk Setup Time Hold Time Recovery Time Input Pulse Width MPU Interface Power–Up Delay (90% of PLL Vref to Data. Clk. 0 k 1 0.5 k E In Scr Out Vref1 BD2 Out Data Out BD1 Out 8 9 10 11 12 13 100 k VCC 100 k Carrier Detect Out Vref2 22.1 Mic Amp Out C In SA Out 0.1 VCC Audio 10 µF 0.2 10 µ F 0.1 MPU Clock Output 4700 32.1 46 MC13110A/B MC13111A/B IC 44 49.1 0.1 DA In Tx In 49.1 49.0 µF MC13110A/B MC13111A/B 7.01 Tx VCO 1.0 µF 2 3 4 0.5 k 0.9 0.0 k 52 0.7 MHz To VCC VCC CF2 455 kHz RF In 0.9 k 22 21 20 19 18 17 16 15 14 5 6 7 0.1 1.9 k 0.1 MOTOROLA ANALOG IC DEVICE DATA Rx Loop Filter NOTE: This schematic is only a partial representation of the actual production test circuit.1 49.5 k 0.1 k 0.1 VCCA V 100 k CC Tx Out 1.01 15 k 0.01 10 µF 22. then capacitor value = pF If <1.1 49.0 – 50 10.4 k 0.01 k 5.01 332 CF1 10.1 0.Mix 1 In1 Q Coil Lim In Lim C1 Lim C2 Mix2 In VCC RF Mix 1 In2 Mix 1Out Gnd RF 110 41 25 42 V Cap Ctrl Gnd Audio SA Out SA In E Out E Cap E In Scr Out Ref2 Ref1 Rx PD PLL Vref LO2 In LO2 Out Tx VCO VB Vag Tx PD Gnd PLL Data DA In Tx In Amp Out C In C Cap Tx Out BD 2 Out DA Out BD 1 Out EN Clk CD Out Clk Out VCC Audio Rx Audio In LO1 Out Det Out 40 26 SGnd RF 10 µ F LO1 In RSSI Mix2 Out Lim Out 10 Figure 1.1 10 L2 0.0 µF 7.1 k 0.1 0. then capacitor value = µ F Det Out 1000 Rx Audio In L3 33 39 38 37 36 35 34 33 32 31 30 29 28 27 0.1 Legend: If ≥1. .9 k 45 VCCA 47 48 49 50 51 1.9 k 43 24 23 SA In E Out 1. Production Test Circuit (52 Pin QFP) 0.1 1.047 3.240 MHz 8.1 0. 0 MHz. Tx PD This pin is a tri–state voltage output of the Rx and Tx Phase Detector. This pin also functions as the test mode input for the counter tests.1 µF capacitor. 8 1. An internal voltage regulator provides a stable power supply voltage for the Rx and Tx PLL’s and can also be used as a regulated supply voltage for other IC’s.ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ PIN FUNCTION DESCRIPTION Pin LQFP–48 48 1 QFP–52 1 2 Symbol/ Type LO2 In LO2 Out E i l Equivalent I Internal l Ci Circuit i (52 Pi Pin QFP) PLL Vref MC13110A/B MC13111A/B D Description i i 1 100 LO2 In PLL Vref PLL Vref These pins form the PLL reference oscillator when connected to an external parallel–resonant crystal (10. “low”.0 mA externally. This pin drives the external Rx and Tx PLL loop filters. PLL Vref PLL Vref Tx VCO is the transmit divide counter input which is driven by an ac–coupled external transmit loop VCO. This pin must be decoupled with a 0.0 pF.” depending on the phase difference of the phase detector input signals.0 mA. During lock. When the IC is set to the inactive mode.0 k TX VCO MOTOROLA ANALOG IC DEVICE DATA 11 . The reference oscillator is also the second Local Oscillator (LO2) for the RF receiver. “LO2 In” may also serve as an input for an externally generated reference signal which is typically ac–coupled. 4 5 PLL Vref VCC Audio 5 PLL Vref 132 k PLL Vref is a PLL voltage regulator output pin. 100 2 LO2 Out 2 3 Vag VCC Audio PLL Vref Vag is the internal reference voltage for the switched capacitor filter section. 5 6 Tx PD (Output) Rx PD. It is either “high”. 6 7 7 8 Gnd PLL Tx VCO (Input) Ground pin for digital PLL section of IC. It can source up to 1. PLL Vref is pulled up to VCC audio for the standby and inactive modes (Note 1). The input capacitance to ground at each pin (LO2 In/ LO2 Out) is 3. Rx and Tx PD outputs can sink or source 1. LO2 In is internally pulled low to disable the oscillator. 3 30 k Vag 3 4 Rx PD (Output) PLL Vref PLL Vref 15 4 6 4. The minimum signal level is 200 mVpp @ 60. or “high impedance. Proper supply filtering is a must on this pin.24 MHz typical). very narrow pulses with a frequency equal to the reference frequency are present. 5.ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ MC13110A/B MC13111A/B PIN FUNCTION DESCRIPTION (continued) Pin LQFP–48 8 9 10 QFP–52 9 10 11 Symbol/ Type Data EN Clk (Input) Equivalent Internal Circuit (52 Pin QFP) VCC Audio PLL Vref Description 9.0 µA Microprocessor serial interface input pins are for programming various counters and control functions. 100 k 15 DA Out 15 17 Tx Out (Output) VCC Audio 17 Tx Out is the Tx path audio output. 11 12 Clk Out (Output) VCC Audio VCC Audio 1. 1) For the MC13110A/B and MC13111A/B the Clk Out can be disabled via the MPU interface. 13 240 CD Out Hardware Interrupt 2) Hardware interrupt input which can be used to “wake–up” from the Inactive Mode. The switching thresholds are referenced to PLL Vref and Gnd PLL. These pins have 1. This output also functions as the output for the counter test modes. 11 240 Data. 2) For the MC13110B and MC13111B this output is always active (on) (Note 2). Tx gain and mute are programmable through the MPU interface. The driver has an internal resistor in series with the output which can be combined with an external capacitor to form a low pass filter to reduce radiated noise on the PCB. 14 16 BD2 Out (Output) BD1 Out BD2 Out Low battery detect output #2 is an open collector with external pull–up resistor. 10. 12 13 CD Out (I/O) VCC Audio PLL Vref 1) Carrier detect output (open collector with external 100 kΩ pull–up resistor. EN. Dual function pin. The inputs operate up to VCC. CD Comparator – 14 BD1 Out VCC Audio Low battery detect output #1 is an open collector with external pull–up resistor.0 k 12 Clk Out The microprocessor clock output is derived from the 2nd LO crystal oscillator and a programmable divider with divide ratios of 2 to 312.0 kHz. 14 16 14. 13 15 DA Out (Output) VCC Audio VCC Audio Data amplifier output (open collector with internal 100 kΩ pull–up resistor). Tx Out VB 12 MOTOROLA ANALOG IC DEVICE DATA .0 µA internal pull–down currents. This pin is sensitive to load capacitance. Internally this pin has a low–pass filter circuitry with –3 dB bandwidth of 4. It can be used to drive a microprocessor and thereby reduce the number of crystals required in the system design. Clk 1. It is necessary to adequately filter this pin. This pin is dc–coupled from the FM detector and has an output impedance of 1100 Ω. The data amplifier input (DA In) resistance is 250 kΩ and must be ac–coupled. This pin is internally biased and has an input impedance of 12. An external resistor is connected to this pin to set the Mic Amp gain and input impedance. too.0 µF.5 k C In VB 18 20 Amp Out (Output) VCC Audio VCC Audio Microphone amplifier output. 20 22 DA In (Input) VCC Audio VCC Audio 250 k 250 k 22 DA In 21 22 23 24 VCC Audio VCC audio is the supply for the audio section.47 µF is the recommended value. 240 25 30 µA Det Out MOTOROLA ANALOG IC DEVICE DATA 13 . 19 12. Tx In must be ac–coupled. C In must be ac–coupled. 0. A practical capacitor range is 0. Rx Audio In (Input) VCC Audio The Rx audio input resistance is 600 kΩ and must be ac–coupled.ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ MC13110A/B MC13111A/B PIN FUNCTION DESCRIPTION (continued) Pin LQFP–48 16 QFP–52 18 Symbol/ Type C Cap Equivalent Internal Circuit (52 Pin QFP) VCC Audio VCC Audio Description 40 k 18 C Cap is the compressor rectifier filter capacitor pin. Hysteresis is internally provided.1 to 1. The feedback resistor should be less than 200 kΩ. 21 19 21 Tx In (Input) 20 Tx In Amp Out VB Tx In is the Tx path input to the microphone amplifier (Mic Amp).5 k. The gain is set with external resistors. 24 600 k Rx Audio In VB 23 25 Det Out (Output) VCC RF VCC Audio Det Out is the audio output from the FM detector. It is recommended that an external filter capacitor to VCC audio be used. C Cap 17 19 C In (Input) VCC Audio C In is the compressor input. 0 k 34 Mix2 In is the second mixer input. A coupling capacitor connects this pin to the quad coil or ceramic discriminator as part of the FM demodulator circuit.5 kΩ at 455 kHz. The input impedance is 2. demodulator).1 µF. 27 Q Coil 26 29 VCC RF VCC supply for RF receiver section (1st LO. 25 28 Lim Out VCC VCC VCC RF RF RF 53. IF amplifier/limiter capacitor pins. 26 RSSI 186 k 24 27 Q Coil VCC RF VCC RF A quad coil or ceramic discriminator connects this pin as part of the FM demodulator circuit. They determine the IF limiter gain and low frequency bandwidth. Proper supply filtering is needed on this pin too. Signals are to be ac–coupled to this pin.ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ MC13110A/B MC13111A/B PIN FUNCTION DESCRIPTION (continued) Pin LQFP–48 30 QFP–52 26 Symbol/ Type RSSI Equivalent Internal Circuit (52 Pin QFP) VCC RF Description VCC RF VCC Audio RSSI is the receive signal strength indicator.1 µF. which is biased internally to VCC RF. limiter. DC–couple this pin to VCC RF through the quad coil or the external resistor. These decoupling capacitors should be 0. Lim Out 1. The input impedance can be reduced by connecting an external resistor to VCC RF. This pin is not connected internally but should be grounded to reduce potential coupling between pins.5 k 30 Lim C2 52 k 29 32 Lim In (Input) Signal input for IF amplifier/limiter.8 kΩ at 455 kHz. This pin must be filtered through a capacitor to ground. Mix2 In 14 MOTOROLA ANALOG IC DEVICE DATA . This pin can drive coupling capacitors up to 47 pF with no deterioration in performance. An external R to ground shifts the RSSI voltage.01 to 0. mixer. The input impedance is 1. Signals should be ac–coupled to this pin.5 k VCC RF 31 27 28 30 31 Lim C2 Lim C1 Lim C1 32 Lim In 28 A quad coil or ceramic discriminator are connected to these pins as part of the FM demodulator circuit. – 33 SGnd RF 31 34 Mix2 In (Input) VCC RF VCC RF 3. This is also the input to the Carrier Detect comparator. The capacitance value range should be 0. 5 kΩ. The oscillator is useable up to 80 MHz. Vcap Ctrl 40 41 43 44 Gnd Audio SA Out (Output) Ground for audio section of the IC. 1. It should be less than 200 kΩ.0 mA. This will set the gain and input impedance and must be ac–coupled. The voltage at this pin is referenced to Gnd Audio and varies the capacitance between LO1 In and LO2 Out. The single–ended and differential input impedance are about 1. Mix1 Out (Output) VCC RF VCC RF The first mixer has a 3 dB IF bandwidth of 13 MHz and an output impedance of 300 Ω. The output current drive is 300 µA and can be programmed for 1.5 MHz and an output impedance of 1.8 kΩ at 46 MHz. 200 37 Mix1 Out 35 38 Mix1 In2 (Input) Vref VCC RF 20 k VCC RF Signals should be ac–coupled to this pin. The speaker amplifier can be muted through the MPU interface.6 V.6 and 1. Mix1 In1 37 38 40 41 LO1 In LO1 Out Tank Elements. 41 40 LO1 Out LO1 In 39 42 Vcap Ctrl VCC RF 55 k 42 Vcap Ctrl is the 1st LO varactor control pin. 42 45 SA In (Input) SA In I SA Out VB MOTOROLA ANALOG IC DEVICE DATA 15 . 39 Mix1 In2. respectively.ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ MC13110A/B MC13111A/B PIN FUNCTION DESCRIPTION (continued) Pin LQFP–48 32 QFP–52 35 Symbol/ Type Equivalent Internal Circuit (52 Pin QFP) VCC RF VCC RF Description Mix2 Out (Output) Mix2 Out is the second mixer output. An external resistor is connected to the speaker amplifier input (SA In). an internal varactor and capacitor matrix for 1st LO multivibrator oscillator are connected to these pins. 950 950 36 39 Mix1 In1 (Input) 38.2 k 35 Mix2 Out 33 34 36 37 Gnd RF Ground pin for RF section of the IC. The output current drive is 50 µA. An increase in voltage will decrease capacitance. The second mixer has a 3 dB bandwidth of 2. which is biased internally to VCC – 1. VCC Audio VCC Audio 45 44 The speaker amplifier gain is set with an external feedback resistor. A typical capacitor range of 0. 50.5 to 10 µF is recommended. It is important to keep this capacitor value equal to the PLL Vref capacitor due to logic timing (Note 9). NOTE: 9. 46 E Out VB 44 47 E Cap VCC Audio VCC Audio 40 k 47 E Cap is the expander rectifier filter capacitor pin.1 to 1.0 µF. 47 52 VB VCC Audio VCC Audio 240 52 VB VB is the internal half supply analog ground reference. E Cap 45 48 E In (Input) VCC Audio The expander input pin is internally biased and has input impedance of 30 kΩ. An additional high quality parallel capacitor of 0. 51 – 51 Ref1 Ref2. The capacitor value should be the same used on the VB pin (Pin 52). Ref1 Reference voltage input for Low Battery Detect #1. Connect an external filter capacitor between VCC audio and E Cap. 48 30 k E In VB 46 49 Scr Out (Output) VCC Audio Scr Out is the Rx audio output. 49 Scr Out VB – 50 Ref2 VCC Audio Reference voltage input for Low Battery Detect #2. 16 MOTOROLA ANALOG IC DEVICE DATA . The recommended capacitance range is 0.01 µF is essential to filter out spikes originating from the PLL logic circuitry.47 µF is the suggested value.5 to 10 µF is desired to reduce crosstalk and noise. 0. This pin must be filtered with a capacitor to ground.ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ MC13110A/B MC13111A/B PIN FUNCTION DESCRIPTION (continued) Pin LQFP–48 43 QFP–52 46 Symbol/ Type E Out (Output) Equivalent Internal Circuit (52 Pin QFP) VCC Audio Description The output level of the expander output is determined by the volume control. Volume control is programmable through the MPU interface.0 kHz. An internal low pass filter has a –3 dB bandwidth of 4. A capacitor range of 0. VB.367 3. This device contains a first and second mixer. the tolerance of the internal reference voltage can be improved to ±1.371 3. It is essential to keep the external reference pins above Gnd to prevent any possible power–on reset to be activated.0 8.457 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Battery Detect Select 0 1 2 3 4 5 6 7 Hysteresis (mV) – 4. low battery detect.0 6. Alternately.861 2. Receive.MC13110A/B MC13111A/B DEVICE DESCRIPTION AND APPLICATION INFORMATION The following text.285 3. By no means is the user to assume that the data following is a guaranteed parametric.291 3.5% through MPU serial interface programming (refer to the Serial Interface section. the Ref 1 and Ref 2 pins become the comparators reference. a high at VCC Audio will yield a high at the battery detect output.461 Ramping Down (V) – 2. For the 52 pin package option.031 3. When considering the non–programmable mode (bits set to <000>) for the 52 pin package. It is important to note that the forgoing data and information was from a limited number of units. Figure 128 describes this operation (refer to the Serial Interface section under Clock Divider Register). receive and transmit baseband processing.0 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ NOTE: 10. Since the internal comparator used is non–inverting. The internal reference can be measured directly at the “VB” pin. demodulator.5 V) Ramping Up (V) – 2. tables and schematics are provided to the user as a source of valuable technical information about the Universal Cordless Telephone IC. and vice versa for VCC Audio set to a low level. Refer to the Pin Function Description table for the simplified internal circuit schematic and description of this device. dual programmable PLL. The voltage reference register value should be stored in ROM during final test so that it can be reloaded each time the combo IC is powered up.375 3.0 6.039 3.199 3. Figure 2.5 V reference voltage (VB). Standby. Internal Low Battery Detect Levels (with VB = 1. graphics.950 3. and serial interface for microprocessor control. extended range receive signal strength (RSSI).207 3. An internal switch is activated when the non–programmable mode is chosen connecting Ref 1 and Ref 2. The voltages on the internal divider network are compared to the Internal Reference Voltage. General Circuit Description The MC13110A/B and MC13111A/B are a low power dual conversion narrowband FM receiver designed for applications up to 80 MHz carrier frequency. limiter. but has other applications such as low data rate narrowband data links and as a backend device for 900 MHz systems where baseband analog processing is required.947 3.0 8.453 Average (V) – 2. The reference for the internal divider network is VCC Audio. the VB internal reference voltage is measured. The relationship of additional current draw due to IP3 bit set to <1> and supply voltage are shown in Figures 9 and 10. The bits are set through the SCF Clock Divider Register as shown in Figures 108 and 126. This device is primarily designated to be used for the 49 MHz cordless phone (CT–0).0 8. the internal reference voltage value is adjusted electronically through the MPU serial interface to achieve the desired accuracy level. two external precision resistor dividers are used to set independent thresholds for two battery detect hysteresis comparators. This information originates from thorough evaluation of the device performance for the US and French applications. Here. the Ref 1 and Ref 2 pins need to be tied to VCC when used in the programmable mode. MOTOROLA ANALOG IC DEVICE DATA 17 . Figure 12 indicates that the VB voltage is fairly flat over temperature. The voltages on Ref 1 and Ref 2 are again compared to the internally generated 1.953 3.0 8. Battery Detect Select 0 is the non–programmable operating mode. This data was obtained by using units from typical wafer lots. During final test of the telephone. generated by an internal source. Then. Figure 131). The battery detect levels will depend on the accuracy of the VB voltage. Note that the 48 pin package can only be used in the programmable mode. The Low Battery Detect threshold tolerance can be improved by adjusting a trim–pot in the external resistor divider (user designed). the user has the option to operate the IC in the programmable or non–programmable modes.864 2. Figures 7 and 8 show the typical behavior of current consumption in relation to temperature. DC Current and Battery Detect Figures 3 through 6 are the current consumption for Inactive. Only the minimum and maximum limits identified in the electrical characteristics tables found earlier in this spec are guaranteed. The Low Battery Detect outputs are open collector.035 3. For the Low Battery Detect.288 3.0%. In the programmable mode several different internal threshold levels are available (Figure 2). The FM receiver can also be used with either a quadrature coil or ceramic resonator. The initial tolerance of the internal reference voltage (VB) is ±6.867 2.204 3. and Active modes versus supply voltages. 1 7.7 7.3 4.1 4.1 5.5 0.4 7.3 4.5 1. SUPPLY VOLTAGE (V) VCC.2 7.7 4.9 4.0 2.9 4.5 MCU Clock Out Off MCU Clock Out On 8.3 7.1 5.9 7.1 3.2 0.8 7.5 3.5 VCC.7 3.4 0.7 5.6 0. TEMPERATURE (°C) TA. SUPPLY CURRENT (mA) Rx ICC. SUPPLY CURRENT (µ A) 35 30 25 20 15 10 5.7 5. MCU Clock Output – On at 2.0 0 2. Current versus Supply Voltage Active Mode MCU Clock Out On MCU Clock Out Off 3.5 VCC. SUPPLY CURRENT (mA) 4.0 0 –2.8 0.3 4.0 –4.9 4.6 7.0 2.1 3.1 0 2.0 –8. SUPPLY VOLTAGE (V) Figure 7.1 3.9 4.7 MCU Clock Out Off MCU Clock Out On Figure 4.5 7.3 0. SUPPLY CURRENT (mA) 40 I INACT IC.5 3.1 5.1 3.048 MHz 3.2 4.0 –6.0 0 –5.4 4.7 0. SUPPLY VOLTAGE (V) VCC. TEMPERATURE (°C) 18 MOTOROLA ANALOG IC DEVICE DATA .5 3.0 –10 –40 –30 –20 –10 Standby ° ° 6.0 0. SUPPLY VOLTAGE (V) Figure 5. Current versus Supply Voltage Receive Mode 5. Current versus Temperature Normalized to 25°C DELTA CURRENT DRAIN (% FROM 25 C) DELTA CURRENT DRAIN (% FROM 25 C) 15 10 5.7 3.0 4. Current versus Supply Voltage Inactive Mode STD ICC.3 4.8 4.5 3.MC13110A/B MC13111A/B DC CURRENT Figure 3. Current versus Temperature Normalized to 25°C Receive Active Inactive 0 10 20 30 40 50 60 70 80 90 –12 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 TA. Current versus Supply Voltage Standby Mode.7 5.9 0.1 5.6 4.5 4.0 2.0 ACT I CC .9 4.3 4.0 7.0 –10 Figure 8.7 5.7 Figure 6. 5000 1.7 2.50 10 5 0 –5 –10 –15 –20 –40 –30 –20 –10 Figure 10.5050 1. SUPPLY CURRENT (mA) Vs . Additional Supply Current Consumption versus Supply Voltage. TEMPERATURE (°C) Figure 11. NORMALIZED VB VOLTAGE (V) 750 700 650 600 550 500 450 400 350 300 1.MC13110A/B MC13111A/B DC CURRENT Figure 9.3 5. TEMPERATURE (°C) MOTOROLA ANALOG IC DEVICE DATA 19 .5075 1.5 V at 25°C 1. IP3 = <1> 1.9 5.7 4.3 3.0 MCU clock off 10 100 1000 No load 10 pF load 1.30 2.4975 1.36 1.7 3.1 4.4925 –20 –10 0 10 20 30 40 50 60 70 80 90 MCU CLK OUT DIVIDE VALUE TA.42 1.1 3.5 VCC.32 1.5025 1.1 5.40 1.46 1. VB Voltage versus Temperature Normalized to 1. Current Standby Mode versus MCU Clock Output 800 STD I CC .5 3.9 3.48 DELTA CURRENT DRAIN (mA) 1.34 1. Additional IP3 Supply Current Consumption versus Temperature Normalized to 25°C ÁÁÁÁÁ ÁÁÁÁÁ Receive/Active ÁÁÁÁ ÁÁÁÁ Receive/Active 0 10 20 30 40 50 60 70 80 90 TA.3 4. SUPPLY VOLTAGES (V) ° DELTA CURRENT DRAIN (% FROM 25 C) 1.44 1.9 4.38 1.4950 Figure 12.5 4. Figure 13.7 pF 1710 Ω // 1. First Mixer Figures 17 through 20 show the first mixer transfer curves for the voltage conversion gain.7 MHz ceramic filter with a source and load impedance of 330 Ω. 20 MOTOROLA ANALOG IC DEVICE DATA . First Mixer Input and Output Impedance Schematic 1st Mixer Mix1 In RPI CPI CPO RPO Mix1 Out ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Figure 14.7 pF 300 Ω // 4.0 –55. They typically have an input impedance much greater than 330 Ω.5 –61.7 pF 1600 Ω // 1. however. output level. The –3.3 mA. Single–Ended data is from measured results. It is important to accurately match to these filters to guaranty a reasonable response.8 pF 1560 Ω // 3. To find the IF bandwidth response of the first mixer refer to Figure 22. Notice that there is approximately 10 dB linearity improvement when the “IP3 Increase” bit is set to <1>. First Mixer Output Impedance Unit 304 Ω // 3.0 dB corner at approximately 13 MHz and is used at a 10.7 MHz IF. The gain of the 1st mixer has a –3.MC13110A/B MC13111A/B FIRST AND SECOND MIXER Mixer Description The 1st and 2nd mixers are similar in design.8 pF 11. The output impedance as described in Figure 14 will be used to match to a ceramic or crystal filter’s input impedance. Figure 15 is a summary of the first mixer feedthrough parameters. Crystal filters are much narrower. more attention needs to be given to the filter characteristics of a crystal filter.8 pF 1570 Ω // 3. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Figure 16. First Mixer Input Impedance over Input Frequency US Center Channels U i Unit 49 MHz 46 MHz Single–Ended Differential Note: 1550 Ω // 3. The “IP3 Increase” bit is a programmable bit as shown in the Serial Programmable Interface section under the Rx Counter Latch Register. Typically the LO is suppressed better than –50 dB for the first mixer and better than –40 dB for the second mixer. 14.0 1st LO Feedthrough @ Mix1 In1 1st LO Feedthrough @ Mix1 Out RF Feedthrough @ Mix1 Out with –30 dBm France Center Channels 41 MHz 26 MHz Figures 13. First Mixer Feedthrough Parameters Parameter (dBm) –70. A series resistor may be used to raise the impedance for use with crystal filters. The IP3 = <1> option will increase the supply current demand by 1. Exact impedance matching to ceramic filters are not critical.8 pF 1670 Ω // 1.8 pF 1650 Ω // 3. A typical ceramic filter input impedance is 330 Ω while crystal filter input impedance is usually 1500 Ω. Differential data is from simulated results. and 16 represent the input and output impedance for the first mixer. Both are double balanced to suppress the LO and the input frequencies to give only the sum and difference frequencies at the mixer output.0 dB bandwidth point is approximately 13 MHz. and intermodulation. Notice that the input single–ended and differential impedances are basically the same.0 pF Output Impedance B IP3 = <0> (Set Low) B IP3 = <1> (Set High) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Figure 15.7 pF 1610 Ω // 1. It has an output impedance of 300 Ω and matches to a typical 10. 695 MHz.0 –10 –15 1.695 MHz.075 MHz 3.0 15 Figure 22. 330 Ω –16 –18 –20 –22 2.5 4. MIXER OUTPUT (dBm) Fundamental Level 0 –20 –40 –60 –80 –100 –40 Figure 20.0 –40 VCC = 3.0 6.0 2.0 4. IP3_bit = 0 0 Mix 1 Out. VOLTAGE CONVERSION GAIN (dB) MXgain1.0 –40 6. MIXER INPUT LEVEL (dBm) Mix1 In.6 V IF = 10.2 4. AUDIO SUPPLY VOLTAGE (V) MOTOROLA ANALOG IC DEVICE DATA 21 . IP3_bit = 1 Fundamental Level 3rd Order Intermodulation VCC = 3. First Mixer Voltage Conversion Gain. 330 Ω 14 Figure 18.7 IP3_bit = 0 10 5. IP3_bit = 1 MXgain1. First IF Bandwidth VCC = 3. VOLTAGE CONVERSION GAIN (dB) 12 VCC = 3.0 dB Mix1.0 0 –5.6 V IF = 10. MIXER INPUT LEVEL (dBm) Mix1 In. 330 Ω 3rd Order Intermodulation Mix 1 Out.9 4.1 5.0 –35 –30 –25 –20 –15 –10 –35 –30 –25 –20 –15 –10 Mix1 In.MC13110A/B MC13111A/B FIRST MIXER Figure 17.0 dB VOLTAGE COMPRESSION (dBm) IP3_bit = 1 MXgain1.6 V IF = 10. MIXER INPUT LEVEL (dBm) Figure 21.695 MHz. MIXER INPUT LEVEL (dBm) Figure 19. VOLTAGE CONVERSION GAIN (dB) –12 –14 IF = 10. IP3_bit = 0 14 12 10 8.0 3. First Mixer Output Level and Intermodulation.6 3. 330 Ω –35 –30 –25 –20 –15 –10 –35 –30 –25 –20 –15 –10 Mix1 In. First Mixer Compression versus Supply Voltage –10 VO 1.695 MHz. First Mixer Output Level and Intermodulation.6 V RL = 330 Ω LO = 36.695 MHz.3 3. First Mixer Voltage Conversion Gain. 1.4 10 f. IF FREQUENCY (MHz) 100 VCC Audio. MIXER OUTPUT (dBm) –20 –40 –60 –80 –100 –40 VCC = 3.8 5.6 V IF = 10. 330 Ω 10 8. 7 MHz ceramic filter. Second Mixer Input and Output Impedance Schematic 2nd Mixer Mix2 In RPI CPI CPO RPO Mix2 Out ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ Figure 25.2 pF IP3 = <1> (Set High) 22 MOTOROLA ANALOG IC DEVICE DATA .1 pF 1435 Ω // 6.5 kΩ making it suitable to match standard 455 kHz ceramic filters. output level.6 pF 2817 Ω // 3. (Note: This is the same programmable bit discussed earlier in the section. and intermodulation. The feedthrough parameters are summarized in Figure 25. Second Mixer Feedthrough Parameters Parameter (dBm) –42.8 kΩ. Second Mixer Input and Output Impedances Input Impedance RPI // CPI 2817 Ω // 3.6 pF Unit Output Impedance RPO // CPO IP3 = <0> (Set Low) 1493 Ω // 6. There is a slight improvement in gain when the “IP3 bit” is set to <1> for the second mixer.9 –61. The –3.5 MHz. 10.7 2nd LO Feedthrough @ Mix2 Out IF Feedthrough @ Mix2 Out with –30 dBm The 2nd mixer input impedance is typically 2. The IF bandwidth response of the second mixer is shown in Figure 31. The second mixer output impedance is 1. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ Figure 24.0 dB corner is 2. It requires an external 360 Ω parallel resistor for use with a standard 330 Ω.) Figure 23.MC13110A/B MC13111A/B Second Mixer Figures 26 through 29 represents the second mixer transfer characteristics for the voltage conversion gain. Second Mixer Compression versus Supply Voltage –10 VO 1.9 4.2 4. MIXER INPUT LEVEL (dBm) Mix2 In. IP3_bit = 0 10 Mix 2 Out.3 3. Second Mixer Output Level and Intermodulation.8 5. Second Mixer Output Level and Intermodulation.5 4.0 dB VOLTAGE COMPRESSION (dBm) –12 –14 IP3_bit = 0 –16 –18 –20 –22 2. IP3_bit = 1 Fundamental Level 3rd Order Intermodulation VCC = 3. 1. IP3_bit = 1 MX gain2.6 V RL = 1500 Ω 1.0 f. Second Mixer Conversion Gain.1 5. VOLTAGE CONVERSION GAIN (dB) VCC = 3. MIXER OUTPUT (dBm) –10 –30 –50 –70 –90 –40 VCC = 3.0 0 0. VOLTAGE CONVERSION GAIN (dB) MX gain2.6 V IF = 455 kHz RL = 1500 Ω Fundamental Level 3rd Order Intermodulation Mix 2 Out. MIXER INPUT LEVEL (dBm) Figure 28.0 dB Mix2. MIXER OUTPUT (dBm) 10 –10 –30 –50 –70 –90 –40 Figure 29. MIXER INPUT LEVEL (dBm) Figure 30.6 V IF = 455 kHz RL = 1500 Ω 16 12 –40 –35 –30 –25 –20 –15 –10 14 –40 –35 –30 –25 –20 –15 –10 Mix2 In. VOLTAGE CONVERSION GAIN (dB) 20 18 VCC = 3.1 Figure 31.6 V IF = 455 kHz RL = 1500 Ω 22 Figure 27.7 IF = 455 kHz RL = 1500 Ω 3.6 V IF = 455 kHz RL = 1500 Ω –35 –30 –25 –20 –15 –10 –35 –30 –25 –20 –15 –10 Mix2 In.6 3.MC13110A/B MC13111A/B SECOND MIXER Figure 26. Second IF Bandwidth MX gain2 . MIXER INPUT LEVEL (dBm) Mix2 In.4 IP3_bit = 1 25 20 15 10 5. AUDIO SUPPLY VOLTAGE (V) MOTOROLA ANALOG IC DEVICE DATA 23 .0 3. Second Mixer Conversion Gain. IF FREQUENCY (MHz) 10 VCC Audio. IP3_bit = 0 22 20 18 16 14 VCC = 3. The overall minimum Q required for first LO to function as it relates to the LO frequency is also given in Figure 34. First Local Oscillator Schematic To select the proper Lext and Cext we can do the following analysis. From Figure 34 it is observed that an inductor will have a significant affect on first LO performance. Figure 32.MC13110A/B MC13111A/B First Local Oscillator The 1st LO is a multi–vibrator oscillator. the minimum operating Q is approximately 25. especially over frequency. higher quality factors (Q) are required for the first LO to function properly. The 1st LO internal component values have a tolerance of ±15%.45 Vdc. and internal varactor. A typical dc bias level on the LO Input and LO Output is 0. internal programmable capacitor matrix. Figure 32 shows a representative schematic of the first LO function. This information will help the user to decide what inductor (Lext) to choose for best performance in terms of Q. lower LO frequencies need higher Q’s. From the following equation: Q Coil = Rp/X Coil where: Rp = parallel equivalent impedance (Figure 35). Cext can be determined as follows: 1 f LO 2p L extC ext + where: Lext = external inductance.08%/°C. Also. Cext = external capacitance. It represents the expected internal capacitance for a given control voltage (V cap Ctrl) of the MC13110A/B and MC13111A/B. Figure 34 clearly indicates that for lower coil values. The local oscillator requires a voltage controlled input to the internal varactor and an external loop filter driven by on–board phase–lock control loop (PLL). The tank circuit is composed of a parallel external capacitance and inductance. Refer to the Auxiliary Register in the Serial Interface Section for further discussion on LO programmability. From Figure 34. Ǹ Vcap Ctrl Varactor 1st LO Programmable Internal Varactor Capacitor LO1 In Cext LO1 Out Lext 24 MOTOROLA ANALOG IC DEVICE DATA . Choose an inductor value. say 470 nH. In Figure 35 the internal programmable capacitor selection relative to the first LO frequency and the parallel impedance is shown. The curve in Figure 33 is the varactor control voltage range as it relates to varactor capacitance. The temperature coefficient of the varactor is +0. AMBIENT TEMPERATURE (°C) Figure 37.0 8.7 Cap 11 1.5 5.7 1.0 2.6 1.S. CAPACITANCE (pF) –20 0 25 55 70 85 C1–C15. CONTROL VOLTAGE (V) Vcap Ctrl.6 10.5 120 100 30 MHz 80 40 MHz 60 40 50 MHz 20 0 100 LO INDUCTOR VALUE (nH) Figure 34. BASESET CHANNEL APPLICATION MOTOROLA ANALOG IC DEVICE DATA 25 . HANDSET CHANNEL APPLICATION CH1–CH25. First LO Varicap Capacitance versus Control Voltage 15 OVERALL MINIMUM Q VALUE 14 Vcap .5 1.9 1 3 5 7 9 11 13 15 17 19 21 23 25 Cap 9 Cap 10 Cap 6 1. U.S.4 9.5 2.8 9. Representative Parallel Impedance versus Capacitor Select 100 RP. Handset Application 1.3 1.MC13110A/B MC13111A/B FIRST LOCAL OSCILLATOR Figure 33.8 Vcap Ctrl. CONTROL VOLTAGE (V) 1. Baseset Application Cap 8 Cap 3 Cap 4 3 5 7 9 11 13 15 17 19 21 23 25 CH1–CH25.8 1. First LO Minimum Required Overall Q Value versus Inductor Value 1000 VcapCtrl.0 3.0 0. Varicap Value at VCV = 1.0 0.2 9.6 1. U.8 1 Figure 38.1 1. U.5 4.5 1.9 0.4 1. REPRESENTATIVE PARALLEL IMPEDANCE (k Ω) 11 10.5 1.0 1.2 1.0 5.S.0 7. Control Voltage versus Channel Number.1 1. CONTROL VOLTAGE (V) Figure 35.0 0 0.3 1.0 V Over Temperature 30 MHz 40 MHz 50 MHz 10 0 2 1 5 6 7 4 3 8 9 10 11 12 13 14 15 Vcap .5 3.S. CAPACITANCE (pF) 13 12 11 10 9. Control Voltage versus Channel Number.0 4. CAPACITANCE SELECT TA.8 Figure 36.2 1. U.4 1. 0 1.9 pF 9.0 4.0 3. Oscillator start–up is also significantly affected by the crystal load capacitance selection. This relationship was defined by using a 6.24 MHz Crystal CL = 10 pF RS = 20 Ω CAPACITOR RATIO (C2:C1) 26 MOTOROLA ANALOG IC DEVICE DATA .0 V 0 0.5 2. Output Impedance (RPO // CPO) SECOND LOCAL OSCILLATOR Figure 41.5 0 –22. and external load capacitance ratio (C2/C1).5 START–UP TIME (ms) 45 22.235 10. and even supply voltage will have and affect on the 2nd LO response as shown in Figures 45 and 46. Second Local Oscillator Input and Output Impedance Input Impedance (RPI // CPI) 11. Given the desired crystal load capacitance.7 V 2.24 f.MC13110A/B MC13111A/B Second Local Oscillator The 2nd LO is a CMOS oscillator.6 V VCC = 5. Figure 46 represents the ESR versus crystal load capacitance for the 2nd LO.5 V on PLL Vref. This is considered the minimum gain margin to guarantee oscillator start–up. The lower the load capacitance the better the performance. Except for the standby mode open loop gain is fairly constant as supply voltage increases from 2. Start–Up Time versus Capacitor Ratio.5 1. It is also interesting to point out that current consumption increases when C1 ≠ C2. Figure 39. See schematic in Figure 39. An external series resistor on the crystal output can be added to reduce the drive level. Second LO Gain/Phase @ –10 dBm 15 Vgain2.7 pF Figure 41 shows a typical gain/phase response of the second local oscillator.0 –10 –15 –20 –25 10. equivalent series resistance (ESR).5 –90 10.0 2. This could cause a noise problem.5 3. Second Local Oscillator Schematic 2nd LO RPI CPI Gm CPO RPO LO2 In Xtal LO2 Out ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ C1 C2 Figure 40. It is designed to utilize an external parallel resonant crystal.5 4.0 Figure 42.5 V. supply voltage. can be seen. It is used as the PLL reference oscillator and local oscillator for the second frequency conversion in the RF receiver.5 –45 –67.0 VCC = 2.0 dB minimum loop gain margin at 3. From the graphs it can seen that optimum performance is achieved when C1 equals C2 (C1/C2 = 1). FREQUENCY (MHz) Phase 10.6 V.0 0 –5.0 1.6 kΩ // 2.245 6.0 0 VCC = 3. C1 and C2 can be determined from Figure 47. LO VOLTAGE GAIN (dB) 10 5. In Figures 42 and 43 the relationship between crystal load capacitance. Load capacitance (CL).6 kΩ // 2.24 MHz Crystal CL = 10 pF RS = 20 Ω C1 = C2 = 15 pF Gain 90 67. Be careful not to overdrive the crystal. if necessary. Inactive to Rx Mode 10.0 VCC = 2. as shown in Figure 44.0 5.3 V 3. This is due to the regulated voltage of 2. 5 1.5 3.5 4. 3.5 2.0 1.0 2.0 1.0 CAPACITOR RATIO (C2:C1) Figure 45.5 1. Maximum Allowable Equivalent Series Resistance (ESR) versus Crystal Load Capacitance 100 10 10 Curve Valid for fosc in the Range of 10 MHz to 12 MHz 12 14 16 18 20 22 24 26 28 30 32 CRYSTAL LOAD CAPACITANCE (pF) CAPACITOR RATIO (C2:C1) Figure 47.0 3.6.0 Standby Current with Clk_Out Off 11 Standby Current with Clk_Out Running at 2.5 2. OPEN LOOP GAIN (dB) 16 VCC = 2.5 CAPACITOR RATIO (C2:C1) Oscillator Level 3.3 V 8.0 V 0.0 3.0 1000 Figure 46.7 V VCC = 3.0 2. SECOND OSCILLATOR LEVEL (dBm) START–UP TIME (ms) 30 25 20 15 10 5.5 9.0 1.048 MHz 12 13 LO2.0 3. STANDBY CURRENT ( µ A) 10.0 2.24 MHz Crystal CL = 10 pF RS = 20 Ω 0.0 4.24 MHz Crystal CL = 10 pF RS = 20 Ω Rx Mode 0 0.7. Maximum Open Loop Gain versus Capacitor Ratio ESR.5 4. Inactive to Rx Mode I STD.0 4.24 MHz Crystal CL = 24 pF RS = 16 Ω VCC = 2.5 1.0 10 15 20 25 30 35 REQUIRED PARALLEL CRYSTAL LOAD CAPACITANCE (pF) MOTOROLA ANALOG IC DEVICE DATA 27 . Second LO Current Consumption versus Capacitor Ratio 800 700 600 500 400 300 200 100 0 0 10. Optimum Value for C1 and C2 versus Equivalent Required Parallel Capacitance of the Crystal 70 OPTIMUM C1 AND C2 VALUE (pF) 60 C1 = C2 50 40 30 20 10 0 0 5.0 0 0 VCC = 2.6 V 10 VCC = 5. Start–Up Time versus Capacitor Ratio.MC13110A/B MC13111A/B SECOND LOCAL OSCILLATOR Figure 43. 5.3 V Figure 44.5 2. EQUIVALENT RESISTANCE ( Ω ) 20 AVOL.0 V 12 VCC = 2.5 3.0 0 10. 0 MHz. Thus. The goal is to tune the inductor in the area that is most linear on the “S–curve” (minimum distortion) to optimize the performance in terms of dc output level. The IF input impedance is 1. The following is a design example for a detector at 455 kHz and a specific loaded Q: The loaded Q of the quadrature detector is chosen somewhat less than the Q of the IF bandpass for margin. Of course.6 kΩ resistor are placed from Pin 27 to VCC .455)(680) = 29. The external quadrature component may be either a LCR resonant circuit. or a ceramic resonator which is usually fixed tuned. just the opposite is true for smaller Rext. An adjustable quadrature coil is selected. the parasitic capacitance may be neglected. Cp is the equivalent parallel capacitance of the parallel resonant tank circuit. Quadrature Detector Demodulator Schematic C28 10 p Lim Out1 Rext 22. Rint at the quadrature tank Pin 27 is approximately 100 kΩ and is considered in determining the external resistance.) Since the external capacitance is much greater than the internal device and PCB parasitic capacitance. MuRata Erie has designed a resonator for this part (CDBM455C48 for USA & A/P regions and CDBM450C48 for Europe).5 kΩ. Rewrite equation (2) and solve for L: L = (0. The output of the detector is represented as a “S–curve” as shown in Figure 52.Thus. Example: Let the total external C = 180 pF.) The bandwidth performance of the detector is controlled by the loaded Q of the LC tank circuit (Figure 50).1 kΩ. Decoupling capacitors should be placed close to Pins 31 and 32 to ensure low noise and stable operation. which may be adjustable. (Note: the capacitance is the typical capacitance for the quad coil.7 pF Lim In Figure 50. Thus.159)2/(C fc2 ) L = 678 µH . (More on ceramic resonators later. Figure 51 shows the schematic used to generate the “S–curve” and waveform shown in Figure 54 and 55. As Rext is increased the detector output slope will decrease. A 22 pF capacitor is placed from Pin 28 to 27 to properly drive the discriminator. a standard value is chosen: L = 680 µH (surface mount inductor) The value of the total damping resistor to obtain the required loaded Q of 15 can be calculated from equation (1): RT = Q(2π f L) RT = 15(2π)(0. This will have an affect on the audio output level and bandwidth. A ceramic discriminator is recommended for the quadrature circuit in applications where fixed tuning is desired.MC13110A/B MC13111A/B IF Limiter and Demodulator The limiting IF amplifier typically has about 110 dB of gain. The maximum audio output swing and distortion will be reduced and the bandwidth increased. 28 MOTOROLA ANALOG IC DEVICE DATA . Rext which is calculated from: Rext = ((RT)(Rint))/(Rint – RT) Rext = 41. Figure 48. The slope of the curve can also be adjusted by choosing higher or lower values of Rext . IF Limiter Schematic Limiter Stage Lim In RPI CPI Lim Out the IF bandpass Q is approximately 23.8 kΩ. This resonator has been designed specifically for the MC13110/111 family.1 k Toko Q Coil 7MCS–8128Z Q Coil The quadrature detector is coupled to the IF with an external capacitor between Pins 27 and 28. the Rext is chosen to be 22. Limiter Input Impedance Input Impedance (RPI) 1538 Ω Unit Input Impedance (CPI) 15. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ Figure 49. the frequency response starts rolling off at 1.5 kΩ The internal resistance. The ceramic discriminator and a 5. choose a standard value: Rext = 39 kΩ In Figure 50. XL is the reactance of the quadrature inductor at the IF frequency (XL= 2π f L). For an IF frequency of 455 kHz and an IF bandpass of 20 kHz. The 455 kHz IF center frequency is calculated by: (2) fc = [2π (L Cp)1/2] – 1 where L is the parallel tank inductor. where RT is the equivalent shunt resistance across the LC tank. This tank circuit represents one popular network used to match to the 455 kHz carrier frequency. the recovered signal level output is increased for a given bandwidth by increasing the capacitor. the loaded Q of the quadrature tank is chosen slightly lower at 15. This is a suitable match to 455 kHz ceramic filters. The following equation defines the components which set the detector circuit’s bandwidth: (1) RT = Q XL. The same resonator is also used for the US application and is centered around 455 kHz.2 1.0 400 200 444 446 448 450 452 454 456 458 460 0 t. S–Curve of Limiter Discriminator with Quadrature Coil 2.6 1. Typical Limiter Output Waveform with Quadrature Coil 800 f = 455 kHz Vpptyp = 344 mV Det Out. the “S–curves” for the resonator and quad coil have very similar limiter outputs.1 1.4 1. TIME (ms) Lim In.2 425 Toko 7MCS–8128Z AC VOLTAGE LEVEL (V) Figure 53.2 1.3 1.7 k Ceramic Resonator Murata CDBM450C34 Q Coil (CDBM455C48 US. DC VOLTAGE (V) 600 1.7 1. S–Curve of Limiter Discriminator with Ceramic Resonator 1.6 440 442 Murata CDBM450C48 AC VOLTAGE LEVEL (V) Figure 55. Ceramic Resonator Demodulator Schematic with Murata CDBM450C48 C28 390 p Lim Out1 Rext 2. the slope of the “S–curve” centered around the center frequency can be controlled by the parallel resistor. Rext. Typical Limiter Output Waveform with Ceramic Resonator 800 f = 450 kHz Vpptyp = 370 mV Det Out. As discussed previously.9 0. Distortion. bandwidth.8 0. INPUT FREQUENCY (kHz) MOTOROLA ANALOG IC DEVICE DATA 29 .0 0.0 400 200 435 445 455 465 475 485 0 t. IF LIMITER AND DEMODULATION Figure 52. CDBM450C48 France) The “S–curve” for the ceramic discriminator shown in Figure 54 is centered around 450 kHz.4 1.7 0.6 0.0 0. Clearly. INPUT FREQUENCY (kHz) Figure 54. TIME (ms) Lim In.8 1. It is for the French application. and audio output level will be affected.MC13110A/B MC13111A/B Figure 51. DC VOLTAGE (V) 600 1.5 1. RSSI dynamic range is typically 80 dB.0 3.04 0.5 mV/dB.03 0.01 0.0 5. The output is proportional to the logarithm of the IF input signal magnitude. RF INPUT (dBm) Figure 58. RF INPUT (dBm) CRSSI.05 0. Figure 59 shows this relationship. Since there is hysteresis in the carrier detect comparator. the less the ripple. A 187 kΩ resistor to ground is provided internally to the IC.0 0 –120 10 nF 22 nF 33 nF 47 nF 100 nF RSSI CHARGE TIME (ms) 35 30 25 20 15 10 5. For low carrier detect threshold settings.0 8.047 µf capacitor is recommended. RF INPUT (dBm) RSSI OUTPUT (Vdc) 1. The Carrier Detect Output (CD Out) is an open–collector transistor output. but RSSI charge time will be affected.2 0 –120 –100 –80 –60 –40 –20 0 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 100 RRSSI.8 0. The user must decide on a compromise between the RSSI ripple and RSSI start–up time. To form a carrier detect filter a capacitor needs to be connected from the RSSI pin to ground. The slope of the curve is 16.6 0. The carrier detect output may appear to be unstable.0 0. the ripple might supersede the hysteresis of the carrier detect.4 MIX1 IN.2 1.0 –110 –100 –90 –80 –70 –60 0 0. An external pull–up resistor of 100 kΩ will be required to bias this device.0 6. Figure 56 shows the RSSI versus RF input. RSSI Charge Time versus Capacitor Value 0.0 1. From Figure 57. at low carrier detect thresholds. Typical RSSI Voltage Level versus RF Input 1.08 0. Figure 58 represents the RSSI ripple in relation to the RF input for different filtering capacitors at RSSI.0 4.06 0. RSSI Ripple versus RF Input Level for Different RSSI Capacitors 11 10 RSSI RIPPLE (mVrms) 9. LOAD RESISTANCE (kΩ) Mixer 1 Input Increasing Signal Decreasing Signal 1000 Increasing Signal Decreasing Signal Limiter Input Figure 57. the higher the capacitor.0 2. LOAD CAPACITANCE (µF) 30 MOTOROLA ANALOG IC DEVICE DATA . However. Choose a 0. This internal resistor converts the RSSI current to a voltage level at the “RSSI” pin.0 7.01 µf capacitor as a starting point.02 Figure 59. the affect of an external resistor at RSSI on the carrier detect level can be noticed. To improve the RSSI accuracy over temperature an internal compensated reference is used. The carrier detect threshold is programmable through the MPU interface (see “Carrier Detect Threshold Programming” in the serial interface section). Clearly.4 0. Carrier Detect Threshold versus External RSSI Resistor Mix1 In. RSSI AND CARRIER DETECT Figure 56.09 0.6 1.MC13110A/B MC13111A/B RSSI and Carrier Detect The Received Signal Strength Indicator (RSSI) indicates the strength of the IF level. The range can be scaled by connecting additional external resistance from the RSSI pin to ground in parallel with the capacitor. Using a large capacitor will help to stabilize the RSSI level. a 0.10 Mix1 In.07 0. one trip level can be found when the input signal is increased while the another one can be found when the signal is decreased. fmod = 1.4 0.2 ± 0.2 ± 0.1 132 41.0 kHz. or Toko products (designed for 25 channel CT–0 cordless phone).8 42. fmod = 1. In production final test. The preamp circuit utilizes a tuned transformer at the output side of the amplifier. Figure 62 is a summary of the RF performance and Figure 63 contains the French RF Performance Summary. The duplexer frequency response at the receiver port has a notch at the transmitter frequency band of about 35 to 40 dB with a 2. 12 dB SINAD Sensitivity Levels.8 75.MC13110A/B MC13111A/B RF System Performance The sensitivity of the IC is typically 0.8 75. US Handset Application Channel 21 Sensitivity (dBm) –115. 50 Ω) Handset –100. The tuned preamp also improves the noise performance by reducing the bandwidth of the pass band and by reducing the second stage contribution of the 1st mixer.2 >80 Unit dBm mVrms dB % dB dB dB Parameter Sensitivity at 12 dB SINAD Recovered Audio SINAD @ –30 dBm THD @ –30 dBm S/N @ –30 dBm AMRR @ –30 dBm RSSI range The graphs in Figures 64 to 69 are performance results based on Evaluation Board Schematic (Figure 138).5 72.8 0.01 15 Mix1 In2 Mix1 In1 AMRR @ –30 dBm RSSI range Single–ended 50 Ω RF In1 49. The duplexer is important to achieve full duplex operation without significant “de–sensing” of the receiver by the transmitter.3 –114.1j Differential matched Single–ended match Single–ended 50 Ω –100. 50 Ω) Handset –91 89.4 >80 Baseset –100. This evaluation board did not use a duplexer or preamp stage.0 to 3.1 132 41.01 Mix1 In1 MOTOROLA ANALOG IC DEVICE DATA 31 .8 90 44. a preamp and passive duplexer may be used.8 Input Impedance (dBm) 50.0 dB insertion loss at the receiver frequency band.1 0. See Figure 45 and 48.3 0.2 73.7 56 >80 Baseset –90.8 78. The preamp and duplexer (differential. The following matching networks have been used to obtain 12 dB SINAD sensitivity numbers: Figure 60. This transformer is designed to bandpass filter at the receiver input frequency while rejecting the transmitter frequency. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Figure 63. To achieve suitable system performance.9 Ω Mix1 In2 0. The preamp is biased such that it yields suitable noise figure and gain.7 >80 Unit dBm mVrms dB % dB dB dB Parameter Sensitivity at 12 dB SINAD Recovered Audio SINAD @ –30 dBm THD @ –30 dBm S/N @ –30 dBm Single–ended Match 680 RF In1 39 1:5 0.1j 50.1 84. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Figure 62.8 78.0 kHz. matched input) yields typically –115 dBm @ 12 dB SINAD sensitivity performance under full duplex operation. The duplexer may be a two piece unit offered by Shimida. each section of the IC is separately tested to guarantee its system performance in the specific application. Sansui. RF Performance Summary for US French Applications MC13110A/MC13111A (fdev = 1.5 kHz. The combination of the duplexer and preamp circuit should attenuate the transmitter power to the receiver by over 60 dB. Matching Input Networks Differential Match 360 RF In1 39 1:5 15 Mix1 In2 Mix1 In1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ Figure 61.1j 50.0 kHz.2 ± 0.1 The exact impedance looking into the RF In1 pin is displayed in the following table along with the sensitivity levels.4 µVrms matched (single ended or differential) with no preamp. RF Performance Summary for US Applications MC13110A/MC13111A (fdev = 3. This will improve the receiver system noise figure without giving up too much IMD performance. 7 0. SPEAKER AMPLIFIER OUTPUT (mVrms) 85 80 SINAD.S. AMRR (dB) 60 SINAD. S/N.5 0.5 85 80 75 70 65 60 55 50 45 40 35 1 3 5 7 9 11 13 15 17 19 21 23 SINAD SA Out Level AMRR S/N 138 137 136 135 134 133 132 131 130 129 128 25 Mix1 In. Typical Performance Parameters Over U. FIRST MIXER INPUT (dBm) Figure 68. Typical Performance Parameters Over U. BASESET CHANNEL NUMBER Mix1 In1. Handset Application Channel 21 80 70 S/N SINAD. Typical Receiver Performance Parameters U. SPEAKER AMPLIFIER OUTPUT (mVrms) Figure 65. S/N. HANDSET CHANNEL NUMBER SA Out.S.9 0.3 0.7 1. Typical Receiver Performance for US Handset Application Channel 21 –10 –30 –50 –70 AMR –90 N –110 –120 –100 –80 –60 –40 –20 0 S+N+D N+D U. AMRR (dB) 75 70 65 60 55 50 45 40 35 1 3 5 7 9 11 13 15 17 19 21 23 SINAD SA Out Level AMRR S/N 138 137 136 135 134 133 132 131 130 129 128 25 SA Out.S. RF INPUT (dBm) U. Baseset Channel Frequencies Figure 67. 12 dB SINAD Sensitivity Over US Baseset Application Channels 1 5 9 13 17 21 25 1 5 9 13 17 21 25 US CHANNEL NUMBERS US CHANNEL NUMBERS 32 MOTOROLA ANALOG IC DEVICE DATA SA Out.S.3 RSSI OUTPUT (V) 1. S/N (dB) RSSI 50 40 SINAD 30 20 10 0 –120 –100 –80 –60 –40 –20 1.S. SPEAKER AMPLIFIER OUTPUT (dBV) Figure 66.1 0.1 0 1. 12 dB SINAD Sensitivity Over US Handset Application Channels –96 –97 12 dB SINAD (dBm) 12 dB SINAD (dBm) –98 –99 –100 –101 –102 –96 –97 –98 –99 –100 –101 –102 Figure 69.MC13110A/B MC13111A/B RF SYSTEM PERFORMANCE Figure 64. Handset Channel Frequencies . Data Amp Comparator The data amp comparator is an inverting hysteresis comparator. In practice this does not cause a problem since the signal is attenuated by at least 50 dB. The “DA In” input signal needs to be ac–coupled. the noise level clearly rises when the scrambler is enabled. However. This signal path consists of filters. the noise data at E Out and SA Out is much more improved. The “SA In” input pin must be ac–coupled. At Scr Out. 77. This spike is formed by rapid change in the phase at the frequency. and 78. and ripple characteristics are also shown in these graphs. External resistors and capacitors are used to set the gain and frequency response. The group delay (Figure 75) has a peak around 6.6 Vpp with a 130 Ω load. “Scr Out”.0 –9. and volume control. Its open collector output has an internal 100 kΩ pull–up resistor. The output capability at “Scr Out” and “E Out” are shown in Figures 76. too. Figures 71 to 73 represent the receive audio path filter response.0 0 10 SCR_Out (dBV) < –95 –92 –85 –76 –85 –77 –66 E_Out (dBV) < –95 < –95 < –95 < –95 < –95 < –95 < –95 SA_Out (dBV) < –95 < –95 < –95 < –95 < –95 < –95 < –95 MOTOROLA ANALOG IC DEVICE DATA 33 . Rx Path Noise Data Volume (dB) muted –14 0 16 –14 0 16 Receive Scrambler off/on off off off on (MC13110A/B) on (MC13110A/B) on (MC13110A/B) Receive Gain (dB) muted –9. A band pass filter is connected between the “Det Out” pin and the “DA In” pin with component values as shown in the Application Circuit schematic. out–of–band. Speaker Amp The Speaker Amp is an inverting rail–to–rail operational amplifier. The “Rx Audio In”. programmable Rx gain adjust. In Figure 70. assuming a nominal output level of –20 dBV (100 mVrms) at the 0 dB gain setting. Inband (audio). The filter response attenuation is very sharp above 3900 Hz. the noise floor is more than 56 dB below the audio signal.0 0 1. which is the cutoff frequency.MC13110A/B MC13111A/B Receive Audio Path The Rx Audio signal path begins at “Rx Audio In” and goes through the IC to “E Out”. The typical maximum output voltage at “E Out” should be approximately 0 dBV @ THD = 5. and “E In” pins are all ac–coupled. However.5 kHz. The typical output voltage at “SA Out” is 2. Rx mute. The results were obtained by increasing the input level for 2. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Figure 70. The speaker amp response is shown in Figures 79 and 80. and finally the expander. noise data for the Rx audio path is shown.0% .0% distortion at the outputs. The noninverting input is connected to the internal VB reference. VOLTAGE GAIN (dB) –10 –30 –50 –70 –110 –90 Rx Audio In to Scr Out Vin = –20 dBV 1000 10000 f. FREQUENCY (Hz) 10000 Figure 75. FREQUENCY (Hz) 100000 1000000 Figure 72. Rx Audio Wideband Frequency Response 10 V gain. FREQUENCY (Hz) 10000 100 Figure 73.1 0 100 1000 f. VOLTAGE GAIN (dB) V gain.0 –15 –25 –35 –45 –55 Figure 76.3 PHASE (°) 0. Rx Audio Ripple Response 0. Rx Audio Inband Frequency Response 5. FREQUENCY (Hz) 10000 Ein.3 –0.1 –0.0 –5.0 –15 –25 –35 –45 –55 100 Rx Audio In to Scr Out Vin = –20 dBV 1000 f.1 –0.MC13110A/B MC13111A/B Rx AUDIO Figure 71. Rx Audio Inband Group Delay Rx Audio In to Scr Out Vin = –20 dBV 1. Rx Audio Inband Phase Response Rx Audio In –135 to Scr Out Vin = –20 dBV –180 100 1000 f.5 100 Rx Audio In to Scr Out Vin = –20 dBV 1000 f.0 4.0 –5. VOLTAGE GAIN (dB) 0.0 Distortion –65 –40 –35 –30 –25 –20 –15 –10 –5. FREQUENCY (Hz) 10000 180 135 90 45 0 –45 –90 Figure 74. INPUT VOLTAGE LEVEL (dBV) 34 MOTOROLA ANALOG IC DEVICE DATA .5 V gain.0 E out .0 0 0 GROUP DELAY (ms) 0. OUTPUT VOLTAGE LEVEL (dBV) 10 5. Rx Audio Expander Response 28 24 DISTORTION (%) Expander Transfer 20 16 12 8. 8 Figure 80.0 7.8 3.6 0.0 5. INPUT VOLTAGE LEVEL (dBV) SA In.2 1.6 V THD = 2% Figure 78.0 10 14 VCC = 3.2 No Load 620 Ω 130 Ω SA Out.0 0.4 0.4 0.0 E out .6 2.8 1.4 2.2 SA In.0 –3. Rx Audio Maximum Output Voltage versus Gain Control Setting –4.0 0.6 2. OUTPUT VOLTAGE LEVEL (dBV) 1.0 0 620 Ω No Load 0 0. OUTPUT VOLTAGE LEVEL (dBV) VCC = 3. OUTPUT VOLTAGE LEVEL(dBV) 1.8 1.0 –1.2 0 0 0.0 –10 –12 –14 –16 –18 –20 –9.0 2.2 1.4 0.0 Scr Out. INPUT VOLTAGE LEVEL (dBV) MOTOROLA ANALOG IC DEVICE DATA 35 .4 2.8 0. OUTPUT VOLTAGE LEVEL (dBV) –6. Rx Audio Speaker Amplifier Drive SA Out.4 0.0 –2.2 0 –14 –10 –6.4 1.0 –7.0 –5.2 1. Rx Audio Speaker Amplifier Distortion 25 130 Ω 20 15 10 5.6 0. Rx Audio Maximum Output Voltage versus Volume Setting Rx PROGRAMMABLE GAIN CONTROL SETTING Rx PROGRAMMABLE VOLUME LEVEL SETTING Figure 79.0 1.0 3.0 9.0 –8.2 1.8 3.6 1.0 2.MC13110A/B MC13111A/B Rx AUDIO Figure 77.6 V THD = 2% 1.4 1.8 0.0 2.0 6. The limiter section provides hard limiting due to rapidly changing signal levels. At an input level above –15 dBV the automatic level control (ALC) function is activated and prevents hard clipping of the output. Similarly. The audio transmit signal path includes automatic level control (ALC) (also referred to as the Compressor). Figure 81. Above 5. The ALC. This is where the compressor curve ends.0. filters. Figure 90 through 93 show the Tx Out signal versus several combinations of ALC and Limiter selected. or transients.MC13110A/B MC13111A/B Transmit Audio Path This portion of the audio path goes from “C In” to “Tx Out”. The “C In” pin will be ac–coupled. Inband (audio). limiter.0 dBV the output actually begins to decrease and distort. External resistors and capacitors are used to set the gain and frequency response. and ripple characteristics are also shown in these graphs. The noninverting input terminal is connected to the internal VB reference. is very definite above 3800 Hz. The “Tx In” input is ac–coupled. Tx mute. The slope below –55 dBV input level is one. Tx Path Noise Data Transmit Gain (dB) muted –9. Figure 68 (ALC and Limiter Off) shows to compressor transfer curve extending all the way up to the maximum output. In Figure 88 the ALC function is off. Finally. The limiter begins to clip the output signal at this level and distortion is rapidly rising. and limiter functions can be enabled or disabled via the MPU serial interface.0%. Figure 81 is the noise data measured for the MC13110A/13111A. shown in Figure 87. has three different slopes. wideband. Here the slope is 2. The filter response attenuation. The typical maximum output voltage at “Tx Out” should be approximately 0 dBV @ THD = 5. A typical compressor slope can be found between –55 and –15 dBV. again. This is the filter cutoff frequency. Here the compressor curve continues to increase above –15 dBV up to –4. This is due to supply voltage limitations. and Tx gain adjust.0 dBV. The Tx gain adjust can also be remotely controlled to set different desired signal levels. With this technique the gain is slightly lowered to help reduce distortion of the audio signal. This is accomplished by clipping the signal peaks.0 0 10 –9. This data is for 0 dB gain setting and –20 dBV (100 mVrms) audio levels. The ALC provides “soft” limiting to the output signal swing as the input voltage slowly increases. Tx mute. The compressor transfer characteristics.0 0 10 Amp_Out (dBV) muted < –95 < –95 < –95 < –95 < –95 –< –95 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Transmit Scrambler off/on off off off on (MC13110A) on (MC13110A) on (MC13110A) Tx_Out (dBV) < –95 –83 –74 –64 –82 –73 –63 Mic Amp Like the Speaker Amp the Mic Amp is also an inverting rail–to–rail operational amplifier. 36 MOTOROLA ANALOG IC DEVICE DATA . Figures 82 to 86 represent the transmit audio path filter response. 0 0 100 1000 f. Tx Audio Inband Frequency Response 5.5 –0.1 –0. FREQUENCY (Hz) 10000 V gain.2 –0. FREQUENCY (Hz) 10000 PHASE (°) 180 135 90 45 0 –45 –90 –135 –180 100 Figure 85.0 Distortion DISTORTION (%) GROUP DELAY (ms) C In to Tx Out Vin = –10 dBV 1.3 0.MC13110A/B MC13111A/B Tx AUDIO Figure 82.1 0 –0. OUTPUT VOLTAGE LEVEL (dBV) 0 –5.0 –15 –25 –35 –45 –55 100 C In to Tx Out Vin = –10 dBV 1000 f.0 –10 –15 –20 –25 –30 –35 –40 –60 Figure 87.2 V gain. Tx Audio Inband Group Delay Tx Out.7 100 C In to Tx Out Vin = –10 dBV 1000 f.3 –0.0 0. FREQUENCY (Hz) 10000 –50 –40 –30 –20 –10 0 0 10 C In.0 V gain.0 ALC On.4 –0. FREQUENCY (Hz) 100000 1000000 Figure 84. Tx Audio Compressor Response 4. Tx Audio Inband Phase Response C In to Tx Out Vin = –10 dBV 1000 f.0 Compressor 2. Tx Audio Wideband Frequency Response 10 0 –10 –20 –30 –40 –50 –60 C In to Tx Out –90 Vin = –10 dBV –100 100 1000 –70 –80 Figure 83.6 –0. FREQUENCY (Hz) 10000 10 Figure 86. VOLTAGE GAIN (dB) 10000 f.1 1. INPUT VOLTAGE LEVEL (dBV) MOTOROLA ANALOG IC DEVICE DATA 37 . Tx Audio Ripple Response 0. Limiter On or Off 3. VOLTAGE GAIN (dB) 0. VOLTAGE GAIN (dB) –5. 0 –10 –15 –20 –25 –30 Distortion –35 –40 –60 –50 –40 –30 –20 –10 0 0 10 1.0 5. Tx Audio Compressor Response 4.0 C –12 –16 –20 –9. Limiter On or Off –7.6 V –4.0 Figure 88. Tx Audio Maximum Output Voltage versus Gain Control Setting 0 Tx Out.MC13110A/B MC13111A/B Tx AUDIO Tx Out.0 0 Figure 89.0 A: ALC Off.0 DISTORTION (%) –5. INPUT VOLTAGE LEVEL (dBV) Figure 90.0 ALC Off. Tx Output Audio Response Limiter On and ALC Off Figure 93. Limiter Off B: ALC Off. Tx Audio Compressor Response 4.0 Compressor Transfer 2.0 9. TIME (µs) 38 MOTOROLA ANALOG IC DEVICE DATA .0 OUTPUT LEVEL (mV) A Figure 91. OUTPUT VOLTAGE LEVEL (dBV) DISTORTION (%) Tx Out. OUTPUT VOLTAGE LEVEL (dBV) 0 –5.0 –10 –15 –20 –25 –30 1.0 3. Limiter On 3.0 7.0 Compressor Transfer 2.0 Distortion –35 –40 –60 –50 –40 –30 –20 –10 0 0 10 C In.0 B –8. Tx Output Audio Response Limiter and ALC Off 200 mV/Div 500 µs/Div Tx PROGRAMMABLE GAIN CONTROL SETTING t. OUTPUT VOLTAGE LEVEL (dBV) VCC = 3.0 –1. Tx Audio Output Response Limiter On and ALC On OUTPUT LEVEL (mV) 200 mV/Div 500 µs/Div OUTPUT LEVEL (mV) 200 mV/Div 500 µs/Div t.0 –5.0 –3. TIME (µs) Figure 92. TIME (µs) t.0 1.0 ALC Off. Limiter Off 3. INPUT VOLTAGE LEVEL (dBV) C In. Limiter On C: ALC On. and positive supply.. For the U. high impedance. The “PLL Vref” pin is the output of a voltage regulator which is powered from the “VCC Audio” power supply pin.S. The phase detectors are best considered to have a current mode type output. Rx and Tx PLL’s. It is important to remember. It is regulated by an internal bandgap voltage reference. Base Rx Ref U. Netherlands. Handset Tx Phase Detector (Current Output) Rx Phase Detector (Current Output) Tx VCO 8 Tx PD 6 Rx PD 4 Vcap Ctrl 42 LO1 In 40 LO1 Out 41 Tx VCO LP Loop Filter LP Loop Filter 14–b Programmable Rx Counter 1st LO Programmable Internal Capacitor MOTOROLA ANALOG IC DEVICE DATA 39 .K. and MPU serial interface are powered by the internal voltage regulator at the “PLL Vref” pin. An exception of this state is for narrow current pulses. and China (see channel frequency tables in AN1575. Internal level shift buffers are provided for the pins (Data. Tx PD and Tx VCO Pins Data. Figure 94 shows a simplified schematic of the I/O pins. When designing the external PLL loop filters.5 V away from either the positive or negative supply rail. The output can have three states. Kpd.24 MHz reference frequency crystal (see power–up default latch register state in the Serial Programmable Interface section). The maximum input and output levels for these pins is VCC. referenced to either the positive or negative supply rails. additional divide by 25 and divide by 4 blocks are provided to allow for generation of the 1. If a higher loop control voltage range is desired. LO2 Out.0 µA Out LO2 In. Clk Out) which connect directly to the microprocessor. the “PLL Vref” pin can be pulled to a higher voltage. The 14–bit Rx counter is programmed for the desired first local oscillator frequency. Dual PLL Simplified Block Diagram 14–b Programmable Tx Counter U. When this is done. internal fixed capacitors can be connected to the tank circuit through microprocessor programmable control. Clk and EN Pins Clk Out Pin PLL Loop Control Voltage Range The control voltage for the Tx and Rx loop filters is set by the phase detector outputs which drive the external loop filters. Figure 94. Tx VCO) is the regulated voltage at the “PLL Vref” pin.7 to 5. it is recommended that the Tx and Rx phase detectors be considered as current drive type outputs.5 V) VCC Audio (2.. This dual PLL is fully programmable through the MCU serial interface and supports most country channel frequencies including USA (25 ch).7 to 5.0 V regulated voltage is available. Spain.K. The programmed divider value for the reference divider is selected based on the crystal frequency and the desired Rx and Tx reference frequency values. LO2 Out. All counters power–up to a set default state for USA channel #21 using a 10.2 kHz reference frequencies. Korea. which in this case is the voltage at “PLL Vref”. PLL I/O Pin Configurations The 2nd LO. When the loop is locked the phase detector outputs are at high impedance.K.5 V. Tx PD. The phase detector current source was not designed to operate at the supply rails. Australia.5 V) VCC Audio (2. The ESD protection diodes on these pins are also connected to “PLL Vref”.5 V) I/O In 2. It can be tied directly to the VCC voltage (with suitable filter capacitors connected close to each pin). EN. Base Tx Ref LO2 In 1 LO2 Out 2 ÷ 25 12–b Programmable ÷4 Reference ÷1 Counter U. The 2nd local oscillator and reference divider provide the reference frequency signal for the Rx and Tx PLL loops. VCO tuning range will also be limited by this voltage range The maximum loop control voltage is the “PLL Vref” voltage which is 2. the internal voltage regulator is automatically disabled.K. Figure 95. the maximum input and output levels for most of the PLL I/O pins (LO2 In. France. The loop filter control voltage must be 0. “Worldwide Cordless Telephone Frequencies”). Rx PD. 25 channel operation. PLL I/O Pin Simplified Schematics PLL Vref (2. U. To extend the sensitivity of the 1st LO for U. will not be affected if the “PLL Vref” is tied to VCC.MC13110A/B MC13111A/B PLL SYNTHESIZER SECTION PLL Frequency Synthesizer General Description Figure 95 shows a simplified block diagram of the programmable universal dual phase locked loop (PLL) designed into the MC13110A/B and MC13111A/B IC.K. Therefore. New Zealand. ground. that if “PLL Vref” is tied to VCC and VCC is not a regulated voltage. This is commonly used in the telephone base set where an external 5. Clk. The 14–bit T x counter is programmed for the desired transmit channel frequency.K. Rx PD. The phase detector gain constant.0 kHz and 6. If the loop voltages get within 0.5 V of either rail the linear current output starts to degrade.5 V) PLL Vref (2. Handset U. the PLL loop parameters and lock–up time will vary with supply voltage variation. This will create sufficient phase margin for stable loop operation.5 V/4. Bode Plot of Gain and Phase in Open Loop Condition 0 Divider (Kn) Where: Kpd = Phase Detector Gain Constant Kf = Loop Filter Transfer Function Ko = VCO Gain Constant Kn = Divide Ratio (1/N) fi = Input frequency fo = Output frequency fo/N = Feedback frequency divided by N From control theory the loop transfer function can be represented as follows: A = Kpd Kf Ko Kn Open loop gain Kpd can be either expressed as being 2. The loop filter can take the form of a simple low pass filter. PLL Model fi Phase Detector (Kpd) Filter (Kf) VCO (Ko) Open Loop Gain fo A. velocity. such as capture range. and acceleration. originating from the loopfilter and the VCO gain. lock–up time. Since there are two integrating functions in the loop. Figure 96 is the general model for a Phase Lock Loop (PLL). type 2 filter will be used in this discussion since it has the advantage of improved step response. The type 2 low pass filter discussed here is represented as follows: Figure 97. the open loop gain and the phase is displayed in the form of a Bode plot. More details about performance of different type PLL loops. it follows: A + openloop Qp ǒ Ǔǒ K T1 pd o w 2C1K nT2 K T2 2 – ) jwT2 ) jwT1 Ǔ (3) The phase margin (phase + 180) is thus determined by: + arctan(wT2)–arctan(wT1) (4) At w=wp.0 mA/2. The fundamental loop characteristics. Figure 96.MC13110A/B MC13111A/B Loop Filter Characteristics Lets consider the following discussion on loop filters. The function of the additional components R2 and C2 is to create a pole and a zero (together with C1) around the 0 dB point of the open loop gain. The filter characteristic needs to be determined such that it is adding a pole and a zero around the 0 dB point to guarantee sufficient phase margin in this design (Qp in Figure 98). the open loop gain response follows a +0+ ) (wT2) 1 ) (wT1) w + wp + 1 ǸT2T1 1 T1 T1 2 (5) (6) Or rewritten: +w 1 2T2 p (7) 40 MOTOROLA ANALOG IC DEVICE DATA . Figure 98. and transient response are controlled externally by loop filtering. In Figure 98. refer to Motorola application note AN535. Loop Filter with Additional Integrating Element From Phase Detector R2 C1 C2 To VCO Phase Qp wp –180 The open loop gain including the filter response can be expressed as: A + openloop K jwK n ǒ ǒ ǒ Ǔ ǓǓ K (1 pd o T2 ) jw(R2C2)) jw 1 ) jw R2C1C2 C1)C2 + R2C2 1 1 (1) The two time constants creating the pole and the zero in the Bode plot can now be defined as: T1 R2C1C2 + C1 ) C2 (2) By substituting equation (2) into (1). Open Loop Gain 0 –90 second order slope (–40 dB/dec) creating a phase of –180 degrees at the lower and higher frequencies. A current output. capacitor C1 forms an additional integrator.0 π or 1.0 π for the CT–0 circuits. and filters the discrete current steps from the phase detector output. the derivative of the phase margin may be set to zero in order to assure maximum phase margin occurs at wp (see also Figure 98). loop bandwidth. This provides an expression for wp: dQ p dw From Figure 97. providing the type 2 response. This will present a less stable system. but also generate higher overshoots on the control line to the VCO. the better the reference frequency is filtered. such step response approach is not really valid. Varicap Capacitance versus Control Voltage 15 14 Vcap . In some applications.0 V to 2. but also increase lock–times.0 3. It does not clearly define what the exact frequency difference is from the desired frequency and it does not show the effect of phase margin.By substituting into equation (4). and equation (2) solve C2 and R2: Ǹ Ko 1 + jw ǒ) Ǔ ǒ) Ǔ 1 1 w pT2 w pT1 2 2 (10) (15) Although the basic loopfilter previously described provides adequate performance for most applications. In general.0 4.5 5. the reference frequency might represent the spacing between channels. Since it is quite complicated to accurately calculate lock time. and thus the absolute value of the complex open loop gain as shown in equation (3) solves C1: As can be derived from Figure 99. that the phase detector steps up to the desired control voltage without hesitation.5 2. too. wp should be chosen far below the reference frequency in order for the filter to provide sufficient attenuation at that frequency. The external capacitors may show some leakage. The free running frequency of the VCO is determined by: f (13) T In which L represents the external inductor value and CT represents the total capacitance (including internal capacitance) in parallel with the inductor. there is no signal coming from the phase detector. Given that the channel spacing in a CT–0 telephone set is based on the reference frequency. an extra pole may be added for additional reference frequency filtering. The practical range for phase margin is 30 degrees up to 70 degrees. As shown in Figure 98. The choice of Qp determines the stability of the loop. solve for T2: Qp 2 T2 + tan ǒ Ǔ )p 4 wp MC13110A/B MC13111A/B C2 (8) *1 + C1 T2 T1 R2 + T2 C2 1 + 2p Ǹ LC ǒ Ǔ (11) (12) By choosing a value for wp and Qp. T1 and T2 can be calculated. Hence. In general. The selection of wp is strongly related to the desired lock–time. It assumes.5 3.0 0 0.5 1. Any feedthrough to the VCO that shows up as a spur might affect adjacent channel rejection. the open loop gain at wp is 1 (or 0 dB). The two input frequencies are not locked. But in practice leakage currents will be supplied to both the VCO and the phase detector.0 2. the varicap capacitance changes 1. choosing a phase margin of 45 degrees is a good choice to start calculations. but the longer it takes for the loop to lock. with the loop in lock. Larger values of phase margin provide a more stable system.3 pF over the voltage range from 1. Their phase maybe momentarily zero and force the phase detector into a high impedance mode. the lock times may be found to be somewhat higher.5 [ w3p (9) Equation (9) only provides an order of magnitude for lock time. Hence.0 V: DCvar + 1. however.0 1. Choosing lower phase margins will provide somewhat faster lock–times. and any feedthrough to ȡ ȧ ȥ ȧ Ȣ Ǹǒ 2p 1 T L C ) DCvar 2 Ǔ * 2p Ǹǒ 1 L C T ) DCvar 2 ȣ ȧ ȧ ǓȦ Ȥ MOTOROLA ANALOG IC DEVICE DATA 41 . the lower wp. The VCO gain can be easily calculated via the internal varicap transfer curve shown below.3VpF (14) Combining (13) with (14) the VCO gain can be determined by: C1 + ǒ Ǔ K K T1 pd o w 2K nT2 With C1 known. Figure 99. CAPACITANCE (pF) 13 12 11 10 9. a good first order approach is: T_lock The VCO gain is dependent on the selection of the external inductor and the frequency required.0 5.0 7.0 8. In theory. In practice.5 4. can be set to: T3 1 + Kw p (23) 42 MOTOROLA ANALOG IC DEVICE DATA . the cut–off frequency must be much lower than the reference frequency. Figure 100. it can be shown: A +– openloop K nw 2 (C1 In which: T1 ǒ K ) C2 ) K pd o C3) – w 2C1C2C3R2R3 1 ) jwT2 ) Ǔ 1 ) jwT1 (16) (C1 ) C2)T2 ) (C1C2)T3 + C1 ) C2 ) C3 * w2C1T2T3 (17) T2 + R2C2 (18) T3 + R3C3 2 (19) From T1 it can be derived that: C2 ) T3 * T1 ) w T1T2T3 + (T1 ) T2)C3 * C1 T2 T3 * T1 ǒ In analogy with (10). by forcing the loopgain to 1 (0 dB) at wp. However. we obtain: C1(T1 ) T2) ) C2T3 ) C3T2 + ǒ Ǔ K pd o K nw p 2 K Solving for C1: Ǹ T2 Ǔ 2 2 (20) 1 1 (T2 * T1)T3C3 * (T3 * T1)T2C3 ) (T3 * T1) (T3 C1 + * T1)T2 ) (T3 * T1)T3 * ǒ ǒ Ǔ K K T1 pd o w p 2K n ǒ Ǔ )ǒ Ǔ ) w pT2 w pT1 ) T3 * T1 ) wp2T1T2T3 T3 Ǹ (21) 1 ) wpT2 2 1) w pT1 2 Ǔ ǒ Ǔ ǒ Ǔ (22) By selecting wp via (9). the additional time constant expressed as T3. Figure 100 shows a loopfilter architecture incorporating an additional pole. Similarly.MC13110A/B MC13111A/B the first LO may effect parameters like adjacent channel rejection and intermodulation. it must also be higher than wp in order not to compromise phase margin too much. The following equations were derived in a similar manner as for the basic filter previously described. Loop Filter with Additional Integrating Element From Phase Detector R2 C1 C2 C3 To VCO R3 For the additional pole formed by R3 and C3 to be efficient. wp is chosen to be 20 times less than the reference frequency of 5.2 nF C2 = 82 nF R2 = 18 kΩ R3 = 100 kΩ C3 = 1 nf Select MOTOROLA ANALOG IC DEVICE DATA 43 .7 kΩ R3 = 100 kΩ C3 = 909.5 pF Fref = 5.MC13110A/B MC13111A/B The K–factor shown determines how far the additional pole frequency will be separated from wp.83 MHz VCO center = 39. Figure 102. With the adjacent channels spaced at least 15 kHz away.54 Mrad/V T2 = 1540 µs T1 = 264 µs T3 = 91 µs C1 = 9.56 Mrad/V T2 = 1540 µs T1 = 264 µs T3 = 91 µs C1 = 7.9 nF R2 = 21.6 nF C2 = 70. By using equations (8) and (7). Choose K to be approximately five times wp (5.082 1000 80 0 Phase Margin –40 40 0 Phase Margin –40 40 20 20 –80 100 1000 10000 f. Finally. Open Loop Response Baseset US with Selected Values From Phase Detector 100 k To VCO 18 k .0 ms (order of magnitude).8 nF C2 = 68 nF R2 = 22 kΩ R3 = 100 kΩ C3 = 1 nf Select Figure 104. the equations may provide negative capacitance or resistor values. With the adjacent channels spaced at least 15 kHz away. C3 becomes known and C1 and C2 can be solved from the equations. FREQUENCY (Hz) 100000 0 1000000 Figure 103. This provides a lock time according to (9) of about 2.0 kHz and the phase margin has been set to 45 degrees. Open Loop Response Handset US with Selected Values From Phase Detector 100 k To VCO 22 k 6800 80 Loop Gain Phase Margin (degrees) Open Loop Gain (dB) Open Loop Gain (dB) 40 60 40 .0 kHz and the phase margin has Figure 101. Selecting too small of a K–factor. The following pages. wp is chosen to be 20 times less than the reference frequency of 5.0wp).77 MHz VCO center = 36.1 nF C2 = 83.068 1000 80 80 Loop Gain Phase Margin (degrees) 60 8200 been set to 45 degrees. Baseset US Conditions L = 470 uH RF = 49.5 nF R2 = 18.075 MHz Results Kpd = 159. By selecting R3 to be 100 kΩ.5 pF Fref = 5. the loopfilter components are determined for both handset and baseset the US application based on the equations described.135 MHz Results Kpd = 159.0 kHz Qp = 45 degrees wp = wref / 20 radians Equations (14). In an application. R2 follows from T2 and C2. Handset US Conditions L = 470 uH RF = 46. reference feedthrough at wp will not be directly disastrous but still.2 uA/rad KVCO = 4. Too large of a K–factor may not provide the maximum attenuation. (15) (8) (7) with K = 7 (21) (20) (18) choose: (19) C1 = 6. the additional pole may be added in the loopfilter design for added safety.0 ms (order of magnitude).4 kΩ R3 = 100 kΩ C3 = 909. the additional pole may be added in the loopfilter design for added safety.2 uA/rad KVCO = 3. time constants T2 and T1 can be derived by selecting a phase margin.0 kHz Qp = 45 degrees wp = wref / 20 radians Equations (14). (15) (8) (7) with K = 7 (21) (20) (18) choose: (19) C1 = 8. This provides a lock time according to (9) of about 2. In an application. FREQUENCY (Hz) 100000 0 1000000 –80 100 1000 10000 f. reference feedthrough at wp will not be directly disastrous but still. Clk. Figure 105. Enable Timing Requirement 50% Clk tsuEC 50% trec 50% Previous Data Latched The MPU serial interface is fully operational within 100 µs after the power supply has reached its minimum level during power–up (see Figure 108).7 V Last Clock First Clock VCC tpuMPU 50% EN Data. It is specified by the address that was previously loaded. the switched capacitor filter clock counter. EN 44 MOTOROLA ANALOG IC DEVICE DATA . Figure 106 shows the timing required on the EN pin. Clock.MC13110A/B MC13111A/B SERIAL PROGRAMMABLE INTERFACE Microprocessor Serial Interface The Data. Figure 106. and various other control functions. Figure 108. EN 50% Data tsuDC th 50% Clk Data MSB 16–Bit Data Latch EN Data Register Programming Mode LSB Latch 10% Data tf The state of the “EN” pin when clocking data into the shift register determines whether the data is latched into the address register or a data register. Microprocessor Interface Programming Mode Diagrams MSB 8–Bit Address LSB Latch EN Address Register Programming Mode After data is loaded into the shift register. Figure 105 shows the timing required on the “Data” and “Clk” pins. up to 16–bits of data is loaded into the shift register and latched into the data latch register. Latching occurs on the negative EN transition. A minimum of four “Clk” rising edge transition must occur before a negative “EN” transition will latch data or an address into a register. Clk. and “EN” respectively) pins provide a MPU serial interface for programming the reference counters. “Clk”. Data is clocked into the shift register on positive clock transitions. The MPU Interface shift registers and data latches are operational in all four power saving modes. The “Data” and “Clk” pins are used to load data into the MC13111A/B shift register (Figure 109). The clock can be in a high state (default high) or a low state (default low) but must not have any transitions during the “EN” high state. Rx. Data can be loaded into the shift registers and latched into the latch registers in any of the operating modes. In the data programming mode. Inactive. and Enable (“Data”. an 8–bit address is loaded into the shift register and latched into the 8–bit address latch register. Data and Clock Timing Requirement tr 90% Data. the data is latched into the appropriate latch register using the “EN” pin. This is done in two steps. Then. there must not be any clock transitions when “EN” is high. First. Microprocessor Serial Interface Power–Up Delay 2. The convention in these figures is that latch bits to the left are loaded into the shift register first. and Active Modes. Figure 107 shows the address and data programming diagrams. the transmit and receive channel divide counters. Standby. Figure 107. 0 kHz reference frequency from a 10. (00000101) 0 MSB LSB MSB LSB 6. Latch bits to the left (MSB) are loaded into the shift register first. The switched capacitor filter clock counter is set properly for operation with a 10. all latch registers are initialized to a defined state. Bits proceeding the register must be “0’s” as shown. (00000011) Reference Counter Latch ALC Disable MPU Clk 2 Limiter Disable Clk Disable MPU Clk 1 MPU Clk 0 Stdby Mode Rx Mode Tx Mute Rx Mute SP Mute 0 MSB 4–b Vol Control LSB 4. HS Select U. The Tx and Rx counter registers are set for USA handset channel frequency. The reference counter is set to generate a 5. (00000010) 0 0 U. (00000110) SCF Clock Dividers Latch (MC13110A/B only) 3–b Low Battery Detect Threshold Select 4–b Voltage Reference Adjust 6–b Switched Capacitor Filter Clock Counter Latch 0 MSB LSB 0 0 MSB LSB 6.K. (00000001) 0 MSB 14–b Rx Counter Rx Counter Latch LSB 2. BS Select MSB 12–b Reference Counter LSB 3. (00000110) SCF Clock Dividers Latch (MC13111A/B only) 0 0 0 0 0 0 0 0 0 3–b Test Mode 4–b 1st LO Capacitor Selection 7. The LSB bit must always be the last bit loaded into the shift register.24 MHz crystal. Rx mode with all mutes active. Figure 110 shows the initial power–up states for all latch registers. (00000100) Mode Control Latch 5–b Tx Gain Control 5–b Rx Gain Control Gain Control Latch 3–b Low Battery Detect Threshold Select 4–b Voltage Reference Adjust Tx Sbl Bypass Rx Sbl Bypass 6–b Switched Capacitor Filter Clock Counter Latch 5–b CD Threshold Control 0 MSB LSB MSB LSB MSB LSB 5. The device is initially placed in the Figure 109.24 MHz crystal. Microprocessor Interface Data Latch Registers Latch Address 0 0 MSB 14–b Tx Counter Tx Counter Latch IP3 Increase LSB 1.K.MC13110A/B MC13111A/B Data Registers Figure 109 shows the data latch registers and addresses which are used to select each of each registers. (00000111) Auxillary Latch MOTOROLA ANALOG IC DEVICE DATA 45 . number 21 (Channel 6 for previous FCC 10 Channel Band). Power–Up Defaults for Data Registers When the IC is first powered up. handset operation. is a special case which requires a different reference frequency value for Tx and Rx. set “U. For U.K. Handset Select” to “1”. MC13110A/B MC13111A/B Tx and Rx Counter Registers The 14 bit Tx and Rx counter registers are used to select the transmit and receive channel frequencies. set “U.K. Then the fixed divider is set to “1” and the Tx and Rx reference frequencies will be equal to the crystal oscillator frequency divided by the programmable reference counter value.K.K. However. Then set the reference divider to 1024 to get a total divider of 4096. there is also an increase in power supply current of 1. Base Select” and “U. Rx and Tx Counter Register Latch Bits 0 0 MSB 14–b Tx Counter Tx Counter Latch 0 IP3 Increase MSB 14–b Rx Counter Rx Counter Latch LSB LSB Figure 112. Reference Counter Register 0 0 U. This will give a fixed divide by 4 for both the Tx and Rx reference. Bits 6 and 7 in the SCF latch register are ”Don’t Cares” for the MC13111A/B since this part does not have a scrambler.K. This is larger than the maximum divide value available from the 12–bit reference divider (4095).K.K. Latch Register Power–Up Defaults MSB LSB R i Register Tx C Count 9966 7215 2048 N/A N/A 31 31 15 – – – – – – – – 14 – – – 0 0 0 0 – 13 1 0 0 0 1 0 0 – 12 0 1 0 0 1 0 0 – 11 0 1 1 0 1 0 0 – 10 1 1 0 1 1 1 1 – 9 1 0 0 1 0 1 1 – 8 0 0 0 0 1 1 1 – 7 1 0 0 1 1 0 – – 6 1 0 0 1 1 0 – 0 5 1 1 0 1 1 0 0 0 4 0 0 0 0 1 1 1 0 3 1 1 0 1 0 1 1 0 2 1 1 0 1 1 1 1 0 1 1 1 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0 Rx Ref Mode Gain SCF (MC13110A/B) SCF (MC13111A/B) Aux N/A NOTE: 12. In this case. Base Select” to “1”. For U. With “IP3 increase” = <1>. Handset Select U. The power–up default for the MC13111A/B is “IP3 Increase” = <0>.ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁÁ ÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Figure 110. Base Select MSB 12–b Ref Counter LSB 46 MOTOROLA ANALOG IC DEVICE DATA .K. set “U.5 kHz reference frequency is used for both the Tx and Rx reference and the total divider value required is 4096. set “U.K. Handset Select” bits to “0”. Handset Select” to “1”. The register bits are shown in Figure 111. Figure 111. require that the Tx and Rx reference frequencies be identical. A 2. In the Rx counter there is an “IP3 Increase” bit that allows the ability to trade off increased receiver mixer performance versus reduced power consumption.3 mA. Reference Counter Register Reference Counter Figure 113 shows how the reference frequencies for the Rx and Tx loops are generated.K.K. The U. Base Select” to “1” and set “U. The Netherlands is also a special case. base operation.K. All countries except the U. there is about a 10 dB improvement in 1 dB compression and 3rd order intercept for both the 1st and 2nd mixers. In this case. Base Tx Reference Frequency LO2 In LO2 LO2 Out ÷ 25 12–b Programmable Reference ÷ 4.K. Reference Counter Register Programming Mode U.099 kHz 4. Figure 114 shows the relationship between different crystal frequencies and reference frequencies for cordless phone applications in various countries. mutes. Operation of the Control Register is explained in Figures 115 through 119. Base/ Handset Divider 1 4 1 1 1 4 Reference Frequency 5. The scrambler mixer modulation frequency is the switched capacitor clock divided by 40 for the MC13110A/B.129 kHz 4.15 MHz Reference Divider Value 2048 1024 2230 2400 1784 446 446 U. The actual switched capacitor clock divider ratio is twice the programmed divider ratio due to the a fixed divide by 2. The switched capacitor filter 6–bit programmable counter must be programmed for the crystal frequency that is selected since this clock is derived from the crystal frequency and must be held constant regardless of the crystal that is selected. volume control.K.16 kHz 165. Mode Control Register The power saving modes.97 kHz 166.15 MHz 11.15 MHz 11. Handset Select 0 0 1 1 U.0 kHz 5.15 MHz 6.K. and microprocessor clock output frequency are all ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁ set by the Mode Control Register. and Netherlands U. Hand Set Netherlands Base and Hand Set ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ Figure 114.K. Mute and Disable Control Bit Descriptions ALC Disable 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Automatic Level Control Disabled Normal Operation Tx Limiter Disable Tx Limiter Disabled Normal Operation Clock Disable (MC13110A/111A) Clock Disable (MC13110B/111B) Tx Mute MPU Clock Output Disabled Normal Operation Don’t Care Normal Operation Transmit Channel Muted Normal Operation Receive Channel Muted Normal Operation Speaker Amp Muted Normal Operation Rx Mute SP Mute MOTOROLA ANALOG IC DEVICE DATA 47 .0 kHz 5. “LO2 In” may also serve as an input for an externally generated reference signal which is ac–coupled. Base Rx Reference Frequency U.K. Base Set U.0 after the programmable counter.K. Reference Frequency and Divider Values MC13110A/B MC13111A/B Crystal Frequency 10. Base Select 0 1 0 1 Tx Divider Value 1 25 4 4 Rx Divider Value 1 4 25 4 Application All but U.K.00 MHz 11.97 kHz Scrambler Modulation Divider 40 40 40 40 40 40 40 Scrambler Modulation Frequency 4.K.0 kHz SC Filter Clock Divider 31 31 34 36 34 34 34 SC Filter Clock Frequency 165.16 kHz 163.24 MHz 11.MC13110A/B MC13111A/B Figure 113.24 MHz 10.167 kHz 4.099 kHz 4.129 kHz 4. Mode Control Register MPU Clk 0 4–b Volume Control 0 ALC Disable MPU Clk 2 Limiter Disable Clk Disable MPU Clk 1 Stdby Mode Rx Mode Tx Mute Rx Mute SP Mute Reference Frequency Selection The “LO2 In” and “LO2 Out” pins form a reference oscillator when connected to an external parallel–resonant crystal.67 kHz 163.K.0 U.0 Counter ÷1. Handset U.0 kHz 5.25 kHz 6.25 kHz 1. disables.97 kHz 163.K.97 kHz 163. The reference oscillator is also the second local oscillator for the RF Receiver.099 kHz 12.099 kHz 4.0 kHz 25 Figure 115. Handset U. Figure 116. Rx.MC13110A/B MC13111A/B Power Saving Operating Modes When the MC13110A/B or MC13111A/B are used in a handset. it is important to conserve power in order to prolong battery life. Only the 2nd LO and MPU clock divider are active. In Standby and Inactive Modes. With the B” version the MPU Clock is always running so that there can never be a register reset if the memory is disturbed. In the Active mode. Figure 119. “PLL Vref” remains powered but is not regulated. By programming the MPU clock divider to a large divide value of 20. “X” is a don’t care 14. 16. There is no Inactive mode for MC13110B/MC13111B. 2 X2 “PLL Vref” Regulated Voltage MPU Serial Interface 2nd LO Oscillator MPU Clock Output RF Receiver and 1st LO VCO Rx PLL Carrier Detect Data Amp Low Battery Detect Tx PLL Rx and Tx Audio Paths NOTES: 15. In the Standby and Interrupt Modes. except that there is no Inactive mode. Circuit Blocks Powered During Power Saving Modes MC13110A/MC13111A MC13110B/MC13111B Rx X X X X X X X X X Standby X1 X X X Circuit Ci i Blocks Bl k Active X X X X X X X X X X X Inactive X1. In the Inactive Mode. Figure 118 shows the control register bit values for selection of each power saving mode and Figure 118 shows the circuit blocks which are powered in each of these operating modes. or 312. and Inactive. Power Saving Application – Option 1 (MC13110B and MC13111B Only) When the handset is in standby. Interrupt. Standby. Power is saved in the low power mode by putting the MC13110B/MC13111B into its “Standby” mode. and Standby. There are five modes of operation for the MC13110A/MC13111A. All mode functions are the same for the MC13110B/MC13111B. power can be reduced by entering a “low power” mode and periodically switching to “sniff” mode to check for incoming calls. all circuitry is powered down except for those circuit sections needed to receive a transmission from the base. all circuit blocks are powered. MPU Clock Out is ”Always On” ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ Á ÁÁÁ Á ÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Figure 118. It will fluctuate with VCC. the 2nd LO and MPU clock run continuously. The MPU maintains control at all times and sets the timing for transitions into the “sniff” mode. In this application. They are Active. shows an application where the “Clk Out” pin provides the clock for the MPU. Figure 117. 48 MOTOROLA ANALOG IC DEVICE DATA . Power Saving Mode Selection “CD Out/ Hardware Interrupt” Pin ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Stdby Mode Bit Rx Mode Bit Power Saving Mode MC13110A/MC13111A 0 0 1 1 1 0 1 0 1 1 X X X Active Rx Standby Inactive 1 or High Impedance 0 Interrupt MC13110B/MC13111B [Note 14] 0 0 1 1 0 1 X X X 0 Active Rx X 1 Standby Interrupt NOTES: 13. In the Rx mode. Rx.5 this will reduce the MPU clock frequency and save power in the MPU. The MC13110B/MC13111B has three modes of operation. Active. Latch memory is maintained in all modes. all circuitry is powered down except the MPU serial interface. all circuitry is powered down except for the circuitry needed to provide the clock output for the microprocessor. 80. 128 or 512 kHz Standby Mode “Sniff” Rx Mode 4. The “CD Out” pin has a dual function. In the Inactive mode.8. the “CD Out” pin is the input for the hardware interrupt function. First put the MC13110A/MC13111A into the Inactive mode. The MPU can then resume control of the IC.MC13110A/B MC13111A/B Power Saving Application – Option 2 (MC13110A and MC13111A Only) In some handset applications it may be desirable to power down all circuitry including the microprocessor (MPU). the MPU Clock output will remain active for a minimum of one reference counter cycle (about 200 µs) and up to a maximum of two reference counter cycles (about 400 µs).0 MHz MOTOROLA ANALOG IC DEVICE DATA 49 . Thereby turning on the MPU Clock Output. An external timing circuit should be used to initiate the turn–on sequence. the IC switches from the Inactive to the Interrupt mode. This turns off the MPU Clock Output (see Figure 120) and disables the microprocessor. Figure 119. Once a command is given to switch the IC into an “Inactive” mode. or Rx modes. because of an external pull–up resistor. The “CD Out” pin must remain low until the MPU changes the operating mode from Interrupt to Standby. This is performed in order to give the MPU adequate time to power down. Power Saving Application – Option 1 MC13110B MC13111B Clk Out Clk In Microprocessor Timer MPU Clk Divider SPI Port SPI Port LO2 Out LO2 In “Low Power” Mode MPU Timer MPU Clock Out 32. Active. In the Standby and Inactive modes the carrier detect circuit is disabled and the “CD Out” pin is in a “High” state. In the Active and Rx modes it performs the carrier detect function. by the external timing circuit. When the “CD Out” pin is pulled “low”. This will eliminate the need for a separate crystal to drive the MPU.460 MHz 4.24 MHz crystal.560 MHz 2.000 MHz 2. Clock Output Values Clock Output Divider 4 5 Crystal Frequency 10.5 5. CD Out Low Standby/Rx/Active MPU Initiates Mode Change External Timer Pulls Pin Low CD Turns Off Timer Output Disabled “MPU Clock Out” remains active for a minimum of one count of reference counter after “CD Out/Hardware Interrupt” pin goes high MPU “Clk Out” Divider Programming The “Clk Out” signal is derived from the second local oscillator. Power Saving Application – Option 2 (MC13110A/MC13111A Only) MC13110A/ MC13111A Clk Out Clk In Microprocessor MPU Clk Divider SPI Port SPI Port LO2 Out Interrupt LO2 In CD Out/ HW Interrupt VCC External Timer Mode Active/Rx Inactive MPU Initiates Inactive Mode Interrupt EN CD Out/Hardware Interrupt MPU Clock Out Delay after MPU selects Inactive Mode to when CD turns off.575 MHz 6.413 MHz 3.000 MHz 2.00 MHz 50 MOTOROLA ANALOG IC DEVICE DATA .400 kHz 12.048 MHz 2. the divide by 312.680 kHz 38.768 kHz 35.400 MHz 512 kHz 557 kHz 600 kHz 128 kHz 139 kHz 150 kHz 32. Figure 121 shows the relationship between the second LO crystal frequency and the clock output for each divide value.096 MHz 4. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ Figure 121.5 gives the same clock frequency as a clock crystal and allows the MPU to display the time on a LCD display without additional external components. thus reducing system cost.800 MHz 3.788 MHz 3.120 MHz 5.15 MHz 2 2.5 3 20 80 312.717 MHz 4. Figure 122 shows the “Clk Out” register bit values.230 MHz 2.MC13110A/B MC13111A/B Figure 120.24 MHz 11. It can be used to drive a microprocessor (MPU) clock input.000 MHz 4. With a 10. This filter should significantly reduce noise radiated by attenuating the high frequency harmonics on the signal line. Special care was taken in the design of the clock divider to insure that the MPU “Clk Out” Radiated Noise on Circuit Board The clock line running between the MC13110A/B or MC13111A/B and the microprocessor has the potential to radiate noise.e. the MPU can change the clock divider value and set the clock to the desired operating frequency. Volume Control Volume Control Bit #3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Volume Control Bit #2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Volume Control Bit #1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Volume Control Bit #0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Volume Control # 0 1 2 3 4 5 6 7 8 9 Gain/Attenuation Amount –14 dB –12 dB –10 dB – 8 dB – 6 dB – 4 dB – 2 dB 0 dB 2 dB 4 dB 6 dB 8 dB 10 11 12 13 14 15 10 dB 12 dB 14 dB 16 dB MOTOROLA ANALOG IC DEVICE DATA 51 . A small capacitor or inductor with a capacitor can be connected to the “Clk Out” line on the PCB to form a one or two pole low pass filter. MPU “Clk Out” Power–Up Default Divider Value The power–up default divider value is “divide by 5”. To further reduce radiated noise. The filter can also be used to attenuate the signal level so that it is only as large as required by the MPU clock input. The reason for choosing a relatively low clock frequency at initial power–up is because some microprocessors operate using a 3. Clock Output Divider MPU Clk Bit #1 0 0 1 1 0 0 1 1 MPU Clk Bit #0 0 1 0 1 0 1 0 1 MPU Clk Bit #2 0 0 0 0 1 1 1 1 Clk Out Divider Value 2 3 4 5 2.ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ Figure 122. especially if the clock is a square wave digital signal with large high frequency harmonics. This provides a MPU clock of about 2. Volume Control Programming The volume control adjustable gain block can be programmed in 2 dB gain steps from –14 dB to +16 dB. the PCB signal trace length should be kept to a minimum.5 MC13110A/B MC13111A/B transition between one clock divider value and another is “smooth” (i.5 20 80 312. The power–up default value for the MC13110A/B and MC13111A/B is 0 dB.0 V power supply and have a maximum clock frequency of 2.0 MHz after initial power–up. (see Figure 123) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ Figure 123. there will be no narrow clock pulses to disturb the MPU). In order to minimize the radiated noise. a 1000 Ω resistor is included on–chip in series with the “Clk Out” output driver. Problems in the system can occur.0 MHz. After initial power–up. it can be programmed through the MPU interface. If a Tx or Rx voltage gain. Alternately. these programmable gain blocks can be used during final test of the telephone to electronically adjust for gain tolerances in the telephone system (see Figure 125). Operation of these latch bits are explained in Figures 124. is desired. In this case. 125 and 126. Gain Control Latch Bits 0 5–b Tx Gain Control 5–b Rx Gain Control 5–b CD Threshold Control ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁ Figure 125. Rx Voltage Gain. Figure 124. the Tx and Rx gain register values should be stored in ROM during final test so that they can be reloaded each time the IC is powered up. and Carrier Detect threshold. other than the nominal power–up default. Tx and Rx Gain Control Gain Control Bit #1 – 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 – Gain Control Bit #4 – 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 – Gain Control Bit #3 – 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 – Gain Control Bit #2 – 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 – Gain Control Bit #0 – 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 – Gain Control # <6 6 7 8 9 Gain/Attenuation Amount –9 dB –9 dB –8 dB –7 dB –6 dB –5 dB –4 dB –3 dB –2 dB –1 dB 0 dB 1 dB 2 dB 3 dB 4 dB 5 dB 6 dB 7 dB 8 dB 9 dB 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 10 dB 10 dB >25 52 MOTOROLA ANALOG IC DEVICE DATA . Tx and Rx Gain Programming The T x and R x audio signal paths each have a programmable gain block.MC13110A/B MC13111A/B Gain Control Register The gain control register contains bits which control the Tx Voltage Gain. MC13110A/B MC13111A/B Carrier Detect Threshold Programming The “CD Out” pin gives an indication to the microprocessor if a carrier signal is present on the selected channel. The internal resistor is 187 kΩ. The nominal value and tolerance of the carrier detect threshold is given in the carrier detect specification section of this document. In this case. If a preamp is used before the first mixer it may be desirable to scale the carrier detect range by connecting an external resistor from the “RSSI” pin to ground. If a different carrier detect threshold value is desired. it is necessary to store the carrier detect register value in ROM so that the CD register can be reloaded each time the combo IC is powered up. Alternately. Carrier Detect Threshold Control CD Bit #1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 CD Bit #0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CD Bit #4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CD Bit #3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CD Bit #2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CD Control # 0 1 2 3 4 5 6 7 8 9 Carrier Detect Threshold – 20 dB –19 dB –18 dB –17 dB –16 dB –15 dB –14 dB –13 dB –12 dB –11 dB 10 11 –10 dB – 9 dB – 8 dB –7 dB 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 – 6 dB – 5 dB – 4 dB – 3 dB – 2 dB –1 dB 0 dB 1 dB 2 dB 3 dB 4 dB 5 dB 6 dB 7 dB 8 dB 9 dB 10 dB 11 dB MOTOROLA ANALOG IC DEVICE DATA 53 . it can be programmed through the MPU interface as shown in Figure 126 below. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Figure 126. the carrier detect threshold can be electronically adjusted during final test of the telephone to reduce the tolerance of the carrier detect threshold. This is done by measuring the threshold and then by adjusting the threshold through the MPU interface. 375 3. In the programmable threshold mode.200 3. Figure 129. However. In this mode. and the scrambler bypass mode (MC13110A/B only). Note the power–up default bit is set to <0>. Low Battery Detect Threshold Selection Low Battery Detect Threshold Select Bit #0 0 1 0 1 0 1 0 1 Low Battery Detect Threshold Select Bit #2 0 0 0 0 1 1 1 1 Low Battery Detect Threshold Select Bit #1 0 0 1 1 0 0 1 1 Select # 0 1 2 3 4 5 6 7 Operating Mode Nominal Low Battery Detect Threshold Value (V) N/A Non–Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable 2. these bits are defined. Figure 129 describes the operation. the voltage reference adjust.288 3. The power–on default value for this register is <0. Figure 127. which is the scrambler bypass mode. for the MC13110A/B.938 3.463 NOTE: 17. Nominal Threshold Value is before electronic adjustment. there are two low battery detect comparators and the threshold values are set by external resistor dividers which are connected to the REF1 and REF2 pins.0. MC13110A/B Bypass Mode Bit Description (MC13110A/B Only) 1 0 1 0 Tx Scrambler Tx Scrambler Post–Mixer LPF and Mixer Bypassed Bypass Normal Operation with Tx Scrambler Rx Scrambler Bypass Rx Scrambler Post–Mixer LPF and Mixer Bypassed Normal Operation Rx Scrambler 54 MOTOROLA ANALOG IC DEVICE DATA .MC13110A/B MC13111A/B Clock Divider/Voltage Adjust Register This register controls the divider value for the programmable switched capacitor filter clock divider. several different threshold levels may be selected through the “Low Battery Detect Threshold Register” as shown in Figure 128. Low Battery Detect The low battery detect circuit can be operated in programmable and non–programmable threshold modes. The Tx and Rx Audio bits are don’t cares for either the MC13111A or the MC13111B device.025 3. Clock Divider/Voltage Adjust Latch Bits 3–b Low Battery Detect Threshold Select 4–b Voltage Reference Adjust Tx Sbl Bypass Rx Sbl Bypass 6–b Switched Capacitor Filter Clock Counter Latch 0 MSB LSB MSB LSB (MC13110A/B) 0 3–b Low Battery Detect Threshold Select MSB 4–b Voltage Reference Adjust LSB 0 0 MSB 6–b Switched Capacitor Filter Clock Counter Latch LSB (MC13111A/B) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁ Figure 128. Operation is explained in Figures 127 through 134.850 2. the low battery detect threshold select.0> and is the non–programmable mode. The non–programmable threshold mode is only available in the 52 QFP package. Figure 130 shows equivalent schematics for the programmable and non–programmable operating modes. Low Battery Detect Equivalent Schematics Ref2 50 BD2 Out 16 Ref 1 51 BD1 Out 14 VB 52 Vref Non–Programmable Threshold Mode: 52–QFP Package VCC Audio 21 VCC Audio 23 BD Out 14 BD2 Out 16 VB 47 Vref VB 52 Vref Programmable Threshold Mode: 48–LQFP Package Programmable Threshold Mode: 52–QFP Package MOTOROLA ANALOG IC DEVICE DATA 55 .MC13110A/B MC13111A/B Figure 130. 240 MHz 2nd LO MC13110A/B MC13111A/B SCF Clock Divider 29 30 31 32 Total Divide Value 58 60 62 64 SCF Clock Freq. It is important to note.758 Tx Upper Corner Frequency (kHz) 3.414 4.2 258. This is based on the 2nd LO frequency which is chosen in Figure 114. Vref Adj.6 % +7. Figure 133.008 3.16 kHz as possible. and all internal analog ground references.55 170.67 165. Vref Adj. the “PLL Vref” voltage regulator.000 Scrambler Lower Corner Frequency (Hz) 267. Then.0% –1.0 SCF Clock LO2 Out MC13110A/B only Divide By 40 Scrambler Modulation Clock +0.902 3.MC13110A/B MC13111A/B Voltage Reference Adjustment An internal 1. Amount –9. Vref Adj.700 3 584 3.0% –7. The initial tolerance of the bandgap voltage reference is ±6%.5 V bandgap voltage reference provides the voltage reference for the “BD1 Out” and “BD2 Out” low battery detect circuits.0 % 10 11 12 13 14 15 Corner Frequency Programming for MC13110A/B and MC13111A/B Four different corner frequencies may be selected by programming the SCF Clock divider as shown in Figures 133 and 134.879 3 758 3.2 Scrambler Upper Corner Frequency (kHz) 3. the internal reference voltage value is adjusted electronically through the MPU serial interface to achieve the desired accuracy level.0 242 2 242. The tolerance of the internal reference voltage can be improved to ±1.2% –3.147 4.4 % +6. 19. The switched capacitor filter clock value is given by the following equation. Bandgap Voltage Reference Adjustment Switched Capacitor Filter Clock Programming A block diagram of the switched capacitor filter clock divider is show in Figure 132.6% LO2 In 2nd LO Crystal 6–b Programmable SCF Clock Counter Divide By 2. The scrambler modulation clock frequency (SMCF) is proportional to the SCF clock.2 % +5.4% –4. The following equation defines its value: SMCF = (SCF Clock)/40 The SCF divider should be set to a value which brings the SCF Clock as close to 165.3 250. Bit #3 Bit #2 Bit #1 Bit #0 # 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 8 9 Vref Adj.823 3.955 3.6% –5. The power–up default SCF Clock divider value is 31.0 % +4. Figure 131.5% through MPU serial interface programming. Rx and Tx Upper Corner Frequencies are the same corner frequencies for the MC13110A/B in scrambler bypass 56 MOTOROLA ANALOG IC DEVICE DATA .6 % +1.8% –6. Corner Frequency Programming for 10.16 160 00 160.772 3. There is a fixed divide by 2 after the programmable divider. Vref Adj. the “VB” reference.8% –0. that all filter corner frequencies will change proportionately with the SCF Clock Frequency and Scrambler Modulation Frequency.650 3 536 3. SCF Clock Divider Circuit ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Vref Adj. The voltage reference register value should be stored in ROM during final test so that it can be reloaded each time the MC13110A/B or MC13111A/B is powered up (see Figure 131). Figure 132.584 Scrambler Modulation Frequency (Clk/40) (kHz) 4.00 Rx Upper Corner Frequency (kHz) 4. (kHz) 176.129 4 000 4. All filter corner frequencies have a tolerance of ±3%.536 NOTE: 18. During final test of the telephone.8 % +9. (SCF Clock) = F(2nd LO) / (SCF Divider Value * 2). the battery detect threshold is measured.267 4.8 % +3. 1 241 1 Scrambler Upper Corner Frequency (kHz) 3. 21. The temperature coefficient of the internal programmable capacitor is negligible. Corner Frequency Programming for 11.15 MHz 2nd LO MC13111A/B SCF Clock Divider 32 33 34 35 Total Divide Value 64 66 68 70 SCF Clock Freq. Digital Test Mode Description “Tx VCO” Input Signal >200 mVpp 0 to 2.7 255.568 3 568 Scrambler Modulation Frequency (Clk/40) (kHz) 4.7 248.850 3. the “Tx VCO” input pin is multiplexed to the input of the counter under test. During normal operation.673 3.29 159 29 Rx Upper Corner Frequency (kHz) 4.5 V 0 to 2.785 3. First Local Oscillator Programmable Capacitor Selection There is a very large frequency difference between the minimum and maximum channel frequencies in the 25 Channel U.5 V 0 to 2. standard.982 3 982 Scrambler Lower Corner Frequency (Hz) 263. The output of the counter under test is multiplexed to the “Clk Out” output pin so that each counter can be individually tested. 136 and 137. (kHz) 174.2 241. Auxiliary Register Latch Bits 0 0 0 0 0 0 0 0 0 MSB 3–b Test Mode LSB MSB 4–b 1st LO Capacitor Selection LSB ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁ Figure 136.741 3 741 Tx Upper Corner Frequency (kHz) 3.733 3.5 V N/A N/A TM # 0 1 2 3 4 5 6 TM 2 0 0 0 0 1 1 1 TM 1 0 0 1 1 0 0 1 TM 0 0 1 0 1 0 1 0 Counter Under Test or Test Mode Option “Clk Out” Output Expected Normal Operation Rx Counter Tx Counter – Input Frequency/Rx Counter Value Input Frequency/Tx Counter Value Reference Counter + Divide by 4/25 SC Counter Input Frequency/Reference Counter Value * 100 Input Frequency/SC Counter Value * 2 N/A N/A ALC Gain = 10 Option ALC Gain = 25 Option Auxiliary Register The auxiliary register contains a 4–bit First LO Capacitor Selection latch and a 3–bit Test Mode latch. The internal varactor adjustment range is not large enough to accommodate this large frequency span.520 3 520 NOTES: 20. All filter corner frequencies have a tolerance of ±3%.S.092 3.099 3. MOTOROLA ANALOG IC DEVICE DATA 57 .ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ MC13110A/B MC13111A/B MC13110A/B Figure 134.355 4.903 3. Tolerance on the varactor and programmable capacitor values is ±15%. Figure 32 shows the schematic of the 1st LO tank circuit.08%/°C. Figure 137 shows the register control bit values. Rx and Tx Upper Corner Frequencies are the same corner frequencies for the MC13110A/B in scrambler bypass Figure 135.5 V 0 to 2.968 3.94 163. An internal capacitor with 15 programmable capacitor values can be used to cover the 25 channel frequency span without the need to add external capacitors and switches. Make sure test mode bits are set to “0’s” for normal operation. Operation of these latch bits are explained in Figures 135. The temperature coefficient of the varactor is 0. Test Modes Test modes are be selected through the 3–bit Test Mode Register.22 168.97 159.624 3. Input signals should be standard logic levels of 0 to 2. In test mode. The internal parallel resistance values in the table can be used to calculate the quality factor (Q) of the oscillator if the Q of the external inductor is known.1 pF. The internal programmable capacitor is composed of a matrix bank of capacitors that are switched in as desired. Programmable capacitor values between about 0 and 16 pF can be selected in steps of approximately 1. The programmable internal capacitor can also be used to eliminate the need to use an external variable capacitor to adjust the 1st LO center frequency during telephone assembly.5 V and a maximum frequency of 16 MHz. Test mode operation is described in Figure 136. the “Tx VCO” input can be a minimum of 200 mVpp at 80 MHz and should be AC coupled.223 4.851 3. ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁ Figure 137. First Local Oscillator Internal Capacitor Selection Internal Programmable Capacitor Value (pF) 0.0 0.6 1.7 2.8 3.9 4.9 6.0 7.1 8.2 9.4 1st LO Cap. Bit 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1st LO Cap. Bit 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1st LO Cap. Bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1st LO Cap. Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1st LO Cap. Select 0 1 2 3 4 5 6 7 8 9 Varactor Value over 0.3 to 2.5 V (pF) 9.7 to 5.8 9.7 to 5.8 9.7 to 5.8 9.7 to 5.8 9.7 to 5.8 9.7 to 5.8 9.7 to 5.8 9.7 to 5.8 9.7 to 5.8 9.7 to 5.8 9.7 to 5.8 9.7 to 5.8 9.7 to 5.8 9.7 to 5.8 9.7 to 5.8 9.7 to 5.8 Equivalent Internal Parallel Resistance at 40 MHz (kΩ) 1200 79.3 131 Equivalent Internal Parallel Resistance at 51 MHz (kΩ) 736 48.8 80.8 19.3 20.8 41 31.4 33.8 66.6 49.9 40.7 27.1 21.6 20.5 18.6 17.2 15.8 15.3 14.2 30.7 25.1 16.7 13.3 12.6 11.5 10 11 10.5 11.6 12 13 14 15 12.7 13.8 14.9 16.0 10.6 9.7 9.4 8.7 MC13110A/B MC13111A/B 58 MOTOROLA ANALOG IC DEVICE DATA MC13110A/B MC13111A/B OTHER APPLICATIONS INFORMATION PCB Board Lay–Out Considerations The ideal printed circuit board (PCB) lay out would be double–sided with a full ground plane on one side. The ground plane would be divided into separate sections to prevent any audio signal from feeding into the first local oscillator via the ground plane. Leaded components, can likewise, be inserted on the ground plane side to improve shielding and isolation from the circuit side of the PCB. The opposite side of the PCB is typically the circuit side. It has the interconnect traces and surface mount components. In cases where cost allows, it may be beneficial to use multi–layer boards to further improve isolation of components and sensitive sections (i.e. RF and audio). For the CT–0 band, it is also permissible to use single–sided PC layouts, but with continuous full ground fill in and around the components. The proper placement of certain components specified in the application circuit may be very critical. In a lay–out design, these components should be placed before the other less critical components are inserted. It is also imperative that all RF paths be kept as short as possible. Finally, the MC13110A/B and MC13111A/B ground pins should be tied to ground at the pins and VCC pins should have adequate decoupling to ground as close to the IC as possible. In mixed mode systems where digital and RF/Analog circuitry are present, the VCC and VEE buses need to be ac–decoupled and isolated from each other. The design must also take great caution to avoid interference with low level analog circuits. The receiver can be particularly susceptible to interference as they respond to signals of only a few microvolts. Again, be sure to keep the dc supply lines for the digital and analog portions separate. Avoid ground paths carrying common digital and analog currents, as well. Component Selection The evaluation circuit schematics specify particular components that were used to achieve the results shown in the typical curves and tables, but alternate components should give similar results. The MC13110A/B and MC13111A /B IC are capable of matching the sensitivity, IMD, adjacent channel rejection, and other performance criteria of a multi–chip analog cordless telephone system. For the most part, the same external components are used as in the multi–chip solution. VB and PLL Vref VB is an internally generated bandgap voltage. It functions as an ac reference point for the operational amplifiers in the audio section as well as for the battery detect circuitry. This pin needs to be sufficiently filtered to reduce noise and prevent crosstalk between Rx audio to Tx audio signal paths. A practical capacitor range to choose that will minimize crosstalk and noise relative to start up time is 0.5 µf to 10 µf. The start time for a 0.5 µf capacitor is approximately 5.0 ms, while a 10µf capacitor is about 10 ms. The “PLL Vref” pin is the internal supply voltage for the Rx and Tx PLL’s. It is regulated to a nominal 2.5 V. The “VCC Audio” pin is the supply voltage for the internal voltage regulator. Two capacitors with 10 µF and 0.01 µF values must be connected to the “PLL Vref” pin to filter and stabilize this regulated voltage. The “PLL Vref” pin may be used to power other IC’s as long as the total external load current does not exceed 1.0 mA. The tolerance of the regulated voltage is initially ±8.0%, but is improved to ±4.0% after the internal Bandgap voltage reference is adjusted electronically through the MPU serial interface. The voltage regulator is turned off in the Standby and Inactive modes to reduce current drain. In these modes, the “PLL Vref” pin is internally connected to the “VCC Audio” pin (i.e., the power supply voltage is maintained but is now unregulated). It is important to note that the momentary drop in voltage below 2.5 V during this transition may affect initial PLL lock times and also may trigger the reset. To prevent this, the PLL Vref capacitor described above should be kept the same or larger than the VB capacitor, say 10 µf as shown in the evaluation and application diagrams. DC Coupling Choosing the right coupling capacitors for the compander is also critical. The coupling capacitors will have an affect on the audio distortion, especially at lower audio frequencies. A useful capacitor range for the compander timing capacitors is 0.1 µf to 1.0 µf. It is advised to keep the compander capacitors the same value in both the handset and baseset applications. All other dc coupling capacitors in the audio section will form high pass filters. The designer should choose the overall cut off frequency (–3.0 dB) to be around 200 Hz. Designing for lower cut off frequencies may add unnecessary cost and capacitor size to the design, while selecting too high of a cut off frequency may affect audio quality. It is not necessary or advised to design each audio coupling capacitors for the same cut off frequency. Design for the overall system cut off frequency. (Note: Do not expect the application, evaluation, nor production test schematics to necessarily be the correct capacitor selections.) The goals of these boards may be different than the systems approach a designer must consider. For the supply pins (VCC Audio and VCC RF) choose a 10 µf in parallel with a high quality 0.01 µf capacitor. Separation of the these two supply planes is essential, too. This is to prevent interference between the RF and audio sections. It is always a good design practice to add additional coupling on each supply plane to ground as well. The IF limiter capacitors are recommended to be 0.1 µf. Smaller values lower the gain of the limiter stage. The –3.0 dB limiting sensitivity and SINAD may be adversely affected. MOTOROLA ANALOG IC DEVICE DATA 59 Figure 138. Evaluation Board Schematic Mix1 Out Mix 2 In BNC C37 0.01 C31 0.1 C30 0.1 R28 txt L1 txt C53 1000 C54 0.01 C55 10 µ F1 txt R37 txt C28 txt F2 txt R34 txt C35 0.01 BNC Mix 2 Out Lim In R53 47 C38 0.01 T1 txt C39 0.01 R39 49.9 36 Gnd RF C26 0.047 C24 0.01 42 Vcap Ctrl R44 150 43 Gnd Audio C44 47 µ 44 SA Out 45 SA In C46 0.1 46 E Out C47 0.47 47 E Cap C48 0.47 48 E In VCC 49 Scr Out 50 Ref 2 51 Ref 1 52 VB LO2 LO2 In Out 1 2 Vag 3 XC txt Rx PD 4 PLL Vref 5 C5a 0.01 Tx PD 6 Gnd Tx PLL VCO 7 8 R51a 82 k R50a 110 k VCC Tx Out 17 BD2 Out 16 DA Out 15 R14 100 k Data 9 R9 10 k EN 10 R10 10 k Clk 11 Clk CD BD1 14 Out Out Out 12 13 R11 10 k R13 100 k VCC C1 txt C2 txt C3 0.1 C5b 10 µ Connector Controllor Rx PD PLL Vref Tx PD Tx VCO VCC R16 100 k Tx Out VCC BD 2 Out DA Out BD 1 Out C Cap 18 VCC C45 220 p R46 47 k R45 47 k VCC Audio 23 DA In 22 R21 47 k C21 0.1 Tx In 21 R20 47 k Amp Out 20 C In 19 C19 0.1 C18 0.47 VCC C20 220 p Tx In Amp Out DA In Rx Audio In 24 C23a 0.01 C23b 10 µ Det Out 25 35 Mix 2 Out 34 33 Mix 2 SGnd In RF 32 Lim In 31 Lim C1 30 Lim C2 29 VCC RF 28 Lim Out 27 Q Coil 26 RSSI 60 VCC Gnd RSSI BNC Det Out R40 49.9 T2–L2 txt 39 38 37 Mix 1 Mix 1 Mix 1 In 2 Out In 1 40 LO1 In C40 txt 41 LO1 Out BNC RF In1 BNC RF In 2 BNC LO 2 In Vcap Ctrl SA Out APPENDIX A E Out MC13110A MC13111A MC13110A/B MC13111A/B Scr Out R51b 100 k R50b 100 k C52 10 µ R42a txt R4a txt Figure 138. C42b txt C42a txt R42b txt R4b txt C4 txt txt: see text Clk Out CD Out MOTOROLA ANALOG IC DEVICE DATA 15 C1 = 18 p 33 p 15 p + 5–25 p 11.082 HS: 0 BS: 0 HS: 0 BS: 0 HS: 8600 BS: 6800 HS: 100 k BS: 100 k HS: 18 k BS: 22 k HS: 1000 BS: 1000 HS: 0.S.01 0.01 Toko 1:5 292GNS–765A0 n. n.47 Toko T1370 HS: 27 pF BS: 22 pF 0.068 MOTOROLA ANALOG IC DEVICE DATA 61 . RF (50 Ω) RF Matched M h d RF Crystal y (50 Ω) French Application Base RF Ceramic (50 Ω) RF Matched M h d LOOP FILTER HANDSET/BASESET R4a R4b C4 R42a R42b C42a C42b HS: 0 BS: 0 HS: 0 BS: 0 HS: 6800 BS: 8200 HS: 100 k BS: 100 k HS: 22 k BS: 18 k HS: 1000 BS: 1000 HS: 0. Evaluation Board Bill of Materials for U.7 k 390 p 4 Element Murata E 4 Element Murata E 4 Element Murata G 4 Element Murata G 4 Element Murata G Ceramic 0 360 Ceramic 0 360 Crystal 1. n.7 k 390 p Ceramic Murata CDBM 450C34 2.2 k 3.01 0.082 BS: 0. 0.m.068 BS: 0.m. n.7 MHz FILTER F1 R37 R34 450 kHz FILTER F2 DEMODULATOR L1 R28 C28 OSCILLATOR Xtal C2 C1 FIRST LO L2 C40 HS/BS 0.7 k 390 p Ceramic Murata CDBM 450C34 2. N Number b INPUT MATCHING T1 C38 C39 10. 0.m.15 C1 = 18 p 33 p 15 p + 5–25 p Q Coil Toko 7MCS–8128Z 22.1 k 10 p Q Coil Toko 7MCS–8128Z 22.22 Toko T1368 BS: 100 p HS: 68 pF 0. and French Application USA Application Handset C Comp.01 0.082 BS: 0.068 HS: 0 BS: 0 HS: 0 BS: 0 HS: 8600 BS: 6800 HS: 100 k BS: 100 k HS: 18 k BS: 22 k HS: 1000 BS: 1000 HS: 0.24 C1 = 10 p 18 p 5–25 p 10.082 HS: 0 BS: 0 HS: 0 BS: 0 HS: 6800 BS: 8200 HS: 100 k BS: 100 k HS: 22 k BS: 18 k HS: 1000 BS: 1000 HS: 0.1 k 10 p Ceramic Murata CDBM 450C34 2.m.m.22 Toko T1368 BS: 100 p HS: 68 pF 0.01 n.m.47 Toko T1370 HS: 27 pF BS: 22 pF 0. 0.01 k Ceramic 0 360 Ceramic 0 360 n.082 BS: 0.24 C1 = 10 p 18 p 5–25 p 11.01 Toko 1:5 292GNS–765A0 n.15 C1 = 18 p 33 p 15 p + 5–25 p 11.068 BS: 0.22 Toko T1368 BS: 100 p HS: 68 pF 10.MC13110A/B MC13111A/B APPENDIX A Figure 139.068 HS: 0 BS: 0 HS: 0 BS: 0 HS: 8600 BS: 6800 HS: 100 k BS: 100 k HS: 18 k BS: 22 k HS: 1000 BS: 1000 HS: 0.m. R x G n d A n t G n d G n d T x 1 2 3 4 5 6 Gnd C87 1000 10 µ F C84 0.1 R28 27 k R30 680 k C33 VCC –A Tx Audio RSSI R33 47 k C88 0.47 47 SA In E Out C30 62 Figure 140.033 P35 RF Input Duplexer Figure 140.01 24 23 22 21 20 19 18 17 16 15 14 5 6 7 8 R20 9 10 k 10 11 12 13 R23 R24 100 k 3 4 100 k 0.7 µ F Gnd Gnd R17 1.10 0.0–25 X1 18 10.47 33 0.2 k C35 0.01 R32 8.1 VCC –A 0.9 k + C32 R27 1.47 µ H 0.047 C31 VCC 10 µF Gnd Mic1 Mic Electret Gnd 39 38 37 36 35 34 33 32 31 30 29 28 27 40 41 42 43 Gnd Audio SA Out R F I n C 1 C 2 R F Mix 1 In 1 M i LO1 In x 1 LO1 Out I n 2 Vcap Ctrl M i x 1 O u t G n d M i x 2 O u t M i x 2 I n S G N D R F L i m L i m L i m V C C C5 22 26 25 L3 0.47 C13 49 50 51 C15 0.01 + C23 C24 10 µ F 3.01 R4 220 Tx RF–In 8128Z APPLICATIONS CIRCUIT C12 48 E In Scr Out Ref 2 P L L Ecap IC1 MC13110A/B MC13111A/B 3300 Gnd Batt Dead R x Data Low Batt Car–Detect 6800 C9 45 R7 47 k 220 46 0.0 k Gnd 0.01 C71 + 10 µ F Gnd R3 220 VCC–RF Gnd P1 T1 S1 S2 3 R34 22 k FL1 2 P2 P3 Gnd R2 100 k C2 R36 330 47 VCC–RF C3 0.1 2 C74 C73 0.15 FL2 R1 33 k C4 0.0 k + C25 22 µ F C7 10 1000 MOTOROLA ANALOG IC DEVICE DATA Legend: If ≥1.068 30 8200 18 k + C22 0.047 SP1 150–300 Ω R8 47 k C10 0.1 Clk Out Clk EN Data 100 k Tx VT + Gnd C26 4. then capacitor value = pF If <1.10 1 C89 L i m O u t Rx Audio In VCC Audio DA In Tx In Amp Out C In C Cap Tx Out BD 2 Out G n d T x V r e f P D P D C l k P L L T x V C O R x V a g D a t a E N C l k O u t DA Out BD 1 Out CD Out Det Out Q Coil RSSI Q1 8519N MPSH10 T2 1 3 C70 10 C86 0. Basic Cordless Telephone Transceiver Application Circuit 1000 C72 0.3 µ F Gnd R21 Tx VCO R18 680 10 k R19 18 k R25 100 k VCC C34 C29 C28 0.1 1 2 Gnd C18 5.0.1 C19 C27 10 R22 10 k C17 R16 0. then capacitor value = µ F .01 R29 27 k R26 VCC–A R31 47 3.24 R13 R11 100 k 100 k VB 52 C14 10 µ F Ref 1 L O VB 2 I n L O 2 O u t C6 47 µ F 44 + Speaker APPENDIX B Gnd MC13110A/B MC13111A/B R10 110 k VCC –A R12 82 k C16 0. 1 µ F C37 6800 2 3 4 R37 22 k C38 8. Basic Cordless Telephone Transceiver Application Circuit (continued) VCC + C57 2.1 Batt1 V+ V– C54 + 10 µ F C53 0.5 k RF Osc RF Output Tr 2 Base Tr 2 Emitter Tx VCO Gnd R46 220 k R47 75 k C50 R45 110 0.5 P3 T3 S1 C41 51 51 Ω C51 Tr 2 Collector VCC Tr 1 Collector R44 110 0.022 C40 10 R41 27 k R42 91 k S2 13630 Tx RF–In MOTOROLA ANALOG IC DEVICE DATA 63 .MC13110A/B MC13111A/B APPENDIX B Figure 140.22 Gnd C58 10 µ F + VCC –A C56 0.0 C48 120 U5 1 R53 68 k C60 0.0 5 6 7 R39 110 k Tx Data 8 Variable Reactance Output Decoupling Modulator Input Mic Amp Output Mic Amp Input Gnd Tr 1 Emitter Tr 1 Base RF Osc C59 180 Tx VT L4 0.022 VCC R51 110 k IC2 MC2833D R49 100 C44 4700 0.022 R43 C52 110 0.22 µ H L5 C43 51 P1 Cx P2 7.22 µ H Tx Audio R54 100 k 1 2 2109 VR2 16 15 14 13 12 11 10 9 C46 36 C45 10 C47 36 R50 1.2 µ F Gnd VCC –RF C55 0.01 VRx L6 56 µ H Gnd Gnd C49 2. 57X of the final steady state value. decay time is defined as the time for the input to settle to 0.5X Final Value Output 1.0 dB Input 12 dB Input 0 mV 0 mV Attack Time Decay Time Attack Time Decay Time 0.5X Final Value Output 0.0 dB step down at the input.MC13110A/B MC13111A/B APPENDIX C – MEASUREMENT OF COMPANDER ATTACK/DECAY TIME This measurement definition is based on EIA/CCITT recommendations. attack time is defined as the time for the output to settle to 0. Compressor Decay Time For a 12 dB step down at the input. Expander Decay For a 6. 6.5X of the final steady state value.5X of the final steady state value. attack time is defined as the time for the output to settle to 1. Compressor Attack Time For a 12 dB step up at the input.75X of the final steady state value.0 dB step up at the input. Expander Attack For a 6.57X Final Value 1.75X Final Value 0 mV 0 mV 64 MOTOROLA ANALOG IC DEVICE DATA . decay time is defined as the time for the output to settle to 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.004) H G M_ –C– SEATING PLANE U_ R Q_ T W X DETAIL C K DIM A B C D E F G H J K L M N Q R S T U V W X MOTOROLA ANALOG IC DEVICE DATA 65 . DATUMS –A–. 7.018 0.08 (0.38 2.5M.13 0.10 2.20 (0.009 0.307 REF 5_ 10_ 0.063 REF C A–B S D S C E M_ DETAIL C –H– DATUM PLANE 0.17 0_ 7_ 0.510 0. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION.009 0.MC13110A/B MC13111A/B OUTLINE DIMENSIONS FB SUFFIX PLASTIC PACKAGE CASE 848B–04 (QFP–52) ISSUE C L B B 39 40 27 26 S S D D –A–. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.02 (0.30 12.398 0.20 (0.25 (0.079 0. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.6 REF INCHES MIN MAX 0.65 BSC ––– 0.002) A–B V C A–B S F M 0.35 0.008) M C A–B S D S S D S SECTION B–B NOTES: 1.026 BSC ––– 0. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –C–.026 0.083 0.530 0.008) M D 0.22 0.008) M J N 52 1 13 14 BASE METAL –D– B 0.65 0.390 0. 2. 6. 3.008) M H A–B 0.80 REF 5_ 10_ 0.10 2.45 0.005 0.13 0.20 (0.95 13.95 13. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –H–.95 7.25 0.013 0.390 0.398 0.008) 0.05 (0.009 0.45 0. 4.510 0.012 0.010 0.014 0.015 0.096 0. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.22 0.45 0.083 0. 5.007 0_ 7_ 0.33 0.010) PER SIDE.00 2.003) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.13 0. –D– DETAIL A DETAIL A –A– L –B– B S H A–B 0.10 0. MILLIMETERS MIN MAX 9. 1982.20 (0.530 0. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE.10 9.45 1. –B– AND –D– TO BE DETERMINED AT DATUM PLANE –H–. –B–.23 0.005 0.005 ––– 0_ ––– 0.002) A–B V 0.10 (0.90 10. CONTROLLING DIMENSION: MILLIMETER.90 10.13 ––– 0_ ––– 12.037 0. ALLOWABLE PROTRUSION IS 0.05 (0.005 0. 354 BSC 0. AND –Z– TO BE DETERMINED AT DATUM PLANE –AB–.270 1. 4 DATUMS –T–.500 0. 7 DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION.230 0.350 1.010) AC T–U S Z S SECTION AE–AE H DETAIL AD W K X Q_ 66 MOTOROLA ANALOG IC DEVICE DATA .014).0076 (0.008) AB T–U Z 9 A1 48 37 A DETAIL Y P 1 36 –T– B B1 12 25 –U– V AE V1 AE NOTES: 1 DIMENSIONING AND TOLERANCING PER ANSI Y14.250 (0.028 12 _REF 0.055 0.170 0.170 0.000 REF INCHES MIN MAX 0.177 BSC 0.500 BSC 0.053 0. ALLOWABLE PROTRUSION IS 0.020 0.050 0.080 (0. 3 DATUM PLANE –AB– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE.276 BSC 0.450 0.063 0.350 (0.006 0.010) PER SIDE.200 0.090 0.000 BSC 4.500 BSC 9.500 BASIC 0. 9 EXACT SHAPE OF EACH CORNER IS OPTIONAL.250 BASIC 1_ 5_ 0.008) AC T–U Z G –AB– –AC– AD BASE METAL 0.138 BSC 0.500 BSC 7.007 0.010 0.000 BSC 3.002 0.006 0.090 0.160 0. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –AB–.177 BSC 0.250 9.5M.006 0.138 BSC 0.007 0.003) M R GAUGE PLANE N J C E 0.500 BSC 1.354 BSC 0.020 BASIC 0. 1982. MILLIMETERS MIN MAX 7.039 REF 13 24 –Z– S1 –T–. 8 MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.008 REF 0. 5 DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –AC–. 2 CONTROLLING DIMENSION: MILLIMETER.011 0.080 (0.MC13110A/B MC13111A/B OUTLINE DIMENSIONS FTA SUFFIX PLASTIC PACKAGE CASE 932–02 (LQFP–48) ISSUE D 4X 0. 6 DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.008 0.200 (0.004 0.010 BASIC 1_ 5_ 0. –U–.0003).700 12 _REF 0.600 0.200 (0.057 0.250 (0.000 BSC 3. –Z– S 4X DETAIL Y 0.004 0. –U–.150 0.276 BSC 0.000 BSC 4.150 0.003) AC DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X M_ TOP & BOTTOM ÉÉÉÉ ÇÇÇÇ ÇÇÇÇ ÉÉÉÉ ÇÇÇÇ F D 0.009 0.200 REF 1.400 1. and expenses. including without limitation consequential or incidental damages. directly or indirectly. or authorized for use as components in systems intended for surgical implant into the body. Motorola products are not designed. including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola makes no warranty. nor does Motorola assume any liability arising out of the application or use of any product or circuit. any claim of personal injury or death associated with such unintended or unauthorized use. subsidiaries.MC13110A/B MC13111A/B Motorola reserves the right to make changes without further notice to any products herein. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application. and distributors harmless against all claims. and specifically disclaims any and all liability. Motorola does not convey any license under its patent rights nor the rights of others. or other applications intended to support or sustain life. is an Equal Opportunity/Affirmative Action Employer. Inc. even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. damages. Motorola. MOTOROLA ANALOG IC DEVICE DATA 67 . Motorola and are registered trademarks of Motorola. employees. All operating parameters. Inc. costs. representation or guarantee regarding the suitability of its products for any particular purpose. or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. intended. affiliates. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Buyer shall indemnify and hold Motorola and its officers. and reasonable attorney fees arising out of. T. Inc.mot..motorola. Box 5405. Shinagawa–ku. Tai Po. Colorado 80217.MC13110A/B MC13111A/B Mfax is a trademark of Motorola. 852–26629298 – http://sps. 81–3–5487–8488 68 ◊ MC13110A/D MOTOROLA ANALOG IC DEVICE DATA .O. 1–303–675–2140 or 1–800–441–2447 Customer Focus Center: 1–800–521–6274 Mfax™: [email protected]. Hong Kong.: SPD. Ltd. N. Nishi–Gotanda.. Strategic Planning Office. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution.com/sps/ JAPAN: Nippon Motorola Ltd. 4–32–1. Denver. 8B Tai Ping Industrial Park.sps. Japan.com – TOUCHTONE 1–602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H. Motorola Fax Back System – US & Canada ONLY 1–800–774–1848 51 Ting Kok Road.com/mfax/ HOME PAGE: http://motorola. P. Tokyo 141. com Datasheets for electronic components.This datasheet has been downloaded from: www.DatasheetCatalog. .