Advanced VLSI DesignCMOS Inverter CMPE 640 Propagation Delay Several observations can be made from the analysis: PMOS was widened to match resistance of NMOS by 3 - 3.5. This was done to provide symmetrical H-to-L and L-to-H propagation delays. This also triples the PMOS gate and diffusion capacitances. It is possible to speed-up the inverter by reducing the width of the PMOS device (at the expense of symmetry and noise margins)! Widening PMOS reduces tpLH by increasing the charging current, but it also degrades the tpHL by causing a larger parasitic capacitance. This implies that there is an optimal ratio that balances the two contradictory effects. 1 Advanced VLSI Design CMOS Inverter CMPE 640 Propagation Delay Consider two identically sized CMOS inverters. The load cap of the first gate is approximated by: C L = ( C dp1 + C dn1 ) + ( C gp2 + C gn2 ) + C W Now assume PMOS devices are made b times larger than NMOS. C dp1 = βC dn1 & C gp1 = βC gn1 C L = ( 1 + β ) ( C dn1 + C gn2 ) + C W Returning to: t pHL + t pLH R eqp t p = ---------------------------- = 0.69C L ⎛ R eqn + ---------- ⎞ ⎝ 2 β ⎠ R eqp 0.69 t p = --------- ( ( 1 + β ) ( C dn1 + C gn2 ) + C W ) ⎛ R eqn + ---------- ⎞ ⎝ 2 β ⎠ r t p = 0.345 ( ( 1 + β ) ( C dn1 + C gn2 ) + C W )R eqn ⎛ 1 + -- ⎞ ⎝ β⎠ 2 6 -.Advanced VLSI Design CMOS Inverter CMPE 640 Propagation Delay r is equal to the resistance ratio of identically sized PMOS and NMOS transistors: Reqp/ Reqn. The optimal value of b can be found by setting ∂t p = 0 ∂β β opt = CW r ⎛ 1 + ----------------------------. r normally used in the non-cascaded case. Example in text gives β of 2. vs. βopt is then 1.⎞ ⎝ C dn1 + C gn1⎠ When wiring capacitance is negligible. This analysis indicates that smaller device sizes (and smaller area) yield a faster design at the expense of symmetry and noise margins.SPICE sims gives optimal value of β = 1.9.4 (=31 kΩ/13 kΩ) for symmetrical response. larger values of b should be used. 3 . βopt equals the sqrt(r). If wiring cap dominates. ⎞ = 0. then propagation delay is: t p = 0.69R eq C int So how does transistor sizing impact the performance of the gate? 4 . Load capacitance can be divided into intrinsic or self-loading and extrinsic components: C L = C int + C ext Assuming Req stands for the equivalent resistance of the gate.69R eq ( C int + C ext ) C ext ⎛ 1 + --------.Advanced VLSI Design CMOS Inverter CMPE 640 Sizing Inverters for Performance Assume a symmetrical inverter (rise and fall times of inverter are identical).69R eq C int ⎝ C ⎠ int Intrinsic or unloaded delay ⎛ 1 + C ext⎞ = t p0 --------⎝ C ⎠ int with t p0 = 0. ⎞ ⎝ SC iref⎠ 5 . Let's use a minimum sized inverter as a reference gate.Advanced VLSI Design CMOS Inverter CMPE 640 Sizing Inverters for Performance Cint consists of the diffusion and Miller caps.⎞ ⎝ ⎝ S ⎠ SC ⎠ iref & R ref R eq = --------S C ext = 0. both of which are proportional to the width of the transistors.69R ref C iref ⎛ 1 + -------------.69 ⎛ ---------⎞ ( SC iref ) ⎛ 1 + -------------. Re-writing previous expression: R ref C ext t p = 0. then: C int = SC iref where S is the sizing factor. no win beyond this size. 6 . eliminates the impact of any external load and reduces the delay to the intrinsic one.Advanced VLSI Design CMOS Inverter CMPE 640 Sizing Inverters for Performance Conclusions Intrinsic delay of the inverter tp0 is independent of the sizing of the gate (determined by technology and layout only). When there is no load. So the more relevant problem is determining the optimum size of a gate when embedded in a real environment. Bear in mind that any size greater than (Cext/Cint) produces similar results while increasing the silicon area -. it also increases its input capacitance. Bear in mind that although sizing up an inverter reduces its delay. the increase in drive of the gate is totally offset by increased cap. Making S infinitely large yields the max performance. 7 . Cg and the intrinsic output capacitance. Both are proportional to gate sizing. so the following is true: C int = γC g The gamma factor γ is only a function of technology and is close to 1 for most processes. Substituting: ⎛ 1 + C ext⎞ = t ( 1 + f ⁄ γ ) --------t p = t p0 p0 ⎝ γC ⎠ g This shows the delay of an inverter is only a function of the ratio between its external load cap and its input cap. and is called effective fan-out f. we need to determine the relationship between the input gate capacitance.Advanced VLSI Design CMOS Inverter CMPE 640 Sizing Inverters for Performance Consider a chain of inverters as the first case. To determine input loading effect. j = t p0 ∑ j=1 ⎛ 1 + C g. 8 . N+1 = CL And we need to solve for N-1 unknowns Cg. j with Cg.3. Cg. min sized gate Some large load we need to drive Delay for j-th inverter stage (ignoring wire cap): t p. Cg.⎞ = t ( 1 + f ⁄ γ ) = t p0 p0 j ⎝ γC ⎠ g.Advanced VLSI Design CMOS Inverter CMPE 640 Sizing a Chain of Inverters Goal is to minimize delay through the following inverter chain: In 1 2 N Cg1 CL input cap of first inverter. j The total delay of the chain is then: N N t p. j + 1⎞ ---------------⎝ γC ⎠ g. j C g. j = ∑ j=1 t p.N.2. j + 1 ⎛ 1 + ---------------. the sizing factor is given as: f = N C L ⁄ C g. j − 1 g.1. The minimum delay through the chain is: t p = Nt p0 ( 1 + ( N F ) ⁄ γ ) First component is intrinsic delay of the stages while second is effective fan-out of each stage.1 and CL. 9 . j = C C g. j + 1 So each inverter is sized up by the same factor f (and has the same delay).Advanced VLSI Design CMOS Inverter CMPE 640 Sizing a Chain of Inverters Solution giving the optimal size of each inverter (that minimizes delay) is the geometric mean of each of the inverter's neighbors: C g. 1 = N F where F represents the overall effective fan-out of the circuit and equals CL/Cg. Given Cg. if too few. effective fan-out dominates. intrinsic delay dominates.= 0 N (1 + γ ⁄ f) N or f = e Under the condition that γ is 0 (self-loading is ignored. load cap only consists of the fanout).71828 10 . If too many.Advanced VLSI Design CMOS Inverter CMPE 640 Sizing a Chain of Inverters The relationship between tp and F is a strong function of the number of stages. the optimal number is: N = ln ( F ) effective fan-out is set to f = e = 2. Differentiating and setting to zero yields: γ+ N F ln ( F ) F − -----------------------.1). The important question now is how to choose the number of stages so that the delay is minimized for a given value of F (CL/Cg. 0 3.5 4.0 4.5 3.0 2.0 normalized delay 7 6 5 4 3 2 1 0 1 1.Advanced VLSI Design CMOS Inverter CMPE 640 Sizing a Chain of Inverters This indicates that the optimal buffer design scales consecutive stages in an exponential fashion (exponential horn).0 2.5 4.0 Right plot shows normalized delay (tp/tpopt) as a function of fan-out f for γ = 1. For a typical case with γ = 1.5 0 0.0 1.5 3.5 f 3. 5. the optimum tapering factor is close to 3.0 2.5 2.6. 11 .0 fopt 3. The solution when self-loading is included can only be computed numerically.5 1.5 γ 2. Note that the use of too few stages (f < fopt) has a significant impact on performance and should be avoided. It is common to select an optimum fan-out of 4 (FO4).Advanced VLSI Design CMOS Inverter CMPE 640 Sizing a Chain of Inverters Here it is clear that choosing values for fan-out that are higher than the optimum does NOT effect the delay very much (and helps reduce area). 12 . Rise-Fall Time of Input Signal It is not realistic to assume that input signal changes abruptly and only one device is on. Reality is that both are on for some portion of time and the total charging/discharging current is directed onto/off the load caps. 4 4.0 4.0 3.0 ts (sec) 8.6 0 2. Key design challenge is to keep the signal rise times <= the gate propagation delay.2 4.Advanced VLSI Design CMOS Inverter CMPE 640 Rise-Fall Time of Input Signal Propagation delay of a minimum sized inverter as a function of input signal slope (fan-out is a single gate).8 tp (sec) 4.0 x10-11 (10%-90%) tp increases approximately linearly with increasing input slope. 13 . for speed and power consumption. x10-11 5. Text gives a more thorough analysis. for ts > tp.0 6. even though its influence can dominate the transient response. inverter drives a single fan-out through a wire of length L.Advanced VLSI Design CMOS Inverter CMPE 640 Wire Delay We've ignored the wire delay so far.69R dr C int + ( 0.69R dr + 0. Consider the following circuit: Vin Vout (rw. L) Cfan 1 N Cint Here. cw.69 ( R dr + R w )C fan 14 . Elmore delay expression yields the propagation delay of the circuit as: t p = 0.38R w )C w + 0. Let the driver be represented by a single resistance Rdr (average of Reqn and Reqp). and Cint and Cfan are the intrinsic cap of the driver and input cap of the fan-out gate. as well as a quadratic one. Here. The latter obviously becomes the dominant factor in the delay of longer wires.69R dr ( C int + C fan ) + 0.38 factor accounts for the fact that the wire represents a distributed delay.Advanced VLSI Design CMOS Inverter CMPE 640 Wire Delay Rearranging yields: t p = 0.69 ( R dr c w + r w C fan )L + 0. the delay expression contains a component that is linear with the wire length.38r w c w L 2 The 0. 15 . Cw and Rw stand for the total capacitance and resistance of the wire. 16 . very small. Rather. For a device at 5V with 1 million devices. its the almost zero power consumption in steady-state mode. power consumption is 0. A more serious source is the subthreshold current. in general.1 to 0.Advanced VLSI Design CMOS Inverter CMPE 640 Power Consumption The almost ideal VTC of the CMOS inverter is not the main reason that high-complexity designs are implemented in static CMOS.5V today. which is > 0. the larger the leakage with VGS = 0V. Typical values are 0.5nA at room temperature. Vout = VDD Drain Leakage current Subthreshold current The reversed-bias diode current is. The closer VT is to zero. This establishes a firm lower bound on VT.5mW. Dynamic power is much larger than static power and can be broken into 2 parts. the resulting static power dissipation is given by: P static = I leakage V DD The junction leakage currents are caused by thermally generated carriers. CL. 17 . Load capacitance. 85 degrees C (a common junction temperature) results in an increase by a factor of 60 over room temperature. power. Their value increases exponentially with increasing junction temperature. For example.Advanced VLSI Design CMOS Inverter CMPE 640 Power Consumption For both sources of leakage. Power consumed via direct path currents (crow-bar currents). 3W are dissipated. at 30fF/gate at 100MHz and VDD = 5V. For example. Half of this energy is stored on the cap (CL *V2DD/2) and later dissipated through the NMOS device. P dyn = C eff V DD f 2 with C eff = αC L Technology advances decrease tp and increase f and CL (higher integration). for a clock frequency of f.44W (assuming the same f). 5V -> 3V drops 4W to 1. 1W is consumed with 100 output pins at 20pF/pin and f = 20MHz. With 200K gates and α = 20%. Therefore. So. For example. 18 .Advanced VLSI Design CMOS Inverter CMPE 640 Power Consumption CL power (we derived this previously): Charging CL to VDD draws CL * V2DD energy from the power supply. 75µW is dissipated per gate. One of the driving forces for lower supply voltages (quadratic effect). an energy = CL * V2DD is consumed for every L->H and H->L transition. Advanced VLSI Design CMOS Inverter CMPE 640 Power Consumption Direct-path currents. Direct-path power is typically only about 20% of the dynamic power. 19 . the power consumed is tr + tf I peak t r I peak t f P dp = ⎛ V DD --------------.VT VT Ipeak Using triangles and VDD >> |VT|. VDD .+ V DD --------------.V DD I peak f ⎝ 2 2 2 ⎠ Avoid large values for tf and tr to minimize. Zero rise/fall times is not a realistic assumption.⎞ f = -----------. Advanced VLSI Design CMOS Inverter CMPE 640 Power Consumption Total power is then: P tot = P dyn + P dp + P static = 2 C L V DD f f ⎛ t r + t-⎞ f + V I + V DD I peak -----------DD leak ⎝ 2 ⎠ The Power-Delay product was also defined previously. This results in a PDP of PDP = C L V DD Under the condition that the static and direct-path currents are ignored. 2 20 . It is the energy consumed by the gate per switching event. We've defined a switching event to consist of a 0 -> 1 and a 1 -> 0 event.