lab manual verilog

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Computer ArchitectureImplementing a Datapath in Verilog A Lab Manual George M. Georgiou and Scott McWilliams Computer Science Department California State University, San Bernardino October 2003 Revision: 1.3, May 3, 2010 Contents Contents 1 List of Code Listings 2 List of Figures 3 I Lab Manual 5 1 The MIPS datapath in Verilog: The IF stage Lab 1–1 1.1 Testbenches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lab 1–5 2 The ID pipeline stage. 3 The EX pipeline stage Lab 3–1 3.1 Testbenches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lab 3–5 4 The MEM pipeline stage. Lab 4–1 5 The WB pipeline stage Lab 5–1 6 Testing the MIPS datapath Lab 6–1 Lab 2–1 Bibliography Bib 1 1 List of Code Listings 1.1 1.2 1.3 3.1 3.2 3.3 6.1 6.2 Verilog code for the multiplexer. . . . . . . . . . . . . . . . . . . . The testbench for the multiplexor in figure 1.5 on page Lab 1–4 . . . The testbench for the incrementer in figure 1.6 on page Lab 1–4 . . The testbench for the 5-bit multiplexor in figure 3.3 on page Lab 3–3 The testbench for the ALU control in figure 3.4 on page Lab 3–4 . . The testbench for the ALU in figure 3.5 on page Lab 3–4 . . . . . . Binary code for testing the MIPS datapath. . . . . . . . . . . . . . . Initial data for memory. . . . . . . . . . . . . . . . . . . . . . . . . 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lab 1–3 Lab 1–6 Lab 1–7 Lab 3–6 Lab 3–7 Lab 3–9 Lab 6–2 Lab 6–2 . . . . . . . . . . . . . . . . . .8 The MEM stage . Lab 1–2 Lab 1–2 Lab 1–3 Lab 1–3 Lab 1–4 Lab 1–4 Lab 1–4 The ID stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 4. . . . . . . The control unit .3 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1. . . . . . . . . .1 4. . . . . . . . . . . . . . . . . . .8 The revised MIPS datapath . . .7 1.1 1. The output when running the testbench for the multiplexer (listing 1. . . . . . . . . . . . . . . . .7 3. . . . .4 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 The output when running the testbench for the ALU (listing 3. . . . . The ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 on page Lab 1–7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The incrementer by 1 . . . . . . . . The program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 on page Lab 3–6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3. . . . . . .9 The output when running the testbench for the ALU control (listing 3. . . . . . . . . . . . . . . . . . . . . 3. . . . . The multiplexer . . . . . . 3. . . . . . . . . . . . . .6 . . . . . . . . . . . . The MEM/WB pipeline register (latch) . . . . . . . . . . . . . . . . . . . . . .3 3. . . . . . . . . .2 3. .4 Lab 4–2 Lab 4–2 Lab 4–3 Lab 4–3 1. .List of Figures 1. . . . . . . . . . . .1 3. . . . .5 1. . . . . . . . . . . . . . . . .2 1. . . . . . . . . . . . . . . . . . . . . . . Lab 3–2 Lab 3–2 Lab 3–3 Lab 3–4 Lab 3–4 Lab 3–4 Lab 3–5 Lab 3–8 Lab 3–8 4. . . . . . . The IF stage . . Lab 2–2 Lab 2–2 Lab 2–3 Lab 2–3 Lab 2–4 Lab 2–4 The EX stage . The ID/EX pipeline register (latch) . . . . . . . . . .5 3. . .2 on page Lab 1–6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3. . . . . . . . . . . . . . . . . . . . . . . . . . The instruction memory . . . . . . . . . . . . . . . .9 2. . . . . . . . . .2 2. . . . . . . . . . . . . . . . . . . .3 1. . The data memory unit . . . . The register file . . . . . . . . The ALU control unit . . . . . . . . . . . . . . . . . . . The and gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2. . . The IF/ID pipeline register (latch) . . . . . . . . . . . . . . . The output when running the testbench for the 5-bit multiplexer (listing 3. . . 3 . . . The multiplexer . The adder . . . . . . . . . . . . . . . . . . . . .1 2. . . . . . . . . . . . . . . . . . . . . . The output when running the testbench for the incrementer (listing 1. . . . .3 4. . . . . . . . . . . Lab 1–5 Lab 1–5 Lab 3–5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ALUOp Control Bit and Function Code Sets (after [4]) The sign-extend unit . . . . . . . . . . . . . .2 on page Lab 3–7) . . . . . . . . . . . .3 on page Lab 3–9) . . . . . . . . . .4 1. . . . . . . . . . . . . . . ALUOp Control Bit and Function Code Sets (after [4]) . The EX/MEM pipeline register (latch) . . . . . . . . . . . . . . . . . . Lab 5–1 The multiplexer . . . . . . . . . . . Lab 5–2 4 . . . . . . . . . . . . . . .2 LIST OF FIGURES The WB stage . . . . . . . . . . . .LIST OF FIGURES 5. . . .1 5. . . . . . . . . . . . . . . . . . . . . . Part I Lab Manual 5 . For now. ID EX. you will implement the IF stage and test the fetching of instructions from memory. 8. such as multiplexors and ALU’s. The series of labs in this manual has ultimate objective to implement and simulate in Verilog the MIPS pipeline datapath Figure 6. EX MEM. but with one exception: basic units. MEM WB. etc. (Simply the 7 least significant bits (2ˆ7 = 128) are used for the time being. time consuming. The IF stage isolated from the rest of the datapath can be seen in figure 1. PC choose. For the time being consider that the 1-bit signal PCSrc comes from a 1-bit register.1 on page Lab 1–2.LAB 1 The MIPS datapath in Verilog: The IF stage Objective: To implement and test the Instruction Fetch (IF) pipeline stage of the MIPS five stage pipeline. They will not change during this simulation. • Initialize IF ID NPC to 32 zeros. • The names of the pipeline registers are IF ID. Initialize the first 10 words of memory (with addresses 0. may implemented as behavioral models. This approach reinforces the object-oriented style of programming. All instructions and the PC are 32-bit wide.) with the following HEX values: Lab 1–1 . 2x1 MUX. and Incrementer-by-4 as separate modules.) • Implement the instruction memory. you will need only IF ID and EX MEM. The slightly revised MIPS datapath to be implemented is in figure 1. while at the same time relieving from the burden of structurally defining the basic units. The model will be structural (as opposed to behavioral). • Initialize IF ID IR (The instruction field of IF/ID) to 32 zeros.2 on page Lab 1–2. • The instruction memory has 128 32-bit words.30 in Paterson and Hennessy’s textbook [4]. For this week. 4. Later it will be expanded. Initialize PC choose and EX MEM NPC to zeros. which can be quite tedious. and beyond the scope of this lab series. LAB 1 The MIPS datapath in Verilog: The IF stage PCSrc ID/EX 2 \ IR 0 \ Control Mux 1 WB EX/MEM M WB WB MEM/WB EX M WB 3 [31:26] 4 \ IF/ID Add Add result IR ALU result Mux Registers Write reg MemtoReg ALU 0 Address Read data 1 1 Data memory Read data 2 Write data 0 IR IR IR [15:0] 16 \ IR 32 Sign extend \ [5:0] 6 \ ALU control ALUOp 0 [20:16] [15:11] 1 RegDst Figure 1.1: The revised MIPS datapath PCSrc From EX/MEM latch 0 Component 1 1 IF/ID Add Component 2 To ID/EX latch 1 PC Component 3 Address Instruction memory Component 4 Component 5 Figure 1.2: The IF stage Lab 1–2 IR MemRead Write data Mux Instruction memory Zero Read reg 2 Mux Address Read reg 1 Read data 1 [20:16] Mux PC [25:21] MemWrite IR ALUSrc IR Branch Add RegWrite 1 . 32 npc \ 32 PC \ PC Figure 1. input [31:0] a. assign y = sel ? a : b. Be ready to demonstrate. input sel . b .1 implements the multiplexer in the IF stage as a combinational circuit.LAB 1 The MIPS datapath in Verilog: The IF stage module mux ( a . A00000AA 10000011 20000022 30000033 40000044 50000055 60000066 70000077 80000088 90000099 • Turn in the source code and the printout of the clock cycle number. Note: The code in listing 1.3: The program counter (PC) addr 32 \ Address Instruction memory 32 \ data Figure 1.1: Verilog code for the multiplexer. output [31:0] y . IF ID IR (in hex). and IF ID NPC (in decimal) for 10 cycles of simulation.4: The instruction memory Lab 1–3 . s e l . y ) . the contents of the PC (in decimal). b . endmodule Listing 1. 6: The incrementer by 1 npc instr 32 32 \ \ 32 32 \ \ npcout instrout Figure 1.5: The multiplexer 32 pcin \ 32 Add \ pcout 1 Figure 1.7: The IF/ID pipeline register (latch) Lab 1–4 .LAB 1 The MIPS datapath in Verilog: The IF stage sel \ 1 32 b 0 32 Mux \ y \ 32 a 1 \ Figure 1. 3 on page Lab 1–7) Lab 1–5 .v’ Finished Phase I Entering Phase II. the standard messages of the runs will be largely omitted.1 1.6 on page Lab 1–4 ..8: The output when running the testbench for the multiplexer (listing 1.00000 Normal exit Figure 1. In the latter. Finished Phase II Entering Phase III..2 on page Lab 1–6 for the multiplexer of figure 1. Finished Phase III Highest level modules: test_mux Compile Complete .00000. and in other testbench runs in the labs that follow. The results of the running the testbench are in figure 1.5 on page Lab 1–4 and one in listing 1. Load time = 0.LAB 1 1.3 on page Lab 1–7 for the incrementer of figure 1.. 0 Warnings Compile time = 0. In this subsection we show two testbenches: One in listing 1.v’ Continuing compilation of source file ’muxtest..00000... Beginning Compile Beginning Phase I Compiling source file: muxtest. Running. At t = 11 sel = 1 A = 00000000 B = 55555555 Y = 00000000 At t = 31 sel = 1 A = 00000000 B = ffffffff Y = 00000000 At t = 36 sel = 1 A = a5a5a5a5 B = ffffffff Y = a5a5a5a5 At t = 41 sel = 0 A = a5a5a5a5 B = dddddddd Y = dddddddd At t = 46 sel = x A = a5a5a5a5 B = dddddddd Y = XXXXXXXX 0 Errors.1.9.9: The output when running the testbench for the incrementer (listing 1. Time = 11 A=3 IncrOut=4 Time = 21 A=15 IncrOut=16 Time = 31 A=64 IncrOut=65 Figure 1.v Compiling included source file ’mux. TESTBENCHES Testbenches Testbenches help us verify that the design is correct.8 and in figure 1. respectively.. Execution time = 0..2 on page Lab 1–6) Running. v ” module t e s t m u x . MUX mux1 ( Y. #10 s e l = 1 ’ b1 . $ t i m e . #5 . A = 32 ’ h00000000 . endmodule // test Listing 1. B. s e l . A. B. B . Y) . / / i n s t a n t i a t e t h e mux i n i t i a l begin A = 32 ’hAAAAAAAA. s e l = 1 ’ bx .1. reg sel . B = 32 ’ h55555555 .LAB 1 1. end a l w a y s @(A o r B o r s e l ) #1 $ d i s p l a y ( ” At t = %0d s e l = %b A = %h B = %h Y = %h ” .5 on page Lab 1–4 Lab 1–6 . B = 32 ’ hFFFFFFFF . #10 . s e l ) . B = 32 ’hDDDDDDDD. TESTBENCHES : t e s t −mux . #5 . / / Filename / / Description // ‘ i n c l u d e ”mux . A = 32 ’hA5A5A5A5 . A. / / Register Declarations r e g [ 3 1 : 0 ] A. v : T e s t i n g t h e 32 b i t m u x module of t h e IF s t a g e of t h e p i p e l i n e . / / Wire P o r t s wire [ 3 1 : 0 ] Y. s e l = 1 ’ b1 . s e l = 1 ’ b0 . #5 . #10 .2: The testbench for the multiplexor in figure 1. LAB 1 1. v” module t e s t ( ) . $ t i m e . / / i n s t a n t i a t e the incrementer i n i t i a l begin #10 A = 3. A) .6 on page Lab 1–4 Lab 1–7 . / / P o r t Wires wire [ 3 1 : 0 ] IncrOut . an i n c r e m e n t e r by 1 (32− b i t i n p u t ) / / Filename / / Description // ‘ include ” i n c r . v : T e s t f o r i n c r . TESTBENCHES : t e s t −i n c r . end a l w a y s @(A) #1 $ d i s p l a y ( ” Time = %0d\ tA=%0d \ t I n c r O u t =%0d ” . #10 . A = 15.3: The testbench for the incrementer in figure 1. INCR i n c r 1 ( I n c r O u t . #5 .1. IncrOut ) . v . endmodule // test Listing 1. #10 A = 64. A. / / Register Declarations r e g [ 3 1 : 0 ] A. S EXTEND.LAB 2 The ID pipeline stage. – The register file REG. The parent module PIPELINE instantiates I FETCH (from the previous lab) and I DECODE. integrate it together with the IF stage of last week. • The module I DECODE instantiates the modules CONTROL. MEM WB Writedata.1 on page Lab 1–2) as a behavioral model in Verilog and simulate it. S EXTEND modules. Objective: To implement and test the Instruction Decode (ID) pipeline stage and integrate it with the IF stage. and label and print out the outputs of the ID EX register. and test both together.2 on page Lab 2–2. – The combinational module S EXTEND receives as input the 16-bit immediate field of IF ID instr and output is the 32 bit sign-extended value. Instr[20-16]. REG. IF ID Instr[20-16] and IF ID Instr[15-11]. Outputs are the contents of register rs and register rt. REG. For this week. and has input the rs and rt fields of IF ID instr. as well as the IF ID NPC. • Testing: Initialize memory to the following hex values. Reg[rs]. Lab 2–1 . beginning with location 0. – The ID EX module includes the pipeline register ID/EX and inputs the outputs of the CONTROL. Simulate for sufficient cycles so that all instructions go through the ID EX register. MEM WB Writereg. Reg[rt]. and Instr[15-11]. you will implement the ID stage figure 2 on page Lab 2–2. The control bits should be binary and all other values should be decimal. and ID EX – The CONTROL module has input the opcode field of the IF ID instr and output is the 9-bit control bits which are shown in figure 2. and RegWrite (for the time being it can be from anywhere). Outputs are the control bits (9 bits) NPC. which has 32 general purpose registers. signExtended (32 bit). This is part of a series of labs to implement the MIPS Datapath (figure 1. 2: ALUOp Control Bit and Function Code Sets (after [4]) Lab 2–2 .1: The ID stage Figure 2.LAB 2 The ID pipeline stage. ID/EX 2 \ IR WB WB 3 [31:26] \ Control M 4 Component 1 \ From IF/ID latch EX M RegDst ALUOp ALUSrc To EX adder RegWrite IR [25:21] Read reg 1 Read data 1 IR To EX ALU [20:16] Read reg 2 Registers Write reg From MEM/WB latch To EX Mux 0 and EX/MEM latch Read data 2 Write data From WB mux Component 2 IR [15:0] 16 \ From IF/ID latch 32 Sign extend \ IR Component 3 IR [20:16] To EX Mux 0 IR [15:11] To EX Mux 1 Component 4 Figure 2. as in testing above. Be ready to demonstrate.3: The sign-extend unit 2 \ opcode 6 3 \ Control \ WB M 4 \ EX Figure 2.LAB 2 The ID pipeline stage. 16 32 Sign extend \ \ Figure 2. 002300AA 10654321 00100022 8C123456 8F123456 AD654321 13012345 AC654321 12012345 • Turn in the source code and the printout of the clock cycle number and outputs off the ID EX register.4: The control unit Lab 2–3 controlbits . 5: The register file 2 ctlwb_out \ 2 WB 3 ctlm_out \ npc readdat1 readdat2 signext_out instr_2016 instr_1511 \ wb_ctlout 3 M 4 ctlex_out \ \ m_ctlout 4 EX \ 32 32 \ \ 32 32 \ \ 32 32 \ \ 32 32 \ \ 5 5 \ \ 5 5 \ \ ex_ctlout npcout rdata1out rdata2out s_extendout instrout_2016 instrout_1511 Figure 2. regwrite 1 5 rs Read reg 1 \ rt \ A Read reg 2 \ Registers 5 rd 32 Read data 1 5 Write reg \ 32 Read data 2 32 writedata \ B Write data \ Figure 2.LAB 2 The ID pipeline stage.6: The ID/EX pipeline register (latch) Lab 2–4 . or. – The ALU CONTROL. – ALU MAX. integrate it together with the IF and ID stages of the previous week. EX MEM NPC . ALUop = 11 and ALU output is 32 x’s. This is part of a series of labs to implement the MIPS Datapath (figure 1. Notice that you may instantiate the previously made MUX in the IF stage. is eliminated in figure 1. and I DECODE.1 on page Lab 1–2. since EX MEM exists now. The specification is found in figure 1 on page Lab 1–3. The parent module PIPELINE instantiates I FETCH. and make them as inputs to the I FETCH module. Inputs are ALUop bits and the function bits. and they are add. – ID MEM.1 on page Lab 1–2) as a behavioral model in Verilog and simulate it. The parent module PIPELINE instantiates I FETCH (from the previous lab) and I DECODE. • Move the above to the EX MEM module. – BOTTOM MUX. the pipeline register. • In the I FETCH module we have resetmargins=true reg reg [31:0] EX MEM PCSrc . If the input information does not correspond to any valid instruction. Notice that the inputs and output are 5 bits. Lab 3–1 .30 in Paterson and Hennessy’s book [4]. For this week. • The module I EXECUTE instantiates the following modules – ADDER for the branch target address computation. Now there is direct line from the input of ”Shift left 2” to its output. you will implement the EX stage figure 3 on page Lab 3–2. – The instructions to be implemented are specified in the figure 3. and I EXECUTE. set less than.LAB 3 The EX pipeline stage Objective: To implement and test the Execution (EX) pipeline stage and integrate it with the IF and ID stages. and test three of them together. CHANGE: Please note that the “Shift left 2” unit that exists in Figure 6. and. subtract.2 on page Lab 3–2. 1: The EX stage Figure 3.2: ALUOp Control Bit and Function Code Sets (after [4]) Lab 3–2 .LAB 3 The EX pipeline stage EX/MEM From ID/EX latch WB From ID/EX latch M MEM/WB latch MemRead MemWrite MEM Branch From ID/EX latch Add result Component 1 To IF mux Add Component 2 From ID/EX latch Zero Component 3 0 To MEM Branch ALU Mux ALU result To MEM Data memory and MEM/WB latch 1 From ID/EX latch ALUSrc To MEM Data memory Component 4 IR 6 [5:0] \ From ID/EX latch ALU control IR [20:16] From ID/EX latch IR Mux 0 Component 5 [15:11] From ID/EX latch ALUOp To MEM/WB latch Component 6 1 RegDst Figure 3. The control bits should be binary and all other values should be decimal. and label and print out the outputs of the ID EX and EX MEM registers. Simulate for sufficient cycles so that all instructions go through the EX MEM register. Turn in the source code and the printout of the clock cycle number and outputs of the ID EX register and the EX MEM register. Be ready to demonstrate. beginning with location 0.LAB 3 The EX pipeline stage • Testing: Initialize memory to the following hex values.3: The multiplexer Lab 3–3 y . sel \ 1 5 \ 0 Mux b 5 \ 5 a \ 1 Figure 3. 002300AA 10654321 00100022 8C123456 8F123456 AD654321 13012345 AC654321 12012345 • Be ready to use initialize memory with a given different set of instructions. 5: The ALU 32 add_in1 \ 32 Add \ 32 add_in2 \ Figure 3.6: The adder Lab 3–4 add_out .4: The ALU control unit 32 A \ 1 \ ALU zero 32 \ result 32 \ 3 \ B control Figure 3.LAB 3 The EX pipeline stage 6 3 ALU control \ 2 select \ \ funct alu_op Figure 3. 8: The output when running the testbench for the 5-bit multiplexer (listing 3.9 on page Lab 3–8.10 on page Lab 3–8.4 on page Lab 3–4 and listing 3..3 on page Lab 3–3 and listing 3.1.LAB 3 3.8. At t = 11 sel = 1 A = At t = 31 sel = 1 A = At t = 36 sel = 1 A = At t = 41 sel = 0 A = At t = 46 sel = x A = 0 Errors.7: The EX/MEM pipeline register (latch) 3.1 Testbenches Testbenches and their corresponding outputs are given for the 5-bit multiplexer (figure 3. for the ALU control unit in figure 3. Running.3 on page Lab 3–9). and the ALU (figure 3. and for the ALU in figure 3. the ALU control unit (figure 3. 0 Warnings Normal exit 00000 00000 00101 00101 00101 B B B B B = = = = = 10101 11111 11111 11101 11101 Y Y Y Y Y = = = = = 00000 00000 00101 11101 xx101 Figure 3.1 on page Lab 3–6). The results of running the testbench for the multiplexer are in figure 3.1 on page Lab 3–6) Lab 3–5 .5 on page Lab 3–4 and listing 3. TESTBENCHES 2 ctlwb_out 2 \ WB 3 ctlm_out adder_out aluzero aluout \ M \ 32 32 \ \ 1 1 \ \ 32 32 \ \ 32 32 \ \ readdat2 muxout \ wb_ctlout 3 5 5 \ \ m_ctlout add_result zero alu_result rdata2out five_bit_muxout Figure 3.2 on page Lab 3–7).. / / Register Declarations reg [ 4 : 0 ] A. B = 5 ’ b11101 . #5 . s e l = 1 ’ b1 . A = 5 ’ b00000 . #10 s e l = 1 ’ b1 . A.1. end a l w a y s @(A o r B o r s e l ) #1 $ d i s p l a y ( ” At t = %0d s e l = %b A = %b B = %b Y = %b ” . B . s e l . #10 . TESTBENCHES : t e s t −5b i t m u x . B = 5 ’ b11111 . s e l ) . Y) . s e l = 1 ’ b0 . A = 5 ’ b00101 . B. #10 . / / Filename / / Description // ‘ i n c l u d e ” 5 b i t −mux . reg sel . / / i n s t a n t i a t e t h e mux i n i t i a l begin A = 5 ’ b01010 . s e l = 1 ’ bx . $ t i m e .LAB 3 3. / / Wire P o r t s wire [ 4 : 0 ] Y. B = 5 ’ b10101 . B. #5 . MUX5 mux1 ( Y.1: The testbench for the 5-bit multiplexor in figure 3.3 on page Lab 3–3 Lab 3–6 . v ” module t e s t ( ) . A. endmodule // test Listing 3. v : T e s t i n g t h e 5 b i t m u x module o f t h e EX s t a g e o f t h e p i p e l i n e . #5 . f u n c t . i n i t i a l begin a l u o p = 2 ’ b00 . f u n c t . a l u o p . #1 f u n c t = 6 ’ b100100 . v ” module t e s t ( ) . $ m o n i t o r ( ”ALUOp = %b \ t f u n c t = %b \ t s e l e c t = %b ” . ‘ i n c l u d e ” a l u −c o n t r o l .4 on page Lab 3–4 Lab 3–7 . #1 a l u o p = 2 ’ b10 . #1 f u n c t = 6 ’ b100101 . TESTBENCHES / / Filename : t e s t −a l u c o n t r o l . f u n c t = 6 ’ b100000 . f u n c t = 6 ’ b100000 . reg [5:0] funct . / / Register Declarations reg [1:0] alu op . / / Wire P o r t s wire [ 2 : 0 ] s e l e c t . ALU CONTROL a l u c o n t r o l 1 ( s e l e c t . #1 a l u o p = 2 ’ b01 . end endmodule / / test Listing 3. #1 $finish . ) .LAB 3 3.1. select ) . a l u o p . f u n c t = 6 ’ b100000 .2: The testbench for the ALU control in figure 3. #1 f u n c t = 6 ’ b101010 . #1 f u n c t = 6 ’ b100010 . v / / Description : T e s t i n g t h e ALU c o n t r o l module // o f t h e EX s t a g e o f t h e p i p e l i n e . 3 on page Lab 3–9) Lab 3–8 .10: The output when running the testbench for the ALU (listing 3.. A = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx B = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ALUOp = 011 result = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ALUOp = 100 result = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ALUOp = 010 result = 00000000000000000000000000010001 ALUOp = 111 result = 00000000000000000000000000000000 ALUOp = 011 result = xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ALUOp = 110 result = 00000000000000000000000000000011 ALUOp = 001 result = 00000000000000000000000000001111 ALUOp = 000 result = 00000000000000000000000000000010 Exiting VeriLogger at simulation time 8000 0 Errors..LAB 3 3. TESTBENCHES Running. ALUOp = 00 funct = 100000 select ALUOp = 01 funct = 100000 select ALUOp = 10 funct = 100000 select ALUOp = 10 funct = 100010 select ALUOp = 10 funct = 100100 select ALUOp = 10 funct = 100101 select ALUOp = 10 funct = 101010 select Exiting VeriLogger at simulation 0 Errors.9: The output when running the testbench for the ALU control (listing 3. 0 Warnings = 010 = 110 = 010 = 110 = 000 = 001 = 111 time 7000 Normal exit Figure 3.1.2 on page Lab 3–7) Running.. 0 Warnings Normal exit Figure 3.. reg [02:0] c o n t r o l .1. #1 $finish .3: The testbench for the ALU in figure 3. c o n t r o l . #1 c o n t r o l <= ’ b001 . wire zero . / / Register Declarations r e g [ 3 1 : 0 ] A. #1 c o n t r o l <= ’ b111 . end ALU ALU1 ( r e s u l t . B <= ’ b0111 . #1 c o n t r o l <= ’ b110 .B . r e s u l t ) . #1 c o n t r o l <= ’ b010 .LAB 3 3. A.5 on page Lab 3–4 Lab 3–9 . v : T e s t module f o r t h e ALU ‘ include ” alu . $ m o n i t o r ( ”ALUOp = %b \ t r e s u l t = %b ” . $ d i s p l a y ( ”A = %b \ tB = %b ” . z e r o . TESTBENCHES / / Filename / / Description : t e s t −a l u . B ) . v” module t e s t ( ) . i n i t i a l begin A <= ’ b1010 . #1 c o n t r o l <= ’ b011 . endmodule / / test Listing 3. / / Wire P o r t s wire [ 3 1 : 0 ] r e s u l t . c o n t r o l <= ’ b011 . A. #1 c o n t r o l <= ’ b100 . c o n t r o l ) . B. #1 c o n t r o l <= ’ b000 . Data memory has 256 32-bit words. the EX EM register. ”write register” and RegWrite from the MEM modules. Be ready to demonstrate. you will implement the MEM stage figure 4 on page Lab 4–2. and test all of them together. and the MEM WB register. I DECODE. ID. The I FETCH module should receive inputs ’write data”. and WB modules. I EXECUTE. EX MEM. and EX stages of previous weeks. This is part of a series of labs to implement the MIPS Datapath (figure 1. The parent module PIPELINE instantiates I FETCH. Objective: To implement and test the Memory (MEM) pipeline stage and integrate it with the IF. The parent module PIPELINE instantiates I FETCH (from the previous lab) and I DECODE. Simulate for sufficient cycles so that all instructions go through the MEM WB register. beginning with location 0. and integrate it together with the IF. and MEM registers. and EX stages. 002300AA 10654321 00100022 8C123456 8F123456 AD654321 13012345 AC654321 12012345 • Be ready to use initialize memory with a given different set of instructions.1 on page Lab 1–2) as a behavioral model in Verilog and simulate it. ID. • Turn in the source code and the printout of the clock cycle number and outputs the ID EX register. The control bits should be binary and all other values should be decimal. Lab 4–1 . • Testing: Initialize memory to the following hex values. For this week.LAB 4 The MEM pipeline stage. • The module MEMORY instantiates the following modules: – D MEM: the data memory module. and label and print out the outputs of the ID EX. MEM. – MEM WB: The pipeline register MEM/WB. MEM/WB From EX/MEM latch WB RegWrite MemtoReg Branch From EX/MEM latch From EX ALU zero PCSrc Component 1 MemWrite From EX/MEM latch Address Read data Component 2 From EX/MEM latch To WB mux 1 Data memory Write data MemRead To WB mux 0 From EX mux To ID Registers Component 3 Figure 4.1: The MEM stage m_ctlout zero AND Figure 4.2: The and gate Lab 4–2 PCSrc .LAB 4 The MEM pipeline stage. 4: The MEM/WB pipeline register (latch) Lab 4–3 .3: The data memory unit 2 control_wb_in Read_data_in ALU_result_in Write_reg_in \ 2 WB \ 32 32 \ \ 32 32 \ \ 5 5 \ \ mem_control_wb Read_data mem_ALU_result mem_Write_reg Figure 4.LAB 4 The MEM pipeline stage. MemWrite 1 32 Address \ Address Read data 32 \ Read_data Data memory 32 Write_data Write data \ 1 MemRead Figure 4. Lab 5–1 . the multiplexer at the output of MEM/WB.LAB 5 The WB pipeline stage Objective: To implement and test the Write-back (WB) pipeline stage and integrate it with the IF. and gives output WriteData.1 on page Lab 1–2) as a behavioral model in Verilog and simulate it. Instantiate the multiplexer at the IF stage. ALUResult. For this week. you will implement the WB stage figure 5. ReadData. This is part of a series of labs to implement the MIPS Datapath (figure 1. MEM. and test all of them together. The parent module PIPELINE instantiates I FETCH. MemtoReg 1 From MEM/WB latch From MEM/WB latch Mux Component 1 To ID Registers 0 Figure 5. • The WB module receives inputs from the MEM WB module MemeReg. EX. EX. ID. I EXECUTE.1: The WB stage The parent module PIPELINE instantiates I FETCH (from the previous lab) and I DECODE. and MEM stages of previous weeks. and integrate it together with the IF. and MEM stages. ID. and WB modules. I DECODE. • The module WB instantiates the following module: – MUX. MemtoReg \ 1 32 \ 1 Mux mem_Read_data 32 \ 32 mem_ALU_result \ 0 Figure 5. and label and print out the outputs of the ID EX. the EX EM register.LAB 5 The WB pipeline stage • Testing: Initialize memory to the following hex values. beginning with location 0.2: The multiplexer Lab 5–2 wb_data . • Turn in the source code and the printout of the clock cycle number and outputs the ID EX register. Simulate for sufficient cycles so that all instructions go through the MEM WB register. Be ready to demonstrate. and MEM registers. The control bits should be binary and all other values should be decimal. and the MEM WB register. EX MEM. 002300AA 10654321 00100022 8C123456 8F123456 AD654321 13012345 AC654321 12012345 Be ready to use initialize memory with a given different set of instructions. and r3 from the ID/EX module. i< 24.txt”. 12. Save it to a file named ”data. f o r ( i =0. i< 6 . display registers r1. t x t ”. end • You must add the NOP instruction in the control module.txt”.. . end Similarly for the data memory module: i n i t i a l begin $readmemb ( ” d a t a .MEM) .1 on page Lab 6–2. r2. 3.MEM) . Register r1 should have values 1. i = i +1) $ d i s p l a y (MEM[ i ] ) .2 on page Lab 6–2. • For testing. t x t ”. This is part of a series of labs to implement the MIPS Datapath (figure 1. Lab 6–1 . i = i +1) $ d i s p l a y (MEM[ i ] ) . For this week you will test the datapath with the given binary program in listing 6. • Make sure that r0 is initialized to zero.1 on page Lab 1–2) as a behavioral model in Verilog and simulate it.. f o r ( i =0.LAB 6 Testing the MIPS datapath Objective: To implement and test the MIPS datapath which was built in the previous labs. 6. How to read data in the instruction memory (in the instruction memory module): i n i t i a l begin $readmemb ( ” r i s c . Its opcode is 100000 and the output of the control unit should be all zeros. Save it to file named ”risc. Simulate for 24 cycles. Also the initial contents of memory are given in listing 6. / /LW r 2 . / / NOP / / NOP / / NOP / / NOP / / NOP 1( r0 ) 2( r0 ) 3( r0 ) r 1 . / / NOP / / NOP / / NOP / / ADD r 1 . / / Contents of 0000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 0000 0 0 0 0 0 0 0 0 data 0000 0000 0000 0000 0000 0000 memory 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0010 0011 0100 0101 // // // // // // Data Data Data Data Data Data Listing 6.2: Initial data for memory. / /LW r 3 . Lab 6–2 0 1 2 3 4 5 .LAB 6 Testing the MIPS datapath / / Program t h a t a d d s t h e numbers ( 1 + 2 ) / / And p l a c e s 12 i n r e g i s t e r 1 100011 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 100011 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 100011 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000000 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000000 0 0 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000000 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 000000 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + 3 + 6 + 0 = 12 / / LW r 1 . r3 r 1 . r2 r 1 . r0 Listing 6. / / NOP / / NOP / / NOP / / ADD r 1 . r1 r 1 .1: Binary code for testing the MIPS datapath. / / NOP / / NOP / / ADD r 1 . / / NOP / / NOP / / NOP / / NOP / / ADD r 1 . Modeling. 1995. Hennessy. Bucknell University. Moorby. Kluwer Academic. [5] D. PrenticeHall. CSCI 320 Computer Architecture Handbook on Verilog HDL.Institute of Electrical and Electronics Engineers.Bibliography [1] Michael D. Ciletti. synthesis. 1991. [2] Dr. Patterson and John L. Morgan Kaufmann. Daniel C. [3] IEEE . 1998. IEEE 1364-1995 Verilog Language Reference Manual. Computer Organization & Design: The Hardware/Software Interface (Second Edition). [4] David A. Thomas and P. and rapid prototyping with the Verilog HDL. The Verilog Hardware Description Language. Bib 1 . 1997. 1999. San Mateo. Hyde.
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