J750 Test SystemJ750 BASIC PROGRAMMING TRAINING 1 J750 Test System Class Syllabus • Day 1 – Basic System Configurations – H/W Architecture – S/W Architecture – Workbook and Worksheets – Pin Map Worksheet – Channel Map Worksheet • Day2 – Program Validation – Spec Worksheets Global, DC, AC – Pin Level Worksheet – Test Instance Worksheet – Templates PPMU, DPS – Intro to Flow Table Worksheet 2 J750 Test System Class Syllabus • Day3 – Define Timing Edges and Timing Modes – Time Sets Basic Worksheet – Time Sets and Edge Sets Worksheet – Functional and BPMU Templates – Program Run Controls and Debug Displays • Day4 – Pattern Editor – Pattern compiler – Pattern Language – Pattern Debugger 3 J750 Test System Class Syllabus • Day5 – Characterization Sheet – Shmoo Plot and Adjust Examples – Visual Basic for Test – Interpose Functions – Student Input and Discretionary Time 4 . J750 Test System Hardware Overview •System Overview •Hardware Overview •Configurations •Channel Board 5 . J750 Test System 512 Pin J750 6 . 8 or 16 Meg Per Pin Vector Memory • Flexible Per Pin Timing & Voltage Resources • Per Pin Parametric Measurement Units • Device Data Oriented Programming • Graphical User Interface based on Windows platform 7 .J750 Test System System Overview • 512 and 1024 I/O Channels Test Head Only Packages • 100 MHz Operation • 4. J750 Test System System Overview • Scan Test • A/D and D/A Converter Test • High Voltage Drivers • Embedded Memory Test • Mixed Signal Test (Audio/Video Instruments) • Instruments to Support x32 Parallel Test 8 . 9 half width cards: 4 DPS. 4 CTO.full width cards: 4 Channel cards each side (8 total)Expandable to 16 9 . 1 CUB Power On & Kinematic Coupler controller Connector Both sides .J750 Test System J750 Main Assembly Air Plenum Channel Boards DPS Boards Fan Assembly Power Supply Assemblies Power Supply Bus Bars CTO Boards Card Cage: 17 slots total:Standard CUB Board Center . J750 Test System 512 Pin Configuration Power Supply Power Supply Maximum Config: • 512 I/O channels • 32 High voltage drivers • 32 Device power supplies • 32 Converter test • Memory test option Base: 27” wide x 30” deep x 25” high 10 . J750 Test System 1024 Pin Configuration Power Supply Power Supply Power Supply Power Supply Maximum Config: • 1024 I/O channels • 64 High voltage drivers • 32 Device power supplies • 32 Converter test • Memory test option Base: 27” wide x 30” deep x 33” high 11 . J750 Test System Card Cage Slot Configuration DUT View Slot# 14 12 10 8 6 4 2 0 CHB# 14 12 10 8 6 4 2 0 CTO# 16 17 18 19 20 1 3 5 7 9 11 13 15 CUB Slot# 21 22 23 24 DPS# 2 0 1 3 1 3 5 7 9 11 13 15 2 0 1 3 12 . J750 Test System Pin Identification – Relay Cards (Channel Board) DUT VIEW 13 . J750 Test System Pin Identification – DPS Board DUT VIEW 14 . J750 Test System Pin Identification – CTO Board DUT VIEW 15 . J750 Test System Pin Identification – CUB Board DUT VIEW 16 . J750 Test System Circuit Boards • PCI Board: Interfaces between the local bus in the PC and the TCIO bus on the CUB Installed in the PC • Channel Board: Each Channel Board has 64 channels It also contains utility bits and relay drivers • Relay Board: Switch the signals to the required pin This is also were the pogo pins are mounted Plugs onto the Channel Board 17 . a DC Capture Input. Generates and distributes the master clock. Each channel consist of a DC Source. Provides switched power to the DIB. Two programmable reference sources plus 2 PPMU’s 18 . • CTO (Converter Test Option): An 8 channel high accuracy DC source and measurement board. monitors the fans and DC power supplies. It also contains hardware to calibrate the J750.J750 Test System Circuit Boards • CUB (Clock Utility Board): Interfaces the PCI data bus to the other boards in the J750. • DPS (Device Power Supply): 8 single quadrant power supply channels per board. Fan Monitor DIB & System Power Supply Monitor Cal Circuitry Master Clock Channel Boards Pattern Generator DPS V/I Measure 8Single Quadrant Supplies Timing Generator CTO Measure BPMU PPMU Measure Pin Elec. Source & 2 References 4x HV Utility Bits Relay Boards DIB 19 .J750 Test System J750 System Diagram PC PCIT PC Internal Bus Local Bus Interface Serial Bus Interface CUB TCIO Data Buses DIB Power Supplies Main & Power Supply Aux. J750 Test System Tester Configuration Located: \Program Files\Teradyne\IG-XL\Tester\CurrentConfig.txt 20 . J750 Test System J750 Software Overview • Software Overview • Data Tool • Pattern Tools • Test Templates • Debug Displays • Production Controls 21 . J750 Test System Software Requirements • Windows NT 4.0 / Windows 95 and later • Excel 8.0 (Office 97) and later • Visual Basic 6.0 (optional) 22 . J750 Test System IG-XL Software Diagram Pattern Tools Pattern Compiler Pattern Editor Pattern Debugger Excel Based Tools Data Tool Production Controls Debug Displays Test Templates Resource Drivers Instrument Drivers Tester Hardware 23 . J750 Test System IG-XL Software Diagram Pattern Tools Pattern Compiler Pattern Editor Pattern Debugger Excel Based Tools Data Tool Production Controls Debug Displays Test Templates Resource Drivers Instrument Drivers Tester Hardware 24 . 25 .J750 Test System Data Tool Device Data rather than Test Instrument oriented programming. including debug tools – Using Excel for the User Interface – Using Excel’s spreadsheet functionality – Used to enter Device Data pin names device specifications etc. J750 Test System Data Tool Architecture Pinmap Chanmap Tset Test Instance Determines Active •AC Spec •DC Spec •Level •Tset •Edgeset •Template Specs AC & DC Test Instance EdgeSet Flow Table Job List Levels Defines •PinMap •DC Spec •AC Spec •Pat Group •Pat Set •Test Instance •Flow Table Pat Set Pat Group Compiled Patterns 26 . J750 Test System IG-XL Software Diagram Pattern Tools Pattern Compiler Pattern Editor Pattern Debugger Excel Based Tools Data Tool Production Controls Debug Displays Test Templates Resource Drivers Instrument Drivers Tester Hardware 27 . J750 Test System Pattern Tools • Pattern Tool – Graphical Pattern editor • Pattern Compiler – Graphical Tool to compile ASCII pattern files to binary pattern files • Pattern Reverse Compiler – Graphical Tool to compile binary pattern files to ASCII pattern files • Pattern Control Display – Graphical Tool to control and debug patterns 28 . J750 Test System Pattern Tools – Pattern Tool 29 . J750 Test System IG-XL Software Diagram Pattern Tools Pattern Compiler Pattern Editor Pattern Debugger Excel Based Tools Data Tool Production Controls Debug Displays Test Templates Resource Drivers Instrument Drivers Tester Hardware 30 . J750 Test System Test Templates • Library of predefined test techniques – Written in Visual Basic within Excel – Very powerful and easy to use source level debugger – Code changes can be made without recompiling or reloading – Custom Excel dialog boxes used to view/edit instance specific arguments to the templates 31 . J750 Test System IG-XL Software Diagram Pattern Tools Pattern Compiler Pattern Editor Pattern Debugger Excel Based Tools Data Tool Production Controls Debug Displays Test Templates Resource Drivers Instrument Drivers Tester Hardware 32 . J750 Test System Debug Displays • Test instrument based graphical tools – Display and modify tester setup – Uses low-level instrument drivers to talk to the tester hardware 33 . J750 Test System IG-XL Software Diagram Pattern Tools Pattern Compiler Pattern Editor Pattern Debugger Excel Based Tools Data Tools Production Controls Debug Displays Test Templates Resource Drivers Instrument Drivers Tester Hardware 34 . J750 Test System Production Control Architecture 35 . XL and the test program • The EquipmentSelect control: This control manages finding and selecting a handler or prober driver at run time • The Operator controls: These are GUI components that allow an operator to perform actions or view status. such as a “start test” button or a display of binning results 36 .J750 Test System Production Control The three elements of Production Control are: • The TesterControl control: This provides an interface to the IG-XL executive. and isolates all communication with IG. J750 Test System Test Program Overview • IG-XL Programming • Creating a Test Program • Workbook and Worksheets • IG-XL Toolbar • On-Line Help • Pin Map Sheet • Channel Map Sheet • Lab 37 . Excel workbook with various worksheets of information • Workbooks .xls extension • All data sheets can be exported as ASCII / imported from ASCII source • Test patterns operate under its own application software 38 .saved with .J750 Test System IG-XL Programming • Data Tool operates under Excel • Test program . J750 Test System IG-XL Program Menu 39 . J750 Test System IG-XL Version Select “About IG-XL” from the Teradyne IG-XL program menu 40 . J750 Test System IG-XL Install Verification Select “About IG-XL” from the Teradyne IG-XL program menu 41 . • Each named combination defined one job.J750 Test System Creating a Test Program • A complete test plan consists of the following: – Job List Sheet • Specify combination of sheets that are to be used in creating a test program. utility) 42 . power. Also defines pin group names and their constituent pins – Channel Map Sheet • Establishes how the DUT connects to the tester • Maps individual device pins to test system resources (channels. enables maintaining several “job variants” within the workbook – Pin Map Sheet • Defines device pin names to be used in the test program and its type. DC & AC Specs Sheets • Define the spec symbols and its corresponding values to be used in creating formulas on other sheets – Pin Levels Sheet • Defines values for input and output voltages and current loads to be applied to DUT – Time Set & Edge Set Sheets • Define named combinations of timing values and data formats that will be used during application of test vectors – Pattern Sets & Pattern Group Sheets • Define a named lists of pattern files to be executed by at test instance • Pattern groups are subsets of pattern sets 43 .J750 Test System Creating a Test Program • A complete test plan consists of the following (cont): – Global. and lets parameters for each test instance to be entered – Flow Table Sheet • Defines the order in which tests will be executed and the binning rules that will be used to categorize tested devices – Home Sheet (Auto generated) • Lists all the worksheets & tests.J750 Test System Creating a Test Program • A complete test plan consists of the following (cont): – Test Instance Sheet • Defines the tests that are to be applied to the DUT. with links. for the active job 44 . J750 Test System Creating a Test Program Select “New Test Program” from the Teradyne IG-XL program menu 45 . J750 Test System Creating a Test Program Opening a new program starts of with four basic sheets 46 . J750 Test System Inserting and Deleting Worksheets • New sheets can be added to a workbook (test program) with the “Insert → Worksheet” command • Sheet content can be entered or copied from other sheets • Non IG-XL sheets to be added to a workbook. as sheets of type “Excel Worksheet” • Remove sheets from a workbook by use of the “Edit → Delete Sheet” command 47 . J750 Test System Inserting Worksheets 48 . J750 Test System Inserting Worksheets 49 . J750 Test System Deleting Worksheets 50 . J750 Test System Importing/Exporting Worksheets Worksheets are Imported or Exported as ASCII text files 51 . J750 Test System Importing/Exporting Worksheets Worksheets are Imported or Exported as ASCII text files 52 . however rows can be inserted/deleted within the data area – User may add their own variables or commentary outside the data area. There must be one blank row or column between the data area and the user inserted data 53 .J750 Test System Worksheet Rules • Control of sheet formatting is required for data validation and import and export sheet data – New sheets are created in a fixed format – User must not change column positions within the data area. Font. cell colors – Controlled via Teradyne-defined Excel “Styles” • Required/Optional Data Titles of data columns are displayed in a different color scheme depending on whether the column data is Required or Optional 54 . or a default value • Hatched Cells – Used to indicate that data entry is prohibited or not required • Column Names.J750 Test System Worksheet Format • Grayed text – Used to de-emphasize a value such as #N/A. Format. J750 Test System Worksheet Format 55 . J750 Test System Worksheet Format – Parameter Filter 56 . J750 Test System Worksheet Names • User can give a sheet any name • It is recommended that names be kept as short as possible in order to minimize tab width in Excel and to facilitate import and export from/to different operating systems 57 . like pin or worksheet names – Values can be entered in terms of formulas or equations for timing or voltage levels – Some inputs are entered by use of drop-down lists that Teradyne provides. Clicking on a cell that has a limited set of legal values will produce a dropdown box from which a selection can be made 58 .J750 Test System Data Entry • There are several types of commonly performed data entry: – Data names must be typed in by the user. are usable through the entire workbook. digits. No symbol is sheet specific 59 . groups. and underscore – First character must not be a digit or underscore – Embedded spaces are not allowed • Scope – Symbol names used on any sheet in a workbook. Their scope is that of the workbook. parameters: alphabetic characters of upper or lower case.J750 Test System Data Names • Character Set – Names for pins. g. amps: A. nano: n. “T13”) 60 . for example in equations. mili: m • Generated Names – Based on the variable names defined by the user – Teradyne creates Excel variables of the same name. must use the underscore version of the symbol name – The use of underscores allows the test program to contain symbols that are otherwise reserved for use by Excel such as cell names (e.J750 Test System Data Names • Reserve Names – Units: secs: S. but preceded by an underscore (ex: _tpd) – References to those variables. volts: V – Scaling values: pico: p. micro: u. and “CS” is typed in on the Channel Map sheet. Excel will automatically convert the “CS” to “cs” 61 . Any reference to a name gets converted to the form used at the time of definition. if “cs” is a pin defined on the Pin Map sheet. the names “cs” and “Cs” are treated as the same name – Named cells (variables) retain the case they were defined with.J750 Test System Data Names • Case sensitivity: Excel is case insensitive but consistency is enforced – For example. – For example. though entries using scaling value (=1*ns) are also acceptable – General format “=value*unit” → where unit is one of the predefined scaling values 62 . but the “formula” button maybe used toggle between displaying the formula and resulting value – Cell reference can be made part of formula “=5*_C24” → “5 x value of spec C24” “=5*C24” → “5 x value of cell C24 of the sheet” • Engineering units – Numbers are always displayed in engineering notation (=1E-09).J750 Test System Cell Formulas • Equation – User may enter a purely numeric value or an equation based on previously defined variables – Normal view shows the result of the calculation in the cell. J750 Test System IG-XL Toolbar IG-XL Toolbar and IG-XL Context Bar are added to the Excel toolbar area when the Data Tool is invoked IG-XL Toolbar IG-XL Context Bar 63 . J750 Test System IG-XL On-Line Documentation Help • On-line Help is provided in several ways: – As an add-in to the Excel Help menu – As context sensitive sheet/column help for each sheet – As Help buttons on dialog boxes. where appropriate 64 . J750 Test System On-Line Help 65 J750 Test System Data Tool On-Line Help 66 J750 Test System Creating a Test Program • IG-XL lends itself to bottom-up programming • A complete test plan consists of the following Data sheets – Pin map: Device pin names/groups and type – Channel Map: How the DUT will be connected to the tester, maps individual device pin names to the test system channels and power supplies – AC/DC Specs: Device operation specifications – Pin Levels: Input and output voltages and current loads to be applied to the DUT – Time Sets: Edge sets, period and data formats used by pins/groups with patterns – Patterns: Digital data applied to the device for testing – Test Instance: List of tests required for each Job – Flow Table: Order in which tests will be executed – Job List: Test/manufacturing process related to the particular device: Mask, Package, Temp, Final, QA 67 J750 Test System Test Program Block Diagram Pinmap Chanmap Tset Test Instance Determines Active •AC Spec •DC Spec •Level •Tset •Edgeset •Template Specs AC & DC Test Instance EdgeSet Flow Table Job List Levels Defines •PinMap •DC Spec •AC Spec •Pat Group •Pat Set •Test Instance •Flow Table Pat Set Pat Group Compiled Patterns 68 . J750 Test System Pin Map Sheet • Recommended to be first sheet created • Data used by other sheets and patterns 69 . Inputs. Power and Utility – Pin name and Group name can not be the same name • Note: All pin names must occur before any groups defined 70 .J750 Test System Pin Map Data Entry • Recommended steps – Enter Pin Name in Pin Name column – Select a type from drop-down list – Move down to next row and repeat as needed for each pin on the DUT – Use Excel’s AutoFill feature to rapidly enter pins for buses • Group Names . Analog. – Groups can contain other groups – Groups can contain the following pin types: I/Os.optional – Enter Group name first. then add pin names previously entered in Pin Name column. Outputs. J750 Test System Pin Type – Required Pin type information describes the type of DUT pin. BPMU or other supply pin Gnd A ground pin Unknown A pin whose type is not known or N/C Utility A pin whose type is Utility 71 . and is used during Validation Type Meaning I/O A bi-directional digital pin Input A digital pin that is input only Output A digital pin that is output only Analog A pin that is the CTO pin Power A pin that is the DPS. “-” on the left column of spreadsheet) 72 .J750 Test System Pin Groups Specify group type in the first row only. the rest of the group defaults to that type Type Meaning Input The bus contains only pins of type Input Output The bus contains only pins of type Output I/O The bus contains I/O pins or a mixture of pin types Analog Group contains only pins of type Analog Power Group contains only pins of type Power Utility Group contains only pins of type Utility Expand/Collapse groups using Excel’s built-in Outline function (“+”. J750 Test System Pin Groups Pin names listed in the Pin Group should be ordered MSB to LSB or as they are defined in the patterns 73 . J750 Test System Channel Map Sheet 74 . J750 Test System Channel Map • Defines how the DUT will be connected to the tester – maps individual device pin names to the test system channels and power supplies – defines tester connections for up to 32 parallel test sites – Wiring information for Device Interface Board (DIB) – DIB ID • Imports Pin Map sheet information 75 . J750 Test System Channel Map 76 . Information in site column is ignored • Channel Type must match pin type from Pin Map sheet – DPS to Power pins. 77 . etc.J750 Test System Channel Map – Required • Device Under Test – Pin Name from Pin Map sheet – All pins in the Pin Map must be listed in the Channel Map. assign to N/C – Group names are not allowed • Channel Type – Selects which tester hardware – I/O – DPS – CTSrc – CTCap – CTRefA – CTRefB – Gnd – Utility – N/C . CTSrc to Analog pins. – Pins that are not wired. utility pins to utility bits. J750 Test System Channel Map – Required • Test Channel Site 0 to n – Site 0: – Parallel testing: – Channels: – Power supplies: – CTO channels: – Utility bits: Required Specify Sites 0 to n=31 ch0 to ch1023 dps0 through dps31 ct0 through ct31 u0 through u127 • Note: All site columns must be filled with data even if you are not using all the sites 78 . A-F) characters and must contain dashes in the above positions – Verified at run time with ID PROM on DIB. program won’t run – DIB ID number is shown on the “DIB ID Prom” display 79 .J750 Test System Channel Map – Optional • DIB ID: ID number of the Device Interface Board to be used with this Channel Map – Format: 879-858-20 – Hexadecimal (0-9. If IDs do not match.