IPC-7351B

IPC-7351BGeneric Requirements for Surface Mount Design and Land Pattern Standard Developed by the Surface Mount Land Patterns Subcommittee (1-13) of the Printed Board Design Committee (1-10) of IPC Supersedes: IPC-7351A - February 2007 IPC-7351 - February 2005 IPC-SM-782A with Amendments 1 & 2 December 1999 Users of this publication are encouraged to participate in the development of future revisions. Contact: IPC 3000 Lakeside Drive, Suite 309S Bannockburn, Illinois 60015-1249 Tel 847615.7100 Fax 847615.7105 51 Soldering Processes . . . 29 Environmental Constraints . . . . . . . . . . . . .2 6. . . . . . . . . . . . . . . . . . . . 49 Nonorganic Base Materials .5 1. . . . . . . . . 41 COMPONENT QUALITY VALIDATION . .3 3. . . . . . . . . . .1 1. .IPC-7351B June 2010 Table of Contents 1 1. . . . .3. . . . . . . .5 3. . . . . . . . . . . . . . .3. . . . . .4 3. . . 7 Electronic Industries Association . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 3. . . . . . . . . . . . . . . . . . . . . . . . . . .1.4. . . . . . . . . .2. . . . 43 Assembled Printed Board Test . .3. . . .5 3 3. . . . . . . . 44 Multi-Probe Testing . . 50 Solder Paste Application . . . . . . . .2. . . . . .1. . . . 31 Single-and Double-Sided Printed Board Assembly . . 49 Supporting-Plane Printed Board Structures . . . . . . . . . . . . . .1 5. . . . . . . . . . . . . . . . . . . . .1 3. . . . . . . . . . . . . . 29 Circuit Substrate Development . . . . . . . . . . . . . . . . 7 DESIGN REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 6. .3. . . . .43 Bare Printed Board Test . . . . . . .3. . . . . . . . . . . . . . . . . . . . . . . . .1 3. . . . 41 Solder Mask Finishes . . . . . . . . . . . . . .4. .4. . . . . . . . . . . . . . . . . . . . . . . . . .3. .4 1. . . . . 46 PRINTED BOARD STRUCTURE TYPES .6 3. . . . . . . . . . . . . 1 Purpose . . . . . 2 Producibility Levels . . . . 49 ASSEMBLY CONSIDERATIONS FOR SURFACE MOUNT TECHNOLOGY (SMT) . . . . .4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 7. . . . . . .4 7 7.2. . . . . . . 49 Alternative Printed Board Structures . . 46 General Considerations . . . . . . . . . . . . . . 49 Porcelainized Metal (Metal Core) Structures . . . . . 29 Assembly Considerations . . . . . . . 30 Moisture Sensitive Components . . . .4 3. . .5 5. . . . . .3 5. . .3 2. . . . . . . . . . . . . . . 43 Printed Board and Assembly Test . 49 Organic-Base Material . . . . . . . . 35 Standard Printed Board Fabrication Allowances . . . . . . . . . . . 29 Documentation for SMT .1 6. . . . .2. . 41 Land Pattern Surface Finishes . . . . . . . . . .3 3. . . . . . . . . . . . . . . . . .1 6. . . . . . .2 6. . . . . . . . . . . . . . . . . . . .2 7. . . . . .5 3. . . .3 3. 42 Validation Techniques . . . . . . . . . . . . 50 Adhesive Application . . . . . . . . . . . . . . . 51 Component Placement . . . . . . . . 12 Dimension and Tolerance Analysis . . . . . . 51 iv . . . . . . . . . . . . . . . . . . . . . . . 51 Component Data Transfer . . . . . . . . . . .2 1. . . 44 In-Circuit Test Accommodation . . . . . . . . . . . . . . . . . 1 Component and Land Pattern Family Structure . . . . .35 Via Guidelines . . .4. . . .1 1. 39 Outer Layer Surface Finishes . . . .2. . . . . . . . .7 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 5. .1. . . . . . . . . . . . . . . . . . . . . . . .2. . . . . . . . . . . . . . .4. . . . . . . .3 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Wave Soldering . . . . . . . . . . . . . .5 3. . . 44 Test Strategy for Bare Printed Boards . . . 45 Test Land Size and Shape . . . . . . .7. . . . . .7 5. .2 3. . . . . . . . . . . . . .1 1. . . . .5. . . 41 3. . . . . . 30 Design Rules . .6 3. . . . . . .1. . . . . . . . . . . . . . . .1 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4. . . . 50 Conductive Adhesive . . .3 1.7. . . . . . . . . . . . . . . . . . . .2. . . . . . . . . . . . . . . . . . . . . . .2 3. . . . . . 7 IPC . . . . . 49 Thermal Expansion Mismatch . . . .4. . . . . . . . . . . . . . 8 Land Tolerancing . . . . . .2 5.3 6 6. . . . . . . . . . . . . . .1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Fabrication Allowances .2 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2. . . . . 1 Documentation Hierarchy . . . . . . . . . . . . . .2 7. . . . . . . . . 29 Standard Component Selection . . . 44 Full Nodal Access for Assembled Printed Board . . . . . . .4 5. . . . . . . . . . . . . . . . . . . . . . . . 2 Terms and Definitions . . . . . . .7. . 6 APPLICABLE DOCUMENTS . . . . . . . . . . . . . . . .2 3. . . . . . . . . . . . . . . . 37 Panelization . . . . . . . . .8 3.3 6. . . . . . . .1. .3 7.1 3. .6 2 2.4. . . . . . . . . . . . . 32 Component Stand-off Height for Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 7. . . 7 Joint Industry Standards (IPC) . . . . . . . 2 Performance Classification .4. . . . . . . . . . . .2. . . . . . . . . . . .1. . . . . . 49 High-Density Printed Board Technology . . . . . . .1 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 3. . . . . . . . . . .31 Component Spacing . .2 6. . . . . . . . . . . .1 5. . . . . . . . 7 Component Tolerancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Nodal Access . . . . . . . . . . . . . . . . .2 5.4 6. . . . . . . . . .1 5.1 5 5.7 Dimensioning Systems . . . . . 12 Assembly Tolerancing . . . . . . . . 29 SMT Land Pattern . . . . . . . .1 SCOPE . . .1 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 End-Use Environment Considerations .2 5. . . . . . . . . 33 Conductors . . . . . . . . . . . 42 TESTABILITY . . . . . .1. . . . . . . . . . . . . . . . . . . .2. . . . . . 3 Revision Level Changes . . . . . . . 45 Printed Board Test Characteristics . . 49 Substrate Preparation . . . . . . . . . . . . . . . . .4 7. . . .4. . 45 Clam-Shell Fixtures Impact . . . . . . . . . 49 Constraining Core Structures . 50 Solder Preforms . . . . . . . . . . . . . . . . . . . . 45 Test Land Pattern Spacing . . . . . . .3 3. . . . . . . . . . . .4. . . . . . . . . . . . . . 45 No Nodal Access . . . . . . . . . . . .1 5. . 12 Design Producibility . . . . . . . . . . . . . .1 Solder Mask Clearances . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Fiducial Marks . . .2 5. . . . . . 7 Joint Electron Device Engineering Council (JEDEC) . .5. . 45 Design for Test Parameters .4 7. . . . . . . . . 49 SMT Assembly Process Sequence . . . . . . . .2. . . . . . . . . .2. 7 International Electrotechnical Commission . . . . . . . . . . . 43 Test Philosophy . . . .3 6. . . . . . . . . .5 3. . . . . . . .4 3. . . . . . . . . . . .4. . . . . . . . . . . . . . . . . . . . 48 Categories . . . . . . . . . . . . . .1. . . . . . . . 29 Provision for Automated Test . . . . . . . . . . . . .2 2. . . 45 Limited Nodal Access . . . . . .2 3. .6 5. . . . . . . . . . . . . . . . . . .2.5. . . . . . . . . . . . . . . . . . . . . . 2 Land Pattern Determination . .3 4 4. .2 5. . . . . .4 2. . . . . . . .1 7. . . . . . .4. . .2 8. . .3 8. . . . . 53 Conduction Reflow Soldering . . .11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 8. .3 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Resistance to Soldering Process Temperatures . . . . . . . . . . . . . . . . . . . . . . . . . 57 Marking . . . . . 60 Carrier Package Format .3 8. . 58 Marking . . . . . . 60 Small Outline Diode. . . 60 Resistance to Soldering Process Temperatures . . . . . 62 SOP8/SOP64 (SOP) . . . . . . . . . . . . .10 8. . . . . . . . . . . . . . . . . . . . . . . . . 58 Carrier Package Format . .1.3. . . . . .3 9. . . . . . .3. .6 7. .4. . . . 57 Resistance to Soldering Process Temperatures . . . . . . . . . . . . . . . . . . . . .2 7. . .12. .8.11. . .5. . . . .4 8. . 64 Carrier Package Format . . . . . . . INDM. .4. .11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4. . .3 7. . . . . . . . . . . . . . . . .2. . . . . . . . . .1 8. . . . . . . 64 SOP127 . . . . 63 Resistance to Soldering Process Temperatures . . 60 Marking . . . . . . . . . . . 59 SOT143 . . . . . . . . . . . . . . . . . . . . .1 8. . . . 60 Marking . . . 61 Resistance to Soldering Process Temperatures . . . 58 SOD123 . . . . . . . . .2 8. . . . . . . . . . . . . . . . . . . 58 IPC-7351B 8. . . .1. . . . . . . . . . . . . 58 Resistance to Soldering Process Temperatures . . . . . . . . 57 Marking . . .5 7. . . . . . . . . . . 54 Basic Construction . . . . . . . .5 8. . . . . .5. . . . 57 Carrier Package Format . . . . . .3 9. . . . . . . . . . . . . . . . . . . . . . .13. . . . . . . . . . . . . . 60 Carrier Package Format . . . . . . . 59 Resistance to Soldering Process Temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Basic Construction . .4 8. . 54 Chip Resistors (RESC) . . . . . . . . . . 58 Basic Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 8. . . . . . .2 8. . . . . . . 55 Carrier Package Format . 55 Marking . . . . 57 Basic Construction . . . . . . . . . . . . . . . . . 53 Repair/Rework . . . . . . . . . . .2 8. . 59 Carrier Package Format . . . .3. . . . . . . . .1 8.7.1 9. . .2 9. . . .1 8. . . . . . . . RESM) .1 8. . . . . .7 8. . . . 59 Marking . . .1 9. . INDP) . . . . . . . . . . . . . . . . CAPM. .13. . . . . . . . . . . . . . . . . . .2 8. . . . . . . . . . . . . . . . . . . . .3 8. .60 Basic Construction . . . . . . . . . . . . . . . . .4 9. . . . . . . . . . 59 DPAK (TO) . . . . . . . . INDP. .8. 59 Basic Construction . . . . . . . . . INDM. . . . . . . . . . . . . . 64 Marking . . . . . . 59 Resistance to Soldering Process Temperatures . . . . . .1 8. . . . . . . . . . . . . . . . . . . . . . . . . 55 Resistance to Soldering Process Temperatures . .3. 56 Marking . . . . . . 59 Basic Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2. . . . . . . . 55 Chip Capacitors (CAPC) . . . .1 8. . . . . . . . . .3 8. . . . . . . 61 Carrier Package Format . . 58 Marking .1 8. . . . .2 8. . . .6. . . . . . . . 52 Laser Reflow Soldering . . Flat Lead (SODFL)/Small Outline Transistor. 58 Basic Construction . . . . . . .9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 8. .12. . . . . . . . . .4. . 53 Dependence on Printed Board Material . . . . . . . . . . .5 7. . . . . . . 63 Carrier Package Format . . . . . . . . 61 SOIC . . .3. . . . . . . . . . . . . . . . . . . . . . . .10. . . . . . . . . . . . . 61 Basic Construction . . . . . . 62 Basic Construction . .2 8.9 8. . . . . . . . . . . . . . 53 Heatsink . . . . . . . . . . . . . . . . . . . . . .3 8. . . . . . . . . . . . . .4 8. . . . . . . . . 62 Carrier Package Format . 56 Inductors (INDC. . . . . . . . . . . . . . . . 53 Dependence on Copper Land and Conductor Layout . 60 Electrolytic Aluminum Capacitor (CAPAE) . . . . . . . . . . . . . .6. . DIOM. . . . . . . . . . . . .2 8. . . . . . . . . . . . . . . . . . .11 8. . . . . . . . . . . . . . . . . . . . . . . . 58 SOT89 .4 8. .9. . . . . . . . .2. . . . . . .1 7. . . . . . . . . 53 IPC-7352 DISCRETE COMPONENTS . . . . . . . . . . . . . . . 59 SOT223 . 58 Carrier Package Format . . . . . . . . . .2 8. . . LEDM. . . .8 8. .4.10. . . . . . . . .3 8.2 8. . . . . . . . . . . . . .1. . 61 Marking . . . . . . . .7. . . .12. . . . . . . . . 56 Carrier Package Format . . . . . . . .3 8.1 9. . . .1 8. . . .2 9. . . . . . . .1. . . . . . . . . . . . . .4 7. . . . . . 55 Resistance to Soldering Process . . . . . . . . . . . . .1 8. . . . . . . .3 8. . TWO SIDES . . .2. . .4 8. .8. . . . . . . . . . . . . . . . . . . . .4. 62 Resistance to Soldering Process Temperatures . . . . . . . . . . Flat Lead (SOTFL) . 58 Resistance to Soldering Process Temperatures . . . .4 8. . . . . .1 8. . .1. . .13. . . . . . . . . . .11. . .6 7. . . . .1. . . . . . RESMELF) . . . . .2 8. . . . . .10. .June 2010 7. . . . . . . . . . . . . . . . . . . . . . . . .6. . . . . . . . . . . . . . . . . . . . . . . . . . 56 Basic Construction . . . . . . . . . . . . . . .5. . . 57 Basic Construction . . . . . . . . . . .1 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 9. . .2 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Carrier Package Format . . . . . . . . . .7. . 64 v .6. 58 Marking . 57 SOT23 . . . . . . . . . . . . . . . . . . . . . .6. . .1. . . .2 7. . . .2 8. . 56 Resistance to Soldering Process Temperatures . . .10. . . . . .9. . . . . . . . . . . . . . . . . . .1 9. . . . . . . . . . . . . . . . . . . . . . . .3 8. . .12. . 58 Basic Construction . . . . . . . . .4 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 8 8. . . . . . . . . . . . . . . .6. . . . . . . . . . . . . . . 58 Carrier Package Format . . . . .2. . . .1 8. . . . . . . . 54 Marking . . . . . . .6. . . . . .4 8. . . . . . . . . . . . .2. . 52 IR Reflow Soldering . . . . .13 8. . . . . . . . . . . . 62 Marking . . . . . . . . . . . .4. . . . . . . . .2. . . . . . . . . . . . . . . . . . . . .3 Vapor Phase (VP) Soldering . . . . . . . . . .12 8. .3 8.2 8. 61 IPC-7353 GULLWING LEADED COMPONENTS. . . . 60 Basic Construction . . . . 52 Hot Air/Gas Convection . .4 8. . . 55 Basic Construction . . . 55 Carrier Package Format . . . . . . . . . .3 9. . . . . . . .3 8. . . . . . . 57 Resistance to Soldering Process Temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Marking . . . . . . . . . .6 8. . . . . . . . . . . . . . . . . . . . .2. . . . . . . . . . . 56 Molded Body (CAPMP. . . . 63 Marking . . . . . . . . . 59 Carrier Package Format . . . . . .4 9 9. . . . . . . . . . .3. . . . . . . . . . . . . . . . . . .4 8. . . . . .9. . .5. . . . . . . . . . . 53 Cleaning . . 57 Metal Electrode Face (DIOMELF. FUSM. . . . . 60 Resistance to Soldering Process Temperatures . . . . . . . . . . .4 9. . . . . . . . . . . . . . . . . . . . . .3 8. . . . . . .8. .1 8.13.7. . . . . . . . . . . . . .5. . . . . . . 64 Marking . . . . . . . . . . . . PSON) . . . . . . . . . . . . . .2 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OSCCCC) . . . . . . . . . . . . . . .1 12 June 2010 PLCC . . .1 15. .2. . . . . . . . 93 Test Patterns -In-Process Validator . . . . . .1 12. . . . . .2 10. 8 Example of 3216 (1206) Capacitor Dimensioning for Optimum Solder Fillet Condition . . . . . . . . . . . . . 80 Flat Chip Array Packages (RESCAF. . . .95 Software Usage . . . . . . . . . . . . . . . . . . . 66 11. . . . . . . . . . . . . . . 64 CFP127 . 72 Marking . .4. . . . . . .3. . . . . . 80 Chip Array Component Lead Packages . . . . . . . . . . . . . . . . . . . .1. .2. . . . . . . . . . . . . . . . . . . . . . . . . . . 72 IPC-7358 AREA ARRAY COMPONENTS (BGA. . .1. . . . . . . . .4 15. . . . . . . . . . . . . .2 15. . . . . . . . . . . . . . . . . . . . . .1. . . . 72 Carrier Package Format . PQFN. . . . . . . .1 13. . . . . . . . . . .4. . . . . . . . . . . . . . . . . . . . . . . . . INDCAV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 IPC-7355 GULL-WING LEADED COMPONENTS. . . . . . . . . . . . . 83 Marking . . . . . . . . . . . . . . . . 73 BGA Packages . . . . .5 15. . . . . CGA. . . . . . . . 85 Carrier Package Format . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Carrier Packages Format . . . . . . 85 Small Outline and Quad Flat No-Lead with Pullback Leads (PQFN. .2 14. .1. . .4. . . . . . . . . .1. . . . . . . 65 Process Considerations . . 82 Carrier Package Format . . . . . 78 Land Pattern Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 15. . . . . . . . . . . . . . . . 85 Carrier Package Format . . . . . .4 16 Land Approximation . . . . . . . . . . . .2 13. . . . . . . . . .4 15. . . . . . . . . . . . . . 78 Handling and Shipping . . . 65 Carrier Package Format . 82 Quad Flat No-Lead (QFN) . . .1 Basic Construction . . . . .1 14. 85 Resistance to Soldering Process Temperatures . . . . . . . . . . .3. . . .2 B. . 72 Termination Materials . . . . . . . .2 15. . 68 Carrier Package Format . . . . . 94 APPENDIX B IPC-7351 LAND PATTERN CALCULATOR . . Chip Array) . . . . . . . . . . . . . . FOUR SIDES . . . . . . . . . . . . . 66 15. . . . . .5. . . . . . .3. . . . . . . . . . .3 14. . . . .5. 86 ZERO COMPONENT ORIENTATIONS . . . . . . . . . . . . . . . . . . . . . . .5. .2 12. . . . . . 64 IPC-7354 J-LEADED COMPONENTS.3 11. . . . . . . . . . . . . . . . . 69 IPC-7356 J LEADED COMPONENTS. . . .2 11. . .2. . . . . . . . . . . . . . . . . . . 82 Process Considerations . . 69 12. 81 LCC . .77 Attachment Site Planning . . 76 Contact Matrix Options . . . . . . 80 Convex Chip Array Packages (RESCAXE. . . . 84 Small Outline No-Lead (SON) . . . CAPCAF. . . . . 80 Concave Chip Array Packages (RESCAV. . . .1. . . . . . .5 14.1 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2. . . . .2. . TWO SIDES . . PSON. . . .2. .2 14. . . 76 Plastic Land Grid Arrays (LGA) . . . . . .79 Land Pattern Calculator . . .5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 B. . . . . . . . . . . . . . . . .1 10. . . .1 12. . . . . . . . . .3 Test Vehicle . . . . . . . . . . . . 71 PLCCR . . . .4 BQFP or PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2. . . . . . . . . . 73 14. . . . . . . . . . . . . . . . .3 10. . . . 86 APPENDIX A (INFORMATIVE) TEST PATTERNS — PROCESS EVALUATIONS . . . . . . . . . .1 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2. . .1 15. . . . . . . . . . . . . . . . . OSCSC. . .1 14. . . . . . . . . . . .2. . . . . 84 Process Considerations . . . . . . . . . . . .1. . . . . . . . . . 71 Premolded Plastic Chip Carriers . . . . . . . . . . . . . . . . . . . . . 71 Postmolded Plastic Chip Carriers . . . . . . . INDCAF) . . . . . . . . . .3. . . . . . . .1 11. . . . . . . . . . . . . . . . . . 85 Solder Mask Considerations . . . . . . 85 Basic Construction . . . . . .3 Software Installation . . . . . . . 84 Solder Mask Considerations . . . . . . . . .1. . . . . . . . .2 12. . . . . .3 14.5. . . . 84 Carrier Package Format . . . .4 Area Array Configurations .3 14. . .2 14. . . .2 13 13. . . .1 B. TWO SIDES . . . . . . . . . . . . . . . . . . . . . .1 11. . . . . . . . . . . .3. . . .4. . 71 IPC-7357 POST (DIP) LEADS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 15. . . . . . . . . . . . . . 76 General Configuration Issues . . . . . . . . . . . . . . . . . . . .1 A. . . . . . . . . . 65 Marking . . RESCAXS) . . . . 74 Fine Pitch BGA Package (FBGA) . .1 14. . . 76 Selective Depopulation . . . . . . . . .5 14. . . .5. . . . . . . . . . . .4 9. . . . . . . . CAPCAV.3 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 15. . . . . . . .1 15. . . . .IPC-7351B 9. . . . . . . . . . . . . .4.3 10 Resistance to Soldering Process Temperatures . . . . . . . . . . . . . . . . . . . . . .1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . FOUR SIDES . . . . . . . . . . . . .4 14. . . . . . . . . . . . . . . . . . 65 10. . .1 14. . . .95 Software Updates . . . . .2 9. . . . . . . . 75 Ceramic/Plastic Column Grid Arrays (CGA) . . . . . . . . . . . . . . 68 Carrier Package Format . . . . . . . . . 78 15 IPC-7359 NO-LEAD COMPONENTS (QFN. . . . . . . LGA. FBGA.1 15. . . . . . . . . . . . . . . . . . . .2. . . . . . . . . . DFN. . . . . . . . . . . . . . . . . . 72 Resistance to Soldering Process Temperatures . 85 Marking . . . . . 81 15. . . . . . . . . . . . . . . . . .2. 71 Postmolded Plastic Chip Carriers . . . 95 FIGURES Figure 3-1 Figure 3-2 Profile Tolerancing Method .1 11. . . 85 Dual Flat No-Lead (DFN) . . . . . . . . .4 14. . . . . . . . . . . . .3 14. . . . . . . . . . .3 15. . . . . . . . . . .2 A. . . . . . . . 68 CQFP . .4 11 14. . . . . . . . . . . . . . . . .1 9. . 81 Marking . .3. . . . 71 Premolded Plastic Chip Carriers . . . . . . . . . 64 Resistance to Soldering Process Temperatures . . . . . .1. . . . . . . . . . . . . . . . . . . . . . . . . .4 14 14. . . . . 85 Marking . . . . . . . 68 QFP . . 77 Defining Contact Assignment . . . . . . . . . 93 Stress Testing . . . . . . . . . . LCC) . . . . . . . . . . . . 93 A. . . . . . . 68 Carrier Package Format . . . . . .2. . . . . . . 85 Process Considerations . . . . .3 15. . 76 Device Outlines . . . . . . . . 9 vi . . . . . . . . . . . .2 14. . . . . . . .3 9. . . .3 13. . . . . . . . . . . . . . SON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Breakaway (Routed Pattern) with Routed Slots . . . . . 41 Component Operating Temperature Limits . . . . . . . . . . . . . . . . . . . . . 33 Global/Panel Fiducials . . . . . . . . . . . . . . . . . . . . . 44 General Relationship between Test Contact Size and Test Probe Misses . . . 71 Figure 12-2 PLCCR Construction . . . . . . . . . . . . . . . . . . 60 Figure 8-14 Aluminum Electrolytic Capacitor (CAPAE) Construction . . . . . . . . 37 Conductor Description . . . . . . . 76 Figure 14-6 One Package Size. . . . . 39 Conductor Clearance for V-Groove Scoring . . . . . . . . . . . . . . . 59 SOT223 Construction . . . . . . . . . . . . . . . Two Full Matrices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 16-1 Zero Component Rotations for Common Package Outlines . . . . . . . . . . . . . . . . . .39 Examples of Modified Landscapes . . . . . . . . . . . . . . . . . . . . . . . . 35 Examples of Via Positioning Concepts . . . . . 71 Figure 13-1 DIP Construction . . . . 81 Figure 14-15 Flat Chip Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 14-12 Corner Concave Chip Component . . . . . . 36 Vias under Components . . . . . . . . . . . 42 Test Via Grid Concepts . . . . . . . . . . . . . . . . . . . . 36 Filled and Capped Via Structure . . 81 Figure 14-14 Convex Chip Component “S Version” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 MELF Component Construction . . . 60 Figure 8-15 SODFL/SOTFL Construction . . . . . . . . . . . . . . . . . . . 81 Figure 15-1 LCC Component . . . . . . . . . . . . . . . . . . . . . . . . . . 59 SOT143 Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 12-1 PLCC Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 15-4 QFN Devices with Multiple Paste Mask Apertures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Fiducial Size and Clearance Requirements . . . . . . . . . . . 34 Use of Vias in High Component Density Printed Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 SOD123 Construction . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 15-7 DFN Construction . . . 41 Pocket Solder Mask Window . . . . . . . 77 Figure 14-10 Device Orientation and Contact A1 Position . . . . . . . . . . . . 10 Pitch for Multiple Leaded Components . . .June 2010 Figure 3-3 Figure 3-4 Figure 3-6 Figure 3-7 Figure 3-8 Figure 3-9 Figure 3-11 Figure 3-10 Figure 3-13 Figure 3-12 Figure 3-14 Figure 3-15 Figure 3-16 Figure 3-17 Figure 3-18 Figure 3-19 Figure 3-20 Figure 3-22 Figure 3-21 Figure 3-23 Figure 3-24 Figure 3-25 Figure 3-26 Figure 4-1 Figure 5-1 Figure 5-2 Figure 5-3 Figure 7-1 Figure 7-2 Figure 8-1 Figure 8-2 Figure 8-3 Figure 8-6 Figure 8-7 Figure 8-5 Figure 8-8 Figure 8-9 Figure 8-10 Figure 8-11 Figure 8-12 Figure 8-13 IPC-7351B Profile Dimensioning of Gull-Wing Leaded SOIC . . . . . . . . . . . 68 Figure 11-1 BQFP Construction . . . . . . . . . . 74 Figure 14-3 Ceramic/Plastic Column Grid Array (CGA) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 SOT 89 Construction . . . . . . . . . . . . . . . . . . . . . . . 35 Land Pattern to Via Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 14-5 Variation of BGA Contact Pitch in Common Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 11-2 QFP Construction . . . . 40 Gang Solder Mask Window . . 27 Component Orientation for Wave-Solder Applications . . . . . . . . . . . . . . . 57 Molded Body Construction . . . 46 Typical Process Flow for One-Sided SMT . . . . . . . . 64 Figure 9-4 CFP127 Construction . . . . . . . . . . . . . . . . 85 Figure 15-6 Pullback Quad Flat No Lead (PQFN) and Small Outline No Lead (PSON) Construction . . . .50 Packaging of Discrete Components . . . . . . . . . . . . . . . . . . . . . . . . 38 Typical Copper Glass Laminate Panel . . . . . . 82 Figure 15-2 Quad Flat No-Lead (QFN) Construction . . . . . . . 72 Figure 14-1 Ball Grid Array (BGA) IC Package Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 SOT23 Construction SOT23 Construction . . . 61 Figure 9-1 SOIC Construction . . . 64 Figure10-1 SOJ Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Examples of Land Shape Modifiers . . . . . . . . 31 Alignment of Similar Components . 81 Figure 14-13 Convex Chip Component “E Version” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Local Fiducials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 15-5 Small Outline No-Lead (SON) Construction . . . . . . . . . . . . . . . . 77 Figure 14-7 Perimeter and Thermally Enhanced Matrices . . . . . . 74 Figure 14-2 Example of Plastic BGA Package Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 DPAK (TO) Construction . . . . . . . . . . 63 Figure 9-3 SOP127 Construction . . . . . . . . . . . . . . . . . . . . . 34 Fiducial Locations on a Printed Board . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 15-3 Quad Flat No-Lead (QFN) Construction (Cross-Sectional View) . . . . . . . . . . . . . . . . . 45 Test Probe Feature Distance from Component . . . . . . 37 Via-in-Pad Process Description . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 11-3 CQFP Construction . . . . . . . . . . . . . . . . . . . . . 76 Figure 14-4 Plastic Land Grid Array (LGA) Package Construction . . . . . . . . 25 Examples of Chamfered Corner Modifiers . . . . . . 87 Figure A-1 General Description of Process Validation Contact Pattern and Interconnect . . 77 Figure 14-8 Staggered Matrix . . . . . . 78 Figure 14-11 Side Concave Chip Component . . . . . . . . . . . . . . . . . . . . 63 Figure 9-2 SOP8/SOP63 Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Assembly Process Flow for Two-Sided Surface Mount with THT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 vii . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 14-9 Selective Depopulation . . . . . . . . 57 Break-Away Diagram of MELF Components . . 54 Chip Resistor Construction . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Chip Capacitor Construction . . . . . . . . . . . . . . . . . . . . . . . 20 Small Outline and Quad Flat No-Lead with Pullback Leads (unit: mm) . . . . . . . . . . . . . . . . . . . . . . .046 mm [0. . 24 Product Categories and Worst-Case Use Environments for Surface Mounted Electronics (For Reference Only) . . . . . . . 70 Package Peak Reflow Temperatures . . . . . . . 21 Small Outline Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Package Peak Reflow Temperatures . . . 75 Ball Diameter Sizes (mm) . . .625 mm pitch) (unit: mm) . . . . . . . . . . . . . . 18 Inward Flat Ribbon L-Leads (Molded Inductors. . 83 Package Peak Reflow Temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . 0. . . . . . . . . 80 Land-to-Ball Calculations for Current and Future BGA Packages (mm) . . . Two Sides . . . 55 Package Peak Reflow Temperatures . . . . . . . . . . . . . . . . . . . . 16 Rectangular or Square-End Components (Capacitors and Resistors) Equal to or Larger than 1608 (0603) (unit: mm) . . . . . . . . 79 BGA Variation Attributes (mm) . . . . . . . . 73 Solderability Tests for Discrete Components . . Bath Method: Test Severities (duration and temperature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bath Method: Test Severities (duration and temperature) . . . . . . . . . . . . . . . 38 Key Attributes for Various Board Surface Finishes . . . . . . . . . . . . . . . . . . . . . . . . 69 Solderability. . . . . . . . . . . . . . 79 Land Approximation (mm) for Non-Collapsible Solder Balls . . . . . . . . . . . . . . 20 Corner Concave Component Oscillator Lead Package (unit: mm) . . . 65 Solderability. 17 Leadless Chip Carrier with Castellated Terminations (unit: mm) . . . . . . . . . . . . . . 66 Solderability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flat Lead (unit: mm) . . . . . . . . . . . . . . . . . . . . . . . . . . 16 J Leads (unit: mm) . . . 73 Package Peak Reflow Temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 JEDEC Standard JEP95Allowable Ball Diameter Variations for FBGA (mm) . . . . . . . . . . . . . . . . . . . . . . . . 62 Solderability. . . . 18 Convex Chip Array Component Lead Package (unit: mm) . . . . . . 48 Solderability Tests for Discrete Components . . . . . . . . . . . . . . . . . . . . . 20 Column and Land Grid Array (unit: mm) . . . . . . Four Sides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Land Approximation (mm) for Collapsible Solder Balls . . Two Sides . . . . . . . . . .IPC-7351B Figure A-2 June 2010 Photoimage of IPC Test Board for Primary Side . . 67 Solderability Tests for J-Leaded Components. . . . . . . . . . . . . . . . . 21 IPC-7351 Land Pattern Naming Convention . . . . . . . . . Bath Method: Test Severities (duration and temperature) . . . . . . . . . . . . . . . . . . . . 83 viii . Bath Method: Test Severities (duration and temperature) . . . . . . . . . . . . . . 66 Solderability Tests for Gullwing Components. . . . . . Diodes & Polarized Capacitors) (unit: mm) . . . . . . . 70 Solderability Tests for Post (DIP) Leads. . . . . . . . . . . . . . . . 72 Solderability. . 80 Solderability Tests for No Lead Components . . . . .38 Feature Location Accuracy (units: mm [in]) . . Bath Method: Test Severities (duration and temperature) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Nominal Finished Conductor Width Tolerances. . . . . . . . . . . . . . . . . . . . . . 17 Cylindrical End Cap Terminations (MELF) (unit: mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Printed Board Structure Material Properties . . . . . 82 Solderability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Package Peak Reflow Temperatures . . . . . . . 19 Small Outline No-Lead (unit: mm) . . . . . . . . 20 Aluminium Electrolytic Capacitor and 2-pin Crystal (unit: mm) . 17 Rectangular or Square-End Components (Capacitors and Resistors) Smaller than 1608 (0603) (unit: mm) . . . . .625 mm pitch) (unit: mm) . . . . . . . . . 46 Printed Board Structure Selection Considerations . 74 Package Peak Reflow Temperatures . . . . . . . . . 67 Package Peak Reflow Temperatures . . 16 Flat Ribbon L and Gull-Wing Leads (less than or equal to 0. . . . mm [in] . . . . . Bath Method: Test Severities (duration and temperature) . . . . . . Four Sides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Butt Joints (unit: mm) . . . 15 Flat Ribbon L and Gull-Wing Leads (greater than 0. . . . . . . . 19 Quad Flat No-Lead (unit: mm) . . . . . . . . . . . . . 63 Solderability Tests for J-Leaded Components. . . . . . . . . . . . . . Two Sides . . . . . . . 17 Concave Chip Array Component Lead Package (unit: mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Solderability. . 19 Ball Grid Array Components (unit: mm) . . . . . . 94 Table 6-1 Table 6-2 Tolerance Analysis Elements for Chip Devices . . . . . . . . . . . . . . . . . . 18 Flat Chip Array Component Lead Package (unit: mm) . . . . . . . . . . . . . . . . . . . Bath Method: Test Severities (duration and temperature) . . . . . . . . . . . . . . . . . . . . . 42 Table 6-3 Table 8-1 Table 8-2 TABLES Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7 Table 3-8 Table 3-9 Table 3-10 Table 3-11 Table 3-12 Table 3-13 Table 3-14 Table 3-15 Table 3-16 Table 3-17 Table 3-18 Table 3-19 Table 3-20 Table 3-21 Table 3-22 Table 3-23 Table 3-24 Table 3-25 Table 3-26 Table 3-27 Table 8-3 Table 9-1 Table 9-2 Table 9-3 Table 10-1 Table 10-2 Table 10-3 Table 11-1 Table 11-2 Table 11-3 Table 12-1 Table 12-2 Table 12-3 Table 13-1 Table 13-2 Table 13-3 Table 14-1 Table 14-2 Table 14-3 Table 14-4 Table 14-5 Table 14-6 Table 14-7 Table 14-8 Table 15-1 Table 15-2 Table 15-3 Printed Board Structure Comparison . . . . . 55 Solderability Tests for Gullwing Leaded Components. 19 Flat Lug Leads (unit: mm) . . . . . . . . . . . . . . .0018 in] Copper. . . JEDEC standard component outlines). and rework of those solder joints. reflow.1  Purpose  The intent of the information presented herein is to provide the appropriate size. Note 5: For surface mount components. Adjustments for wave or other soldering processes. Note 1: The dimensions used for component descriptions have been extracted from standards listed in Section 2.2  Documentation Hierarchy  This standard identifies the generic physical design principles involved in the creation of land patterns for surface mount components. within “PCB Tools and Calculators. 1 . org) under the “Knowledge” menu. but the mechanical support as well. given in this standard are related to the reflow soldering process.g. clearance between the bottom of the component and the printed board surface (if relevant). have to be carried out by the user. Updates to land pattern dimensions.ipc. The IPC-7351 Land Pattern Calculator is provided on CD-ROM as part of this standard. Caution: Users should be aware that individual component data sheets may not meet standardized component outlines (. Note 3: This standard assumes that even under worst case tolerance conditions the opportunity for an acceptable solder fillet will be maintained. particularly the courtyard. solder paste stencil aperture sizes. as well as surface mount design recommendations for achieving the best possible solder joints to the devices assembled.. thus.June 2010 IPC-7351B Generic Requirements for Surface Mount Design and Land Pattern Standard 1  SCOPE This document provides generic requirements on land pattern geometries used for the surface attachment of electronic components. the individual component dimensions and corresponding land pattern recommendations based upon families of components. and suitable rules for adhesive applications. Note 2: Elements of the mounting conditions. Heavier components (greater weight per land) require larger lands. 1. The producibility aspects also pertain to the use of solder mask and the registration required between the solder mask and the conductor patterns. This may also be relevant when solder alloys other than eutectic tin lead solders are used. shape and tolerance of surface mount land patterns to insure sufficient area for the appropriate solder fillet to meet the requirements of IPC J-STD-001. can be found on the IPC website (www. and is supplemented by a shareware IPC-7351 Land Pattern Calculator that provides.e. or other type of soldering. 1. including patterns for new component families. considering additional measures may be necessary. such as solder mask clearance. These additional features become part of the overall land pattern standard for each component type. subjected to wave. testing. In addition to the land pattern geometries required for proper solder joint formation. the solder joints provide not only the electrical connection. Designers should refer to the manufacturer’s data sheet for specific component package dimensions. in these cases. In some cases the lands shown in this standard may not apply for a particular application and may need to be increased in a land pattern library. clearance between adjacent components. through the use of a graphical user interface. Whether parts are mounted on one or both sides of the printed board. adding additional land pattern surface will increase surface area of molten solder to enhance capabilities of extra weight. keep-out areas (if relevant). Designers can use the information contained herein to establish standard land pattern geometries not only for manual designs but also for computer-aided design systems. Land patterns become a part of the printed board circuitry and they are subject to the producibility levels and tolerances associated with fabrication and assembly processes. Note 4: Heat dissipation aspects have not been taken into account in this standard. and also to allow for inspection.’’ See Appendix B for more information on the IPC-7351 Land Pattern Calculator. other mounting conditions must be considered. if applicable. the land pattern and part dimensions should be optimized to insure proper solder joint and inspection criteria. Greater mass may require slower process speed to allow heat transfer.