Ipc 6012C Draft

DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLYIPC-6012C Qualification and Performance Specification for Rigid Printed Boards PROPOSED STANDARD FOR BALLOT – JANUARY 2010 1 SCOPE 1.1 Statement of Scope This specification establishes and defines the qualification and performance requirements for the fabrication of rigid printed boards. 1.2 Purpose The purpose of this specification is to provide requirements for qualification and performance of rigid printed boards based on the following constructions and/or technologies: • • • • • Single-sided, double-sided printed boards with or without plated-through holes (PTHs). Multilayer printed boards with PTHs with or without buried/blind vias. Multilayer printed boards containing build up High Density Interconnect (HDI) layers conforming to IPC-6016. Active embedded passive circuitry printed boards with distributive capacitive planes and/or capacitive or resistive components. Metal core printed boards with or without an external metal heat frame, which may be active or non-active. 1.2.1 Supporting Documentation IPC-A-600, which contains figures, illustrations and photographs that can aid in the visualization of externally and internally observable acceptable/nonconforming conditions, may be used in conjunction with this specification for a more complete understanding of the recommendations and requirements. 1.3 Performance Classification and Type 1.3.1 Classification This specification establishes acceptance criteria for the performance classification of rigid printed boards based on customer and/or end-use requirements. Printed boards are classified by one of three general Performance Classes as defined in IPC-6011. 1.3.1.1 Requirement Deviations Requirements deviating from these heritage classifications shall be as agreed between user and supplier (AABUS). 1.3.1.2 Space and Military Avionics Deviations Space and Military Avionics performance classification deviations are defined and listed in Appendix A of this specification. These are commonly referred to as Class 3/A. 1.3.2 Printed Board Type Printed boards without PTHs (Type 1) and with PTHs (Types 2-6) are classified as follows: Type 1—Single-Sided Printed Board Type 2—Double-Sided Printed Board Type 3—Multilayer Printed Board without blind or buried vias Type 4—Multilayer Printed Board with blind and/or buried vias Type 5—Multilayer metal core Printed Board without blind or buried vias Type 6—Multilayer metal core Printed Board with blind and/or buried vias 1.3.3 Selection for Procurement Performance class shall be specified in the procurement documentation. The procurement documentation shall provide sufficient information to fabricate the printed board and ensure that the user receives the desired product. Information that should be included in the procurement documentation is to be in accordance with IPC-D-325. The procurement documentation shall specify the thermal stress test method to be used to meet the requirement of 3.6.1. Selection shall be from those depicted in 3.6.1.1, 3.6.1.2 and 3.6.1.3. If not specified (see 5.1), the default shall be per Table 1-2. During the selection process, the user should take into consideration the following when determining the appropriate thermal stress test method: 1 DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY • • • Wave solder, selective solder, hand solder assembly processes (see 3.6.1.1) Conventional (eutectic) reflow processes (see 3.6.1.2) Lead-free reflow processes (see 3.6.1.3) 1.3.3.1 Selection (Default) The procurement documentation shall specify those requirements that are a result of the selection process within this specification. This includes all references to “AABUS” and Appendix A. If the requirement selection is not made in accordance with 1.3.3.2, the procurement documentation, Ordering Data (see 5.1), Customer Drawing and/or supplier control plan (SCP), then the default requirement in Table 1-2 shall apply. 1.3.3.2 Selection System (Optional) The following product selection identifier system is provided for clarification of the build type. Quality Specification, the generic quality specification. Specification, the base performance specification. Type, the printed board type per 1.3.2. Plating Process, the plating process per 1.3.4.2. Final Finish, the final finish code per 1.3.4.3. Selective Finish, the selective finish code adder per 1.3.4.3, enter ‘‘-’’ when no selective finish is required. Classification, the classification per 1.3.1 or performance specification sheet. Technology Adder, the technology adder as specified in Table 1-1. Add multiple codes as required. Table 1-1 Technology Adders Technology Code HDI VP WBP AMC NAMC HF EP VIP-C VIP-N Technology HDI build-up features per IPC-6016 Via Protection Wire Bondable Pads Active Metal Core Non-active Metal Core External Heat Frame Embedded Passives Via-in-Pad, Conductive Fill Via-in-Pad, Nonconductive Fill Example: IPC-6011/6012/3/1/S/-/3/HDI/EP 1.3.4 Material, Plating Process and Final Finish 1.3.4.1 Laminate Material Laminate material is identified by numbers and/or letters, classes and types as specified by the appropriate specification listed in the procurement documentation. Table 1-2 Default Requirements Category Performance Class Material Final Finish Minimum Starting Foil Default Selection Class 2 Epoxy-Glass Laminate per 3.2.1 Finish X per Table 3-2 1/2 oz. [17.10 µm] for all internal and external layers except Type 1 which shall start with 1 oz. [34.30 µm] Electrodeposited per 3.2.4 Copper Foil Type 2 DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY Hole Diameter Tolerance Plated, components Plated, via only Non-plated Conductor Width tolerance Conductor Spacing tolerance Dielectric Separation Lateral Conductor Spacing Marking Ink Solder Mask Solder Mask, specified Solder Coating Solderability Test Thermal Stress Test Test Voltage, Isolation Resistance Qualification not specified (±) 100 µm [3,937 µin] (+) 80 µm [3,150 µin], (-) no requirement, (may be totally or partially plugged) (±) 80 µm [3,150 µin] Class 2 requirements per 3.5.1 Class 2 requirements per 3.5.2 90 µm [3,543 µin] minimum per 3.6.2.15 100 µm [3,937 µin] minimum per 3.6.2.14 Contrasting color, nonconductive per 3.3.5 Not applied, if not specified per 1.3.4.3 Class T of IPC-SM-840 if class not specified per 3.7 Sn63/Pb37 per 3.2.7.3.1 Category 2 of J-STD-003, tin-lead solder per 3.3.6 IPC-TM-650, Method 2.6.8, Condition A per 3.6.1 Per IPC-9252 See IPC-6011 1.3.4.2 Plating Process The copper plating process, which is used to provide conductivity in the holes, is identified by a single number as follows: 1- Acid copper electroplating only 2- Pyrophosphate copper electroplating only 3- Acid and/or pyrophosphate copper electroplating 4- Additive/electroless copper 5- Electrodeposited Nickel underplate with acid and/or pyrophosphate copper electroplating 1.3.4.3 Final Finish and Coatings The final finish/coating can be one of the finishes/coatings specified below or a combination of several platings and is dependent on assembly processes and end-use. If required, the thickness shall be specified in the procurement documentation. If not specified, the thickness shall be as listed in Table 3-2. Coating thickness may be exempted in Table 3-2 (i.e., tin-lead plate or solder coating). Designators for final finish are as follows: S T X TLU b1 G GS GWB-1 GWB-2 N NB OSP HT OSP ENIG Solder Coating Electrodeposited Tin-Lead, (fused) Either Type S or T Electrodeposited Tin-Lead (unfused) Lead-free Solder Coating Gold Electroplate for Edge Printed Board Connectors Gold Electroplate for Areas to be Soldered Gold Electroplate for areas to be wire bonded (ultrasonic) Gold Electroplate for areas to be wire bonded (thermosonic) Nickel for Edge Printed Board Connectors Nickel as a Barrier to Copper-Tin Diffusion Organic Solderability Preservative High Temperature OSP Electroless Nickel Immersion Gold (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) 3 4.’’ the imperative form of the verb. All dimensions greater than or equal to 1.2.0 mm [0.2.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY ENEPIG DIG NBEG IAg ISn C SMOBC SM SM-LPI SM-DF SM-TM Y Electroless Nickel/Electroless Palladium/Immersion Gold Direct Immersion Gold Nickel Barrier/Electroless Gold Immersion Silver Immersion Tin Bare Copper Solder Mask over Bare Copper Solder Mask over Non-Melting Metal Liquid Photoimageable Solder Mask over Non-Melting Metal Dry Film Solder Mask over Non-Melting Metal Thermal Mask Solder Mask over Non-Melting Metal Other (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (Table 3-2) (3.8) (3. 2 APPLICABLE DOCUMENTS The following specifications of the revision in effect at the time of order form a part of this document to the extent specified herein.8) (3.0394 in] will be expressed in micrometers and microinches.8) (3.1 IPC1 IPC-A-47 Composite Test Pattern Ten Layer Phototool IPC-T-50 Terms and Definitions for Interconnecting and Packaging Electronic Circuits IPC-DD-135 Qualification Testing for Deposited Organic Interlayer Dielectric Materials for Multichip Modules IPC-CF-152 Composite Metallic Material Specification for Printed Wiring Boards IPC-D-325 Documentation Requirements for Printed Boards.8) (3. Agreements can be used to define test methods.0 mm [0. Changes to a figure or table are indicated by gray shading of the figure or table header.2. Deviation from a ‘‘shall’’ requirement may be considered if sufficient data is supplied to justify the exception.5 Interpretation ‘‘Shall. To assist the reader. All dimensions less than 1. frequencies.7. 1. this specification shall take precedence. 1.0394 in] will be expressed in millimeters and inches.8) (3.2. 1.4. and Support Drawings IPC-A-600 Acceptability of Printed Boards IPC-TM-650 Test Methods Manual2 4 .1.11) 1.6 Presentation All dimensions and tolerances in this specification are expressed in hard SI (metric) units and parenthetical soft imperial (inch) units. categories or acceptance criteria within a test. 2. the word ‘‘shall’’ is presented in bold characters. if not already established. Users of this specification are expected to use metric dimensions. If a conflict of requirements exists between this specification and the listed applicable documents. Assemblies.7 Revision Level Changes Changes that were incorporated in the current revision of this specification are indicated throughout by gray shading of the relevant subsection(s).2. Examples include contractual requirements.1 As Agreed Between User and Supplier (AABUS) Indicates additional or alternate requirements to be decided between the user and the supplier in the procurement documentation. conditions.2. modifications to purchase documentation and information on the drawing. 1. The words ‘‘should’’ and ‘‘may’’ are used whenever it is necessary to express non-mandatory provisions. ‘‘Will’’ is used to express a declaration of purpose.4 Terms and Definitions The definition of all terms used herein shall be in accordance with IPC-T-50 and as defined in 1. is used throughout this standard whenever a requirement is intended to express a provision that is mandatory. 2 Microsectioning.36 Rework Simulation.28.4. Printed Wiring Materials 2. Metal Foil 2.18.6. Rigid Printed Wiring 2.6.15 Surface Finish.5 Physical Shock.8 Thermal Stress.3 Moisture and Insulation Resistance. Semi or Automatic Technique Microsection Equipment (Alternate) 2.5.6.4.5.4.1 Adhesion.6.6.2 Coefficient of Thermal Expansion.7 Dielectric Withstand Voltage. Plated-Through Holes 2.9 Vibration. Printed Boards 2.41.38 Surface Organic Contaminant Detection Test 2.27 Thermal Stress.25 Conductive Anodic Filament (CAF) Resistance Test (Electrochemical Migration Test) 2. Printed Boards 2.4.6.5.22 Bow and Twist 2.25 Detection and Measurement of Ionizable Surface Contaminants 2.7.3.3.1 Fungus Resistance.4 Outgassing.4.4.6. Rigid Boards 2.3.2 Thermal Shock.3.6. In-House Plating 2.1. Unsupported Component Hole 2.15 Purity.7 Surface Insulation Resistance 2.39 Surface Organic Contaminant Identification Test (Infrared Analytical Method) 2.1 Tensile Strength and Elongation.6. Components and Materials Qualification and Performance of Electrical Insulating Compound for Printed Board Assemblies Qualification and Performance Specification of Permanent Solder Mask Generic Standard on Printed Board Design Design Guide for the Packaging of High Speed Electronic Circuits 5 .7 Characteristic Impedance and Time Delay of Lines on Printed Boards by TDR 2. Tape Test Method 2.1 Adhesion. Copper Foil or Plating 2. Strain Gage Method 2.3.1. Continuity and Microsection.4.21 Land Bond Strength. Multilayer Printed Wiring 2. Plated-Through Holes for Leaded Components 2. Tape Testing 2.6. Solder Resist (Mask).1 Microsectioning 2.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY 2.1. Convection Reflow Assembly Simulation IPC-QL-653 IPC-CC-830 IPC-SM-840 IPC-2221 IPC-2251 Certification of Facilities that Inspect/Test Printed Boards.4. PWB 2. Capability. Quality and Relative Reliability (PCQR2) Benchmark Test Standard and Database Requirements for Electrical Testing of Unpopulated Printed Boards User Guide for the IPC-TM-650.6. Pb-Free and Other Attributes Current Tin Whiskers Theory and Mitigation Practices Guideline J-STD-609 JP002 2. Modification and Repair of Electronic Assemblies Printed Board Process. Conductive Anodic Filament (CAF) Resistance Test (Electrochemical Migration Test) IPC-4552 IPC-4553 IPC-4554 IPC-4562 IPC-4563 IPC-4781 IPC-4811 IPC-4821 IPC-6011 IPC-6016 IPC-7711/21 IPC-9151 IPC-9252 IPC-9691 2. Method 2. PCBs and PCBAs to Identify Lead (Pb).3 Federal3 6 .2 Joint Industry Standards1 J-STD-001 Requirements for Soldered Electrical and Electronic Assemblies IPC-HDBK-001 Handbook and Guide to Supplement J-STD-001 J-STD-003 J-STD-006 Solderability Tests for Printed Boards Requirements for Electronic Grade Solder Alloys and Fluxed and Non-Fluxed Solid Solders for Electronic Soldering Applications Marking and Labeling of Components.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY IPC-4101 IPC-4103 IPC-4202 IPC-4203 Specification for Base Materials for Rigid and Multilayer Printed Boards Specification for Base Materials for High Speed/High Frequency Applications Flexible Base Dielectrics for use in Flexible Printed Circuitry Adhesive Coated Dielectric Films for Use as Cover Sheets for Flexible Printed Circuitry and Flexible Adhesive Bonding Films Specification for Electroless Nickel/Immersion Gold (ENIG) Plating for Printed Circuit Boards Specification for Immersion Silver Plating for Printed Circuit Boards Specification for Immersion Tin Plating for Printed Circuit Boards Metal Foil for Printed Wiring Applications Resin Coated Copper Foil for Printed Boards Guideline Qualification and Performance Specification of Permanent. Semi-Permanent and Temporary Legend and/or Marking Inks Specification for Embedded Passive Device Resistor Materials for Rigid and Multilayer Printed Boards Specification for Embedded Passive Device Capacitor Materials for Rigid and Multilayer Printed Boards Generic Performance Specification for Printed Boards Qualification and Performance Specification for High Density Interconnect (HDI) Layers or Boards Rework.25. 1 American Society for Testing and Materials4 ASTM B-152 Standard Specification for Copper Sheet.ipc. unclad laminates and bonding material (prepreg) shall be selected from IPC-4101. Plate. resistive and insulating characteristics as applicable. IPC-4202.4 Other Publications 2.ul.com 6.4. Strip.1 Surface Texture (Surface Roughness. The specification sheet number.nema. www. it is necessary to specify those requirements in material procurement documents.2 Underwriters Lab5 UL 94 Tests for Flammability of Plastic Materials for Parts in Devices and Appliances 2.4.3 National Electrical Manufacturers Association6 NEMA LI-1 Industrial Laminated Thermosetting Product Standard 2. metal cladding type and metal clad thickness (weight) shall be as specified in the procurement documentation.2.org 2.sae. www. www.org/html/testmethods. IPC-4203 or as specified in the procurement documentation. When specific requirements such as the flammability requirements shown in UL 94 for laminate and bonding materials are required.4.asq. www. IPC Test Methods are available on the IPC Web site (www.htm) 3.ipc.4. IPC-4203.org 5.org 4. 3.astm.1 Laminates and Bonding Material Metal clad laminates.6 American Society of Mechanical Engineers8 ASME B46. Waviness and Lay) 1. Descriptions and purposes of test coupons are documented in IPC-2221.org 7. Carbon 2. 3. The procurement documentation should specify dielectric. and Rolled Bar ASTM B-488 Standard Specification for Electrodeposited Coatings of Gold for Engineering Uses ASTM B-579 Standard Specification for Electrodeposited Coating of Tin-Lead Alloy (Solder Plate) ASTM-B-679 Standard Specification for Electrodeposited Coatings of Palladium for Engineering Use 2. 7 . www. conductive.4.5 AMS3 SAE-AMS-QQ-A-250 General Specification for Aluminum and Aluminum Alloy. or NEMA LI-1.org 8.1 General Printed boards furnished under this specification shall meet or exceed the requirements of IPC-6011 and the specific performance class as required by the procurement documentation.4 American Society for Quality7 H1331 Zero Acceptance Number Sampling Plans 2. www. www.4.2 External Bonding Materials The material used to adhere external heat sinks or stiffeners or used as an insulator layer to the printed board shall be selected from IPC-4101.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY QQ-S-635 Military Standard Steel Plate. Embedded device materials shall be selected from IPC-4811 or IPC-4821. Plate and Sheet 2.2. Polytetrafluoroethylene (PTFE) material types shall be selected from IPC-4103.org 3 REQUIREMENTS 3.asme.2 Materials 3. 000 PSI] and the elongation shall be no less than 12%. electrodeposited copper platings shall meet the following criteria. Foil type.4 Metal Foils Copper foil shall be in accordance with IPC-4562.6 Base Metallic Plating Depositions and Conductive Coatings The thickness of the plating/final finish coatings shall be in accordance with Table 3-2. using 50 .937 µin] thick samples.2.100 µm [1. 3.1 Resistive Metal Foil Resistive metal foil shall be as specified on the master drawing.7.50%. Deviations shall be AABUS.4. or metallic or non-metallic conductive coatings. Conductor surfaces may have exposed copper in areas not to be soldered within the limits of 3.1.2.6.2. Table 3-4 and Table 3-5.6.2. 3. Method 2. Coverage of platings and metallic coatings does not apply to vertical conductor edges.3 Other Dielectric Materials Photoimageable dielectrics should be selected from IPC-DD-135 and specified in the procurement documentation. 3.4.3. blind and buried vias shall be as specified in Table 3-3. The plating thickness for final finishes or combinations there-of selected from those listed in 1.5 Metal Planes/Cores Internal or external metal planes and/or metal core substrates shall be specified on the master drawing as shown in Table 3-1. via holes.3 Fully Additive Electroless Copper Depositions Additive/electroless copper platings applied as the main conductor metal shall meet the requirements of this specification.2 Electrodeposited Tin-Lead Tin-lead plating shall meet the composition (50-70% tin) requirements of ASTM B-579. vacuum deposited metal.7. or prevent. It is recommended that the user refer to JEDEC/IPC JP002 for guidance on potential mitigation practices that may delay the onset of. Frequency of testing shall be determined by the manufacturer to ensure process control. The copper plating thickness for the surface.2. Other dielectric materials may be specified in the procurement documentation.15.4.969 . foil thickness.2. Resin coated copper foil shall be in accordance with IPC-4563.2 Electrodeposited Copper When copper plating is specified. Fused tin-lead plating or solder coating only requires visual coverage and acceptable solderability testing per J-STD-003.5.2. 8 .6.2.2. b) When tested as specified in IPC-TM-650.2.3. a) When tested as specified in IPC-TM-650. Table 3-1 Metal Planes/Cores Specification SAE-AMS-QQ-A-250 QQ-S-635 ASTM-B-152 or IPC-4562 IPC-CF-152 IPC-CF-152 As Specified Material Aluminum Steel Copper Alloy As Specified As Specified As Specified As Specified As Specified As Specified Copper-Invar-Copper Copper-Moly-Copper Other 3. 3. the purity of copper shall be no less than 99.7 Final Finish Depositions and Coatings . PTHs. bond enhancement treatment and foil profile should be specified on the master drawing if critical to the function of the printed board.1 Electrodeposited Tin The allowance of and the requirements for use of electrodeposited tin shall be AABUS.2.1 Electroless Copper Depositions and Conductive Coatings Electroless depositions and conductive coatings shall be sufficient for subsequent plating processes and may be either electroless metal. 3. Method 2. the tensile strength shall be no less than 248 MPa [36. 3.7.Metallic and Non-Metallic 3.18.3 shall be as specified in Table 3-2. 3. tin whisker formation. foil grade. 3. Fusing is required unless the unfused option is selected wherein the thickness specified in Table 3-2 (Code T) applies.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY 3.4.3. The thickness for specific use platings shall be as specified in Table 3-2. lead-bearing coatings shall be in accordance with the requirements of 3.2. 3.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY 3. The thickness shall be as specified in Table 3-2 (Code G. shall be specified in the procurement documentation.1 Eutectic Tin-Lead Solder Coating The solder used for conventional. Electroless palladium (alloyed or non-alloyed) shall be in accordance with ASTM-B-679. 3.4 Electrodeposited Nickel Nickel plating thickness shall be as specified in Table 3-2 (Code NB).3. Deposit thickness range shall be in accordance with IPC-4554 and as specified in Table 3-2 (code ISn).3. 3. Pad size for thickness measurements shall be in accordance with IPC-4553 and as specified in Table 3-2 (code IAg).11 Other Metals and Coatings The allowance of and the requirements for use of other depositions as a 9 . GWB-1 and GWB-2). palladium is more resistant to immersion gold. GS.2.2.3. acceptance of the solderability coupon may not represent the part. Measurement methodology shall be by XRF Spectrometry in accordance with Appendix 4 of IPC-4552. Caution: Immersion gold thicknesses above 0.2.3 Deviations to these requirements shall be AABUS.7. When used as an undercoat or barrier layer for gold or other metals.6 Electroless Nickel Immersion Gold (ENIG) ENIG plating deposit shall be in accordance with IPC-4552. Specific solderability shelf-life and soldering cycle requirements.925 µin] can indicate an increased risk of having compromised the integrity of the nickel undercoat due to excessive corrosion. pre-assembly baking and sequential soldering processes impact solderability. 3. Allowable thickness cited in Table 3-2 could skew to the lower or higher part of the range for optimum connector or solderable surface metallurgy.3 Hot Air Solder Leveling (HASL)/Solder Coating The solder coating shall be as specified on the master drawing in accordance with the requirements of J-STD-006. This applies to both standard and high-temperature OSP formulations.7. 3.2. if applicable.5 Electrodeposited Gold Electrodeposited gold plating shall be in accordance with ASTM-B-488.10 Organic Solderability Preservative (OSP) OSPs are anti-tarnish and solderability protectors applied to copper to withstand storage and assembly processes in order to maintain solderability of surfaces. Purity and hardness shall be specified in the procurement documentation. except the thickness shall be in accordance with Table 3-2 (Code S). Unlike nickel.3.2.7. except the thickness shall be in accordance with Table 3-2 (Code b1). 3.2.7 Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) Electroless nickel shall be in accordance with IPC-4552.8 Immersion Silver Immersion silver plating shall be in accordance with IPC-4553.7. Measurement location and extent shall be AABUS.7.2. Measurement methodology shall be by XRF Spectrometry in accordance with Appendix 4 of IPC-4554. 3.7.2.7.2 Lead-Free Solder Coating The solder used for lead-free solder coating shall be in accordance with the requirements of 3.7. the thicknesses shall be as specified in Table 3-2 (Code NB). 3. 3. Frequency of sample thickness measurement for Class 1 and Class 2 shall be in accordance with IPC-4554 and for Class 3 location and extent of sampling shall be AABUS. hence the reduced thickness requirement for gold (coverage only).7.2.7.2. Correlation of thickness measurements across the pattern is strongly encouraged to demonstrate uniformity of the coating thickness. The coating storage.9 Immersion Tin Immersion tin plating deposit shall be in accordance with IPC-4554. Deposit thickness range shall be in accordance with IPC-4552 and as specified in Table 3-2 (Code ENIG).7. 3. Immersion gold shall be in accordance with IPC-4552. Refer to IPC-J-STD-001 and IPC-HDBK-001 for further information on gold removal to prevent the formation of brittle solder joints resulting from high concentrations of gold dissolving into the solder joint. Due to the influence of the design pattern and chemistry process variability.7.7.3. 3.7. Note: Industry investigations have shown that a gold-tin intermetallic phase forms under normal soldering process parameters when the weight percent of gold in the solder joint reaches the 3-4% range. Frequency of sample thickness measurement for Class 1 and Class 2 shall be in accordance with IPC-4552 and for Class 3 location and extent of sampling shall be AABUS.2.125 µm [4.2. The thicknesses shall be as specified in Table 3-2 (Code ENEPIG) and may be measured by XRF Spectrometry.2. HASL is the process for solder coating that involves dipping a printed board into solder and using hot air to level the resultant solder surface. Hot Air Leveling (HAL) or Hot Air Solder Leveling (HASL) processes are considered to have a degree of difficulty in their control.0 µm [118 µin] 0.Electroplate for edge printed board connectors .DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY final finish per 1. See also 3. Table 3-2 Final Finish and Coating Requirements Code Finish Thickness Coverage & Solderable2 Coverage & Solderable 2 Applicable Acceptability Specification J-STD-003 J-STD-006 J-STD-003 J-STD-006 Marking Code1 S b1 T X TLU Solder Coating over Bare Copper Lead-Free Solder Coating over Bare Copper b0 b1 b3 J-STD-003 Electrodeposited Tin-Lead (fused) 2 Coverage & Solderable J-STD-006 minimum Either Type S or T As indicated by code Electrodeposited Tin-Lead Unfused J-STD-003 8.3 µm [51. coupled with pad sizes and geometries placing additional challenges on such processes.minimum Nickel-Electroplate as a barrier4 minimum Organic Solderability Preservative High Temperature OSP Electroless Nickel .0 µin] Coverage and Solderable7 Solderable 5 6 ENEPIG Solderable Solderable7 AABUS Note 1.2 µin] Solderable Solderable 7 7 b3 G None b4 None None None b4 b4 b4 GS GWB-1 Electrolytic nickel under gold for areas to be wire bonded (ultrasonic) minimum Gold Electroplate for areas to be wire bonded (thermosonic) .97 µin] 3.4 µin] 1.0 µm [118 µin] Class 1 and Class 2 0.5 µin] 3.minimum GWB-2 Electrolytic nickel under gold for areas to be wire bonded (thermosonic) minimum Nickel .97 µin]5 3.0 µm [118 µin] Class 1 2.3.0 µm [78.7 µin] Class 2 and Class 3 2.0 µm [118 µin] 0.05 µm [1.3 µm [11. palladium and rhodium shall be AABUS.3 such as bare copper. places the creation of a practical minimum thickness outside the scope of this specification.25 µm [49.6.8 µm [31.05 µm [2.8 µm [31.4.45 µm [17.05 µm [1.minimum Immersion Gold – minimum DIG IAg ISn C Direct Immersion Gold (Solderable Surface) Immersion Silver Immersion Tin Bare Copper None b4 None b4 N/A None N NB OSP HT OSP None None None IPC-4552 IPC-4552 ASTM-B-679 None None IPC-4553 IPC-4554 AABUS N/A b6 b6 b4 b4 b4 N/A b4 b4 b2 b3 N/A 3.minimum ENIG Immersion Gold . Note 2. These marking and labeleing codes represent the codes for surface finish categories established in IPC/JEDEC-J-STD-609.minimum Electroless Nickel .0 µm [315 µin] minimum J-STD-006 Gold for edge printed board connectors and areas not to be soldered minimum Gold Electroplate on areas to be soldered –maximum3 Gold Electroplate for areas to be wire bonded (ultrasonic) – minimum Class 1 and Class 2 0. This.72 µin] 0.8 µin] Class 3 0.5 µm [98.21 µin] 0.minimum Electroless Palladium .3. 10 .5 µin] Class 3 1. 8 Polymer Coating (Solder Mask) When permanent solder mask coating is specified as a final finish per 1.1. See IPC-4553 for detailed measurement requirements.2.4.11 Hole Fill Insulation Material Electrical insulation material used for hole-fill for metal core printed boards shall be AABUS. and Buried Vias > 2 Layers1 Copper – average2. photo imaging or conductive ink formation followed by a plating operation.6. Table 3-3 Surface and Hole Copper Plating Minimum Requirements for Through-Holes. Stacked microvias may also require different inspection criteria. Note 3. Blind.2) thickness shall be continuous and wrap from hole walls onto outer surfaces. If a conductive marking ink is used.3.3. there is little known about this structure and the reliability results are not consistent with buried and blind microvias.2. Note 2. require a unique pad size for both thin and/or thick silver deposits. Wrap copper plating for filled microvias shall be in accordance with 3.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY Note 3. The fusing fluid shall act as a heat transfer and distribution medium to prevent damage to the bare laminate of the printed board.4 12 µm [472 µin] 10 µm [394 µin] AABUS 12 µm [472 µin] 10 µm [394 µin] 5 µm [197 µin] 12 µm [472 µin] 10 µm [394 µin] 6 µm [236 µin] Note 1.15 mm [0. Copper plating (1.6. Note 7. Refer to IPC-A-600 for discussion on copper plating thickness for hole walls. Note 4.3 Thin areas3 Wrap2 13 µm [512 µin] 11 µm [433 µin] AABUS 15 µm [592 µin] 13 µm [512 µin] 5 µm [197 µin] 15 µm [592 µin] 13 µm [512 µin] 7 µm [276 µin] Note 1. Microvias are vias that are < 0. See 3.3.3. Note 3. Table 3-5 Surface and Hole Copper Plating Minimum Requirements for Buried via cores (2 layers) Copper – average1. Wrap copper plating for filled PTHs and vias shall be in accordance with 3.1.1. See 3.15 mm [0.12 Heatsink Planes.2.6.2.4. Note 4. As of the publication of this specification. Refer to IPC-A-600 for discussion on copper plating thickness for hole walls.6. Note 2. photo imaging or conductive ink formation followed by a plating operation.4 Thin areas4 Wrap3 Class 1 20 µm [787 µin] 18 µm [709 µin] AABUS Class 2 20 µm [787 µin] 18 µm [709 µin] 5 µm [197 µin] Class 3 25 µm [984 µin] 20 µm [787 µin] 12 µm [472 µin] Note 1. Does not apply to microvias.11. 11 .2) thickness shall be continuous and extend or wrap from hole walls onto outer surfaces.006 in] in diameter and formed either through laser or mechanical drilling. 3. Marking inks shall be applied to the printed board.10 Marking Inks Marking inks shall be permanent and shall conform to IPC-4781 or be as specified in the procurement documentation. Wrap copper plating for filled buried via cores shall be in accordance with 3. See 3.6.2.1. 3.2. Nickel plating used under the tin-lead or solder coating for high temperature operating environments act as a barrier to prevent the formation of copper-tin compounds. See also 3. 3. Microvias are vias that are < 0. 3.7.2.5. See 3. Note 3.4.2.6. See notation in 3.7. Blind vias have greater than 1:1 aspect ratio. when required for immersion silver thickness. Bonding material shall be as specified in 3.2.2.11. the marking shall be treated as a conductive element on the printed board. Refer to IPC-A-600 for discussion on copper plating thickness for hole walls. or to a label applied to the printed board. Table 3-4 Surface and Hole Copper Plating Minimum Requirements for Microvias (Blind and Buried)1 Copper – average Thin areas Wrap3 4 2.4.11.2. Note 6.006 in] in diameter and formed either through laser or mechanical drilling.6.2) thickness shall be continuous and extend or wrap from hole walls onto outer surfaces.3. Copper plating (1. Note 2.2. External Thickness and materials for construction of heatsink planes shall be as specified in Table 3-1 and/or the procurement documentation.6. it shall be a polymer coating conforming to the requirements of 3. The values given for blind and buried microvias are not applicable for stacked microvias. 3.11.2.7. Note: Fusing fluid compatibility should be confirmed with end users’ cleanliness requirements due to the diverse interactions experienced at assembly soldering. wet/dry etching.11. Note 5.1.11.2.2. wet/dry etching.3. Surface measurements.1. Copper plating (1.9 Fusing Fluids and Fluxes The composition of the fusing fluids and fluxes used in solder coating applications shall be capable of cleaning and fusing the tin-lead plating and bare copper to allow for a smooth adherent coating. Note 4. Although process indicators should be monitored as part of the process control system. workmanship or process that is not a defect. the distance of crazing shall not span more than 50% of the distance between adjacent conductors. These include laminate materials.2. Refer to IPC-A-600 for more information.0984 in].1 Edges Nicks or crazing along the edge of the printed board. Nonmetallic burrs are acceptable as long as they are not loose and/or do not affect fit and function. edge of cutouts and edges of non-plated holes are acceptable provided the penetration does not exceed 50% of the distance from the edge to the nearest conductor or 2.2 Crazing Crazing is acceptable for all classes of end product provided the imperfection does not reduce the conductor spacing below the minimum and there is no propagation of the imperfection as a result of thermal testing that replicates future assembly processes.5 mm [0.1 Measling Measling is acceptable for Class 1. There shall be no propagation of imperfections as a result of thermal testing that replicates future assembly processes.3. They shall be of uniform quality and shall conform to 3. Other particles trapped within the printed board shall be acceptable. it should be verified at progressively higher magnifications (up to 40X) to confirm that it is a defect. Embedded passive materials shall be in accordance with IPC-4811 or IPC-4821.2. provide additional information for determining laminate performance regarding CAF growth. 3. provided the particle does not reduce the spacing between adjacent conductors to below the minimum spacing specified in 3. 3. 3. If confirmation of a suspected defect cannot be made at 3 diopters.13 Via Protection Materials used for a via protection method shall be AABUS. Panels.3.3. and which may be used with conventional core materials for the manufacture of printed boards.1.14 Embedded Passive Materials Embedded passive materials are defined as materials and processes which add capacitive.75X). Class 2 and Class 3 end product. 3. plated resistors. Dimensional requirements such as spacing or conductor width measurements may require other magnifications and devices with reticules or scales in the instrument. Edges shall be clean cut and without metallic burrs.2. For Class 2 and Class 3. etc.3. disposition of individual process indicators is not required and affected product should be used as is. Measled areas in laminate substrates exceeding 50% of the spacing between non-common conductors are a process indicator for Class 3 end product. Users who wish to incorporate additional criteria for measling conditions may consider incorporating Class 3/A requirements which does not allow measles.3 Visual Examination Finished printed boards shall be examined in accordance with the following procedure.25.1 through 3. or 100 µm [3. equipment operation. Delamination is an internal condition which may propagate under thermal stress and may be a catalyst for CAF growth. For Class 2 and Class 3.2. 3.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY Deviations to this requirement shall be AABUS.3.2 Laminate Imperfections Laminate imperfections include those characteristics that are both internal and external within the printed board but are visible from the surface.2.937 µin] if not specified. indicating a variation in material. 3.5. Visual examination for applicable attributes shall be conducted at 3 diopters (approx.4 Foreign Inclusions Translucent particles trapped within the printed board shall be acceptable. Refer to IPC-A-600 for more information.2. the blister or delamination shall not span more than 25% of the distance between adjacent conductive patterns. The distance between the haloing penetration and the nearest conductive feature shall not be less than the minimum lateral conductor spacing. 12 . resistive and/or inductive functionality within the printed board. The IPC-9691 user’s guide for CAF resistance testing and IPC-TM-650. protectant materials. 3.3. which allow accurate measurements of the specified dimensions. conductive pastes.6. Note: Measling is an internal condition which does not propagate under thermal stress and has not been conclusively shown to be a catalyst for Conductive Anodic Filament (CAF) growth.9. 3. 3. Method 2. resistive metal foils.2.3.3. Contract or specification may require other magnifications. whichever is less.3 Delamination/Blistering Delamination and blistering is acceptable for all classes of end product provided the area affected by imperfections does not exceed 1% of the printed board area on each side and does not reduce the spacing between conductive patterns below the minimum conductor spacing. which are scored or routed with a breakaway tab. shall meet the depanelization requirements of the assembled printed board. Circumferential voids shall not extend beyond 90° for Class 1.2.2.7 Scratches. 3.10) shall be considered as electrical elements of the circuit and shall not reduce the electrical spacing requirements. 3. each qualification printed board. The Category of durability shall be specified on the master drawing.5 Weave Exposure There shall be no weave exposure on the printed board for Class 3. as in the case where press-fit components are used. however. Dents. 3. 3. Class 2 or Class 3. or by use of a permanent fungistatic ink or paint (see 3. Conductive markings.2.2. Note 1.9 Color Variations in Bond Enhancement Treatment Mottled appearance or color variation in bond enhancement treatment is acceptable. When required by the procurement documentation. dents. For Class 1 product. 3. Random missing areas of treatment shall not exceed 10% of the total conductor surface area of the affected layer.3.8 Surface Voids Surface voids are acceptable provided they do not exceed 0.3. Refer to IPC-A-600 for legibility requirements. copper voids shall not exceed 5% of the hole length.3. Printed boards that do not require soldering do not require solderability testing and this shall be specified on the master drawing. etc. the labeling requirements of J-STD-609 shall be met.5 Marking Each individual printed board. Category 2 shall be used.3. In addition to this marking. The marking shall be produced by the same process as used in producing the conductive pattern. there shall be no lifted lands on the delivered (nonstressed) printed board.3.). more than 5% of the holes. bridge conductors. more than 5% of the holes. or exceed 5% of the total printed board area per side. Refer to IPC-A-600 for more information.3 Plating and Coating Voids in the Hole Plating and coating voids shall not exceed that allowed by Table 3-6.2. For Class 2 product.6 Solderability Only those printed boards that require soldering in a subsequent assembly operation require solderability testing.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY 3.2. legible for all tests. 13 . Weave exposure is acceptable for Class 2 and Class 1 provided the imperfection does not reduce the remaining conductor spacing (excluding the area(s) with weave exposure) below the minimum.4 Lifted Lands When visually examined in accordance with 3. For lead-free end product. Printed boards to be used only for surface mount do not require PTH solderability testing. For Class 1. Note 2. the use of bar code marking is permissible. if not specified.3. For Class 2 and Class 3 product. Test coupons or production printed boards to be tested shall be conditioned. 3.10). and in no case affect printed board performance.3. finished coating voids shall not exceed 5% of the hole length. Marking shall not cover areas of lands that are to be soldered.3.3.3. and evaluated for surface and PTH solderability using J-STD-003.6 Exposed/Disrupted Fibers Exposed/disrupted fibers are acceptable for all Classes provided the imperfection does not bridge conductors and does not reduce the remaining conductor spacing below the minimum. and Tool Marks Scratches. LASER marker or by vibrating pencil marking on a metallic area provided for marking purposes or a permanently attached label. if required. copper voids shall not exceed 10% of the hole length. Circumferential voids shall not extend beyond 90° of the circumference.2. either etched copper or conductive ink (see 3.10 Pink Ring No evidence exists that pink ring affects functionality. Five voids allowed per hole in not Three voids allowed per hole in not One void allowed per hole in not more than 15% of the holes.8 mm [0. date code shall be formatted per the suppliers discretion in order to establish traceability as to when the manufacturing operations were performed.3. and quality conformance test circuitry (as opposed to each individual test coupon) shall be marked in order to ensure traceability between the printed boards/quality conformance test circuitry and the manufacturing history and to identify the supplier (logo. finished coating voids shall not exceed 10% of the hole length. Table 3-6 Plating and Coating Voids in the Hole Material Copper1 Finish Coating2 Class 1 Class 2 Class 3 Three voids allowed per hole in not One void allowed per hole in not None more than 10% of the holes. The presence of pink ring may be considered an indicator of process or design variation but is not a cause for rejection. The focus of concern should be the quality of the lamination bond. When used. 3. and tool marks are acceptable provided they do not bridge conductors or expose/disrupt fibers greater than allowed in the paragraphs above and do not reduce the dielectric spacing below the minimum specified. more than 5% of the holes.2. 3.031 in] in the longest dimension. 3. accelerated conditioning for coating durability shall be in accordance with J-STD-003. All markings shall be compatible with materials and parts. hole pattern accuracy and feature location accuracy shall be as specified in the procurement documentation. tin/ lead or solder smear transfer to the dielectric surface. the feature tolerances of the applicable design series specification shall apply. or of the conductor from the base laminate in excess of that allowed.4. which are seen when a metallic or non-metallic semi-conductive coating is used. Exposed Copper Gap 2. notches.04921 in] 0. fingerprints. foreign matter. in the event that dimensional tolerances are not specified in the procurement documentation. scoring and edge printed board contacts to connector key area shall be as specified in the procurement documentation. Gold Overlap 2. ability to assemble and serviceability.8 mm [0. As both increase.4. If overhanging metal (slivers) breaks off and adheres to the tape.3. the amount of time to properly wet the sides of the PTH and the tops of the lands increases proportionately. Only specific dimensioned holes. 3.4).1 Hole Size.25 mm [0.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY When solderability testing is required. Method 2. The exposed copper/plating or gold overlap may exhibit a discolored or gray-black area which is acceptable (see 3. it is evidence of overhang or slivers.3.3. Unless required by the master drawing.5. as shown by particles of the plating or pattern foil adhering to the tape. There shall be no loose plating slivers on the surface of the printed board. 3.0984 in] 1. There shall be no evidence of any lifting or separation of platings from the surface of the conductive pattern.9 Workmanship Printed boards shall be processed in such a manner as to be uniform in quality and show no visual evidence of dirt.5 mm [0.8 mm [0. Junction of Gold Plate to Solder Finish Exposed copper/plating overlap between the solder finish and gold plate shall meet the requirements of Table 3-7. Supplier in-process certification of features of accuracy to reduce inspection is allowed provided the method is documented and demonstrates capability to meet the specified requirements.8 Edge Printed Board Contact. printed board periphery. 3. 3.4.5 mm [0. There shall be no evidence of any portion of the protective plating or the conductor pattern foil being removed. using a strip of pressure sensitive tape applied to the surface and removed by manual force applied perpendicular to the circuit pattern.0984 in] 1. The printed board shall meet the dimensional requirements specified in the procurement documentation. thickness. Hole Pattern Accuracy and Pattern Feature Accuracy The hole size tolerance. cutouts. Printed boards shall be free of defects in excess of those allowed in this specification.4. consideration should be given to printed board thickness and copper thickness. However. Finished hole size tolerance shall be verified on a sample basis across all hole sizes applicable to the design. to include both non-plated and plated-through. are not foreign material and do not affect life or function. shall be inspected for hole pattern accuracy to meet printed board dimensional requirements of 3.031 in] 3.7 Plating Adhesion Plating adhesion shall be tested in accordance with IPC-TM-650. but not limited to. Printed board dimensional locations of basic or bilateral tolerance as defined in the procurement documentation shall be inspected in accordance with the applicable AQL classification as specified in Table 4-3. but not of plating adhesion failure.4 Printed Board Dimensional Requirements Inspection of dimensional requirements shall be as defined herein unless otherwise AABUS. oil. slots. flux residue and other contaminants that affect life.25 mm [0. Visually dark appearances in nonplated holes. All dimensional characteristics such as.04921 in] 0. In the event that the supplier does not have a process certification system for dimensional accuracy the AQL levels of Table 4-3 shall apply for each production lot. The supplier may provide a statement of certification of accuracy based on the suppliers sampling plan which includes a process data collection and recording system.1. Table 3-7 Edge Printed Board Contact Gap Class 1 Class 2 Class 3 Max. holes.031 in] Max. 14 . Automated Optical Inspection (AOI) technology is allowed. The number of measures per hole size shall be determined by the manufacturer to adequately sample the quantity of holes within the population. External Unsupported holes The minimum external annular ring may have a 20% reduction of the minimum The land/conductor junction The land/conductor junction shall annular ring in isolated areas due to shall not be reduced below the not be reduced below the allowable defects such as pits.1. Note 2.2.969 µin]. Employment of filleting or ‘‘tear drops’’ in Class 3 product shall be AABUS. assessed. or splay in the annular ring of 3. nicks. nicks. See 3. never be less than 50 µm [1.1 3. junction is not reduced below the the allowable width reduction in allowable width reduction in 3.3.1.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY hole pattern accuracy for other nonspecifically dimensioned holes.4.2 (see Figure 3-2 and Figure 3-3). the applicable design series shall apply.3.1.3.5. The printed board with the related breakout shall meet the electrical requirements of 3. If breakout occurs at the conductor/land intersection it shall be acceptable if in accordance with Figure 3-3. isolated areas.5. Unless prohibited by the customer. Minimum lateral spacing shall be maintained. However.9 regarding internal annular ring requirements for functional and nonfunctional lands.4. the employment of filleting or ‘‘tear drops’’ to create additional land area at the conductor junction shall be acceptable for Class 1 and Class 2 and in accordance with general requirements for lands with holes detailed in IPC-2221.3. Pattern feature accuracy may be certified through a statement of qualification or by AQL sampling per 3. allowable width reduction in The conductor junction should pinholes.3. Hole breakout is allowed 90° hole breakout is allowed provided the land/conductor 3 provided the land/conductor The minimum internal annular ring junction is not reduced below shall be 25 µm [984 µin]. pinholes or splay in the annular ring of 3.2 Characteristic Class 1 Class 2 Not greater than 90° breakout of hole from land when visually assessed. Note 1.906 µin]. The minimum external annular ring may not be reduced below the allowable have 20% reduction of the minimum The land/conductor junction width reduction in 3.4. need not be checked as they are database supplied locations and are controlled by annular ring requirements to surface or internal lands. allowable width reduction in width reduction in 3. Nodules or rough plating in PTHs shall not reduce the hole diameter below the minimum limits defined in the procurement document.3. The measurement of the annular ring on external layers is from the inside surface (within the hole) of the PTH. of hole from land when visually The land/conductor junction shall assessed. hole pattern accuracy may be certified by a statement of qualification or by AQL sampling per 3.5. µin] or the minimum line width. 15 .1. dents. See Figure 3-2 and Figure 3-3 for visual examples of land breakout and conductor width reduction at land. annular ring in isolated areas due to shall not be reduced below the defects such as pits. Note 3. Pattern feature accuracy shall be as specified in the procurement documentation. such as PTHs and vias.6. to the outer edge of the annular ring on the surface of the printed board as shown in Figure 3-1. dents. AOI is allowed.8. whichever is smaller. 3.969 isolated areas.5. If required by master drawing. in the event that any of these characteristics are not specified in the procurement documentation.2 Annular Ring and Breakout (External) The minimum external annular ring shall meet the requirements of Table 3-8.5. The minimum annular ring shall be 150 µm [5.1 Not greater than 90° breakout of Not greater than 90° breakout of hole from land when visually hole from land when visually assessed. or unsupported hole.5. Class 3 External PTHs Internal PTHs The minimum annular ring shall be 50 Not greater than 180° breakout µm [1. Table 3-8 Minimum Annular Ring1. 3.3.5% for all other printed boards.4. End products shall be assessed in the delivered form.4. or any combination thereof.3 Bow and Twist Unless otherwise specified in the procurement documentation.5. Internal conductors are examined during internal layer processing prior to multilayer lamination.2. The physical geometry of a conductor is defined by its width x thickness x length.6.5. and 30% of the minimum value for Class 1.0 mm [0.13. When not specified on the master drawing. the allowed reduction in the nominal conductor spacings shown in the engineering documentation due to processing shall be 20% for Class 3 and 30% for Class 1 and Class 2 (minimum product spacing requirements as previously stated apply). whichever is less.3 Conductor Imperfections The conductive pattern shall contain no cracks. Verification of dimensional attributes shall be performed in accordance with 3. lands and planes shall meet the visual and dimensional requirements of the following sections.5.5. 3. 3.2 Conductor Spacing The conductor spacing shall be within the tolerance specified on the master drawing.3 and IPC-A-600. Method 2. If minimum spacing is not specified.6. 3. Minimum spacing between the conductor and the edge of the printed board shall be as specified on the master drawing.2.1 Conductor Width and Thickness When not specified on the master drawing the minimum conductor width shall be 80% of the conductor pattern supplied in the procurement documentation.12 and 3.0 mm [0.4 of IPC-2221. the minimum conductor thickness shall be in accordance with 3.5 Conductor Definition All conductive areas on printed boards including conductors.75% for printed boards that use surface mount components and 1. twist.3.5. the printed board shall have a maximum bow and twist of 0. when designed in accordance with 5.2. shall be determined by physical measurement and percentage calculation in accordance with IPC-TM-650.1 and 3. AOI inspection methods are allowed. Bow. Any combination of defects specified in 3.512 in] for Class 2 or 3.5. 3. splits or tears.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY Figure 3-1 Annular Ring Measurement (External) Figure 3-2 Breakout of 90° and 180° Figure 3-3 Conductor Width Reduction 3.22. The total combination of defect area lengths on a conductor shall not be greater than 10% of the conductor length or 25.984 in] for Class 1 or 13. 3.1 Conductor Width Reduction Allowable reduction of the minimum conductor width (specified or derived) 16 . The conductor pattern shall be as specified in the procurement documentation.2 shall not reduce the equivalent cross sectional area (width x thickness) of the conductor by more than 20% of the minimum value (minimum thickness x minimum width) for Class 2 and Class 3. There shall be no defects within the pristine area which is defined by the central 80% of the land diameter.e.e.2.5.0394 in] in their longest dimension and there are no more than four per side per 625 cm2 [96. dents. 3.1 Nicks and Pinholes in Ground or Voltage Planes Nicks and pinholes are acceptable in ground or voltage planes for Class 2 and Class 3 provided they do not exceed 1.2. pinholes.5.1 Rectangular Surface Mount Lands Defects such as nicks. Class 2 and Class 3. Class 2 and Class 3 are considered cosmetic in nature and are acceptable provided the requirements for final finish are met. which is defined by the central 80% of the land width by 80% of the land length as shown in Figure 3-4. per 625 cm2 [96. and 30% of the minimum conductor width for Class 1.2 Round Surface Mount Lands (BGA Pads) Defects such as nick. or 20% for Class 1.4 Conductive Surfaces 3. edge roughness. 3.1 and 3. Figure 3-4 Rectangular Surface Mount Lands 3.5. Electrical test probe ‘‘witness’’ marks within the pristine area for Class 1. 3.2. depressions and scratches) shall not exceed 20% of the minimum conductor thickness for Class 2 and Class 3.4.2.4. For Class 1.88 in2]. the longest dimension shall be 1. Note: The allowable reductions assume that the manufacturer at front end tooling (CAM) understands their etch allowance and adds a producibility compensation to the original artwork design. edge roughness. pinholes and scratches) which exposes base material shall not exceed 20% of the minimum conductor width for Class 2 and Class 3.5.5. dents and pin holes along the edge of the land shall not radially extend towards the center of the land by more than 10% of the diameter of the land for Class 1. nicks. 3.3.2. One electrical test probe ‘‘witness’’ mark is allowed within the pristine area for Class 1. Class 2 or Class 3 printed boards and shall not extend more than 20% around the circumference of the land for Class 2 or Class 3 printed boards or 30% for Class 1 as shown in Figure 3-5. and pin holes along the external edge of the land shall not exceed 20% of either the length or width of the land for Class 2 or Class 3 printed boards.2 Conductor Thickness Reduction Allowable reduction of the minimum conductor thickness due to isolated defects (i. Defects internal to the land shall not exceed 10% of the length or width of the land for Class 2 or Class 3 printed boards.5.. and 30% of the minimum conductor thickness for Class 1. nicks. or 30% for Class 1. and shall not encroach the pristine area.4.5.4.4.. and shall remain outside of the pristine area of the surface mount land.2 Solderable Surface Mount Lands Defects along the edge of the land or internal to the land shall not exceed the requirements in 3.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY due to misregistration or isolated defects (i.0 mm [0.0591 in] with no more than six per side.5 mm [0.4. 17 .88 in2].5. 4 Printed Board Edge Connector Lands On gold or other noble metal plated edge printed board connector lands.6 Structural Integrity Printed boards shall meet structural integrity requirements for thermally stressed (see 18 . 3. solder splashes or tin-lead plating.15.15 mm [0. Class 3−5%.15 mm [0.3 for ultrasonic (GWB-1) and thermosonic (GWB-2) wire bonding of gold electroplate or electroless nickel/immersion gold (ENIG). Class 2−5%.00591 in].4. areas of solder connection. There shall be no pits.4.5.6 Nonwetting For tin.8 µm [32 µin] RMS roughness requirement.4.5. or as specified in the procurement documentation. For more information on surface roughness. nodules. Pits. The maximum surface roughness in the pristine area of the wire bond pad shall be measured in accordance with an applicable test method or AABUS and shall be 0.4. it is recommended that the roughness-width cutoff identified in that method be adjusted to approximately 80% of the maximum length of the wire bond pad in order to obtain the RMS value within the pristine area.4. 3. 3.5.1 Exposed Copper (Areas not to be soldered) Exposed copper on areas not to be soldered is permitted on 1% of the conductor surfaces for Class 3 and 5% of the surfaces for Class 1 and Class 2. Individual areas of solder connection – Class 1−15%.5. and nodules or metal bumps that protrude above the surface.15 mm [0. The pristine area shall consist of the central 80% of the pad width by 80% of the pad length of the wire bond pad as shown in Figure 3-4.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY Figure 3-5 Round Surface Mount Lands 3. tin/lead reflowed or solder coated surfaces. the insertion or critical contact area shall be free of cuts or scratches that expose underlying nickel or copper. scratches. 3.4. 3.3.5 Dewetting For tin. 3. or solder coated surfaces. plating voids exposing the resin fill are not allowed. electrical test probe ‘‘witness’’ marks.5.5.7 Final Finish Coverage Final finish shall meet the solderability requirements of J-STD-003.8 µm [32 µin] RMS (Root-Mean-Square). 3.4.00591 in] wide around the perimeter of the land including the critical contact area.7. nonwetting is not permitted on any conductive surface where a solder connection will be required. dents or depressions are acceptable if they do not exceed 0. except as noted below.8 Cap Plating of Filled Holes When cap plating of the filled via is specified on the procurement documentation. 3. The imperfection limits do not apply to a band 0. Coverage does not apply to vertical conductor edges.00591 in] in their longest dimension and there are not more than three per land and do not appear on more than 30% of the lands. unless covered by solder mask. and ground or voltage planes is allowed to the extent listed below: a) b) Conductors and planes—permitted for all classes. dewetting on conductors.7. The final finish coating thickness shall be per Table 3-2 for the applicable coating used.5.4. or other defects in the pristine area that violate the 0.1.2 Tin-Lead under Solder Mask (Areas not to be soldered) Solder mask overlap or encroachment onto tin lead or solder on areas not to be soldered is acceptable provided the overlap does not exceed 0.4. Method 2. tin/lead reflowed.4. refer to ASME B46.3 Wire Bond Pad (WBP) The wire bond pad shall have a final conductor finish as specified in 1. Visually discernable depressions (dimples) and protrusions (bumps) over via fill are acceptable providing they meet the requirements of Table 3-10.5. If using IPC-TM-650. 6. 260° C reflow profile.1. Structural integrity shall be used to evaluate test coupons or production printed boards from Type 2 through Type 6 printed boards by micro-sectioning techniques. the test coupons or printed boards shall meet the requirements of Table 3-9 and paragraph 3.3.8 Test coupons or production printed boards shall be thermally stressed in accordance with IPC-TM-650.6. 3.. The evaluation of all properties and requirements shall be performed on the thermally stressed test coupon or production printed board and all requirements shall be met. 230° C reflow profile. no plating cracks.6.6. the allowance for the usage of printed boards to establish acceptance criteria for the product shall be AABUS. or 2. For Class 2 and Class 3 product.6.27. 3.6.6.2 Requirements for Microsectioned Coupons or Printed Boards When examined in microsection. and shall each have three (3) holes minimum. Blind and buried vias shall meet the requirements of PTHs. Refer to IPC-2221 for appropriate coupon design of blind and buried vias for PTH evaluation. lay-up orientation.2. innerlayer inclusions.6.27 (230 °C)Test coupons or production printed boards shall be thermally stressed in accordance with IPC-TM-650.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY 3.1. For foils less than 3/8 oz. shall meet the above requirements when made from copper. lamination and plating voids. shall be inspected in the x and y axis. shall be accomplished at magnifications specified above. Method 2.0 µm [39.6.1 through 3.2. 3. and so forth. Note: Alternate techniques used to supplement microsection evaluation shall be AABUS. Evaluation of all applicable PTHs and vias. Plating thicknesses below 1. test coupons or printed boards shall be microsectioned.6. and inner foil cracks) are not evaluated. 3.1.1) evaluation test coupons specified in 3. Areas selected from printed boards shall contain holes and copper features so that all criteria within this specification can be evaluated.1 Plating Integrity Plating integrity in the PTHs shall meet the requirements detailed in Table 3-9. The production printed boards and all other test coupons in the quality conformance test circuitry which contain PTHs shall be capable of meeting the requirements of this section.6. Method 2.1. Characteristics not applicable to Type 2 printed boards (i. Examination for laminate thickness. Metal core or thermal planes. Method 2.8.6. foil thickness. for all such structures found on the finished printed board shall be inspected in the vertical cross section in accordance with Table 4-3. 3.2. when used as electrically functional circuitry. Dimensional measurements that are only possible through the use of microsectioning techniques are also defined in this section. one or more of the following Test Methods shall be required. but those made from dissimilar metals may have small spots or pits at their junction with 19 .27. Test condition A. The coupons shall be tested after the printed board is exposed to all coating.6. Method 2.6.6. Microsections selected from productions printed boards shall be removed from opposite panel corners. The grinding and polishing accuracy of the microsection shall be such that the viewing area of each of the PTHs is within 10% of the drilled diameter of the hole.1. including blind and buried.2.e.2 on test coupons or production printed boards. Method 2.4 Deviations to Thermal Stress Testing Deviations to these requirements shall be AABUS. Microsectioning shall be accomplished per IPC-TM-650.2 Thermal Stress Testing.1.17.3. PTHs shall be examined for foil and plating integrity at a magnification of 100X ± 5%. 3. Each side of the hole shall be examined independently. Referee examinations shall be accomplished at a magnification of 200X ± 5%. there shall be no separation of plating layers (except as noted in Table 3-9).1 Thermal Stress Testing Test coupons or production printed boards shall be thermally stressed..1 Thermal Stress Testing.6.6. and internal interconnections shall exhibit no separation or contamination between the PTH wall and internal layers. 3. Method 2.6. plating thickness.1.5 Microsection Requirements Following stress. Method 2.1. 200X magnification and 400-500X referee magnification may be required to confirm minimum thickness requirement. requirements for innerlayer separations. Per the applicable criteria listed in 1. 3. final finish and thermal processing.27 (260 °C)Test coupons or production printed boards shall be thermally stressed in accordance with IPC-TM-650.3 Thermal Stress Testing.1. Although the A and B or A/B coupons are assigned for this test.4 µin] shall not be measured using metallographic techniques. If a void is detected during evaluation of a microsection which meets the above criteria. None allowed. Conductor finish plating or coating material between the base material and copper plating (i. ‘‘A’’ and ‘‘B’’ cracks allowed. ‘‘A’’ cracks allowed.150 µin] maximum Wicking (Copper Plating) Innerlayer inclusions (inclusions at the interface between internal lands and through hole plating) Internal foil cracks1 None allowed. the product which the test coupon or production printed boards represent are considered acceptable. if a plating void is present in the microsections. When negative etchback results in folds in the copper plating.921 µin] maximum Allowed on only one side of hole wall at each land location on 20% of each available land. Allowed on only one side of hole wall at each land location on 20% of each available land. the copper thickness shall meet the minimum requirements as measured from the face of the internal layer as depicted in Figure 3-8.2. ‘‘D’’ cracks not allowed. there shall be no more than one void per test coupon or production printed board.6. The negative etchback limits shall be in accordance with Figure 3-12.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY the hole wall plating. Class 1 product shall meet the requirements for plating voids established in Table 3-6. 125 µm [4. External foil cracks1. resample in accordance with Table 4-2 using samples from the same lot to determine if the defect is random. See 3. behind the hole wall copper plating) is evidence of a void. None allowed. Those areas of contamination or inclusions shall neither exceed 50% of each side of the interconnection. No void shall be longer than 5% of printed board thickness. There shall be no plating void in excess of 5 percent of the total printed board thickness.2 are met. nor occur in the interface of the copper cladding on the core and the copper plating in the hole wall when viewed in the microsection evaluation.2 Plating Voids Any copper plating thickness less than that specified for minimum thin areas in Table 3-3 through Table 3-5 shall be considered a void.6. regardless of length or size. For positive etchback. the product shall be considered nonconforming. There shall be no plating voids evident at the interface of an internal conductive layer and the PTH wall.3 (Type ‘‘A. 20 .2. Any PTH exhibiting this condition shall be counted as having a single void for panel acceptance purposes. however.11.6. Burrs and nodules2 Glass fiber protrusion 2 Allowed. Table 3-9 Plated Hole Integrity After Stress Property Copper voids2 Class 1 Three voids allowed per hole. For Class 2 and Class 3 product. Circumferential plating voids greater than 90° are not allowed.e.2. 3. No circumferential voids greater than 90° allowed. Allowed if minimum hole diameter is met.’’ ‘‘B’’ and ‘‘D’’ cracks) Barrel/Corner cracks1 (type ‘‘E’’ and ‘‘F’’ cracks) Innerlayer separation (separation at the interface between internal lands and through hole plating) ‘‘D’’ and ‘‘B’’ cracks not allowed. None allowed. Voids in the same plane are not allowed. measurements should follow the topography of the dielectric. and the following criteria must be met: a) b) c) d) There shall be no more than one plating void per test coupon or production printed board. ‘‘C’’ cracks allowed on only one side of hole provided it does not extend through foil thickness. 100 µm [3..937 µin] maximum 80 µm [3. If the additional test coupons or production printed boards have no plating voids. Plating folds/inclusions The minimum copper thickness in Table 3-3 through Table 3-5 must be met. Class 2 Class 3 One void allowed per specimen provided the additional microsection criteria of 3. Sample must be microetched to evaluate. Figure 3-7 Separations at External Foil 21 .DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY Allowed (see Figure 3-7) Allowed (see Figure 3-7) Allowed at knee (see Figure provided it does not extend provided it does not extend 3-7). external copper foil. None allowed. Figure 3-6 Crack Definition Note: Copper plating as shown may include multiple plating layers or cap plating. The category “B” and “D” cracks apply regardless of the number of plating layers (may or may not include cap plating).4.118 µin]. Note 2.3. Acceptable provided dimensional and plating requirements are met. Copper crack definition: See Figure 3-6 “A” crack=A crack in the external foil “B” crack=A crack that does not completely break plating (minimum plating remains) “C” crack=A crack in the internal foil “D” crack=A crack in the external foil and plating-complete break in foil and plating “E” crack=A barrel crack in plating only “F” crack= A corner crack in the plating only The minimum copper thickness in Table 3-3 through Table 3-5 must be met. external copper foil. Separations along the vertical edge of the external land(s) Plating separation Hole wall dielectric/plated barrel separation Lifted lands after thermal stress or rework simulation Note 1. Allowed provided the finished printed boards meet the visual criteria of 3. Note 3. maximum length 130 µm beyond the vertical edge of the beyond the vertical edge of the [5. Areas with the appearance of plating folds where there is no plating demarcation evident between the void and the inside edge of the plating. Laminate anomalies or imperfections in the non-evaluation areas are not evaluated on specimens which have been exposed to thermal stress or rework simulation. and 150 µm [5. Note 2. Delamination/Blistering is evaluated in both Zone A and Zone B.3 Laminate Voids For Class 2 and Class 3 products. Boundary line voids that overlap Zone A and Zone B or are entirely in Zone B shall not be in excess of 80 µm [3.150 µin] for Class 2 or Class 3 products and 150 µm [5. Multiple cracks between two adjacent PTHs in the same plane shall not have a combined length which exceeds these limits. Multiple voids between two adjacent PTHs in the same plane shall not have a combined length which exceeds these limits. The thickness measurement of A . there shall be no laminate voids in Zone B (Figure 3-9) in excess of 80 µm [3.906 µin]. Note 1. For Class 1 products.2. Boundary line cracks that overlap Zone A and Zone B or are entirely in Zone B shall not be in excess of 80 µm [3. either internal or external. Figure 3-9 Typical Microsection Evaluation Specimen 22 .DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY Figure 3-8 Plating Folds/Inclusions – Minimum Measurement Points Note 1. extending furthest into the laminate area.2.150 µin]. Note 2. Voids between two uncommon conductors in either the horizontal or vertical direction shall not decrease the minimum dielectric spacing. Enclosed folds (inclusions) acceptable if minimum thickness is met Note 3. 3. Minimum measurement points.6. voids allowed in Zone B (Figure 3-9) shall not exceed 150 µm [5.2.11. Folds that are not enclosed are acceptable if minimum thickness is met where indicated.6.0031 in] beyond the end of the land.4 Laminate Cracks Laminate cracks in Zone A (Figure 3-9) are acceptable with the exception that cracks between two uncommon conductors in either the horizontal or vertical direction shall not decrease the minimum dielectric spacing.7.08 mm [0. The thermal zone extends 0. Laminate anomalies or imperfections in the Zone A area are not evaluated on specimens which have been exposed to thermal stress or rework simulation. Note 4.B shall comply with the minimum plating thickness in 3.906 µin] for Class 1 products. Measure copper plating between lines on inclusions (must meet minimum thin area requirement) Note 4.906 µin] for Class 1 products.150 µin] for Class 2 or Class 3 products. Note 3. 3. Smear removal is not required of Type 1 or Type 2 printed boards.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY 3. 23 .3.150 µin] with a preferred depth of 13 µm [512 µin] as shown in Figure 3-10. Shadowing is permitted on one side of each land.6 Etchback When specified on the master drawing. The etchback shall be between 5 µm [197 µin] and 80 µm [3. evaluate the entire printed board per 3. printed boards shall be etched back for the lateral removal of resin and/or glass fibers from the drilled hole walls prior to plating. 3.3. Measurement for maximum dielectric removal is depicted in Figure 3-11.7 Smear Removal Smear removal is removal of resin debris that results from the formation of the hole.2. Smear removal shall not include the lateral removal of resin greater than 25 µm [984 µin].2. wicking and random tears or drill gouges resulting from hole formation and/or hole cleaning shall not exceed the sum of the maximum allowable etchback and the maximum allowable wicking. Figure 3-11 Maximum Dielectric Removal Resulting From Etchback 3. random tears or drill gouges which produce small areas where the 25 µm [984 µin] depth is exceeded shall not be evaluated as smear removal. Smear removal shall be sufficient to meet the acceptability criteria for plating separation per Table 3-9. When no etchback is specified and the printed board manufacturer elects to use etchback.6. For Class 1.8 Negative Etchback Negative etchback shall not exceed the dimensions in Figure 3-12 when measured as shown in Figure 3-12.2.6.6. Negative etchback shall not be allowed when etchback has been specified on the procurement documentation. if delamination or blistering is present.2. 3.2.5 Delamination or Blistering For Class 2 and Class 3 there shall be no evidence of delamination or blistering. the manufacturer shall be qualified to perform etchback through demonstration of qualification test coupons or production printed boards. Figure 3-10 Measurement for Etchback The combination of dielectric removal from etchback.6. Custom designed electrically testable coupons. Figure 3-13 Annular Ring Measurement (Internal) Note: Consideration should be given to how the microsection cut is ‘‘clocked.4. Measurements for internal annular ring are taken at the copper hole wall plating/internal land interface to the outer most tip of the internal land as shown in Figure 3-13.2. See Figure 3-14 and Figure 3-15 for an example of how breakout may or may not be detected within a microsection based on the rotation.2.9 Annular Ring and Breakout (Internal) Internal annular ring. if internal annular ring breakout is detected in the vertical cross section. shall be measured by microsection to verify conformance to Table 3-8 as shown in Figure 3-13. Radiographic (x-ray) techniques. Unless prohibited by the customer. if not determined by alternate techniques as agreed upon between user and supplier (AABUS). For Class 2 printed boards. Employment of filleting or ‘‘tear drops’’ in Class 3 product shall be AABUS. but the degree of breakout cannot be determined.2. the employment of filleting or ‘‘tear drops’’ to create additional land area at the conductor junction shall be acceptable for Class 1 and Class 2 and in accordance with general requirements for lands with holes detailed in IPC-2221. which shall be met in the microsection after final lamination. probes.6. and/or software. if it exists.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY Figure 3-12 Negative Etchback 3.8 and Figure 3-12. which are configured to provide information on the interpolated annular ring remaining and pattern skew.’’ or rotated. CAD/CAM data analysis as correlated to pattern skew by layer. Techniques include.6.2. internal registration may be assessed by nondestructive techniques other than microsection. such as special patterns. Negative etchback is evaluated per 3. but are not limited to the following: a) b) c) d) e) The optional F or R coupon. Microsection analysis is performed per 3. Misregistration can occur randomly as opposed to orthogonally and therefore an orthogonal cut will not guarantee that a microsection view will portray hole breakout.6. 24 . External pads of sequentially laminated structures that are buried are considered as an external layer and are evaluated in process prior to additional lamination(s) to the annular ring and breakout requirements as stated in 3. Horizontal microsection. 1 Breakout (Internal) Conditions If misregistration to the point of breakout is detected in vertical micro sections. b.11 Plating/Coating Thickness Based on microsection examination or on the use of suitable electronic measuring equipment. Isolated thick or thin sections shall not be used for averaging. 3.2. Deviations to these requirements shall be AABUS.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY Note: Microsectioning or statistical sampling shall be used to verify correlation of the approved technique. 3. the concerns are that: a.9.2. Actual printed boards or appropriate test coupons shall then be tested to determine compliance.2.6.9. plating/coating thicknesses shall meet the requirements of Table 3-2 through Table 3-5. Measurements in the PTH shall be reported as an average thickness per side of the hole. and a calibration standard established for the specific technique employed.2. The extent and direction of misregistration shall be determined. There is insufficient electrical spacing.6.10 Lifted Lands Lifted lands are allowed on the thermally stressed microsection.6.6. This may be accomplished by the techniques listed in 3. Isolated areas of reduced copper thickness due to glass fiber protrusions shall meet the minimum thickness requirements of Table 25 . The conductor width minimum may be compromised at the land junction and. Figure 3-14 Microsection Rotations for Breakout Detection Figure 3-15 Comparison of Microsection Rotations 3. the product which the test coupons or production printed boards represent are considered acceptable. etching. Note: Cap plating.11. planarization.2. if reduced copper thickness is present in the microsections.1 Copper Wrap Plating Copper wrap plating minimum as specified in Table 3-3 through Table 3-5 shall be continuous from the filled plated hole onto the external surface of any plated structure and extend by a minimum of 25 µm [984 µin] where an annular ring is required (see Figure 3-16 and Figure 3-17). If the additional test coupons or production printed boards have no isolated areas of reduced copper thickness. Figure 3-18 Wrap Copper Removed by Excessive Sanding/Planarization (Not Acceptable) 3. however. the requirements in Table 3-10 and the following shall apply.6.) resulting in insufficient wrap plating is not allowed (see Figure 3-18). it should be considered a void and resampled in accordance with Table 4-2 using samples from the same lot to determine if the defect is random. if required. Figure 3-16 Surface Copper Wrap Measurement (Applicable to all filled PTHs) Figure 3-17 Wrap Copper in Type 4 Printed Board (Acceptable) Note: Dimension lines and arrows indicate where wrap copper has been removed.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY 3-3 through Table 3-5 as measured from the end of the protrusion to the hole wall. 3. over filled holes is not considered in wrap copper thickness measurements.2. etc.11.6. Reduction of surface wrap copper plating by processing (sanding. the product shall be considered nonconforming. 26 . If copper thickness less than the minimum specified in Table 3-3 through Table 3-5 is detected in isolated areas.2 Copper Cap Plating of Filled Holes When copper cap plating of filled holes is specified by the procurement documentation (see also Figure 3-19). 005 in] Filled Via Protrusion (Bump) . When the procurement documentation specifies a minimum copper thickness for internal conductors. The minimum surface conductor thickness after processing values given in Table 3-12 are determined by the following equation: Minimum Surface Conductor Thickness = a + b .003 in] 50 µm [0. 27 . Table 3-10 Cap Plating Requirements Class 1 Class 2 Copper Cap – Minimum Thickness AABUS 5 µm [0. Voids over the resin fill are not allowed as shown by example in Figure 3-22. When the procurement documentation specifies a minimum copper thickness for external conductors. the test coupon or production printed board shall meet or exceed that minimum thickness. Separation of the cap plating to underlying plating shall not be acceptable.2.c Where: a = Absolute copper foil minimum (IPC-4562 nominal less 10% reduction). the conductor shall meet or exceed that minimum thickness.2.Maximum AABUS 50 µm [0.Maximum AABUS 127 µm [0. the minimum internal copper thickness after processing shall be in accordance with Table 3-11 for all classes.13 Minimum Surface Conductor Thickness The minimum total (copper foil plus copper plating) conductor thickness after processing shall be in accordance with Table 3-12.002 in] Class 3 12 µm [472 µin] 76 µm [0.6. This requirement is based on minimum copper foil thickness allowances per IPC-4562 followed by two successive scrubbings.12 Minimum Internal Layer Copper Foil Thickness If the internal conductor thickness is specified by a foil weight.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY The cap protrusion (bump) and depression (dimple) shall be measured as shown in Figure 3-20 and Figure 3-21.002 in] Figure 3-19 Copper Cap Thickness Figure 3-20 Copper Cap Filled Via Height (Bump) Figure 3-21 Copper Cap Depression (Dimple) Figure 3-22 Copper Cap Plating Voids 3. Separation of copper cap plating to fill material is acceptable.6.0002 in] Filled via Depression (Dimple) . Each scrub is expected to remove a specific amount of copper and is represented by a variable processing allowance reduction. 3. 3 [1.60 [967] 27.004] 81.6 [4. 123.1 [909] 26.00 [236] 6. Table 3-12 External Conductor Thickness after Plating Absolute Cu Min.4 [1.409] 40.9 [1.886] 78.2 [1.50 [4.70 [2.00 [236] 6.30] 2 oz.00 [236] 6.2 [244] 9. 1/4 oz.1 [122] 6.862] IPC-4562 value less 10% reduction Maximum Variable Processing 1 Allowance Reduction (µm) [µin] 1. Note 2.350] [1.1 31. the process allowance reduction allows for one rework process.50 [59] 4. the process allowance reduction allows for one rework process.00 [79] 3.60 [181] 7. [17.295] [4.40 [1..2.00 [157] 139. (IPC-4562 less 10% reduction) (µm) [µin] 4. (IPC-4562 less 10% reduction) (µm) [µin] Weight 1/8oz. 1/2 oz. For 1/2 oz.217] 112.626] 6 µm [236 µin] below minimum thickness of calculated 10% reduction of foil thickness in IPC-4562 Process allowance reduction does not allow for rework processes for weights below 1/2 oz.5 [5.00 [118] 4.70 [1.50 [59] 2.846] 4. 4.20] Above 4 oz.60 [3. 25 µm [984 µin] for Class 3).9 [980] 55. [137.193] 86.00] 1/2 oz.492] 144.3 [366] 11.90 [1.689] Note 1.70 [303] 10. 2 oz. For copper foil above 4 oz.80 [1.50] 3/8 oz.80 [425] 15.00 [157] Class 1 & 2 23.512] [2.5 [4.13.50 [59] 1.40 [606] 30. nonfunctional lands and/or PTHs shall be 100 µm [3.60 [4.862] 143.40 [1. [12. Figure 3-23 Metal Core to PTH Spacing 28 .154] 33.228] [1.90 [2.00 [118] 3.394] 50.646] Plus minimum plating for Class 1 and 2 2 (20 µm) [787 µin] 24. and above.7 [3.091] 30.429] 92.217] 61.083] [3.50 [5.031] 29.70 [303] 10.7 113.10] 1 oz.276] Class 3 28. [68. c = A maximum variable processing allowance reduction.2.70 [3.60 [3. [8.409] 117.650] 148.937 µin] (see Figure 3-23).50 [4.14 Metal Cores The minimum lateral spacing between adjacent conductive surfaces.6 [1.00 [157] 6.098] 108.4 [449] 24.4 52.70 [2.50 [5. Process allowance reduction does not allow for rework processes for weights below 1/2 oz. [5.591] 55.60 [1.70 [3.630] Minimum Surface Conductor Thickness after Processing (µm) [µin] Maximum Variable Processing Allowance 3 Reduction (µm) [µin] 1.90 [1.80 [425] 15.7 [2.6.60] 3 oz.5 [5. 1.646] 123.90 [2. and above. 3.50 [59] 1.433] Plus minimum plating for Class 3 2 (25 µm) [984 µin] 29.00 [236] Minimum Foil Thickness after Processing (µm) [µin] 3. 3/8 oz.6 [3.315] 47.20] Note 1.413] 117. Reference: Min.9 83.10] 1/4 oz. Table 3-11 Internal Layer Foil Thickness after Processing Absolute Cu Min.217] 61.50 [59] 1. 1 oz.429] 92.00 [236] 6.4 4 oz. [34. 3 oz.90] 4 oz. For 1/2 oz. Cu Plating Thickness Class 1 = 20 µm [787 µin] Class 2 = 20 µm [787 µin] Class 3 = 25 µm [984 µin] Note 4.40 [606] 30.80 [1.472] Weight 1/8 oz. [102. utilize the formula provided in 3.201] 86.287] 35.3 38.6. Starting foil weight of design requirement per procurement documentation.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY b = Minimum copper plating thickness (20 µm [787 µin] for Class 1 and Class 2.60 [4.213] 35. [137. Note 3.70 [1.2 34.60 [181] 7.50 [59] 1.106] [1.165] 32. if required to cover these areas with solder mask.543 µin].003 in] unless otherwise specified.076 mm [0. Solder mask need not be flush with the surface of the land. shall be of a material that is compatible to and of equal resistance to soldering and cleaning as the originally applied solder mask. 3. the area covered by a component shall be shown in the procurement document. When cap plating is specified.6. mask shall not encroach upon the barrel of this type of PTHs Other surfaces such as edge printed board connector fingers and surface mount lands shall be free of solder mask except as specified. Products designed for transmission line impedance applications may have special requirements and measurement methods specified within the procurement documentation. If a solder mask performance class is not specified for Class 1 or 2.0. Fill material within the blind via shall be planar with the surface within +/. Misregistration of a solder mask defined feature shall not expose adjacent isolated lands or conductors.7 Solder Mask Requirements When solder mask is required on printed boards. Low profile copper foils should be used with dielectrics below 90 µm [3. IPC-SM-840 Class H shall be used.1 Solder Mask Coverage Solder mask coverage manufacturing variations resulting in skips.16 Material Fill of Blind and Buried Vias Fill material in a blind via with an aspect ratio greater than 1:1 shall be 60% minimum for Class 2 and Class 3 or as specified in the procurement documentation. If the component pattern is not readily apparent. Note: If the minimum dielectric spacing and the number of reinforcing layers are not specified.2. Touch up.2. the minimum dielectric spacing shall be 90 µm [3.6. Buried vias shall be at least 60% filled with the laminating resin or similar via filling material for Class 2 and Class 3.17 Nail Heading No evidence exists that nail heading affects functionality. d.2.6. the minimum dielectric spacing is 25 µm [984 µin] and the number of reinforcing layers may be selected by the supplier.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY 3. c. and misregistration are subject to the following restrictions: a. Note: Through hole fill requirements are AABUS.543 µin]. In areas containing parallel conductors. They may be completely void of fill material for Class 1.543 µin] and the number of reinforcing layers shall be selected by the supplier to ensure the minimum dielectric spacing.7.15 Dielectric Spacing The minimum dielectric spacing shall be specified in the procurement documentation. voids. Figure 3-24 Measurement of Minimum Dielectric Spacing 3. it shall meet the qualification/conformance requirements of IPC-SM-840. e. When the nominal dielectric spacing on the drawing is less than 90 µm [3. Solder mask is allowed on lands for PTHs to which solder connections are to be made provided the external annular ring requirements for that Class of products are not violated. For Class 3. The presence of nail heading may be considered an indicator of process or design variation but is not a cause for rejection. IPC-SM-840 Class T shall be used. Conductors under components shall not be exposed or shall be otherwise electrically isolated. Solder mask is allowed in PTHs 29 b. fill material within the blind via shall meet the dimple/bump requirements of Table 3-10. solder mask variations shall not expose adjacent conductors unless the area between the conductors is purposely left blank as for a test point or for some surface mount devices. Metal conductors shall not be exposed in areas where solder mask is required. 3. Figure 3-24 provides an example of a measurement technique for minimum dielectric spacing. 3. . g.8. misregistration shall not cause encroachment of the solder mask on the land or lack of solder-mask-definition in excess of the following: 1) on surface mount lands misregistration shall not cause encroachment of the solder mask over the land area greater than 50 µm [1. b. When a land contains no PTHs. bubbles or blistering to the following extent: a. no encroachment of the solder mask on the land is allowed except at the conductor attachment. whichever is less.28. the maximum percentage of cured solder mask lifting from the G coupon or production printed board shall be in accordance with Table 3-13. if the land is solder-mask defined.1. 3. as in the case of surface mount or ball grid array lands. When design requires coverage to the printed board edge. the printed boards shall meet the electrical requirements detailed in the following paragraphs. if required to cover these areas with solder mask. The 30 .8 Electrical Requirements When tested as specified in Table 4-3 and Table 4-4. h. without flashover.25 mm [0.04921 in] or 50% of the distance to the closest conductor.969 µin] for a pitch of 1.04921 in] or greater. i. fused tin-lead. 3. Solder mask may tent or plug via holes and may be required for that purpose. and bright acid-tin) Maximum Percentage Loss Allowed Class 1 10 25 10 50 Class 2 5 10 5 25 Class 3 0 5 0 10 3. and does not reduce electrical spacing between conductors by more than 25%. 2) on ball grid array lands. Class 1 does not bridge between conductors.2. Method 2. shall be of a material that is compatible to and of equal resistance to soldering and cleaning as the originally applied solder mask. When tested in accordance with IPC-TM-650. or conductors and lands. encroachment may occur on adjacent sides but not on opposite sides of a surface mount land.7. f. Test points that are intended for assembly testing must be free of solder mask unless coverage is specified. Class 2 and Class 3 two per side.25 mm [0. misregistration may allow a 90° breakout of the solder mask on the land.3 Solder Mask Thickness The requirement to measure solder mask thickness shall be AABUS. if clearance is specified. Pits and voids are allowed in nonconductor areas provided they have adherent edges and do not exhibit lifting or blistering in excess of the allowance in 3.25 mm [0. or breakdown between conductors.7.04921 in].25 mm [0.2 Solder Mask Cure and Adhesion The cured solder mask coating shall not exhibit tackiness. delamination. Coverage between closely spaced surface mount lands shall be as required by procurement documentation.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY and via holes into which no component lead is soldered unless the procurement document requires that the holes be completely solder filled. If a thickness measurement is required.00984 in] in longest dimension. chipping or lifting of solder mask along the printed board edge after fabrication shall not penetrate more than 1. and encroachment shall not exceed 25 µm [984 µin] for a pitch less than 1.7. instrumental methods may be used or assessment may be made using a microsection of the parallel conductors on the E coupon. Rework and touch up.4.1 Dielectric Withstanding Voltage Applicable test coupons or production printed boards shall meet the requirements of Table 3-14. Table 3-13 Solder Mask Adhesion Surface Bare Copper Gold or Nickel Base Laminate Melting Metals (Tin-lead plating. maximum size 0. 3. 2 Cleanliness After Solder Mask.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY dielectric withstanding voltage test shall be performed in accordance with IPC-TM-650. or Alternative Surface Coating Application When specified. the uncoated printed boards shall be within the allowable limits of ionic and other contaminants prior to the application of solder mask coating. Equivalent methods may be used in lieu of the method specified. The dielectric withstanding voltage shall be applied between all common portions of each conductor pattern and adjacent common portions of each conductor pattern.g. Method 2.4.150 µin] or greater No requirement 500 Vdc +15.1. Insulation resistance shall meet the minimum requirements shown in Table 3-15 (at 500 volts DC). Conformal coating in accordance with IPC-CC-830 shall be applied to the external conductors prior to chamber exposure.8.2. When noncoated printed boards are tested per 3.8. -0 250 Vdc +15. Resistance of Solvent Extract Method. Non-component flush printed boards shall have a minimum requirement of 50 MΩ for all classes.. Table 3-15 Insulation Resistance Class 1 Class 2 As received After exposure to moisture Maintain electrical function Maintain electrical function 500 MΩ 100 MΩ Class 3 500 MΩ 500 MΩ The moisture and insulation resistance for printed boards shall be performed in accordance with IPC-TM-650. 3. 31 . 3.3 Circuit/PTH Shorts to Metal Substrate Printed boards shall be tested in accordance with 3.4 Moisture and Insulation Resistance (MIR) Test coupons shall be tested in accordance with the procedure outlined below.9. The voltage shall be applied between conductor patterns of each layer and the electrically isolated pattern of each adjacent layer. -0 Voltage For Spacing less than No requirement 80 µm [3.8. 3. Solder. Method 2. There shall be no flashover or dielectric breakdown. The printed board shall be capable of withstanding 500 volts (DC) +15. using a metallic brush or aluminum foil).1 Dielectric Withstanding Voltage After MIR A dielectric withstanding voltage test shall be performed after moisture and insulation resistance in accordance with 3. -0 shall be applied between conductors and/or lands and the metal substrate (heat sink or core) in a manner such that each conductor/land area is tested (e.9 and meet the requirements in the procurement documentation. Final measurements shall be made at room temperature within two hours after removal from the test chamber. -0 30 sec +3. 3.2 Electrical Continuity and Isolation Resistance Printed boards shall be tested in accordance with IPC-9252.1 Cleanliness Prior to Solder Mask Application When a printed board requires a permanent solder mask coating.9 Cleanliness Printed boards shall be tested in accordance with IPC-TM-650.3. Mealing of the conformal coating shall not extend more than 3.0 mm [0. Method 2.8.1 except that polarizing voltage of 500 volts (DC) +15. 3. Table 3-14 Dielectric Withstanding Voltages Class 1 Class 2 and Class 3 Voltage For Spacing 80 µm [3.8.6. however it shall be demonstrated to have equal or better sensitivity and employ solvents with the ability to dissolve flux residue or other contaminants as does the solution presently specified.25 paragraph 4.3. printed boards shall be tested per 3.9.9.12 in] from the edge of the test coupon or production printed board. All layers have a 100 ± 10 volts DC polarizing voltage applied during chamber exposure. the contamination level shall not be greater than an equivalent of 1. -0 between circuitry/PTHs and the metal core substrates.56 µg/cm2 of sodium chloride. 3. The test coupon shall not exhibit subsurface imperfections in excess of that allowed in 3.8.10. Insulation resistance requirements in the as-received condition shall be AABUS in accordance with 3.7.3.150 µin] Time No requirement 3.5.9. 1) shall specify which are required. Method 2.41. 3. 3.5 Mechanical Shock The test printed boards shall pass the circuitry test in 3.9. The procurement documentation and/or ordering data (see 5.13 shall be AABUS.6. Method 2.10. Input acceleration over the 20 to 2000 Hz frequency range shall be maintained to 15 Gs. 3. Method 2.3 Fungus Resistance Completed printed boards or representative printed board sections from the lot shall not support fungus growth when tested in accordance with IPC-TM-650.7. An increase in resistance of 10% or more shall be considered a reject.5 milliseconds in each of the three principal planes. It is dried and compared with a slide having dried. 3.2.5. The TDR (Time Domain Reflectometer) technique in accordance with IPC-TM-650.10. The printed board shall be tested in accordance with IPC-TM-650.5.1%). The test coupons or production printed boards shall be restrained from movement by fixturing on all four sides. Method 2. Method 2.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY 3.5.4.8. 3. The mechanical shock test shall be performed in accordance with IPC-TM-650. For large impedance tolerances. Method 2. Other methods of determining the CTE shall be AABUS.3. the CTE shall be within ± 2 ppm/°C for the CTE and temperature range specified on the procurement documentation.10. Method 2.2. Resonance Dwell – Test coupons or production printed boards shall be subjected to a 30 minute resonance dwell with 25 Gs input or a maximum of 100 Gs output measured at the geometric center of the test coupon or production printed board.10.10. the printed boards or test coupons shall meet the requirements of Table 3-9 and Figure 3-6. dimensional measurements from a micro-section utilizing a special test coupon may be used to calculate and verify impedance values in accordance with IPC-2251.9 and the acceptance criteria for that testing shall be AABUS.1 Outgassing The degree of Outgassing shall have a Total Mass Loss (TML) of less than one percent (1%) and Collectible Volatile Condensable Material (CVCM) of less than one tenth of one percent (0. If evidence of organic contamination is detected. 3. 3.6.4 Vibration The test coupon or production printed board shall pass the circuitry test in 3. 3.10. After microsectioning.1. 32 . Method 2.2 following the vibration test procedure below and shall not exhibit bow or twist in excess of that allowed in 3. Mass loss shall be determined on test coupons or production printed boards of representative substrates when tested in accordance with IPC-TM-650. uncontaminated acetonitrile on it for visual evidence of organic residue.10 Special Requirements The requirement to mandate the special testing listed in 3.2 after being subjected to mechanical shock testing as follows.4. This is a qualitative method in which very pure acetonitrile is dripped across the test coupon or production printed board and collected on a microscope slide.10.38.2 Organic Contamination Non-coated printed boards shall be tested in accordance with the procedure outlined below.39 shall be used to determine the nature of the contaminant by the use of infrared spectrophotometric analysis using the Multiple Internal Reflectance (MIR) method.3 Cleanliness of Inner Layers After Oxide Treatment Prior to Lamination The requirements to test the printed boards in accordance with 3.10.3. IPC-TM-650.10. Any visual evidence of organic residue shall constitute a failure.6.10.6.1 through 3. Method 2. The printed boards shall be subjected to both a cycling and resonance dwell test with the flat surface of the printed board mounted perpendicular to the axis of vibration in accordance with IPC-TM-650.4.3 following testing.8. Testing shall be by the strain gauge method in accordance with IPC-TM-650.7 may be used to perform impedance testing on a test coupon or a designated circuit in the production printed board. 3.9. The test coupons or production printed boards shall be restrained from movement by fixturing on all four edges.6.8 Thermal Shock Printed board or test coupons shall be tested in accordance with IPC-TM-650. The printed boards shall be subjected three times to a shock pulse of 100 Gs with a duration of 6. Cycling Test – The cycling test shall consist of one sweep from 20 to 2000 Hz performed in 16 minutes.7 Coefficient of Thermal Expansion (CTE) When printed boards that have metal cores or reinforcements with a requirement to constrain the thermal expansion in the planar directions.6 Impedance Testing Requirements for impedance shall be AABUS. Method 2.1.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY 3.1 prior to microsectioning. databases.09 m2 or less of layer area per side.2 Surface Mount Components Test coupons or production printed boards shall be 100% tested.6.1 Qualification Qualification shall be AABUS (see IPC-6011). Circuit repairs on any impedance controlled circuits shall not violate the impedance requirement. found on the finished printed board. Lifted lands are allowed. 3.21. Circuit repairs shall not violate the minimum electrical spacing requirements. The touch-up of surface imperfections in the base material or removal of residual plating materials or extraneous copper will be permitted for all products when such action does not affect the functional integrity of the printed board.1. 3. 3. Method 2.3. 3. Wicking and/or radial cracks shall not exceed 75 µm [2. The DPA printed board shall be selected from a single common inspection lot from a panel that has previously passed acceptance testing for structural integrity after stress in accordance with Table 4-3. The insulation resistance shall be no less than that shown in Table 3-15. or phototools are available from IPC. Test coupons or production printed boards should be conditioned at 50 ± 5 °C [122 ± 9 °F] with no added humidity for a period of 24 hours. The requirements specific to rigid printed boards are contained in this specification and include the Qualification Testing. lot acceptance shall require the destructive physical analysis (DPA) of a representative printed board per lot. For each type defined in 1.11 Rework Simulation 3. The unsupported component hole land shall withstand 2 kg or 35 kg/cm2. 4.11. 3. 3. Master drawings. preproduction samples.7. Qualification as AABUS may consist of documentation that the supplier has furnished similar product to other users or to other similar specifications. 4 QUALITY ASSURANCE PROVISIONS 4. Each DPA printed board shall be thermally stressed. the repairs shall be in accordance with IPC-7711/21.10 Metal Core (Horizontal Microsection) Metal core printed boards which have clearance between the PTHs and the metal core shall require a horizontal microsection prepared to view the metal core/hole fill insulation.937 µin].10. lateral spacing or voids in the hole-fill insulation material shall not reduce the electrical spacing between adjacent conductive surfaces to less than 100 µm [3. Qualification should include those applicable tests as referenced in Table 4-3 and Table 4-4. Unless otherwise specified by the procurement documentation. 3.4. Wicking. and Class 3 printed boards shall be AABUS.11.10. radial cracks. there should be no more than two circuit repairs for each 0.13 Destructive Physical Analysis When specified.10.10.36 and then microsectioned and examined in accordance with 3.953 µin] from the PTH edge into the hole-fill. whichever is less. After cooling. production sample or test coupons that are produced by the same equipment and procedures planned for the production printed boards. Acceptance Testing and Frequency of Quality Conformance Testing.3.9 Surface Insulation Resistance (As Received) Test coupons shall be tested in accordance with the procedure outlined below.1 Through Hole Components Test coupons or production printed boards shall be tested in accordance with IPC-TM-650.6. 4.11. Test coupons or production printed boards shall have been subjected to thermal stress in accordance with 3. including blind and buried.2 Sample Test Coupons Sample test coupons may be used for qualification or for on-going process control. the master 33 . Method 2.10. the insulation resistance test shall be performed in accordance with the ambient temperature measurements specified in IPC-TM-650.10.12 Bond Strength. As a guideline. Calculations of land area of the unsupported hole do not include the area occupied by the hole. Class 2.2.11 Repair The allowance of and the requirements for repair of bare printed boards shall be AABUS.1 Circuit Repairs Allowance of circuit repairs on Class 1.12 Rework Rework is permitted for all Classes. Disposition of lots where DPA has failed shall be AABUS.10. microsectioned and inspected in accordance with 3. DPA microsections shall include a minimum of three holes of each applicable PTH and via structure. Unsupported Component Hole Land The unsupported component hole lands shall be tested in accordance with IPC-TM-650.6. 3.6.4.1 General General Quality Assurance Provisions are specified in IPC-6011 and each sectional specification. The qualification should consist of capability analysis assessments (see IPC-9151). 4. A3.) protection at the 0.10 ‘‘consumer risk’’ level.T. A4. Class 3 testing may be extended to reliability test and evaluation for Class 2. D5 E2.5 All S1. E6 Types 4. M5 All N1.D. E6 Printed Board3 X X 34 Solderability Surface1 1 Hole Dimensional1 Physical Plating Adhesion1 Bond Strength Construction Integrity PTH Prior to Stress Additional Dimensions PTH After Stress Thermal Stress Horizontal micro (Metal Core) Rework Simulation Electrical Requirements DWV Continuity Insulation Resistance . E3.3 Quality Conformance Testing Quality Conformance Testing shall consist of inspections specified in Table 4-4 in a laboratory. Table 4-1 specifies the test coupons on the sample used for qualification and process capability evaluations. The numerical designation following each coupon. all samples (shown in Table 4-2) shall conform to the requirements. E5 D1. E5 D1.1 C=0 Zero Acceptance Number Sampling Plan The C=0 Zero Acceptance Number Sampling Plan shall be in accordance with the requirements of ASQ H1331.S6 All N1. 6 All S1. A6 E1. Deviations to these requirements shall be AABUS. B6 E1.L. E6 Types 2. D4. For a lot to be accepted.2 Acceptance Tests Use the C=0 Zero Acceptance Number Sampling Plan specified in Table 4-2 when ‘‘Sample’’ is indicated in Table 4-3. 4.P. This plan provides greater or equal protection for the Lot Tolerance Percent Defective (L. N5 A2. 4. The test coupons are described in IPC-2221. E4.2. B5 Design Requirement E4. A4. B4. Table 4-1 Qualification Test Coupons Test Visual 1 Type 1 All M2. 4.2 Referee Tests Two additional microsection sets from the same panel may be prepared and evaluated for microsection defects that are considered to be isolated or random in nature or caused by microsection preparation. which indicates the purpose of each coupon and its frequency on a manufacturing panel. The Index Values at the top of each sample size column associates to the A. N5 A1. A5 A1. N5 Design Requirement Design Requirement Design Requirement A1.S6 All N1. which meets all requirements of IPC-QL-653. relates to multiple instances of the coupon on the sample as indicated within IPC-A-47.Q. 4. E5 Design Requirement E3. A5 B4. both referee sets must be defect free.1 Coupon Selection Two sets of test coupons of the most complex printed board of each type of material (primary resin system and primary reinforcement) processed during the inspection period shall be selected from lots that have passed acceptance testing.3. N4. A5 A1. Acceptance testing shall be performed as specified in Table 4-3 to the requirements of this specification and IPC-6011 using either test coupons and/or production printed boards. E4. N4. A4. Both the IPC-100103 and IPC-100002 are part of the IPC-A-47 artwork package available in Gerber format. E3.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY drawing and artwork is listed as follows: Type 1 Use surface layers of IPC-A-47 artwork Type 2 Use surface layers of IPC-A-47 artwork Type 3 Use Master Drawing IPC-100103 within IPC-A-47 artwork Note: IPC-100002 is the universal drilling and profile master drawing. B5 B3. Disposition of rejected lots shall be fully documented.3. For acceptance. D4. such as M5. level. D5 E2. N4.2. 0) Sample (6.5) Sample (4. The “X in this column is not to be confused with the X test coupon which is described in IPC-2221 and IPC-A-47 and used for flexural endurance testing.5 2.01 3 3 3 7 8 9 10 11 15 18 22 29 Note 1.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY Environmental Thermal Shock Cleanliness1 Moisture/Insulation Resistance Special Requirements2 Outgassing Organic Contamination Fungus Vibration Mechanical Shock Impedance Thermal Expansion D2. Index Value is associated to the A. Note 3.0 0.5) Sample (1. **Denotes inspect entire lot.2 3. H3 Design Requirement E1.0) 35 . Lot Size 1-8 9-15 16-25 26-50 51-90 91-150 151-280 281-500 501-1200 1201-3200 3201-10.2.000 10. E5 D2. D3. Table 4-3 Acceptance Testing and Frequency Sample Test Production Coupon Requirement Printed By Printed and Method Board Board Section Test Frequency Inspection Material Class 11 Class 21 Class 31 Remarks Verifiable certificate of compliance or SPC program Per Printed Board Per Printed Board Per Printed Board Per Printed Board 3.3. E4.0) Sample (4.0) Sample (4.3.5) Sample (2.3.0 6.4 X X X X Sample (4.000 Table 4-2 C=0 Sampling Plan (Sample Size for Specific Index Value1) Class 1 Class 2 Class 3 1 1 1 1 1 1 1 2. An “X” in the “Printed Board” column denotes that the respective test is to be performed on the entire printed board and not on individual test coupons. Not technology dependent.3 3.1 3.5 4. If a particular product is determined to be ‘‘critical’’ by the user and a smaller index value is required. the user shall designate the requirement in the procurement document and should state the ‘‘critical’’ requirement on the master drawing.5) Sample (2. E4. D6 E1. E5 X X X X X X Note 1.0) Sample (4. D3.5 4. E5 H1.14 Manufacturer’s Certification Visual Edges of Printed Board Laminate imperfections Plating and Coating Voids in the Hole Lifted lands 3. H2.5 1.10 1.L.5) Sample (2.51 ** ** ** 5 3 3 5 3 5 ** 5 3 3 8 5 3 13 5 ** 5 3 3 8 5 3 13 5 ** 7 7 5 8 7 7 13 7 ** 11 8 5 13 11 8 13 11 11 9 6 19 11 9 125 19 11 13 10 7 19 13 10 125 29 13 16 11 9 21 16 11 125 29 16 19 15 11 27 19 15 125 34 19 23 18 13 35 23 18 125 42 23 29 22 15 38 29 22 192 50 29 35 29 15 46 35 29 294 60 35 4.3. Note 2.Q. D6 E1.0) Sample (2.5) Sample (2.2.01 2. value.1-3. E4. The requirement for additional test coupons shall be AABUS.001-35. 5) Per Printed Board Per Printed Board Per Printed Board Minimum 10 evaluations per panel X Sample (6.5) Solderability Surface PTH7 3.9 X X Coupons and Printed Board Sample (6.7-3.5 3.4 X X Sample (6.2.5.0) Dimensional Printed Board Dimensional Hole size Hole pattern accuracy Pattern feature accuracy Annular ring (external) Bow and twist Solder mask coverage Plating/coating thickness (electronic) Internal External Internal 3.4.5) Physical 36 Sample (4.5) Sample (4.0) Sample (4.5) 3.1 X X Sample (4.4.4.5) Sample (6.5) Sample (4.0) Sample (2.0) Sample (2.6. pinholes Dewetting/ nonwetting/final finish coverage Edge printed board connector Surface mount 3.0) Sample (4.0) Sample (4.5) Conductive Surfaces (Surface Only) Edge printed board contact.2 X Sample (6.5) Sample (4.8 X Sample (6.0) Sample (4.5) Sample (2.5) Sample (6.5) Sample (2.0) Sample (4.1 3.0) Sample (4.0) Sample (4.5.0) Conductor Spacing Per panel layer (minimum 5 evaluations per layer set) Per Printed Board Sample (2.5.4.1 3.0) Sample (4. dents.4.0) Sample (4.5.0) Sample (4.3.5) Sample (2.0) Per Printed Board Per Printed Board Per panel Per panel Sample (2.5) Sample (2.5) Per Printed Board 3.0) Sample (4.11 X X X X X C or N Sample (6.0) Per Printed Board Per Printed Board Supplier certification allowed Supplier certification allowed Per panel Per Printed Board Per Printed Board Per panel 2 Sample (4.3 3.6 3.4.0) Sample (4.0) Sample (4.7 3.4.0) Sample (2.0) Sample (4.4.1 3.5) Conductor Width 3.5) Sample (2.5) Sample (4.5) Sample (2.3.5) Sample (2.0) Sample (2.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY Marking and traceability Workmanship 3.5. junction of gold plate to solder finish Nicks.1 3.5) Sample (6.3.5) Sample (6.5) 3.0) Sample (2.5) Sample (6.2 X Sample (4.4 3.0) Sample (4.5) Sample (4.6 3.2 X Sample (4.5 3.5.5.5.0) Sample (2.5.7.0) Sample (4.5) Sample (2.2 3.5) Sample (6.4.5) 3.5) Per internal panel layer Per panel External 3.0) Sample (4.3.5) Sample (6.5) Sample (2.4.4.5) Sample (6.1 3.0) Sample (4.6 M A or A/B or S X X X Sample (4.0) Sample (4.1 Sample (6.5.0) Sample (2.3.5) . 5) Sample (0.5) Sample (0.5) Sample (0.2.8.6.0) Sample (2.5) Sample (0.5) Sample (4.5) Sample (1.2 X X C or N G Sample (6.11 3.2.6.2.0) Sample (2.0) Sample (2.8 3.5) Electrical Sample (4.2 X Type 6 1-2 Type 3-6 Sample (2.2.6.6.6.2.1 Laminate voids 3.11 3.5) Lifted lands B or A/B Sample (6.6.5) Sample (1.6.6 3.7.6.5) Sample (4.2.6 3.5) Sample (1.1) Sample (2.1) Sample (0.2.5) Sample (4.6 3.13 3.6.11 3.5) Sample (4.6 3.2.10 Hole plating thickness Surface plating and conductor thickness Electrical continuity and Isolation Resistance 3.2.5) Per Panel Per Panel Per Panel Per Panel Per Panel B or A/B Sample (6.0) Sample (4.6.6.16 Sample (2.2.1 Laminate voids 3.0) Sample (2.6 3.3.0) Per panel (1 coupon) Per panel (1 coupon) Structural Integrity After Stress Types 3-6 (Microsection)3 A and B or A/B A and B or A/B A and B or A/B A and 2B or 2 A/B A and B or A/B A and B or A/B A and B or A/B A and B or A/B A and B or A/B A and B or A/B A and B or A/B Sample (2.0) Sample (4.5) Sample (4.14 3.5) Sample (1.3 3.15 3.1) Per Panel Per Panel Per Panel Per 4.2.12 3.5) Sample (0.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY Plating adhesion Solder mask cure and adhesion Plating integrity 3.5) Sample (1.5) Sample (1.5) Sample (0.5) Sample (1.5) Sample (0.3 Etchback/ negative etchback Annular ring and Breakout (internal) Lifted lands 3.0) Sample (2.1) Sample (2.10 3.6.2.6.6 3.11 3.5 panel Per Panel Per Panel Per Panel Per Panel Per Panel Per Panel Per Panel Sample (2.1) Sample (2.1) Sample (6.5) Sample (0.5) Sample (1.5) Structural Integrity After Stress Type 2 (Microsection)8 3.6.5) Sample (1.1) Sample (2.0) Sample (2.2.1) Sample (2.1) Hole plating thickness Surface plating and conductor thickness Copper foil thickness (internal) Metal core spacing Dielectric thickness Material Fill of Blind and Buried Vias Plating integrity 3.2.6.5) Sample (2.5) Sample (1.6.2.2.6 3.6 3.6.5) Sample (4.13 B or A/B Sample (6.2.5) B or A/B Sample (6.9 3.6 3.5) 3.5) Type 1-26 Type 3-6 100% Type 1-26 Type 3-6 100% Per Printed Board 37 .6.2.2.5) Sample (6.7 3.1) Sample (2.0) Sample (4.5) Sample (0.6 3.5) B or A/B Sample (6.6. PTH solderability testing not required for Type 2 double-sided printed boards without PTHs. Note 7. each coupon from opposite corners of the panel and in opposing axes (one in the ‘‘x’’ axis and the other in the ‘‘y’’ axis). requires registration evaluation.11 3.10.10.7.BN. For Class 2 product. the degree of breakout may be assessed by methods other than horizontal microsection.10. two coupons representing that hole type are required. Note 6.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY Cleanliness Cleanliness prior to solder mask application Metal core (horizontal microsection) Solder mask thickness Dielectric withstanding voltage Circuit/plated though shorts to metal substrate Cleanliness after surface coating application Cleanliness of inner layers after oxide treatment prior to lamination Outgassing Organic contamination Fungus resistance Vibration Mechanical shock Impedance testing Coefficient of thermal expansion Thermal shock Surface insulation resistance (as received) Repair Circuit repair 3. with the two B coupons taken from opposite corners of the panel and in opposing axes (one in the ‘‘x’’ axis and the other in the ‘‘y’’ axis). For each manufacturing panel.g. unfilled through-hole.6 3. a minimum of 3 coupons (1 A and 2B) are necessary.10.5) Sample (4. 38 . Note 2.11.9. visual or AOI inspection may be used in lieu of electrical testing.9 3. All via structures shall be represented in the thermally stressed evaluations.8..4 3. buried.8 3. Measurement location must be 30% larger than collimated source. Note 5.2 3. etc. Note 4. Number in parentheses is the AQL level. Structural integrity sample can be used as ½ of the registration pair.) and plating steps define a via structure. etc. Unique construction (e.9. for a total of two coupons. For Type 1 and Type 2 printed boards. MIcrosectioning for PTH evaluation not required for Type 2 double-sided printed boards without PTHs. when utilizing the A/B design.10.10.3 3.9.. A minimum of one thermally stressed coupon representing via structures B2.10 3.. For designs with a single type hole.8. blind.1 3.1 3.10. Note 8. when utilizing the individual “A” and “B” coupon designs.10.0) Sample (4.3 3. Note 3.10. 2 A/B coupons per panel. For each manufacturing panel. B3.2 3.1 X Sample (6.1 Note 1.7 3.3 3.0) Per lot Special Requirements (when specified) As specified by contract or master drawing (frequency of inspection shall be AABUS) 3.10. filled through-hole.5 3. Not all A coupon designs will reflect the tightest design annular ring and may not provide sufficient annular ring assessment.3 3. 0984 in] grid. and date of current applicable master drawing. e. Test Coupon A or A/B contains the largest component PTH and land associated with that PTH that can be fitted to a 2. c. Title. 5. Special tests required and frequency. Part Identification and Marking instructions. issue.1 Ordering Data The procurement documentation should specify the following: a. additions or conditions to this specification that are required by the user. if applicable. number.5 mm [0.8. Specific exceptions. b. 39 . as well as the criteria invoked by the “AABUS” requirements.11 3.1 3.4 Test Coupon Type 1 A or A/B E E Types 2-6 1 1 A or A/B Test Frequency Class 1 NA NA NA NA Class 2 NA Quarterly Quarterly Quarterly Class 3 Monthly Monthly Monthly Monthly Inspection Rework simulation (when specified) Bond strength Dielectric withstanding voltage Moisture and insulation resistance E E Note 1.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY Table 4-4 Quality Conformance Testing Requirement and Method Section 3.12 3. d.2 Superseded Specifications This specification supersedes and replaces IPC-6012B with Amendments 1 & 2 in the performance and requirements section. 5 NOTES 5.10.8. revision letter. variations. Information for preparation for delivery.10. 5) Plating Adhesion 3.1 Intent This Appendix defines supplemental requirements to existing Class 3 performance attributes of this base specification for use by the space and military avionics sector of the electronics interconnect industry. Delamination.4.10 Visual - Per Printed Board 3. Crazing.2 3.3.18.3.6.3.0 µm [315 µin] Microsection or X-Ray When Code T is (Electroplated Tin-Lead prior to Fluorescence (XRF) specified fusing/reflow) Per Lot Visual 3.2.3 Class 3 Visual All subparagraphs of 3.2.4 Visual - Per Printed Board Pink Ring Plating and Coating Voids in the PTH Solderability .3.3.3 No measling.1.2.3.3.2 & Table 3-2 - Monthly Solder Thickness Minimum 8.2 3.7.2. Blisters 3. Table A.6 Visual IPC-J-STD-003 IPC-J-STD-003 IPC-TM-650 Method 2.2.1.3 require 100% inspection Per Printed Board unless otherwise indicated Does not apply to edges as defined Per Printed Board in 3.3.7 Per Panel 40 .5) Sample (2.1. delamination or blisters allowed No foreign inclusions allowed that reduce dielectric spacing below minimum Pink ring is acceptable as long as it does not propagate as a result of thermal stress None allowed on the surface 8 hour durability conditioning 8 hour durability conditioning Evidence of overhanging metal (slivers) adhering to the tape is evidence of excessive outgrowth and not allowed Visual Foreign Inclusions 3.2. A.1 3.2 Purpose When Class 3/A is specified in procurement documentation.1 SCOPE A. Specify space applications when required.4.1 1 EA – M Coupon 1 EA – S Coupon 1 Printed Board Per Printed Board Sample (2.PTH 3.1 apply.1 Remarks Class 3/A Material Type E3 (HTE) Copper Tensile 40. These Class 3/A supplemental requirements are reflective of existing performance attributes within internal OEM and recognized Industry Specifications.000 PSI [275.2.2.1 Class 3/A Supplemental Requirements Test Frequency Requirement Attribute IPC-6012 Requirement Section 3. the following Class 3/A supplemental requirements in Table A.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY APPENDIX A Space and Military Avionics Class 3/A Performance Requirements A.3.3.Surface Solderability . crazing.1 Measling. Elongation 18% minimum - Per Lot Copper Deposition 3.8 MPa] or higher.3 3.6 3. NOTE: Class 3/A product shall meet all IPC-6012 Class 3 requirements in addition to the supplemental requirements listed in Table A.6 Class 3/A Requirement Inspection/ Test Method Manufacturer’s Certificate of Compliance IPC-TM-650 Method 2. 6.076 mm [0. including surface mount lands If non-stressed coupon is evaluated.6.3 3. or laminate voids over 0.4. No contamination can occur at copper foil interface On metal core printed boards with dissimilar metals.10 3. it shall not have: Lifted lands.2.6 3.A or B Coupon or A/B Coupon Per Panel Structural Integrity after Thermal Stress Thermal Stress Testing 3.5% Class 3 None allowed on surfaces to be soldered.6.2 Table 3-9 Table 3-9 Table 3-9 3.2.4.6.2.969 µin] Not acceptable Acceptable on 20% of Invar on CIC layers Thickness of foil plus plating When Specified 5 µm [197 µin] – 40 µm [1.9 Class 3 Microsection IPC-TM-650 Method 2.4.003 in] Class 3 Class 3 On metal core printed boards with dissimilar metals. contamination at the conductive interface shall not exceed 50%.5 0.1 Microsection Microsection - Per Panel Per Panel Plating Integrity For Space Applications Only 3.574 µin] The following apply to minimum copper average and minimum thin areas: 12 µm [742 µin] above Class 3 requirement in Table 3-3 8 µm [315 µin] above Class 3 requirement in Table 3-4 5 µm [197 µin] above Class 3 requirement in Table 3-5 Per Printed Board Per Printed Board Per Printed Board Structural Integrity before Thermal Stress Additional Requirement As Specified in Procurement Documentation Microsection 1 .5 3.6.2.6 Microsection Microsection Microsection Microsection Microsection Microsection A and B or A/B Sample (2.22 Visual/Measurement Visual Per Panel Bow and Twist Conductor Definition Dewetting 3. No contamination can occur at copper foil interface No copper plating voids are allowed 50 µm [1.076 mm [0.11 Microsection A and B or A/B Per Panel 41 .6.4.2 Class 3 Visual and/or Microsection 4 .003 in] depth or more than 40% of cumulative dielectric thickness.5.5) - 2 Sections per Panel Per Panel Per Panel Per Panel Per Panel Per Panel Plating/Coating Thickness 3.F or R Coupons (Optional) Per Panel Annular Ring (Internal) 3.2.6.1 Microsection - Per Panel Plating Voids Wicking Separation Along Vertical Edge of External Lands Plating Separation Lifted Lands after Thermal Stress or Rework Etchback 3.1 Microsection - Per Panel Plating Integrity 3.2.2.1 Table 3-9 3.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY Annular Ring (External) 3.2. resin recession greater than 0. contamination at the conductive interface shall not exceed 20%.6.6. Dielectric Thickness 3.G Coupon Coupon or Production Printed Board - Per Printed Board Per Printed Board Per Panel Per Panel Per Printed Board Thermal Shock 3.6.2.004 in] max over laminate Net List Testing .6.7.1 Measurement or microsection IPC-9252 1 .2.8.7.15 Microsection A and B or A/B Per Panel Material Fill of Blind and Buried Vias Buried Vias: Minimum 85% fill 3.7.16 Blind Vias: Minimum 75% fill Microsection A and B or A/B Per Panel Solder Mask Requirements Solder Mask Coverage Solder Mask Cure and Adhesion Solder Mask Thickness Electrical Continuity and Isolation Resistance 3.4.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY If the number of reinforcing layers is not specified.2 Class 3 Class 3 Class 3 Solder Mask thickness 0.7 3.28.D Coupon on the most Complex Every Two Years Design per Minimum Material Type NA Per Lot Repair Destructive Physical Analysis (DPA) 3.100 Megohms Min IPC-SM-840 Visual IPC-TM-650 Method 2.1 3.8 No repair - IPC-TM-650 Method 2.6.2 3.13 42 .1 mm [0.7.11 3.250 Vdc .3 3.10.2 NA Microsection 1. the number of reinforcing layers shall not be less than 2.10. Minimum spacing shall be as specified on the drawing. Random missing areas of treatment shall not be >10%.969 µin]. If not specified. Minimum conductor spacing Minimum conductor spacing may be reduced an may be reduced an additional 30% due to processing. Bow and Twist Burrs and Nodules Cap Plating of Filled Holes Circuit Repair Hole breakout is allowed 90° hole breakout is allowed The minimum internal provided the land/conductor provided the land/conductor annular ring shall be 25 µm junction is not reduced junction is not reduced [984 µin]. The minimum annular ring 3. If not specified. minimum conductor thickness shall be in accordance with 3.2. Allowed if minimum hole diameter is met. lengthy requirements.2. Meet visual and dimension req.2 and Table shall be 150 µm [5.5% for all other printed board technologies.41.9. voids over the resin fill are not allowed. There shall be no flashover or dielectric Metal Substrates breakdown.8 and 3.25. 3-8 3.5.3.3 Table 3-9 3.1 3. whichever is less.5.512 in].3. Not greater than 90° breakout of hole from land when visually assessed.5.5. -0 between Circuits/PTH Shorts to circuitry/PTHs and the metal core substrates.5.09 m [0.56 µg/cm of sodium chloride.969 ft ]. minimum. 30% of minimum specified in 10% of length or 25 mm [0.6.11.1. violated. below the allowable width below the allowable width reduction in 3. if not specified. Method 2..9 and Table 3-8 Requirements Class 1 Not greater than 180° breakout of hole from land when visually assessed. splits or tears.5.10.11.1 The printed board shall be capable of withstanding 500 volts (DC) +15. 3-8 when visually assessed.12 and 3.3. Reduction of conductor thickness not >30% of Reduction of conductor thickness not >20% of minimum.3 Conductor Spacing 3.2.984 in].7 3.3.4 3.6.6.2 and Table breakout of hole from land shall be 50 µm [1. Special conditions. No cracks. reduction in 3. Visually discernable depressions (dimples) and protrusions (bumps) over via fill are acceptable providing they meet the requirements of Table 3-10. Other methods of determining the CTE shall be AABUS.5 Conductor Imperfections 3. Characteristic Inspection Etched Annular Ring (External PTHs) Etched Annular Ring (External Unsupported Holes) Etched Annular Ring (Internal PTHs) Requirement Paragraph Class 2 Class 3 Not greater than 90° The minimum annular ring 3.3 3.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY APPENDIX B Appendix B presents the performance requirements of IPC-6012C in an abbreviated form and alphabetical order. minimum conductor width shall be 80% of conductor pattern f i h d Coefficient of Thermal Expansion Color Variations in Bond Enhancement Treatment Conductor Definition 3.4. no impedance or minimum electrical spacing req.13. testing w/ strain gauge method. Minimum spacing shall be as specified on the drawing.75% for surface mount printed boards and 1.6. When cap plating of the filled via is specified on the procurement documentation.1 43 . additional 20% due to processing.4. to constrain thermal expansion in planar directions. Maximum of 0. 3.1 3. according to IPC-TM-650. If have metal cores/reinforcements with a req.5.2. whichever is less. if not specified.2.9 3.2. Mottled appearance/color variation accept.3.2 Conductor Surfaces Conductor Thickness Conductor Thickness Reduction Conductor Width 3.2 3. pattern and thickness as specified in procurement documentation.4. Cleanliness Testing in accordance to IPC-TM-650.906 µin]. 2 2 No more than two repairs for each 0. Method 2.2 3. CTE shall be within ± 2 ppm/°C for CTE and temp range spec on master drawing.1.4. 20% of minimum specified in 10% of length or 13 mm [0.8.4. See the referenced paragraph in this appendix for the full specification requirements.5. with contamination level not 2 greater than an equivalent of 1.5. and tutorial information may be shortened or partially omitted in this appendix. 5 mm [0. the minimum dielectric spacing shall be 90 µm [3. Junction of Gold Plate to Solder Edge Printed Board Contact.2. “C” cracks allowed on only one side of hole provided cracks do None allowed.906 µin]. Reduction of surface wrap copper plating by processing resulting in insufficient wrap plating is not allowed (see Figure 3-18).3.150 µin]. elongation not less than 12%. No evidence of delamination or blistering.3.5 3. Spacing 80 µm [3.150 µin] or greater.11.543 µin] and the number of reinforcing layers shall be selected by the supplier to ensure the minimum dielectric spacing. Allowed if cracks do not extend into plating. Barrel/Corner Cracks. not extend through foil thickness.25 mm [0. Imperfection does not reduce the conductor spacing below the minimum and there is no propagation of the imperfection as a result of thermal testing that replicates the manufacturing process.2.2. 500 Vdc Time: 30 sec (+3. The minimum dielectric spacing shall be specified in the procurement documentation. Junction of Gold Plate 3. 150 µm [5.2 Acceptable for all classes of end product provided the area affected by imperfections does not exceed 1% of the printed board area on each side and does not reduce the spacing Delamination/Blistering between conductive patterns below the minimum conductor spacing. For Class 2 and 3. No requirement.8 mm [0.3.000 PSI [248 MPa].2. 2 and 3. Reduction of conductor width not >20% of minimum. 3.6. Copper: 2.6.2. tensile strength not less than 36. the distance of crazing shall not span more than 50% of the distance between adjacent conductors.4 3.2.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY Conductor Width Reduction Copper Purity Elongation and Tensile Strength Reduction of conductor width not >30% of minimum.8 mm [0.5% pure. None allowed for Class 1.6.5 mm [0.8 3.25 mm [0.3. Cracks between two uncommon conductors in either horizontal or vertical direction shall not decrease the minimum dielectric spacing.4 Cracks. Solder connection: 15%. Solder connection: 5%. Copper wrap plating minimum as specified in Table 3-2 shall be continuous from the filled plated hole onto the external surface of any plated structure and extend by a minimum of 25 µm [984 µin] where an annular ring is required.2.5.3. Delamination or Blistering Dewetting If present evaluate entire printed board per 3. Laminate Crazing 3. For Class 2 and 3. If the minimum dielectric spacing and the number of reinforcing layers are not specified.0984 in] Gold: 2.1 Purity shall be no less than 99. External Foil Table 3-9 Table 3-9 Cracks.2 Copper Wrap Plating 3.4. Boundary line cracks that overlap Zone A and Zone B Boundary line cracks that overlap Zone A and Zone B or or are entirely in Zone B are entirely in Zone B shall not be greater than 80 µm shall not be greater than [3. 3. There shall be (Visual) no propagation of imperfections as a result of thermal testing that replicates the manufacturing process.3 3. 250 Vdc Time: 30 sec (+3.6.3.6.1 Cracks.150 µin].8 . 3.031 in] Dielectric Thickness 3.1 and Table 3-14 3.04921 in] Gold: 1. -0) Spacing less than 80 µm [3.04291 in] Copper: 0.5. the blister or delamination shall not span more than 25% of the distance between adjacent conductive patterns.0984 in] Copper: 1. Internal Foil Table 3-9 3.3.5 Conductors and planes are permitted.15 Dielectric Withstand Voltage Dimensional Requirements Edge Printed Board Contact.031 in] Gold: 0.8.2. -0) AABUS. 8.1 Impedance Testing 3.5.5 mm [0.7. Measling 3.4.2 Measling is acceptable for Class 1.15 mm [0.1 3.6.00394 in]. Coverage does not apply to vertical conductor edges. and not appear in >30% of lands.10. 3. Printed board shall pass test requirements of 3. workmanship or process that is not a defect. Table 3-9 3.1 3.10. 3.9 and Table 3-5 After exposure to moisture: After exposure to moisture: After exposure to moisture: 3. Method 2. Lifted lands are allowed on the thermally stressed microsection.0984 in] or 50% of distance to closest conductor. Applicable design series requirements shall apply if not specified. or depressions accept Edge Connector Lands if not exceed 0. radial cracks. As received: Maintain electrical function.2.2.2 after mechanical shock.1 Mechanical Shock Metal Cores.2. wicking and random tears or drill gouges resulting from hole formation and/or hole cleaning shall not exceed the sum of the maximum allowable etchback and the maximum allowable wicking.5 3.6. AABUS.5 3. indicating a variation in material. Innerlayer (Inclusions Between Interface of Internal Land and ThroughHole Plating) Insulation Resistance (As Received) Laminate Integrity Lifted Lands Lifted Lands (Visual) Marking (Visual) Material None allowed.2. Laminate.4.3.5. Edges (Visual) Electrical Requirements Electrical Continuity and Isolation R i t Etchback (When Specified) Nicks or haloing do not penetrate more than 50% of distance from edge to nearest conductor or 2.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY No cuts or scratches that expose nickel or copper. 3-5 See Voids.2.8.3. Pits.2.7 may be used to perform impedance testing on a test coupon or a designated circuit in the production printed board.4 3. Allowed on only one side of hole wall at each land location on 20% of each available land.4.10. whichever is less.6. Wicking.5. 500 megohms. 100 megohms. Wicking and/or radial cracks shall not exceed 75 µm [2. Translucent and other particles acceptable provided the particle does not reduce the spacing between adjacent conductors to below the minimum spacing specified in 352 No fungus growth when tested in accordance with IPC-TM-650.5 mm [0. or voids in the hole-fill insulation material shall not reduce electrical spacing between adjacent conductive surfaces to <0. Requirements for impedance shall be AABUS.10 3.1.8 Testing conducted in accordance with IPC-9252. Method 2. The TDR (Time Domain Reflectometer) technique in accordance with IPC-TM-650.1 3. Horizontal Microsection Metal Core.8.3 As received: 500 megohms.4 and Table Maintain electrical function.3 3.0984 in].4 3. and not reduce electrical spacing requirements.10 3.100 mm [0. Does not penetrate more than 2. The combination of dielectric removal from etchback.2 3.3.150 µin] with a preferred depth of 13 µm [512 µin].14 . equipment operation. lateral spacing.10. The minimum lateral spacing between adjacent conductive surfaces. whichever is less. 3. dents. the labeling requirements of J-STD-609 shall be met.3. Measled areas in laminate substrates exceeding 50% of the spacing between non-common conductors are a process indicator for Class 3 end product. Internal Spacing 3. For lead-free end product. No lifted lands on the delivered (non-stressed) printed board.6 Final Finish Coverage (Areas not to be Soldered) Foreign Inclusions Fungus Resistance Haloing Hole Size and Hole Pattern Accuracy 3.3.00591 in] in longest dimension with no more than three per land. Exposed copper on areas not to be soldered is permitted on 1% of the conductor surfaces for Class 3 and 5% of the surfaces for Class 1 and Class 2. 3.6 Inclusions.4 3. Between 5 µm [197 µin] and 80 µm [3.3.953 µin] from the PTH edge into the hole-fill.937 µin]. nonfunctional lands and/or PTHs shall be 100 µm [3.10.5. Shadowing is permitted on one side of each land. Class 2 and Class 3 end product. Conductive marking must be compatible with materials.6.6. 5. Blind Vias > 2 layers Plating Thickness. When negative etchback results in folds in the copper plating.11. insulation resistance meet requirements of Table 3-15.10. 20 µm [787 µin] Min.2. than six per side. not permitted on any conductive Nonwetting surface where a solder connection will be required. Copper. Acceptable Distance “X” not to exceed 25 µm [984 µin] if etchback not specified on procurement documentation.3. per 625 cm2. moisture and insulation resistance testing according to IPC-TM-650.12 3.2 3. 25 µm [984 µin] Min. Copper.2. the copper thickness shall meet the minimum requirements as measured from the face of the internal layer as shown in Figure 3-8. See Table 3-12.4.3.6.7 Table 3-9 Plating Integrity.3.8 and Figure 3-12 When negative etchback results in folds or inclusions in the copper plating. Distance “X” not to exceed 13 µm [512 µin] if etchback not specified on procurement documentation. Thin areas 13 µm [512 µin] See Table 3-2.4.6.476 µin] if etchback not specified on procurement documentation.2.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY Minimum Internal Layer.0394 in] with not more than [0. Table 3-2 Avg.3.6.2. than 5% of holes. Table 3-4 3.10. Nicks and Pinholes in Ground or Voltage Planes Plating Folds. Finished Coating: five voids Finished Coating: three Finished Coating: one void per hole in not more than voids per hole in not more per hole in not more than 15% of holes. Method 2.6 3.38 or 2. Method 2. Properties specified in Table 3-9. in <10% of holes.4 3. 3. tin/lead reflowed.5.2.17 Negative Etchback Distance “Z” not to exceed 37. Tested according to IPC-TM-650. not resulting in a weight loss of Outgassing more than 0. Table Thin areas 20 µm [787 µin] 3-3 3.3.1 3. Plating and Coating Voids in the Hole (Visual) Copper: three voids per hole Copper: one void per hole in Copper: none.11.3 . 12 µm [472 µin] Min. 5% of holes.5 mm Maximum size 1. Testing in accordance to procurement documentation. Thin areas 10 µm [394 µin] Avg. Distance “Z” not to exceed 19. Thin areas 18 µm [709 µin] 3. Testing in Plating Adhesion accordance with IPC-TM-650. 15 µm [592 µin] Min.0591 in] with not more four per side.10 3.1%. Pink Ring Acceptable. the copper thickness shall meet the minimum requirements as measured from the face of the internal layer (see Figure 3-8). per 625 2 cm For tin. Inclusions The minimum copper thickness in Table 3-2 must be met.2.6.5 µm [1.1. 13 µm [512 µin] Min.13 3. with no positive visual ID Organic Contamination of organic contamination.3.2. 3.2.6.5 µm [768 µin] if etchback not specified on procurement documentation. Avg.8. For positive etchback.39. Blind and Buried Microvias Plating Thickness.6. 11 µm [433 µin] Avg. Copper. measurements should follow the topography of the dielectric.2. < 5% of holes. 3.11.1 3.0 mm [0. negative etchback limits shall not be exceeded. Maximum size 1.6. PTHs Plating Thickness. 3.4.6. No portion of protective plating or conductor pattern foil shall be removed. or solder coated surfaces.1 Avg. Areas of contamination or inclusions not to exceed 5% of each side of the interconnection or occur in the interface of the copper cladding on the core and the copper plating in the hole wall. Table 3-5 3.3.2.6. blistering or delamination in excess of that allowed in 3. Method 2.11.6. Buried Via Cores (2 layers) Final Finish and Coating Thickness 3.2. Copper Foil Thickness Minimum Surface Conductor Thickness Moisture and Insulation Resistance Nail Heading See Table 3-11. No measling. 0. Solder Mask Coverage Defects along edge of land do not radially extend Defects along edge of land do not radially extend towards center by more than Solderable Surface towards center by more than 20% of the diameter of the 30% of the diameter of the Mount Lands (Round) land and not extend more than 20% of the circumference land and not extend more of the land.6. Through-Hole Plating Separation. For exposed dielectric. None allowed.3. Solderable Surface not >20%. fill material within the blind via shall meet the dimple/bump requirements of Table 3-10.2. delamination or blistering.3.2 3. No more than one void per specimen.4.2. Do not bridge conductors or expose fibers greater than that allowed in 3. maximum loss of adhesion after tape test per Adhesion Table 3-13. 3.2. No circumferential plating voids greater than 90°. 2 and 3.7 Solder Mask Conductors not to be exposed or bridged by blisters in solder mask areas. Dents. Plating None allowed. µm [5.10 3. Solder Mask Cure and No tackiness. Not exceed 0. The repairs shall be in accordance with IPC-7711/21. and do not reduce dielectric spacing below minimum.2.7. Fill material within the blind via shall be planar with the surface within +/. blistering.1 3. encroachment on lands. Solderability (Visual) Solderability testing and accelerated aging will be in accordance to J-STD-003.6.6. Table 3-9 Table 3-9 Smear Removal Smear removal shall be sufficient to meet the acceptability criteria for innerlayer separation per Table 3-9.5. or pristine area.11 Material Fill of Blind and Buried Vias 3. Does not affect functional integrity of printed board. Fill material in a blind via with an aspect ratio greater than 1:1 shall be 60% minimum for Class 2 and Class 3 or as specified in the procurement documentation. 3. than 30% around the circumference of the land. 3.7 Table 3-9 Separation.8 3. When cap plating is specified.2.6 3. internal defects not not >30%. No plating voids evident at internal layer and PTH hole wall interface.4 and 3. Special Requirements AABUS.3.1. Allowed at knee (see Figure Allowed provided the separation does not extend beyond 3-7). internal defects >10%.2 Repair AABUS.2.2.6.3.5.7.3.2. nor exceed Surface Microvoids 5 % of printed board area per side. Defects along edge of land Defects along edge of land not >20%.7 3. bridge conductors. 118 µin]. maximum length 130 the vertical edge of the external copper foil. and Tool Marks Separation Along Vertical Edge of External Land 3. regardless of length or size. pits and voids in dielectric areas and printed board edge chipping.5.7.2 .0315 in] in longest dimension. Mount Lands Defects internal to the land remain outside of the central 80% of the land width by (Rectangular) 80% of the land length. They may be completely void of fill material for Class 1.4.1 3. No plating void in excess of 5% of total printed board thickness. Innerlayer Allowed on only one side of (Separation at the hole wall at each land Interface Between location on 20% of each Internal Lands and available land.076 mm [0.8 mm [0.2. random tears or drill gouges which produce small areas where the 25 µm [984 µin] depth is exceeded shall not be evaluated as smear removal.6 3.12 3.003 in] unless otherwise specified. Buried vias shall be at least 60% filled with the laminating resin or similar via filling material for Class 2 and Class 3.2. (When Specified) Shall meet structural integrity requirements for thermally stressed evaluation coupons Structural Integrity specified in 3.16 Rework Scratches. One electrical test probe mark allowed within the pristine area for Class 1. see 3. 3.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY Plating Voids Meet requirements established in Table 3-9. Smear removal shall not include the lateral removal of resin greater than 25 µm [984 µin]. oil.1.3 3.6.27 (260 °C) Vibration Visual Printed board shall pass test requirements of 3.8 3. foreign matter.150 µin] maximum Final conductor finish as specified in 1.no visual of dirt. Weave exposure does not reduce the remaining conductor spacing (excluding the area(s) with weave exposure) below the minimum. Final finish coating per Table 3-2 for applicable coating. one or more of the following Test Methods shall be required: Thermal Stress Testing 3. No pits.2. 2 and 3.8 mm [0. 3.2 after vibration cycling. An increase in resistance of 10% or more shall be considered a reject and shall meet requirements of Table 3-9 after cycling.2. One electrical test probe mark allowed within the pristine area for Class 1.2. 3.3.3.6. Acceptable if not > 0.6.4.1.5.031 in] in longest dimension or exceed 5% of the printed board area per side. or pristine area. GWB-2 or ENIG.8 µm [32 µin] RMS as measured in accordance with IPC-TM-650.6.8.1.6. Laminate 3. testing/evaluation according to IPC-TM-650.9 .4 3. be of uniform quality.2.4.9.1 through 3.3. fingerprints.3.6.6.3.10.1 3.921 µin] maximum [3.3.1 Thermal Stress Testing.906 µin].3.150 µin].6. with temp range between -65 to 125 °C [-85 to 257 °F].27 (230 °C) 3. Shall be free of defects and of uniform quality . Finished product shall be examined. Per the applicable criteria listed in 1.15.2 Thermal Stress Testing. Method 2.7.10.4.3 3. electrical test probe marks within the pristine area that violates RMS requirement.9. nodules.5 Table 3-9 Wire Bond Pads Workmanship 125 µm 100 µm 80 µm [4. Thermal Shock When specified. not >150 µm [5.8 Voids. Pristine area shall have maximum surface roughness of 0.3 for GWB-1.6. Boundary line voids that overlap Zone A and Zone B Boundary line voids that overlap Zone A and Zone B or or are entirely in Zone B are are entirely in Zone B are not > 80 µm [3. Method 2. Test coupons or production printed boards shall be thermally stressed. and conform to 3. scratches. No weave exposure.3 Voids in Surface Weave Exposure Wicking 3. 3. Method 2.DRAFT DOCUMENT FOR INDUSTRY CONSENSUS REVIEW ONLY Defects internal to the land remain outside of the central 80% of the land width by 80% of the land length.937 µin] maximum [3. Method 2.3.3 Thermal Stress Testing. Method 2. second 1. Minimum Starting Foil for HDI layers . Final Finish – Finish X.IPC Compilation of Comments IPC-6012C.2 is ok Accepted Randy Reed.1. Tin/Lead solder Companies requiring lead free acceptance Accepted has to state lead free to invoke other inspection criteria in this specification.7. nominal value.2 It is redundant and incomplete.10 um external layers except for Type 1 which shall start with 30.3. 1.] for all internal and IPC discontinue the used of copper Accept with modification – reference the 17. Class 3A is a component of the IPC-6012 heritage specification.3.90 weights (oz. This – Table 1-2 will be updated default aligns with the thermal stress test to reference applicable specified as the default. Test Voltage.3. the typically copper weight is ¼ Revision D effort to internal and external layers.7.]. Insulation Resistance – 40 Volts.3 E E E T E Joey Rios. 1. Merix Corp Table 1-2 T Table 1-2 T Randy Reed.1 Merix Corp E E E Delete the first 1.3 Raytheon Peiliang CPCA Chen.3. 1.1. 1.3 Merix Corp Alan Exley.40 absolute minimum Solderability Test – Category 2 of J-STD-003. will reference IPC-9252 and will also no longer call out 40 volts (considered exclusionary for many current test probe systems) Move ‘Y’ to the bottom of the list ‘Other’ requirements are typically the last Accepted item listed.1.3 Scott Bowles. Final Draft for Industry Review . Eutectic Tin-Lead Solder Coating Paragraph 3.] for all For foil lamination builds with HDI Not Accepted – deferred to structures.2 Hallmark Circuits Accepted Incorrect numbering based on subject content Change paragraph number to 1. or 3/8 oz.Solder Coating ENEPIG Electroless Nickel Electroless Palladium Immersion These are listed in Table 3-2 Gold Accepted Add ENEPIG to the list of final finishes. Consistent with Table 3-2 updates Accepted– will place in T-50 Remove Should be in IPC-T-50 .3. Merix Corp Table 1-2 T Randy Reed.July 2009 Commentor Paragraph/ Figure/ Table Type of comment (Technical/ Editorial) Recommendation Reason for Recommendation IPC Committee Disposition on each comment submitted (Accepted/Not Accepted/Withdrawn) Scott Bowles.3 has (2) options. This Accepted with modification clarifies which option is the default.3.4.) for copper foil thickness.3.7um [303 uin.1 Hallmark Circuits Randy Reed.3.1.2 Hallmark Circuits Scott Bowles.4.4. EIT 1. Merix Corp Randy Reed.2 Change to 1. not the um [1.2. Accepted Add “as” to third sentence – If not specified. 1. Merix Corp Table 1-2 T Randy Reed. paragraphs.4. 1. 2 megohms Isolation resistance is not provided in the Not Accepted – Table 1-2 default.1. the thickness shall clarification be as specified… Accepted Add: b1 Lead Free Lead. Merix Corp Table 1-2 E Randy Reed.4. incorporate HDI requirements Minimum Starting Foil – 1540 um [606 uin. 15.1. 1.2 Class 3A is not an agreement between the Accepted user and supplier (AABUS).217 uin. The dimension 0.6 3. 3. Not Accepted – the TG previously agreed to with the exception of removing the bake step in Section within The bake step affects the tensile strength the test method. The copper plating thickness on repetitive requirement. E E E Remove specific examples or add “or used as an insulator Some designs use pre-preg as an external layer” insulating layer. remove the word “for”. Merix Corp Randy Reed. 3. page 11 IPC Staff . This is also an issue on IPC6013 and was brought up at APEX 2009. 14.0394 in] will be expressed in millimeters and inches. ” Accepted with modification . 3-2B. Not Accepted – some use hybrid printed boards containing PTFE materials.2. Accepted with modification – reference to both QQ-N290A and AMS-2424 will be removed.reference to both QQ-N290A and AMS-2424 will be removed. Accepted – add proposed wording.6 E 2.2(b) T Two sets of Tables 3-2. Only thickness will be called out per Table 3-2 until such time as AMS2424 can be “mined” for applicable requirements. via holes… When tested as specified in IPC-TM-650. Merix Corp 1.Commentor Paragraph/ Figure/ Table Type of comment (Technical/ Editorial) Recommendation Reason for Recommendation IPC Committee Disposition on each comment submitted (Accepted/Not Accepted/Withdrawn) Randy Reed.1 Note 2 E All dimensions greater than or equal to 1. The thickness of the plating/final finish coatings shall be in On surface and on PTHs. 3-2c 3.0394 in] will be expressed… Latest revision IPC Test Methods are available ….4.2. using 50um ….2. EIT Randy Reed.6.040 in is heard imperial unit and this paragraph specifies the dimension shall be soft imperial unit. the surface. remove the exception to the bake step from Rev B. 15. number.4 Replace SAE-AMS-2424 Plating.0mm [0. Nickel Low-Stressed Deposit QQ-N-290 was reinstated by SAE.5 T Replace SAE-AMS-2424 with QQ-N-290A or an adopted IPC SAE-AMS-2424 is not appropriate for use version of the QQ spec with PWB. Merix Corp Randy Reed. 3-5.1 Raytheon Alan Exley. Merix Corp 3.2.2. All dimensions less than 1. Method 2.2. Remove references to PTFE materials as well as IPC-4103. via holes is a Accept with modification – accordance with Table 3-2.6 T Accept with modification – remove “Current and Revised” The new Revision B to this spec (July 2009) says: “AMS-QQ-N-290B has been reinstated to cover previously qualified products.Accepted with Modification and pages 13. Merix Corp Randy Reed. in PTHS.7.0mm [0.4..2 Raytheon Joey Rios.5 AMS T and 3. Current and revised are conflicting terms to Chinese colleagues Accepted 2.4. It was agreed that if a change needs to be made it should be made to the method.1. Rename the tables on page 11 to 3-2A.18. Jim Monarchio/TTM 2. why are we referencing them here? Alan Exley. 3-4. with SAE-AMS-QQ-N-290. 2 . If PTFE based board requirements are covered in IPC-6018. The bake step was deleted in this revision. 3.2. sentence to the ongoing applications”.7 appear to contradict one another for immersion gold thickness in ENEPIG. Joe Schmidt.3. 3. EIT Peiliang Chen. 12% minimum from Rev B.6.1. Accepted – task group Elongation requirement changed from 12% to 18%. 3.7.2. Table 3-2 and 3. hence the reduced thickness requirement for gold (coverage) only. Accepted – Table 3-2 thickness changed to “Coverage and Solderable” 3 . though the 4-14 plating subcommittee should create an appropriate test method for IPC-TM-650. agreed to revert back to the 12% minimum from Rev B.7 Phil Henault.2. such as via fill or dc Accepted – task group plate may not meet 18% consistently agreed to revert back to the 12% minimum from Rev B.7. no less than 18% for class 3. Merix Corp 3. Raytheon/ Joe Schmidt.1 Merix Corp Randy Reed.6. but section 3. class 1 and class 2.5mm x 1. Appendix 4 is being used out of context per Gerard O’Brien author of Appendix 4. Not Accepted – task group feels that IPC-4552 Appendix 4 already address this. Not Accepted Accept with modification – nd remove the entire 2 sentence.6. method (through hole.1 to get to Table 1-2. based on how the chemistry is configured.7.2 CPCA Randy Reed.2. press-fit. 3. Accepted Change to: “the tensile strength shall be no less than MPa is a SI (metric) unit and PSI is T T Joey Rios.2 3.6.6.1 and 5.2. Accepted – will transfer that “This finish is suitable for wire bond and connector Clarification.7.6 E E E 248 MPa [36. If not specified.2. 3.7. SMT. Accepted – task group Change to: ”and the elongation shall be no less than 12% for agreed to revert back to the 18% may be required for class 3and class 12% minimum from Rev B. T Measurement methodology shall be by XRF Spectrometry with a maximum collimator that is 70% of the feature size measured. This is where the user will go for this requirement with wandering through 1.7. Not sure what is meant by “connector final finish update in IPCapplications”. The intent is the collimator size or feature size needs to be controlled.” Which is correct? Accepted Add a reference to allowing XRF as a measurement tool for Consistent with ENIG.3 Merix Corp Randy Reed.” 3A only. the selection default is Table 1-2.2.2b Raytheon / Alan Exley. Intimate contact….7 T Joey Rios.2(b) T The tensile number was increased from 12% to 18%. The feature size being recommended by IPC-4552 is 1.2b T Please provide the technical data for the Accepted – task group change. palladium is more resistant to immersion gold. Merix Corp 3. Marybeth Perrino.2. 3. Raytheon Table 3-2 calls out for 1 um minimum for immersion gold for ENEPIG.)? ( Phil Henault) Are these statements more appropriate for IPC2221 instead of 6012 (Joe Schmidt) imperial. Paragraph 1.Commentor Paragraph/ Figure/ Table Type of comment (Technical/ Editorial) Recommendation Reason for Recommendation IPC Committee Disposition on each comment submitted (Accepted/Not Accepted/Withdrawn) Randy Reed. EIT 3.1 already states all deviations are AABUS.7 states “Unlike nickel.7. Adopt MIL-PRF 31032 parameters for elongation (12%) Various plating baths. Raytheon Peiliang CPCA Chen.6.2.3.2.2. 18% is too high for class 1 and class 2. EIT 3. They do however meet 12% with ample margin. This dimension excludes BGA pads which is not realistic.000 PSI] …” Remove last sentence Deviations shall be AABUS. and it is how ENEPIG thickness currently practiced by fabricators.2.5m.2. Request it Request justification/data for the change agreed to revert back to the be returned to 12%.7 T T 3. Is this referring to the connector assembly 2221B.3. Table 3-2 E Peiliang CPCA Chen. Accepted with modification Applicable Acceptability Specification for Code S. Raytheon Table 3-2 T 4 .7. J-STD-003 is used. be “J-STD-003” alloys Not Accepted – although ASTM B-579 is the specification for occasionally used for Applicable Acceptability Specification for Code TLU should be electrodeposited coating of tin-lead alloy printed boards. Cisco Joey Rios.08 . the ASTM “ASTM B-579” specification is not written (solder plate) for printed boards.05um [1.8 T Delete “and apply for both a thin silver deposit and/or a thick No more thin silver deposit in new edition silver deposit. J-STD-003 states the test – reference both J-STD-003 methods and inspection criteria for and J-STD-006. Accepted Consistent with description in section 3.97 uin] and Gold thickness alone does guarantee the solderable.” of IPC-4553A IPC Staff . (Mike Luke) thickness requirement as is suggests .3. Accepted with modification Remove footnote for OSP. HT OSP. For solderability test. Alan Exley.3 consistent with IPC-4553 and IPC-4554. surface is solderable. T should – reference both J-STD-003 and J-STD-006 is requirements for solder and J-STD-006. and TLU Applicable Acceptability Specification is J-STD-003 Table 3-2 Table 3-2 T T Randy Reed. surfaces on PBs (Joe Schmidt) ENEPIG: Change minimum thickness of Imm Au to coverage only Code S. solderability.1-9. Table 3-2 T Peiliang CPCA Chen. Merix Corp Table 3-2 T Mike Luke.Commentor Paragraph/ Figure/ Table Type of comment (Technical/ Editorial) Recommendation Reason for Recommendation IPC Committee Disposition on each comment submitted (Accepted/Not Accepted/Withdrawn) Peiliang CPCA Peiliang CPCA Chen. b1. Applicable Acceptability Specification – IPC-4552 and J-Std003. ASTM B679 bondable finish.8 micro-inches for solderable for nickel and gold. ENEPIG finish is for a range but no range is specified.7 J-STD-006 controls solder alloys and flux Accepted with modification material testing. EIT Randy Reed. Withdrawn Code ENIG – Solderable Surface -0.. Merix Corp Table 3-2 T Not Accepted – IPC-6012C must use IAg and ISn throughout in order to be Change Code IAg and ISn to IS and IT To conform with 1.Accepted Chen. Table 3-2 T Jennifer Burlingame.6. Joe Schmidt. T. Range for both solderable and wire Accepted with modification – changed to a minimum Suggest 15 to 30 microinches (Mike Luke). and ISn “solderable” This footnote only applies to HAL & HASL – replace with reference to requirements coatings as it is currently written 3. 3. b1.2.7.4.25 um or 3.2.3. 3-5. Note 2 makes it sound like the total 1st Comment: Accept with Reword note 2. T Section 3. Cisco Wendi (ddi) Table 3-3. 3. then I strongly suggest adding columns. 3-4 Randy Reed.6. 3-5 Re-number tables so there aren’t two labeled “Table 3-3” It is critical to clarify that these values Accepted with modification should be the minimum average – add “Minimum” to the title of the Table and remove the thicknesses allowed. Cisco Jennifer Burlingame.Accepted Duplicate numbering Tables 3-3. and 3. requirement. It is tagged on and extend or wrap from (Copper – Average) section. it in a footnote. “average” means in copper plating – use this reference for both thin areas and average in thickness requirements. If more wording is required to corresponding table clarify this.2 – which defines Needs further clarification as to what is Not Accepted – these tables are for thickness how many and what percentage of these “thin areas” are meant by “thin area” in copper plating requirements and 3. restoring original text in aspect ratio.11 (T) Boger Table 3-3. copper thickness must be continuous from modification – Note 2 will now say “shall be continous the hole onto the surface.2.6.6. I would think most OEMs using Class 3 would prefer to maintain an average above 1 mil. Table 3-2 Note 3 of IPC6012B W/AM1 5 . Table 3-3 through 3-5.3 Tables 3-3. however.3.2 is thickness requirements. Cisco Table 3-3 T Change category title to “Copper – minimum average” Jennifer Burlingame. for plating voids. I see that footnote 3 was added to target high reliability end boards through-holes. Merix Corp Table 3-3 Note 1 T Suggest adding a reference to Section 3. 3.2.6.Commentor Paragraph/ Figure/ Table Type of comment (Technical/ Editorial) Recommendation Reason for Recommendation IPC Committee Disposition on each comment submitted (Accepted/Not Accepted/Withdrawn) Jennifer Burlingame. not the target word “Minimum” from the average. Note 1 original text in Table 3-2 difference how the via is formed. Cisco Jennifer Burlingame. Accepted with modification Suggest adding a reference to Section 3.11 – which Needs further clarification as to what defines what is meant by “average” and how to calculate it. IPC Staff .2. 2nd Comment: Accept with I don’t think it really makes any modification by restoring Note 1 (table 3-4) remove the mention of mechanical drills. I believe the hole walls…” Also update intent is to have the minimum wrap plating Figure 3-17 by depicting a thickness be continuous not the total hole through-via without fill.T 4. Note 3 of IPC-6012B Does not apply to aspect ratios less than or equal to 1:1 The microvia definition is based on aspect Accept with modification by ratio.T 4. allowed.2. The microvia definition is based on aspect ratio. Figure 3-4 Raytheon Joe Schmidt. as the same number. IPC Staff . Marking inks shall be applied to the PB. Randy Reed. Accepted 6 . Merix Corp Joey Rios. or to a label applied to the PB. Request note 3 be removed. the marking shall be treated as a conductive element on the PB.10 Marking Inks Marking inks shall be specified in the procurement documentation. Would make the wrap plating requirement effectively the Note 2 will now say “shall be continous and extend or same as the copper hole requirement. Marking inks shall conform to IPC-4781. Merix Corp Table 3-4 Note 1 T Randy Reed. Table Raytheon Note 3 3-3 T Minimum thin area copper on via diameter less than or equal Request justification/data for the change.Commentor Paragraph/ Figure/ Table Type of comment (Technical/ Editorial) Recommendation Reason for Recommendation IPC Committee Disposition on each comment submitted (Accepted/Not Accepted/Withdrawn) Joe Schmidt.Accepted Move figure location to after Table 3-9 where it is referenced Moving figure closer to the referring paragraph IPC Staff . There should be no criteria based on the forming method for the hole (i. IPC Staff . EIT Figure 3-4 E E E Joe Schmidt. as defined in this document. or to a label applied to the PB. the marking shall be treated as a conductive element on the PB. Marking inks shall be applied to the PB. EIT Wendi (ddi) Boger Table 3-4 Note 1 Table 3-4 Table 3-5 T E Joey Rios.2. 3. Figure 3-5 Raytheon Microvias are defined as less than or equal to 1:1 aspect ratio. to . microvias. Does not make sense to have a minimum and a minimum avg.Accepted Move figure location to after Table 3-9 where it is referenced Moving figure closer to the referring paragraph Accept with Modification: Accepted – it was noted that this notation was originally intended for IPC6013 flex. mechanical drill).e. Delete sentence ‘All performance characteristics for plated This statement is not applicable for through holes. Other requirements are specified in IPC4781 Qualification and Performance Specification of Permanent. 3.Accepted Revise footnote 1 reference to a Table 3-2C The draft does not have a Table 3-2c Accept with modification – Reword note 1.10 T Change to: 3. wrap from hole walls…” IPC Staff .35mm and aspect ration >3.2. If a conductive marking ink is used.Accepted Consider moving subject figure closer to table 3-9 Flows better when it’s near its initial reference. where the higher requirement is necessary due to the acrylics present in plated holes in flexible printed boards Accept with modification by restoring original text in Table 3-2 Note 3 of IPC6012B W/AM1 Accepted Peiliang CPCA Chen. SemiPermanent and Temporary Legend and/or Marking Inks Steve Vetter. Marking inks shall be permanent and shall conform to IPC-4781 or be as specified in the procurement documentation.2. shall be met.5:1 change from 20 to 25um. If a conductive marking ink is used. Similar issue as above.14 NSWC Crane E Embedded passive materials shall be selected from in accordance with IPC-4811 or IPC-4812. 2. 3. Table 36 is part of visual evaluations (1. Why was this paragraph updated? Weave exposure and exposed/disturbed fibers were acceptable for all classes as long as minimum spacing was reduced.3.Accepted – separate the criteria for for class 3 as long as they do not reduce weave exposure and minimum spacing. 3. Phil Henault. however.5 Hallmark Circuits Randy Reed. intended to agree.2 E T Second sentence.” 7 . T Clarify the statement applies with a layer Accepted with modification and between layers on the board edge.4. This statement is in alignment with internal Accepted with modification layers where is breakout is an acceptable – “If breakout occurs at the condition.2 Change Table 3-9 and 3. The assessments on outer conductor/land intersection layers will be more accurate than internal it shall be acceptable if in layers because the orientation of the drill accordance with Figure 3to the pad is apparent in all axes. Why was the Class 3 requirement tightened? (Joe Schmidt) Alan Exley.2 to agree with Table 3-6 in terms of allowable / unallowable number of voids.3. If breakout occurs it shall not reduce the conductor/land intersection less than the minimum annular ring requirement. 2nd Comment .3. Delamination is an internal condition that propagates after thermal stress exposure and may be a catalyst for CAF growth. as well as 3. change “insure” to “ensure” Add sentence The reflow process type shall be specified on the master drawing. inspection criteria in this specification. 3.. The agreement made with the Accepted with modification Assembly/Joining group was premised on – use the word “does” the definition differences between instead of “may” in place of measling and delamination that can have “shall”.1 Note T Solid ground planes. 3. but Table 3-6 indicates that Class 3 can have 1 void per hole Scott Bowles. Merix Corp 3.2. shall be exempt from this distance measurement. Not Accepted .1 T Randy Reed.6. wording in rev B.Perry to locate original data What is the justification for not allowing supporting Class 3 weave exposure on Class 3? (Joe requirement for weave Schmidt) exposure in IPC-A-600. – text removed and action to incorporate this into IPC2221/2222.(Phil Henault). Table 3-3 indicates that Class 3 cannot have voids. Merix Corp 3.3. Joe Schmidt Raytheon T Delete reference to “exposed/disturbed fibers”. Delamination does propagate.5 Raytheon. (Phil Henault).Accepted Correct spelling and consistency with term used elsewhere within this document Companies requiring lead free acceptance OBE – now addressed in has to state lead free to invoke other Table 1-2. Measling does not propagate when exposed to thermal stress.3. st Exposed/disturbed fibers are acceptable 1 Comment . with an exception of adjacent planes (vertical or lateral) with a voltage gradient between such planes at the PB edge. if not specified. The difference is size of the surface being evaluated. Measling is an internal condition that shall not propagate after thermal stress exposure and has not …. tin/lead soldering method and inspection criteria shall be used.Commentor Paragraph/ Figure/ Table Type of comment (Technical/ Editorial) Recommendation Reason for Recommendation IPC Committee Disposition on each comment submitted (Accepted/Not Accepted/Withdrawn) Randy Reed. (see Rev B and Aexposed/disrupted fibers as 600).These Tables 3-6 and 3-9 need to agree in sections were never number of voids allowed. IPC Staff . Merix Corp 3.2.6. Go back to the is done in IPC-A-600.75X – 40X) and Table 3-9 is part of microsection evaluations (100X – 200X).2.. a common appearance during visual assessment. Table 3-6 and T Raytheon 3-9.6 Merix Corp Randy Reed. Consistent with the order in which they appear in the document. which itself needs to be bulk plating. land/junction reduction allowance from Table 3-5 Table 3-9 for PTH integrity after thermal stress (now Figure 3-7).2 Hallmark Circuits T Remove entire section or add more clarification Doesn’t make any logical sense to me as worded. All areas under solder mask are not to be soldered. These drawings need to be – add text to the reference updated to reflect that cap plating applies to Figure 3-5 that the “B” to partial and complete cracks in the and “D” cracks apply copper plating or that the cap plating does regardless of number of not apply. Merix Corp Randy Reed.00591 in]. minimum spacing on the board. Joey Rios.1. Accepted with modification – reworded as follows: Solder mask overlap or encroachment onto tin lead or solder on areas not to be soldered is acceptable provided the overlap does not exceed 0. Intent not clear.2 T Randy Reed.5. plating layers (may or may not include cap plating) – Now Figure 3-6. Merix Corp Randy Reed. Phil Henault 3. to the Table title. Scott Bowles.2. Delete the line extending end of layer in the lower left hand Accepted (Now Figure 3-7) corner of the Figure.4.6.11. Not Accepted – the task Suggest adding one additional category of barrel/corner cracks A defect mode not categorized by current group feels this is already besides type E and F – where there is a foil-to-Cu plating types addressed through Figure separation/crack but it doesn’t extend beyond the foil into the 3-4.5.4. Cisco Figure Table note 1 3-5. Final finish could be “T” or “IT” and then solder mask.4.This prevents drill deflection from reducing Accepted – Note 2 moved instate Note 2. Not considered a crack but a separation.15 mm [0. Accepted – see above.3 and renumber to 3-4 and 3-5.7. Accept with modification – move both figures to before paragraph 3.4.5. B and D cracks do not represent designs with cap plating.7.4. I guess you could have spots of tin or tin-lead that were not completely removed after etching that end up under the solder mask. Internal Plated-Through Holes Class 1 and Class 2 – Re. E 3-9 Accepted and OBE (see comment above) – modifiy Figure 3-3 to indicate that A is less than B. EIT 3. Cap plating is specifically defined in Accepted with modification Update the drawings to reflect that cap plating applies.5. 8 .2. 3. 3.Commentor Paragraph/ Figure/ Table Type of comment (Technical/ Editorial) Recommendation Reason for Recommendation IPC Committee Disposition on each comment submitted (Accepted/Not Accepted/Withdrawn) Phil Henault 3. Merix Corp Table 3-8 Figure 3-4 Figure 3-5 T E T Jennifer Burlingame. moved to appear after Either delete new sentence or delete Figure 3-3 and Contradictory requirements.2 E Consider renaming Figure 3-7 as 3-6 and vice versa.2 T Reword. Ambiguous. 2. Microsections selected from productions PBs shall be removed The 3 holes minimum assures the same from opposite panel corners. this can be AABUS.5. Accepted with modification – will read as “When cap plating of the filled via is specified on the procurement documentation. Suggest 200x w/ 400x for referee. etc. EIT Sec 3.1 is for microsection evaluation – both sections were assigned for development by the D-33a TG. Accepted with modification: “Microsections selected from productions PBs shall be removed from opposite panel corners. float only. final finish and thermal processing.1. Randy Reed.11. If three holes are not available. are not allowed. Cisco 3. and shall have (3) holes minimum. order.2.3 shall be out of Table 3-2 to Table 3-3 through 3-5. and shall each have three (3) holes minimum.5.6.Commentor Paragraph/ Figure/ Table Type of comment (Technical/ Editorial) Recommendation Reason for Recommendation IPC Committee Disposition on each comment submitted (Accepted/Not Accepted/Withdrawn) Jennifer Burlingame.2 and Table 3-10.4. 3.8 T When cap plating of the filled via is specified on the Clarify so reader does not confuse this procurement documentation. Randy Reed. The current wording would permit the supplier to remove the sample after copper etch for these processes. shall be inspected in the x and y number of holes is evaluated within the axis.6. lands.8 E Delete this section Duplicate of Section 3. plating voids exposing the resin fill are not allowed.6. The evaluation of all properties and requirements shall be performed on thermally stressed test coupons and all requirements must be met.5 Raytheon Table 3-9 Jennifer Burlingame. cap to underlying – clarification provided to “Separation along the cap plating section if this falls into this category or to reference plating.1. Specify “higher” magnification allowed for foils that are less Clarification than 3/8 oz.” Accepted 9 .Accepted specified for minimum thin areas in Table (3.6. Joey Rios. Cisco Steve Vetter. shall be inspected in the x and y axis.4. Not Accepted – this is in section 3 for visual acceptance – section 3.2. vertical edge of the external for exception requirements.6. Merix Corp 3.6 T Include in the parenthetical phrase a reference to next gen Parenthetical phrase references solder thermal stress testing. considered a void.” Plating Voids Any copper plating thickness less than that Copper plating thickness has been moved IPC Staff . Merix Corp 3.6 T Randy Reed.” Accepted with modification – replace reference to solder float with reference to para.2) 3. Recommend adding clarity to what is meant and included in Not clear if this is only between multiple Accepted with modification the “Plating separation” category. final finish voids over the resin fill requirement with copper voids.11. 3. Add reference footnote to Cu plating layers. and really doesn’t fit into this part of the document as anything related to previous sections.” Accepted with modification: “The coupons shall be tested after the PB is exposed to all coating.6 T Alan Exley.2 NSWC Crane T E E This statement assures product that exposed to tin/lead reflow and HASL are thermal stressed after these steps. The coupons shall be tested after the PB is exposed to all process steps that exceed the glass transition temperature for the material. 3. Merix Corp 3. Commentor Paragraph/ Figure/ Table Type of comment (Technical/ Editorial) Recommendation Reason for Recommendation IPC Committee Disposition on each comment submitted (Accepted/Not Accepted/Withdrawn) Randy Reed, Merix Corp Figure Note 2 3-8, T Phil Henault Fig. 3-8 T Randy Reed, Merix Corp Figure 3-8 T Folds shall be enclosed and comply with minimum plating IPC-T-50 defines inclusions as metallic or Withdrawn contingent on non-metallic particles. Air gaps are not the 2-30 committee thickness in 3.2.7.11. included in the definition. adoption the new definition for “Inclusion” in IPC-T-50 Add “Minimum Measurement Points” to title. Change Footnote Eliminate the word “nonconforming” which Accepted – incorporate the change to Footnote 1. 1 to read “Folds that are not enclosed are acceptable if may be interpreted as “rejectable”. minimum thickness is met where indicated.” Add Note 4 Areas with the appearance of plating folds where The missing demarcation line is indicative Accepted with Modifcation – there is no plating demarcation evident between the void and of a metallurgical bond that has Randy to provide the the inside edge of the plating, combined the plating thickness. acceptable reliability performance. following changes to the The thickness shall comply with the minimum plating thickness Figure: in 3.2.7.11. 1) Alteration of Note 3 to show multiple points of measurement. 2) Illustrate demarcation line Randy Reed, Merix Corp 3.6.2.4 T Randy Reed, Merix Corp Figure 3-9 T Randy Reed, Merix Corp Figure 3-9 T Cracks in Zone A and Zone B or are entirely in Zone B shall Remove ‘originate in’ and ‘extend to’. Accept – remove the word not be in excess of …… Origination and propagation of laminate “originate” and replace with cracks rarely is apparent after thermal “boundary line”. stress. This is more apparent after reliability testing. Plating Voids in same Plane pictorial. None of the voids are in Provide a valid example in drawing. Accepted with modification the same plane. Update drawing or change the label to say – IPC Staff to remove the ‘Plating Voids not in same plane’. words “in Same Plane” and move “Plating Voids” closer to the hole in the Figure. Have some of the layers misregistered to depict how to Boards are rarely perfectly registered as in Accepted – IPC Staff to measure and define Zone A. this drawing. Provide a more realistic update Figure 3-9 example. 10 Commentor Paragraph/ Figure/ Table Type of comment (Technical/ Editorial) Recommendation Reason for Recommendation IPC Committee Disposition on each comment submitted (Accepted/Not Accepted/Withdrawn) Randy Reed, Merix Corp Figure 3-9 T Randy Reed, Merix Corp 3.6.2.6 T Randy Reed, Merix Corp Randy Reed, Merix Corp Jennifer Burlingame, Cisco Jennifer Burlingame, Cisco 3.6.2.6 3.6.2.6 3.6.2.7 E T T 3.6.2.6, 3.6.2.7, Figure 3-10 E Void at boundary line (see Note 2). Remove reference to Note Voids at boundary line and note are Accepted – note 2 does not 2. related. Voids at boundary line (Zone A apply. Figure 3-9 also and B) are unacceptable. needs to be updated to move the text above the double arrows in Zone A closer to those arrows. We also need to depict blistering linked to Note 3. Withdrawn – task group Delete the sentence above Figure 3-11 stating the maximum Combine this statement with the 2nd sentence of this paragraph which gives agreed to add new wording dielectric removal. the minimum preferred, and maximum indicating dielectric removal preferred depth. resulting from a combination of etchback, wicking, and gouging, with a corresponding update to Figure 3-11 Accepted The etchback shall be between 5um and 80um with a preferred depth of 13um is depicted in Figure 3-10. Remove the caution. This is not true for periodic reverse pulse Accepted – move to IPCplate chemistries. 2221B. Accepted Suggest new wording of 2nd sentence to be: “Smear removal Clarification of defect: should be separation, not plating shall be sufficient to meet the acceptability criteria for innerlayer separation innerlayer separation per Table 3-9.” Suggest consolidating the categories marked as “maximum Very confusing what the difference is – if Accepted with modification – 3.6.2.6 will say “The dielectric removal” in 3.6.2.6 (including Figure 3-11) and any- between these 2 types of defects. I combination of dielectric Section 3.6.2.7 into one section. Simplify into 2 main defects – believe they are one and the same, but it removal from etchback, shows 2 different specs. excessive etchback and smear removal. wicking and random tears or drill gouges resulting from hole formation and/or hole cleaning shall not exceed the sum of the maximum allowable etchback and the maximum allowable wicking.” 11 Commentor Paragraph/ Figure/ Table Type of comment (Technical/ Editorial) Recommendation Reason for Recommendation IPC Committee Disposition on each comment submitted (Accepted/Not Accepted/Withdrawn) Jim Monarchio/TTM 3.6.2.6; 3.6.2.7 Table 3-9 T Remove any measurement of Etchback for 3.6.2.7 These 3 appear to be in conflict. 3.6.2.6 Accepted with modification addresses Cliff Maddox, 3.6.2.8 Boeing Cliff Maddox, 3.6.2.8 Boeing T T Randy Reed, Merix Corp 3.6.2.8 Note T Randy Reed, Merix Corp Figure 3-12 T Joey Rios, EIT 3.6.2.9 E Address wicking in a Fig like Fig 3-10; defining where Accepted – update Figure 3.6.2.6 addresses Etchback and resin 3-11 to incorporate wicking etchback ends and wicking begins removal but does not address wicking as part of the total boundary (Table 3-9) allowance described in 3.6.2.6. i.e if a glass bundle lies against a layer and the Cu plate wicks along the Cu layer is that wicking, etchback, or both? Accepted Delete NOTE: text associated with Figure 3-12 in its entirety New text supporting negative etchback is confusing and unnecessary Delete or redraw Fig 3-12 (now Figure 3-8) and supporting Fig 3-12 (now Figure 3-8) is confusing and Accepted – Figure 3-12 will be moved to occur after text. poorly drawn to show primarily laminate Table 3-9 (now becomes tear-out with only a single instance of Figure 3-8). This removes negative etchback. Is intended to show its applicability to section plating folds and inclusions but is included 3.6.2.8 and now serves as a at 3.6.2.8 under “NEGATIVE reference only to Table 3-9 ETCHBACK”. This adds nothing for plating folds/inclusions. significant to 3.6.2.8. Possibly this could be redrawn for clarity and used under 3.6.2.11 “PLATING AND COATING THICKNESS”. Dimension “Y” within Figure 3-11 depicts a condition that is a Dimension X is not thickness of the foil. Accepted by default – note was deleted per previous process indicator of negative etchback. There is no evidence Need to add dimension Y to drawing. nd comment to Figure 3-11 (2 exists that boards result of the front of the copper foil affects comment prior to this I can support a statement this is a process functionality. comment). indicator. If stronger wording is desired, the committee needs to review engineering data. Add Distance ‘Z’ dimension All dimensions are 1.5 times the Distance Accepted – IPC Staff to X. update Figure 3-12 Class 1 – 37.5 um [1,476 uin] This removes misinterpretation of Class 2 – 37.5 um [1,476 uin] Distance Z measurement. Class 3 – 19.5 um [768 uin] Within the sentence "External pads of sequentially laminated Unclear if internal or external annular ring Accepted with Action Item structures....." clarifiy if the external pad of an internal structure criteria applies to the ‘external pads’ of to submit proposed wording change to task group via e(as initially built) that ends up buried in the final structure is internal via structures. mail correspondence for then evaluated for annular ring with external or internal approval on 09/30/09 critieria. 12 This problem needs to be solved by updating the legacy drawings. Highlight internal via pth wrap in figure 3-17. Merix Corp Randy Reed. In case the copper cap is used as a test point the cap tends to come completely loose of the PB.13 T Change the 3rd sentence (new sentence). as applicable.6. 3.2. Minimum surface The board manufacturer needs to conductor thickness should not be expressed in oz. weight. Issue to be deferred to discussions on the build of new HDI/IPC6016 requirements for a future revision of IPC-6012.1 is unclear on whether wrap requirements apply to internal vias as well as vias that terminate on the surface of a board. conductive fill (or resin) material that is added into the hole after plating. Add specific copper wrap plating requirements (if any) for Copper Wrap Plating requirements seem to be specific for a conductive or noncopper plated shut (filled) vias.11.2. Not Accepted – The current requirements in IPC-6012C (Table 3-4) apply to copper filled vias. Some Default could be AABUS.task group requests clarification with the addition of visual examples of the failure condition for consideration in a future revision. We do not use a qualifier Absolute on any other minimum dimensions. The copper cap thickness on internal microvia target land Clarify statement. Merix Corp Visa Ruuhonen. Merix Corp 3.6. Wrap requirements as written in this draft does not appear to apply. This specification presents excellent justification why microsection cannot assess annular ring.11.2. EIT Fig 3-17.2.11.6. customers are specifying a 100% copper plated shut microvia. The wording on 3. Nokia Siemens Networks Table 3-10 E Table 3-10 Table 3-10 Note 1 3.2 T E Conflicts with Class 2 PBs paragraph later in this section. weight. Figure 3-17 does not highlight internal via wrap. Not to allow separation of copper cap plating to fill material. Merix Corp Randy Reed. 3-18 E Randy Reed. Accepted – restore dimension lines and arrows to the bottom side of all four via structures in Figure 3-18 Accepted Accepted Accepted with modification – it was agreed to remove the note.Commentor Paragraph/ Figure/ Table Type of comment (Technical/ Editorial) Recommendation Reason for Recommendation IPC Committee Disposition on each comment submitted (Accepted/Not Accepted/Withdrawn) Randy Reed. flexibility to report the surface thickness in the same units as the master drawing The preferred conductor thickness units is metric. Merix Corp 3. yet figure 3-18 does. Copper Cap –Minimum Thickness Remove the word Absolute.2. The tables will incorporate the designators from IPC-4562 in addition to the oz. In IPC-6012. without requiring an AABUS.9 T Delete ‘Alternate techniques shall be AABUS.1 T Joey Rios.6. Class 3 Minimum Thickness – 12um [472 uin] This is minimum copper thickness for blind and buried via in 3. Not Accepted .2.11. 13 . R Randy Reed. Accepted with modification – restored original text from IPC-6012B w/AM1. Accepted with modification– IPC should request that the IPC-2221 design group take the effort of requiring the thickness to be specified in micrometers. Scott TTM Bryan.7.6. (microvia bottom land) shall be in accordance with Class 3. 120” Present allowance does not all electroless Cu pre-plate etch processes – some intent of the Task Group to tailor this table to meet process call for 0. Revise to lower surface plate requirements to not conflict with Present wording allows for a conflict when Not Accepted – this needs wrap requirements. Joe Schmidt.543 µin]. The Table holds the plus side to 50um.6. everyone’s process. during the final microsection evaluation layers 2 & 29 are not external layers but they are also should not just be evaluated to the minimum copper foil thickness requirement in Table 3-11.0.2. new Table patterned after Table 3-12.” 30um number is also confusing when the dielectrics below 90 µm rest of the note refers to a 25um minimum. Not Accepted . fill material within the blind via shall meet the dimple/bump requirements of Table 3-10. The foils should be used with consideration so as not to cause breakdown between layers. as to how thick the new Table patterned after conductor thickness shall be because the current Table 3-12.076 mm disagrees with the table. Please use larger font for the words and thicker lines for the Help a blind man see Accepted measurement locations. Accepted with modification: Fill material within the blind via shall be planar with the surface within +/. same. When cap plating is specified.. low copper foils should be be specified) and is providing information –first sentence revised to say: “Low profile copper used and the voltages employed should be taken into that is more appropriate in IPC-2221.6. 3.Commentor Paragraph/ Figure/ Table Type of comment (Technical/ Editorial) Recommendation Reason for Recommendation IPC Committee Disposition on each comment submitted (Accepted/Not Accepted/Withdrawn) Scott Bowles.not the Revise process allowance to 0. 3. dimple/bump requirements of Table 3-10.003 in] unless otherwise specified. layers 2 & 29 with buried vias in a 30 amendment that involves a layer design. Should probably also add a Note 5 under Table 312 explaining how to evaluate internal plated layers.” Remove term “External” for table title Restate as: Fill material within the blind via shall meet the The +/-. Suggest using table instead of calling requirement out twice. Table 3-12 Hallmark Circuits T Table 3-12 Jim Monarchio/TTM Table 3-12 Jim Monarchio/TTM Randy Reed. Thus making surface plate and wrap the filled non-capped vias and thru holes to be deferred to a future amendment that involves a terminate on the same layer. however. revision – this needs to be deferred to a future e.076 mm [0.g. [3.080” of Cu removal. Delete first sentence of note “Minimum dielectric spacing may Sentence conveys no requirements (may Accepted with modification be specified to be 30 um. Figure 3-24 Merix Corp Joe Schmidt.2.15 Raytheon T T E T Not Accepted for this There is confusion in the industry regarding plated layers for buried vias.16 Raytheon T 14 . 5. This – see comment above to 3.6. The AABUS statement for the 3. Reproduction of the old (now obsolete) requirements here is redundant Accepted No tolerance given .10.10 series is in 3. section is in conflict with the table.2. – now reads “Unless otherwise specified by the procurement documentation. Table 3-10 defines the dimple and Accepted with modification protrusion according to class.8.10.7 T Add tolerance to voltage – suggest +15 / .2. Merix Corp Randy Reed. 3.8. Other methods of determining CTE for cores or reinforcement to constrain planar movement of the PB shall be AABUS.10 series is in 3.10 series is in 3.10.10. Alternatively.10.8.2. The AABUS statement for the 3. dimensional measurements from a micro-section utilizing a special test coupon may be used to calculate and verify impedance values in accordance with IPC-2251. Delete the last sentence.10 series Accepted with modification is in 3. 3. 3.2.0.10. For large impedance tolerances. The AABUS statement for the 3. Delete ‘When specified’ in the first sentence. 15 . Merix Corp Randy Reed. The AABUS could be extended to include CTE measurements for laminate material because this is the only CTE statement in IPC-6012.2 regarding default test voltage in Table 1-2 Alan Exley.10. The AABUS statement for the 3.8.10.10.1 E Delete the first sentence. Merix Corp 3.11. sentence.2 Raytheon T Alan Exley.16 T Delete the first sentence. use 500 VDC min Impedance Testing.8. Accepted IPC-9252 now specifies the requirements for electrical test of PB’s.10. Delete the last sentence. Test coupons or production PBs shall be tested per IPC-TM-650.8 3. the repairs shall be in accordance with IPC-7711/21” The AABUS statement for the 3. Merix Corp Alan Exley. Raytheon Randy Reed. The 75% fill is in agreement with Class Accepted with modification 3/A.10 3.1 3.5.10.3 Raytheon Randy Reed. The micro-section technique makes dimensional measurements. The AABUS statement for the 3.2.10 series Withdrawn is in 3. Wendi (ddi) Boger 3.1 and 3. Merix Corp 3.11 3.6.11.6. Add clarifying statement to 3.6 Merix Corp T T Randy Reed. Fill material in a blind via with an aspect ratio greater than 1:1 shall be 75% fill for Class 2 and Class 3.11.16 from Raytheon. Add “No repairs are allowed for Class 3 PB’s” Repairs shall be in accordance with IPC-771/21.10.10 series is in 3.7.10 series Accepted with modification is in 3.11 E E E E T E Delete ‘When specified’ in the first sentence.clarification The AABUS statement for the 3. – agreed to 60% along with the new wording on The aspect ratio is required so this planarity in the second requirement does not apply to microvias.10. Merix Corp 3.16 (T) Fill material with in the blind via should be planar with surface in accordance with table 3-10 Delete 3. Clarification to match mil requirements Not Accepted Randy Reed. Merix Corp Randy Reed.2 3.2. Accepted Accepted Accepted Accepted Not Accepted – Class 3/A provides this requirement Randy Reed.Commentor Paragraph/ Figure/ Table Type of comment (Technical/ Editorial) Recommendation Reason for Recommendation IPC Committee Disposition on each comment submitted (Accepted/Not Accepted/Withdrawn) Randy Reed. Method 2. Merix Corp 3. 11. 4. /24. The task group agreed this should be deferred to future discussions of any potential IPC-601 Qual Program. Elaine Brown. (rerouting for noise and ground). --The artwork can change after CAD net list.1. It should be part of the design/procurement requirements. did not paginate to 2 lines for Construction Accepted integrity Types 4.1 Merix Corp E T Accepted – Document will reference ASQH1331.1 “GENERAL” requiring fabricator to “receive” a CAD 3.”ELECTRICAL REQUIRMENTS” (4. instead of an individual slash sheet.6.each type of material example. production sample or test coupons that are produced by the same equipment and procedures planned for the production PBs. For “.1 does not support a “requirement”). Update “ASQ H0862” to active specification ASQ H0862 has been inactivated Not Accepted.LMSI 4. 3) 4. Merix Corp Table 4-1 E Two sets of coupons of the most complex pattern of each type Testing should be based on a group of Accepted with modification – will use the following: of material (for example GFN) processed during the inspection slash sheets with similar properties ….8. Requiring qualification to consist of tests in Table 4-3 and Table 4-4 is a major change. 16 .1 T Reword section as follows: Qualification shall be in accordance with IPC-6011 and should consist of capability analysis assessments in accordance with IPC-9151. Deviations to these Qualification requirements or the allowance of different methodologies shall be AABUS. Randy Reed.Commentor Paragraph/ Figure/ Table Type of comment (Technical/ Editorial) Recommendation Reason for Recommendation IPC Committee Disposition on each comment submitted (Accepted/Not Accepted/Withdrawn) Cliff Maddox.1 Boeing E T Delete reference to “FLEXIBLE PB” from text 6012 does not cover flexible PBs Accepted Accepted Delete “QUALITY ASSURANCE PROVISIONS” paragraph 1) Electrical test data is NOT covered in under 4..2.1 2nd Paragraph R Accepted and OBE – 2nd paragraph removed per previous comment Dewey Whittaker. and /98 have (primary resin system and similar material properties and 1 submit primary reinforcement) for testing should be required. Cliff Maddox. processed…” Design req. --If a customer wants class 3 and doesn’t provide a net list. Honeywell Aerospace 4. netlist in order to certify product as Class 3 compliant. it shouldn’t be the fabricator that is required to police that. 4. /97.1 conflicts with 9252A The test should be able to be done with a net list generated from the artwork data received from the customer with software that can interface with the tester and compared to a CAD Designed net list if it is received.1 Boeing Randy Reed.1 Boeing Cliff Maddox. 2) Requirements for electrical test source data are now well covered in IPC-9252A. 4. preproduction samples.3. --A net list can meet all the requirements of IPC-D-356 but can be interpreted differently by different test software packages. /21. Qualification shall include those applicable tests as referenced in Table 4-3 and Table 4-4. 3. Annular ring and break-out (internal): Change requirement to Need a location in the document that Accepted with modification Per panel. – Staff to place dashes in the PB column where coupons are used instead. The test Impedance need to be is a separate box.Commentor Paragraph/ Figure/ Table Type of comment (Technical/ Editorial) Recommendation Reason for Recommendation IPC Committee Disposition on each comment submitted (Accepted/Not Accepted/Withdrawn) Randy Reed. H2. B3.I.A. per hole type” to “Per inspected for registration. A user can draw the conclusion that impedance testing is done on the production PB. as this is already being addressed by Note 3 in Table 4-3. Table 4-3 Raytheon E Cliff Boein T Maddox. requires registration evaluation. A and 2B) are necessary.BN. The format is not apparent where Note 3 applies. Table 4-3 Raytheon Annular ring and Breakout (Internal) Joe Schmidt. panel corners. Merix Corp Table 4-1 T Environmenta l The test Cleanliness needs to be in a separate box. and H3 and that Note 3 does not apply. one each from opposing instructions for using “A” and “B” coupons and “B” coupons are used. etc. Panel”.5:1 per Note 3 in Table 3-3 (unless committee deletes this required here as a result. per hole type insures that blind. Randy Reed. In addition. Accepted . note as requested above) Clarify sample frequency to specify that two “A” and “B” Latest Table 4-3 text has dropped Accepted with modification – will read: If individual “A” coupon shall be used per panel.35mm and aspect ration comment – no change >3. OBE – column format fix made. one oriented in the “X”.I.3 Annular ring and Breakout (Internal) The format is not apparent that impedance testing is done on H1. Note 5 has been appended to include the following text: “A minimum of one thermally stressed coupon representing via structures B2. 17 . Merix Corp Table 4-1 T Special Requirements T Joe Schmidt.. buried and microvias – the task group agreed to change all instances of “Per will be sectioned in two locations and Panel. with the two B coupons taken from opposite corners of the panel and in opposing axes (one in the ‘‘x’’ axis and the other in the ‘‘y’’ axis). A user can draw the conclusion that Thermal Shock and MIR testing is done on the production PB. – Staff to place dashes in the PB column where coupons are used instead. Table 4.” Accepted – Note 3 in Table Add for the Buried and Blind via Plating Thickness the 25 um Incomplete requirement call-out. the second oriented in a minimum of 3 coupons (1 the “Y” direction. A. 3-3 removed per previous on via diameter less than or equal to .. Add a new note number for the statement “The A coupon design will not always reflect the tightest design annular ring resulting in not providing sufficient annular ring assessment. Add new note number to Annular Ring and Breakout (Internal) inspection. Therefore the requirement is “B or A/B”. The task group does not want an “A” coupon. Merix Corp Randy Reed.Commentor Paragraph/ Figure/ Table Type of comment (Technical/ Editorial) Recommendation Reason for Recommendation IPC Committee Disposition on each comment submitted (Accepted/Not Accepted/Withdrawn) Randy Reed. Accepted Accepted 18 . E Test Frequency column. This portion of Note 3 does not apply to all inspections under the ‘Structural Integrity After Thermal Stress Types 3-6’ header. Note 2 Table 4-3 Note 3 E Remarks column. Merix Corp Table 4-3 Electrical. change ‘Per Board’ to ‘Per PB’. Merix Corp Randy Reed. Be consistent. Merix Corp Randy Reed. Accepted E Remarks column. in cases where the A/B coupon design is not being used. Accepted T T Measurement location must be 30% larger than collimated source. Component hole sampling is required.The issue of distinction for PTH failures between innerlayer separation and barrel failures among A and B coupons are not present in double-sided boards where aspect ratios do not differ greatly. Not Accepted . delete second instance of the word ‘Per’ This specification is a ‘NO KITTY’ zone. Merix Corp Table 4-3 T Structural Integrity After Stress Type 2 Segment A was deleted from the Test coupon column. Randy Reed. Merix Corp Randy Reed. as opposed to providing an option for an A or a B. Isolation Resistance Table 4-3 Special Requirements Table 4-3. Update per IPC-4552 subcommittee recommendations. These requirements shall be AABUS’ Be consistent Accepted with modification – “PB” to be replaced by “printed board” in entirety of document. Isolation Resistance Table 4-3 Electrical. to be used for plating and coating thickness evaluation. the smallest holes do need to be addressed and therefore the decision is to require a B coupon. representing the largest hole. However. ” The wording change to this note is Accepted with modification misleading. – Note 5 to include the following “A minimum of Clarify the opposite corner sampling does one thermally stressed not apply to Segment B patterns coupon representing via structures B2.1 are requirements for Space and not to cherry pick Military Avionics.” Add sampling plan to Appendix A or incorporate into Table 4-3 Presently no sampling plan addresses 3A Accepted – new column for test frequency to be incorporated Not Accepted – group Add additional text.g. Keep terms used consistent in Accepted specification. Merix Corp Joe Schmidt. If individual “A” and “B” coupons are used. Raytheon/Phil Henault Raytheon Table 4-3 Note 8 Table 4-3 New Note 9 E T Jim Monarchio/TTM Appendix A T Scott Bowles.A. Add the following foot note 9 and tag the title of the two Hole type is used as a criteria but is not Accepted with modification Note 3 to append the structural integrity sections. Merix Corp Randy Reed. 2A or 2B) are necessary. representing the blind/buried via patterns. etc. requires registration evaluation. B3.3 Annular ring and Breakout with the use of A/B style coupons. Restate as: For through hole constructions.Commentor Paragraph/ Figure/ Table Type of comment (Technical/ Editorial) Recommendation Reason for Recommendation IPC Committee Disposition on each comment submitted (Accepted/Not Accepted/Withdrawn) Randy Reed. that these are options that various end but to conform to all users require and all are not required.) and plating steps define a via structure. but both coupons must represent the worst case annular ring condition.. Unique construction (blind. They do not understand requirements from this table use applications.g. filled through-hole.1 that are required for end. a minimum of 2 coupons is necessary. each coupon from opposite panel corners and opposing axes. If A/B style coupons are used. unfilled throughprecedent already (Phil Henault) hole. I like following: Unique unfilled through hole. T Change last sentence.1 Hallmark Circuits T&E For each manufacturing panel when utilizing the A and B design. e. each coupon segment from opposite corners of the panel and in opposing axes. A. one in the “x” axis. filled through hole) and plating steps “Via Structure” better than “Hole Type” but construction (e. …. etc.1. It associates requirements to – see previous committee use coupons from panel extremes and disposition to comment from evaluation in “x” and “y” directions ONLY Cliff Maddox on Table 4.BN. This phrasing is Accepted discontinued in other portions of the specification. (Internal) 19 . T Randy Reed. thinking that everything listed in Table discussion at IPC Midwest 2009 showed the intent is to select the options from Table A.. Table Note 5 4-3. a minimum of 2 coupons ( 1 A and 1B. blind. 2 A segments and 2 segments per panel. defined. a minimum of 2 coupons per panel are to be evaluated. Micro-sectioning for PTH evaluations not required …. This inspection does not apply to the segment B patterns representing the buried and blind vias. the document seems to have set the define a hole type. Lance Raytheon Auer. for a total of 4 coupons.. buried. Merix Corp Table 4-3 Note 4 Table 4-3 Note 5 E For Class 2 product.. buried. Note: It is not the intent for We have customers that just specify Class procurement documentation to just state Class 3/A but rather 3/A. Clarify the sample plan for those using the Accepted with modification A and B coupons permitted in Table 4-3. (Joe Schmidt) To be honest. the other in the “y” axis. requirements in this table for Class 3/A product Delete the word ‘end’. DWV. Accepted with modification – Class 3/A requirements removed from Table A. Merix Corp Appendix 3A E Appendix A Solderability Surface Appendix A T Use the procurement documentation to control the special Class 3A has made mandatory Accepted with modification – new columns for test testing (acceptance testing) the Special testing frequency and “Remarks” to requirements of class 3.Please add a note and state Clarity requirement in a complete sentence for clarity. and MIR Appendix A. E Rework Simulation.Please confirm all panels are Clarity required to be submitted for this test for each lot. Clarify how to do the assessment.1 as they do differentiate from Class 3 requirements 20 . Merix Corp Randy Reed. Randy Reed. and Plating Voids seem to conflict. Accepted – IPC staff to Match the reference paragraphs to rev C The reference paragraphs are still to update paragraph Revision B.1 as they do differentiate from Class 3 requirements Within “Remark” Column . Conformance per Coupon or Per Board column is blank. fungus resistance or thermal shock-.LMSI Randy Reed. DWV. Merix Corp Appendix A Appendix A T T Please add a note stating the protocol for the table where the Inspection/Test Method column is blank. Bond Strength. Merix Corp Randy Reed. references Steam age test no longer referenced in J-STD-003 Please alternate source for test method. Accepted – new columns for test frequency and “Remarks” to be added to Table A. this requires be added to Table A. Remarks for Structural Integrity before Thermal Stress. Clarify whether Plating void sample plan takes precedence because the sample plan is more stringent. and MIR Within “Remark” Column .Commentor Paragraph/ Figure/ Table Type of comment (Technical/ Editorial) Recommendation Reason for Recommendation IPC Committee Disposition on each comment submitted (Accepted/Not Accepted/Withdrawn) Elaine Brown. Accepted T Please add a note stating the protocol for the table where the Clarify sample location.but there are more). Merix Corp Appendix A. Accepted with modification – Class 3/A requirements removed from Table A. Bond Strength. T Rework Simulation. (for example.1 Accepted Accepted Randy Reed. Merix Corp Randy Reed.1 testing that is usually required annual or once. Structural Integrity after Thermal Stress. into being required on a panel of even an individual piece basis.LMSI Appendix 3A T Elaine Brown. A group of volunteers should proof this section after all Accepted – IPC Staff Action comments are dispositioned. Change to say: "60% fill for laminating no fill requirements for blind vias requirements for buried and resin or similar filling material for Class 2 and 3 buried vias. 21 . What is the sampling frequency Clarity Resistance and Organic for this AABUS? Contamination removed Thermal Shock Outgassing from Table A. Merix Corp Appendix B E Accepted (Fungus This is a special requirement. prior to ballot. blind approved.1) Organic Contamination Fungus Resistance Material Fill of Blind and Buried Vias: Move to correct Paragraph is in error stating that there are Accepted with modification – separate Class 3/A alphabetic location.Commentor Paragraph/ Figure/ Table Type of comment (Technical/ Editorial) Recommendation Reason for Recommendation IPC Committee Disposition on each comment submitted (Accepted/Not Accepted/Withdrawn) Randy Reed. Appendix B Raytheon T Randy Reed. Merix Corp Appendix A T Joe Schmidt. following completion of Final Draft comment Review (following all changes made to IPC6012C). Sampling Dimple and Bump requirements per Table 3-7. frequency approved.