I nternational J ournal of Engineering Trends and Technology (I J ETT) – Volume 4 I ssue 9- Sep 2013ISSN: 2231-5381 http://www.ijettjournal.org Page 3899 Implementation of Multitrack Simulator in FPGA for ESM Processor K Pradeep Kumar #1 , A Sreedevi *2 #1 M. Tech Student & Department of ECE & JNTU- HYD H:NO: 1-75/7/5, Brundavan Colony, Boduppal, Hyderabad, A.P, India *2 Manager & Development and Engineering & BEL- HYD Abstract— ESM (Electronics support measure) systems intercept radar emissions which are within the operating frequency range of the system. ESM System consists of Antennas, Front End Receiver, Receiver subsystem, Processor subsystem and Display subsystem. Antennas intercepts the RF signals which are given to Front end receiver. The Front End Receiver gives amplified RF and detected video outputs. Amplified RF output is given to DIFM unit which measures the frequency. Video output of Front End Receiver is connected to the receiver subsystem. The receiver subsystem measures the parameters such as Pulse width, Pulse repetition frequency and Amplitude of the on pulse by pulse basis. It also timestamps the received signal by generating the time of arrival(TOA) parameter. The measured frequency from DIFM Receiver is also routed to receiver subsystem. The above mentioned measured parameters are interleaved into 128 bit word called Pulse descriptor word (PDW). This project Pulse Descriptor Word Simulator aims at developing a simulator which can be used to test the processor in the absence of Receiver hardware. This simulates the 128 bit PD Word along with the required control signals which will be generated by the receiver card ESM Processor. The 128 bit PD Word is organized as four 32 bit words. Two address bits are used to indicate the word address. A strobe is to be provided to indicate the presence of each word. The simulator is being planned to be developed using Xilinx ISE 10.1 and the simulated results are to be demonstrated on modelsim simulator. Key Words -- Electronic Support Measure, Parameters of signals, Pulse Descriptor Word. I. INTRODUCTION In military telecommunications, the terms Electronic Support (ES) or Electronic Support Measures (ESM) describe the division of electronic warfare involving actions taken under direct control of an operational commander to identify, intercept, detect, record, locate, and/or analyze sources of radiated electromagnetic signals for the purposes of immediate threat recognition or longer-term operational planning. Thus, Electronic Support Measure provides a source of information required for decisions involving Electronic Protection (EP), Electronic Attack (EA), avoidance, targeting, and other types of forces. Electronic Support data can be used to produce signals intelligence (SIGINT), communication intelligence (COMINT) and electronics intelligence (ELINT). Electronic support measures gather intelligence through passive "listening" to electromagnetic radiations of military interest. It can provide initial detection or knowledge of foreign systems, a library of technical and operational data on foreign systems, and tactical combat information utilizing this library. It contains a collection platforms that can remain electronically silent and detect and analyze RADAR transmissions beyond the RADAR detection range because of the greater power of the transmitted electromagnetic pulse with respect to a reflected echo of that pulse. US airborne Electronic Support Measure receivers are designated in the AN/ALR series. Desirable characteristics for electromagnetic surveillance and collection equipment include wide-spectrum or bandwidth capability because foreign frequencies are initially unknown, wide dynamic range because signal strength is initially unknown, narrow band pass to discriminate the signal of interest from other electromagnetic radiation on nearby frequencies, and good angle-of arrival measurement for bearings to locate the transmission of signals. The frequency spectrum ranges from 30 MHz to 50 GHz. Multiple receivers are typically required for surveillance of the entire spectrum. But in the case of tactical receivers, it may be functional within a specific signal strength threshold of a smaller frequency range. II. ESM PROCESSOR Uses of ESM Processor Intercept , identify , locate , record and/or analyze sources of radiated electromagnetic energy for the purposes of immediate threat recognition (such as warning that fire control I nternational J ournal of Engineering Trends and Technology (I J ETT) – Volume 4 I ssue 9- Sep 2013 ISSN: 2231-5381 http://www.ijettjournal.org Page 3900 RADAR has locked on a combat vehicle , ship , or aircraft) or longer-term operational planning. III. BLOCK DIAGRAM A. Blocks used for generation of signals The main blocks are 8254Timer, 36-bit free running counter, different types of memories, latches, MUX, 32-bit PD word, PD word control bits. B. 8254 Timer i. Block Diagram ii. 8254 PROGRAMMABLE INTERVAL TIMER Easy to use with All Intel and Most Other Microprocessors Handles Inputs from DC to o 8 MHz 8254 o 10 MHz 8254-2 Status Read-Back Command Six Programmable Counter Modes Three Independent 16-Bit Counters Binary or BCD Counting C. Modes of 8254 timer Mode 0 – Interrupt on terminal count Mode 1 -- Hardware Re-Trigger able one-shot Mode 2 – Rate Generator Mode 3 -- Square wave mode Mode 4 -- Software triggered strobe Mode 5 – Hardware triggered(Re-triggerable) strobe In this project we go with the Mode 2, as it is a real time clock interrupt and Counter 0. D. Control word format SELECT COUNTER SC0 SC1 0 0 Select counter 0 0 1 Select counter 1 1 0 Select counter 2 1 1 Read- Back command READ/ WRITE RW1 RW2 0 0 Counter Latch Command 0 1 Read/Write least significant byte only I nternational J ournal of Engineering Trends and Technology (I J ETT) – Volume 4 I ssue 9- Sep 2013 ISSN: 2231-5381 http://www.ijettjournal.org Page 3901 READ/ WRITE RW1 RW2 1 0 Read or Write most significant byte only 1 1 Read/Write least significant byte first and then most significant byte BCD 0 Binary Counter 16-bits 1 Binary Coded Decimal (BCD) Counter (4 Decades) MODE M2 M1 MO MODE 0 0 0 0 MODE 1 0 0 1 MODE 2 X 1 0 MODE 3 X 1 1 MODE 4 1 0 0 MODE 5 1 0 1 IV. PROGRAMMING The VHDL code for 8254 timer and checked out in Xilinx software for errors. After checking the syntax of the program, we go for test bench wave form of 8254 timer. The total components of the timer are checked in the same process. The main components are 16-bit down counter and counter control operations which are used in our project for selecting modes and counter. The VHDL is also written for 36-bit free running counter and Pulse Descriptor bits. In the main module of the code all the components (8254 timer, 36-bit free running counter, Pulse Descriptor bits) are added, and checked out for syntax errors. After checking out the syntax errors, write the test bench for the program in simulation model, and check out the wave form in Modelsim. The total program is dumped on to the FPGA kit with the help of Chipscope tool. In our Project we go with FPGA Virtex-5. The FPGA kit after the programs are dumped , it is inserted into the ESM processor. By using Ethernet, the signals are given to the processor for detection. V. FPGA VIRTEX-5 The Virtex-5 family provides the newest most powerful features in the FPGA market. Using the second generation Advanced Silicon Modular Block column-based architecture, the Virtex-5 family consists of five distinct platforms (sub- families), the most useful choice offered by any FPGA family. Each platform contains a different range of features to address the needs of a wide variety of advanced logic designs. Virtex-5 FPGA Features: Five platforms - LX: High-performance general logic applications - LXT: High-performance logic with advanced serial connectivity - SXT: High-performance signal processing applications with advanced serial connectivity - TXT: High-performance systems with double density advanced serial connectivity - FXT: High-performance embedded systems with advanced serial connectivity Cross-platform compatibility High-performance Most advanced, optimal-utilization Powerful clock management tile (CMT) clocking 36-Kbit block RAM/FIFOs Parallel SelectIO technology with high-performance Advanced DSP48E slices Flexible configuration options Monitoring capability on all devices PCI Express Designs with integrated Endpoint blocks Tri-mode 10/100/1000 Mb/s to Ethernet MACs PowerPC 440 Microprocessors 65-nm copper CMOS process technology 1.0V core voltage Flip-chip packaging with high signal-integrity available in standard or Pb-free package options I nternational J ournal of Engineering Trends and Technology (I J ETT) – Volume 4 I ssue 9- Sep 2013 ISSN: 2231-5381 http://www.ijettjournal.org Page 3902 VI. EXPECTED RESULTS I nternational J ournal of Engineering Trends and Technology (I J ETT) – Volume 4 I ssue 9- Sep 2013 ISSN: 2231-5381 http://www.ijettjournal.org Page 3903 REFERENCES [1] Craig A. Hanna, "The Associative Comparator: Adds New Capabilities to ESM Signal Processing” [2] A.G. Kellet, "SADIE - A High Performance ESM Signal Processor" [3] Colloqutim on Signal Processing for ESM Systems, April 1988, London UK. [4] Stephen C. Smith and Michael P. Beakes, "The Pulse Sort Module: VLSI Technology inthe ESM System," IBM Technical Directions, Vol. 13 No. 1 1987, IBM Federal Systems Division, Owego, NY. pp. 37-42. [5] R.S. Andrews, "ESM Processing Using 3-Dimensional Memory Mapping and Adaptive Pattern Formation Algorithms," Conference Proceedings - Military Microwaves '84, Oct 1984, London England, pp. 27-36. [6] P. Hollands, M.A., "Us:e of Simulation Methods as a Design Tool in the Development of an ESM Processing System," !"-E Procs, Vol. 132, Pt F, No. 4, July 1985, pp. 292-297. [7] J.B.G. Roberts, P. Simpson, B.C. Merrifield, and J.F. Cross, "Signal Processing [8] Applications of a Distributed Array Processor," lEE Proceedings, Vol. 131, Pt F, No. 6, October1984, pp. 603-609. [9] B.C. Merrifield, J.B.G. Roberts, P. Simpson, A. Stanley, "Real Time Applications of DAP," ICS 88, International Conference on Supercomputing Proceedings, Supercomputing '88,pp. 54-62, May 1988, Boston MA. [10] R.D. Beton, S.P. Turner, C. Upstill, "Hybrid Architecture Paradigms in a Radar ESM Data P'rocessing Application," Microprocessors and Microsystems, Vol 13 No. 3, April 1989, pp. 160-164. [11] S. Cussons, J. Roe, and A. Felthamn,"Knowledge Based Signal Processing for Radar ESM Systems," ESM Division, Admiralty Research Establishment, Portsdown, Cosham., Hants. [12] P.L. Danielsen, D.A. Agg, N.R. Burke, Smith Associates Limited, Guildford, UK; "The Apllication of Pattern Recognition Techniques tc ESM Data Processing," Conference Title: IEE Colloquium on 'Signal Processing for ESM Systems' Digest No. 1988/62 p.6/1-4, Conference Date: 26 Apr 1988, Conference Loc: London, UK.
Report "Implementation of Multitrack Simulator in FPGA for ESM Processor"