www.gatehelp.com IES Electrical Engineering Topic wise Questions Microprocessor YEAR 2008 MCQ 1 Three devices P, Q and R have to be connected to an 8085 microprocessor. Device P has the highest priority and device R has the lowest priority. L 1 this context, which of the following is the correct assignment of interrupt inputs ? (A) P uses TRAP, Q uses RST 5.5 and R uses RST 6.5 (B) P uses RST 5.5, Q uses RST 6.5 and R uses RST 7.5 (C) P uses RST 7.5, Q uses RST 6.5 and R uses RST 5.5 (D) P uses RST 5.5, Q uses RST 6.5 and R uses TRAP MCQ 2 The content of the Program Counter of an intel 8085 A microprocessor specifies which one of the following ? (A) The address of the instruction being executed (B) The address of the instruction executed earlier (C) The address of the next instruction to be executed (D) The number of instructions executed so far MCQ 3 Both the ALU and control section of CPU employ which special purpose storage locations ? (A) Buffers IES EE Topic wise 2001-2008 Microprocessor www.gatehelp.com (B) Decoders (C) Accumulators (D) Registers MCQ 4 In an Intel 8085 A, what is the content of the Instruction Register (IR) ? (A) Op-code for the instruction being executed (B) Operand for the instruction being executed (C) Op-code for the instruction to be executed next (D) Operand for the instruction to be executed next MCQ 5 In an Intel 8085 A microprocessor, why is READY signal used ? (A) To indicate to user that the microprocessor is working and is ready for use (B) To provide proper WAIT states when the microprocessor is communicating with a slow peripheral device (C) To slow down a fast peripheral device so as to communicate at the microprocessor’s device (D) None of the above MCQ 6 In an Intel 8085 A, which is always the first machine cycle of an instruction ? (A) An op-code fetch cycle (B) A memory read cycle (C) A memory write cycle (D) An I/O read cycle MCQ 7 The addressing mode used in the instruction JMP F 347 H in case of an Intel 8085 A microprocessor is which one of the following ? (A) Direct (B) Register-indirect Page 2 www.gatehelp.com (C) Implicit (D) Immediate MCQ 8 IES EE Topic wise 2001-2008 Microprocessor What is the number of machine cycles in the instruction LDA 2000 H that consists of thirteen states ? (A) 2 (B) 3 (C) 4 (D) 5 MCQ 9 Match List I (Feature of instruction) with List II (Instruction) and select the correct answer using the code given below the lists : List I A. Maskable interrupt B. Signal C. Instruction D. Memory location 002C H Codes : A (A) (B) (C) (D) 4 2 4 2 B 1 3 3 1 C 2 4 2 4 D 3 1 1 3 List II 1. RST 5.5 2. XTHL 3. SID 4. RST 6.5 MCQ 10 An intel 8085 A microprocessor is operated at a frequency of 2 MHz. If the instruction LXI H, E000 H that takes ten ‘T’ states, is executed, then what is the instruction cycle time ? (A) 10 μs (B) 5 μs (C) 4 μs Page 3 gatehelp. what would be the content of the stack pointer ? (A) ABCD H (B) ABCA H (C) ABC9 H (D) ABC8 H MCQ 13 If the HLT instruction of an Intel 8085 A microprocessor is executed (A) the microprocessor is disconnected from the system bus till the RESET is pressed (B) the microprocessor halts the execution of the program and returns to the monitor (C) the microprocessor enters into a HALT state and the buses are tri-stated (D) the microprocessor reloads the program counter from the locations 0024 H and 0025 H Page 4 .com (D) 2.IES EE Topic wise 2001-2008 Microprocessor www.5 μs MCQ 11 When TRAP interrupt is triggered in an intel 8085 A. the program control is transferred to which one of the following ? (A) 0020 H (B) 0024 H (C) 0028 H (D) 002C H MCQ 12 The stack pointer of an 8085 A microprocessor contains ABCD H. PUSH XTHL PUSH JMP D EC 75 H PSW At the end of the execution of the above instructions. com MCQ 14 IES EE Topic wise 2001-2008 Microprocessor The contents of Program Counter (PC). Page 5 . when the microprocessor is reading from 2FFF H memory location.gatehelp. This number is (A) 2 (B) 3 (C) 4 (D) 5 MCQ 18 Assertion (A) : Each memory cell of a DRAM requires refreshing every 2. will be (A) 2FFE H (B) 2FFF H (C) 3000 H (D) 3001 H MCQ 15 Carry flag is not affected after the execution of (A) ADD B (B) SBB B (C) INR B (D) ORA B MCQ 16 Which one is the indirect addressing mode in the following instructions ? (A) LXIH 2050 H (B) MOV A. B (C) LDAX B (D) LDA 2050 H MCQ 17 An 8254 programmable interval timer consists of independent 16-bit programmable counters.www. 4 or 8 ms or its data will be lost. com Reason (R) : DRAM stores 1s and 0s as charges on a small MOS capacitor which has tendency to leak off charges after a period of time. what is the address of Port C ? (A) F C (B) F D (C) F B (D) F E MCQ 21 The power failure alarm must be connected to which one of the following interrupt of 8085 ? (A) RST 7.IES EE Topic wise 2001-2008 Microprocessor www.5 (B) TRAP (C) INTR (D) HOLD MCQ 22 Page 6 . what is the address of port A ? (A) 80 (B) F A (C) F B (D) F C MCQ 20 If 8255 A chip is selected when A 2 to A 7 pins are 1.gatehelp. (A) Both A and R are true and R is the correct explanation of A (B) Both A and R are true but R is not the correct explanation of A (C) A is true but R is false (D) A is false but R is true YEAR 2007 MCQ 19 If 8255 A chip is selected when A 2 to A 7 bits are all 1. 0 and 1 respectively Page 7 . Auxiliary Carry and Zero flag set to 0. Auxiliary Carry and Zero flag set to 0. 91H XRI 91H Which one of the following is correct ? (A) Content of accumulator is 00H. respectively (C) Content of accumulator is 00H.com The cycle required to fetch and execute an instruction in a 8085 microprocessor is which one of the following ? (A) Clock cycle (B) Memory cycle (C) Machine cycle (D) Instruction cycle MCQ 23 IES EE Topic wise 2001-2008 Microprocessor Which one of the following statements corresponding to execution of SIM instructions is not correct ? (A) It will selectively mark all the interrupts of 8085 (B) Contents of bit (b 7) are copies on SOD pin only if bit b 6 in acc is ‘1’ (C) RST 7. 1 and 0. Carry. Carry Auxiliary Carry and Zero flag set to 0. called ? (A) Mnemonics (B) Directives (C) Identifiers (D) Operands MCQ 25 On execution of the following segment of instructions in sequence MVI A.5 can reset without executing ISR for RST 7.www.5 (D) It can handle interrupts and serial I/O MCQ 24 What are the sets of commands in a program which are not translated into machine instructions during assembly process. Carry. respectively (B) Content of accumulator is 91H.gatehelp. 0 and 1. 1 and 0 respectively MCQ 26 Read the following Assembly Language Program Segment of 8085 Microprocessor : LXI MOV ORI MOV MOV ANI MOV HLT What are the contents of A. L FOH L. 05 and 01. respectively (B) Contents of A.5 interrupt (D) Resets RST 7. respectively (C) Contents of A. Carry Auxiliary Carry and Zero flat set to 0. H FOH H.gatehelp. A A. 25 and 01. H and L registers are 25. 10 and F1. 2501 H A. A Read the following Assembly Language Program Segment of 8085 : EI RIM ANI 80 H SIM What kind of task is performed by above set of instructions ? (A) Sends bit out on SOD pin (B) Accepts bit in from SID pin (C) Accepts RST 7.5 interrupt Page 8 .com (D) Content of accumulator is 91H. H and L registers after executing the above set of instructions in sequence ? (A) Contents of A. respectively (D) Contents of A. 20 and F1. respectively MCQ 27 H. H and L registers are 05. H and L registers are 25.IES EE Topic wise 2001-2008 Microprocessor www. H and L registers are 10. What is the size of this memory system ? (A) 512 # 2 bits (B) 256 # 4 bits (C) 64 # 16 bits (D) 32 # 32 bits MCQ 30 Assertion (A) : A subroutine is a program written separately from the main program to perform a function that occurs repeatedly in the main program.www. Reason (R) : Many applications in real word produce signal analog in nature.com MCQ 28 IES EE Topic wise 2001-2008 Microprocessor Which one of the following statements does not describe property/ characteristic of a stack pointer-register in 8085 microprocessor ? (A) It points to top of the stack (B) It is UP/DOWN counter (C) It is automatically initialized to 0000H on power-on (D) It is a 16-bit register MCQ 29 Eight memory chips of 32 # 4 bit size have their address buses connected together. (A) Both A and R are true and R is the correct explanation of A (B) Both A and R are true but R is not the correct explanation of A (C) A is true but R is false (D) A is false but R is true MCQ 31 Assertion (A) : Analog to digital converters are used to interface microprocessor to analog signals.gatehelp. Reason (R) : A subroutine can be called by a CALL instruction. (A) Both A and R are true and R is the correct explanation of A (B) Both A and R are true but R is not the correct explanation of A (C) A is true but R is false (D) A is false but R is true Page 9 . 5 (B) RST 7 (C) RST 6. 2. ROMs are used in μC security systems.5 (B) RST 7 (C) RST 6. 2 and 3 (B) 1 and 2 (C) 2 and 3 (D) 1 and 3 MCQ 33 Which interrupt has the highest priority ? (A) RST 7.IES EE Topic wise 2001-2008 Microprocessor www.5 (D) INTR YEAR 2006 Page 10 .gatehelp. ROMs are volatile memories. 3.com MCQ 32 Consider the following statements : 1.5 (D) INTR MCQ 34 The contents of memory location 4 FFFH are 11011011. What of the statements given above are correct ? (A) 1. The memory word could not be interpreted as which one of the following ? (A) 2’s complement number (B) 1’s complement number (C) Octal number (D) BCD number MCQ 35 Which interrupt has the highest priority ? (A) RST 7. The process of entering data is called burning in ROM. 5 C.com MCQ 36 IES EE Topic wise 2001-2008 Microprocessor Consider the following statements : 1. TRAP Codes : A (A) 1 B 3 C 4 D 2 Page 11 List II 1. 2 and 3 (B) 2 and 4 (C) 3 and 4 (D) 1 and 3 MCQ 37 Which one of the following instructions is a 3-byte instruction ? (A) M V I A (B) L D A X B (C) J M P 2050 (D) MOV A. RST 7.5 B. RST 5. With an 8085 microprocessor. 4. Non-vectored . Edge sensitive 3. INTR D. Indirect addressing is not possible for I/O mapped I/O port addresses Pointers cannot be used to access memory mapped I/O addresses Fewer machine instructions can be used with I/O mapped I/O addressing as compared to memory mapped I/O addressing. 2. 3. one can access at the most 512 devices with unique addresses using I/O mapped I/O addressing Which of the statements given above are correct ? (A) 1. M MCQ 38 Match List I (Interrupt) with List II (Property) and select the correct answer using the code given below the lists : List I A. Non-maskable 2.gatehelp. Level sensitive 4.www. IES EE Topic wise 2001-2008 Microprocessor www. respectively (B) Contents of H and L registers are AAH and BBH.gatehelp. 2001 H 2001 H Select the correct answer using the codes given below : (A) Contents of H and L registers are 20 H and 01 H. 2001 H and 2002 H are AAH. respectively MCQ 40 How many times will the following loop be executed ? LXIB LOOP DCX MOV ORA JNZ (A) 10 (B) 100 (C) 16 (D) 15 MCQ 41 0010 H B A. What are the contents of H and L registers after executing the following instructions in sequence ? LXI LHLD H. respectively (D) Contents of H and L registers are CCH and BBH. the DDA instruction is used for (A) Direct Address Accumulator (B) Double Add Accumulator Page 12 . BBH are CCH respectively. B C LOOP Select the correct answer using the code given below : In 8085.com (B) (C) (D) 2 1 2 4 4 3 3 3 4 1 2 1 MCQ 39 The contents of memory locations 2000 H. respectively (C) Contents of H and L registers are BBH and CCH. AC. Codes : (A) Both A and R are true R is the correct explanation of A (B) Both A and R are true but R is NOT the correct explanation of Page 13 . one labelled as Assertion ‘A’ and the other labelled as Reason ‘R’. OV.www. P. CY (B) S. CY (D) S. Which are these five flags ? (A) S. AC. P. 1 MB ROM can be obtained from (A) 16 ICs in a row (B) 16 ICs in a column (C) 8 ICs in a column and 2 ICs in a row (D) None of the above MCQ 44 Which one of the following is the software intercept of 8085 microprocessor ? (A) RST 7. P. OV MCQ 43 Suppose 64 kB. AC. Select your answers to these items using the codes given below.gatehelp. P. Z. CY (C) S. OV. Z. ROM ICs are available in abundance. You are to examine these two statements carefully and decide if the Assertion A and the Reason R are individually true and if so.com (C) Decimal Adjust Accumulator (D) Direct Access Accumulator MCQ 42 IES EE Topic wise 2001-2008 Microprocessor Programme status ward of 8085 microprocessor has five flags. Z.5 (B) RST 7 (C) TRAP (D) INTR Direction : The following item consist of two statements. whether the Reason is a correct explanation of the Assertion. 3. Calculates addresses of data in data-segment Codes : A (A) (B) (C) (D) 2 3 2 3 B 4 1 1 4 C 1 4 4 1 D 3 2 3 2 List II 1. DI 2. TF MCQ 47 Consider the following statements about register indirect addressing : 1. IP 4. Modified during fetch phase B. YEAR 2005 MCQ 46 Match List I with List II and select the correct answer using the correct codes given below the lists : List I A.com A (C) A is true but R is false (D) A is false but R is true MCQ 45 Assertion (A) : Stack is a group of memory locations in RAM used for temporary storage of data Reason (R) : PUSH and POP instructions are used to send and retrieve data from stack. Page 14 It helps in writing code that executes faster It helps in writing compact code It allows reuse of memory CPU data transfer instruction It is essential for stack operations . DS 3. Needed by the DEBUG program D.IES EE Topic wise 2001-2008 Microprocessor www. 2.gatehelp. 4. Holds subscripts of array C. com Which of the statements given above are correct ? (A) 1. 2 and 3 MCQ 48 IES EE Topic wise 2001-2008 Microprocessor Which of the following does not take place when 8085 processor is reset ? (A) 8085 gives reset out signal to reset external hardware (B) 8085 resets program counter to FFFFH (C) The interrupt system is disabled (D) The busses are tristated MCQ 49 Memory chips of four different sizes as below are available : 1. 2 and 4 (C) 2. 3 and 4 (B) 1. 4.gatehelp. 32 k # 4 2. 3. 32 k # 16 8k#8 16 k # 4 All the memory chips as mentioned in the above list are Read/Write memory. What minimal combination of chips or chip alone can map full address space of 8085 microprocessor ? (A) 1 and 2 (B) 1 only (C) 2 only (D) 4 only MCQ 50 A good assembly language programmer should use general purpose registers rather than memory in maximum possible ways for data processing. 3 and 4 (D) 1.www. This is because : (A) Data processing with registers is easier than with memory (B) Data processing with memory requires more instructions in the program than that with registers Page 15 . IES EE Topic wise 2001-2008 Microprocessor www. Which of the following is correct about INR instruction ? (A) Overflow cannot be detected (B) Overflow can be detected (C) If a programme requires overflow to be detected. Now. XRA A. MCQ 53 Which of the following is not correct ? (A) Bus is a group of wires (B) Bootstrap is a technique or device for loading first instruction (C) An instruction is a set of bits that defines a computer operation (D) An interrupt signal is required at the start of every program Page 16 . 2. SUB A. CMP A. ORA A. All are arithmetic and logic instructions All cause the accumulator to be cleared irrespective of its original contents All reset the carry flag All of them are 1-byte instructions Which of the statements given above is/are correct ? (A) 1. 2 and 4 (D) 1. 3 and 4 (B) 2 only (C) 1. ADD instruction should be used instead of INR (D) It can be used to increase the contents of the BC register pair. consider the following statements : 1. 3 and 4 MCQ 52 INR instruction of 8085 does not affect carry flag.com (C) Of limited set of instructions for data processing with memory (D) Data processing with registers takes fewer cycles than that with memory MCQ 51 Consider the following 8085 instructions : ANA A. 2. 4. 3.gatehelp. 2 and 3 MCQ 56 The following sequences of instructions are executed by an 8085 microprocessor : 1000 LXI SP.www. HL = 1003 (B) SP = 27 FD.gatehelp. A total of about one million bytes can be directly addressed by the 8086 microprocessor 8086 has thirteen 16-bit registers 8086 has eight flags Compared to 8086. HL = 1006 Page 17 . 3. 4. 2. 2 and 4 (D) 1. HL = 1003 (C) SP = 27 FF. 3 and 4 (B) 1. 27FF 1003 CALL 1006 1006 POPH What are the contents of the stack pointer (SP) and the HL register pair on completion of execution of these instruction ? (A) SP = 27 FF. 3 and 4 (C) 1. the 80286 provides a higher degree of memory protection. Which one of the statements given above are correct ? (A) 2.com MCQ 54 IES EE Topic wise 2001-2008 Microprocessor The interrupt vector table IVT of 8086 contains (A) The contents of CS and IP of the main program address to which the interrupt has occured (B) The contents of CS and IP of the main program address to which the control has to come back after the service routine (C) The starting CS and IP values of the interrupt service routine (D) The staring address of the IVT MCQ 55 Consider the following statements : 1. gatehelp. 0B H H. ROMs are used for temporary program and data storage 2. HL = 1006 MCQ 57 Consider the program given below. Page 18 Dynamic RAM is less expensive than static RAM MASK ROM is used in high volume microprocessor based system . 3. 1. it : (A) Resets both IF and TF flags (B) Resets all flags (C) Sets both IF and TF (D) Resets the CF and TF MCQ 59 Consider the following statements : In memories.com (D) SP = 27 FD. which transfer a block of data from one place in memory to another : MVI LXI LXI L1 : MOV STAX INR INR DCR JNZ C. M D L E C L1 What is the total number of memory accesses (including instruction fetches) carried out (A) 118 (B) 140 (C) 98 (D) 108 MCQ 58 When an 8086 executes an INT type instruction. 2400 H D. 3400 H A.IES EE Topic wise 2001-2008 Microprocessor www. XTHL D. PCHL B. 2 and 3 IES EE Topic wise 2001-2008 Microprocessor YEAR 2004 MCQ 60 Which one of the following statements is correct ? In Intel 8085. Exchange the contents of HL with those of DE pair 3. SPHL C.www. Transfer the contents of HL to the stack pointer 4. the interrupt enable flip-flop is reset by (A) DI instructions only (B) System RESET only (C) Interrupt acknowledgement only (D) Either DI or system RESET or interrupt acknowledgement MCQ 61 Match List I (Instruction) with List II (Operation) for Intel 8085 and select the correct answer using the codes given below : List I A.com Which of the statements given above is/are correct (A) 1 only (B) 1 and 2 (C) 2 and 3 (D) 1.gatehelp. XCHG Codes : A (A) (B) (C) (D) 3 3 4 4 B 4 4 3 3 C 1 2 2 1 D 2 1 1 2 Page 19 List II 1. Transfer the contents of HL to the programme counter . Exchange the top of the stack with the contents of HL pair 2. BCD addition Codes : A (A) (B) (C) (D) 5 3 5 3 B 4 1 1 4 C 2 5 2 5 D 1 2 4 1 MCQ 63 Which one of the following statements is correct ? (A) ROM is a Read/Write Memory (B) PC points to the last instruction that was executed (C) Stack works on the principle of LIFO (D) All instructions affect the flags MCQ 64 What must be the contents of the control word of Intel 8255 for Mode 0 (operation) and for the following ports configuration : Port A-output. Checking the current interrupt mask setting 5. Port C upper -input ? (A) 85 H (B) 86 H (C) 87 H (D) 88 H Page 20 . DAA D.gatehelp. SPHL List II 1. Serial output data 4. DAD C. Port B-output.com MCQ 62 Match List I (Instruction) with the List II (Application) and select the correct answer using the codes given below : List I A. 16-bit addition 2. Port C lower -Output. Initializing the stack pointer 3. SIM B.IES EE Topic wise 2001-2008 Microprocessor www. 5 List II 1. RST 7.www. Positive edge triggered Page 21 .com MCQ 65 IES EE Topic wise 2001-2008 Microprocessor Which one of the following 8085 assembly language instructions does not affect the contents of the accumulator ? (A) CMA (B) CMPB (C) DAA (D) ADDB MCQ 66 MC 1488 and MC 1489 are needed when using RS 232 for which one of the following ? (A) To convert the logical levels at the receiving and sending ends of RS 232 into TTL compatible levels (B) To convert the TTL level voltage at the sending and receiving ends of RS 232 to ! 12 V level (C) They are not required while using RS 232 (D) To improve the current drive of the RS 232 output signals MCQ 67 Which one of the following statements for Intel 8085 is correct ? (A) Program counter (PC) specifies the address of the instruction last executed (B) PC specifies the address of the instruction being executed (C) PC specifies the address of the instruction to be executed (D) PC specifies the number of instructions executed so far MCQ 68 Match List I (Interrupts) with List II (Corresponding Characteristics) and select the correct answer using the codes given below : List I A. RST 6. TRAP B. Level triggered 2.5 D.gatehelp. INTR C. For increasing the number of interrupts 4. Non maskable 3. Direct addressing Codes : A (A) (B) (C) (D) 4 4 3 3 B 1 2 2 1 C 2 1 1 2 D 3 3 4 4 List II 1. Register-Indirect C.com Codes : A (A) (B) (C) (D) 2 1 1 2 B 4 4 3 3 C 3 3 4 4 D 1 2 2 1 MCQ 69 What is the total number of memory locations and input-output devices that can be addressed with a processor having 16-bits address bus. JMP 3 FAO H 2. RAL MCQ 71 Page 22 . LDA 03 FC H 4. M 3. Implicit addressing B. MOV A.gatehelp.IES EE Topic wise 2001-2008 Microprocessor www. Immediate D. match List I (Addressing Mode) with List II (Instruction) and select the correct answer using the codes given below : List I A. using memory maped I/O ? (A) 64 K memory locations and 256 I/O devices (B) 256 I/O devices and 65279 memory locations (C) 64 K memory locations and no I/O devices (D) 64 K memory locations or input-output devices MCQ 70 For Intel 8085. Mnemonic D. Used to indicate memory location 2.com A memory system of 64 kbytes needs to be designed with RAM chips of 1 kbyte each.www. A program that translates symbolic instructions into binary equivalent 4. Assembler C. An operating system YEAR 2003 MCQ 73 A Direct Memory Access (DMA) transfer implies (A) Direct transfer of data between memory and accumulator (B) Direct transfer of data between memory and I/O devices without the use of microprocessor (C) Transfer of data exclusively within microprocessor registers (D) A fast transfer of data between microprocessor and I/O devices Page 23 . Monitor program B. A combination of letters. What is the total number of decoder chips ? (A) 21 (B) 64 (C) 32 (D) 25 MCQ 72 IES EE Topic wise 2001-2008 Microprocessor Match List I with List II and select the correct answer using the codes given below the lists : List I A. and a decoder tree constructed with 2:4 decoder chips with “Enable” input.gatehelp. symbols and numerals 3. Program counter Codes : A (A) (B) (C) (D) 4 4 3 3 B 3 3 4 4 C 2 1 1 2 D 1 2 2 1 List II 1. IES EE Topic wise 2001-2008 Microprocessor www. because (A) It counts 16 bits at time (B) There are 16 address lines (C) It facilitates the user storing 16-bit data temporarily (D) It has to fetch two 8-bit data at a time MCQ 76 A microprocessor is ALU (A) and control unit on a single chip (B) and memory on a single chip (C) register unit and I/O device on a single chip (D) register unit and control unit on a single chip MCQ 77 In Intel 8085 a microprocessor ALE signal is made high to (A) Enable the data bus to be used as low order address bus (B) To latch data D 0 − D7 from data bus (C) To disable data bus (D) To achieve all the functions listed above MCQ 78 Page 24 . the flag register of a 8085 microprocessor has the following look : D7 1 D6 0 D5 X D4 1 D3 X D2 0 D1 X D0 1 The arithmetic operation has resulted in (A) A carry and an odd parity number having 1 as the MSB (B) Zero and the auxiliary carry flag being set (C) A number with even parity and 1 as the MSB (D) A number with odd parity and 9 as the MSB MCQ 75 The program counter in a 8085 microprocessor is a 16-bit register.gatehelp.com MCQ 74 After an arithmetic operation. Immediate addressing Codes : A (A) (B) (C) (D) 5 4 5 4 B 4 5 4 5 C 1 3 2 1 D 3 1 3 3 Page 25 . 2 and 4 MCQ 79 Match List I (Introduction) with List II (Type of Addressing) and select the correct answer : List I A. Register indirect addressing 5. Zero flag is set Zero flag is reset Carry flag is cleared Auxiliary carry flag is set Select the correct answer using the codes given below : (A) 1 and 3 (B) 2. Implicit addressing 4. E400H C. Register addressing 3. LXIH.www. 3 and 4 (D) 1. CMC List II 1. 3. 3 and 4 (C) 1. The input port has an address of 01H and has a data 05H to input : IN ANI 01 80 IES EE Topic wise 2001-2008 Microprocessor After execution of the two instructions the following flag portions may occur : 1. Direct addressing 2. MOV A. 2. M B. 4.com Examine the following instruction to be executed by a 8085 microprocessor. LDA F1 CDH D.gatehelp. 5.5 and C uses RST 6. Memory read and Memory write MCQ 81 Output of the assembler in machine codes is referred to as (A) Object program (B) Source program (C) Macroinstruction (D) Symbolic addressing MCQ 82 Three devices A. B uses RST 6. Fetch and Memory write (B) 3.5 and C uses RST 7. B and C are connected to an Intel 8085 A microprocessor.com MCQ 80 How many and which types of machine cycles are needed to execute PUSH PSW by an Intel 8085 A microprocessor ? (A) 2. Fetch and 2 Memory read (D) 3.5 and C uses RST 5. The correct assignment of interrupt inputs is (A) A uses RST 5.5. Fetch. B uses RST 6.gatehelp. Fetch and 2 Memory write (C) 3. B uses RST 6.5 (D) A uses TRAP. the instruction ACI 56 H will result in (A) 8E H (B) 94 H (C) 7E H (D) 84 H MCQ 84 Which one of the following statements about RAM is NOT correct ? Page 26 . Device A has the highest priority and device C has the lowest priority.5 and C uses TRAP (B) A uses RST 5.5.5 MCQ 83 If the accumulator of an Intel 8085 A microprocessor contains 37 H and the previous operation has set the carry flag.5 (C) A uses RST 7. B uses RST 5.IES EE Topic wise 2001-2008 Microprocessor www. Printer Floppy disk drives Video display unit Incoming power supply Select the correct answer using the codes given below : (A) 1 and 2 (B) 2 and 3 (C) 3 and 4 (D) 1 and 3 Direction : The following item consist of two statements. 3.gatehelp. 2.www. 4. You are to Page 27 .com (A) RAM stands for random-access memory (B) It is also called read/write memory (C) When power supply is switched off. the information in RAM is usually lost (D) The binary contents are entered or stored in the RAM chip during the manufacturing state MCQ 85 IES EE Topic wise 2001-2008 Microprocessor A handshake signal in a data transfer is transmitted (A) Along with the data bits (B) Before the data transfer (C) After the data transfer (D) Either along with the bits or after the data transfer MCQ 86 Which one of the following is NOT a vectored interrupted ? (A) TRAP (B) INTR (C) RST 3 (D) RST 7. one labelled as Assertion ‘A’ and the other labelled as Reason ‘R’.5 MCQ 87 Ports are used to connect the CPU to which of the following units ? 1. YEAR 2002 MCQ 89 The number of output pins of a 8085 microprocessor are (A) 40 (B) 27 (C) 21 (D) 19 MCQ 90 Consider the execution of the following instructions by a 8085 microprocessor : LXI H.com examine these two statements carefully and decide if the Assertion A and the Reason R are individually true and if so. B Reason (R) : After the execution of a data transfer instruction. Select your answers to these items using the codes given below. whether the Reason is a correct explanation of the Assertion. Codes : (A) Both A and R are true and R is the correct explanation of A (B) Both A and R are true but R is NOT the correct explanation of A (C) A is true but R is false (D) A is false but R is true MCQ 88 Assertion (A) : The zero-flag of a 8085 microprocessor is not affected after the execution of the following couple of instructions : MVI MOV B. 01FFH SHLD 2050 H After execution the contents of memory locations 2050 H and 2051 H Page 28 .gatehelp. 03 A. zeroflag is set if the accumulator content is zero.IES EE Topic wise 2001-2008 Microprocessor www. 2051 H " 01.gatehelp. L " 01 (C) 2050 H " FF. L " 01 (B) 2050 H " 01.8257 Page 29 . L " FF (D) 2050 H " FF. H " 00. 2051 H " 01. L " 00 MCQ 91 IES EE Topic wise 2001-2008 Microprocessor Which one of the following functions is performed by the 8085 instruction MOV H. H " 01.com and the registers H and L. 2051 H " 01. is used for (A) small systems (B) large systems (C) both large and small systems (D) very large systems MCQ 94 The interfacing device used for the generator of accurate time delay in a microcomputer system is (A) Intel . will be (A) 2050 H " FF. the instruction RST. C ? (A) Moves the contents of H register to C register (B) Moves the contents of C register to H register (C) Moves the contents of C register to HL pair (D) Moves the contents of HL pair to C register MCQ 92 For 8085 microprocessor. H " FF. H " FF.6 restarts subroutine at address (A) 00H (B) 03H (C) 30H (D) 33H MCQ 93 Memory-mapped I/O-scheme for the allocation of address to memories and I/O devices.www.8251 (B) Intel . 2051 H " FF. The wait states are always inserted between (A) T1 and T2 (B) T2 and T3 (C) T3 and T4 (D) T4 and T1 MCQ 96 When RET instruction is executed by any subroutine then (A) the top of the stack will be popped out and assigned to the PC (B) without any operation. the calling program would resume from instruction immediately following the call instruction. Page 30 30H ADC port address 30H is decoded . The byte represents digital equivalent of analog input voltage Vin applied to ADC when RD is asserted.com (C) Intel . ADC GETADC : EQU IN RET When RET is executed 1. T2.IES EE Topic wise 2001-2008 Microprocessor www.8259 YEAR 2001 MCQ 95 The length of a bus cycle in 8086/8088 is four clock cycles. and also the PC will be incremented after the execution of the instruction MCQ 97 Consider the following set of 8085 instructions used to read a byte of data from the output of an ADC.8253 (D) Intel . Op-code of IN is fetched 2. T1.gatehelp. the calling program would resume from instruction immediately following the call instruction (C) the PC will be incremented after the execution of the instruction (D) without any operation. T4 and an indeterminate number of wait state clock cycles denoted by TW . T3. 3.www. 4. 3. 4 (C) 1. 2. a number of the form 000XXXX0 stored in the accumulator is processed by the programme (Assume Cy = 0 ) as follows ANI RAL MOV ANI RAL ANI RAL ADD B FFH B.gatehelp. A FFH FFH The operation carried out by the programme is (A) multiplication of accumulator content by 10 (B) complement of accumulator content (C) multiplication of accumulator content by 9 (D) rotation of accumulator content three times MCQ 99 Which one of the following circuits transmits two messages simultaneously in one direction ? (A) Duplex (B) Diplex (C) Simplex (D) Quadruplex Page 31 . 2. 2 (D) 3. 1. 4.com 3. Op-code of IN is decoded I/O read operation is performed IES EE Topic wise 2001-2008 Microprocessor The correct sequence of these operations is (A) 3. 4. 4 MCQ 98 In 8085 microprocessor. 1. 2 (B) 1.