ICC1 200703 IG 01 Basicflow

AgendaDAY 1 i 1 2 Introduction & Overview IC Compiler Basic Flow Placement, Power & Test Synopsys 20-I-071-SSG-007 © 2007 Synopsys, Inc. All Rights Reserved 1- 1 Unit Objectives After completing this unit, you should be able to:   Create a Milkyway library to hold your design Read all necessary files required to run IC Compiler, resolving common errors/warnings Set up timing for analysis and optimizations Execute the basic flow for placement, CTS and routing in IC Compiler   1- 2 Unit Roadmap Data Setup Read netlist and SDC Setup timing libraries Setup Milkyway Apply the floorplan Break Basic Flow Placement Clock tree synthesis Routing Analysis Timing Setup and RC Modeling Timing variables RC and TLU+ models Delay calculation 1- 3 General IC Compiler Flow Synthesis  Design Setup Design Planning place_opt clock_opt route_opt Chip Finishing Unit 1 Unit 5 Unit 2 Unit 3 Unit 6 Unit 7 1.4 . Placement.5 . Routing with Optimizations Gate-Level Netlist IP IC Compiler Optional: Floorplan Placed. Routed & Optimized Design with Clock Trees 1. CTS. 4. 2. 3. Std cells placed Clock tree(s) built Clock and signal routing completed place_opt clock_opt route_opt Chip finishing and DFM 1. IO pads placed Chip/core boundary Cell rows.IC Compiler Data Flow 1. 2. wire tracks created Macro placement final Floorplan Power plan Design Planning Output 1. 2. Tech File TLU + IO TDF file Netlist SDC Output DEF MW 1. 5. 3. 4.6 . 3. Unit Flow: From Setup to Output Logical Data Setup Physical Data Setup place_opt clock_opt route_opt Analysis Output 1.7 . . set_output_delay –max 2. .8 .2 ..db Gate-Level Netlist(s) create_clock –period 10 ...Logical Data Logical Data Logical Data Physical Data place_opt clock_opt route_opt Analysis Output Logical Libraries ... set_driving_cell ..5 . link Logical (Timing) Constraints check_timing 1.. set_input_delay –max 1...... v … 1.v file2.Reading Gate-Level Netlists from Synthesis  IC Compiler can open a Milkyway database written by Design Compiler And other formats supported by Design Compiler read_ddc read_verilog read_vhdl …  ! Milkyway and DDC can also contain design attributes  You can read one or many files read_verilog file1.10 9 . i. the first commands of your ICC script should be: current_design MY_TOP_DESIGN uniquify MY_TOP_DESIGN  PARSER1 PARSER PARSER2 PARSER3 1.No Multiply Instantiated Designs  IC Compiler does not support non-uniquified designs.11 10 .e. designs with multiple instantiations! When reading in a non-uniquified design. RAM.db" “*” = Search all designs in memory 1. or. …) Provide timing information for hard macros (IP.Logical Libraries   Provide timing and functionality information for all standard cells (and.db  Define drive/load design rules:   Max fanout and transition Max/Min capacitance ! Make sure the first specified db contains the correct units  Specified as follows: set link_library "* gates.12 11 .db io. ROM. …) Logical Libraries . flipflop.db rams. Noise.CCS Library Support  IC Compiler supports NLDM and CCS (Composite Current Source) libraries  Current-based approach more accurately models Timing. Power High impedance interconnect  Miller effect  Dynamic IR-drop  Multi-voltage  Temperature Inversion   NLDMs are not accurate enough for 90 nm and below  Use CCS 1.14 12 . CCS Supported Throughout Galaxy Galaxy CCS Support Tools Timing Noise Power NanoChar PrimeTime IC Compiler Design Compiler n/a Design Compiler Signoff IC Compiler Milkyway 1.15 13 . /scripts lappend search_path [glob $MW_libs/*/LM]   The above paths will be used by IC Compiler for reading or accessing files 1./design_data .16 14 .. you must specify the unix-path for all files (relative or absolute) You may specify where to look for files: lappend search_path .How does IC Compiler Find Files?  By default. you need to specify the logical library that will be used for mapping/optimization: set target_library "gates.Target Libraries  Along with the link_library and search_path variables.17 15 .db"  Typically. the target_library points to your standard cells only 1. which are stored in the logical libraries.Resolving References  Gate-level netlists contain references to standard cells and macros.18 16 .db mem. as well as other hierarchical logic blocks The link command will ensure that all references can be resolved link_library nand nor inv ff pci_core risc_core sdram_if gates.db  Gate-Level Netlist(s) link * ip.db 1. Shortcuts… import_designs orca.v current_design ORCA_TOP uniquify link save_mw_cel –as ORCA_TOP 1.v \ -format verilog \ -top ORCA_TOP Format can be verilog. db.19 17 . ddc Replaces: read_verilog –netlist orca. Timing Constraints  “Timing Constraints” are required to communicate the design’s timing intentions to IC Compiler  They should be the same ones used for synthesis with Design Compiler (preferably SDC) read_sdc timing_constraints.20 18 .sdc SDC = Synopsys Design Constraints create_clock –period 10 [get_ports clk] set_input_delay 4 –clock clk \ [get_ports sd_DQ[*]] set_output_delay 5 –clock clk [get_ports sd_LD] set_load 0. 1..2 [get_ports pdevsel_n] set_driving_cell –lib_cell buf5 \ [get_ports pdevsel_n] .. Constraint Management 2006. resistance. checks To remove all settings: reset_design • Removes all optimization attributes (dont_touch. capacitance. latencies and transitions remove_annotations • Removes all annotated delays.06 and later remove_sdc • Removes all SDC constraints remove_ideal_network -all • Removes ideal_network attributes.21 19 . transition. 1. size_only…) and all constraints. 22 20 . you should ensure that the design is completely constrained IC Compiler will not optimize paths that are not constrained for timing No checking for missing external loads or drive characteristics will be performed!   ! 1.Timing Check check_timing  Before proceeding. check_timing: False Paths   check_timing reports all unconstrained paths False paths are also considered unconstrained!  To verify that unconstrained paths are OK: report_timing_requirements Reports false paths set on design Compare these paths to the ones reported by check_timing   1.23 21 . 24 22 .Physical Data Logical Data Physical Data Data Physical place_opt clock_opt route_opt Analysis Output Constrained and linked design Physical Reference Libraries (Milkyway) IP Floorplan check_physical_constraints 1. 26 23 .0)  Define placement unit tile INV F  Contain physical information of standard and macro cells necessary for placement Symmetry (X. layer and shape) Dimension “bounding box” VDD A B reference point (typically 0.Physical Libraries Reference Libraries (Milkyway) Blockage Y Pins (direction. Y. or 90º) NAND_1 GND Abstract View unit tile (site) BUF FF NOR 1. xor3a27 FRAM/ and2a1 and2a2 ….db …. CEL/ and2a1 and2a2 …. xor3a27 1.27 24 .db lib_min.Milkyway Reference Libraries Information is stored in so-called “views”. for example:    CEL: The full layout view FRAM: The abstract view used for P&R LM: Logic Model with Timing and Power info (optional*) VENDOR_XYZ_std_cell_90nm Used for P&R LM/ lib_max. Technology File (. etc.tf file)   Tech File is unique to each technology Contains metal layer technology parameters:     Number and name designations for each layer/via Dielectric constant for technology Physical and electrical characteristics of each layer/via Design rules for each layer/Via (Minimum wire widths and wire-to-wire spacing.) Units and precision for electrical units Colors and patterns of layers for display    … 1.28 25 . 23 = 0.tf dielectric unitTimeName timePrecision unitLengthName lengthPrecision gridResolution unitVoltageName } .29 26 .23 1..23 = 0.Example of a Technology File Technology { = 3.56 = 0.. = 16 = "metal1" = 0.7 = "ns" = 1000 = "micron" = 1000 = 5 = "v" abc_6m... Layer "m1" { layerNumber maskName pitch defaultWidth minWidth minSpacing . 30 27 .tf \ -mw_reference_library “sc io ram32” -open \ Now you are ready to apply the floorplan… 1.Specifying Reference Libraries How are physical reference libraries and the technology file specified? By creating a design library! create_mw_lib design_lib_orca \ -technology techfile. read_def my_floorplan.Applying the Floorplan Cluster Hard Boundary Site Arrays Array of placement sites RAM Fixed Cells Example: RAM placement Port Locations Signal I/O Keepouts & PG nets Allows physicalonly objects like PG nets.31 28 .def –allow_physical 1. 32 29 .Copying the Floorplan from another MW Cell Cell_A copy_floorplan Cell_B Existing unfloorplanned cell Useful if reading a new netlist of the same design that was floorplanned in IC Compiler or JupiterXT. 1. sdc place_opt clock_opt route_opt save_mw_cel -as routed Apply your timing constraints for P&R.mw open_mw_cel floorplanned set_tlu_plus_files .db rams. 1.db" open_mw_lib my_jxt_lib.Opening a MW Design from JupiterXT lappend search_path ./db set link_library "* gates..explained later remove_sdc read_sdc mydesign.. .33 30 ..db" set target_library "gates. 34 31 .Check Physical Constraints check_physical_constraints  Checks libraries and floorplan:     Physical  Logical library inconsistencies Insufficient core placement area Warns about narrow placement regions (Chimneys) Reports on number of physical_only_cells. available sites and overall utilization RC parameters …see man page for more details   1. save the Milkyway design: save_mw_cel –as orca_init  By default. link_library. by default the stored settings are not re-applied. the settings have to be re-applied. target_library and TLU+ settings are stored with the CEL  If library files change or move to somewhere else. unless you set: set auto_restore_mw_cel_lib_setup true open_mw_cel orca_init 1. See notes section below!  When you re-open the CEL.Saving and Loading the Design  Once setup is complete.35 32 . search_path. tf Design Library design_lib_orca Container for all data! TLU+ RC models orca.def orca_init …more later 1.The Design Library sc.v orca.sdc orca.db link_library target_library settings MW Standard cells MW Macro cells MW Pad cells Technology File abc_6m.db io.36 33 . UNIX Structure of a Design Milkyway Database MW Design Library .C.O. technology data etc.37 34 . Saved Cell … lib lib_1 lib_bck CEL/ …. orca_init:1 1./design_lib_orca/ Database T. Corrupted! CEL/ ORCA_init … ORCA_floorplanned ORCA_placed ORCA_cts ORCA_routed 1. .38 35 .UNIX Manipulation of a Milkyway Database UNIX% cd CEL UNIX% rm ORCA_placed UNIX% cp ~Joes_Lib/ORCA_placed .O.C./design_lib_orca/ STOP lib lib_1 lib_bck T. IC Compiler requires a chip-level floorplan including IO PADs. What is the difference between the link_library and the target_library? 3. List the 2 variables that need to be set up to successfully read all design files! 2. Which of the following is not recommended? a. A floorplan must always be input to IC Compiler by reading a DEF file. set search_path my_path c. True / False 4. lappend search_path my_path b. True / False 5. set search_path "$search_path my_path" 1.39 36 .Test for Understanding 1. sdc read_sdc create_mw_lib –technology … –mw_reference_library … MW Reference Libraries IC Compiler read_def Physical Constraints DEF or MW library + tech file check_timing check_physical_constraints Ready for Place & Route 1.db" set target_library sc.db Logical Library .Summary Gate-Level Netlist set link_library "* sc.40 37 .db read_verilog/vhdl/ddc Or: import_design Logical Constraints . 10 Minute Break 1.41 38 . db" All setup done first and stored in .sdb io_icon./ref/sdb .setup create_mw_lib design_lib_orca -open \ -technology techfile.db io..tf \ -mw_reference_library "mw/sc mw/io mw/ram32" set mw_logic0_net "VSS" set mw_logic1_net "VDD" import_designs design...ddc \ -format ddc \ -top ORCA_TOP read_def –allow_physical design./scripts .tcl lappend search_path ./ref/db set symbol_library "sc_icon.def save_mw_cel –overwrite # CEL saved as ORCA_TOP 1.synopsys_dc.42 39 .db" set target_library "sc_max.db ram16x128_max.IC Compiler Recommended Setup # load common settings & useful procedures source .sdb" set link_library "* sc_max./ref/icc_settings. in the order shown above.synopsys_dc.synopsys_dc.synopsys_dc.setup are executed upon tool startup. 1.synopsys_dc.43 40 .setup User’s Specific Project Setup ICC startup directory 3 .setup Standard Setup .IC Compiler Three Initialization Files User’s General Setup 1 ~user 2 $SYNOPSYS/admin/setup .setup Commands in . (TIM-177) report_constraint –all report_timing set_zero_interconnect_delay_mode false Information: Timer is not in zero interconnect delay mode.44 41 .Placement stage Logical Data Physical Data place_opt clock_opt route_opt Analysis Output Before starting placement & optimization:  Do not over-constrain the design  Constraints should match design specification  Report timing before placement  Check for unrealistic or incorrect constraints set_zero_interconnect_delay_mode true Warning: Timer is in zero interconnect delay mode. (TIM-176) 1. Placement and Related Optimizations place_opt Performs iterative placement and optimization.  DTDP: slack is a direct placement objective Logic moved closer together for shorter nets Cells upsized for optimal drive/speed 1.45 42 . 46 43 .Clock Tree Synthesis Logical Data Physical Data place_opt clock_opt route_opt Analysis Output 1. Set the clock tree options/exceptions Run the clock_opt command clock_opt  Builds the clock trees    Performs incremental logic and placement optimizations Runs clock tree optimizations Routes the clock nets Optionally. 2. clock_opt can   Fix hold time violations Perform inter-clock balancing 1. placement.47 44 . routing and crosstalk optimizations to produce the best routed design 1.Routing Logical Data Physical Data place_opt clock_opt route_opt Analysis Output route_opt    runs the routers: Global Route Track Assignment  Detailed Route Then performs numerous logic. Analysis Logical Data Physical Data place_opt clock_opt route_opt Analysis Analysis Output  Examine the screen-outputs of place_opt and route_opt for design summaries:   Utilization WNS – Worst Negative Slack     TNS – Total Negative Slack Legality of cell placement Cell count and area Design rule violations  Use report_qor to see:   WNS/TNS per path group (clock group) Other statistics 1.48 45 . g. utilization)  report_design -physical  Analyze the congestion Congestion map (GUI)  report_congestion  1.49 46 .Analysis – Details  Generate more detailed reports  Show all violating path end points  report_constraint –all_violators report_timing  Show details of the worst violating setup paths   Report physical design statistics (e. v  Save the floorplan only write_def -output floorplan.tcl 1.50 47 .Output Logical Data Physical Data place_opt clock_opt route_opt Analysis Output Output  Apply consistent naming change_names –hierarchy –rules verilog Imperative when exporting data  always!  Save the design in the Milkyway database save_mw_cel -as routed  Save as Verilog netlist write -format verilog \ -hierarchy -output routed.def write_floorplan floorplan. explained later… read_sdc my_design..log save_mw_cel -as routed 1.51 48 .sdc check_timing read_def -allow_physical my_design.mw \ –technology tech_file.def check_physical_constraints place_opt clock_opt route_opt run./tlup set link_library "* gates./db ./design_data .db" create_mw_lib my_lib.tcl | tee myrun.tcl UNIX$ icc_shell –f run.v \ -format verilog \ -top MYDESIGN set_tlu_plus_files \ -max_tluplus abc_max.db" set target_library "gates..tf \ –mw_reference_library "mwlib/gates mw_lib/rams“ \ -open import_designs my_design.tlup \ -min_tluplus abc_min.db rams.tlup \ -tech2itf_map abc.map .Example “run” Script lappend search_path . Local Disk Space Usage  When running a design through the IC Compiler flow, you will require local disk space to store the database. Example: Design size (instances) Milkyway database** size place_opt clock_opt route_opt --------------------------------------------------------------- 150K 250K 400K 625K 700K 850K 56MB 150MB 242MB 277MB 344MB 917MB 62MB 178MB 269MB 325MB 419MB 950MB 120MB 303MB 460MB 569MB 741MB 1.5GB ** this includes all CEL/ROUTE/PARA/... views plus any CEL attachments  The above table shows the incremental disk space requirements for each step. So, to complete a 150K design, you need 56 + 62 + 120 = 238 MB. 1- 52 49 Usage of the /tmp Directory  IC Compiler uses the /tmp directory for temporary data storage. This can be changed using a Unix env. variable: setenv $TMPDIR directory_name  Overall disk space required for the /tmp directory is 3x the physical RAM size  For example, a machine with 16G of physical RAM needs a minimum of 48G of disk space for the /tmp directory  You need to pay special attention to the RAM utilization when you run several large designs on the same machine, even with multiple CPUs Designs of the same size but different constraints or levels of logic can require very different storage 1- 53 50  Static Timing Analysis  IC Compiler is set up very similarly to Design Compiler and PrimeTime Before starting with IC Compiler, set up the libraries and operating conditions. Example: set link_library "* abcmax.db" set_operating_conditions \ –analysis_type on_chip_variation \ -max abc_wc -max_library abc_max Using operating conditions ‘abc_wc' found in library ‘abc_max'.  report_timing –delay max|min 1- 54 51 Timing and Optimization Setup (1/2)  Timing and optimization in IC Compiler is controlled by many variables and commands.55 52 . then copy the variables / commands into your setup file 1. Example set enable_recovery_removal_arcs true set timing_self_loops_no_skew true set_cost_priority {max_delay max_capacitance} set_ahfs_options -enable_port_punching true  Memorizing all these variables and commands can be a challenge – the GUI provides help! Use the GUI to perform your timing and optimization setup. 56 53 .Timing and Optimization Setup (2/2) 1. 57 54 . ICC needs to know each net’s parasitic Rs and Cs 1. Cnet + Cpin)   ICC calculates delay for every cell and every net To calculate delays.Timing is Based on Cell and Net Delays 0. Cnet + Cpin) Net Delay = (Rnet.5 ns Rnet Cpin Cnet Cell Delay = (Input Transition Time. TLU+ Models  IC Compiler calculates C and R using the net geometry and the TLU+ look-up tables UDSM process effects modeled  UDSM Process Effects  Conformal Dielectric  Metal Fill  Shallow Trench Isolation  Copper Dishing: • Density Analysis • Width/Spacing  Trapezoid Conductor See Appendix B for details TLU+ ICC. Astro™ Single Process File (ITF) nxtgrd Star-RCXT™ 1.58 55 . PC. binary TLU+ model file Always use the latest Star-RCXT release to generate the models.Generating TLU+ Models   ITF (process file) provided by the vendor TLU+ model is generally not provided  Generate TLU+ from ITF unix% grdgenxo -itf2TLUPlus -i <ITF file> -o <TLU+ file> Where: -itf2TLUPlus generates TLU+ instead of nxtgrd file -i is the ITF file -o is the output. 1.59 56 . Loading TLU+ Models set_tlu_plus_files \ -max_tluplus abc_max.map IC Compiler searches search_path to find TLU+ files check_tlu_plus_files   Performs sanity check on TLU+ settings Execute this command after setting TLU+ to ensure correct TLU+ and map file 1.tlup \ -min_tluplus abc_min.tlup \ -tech2itf_map abc.60 57 . 26 WMIN=0.16 …} DIELECTRIC diel1d { THICKNESS=0.2 } … abc.tf (MW technology file) layer/via names to Star-RCXT .tf Layer "METAL" { layerNumber maskName … = 14 = "metal1" abc.61 58 .2 } CONDUCTOR cm { THICKNESS=0.435 ER=4. abc.06 ER=4.Mapping file The Mapping File maps the .itf layer/via names.map conducting_layers poly metal1 metal2 … poly cm cm2 1.itf DIELECTRIC cm_extra3 { THICKNESS=0. only Ctotal / Ceff is needed R3 C3 C4 U2 U1 R2 R1 C2 C1  Calculating Net Delay is done using Delay Calculation algorithms: Elmore.Calculating Cell and Net Delay  Now that R and C are known from TLU+.62 59 . the delays can be calculated  For Cell Delays. Arnoldi 1. an Elmore model is used for delay calculation 1. net geometry is estimated based on a Virtual Route Since Virtual Routing is only an estimate.PreRoute Delay Calculation Algorithm Virtual Route Pin-to-pin timing  Prior to routing.63 60  . PostRoute Delay Calculation Algorithms Detailed Route    After routing. detailed nets are available and extraction can be more accurate By default. Elmore is still used Arnoldi can be turned on for postroute calculations 1.64 61 . Basic Flow Summary You should now be able to:  Create a Milkyway library to hold your design Read all necessary files required to run IC Compiler. resolving common errors/warnings Set up timing for analysis and optimizations Execute the basic flow for placement. CTS and routing in IC Compiler    1.65 62 . Lab 1: Baseline flow for IC Compiler Create MW database with attached libraries 45 minutes Goals:  Read design. constraints.66 63 . floorplan Setup design database and timing Perform baseline place. cts & route operations with associated default optimizations place_opt  clock_opt route_opt Analysis and Output 1. Appendix A MW reference library preparation 64 . write_lib Database ( db ) Library db (timing) PDB (physical) Design db/ddc Setup without using Milkyway: search_path link_library target_library Milkyway Terminology Milkyway tool (create/edit Milkyway Library) read_lef. … Milkyway Library Library db (can be part of Ref Lib as LM view) Reference Library Design Library Setup using Milkyway library: search_path link_library target_library set_mw_lib_reference 1.68 65 . read_plib.Migration from DB/PDB to MW: Terminology DC / PC Terminology Library Compiler (compile library) read_lib. Reference Library Requirements    Logical libraries (.1200.7600.db) Physical libraries (MW) Libraries are provided by the ASIC vendor libraries must match • cell names • pins physical only cell Cell Logical Library Cell Attribute Physical Library size ----------------------bufbd1 sdbfb1 t(mux_ff) -------------------------bufbd1 sdbfb1 filler (1. 3.6900) (14.db} set_mw_lib_reference {art005} 1.6900) (13. 3. 3.6400.69 66 .6900) test cell set target_library {art005. 70 67 .9e-05 Capacitance : 1.19e-05 Routing layer : METAL2 width: 200 pitch: 410 space: 210 Routing Layer : METAL2 Resistance : 3...7e-05 Capacitance : 1.02e-05 . pitch spacing width 1. Physical Library: design_lib_orca Routing layer : METAL width: 160 pitch: 410 space: 180 Routing Layer : METAL Resistance : 6..4e-05 Capacitance : 4.39e-05 Routing layer : METAL4 width: 440 pitch: 970 space: 460 Routing Layer : METAL4 Resistance : 1..7e-05 Capacitance : 2.Physical Technology Data icc_shell> check_physical_constraints .23e-05 Routing layer : METAL3 width: 200 pitch: 515 space: 210 Routing Layer : METAL3 Resistance : 3. Finally. 1.71 68 . Press Apply: This converts the cells in the LEF file into FRAM views and adds them to the Milkyway library. unless the MW library has already been prepared with a MW techfile.Convert LEF to Milkyway FRAM UNIX% Milkyway -galaxy Command: read_lef Specify the MW library name Specify the tech LEF. if one is available. specify you cell LEF files. Finally. Press Apply: This converts the cells in the pdb/plib file into FRAM views and adds them to the Milkyway library.Convert PLIB/PDB to Milkyway FRAM UNIX% Milkyway -galaxy Command: read_plib Specify the MW library name Specify the tech pdb. 1. specify you cell PDB files.72 69 . if one is available. unless the MW library has already been prepared with a MW techfile. Appendix B DSM Effects 70 . Not very relevant for routing modeling Chemical Mechanical Polishing (CMP) 1.74 71 .DSM Effects UDSM Process Effects  Conformal Dielectric  Metal Fill  Shallow Trench Isolation  Copper Dishing: • Density Analysis • Width/Spacing  Trapezoid Conductor Conformal Dielectric STI . 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