gpdk045_pdk_referenceManual.pdf

March 30, 2018 | Author: Michael Clarke | Category: Mosfet, Bipolar Junction Transistor, Library (Computing), Field Effect Transistor, Electrical Resistance And Conductance
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GPDK045 Reference ManualREVISION 2.0 Reference Manual Generic 45nm Salicide 1.0V/1.8V 1P 11M Process Design Kit and Rule Decks (PRD) Revision 2.0 4/29/09 CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 1 GPDK045 Reference Manual REVISION 2.0 Table of Contents 1 OVERVIEW .......................................................................................................................................................5 1.1 SOFTWARE ENVIRONMENT ..........................................................................................................................5 2 DOCUMENTS....................................................................................................................................................6 3 WHAT MAKES UP A PRD? ............................................................................................................................7 4 INSTALLATION OF THE PRD ......................................................................................................................8 5 PRD INSTALL DIRECTORY STRUCTURE/CONTENTS .........................................................................9 6 CREATION OF A DESIGN PROJECT ........................................................................................................10 7 TECHNOLOGY FILE METHODOLOGY ..................................................................................................11 8 CUSTOMIZING LAYER DISPLAY PROPERTIES...................................................................................12 9 SCHEMATIC DESIGN...................................................................................................................................14 10 LIBRARY DEVICE SETUP ...........................................................................................................................15 10.1 10.2 10.3 10.4 10.5 10.6 11 SUPPORTED DEVICES.................................................................................................................................18 11.1 11.2 11.3 11.4 11.5 11.6 12 RESISTORS.................................................................................................................................................15 MOSFETS ...................................................................................................................................................15 BIPOLAR TRANSISTORS .............................................................................................................................16 DIODES ......................................................................................................................................................16 CAPACITOR ...............................................................................................................................................16 INDUCTOR .................................................................................................................................................17 MOSFETS ...................................................................................................................................................18 RESISTORS.................................................................................................................................................18 CAPACITOR ...............................................................................................................................................19 BIPOLARS ..................................................................................................................................................19 DIODES ......................................................................................................................................................20 INDUCTORS ...............................................................................................................................................20 VIEWS PROVIDED ........................................................................................................................................21 12.1 MOSFETS ...................................................................................................................................................21 12.2 RESISTORS.................................................................................................................................................21 12.3 CAPACITOR ...............................................................................................................................................21 12.4 DIODES ......................................................................................................................................................22 12.5 BIPOLARS ..................................................................................................................................................22 INDUCTORS ..............................................................................................................................................................22 12.6 .........................................................................................................................................................................22 13 CDF PARAMETERS ......................................................................................................................................23 13.1 13.2 13.3 13.4 13.5 14 MOSFETS ...................................................................................................................................................23 RESISTORS.................................................................................................................................................24 MOSCAPS .................................................................................................................................................25 BIPOLARS ..................................................................................................................................................26 INDUCTORS ...............................................................................................................................................27 MODEL SETUP...............................................................................................................................................28 CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 2 GPDK045 Reference Manual REVISION 2.0 15 TECHFILE LAYERS......................................................................................................................................29 16 VIRTUOSO L,XL,GXL...................................................................................................................................32 17 DIVA DECKS...................................................................................................................................................33 17.1 17.2 17.3 18 ASSURA DECKS .............................................................................................................................................34 18.1 18.2 18.3 19 ASSURA DRC............................................................................................................................................34 ASSURA LVS.............................................................................................................................................34 ASSURA QRC............................................................................................................................................34 GPDK045 PCELL LAYOUTS........................................................................................................................35 19.1 19.2 19.3 19.4 19.5 19.6 20 DIVA DRC ................................................................................................................................................33 DIVA EXTRACT .........................................................................................................................................33 DIVA LVS .................................................................................................................................................33 MOS PCELL ...............................................................................................................................................35 RESISTOR PCELL .......................................................................................................................................37 CAPACITOR PCELL ....................................................................................................................................38 DIODE PCELL.............................................................................................................................................39 BIPOLAR PCELL .........................................................................................................................................40 INDUCTOR PCELL ......................................................................................................................................41 GPDK045 DEVICE DATASHEETS ..............................................................................................................42 20.1 20.2 20.3 20.4 20.5 20.6 20.7 20.8 20.9 20.10 20.11 20.12 20.13 20.14 20.15 20.16 20.17 20.18 20.19 20.20 20.21 20.22 20.23 20.24 20.25 20.26 20.27 20.28 20.29 20.30 20.31 20.32 20.33 20.34 NMOS1V DATASHEET ................................................................................................................................42 NMOS1V_HVT DATASHEET ........................................................................................................................44 NMOS1V_LVT DATASHEET ........................................................................................................................46 NMOS1V_NAT DATASHEET ........................................................................................................................48 NMOS2V DATASHEET ................................................................................................................................50 NMOS2V_NAT DATASHEET ........................................................................................................................52 PMOS1V DATASHEET .................................................................................................................................54 PMOS1V_HVT DATASHEET ........................................................................................................................56 PMOS1V_LVT DATASHEET.........................................................................................................................58 PMOS2V DATASHEET .................................................................................................................................60 RESM1-RESM11 DATASHEET .....................................................................................................................62 RESNSNDIFF DATASHEET...........................................................................................................................64 RESNSNPOLY DATASHEET .........................................................................................................................66 RESNSPDIFF DATASHEET ...........................................................................................................................68 RESNSPPOLY DATASHEET ..........................................................................................................................70 RESSNDIFF DATASHEET .............................................................................................................................72 RESSNPOLY DATASHEET ...........................................................................................................................74 RESSPDIFF DATASHEET .............................................................................................................................76 RESSPPOLY DATASHEET ............................................................................................................................78 RESNWOXIDE DATASHEET .........................................................................................................................80 RESNWSTI DATASHEET ..............................................................................................................................82 MIMCAP DATASHEET .................................................................................................................................84 NMOSCAP1V DATASHEET ..........................................................................................................................86 NMOSCAP2V DATASHEET ..........................................................................................................................88 PMOSCAP1V DATASHEET...........................................................................................................................90 PMOSCAP2V DATASHEET...........................................................................................................................92 VPNP2 DATASHEET....................................................................................................................................94 VPNP5 DATASHEET....................................................................................................................................96 VPNP10 DATASHEET..................................................................................................................................98 NPN2 DATASHEET ...................................................................................................................................100 NPN5 DATASHEET ...................................................................................................................................102 NPN10 DATASHEET .................................................................................................................................104 NDIO DATASHEET ....................................................................................................................................106 PDIO DATASHEET ....................................................................................................................................108 CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 3 ...............................................................................................................114 NDIO_2V DATASHEET ...................................................................................................................................................................112 NDIO_NVT DATASHEET ..............GPDK045 Reference Manual 20..................................126 CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 4 .....38 20...............................................................................................................................43 REVISION 2......124 IND_S DATASHEET .........39 20..........41 20............................................................122 IND_A DATASHEET .........................120 PDIO_2V DATASHEET .......0 NDIO_LVT DATASHEET....................40 20......................................................................................................................................................................................................35 20...............................36 20..............................................................................................110 NDIO_HVT DATASHEET .............................................................116 PDIO_LVT DATASHEET ...42 20.............................................118 PDIO_HVT DATASHEET ................................37 20..................................................................................... Inc.GPDK045 Reference Manual REVISION 2. Physical Design Cadence Space Based Router IUS81 Cadence AMS Designer. AMS/Ultra MMSIM70 Cadence Spectre. 1. Ultrasim ASSURA32 Cadence DRC. Analog Design and Simulation. XL. (“Cadence”).1 Software Environment The GPDK045 has been designed for use within a Cadence software environment that consists of the following tools – GPDK045 Cadence IC613 Database Software Release Key Products Stream IC613 FINALE72 Cadence Virtuoso Design Environment. GXL) ANLS71 Cadence VoltageStorm SOC71 Cadence SOC Encounter CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 5 .0 1 Overview The purpose of this Reference Manual is to describe the technical details of the 45nm Generic Process Design Kit (“GPDK045”) provided by Cadence Design Systems. LVS EXT81 Cadence QRC Extraction (L. pdf gpdk045_drc.pdf DOCUMENT DATE :15/05/2009 Rev 2.0 2 Documents Documents Used Design Rule Document Design Rule Document CADENCE CONFIDENTIAL gpdk045_drc.GPDK045 Reference Manual REVISION 2.0 PAGE 6 .0 1. X environment. The diagram shows the relationship between the PRD and the Cadence IC6. AMS P D K Spectre Models ADEL. ADEXL.GPDK045 Reference Manual REVISION 2. Ultrasim. LVS & Extraction Device Layout Virtuoso L Device Connectivity Editing Virtuoso XL Device Place and Route Virtuoso GXL Physical Verification Assura DRC/LVS/RCX Process Design Kits (PDK) contains the following: • Symbols & CDFs & Callbacks • Simulation & CDFs • Spectre Models • Fixed Layouts & Parameterized Cells • IC6.0 3 What makes up a PRD? A PRD contains the process technology and needed information to do chip-level design in the Cadence IC6.X tool suite that it enables. ADEGXL Fixed Layouts & Parameterized Cells IC6. PRD Symbols CDFs & Callbacks Simulation & CDF Netlisting Cadence Tool Schematic Capture VSEL. VSEXL Simulation Spectre.X Technology File Rule Decks (RD) contain the following • DRC Rule Decks • LVS Rule Decks • Extraction Files CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 7 .X Techfile • Layer Defs • Design Rules • Vias • Connectivi R D DRC. tar. Connect to the directory where the PRD will be installed: cd <PRD_install_directory> Extract the PRD from the archive using the following commands: gzip -dc <path_to_PRD_tar_file>/gpdk045_<version>.0 4 Installation of the PRD The user who will own and maintain the PRD should logon to the computer. Other users will have only read and execute access. Choose a disk and directory under which the PRD will be installed. This PRD requires the following UNIX environmental variables: “CDS_Netlisting_Mode” to be set to “Analog” “CDSHOME” to be set to the Cadence DFII installation path CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 8 . read and execute access.gz | tar xf The default permissions on the PRD have already been set to allow only the owner to have write. This disk should be exported to all client machines and must be mounted consistently across all client machines.GPDK045 Reference Manual REVISION 2. defs .Directory containing the Physical Verification Rule Decks for Assura assura_tech.lib .0 5 PRD Install Directory Structure/Contents Within the <PRD_install_directory> directory there are several directories to organize the information associated with the PRD. assura .GPDK045 Reference Manual REVISION 2.lib .File containing the Cadence Assura PV initialization path cds.Directory containing the Cadence PRD documentation and the Process gpdk045 – The IC613 version of the PDK library lib.File containing the Cadence library definition file. docs .Directory containing the device spectre models CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 9 .File containing the Cadence library definition file. models . lib Where "PRD_install_directory" is the path to where the GPDK045 PRD was installed. The following UNIX links are optional but may aid the user in entering certain forms with the Cadence environment.lib" file. The user should create a "cds. "PRD_install_directory" is the path to where the GPDK045 PRD was installed. The following command can be executed in UNIX: mkdir ~/circuit_design cd ~/circuit_design All work by the user should be performed in this circuit design directory.GPDK045 Reference Manual REVISION 2.lib file: INCLUDE <PRD_install_directory>/cds.0 6 Creation of a Design Project A unique directory should be created for each circuit design project. In UNIX the following command can be used: ln -s <PRD_install_directory>/models Where. again. Using any text editor the following entry should be put in the cds. CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 10 . CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 11 . Select the gpdk045 library when asked for the name of the Attach To Technology Library. This techfile will contain all required techfile information. An ASCII version of this techfile is shipped with the PRD. Note: This PRD is using 2000uu/dbu for all layout views.GPDK045 Reference Manual REVISION 2.0 7 Technology File Methodology The GPDK045 Library techfile will be designated as the master techfile. use the command File->New->Library from either the CIW or library manager and select the Attach to an existing techfile option. This ASCII version represents the techfile currently compiled into the gpdk045 library The attach method should be used for any design library that is created. To create a new library that uses an attached techfile. This allows the design database techfile to be kept in sync with the techfile in the process PRD. from the CIW and enter the location of the display.drf file.0 8 Customizing Layer Display Properties The display. If the display.drf file (or load a new version).drf file at Cadence start-up time put the display. choose Tools->Display Resources>Merge Files. lineStyle. A display..( DisplayName ( display dots CADENCE CONFIDENTIAL StippleName Bitmap ) ( DOCUMENT DATE :15/05/2009 PAGE 12 .drf file in the Cadence start-up directory.( DisplayName PacketName Fill Outline ) Stipple ( display solid green green ) Red Green 204 102 Size Pattern ) m3 dots LineStyle ) drDefineColor( .( DisplayName ( display solid LineStyle 1 (1 1 1) ) ) drDefineStipple( . drDefinePacket( .il file whenever the gpdk045 library is opened. To manually load the display. To auto-loaded your own display.drf file is not auto-loaded and you do not manually load it.. color.drf file that you want to use.( DisplayName ( display green ColorName 0 Blue Blink ) nil ) ) drDefineLineStyle( . The packet info references predefined color. Listed below are the packet. and stipplePattern definitions for a metal3 drawing layer.drf file is automatically loaded by the libInit.drf file for the GPDK045 can be found in the PRD install directory under techFiles directory. Any of these can be changed to suit an individual user’s preferences in the project copy of the display.GPDK045 Reference Manual REVISION 2. you will get error messages about missing packets when you try to open a schematic or layout view and you will not be able to see any process specific layers. and stipplePattern definitions. lineStyle. 0 (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) (0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1) (0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0) ) CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 13 .GPDK045 Reference Manual REVISION 2. GPDK045 Reference Manual REVISION 2. CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 14 . This would prevent your designs from inheriting any fixes done to the PRD library from an upgrade. While similar parameters will inherit values. Partitioning of schematics. This would cause dependent parameters to have incorrect values. These references should not be copied locally to the project directories and the references set to the local copy of PRD cells. Users can add instances from the PRD library to designs stored in the project libraries. Users should exercise caution when querying an instance and changing the name of the cell and replacing it with a reference to another cell. Schematics should be designed with schematic driven layout methodology in mind. should be done in a clean and consistent fashion. input and output ports. care should be taken to preserve the references to the PRD libraries. callbacks are not necessarily executed.0 9 Schematic Design The user should follow the guidelines listed below while building schematics using Composer: Project libraries should list the primitive PRD library as a reference library in the library properties form. hierarchical design. When performing hierarchical copy of schematic designs. they are 2-terminal devices. Design variables are allowed for specifying parameter values on mosfet devices. These resistors are also three-terminal devices. The width and length are snapped to grid. respectively. The finger width is calculated by dividing the total width by the number of fingers. insulated. and metal. Serpentine resistor layouts are not allowed. Depending upon which value is entered into the form by the user. The insulated resistors are those that are isolated from silicon by an insulator (oxide) such as poly resistors. Calculation: The area and perimeter parameters for the sources and drains are calculated from the width and the number of fingers used. number of resistor segments (series or parallel).2 Mosfets All mosfets in the PRD library are 4 terminals. Units: The length and width are specified in meters for schematic simulation.GPDK045 Reference Manual REVISION 2. with areas and perimeters in meters squared and meters. In both cases. and the resistances are recalculated and updated on the component form based on actual dimensions. resistance value. Simulation: CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 15 . Simulation: Subcircuit definitions are used to model the resistors 10. Calculation: The user has two choices in determining how the final resistor configuration is calculated.0 10 Library Device Setup 10. the calculated values are determined based upon a combination of the length. The user may request the calculation of either the resistor length or the resistor value.1 Resistors The resistors in the library consist of three types. The diffused types include p+ and n+ and come in three-terminal varieties. width. either the total width or the finger width will be calculated using the aforementioned calculation. and contact resistance. The metal resistors are those resistors that are used as interconnect and feed-throughs. Design variables are supported for both the length and width parameters. Units: Length and width are in meters. diffused. This calculation assumes that the drain will always have the less capacitance (area) when there are an even number of fingers (odd number of diffusion areas). 10. Calculation: The area is calculated from the width and length entered. Calculation: The area is calculated from the emitter size of the device.4 Diodes All diodes in the PRD library are two-terminal. Design variables are allowed for Length and Width entries. Simulation: These BJTs are netlisted as their predefined device names for simulation purposes. Simulation: These capacitors are netlisted as their predefined device names for simulation purposes. Units: Length and width are in meters.5 Capacitor The metal capacitor is three-terminal. and 10 are available. Units: Only fixed size devices are allowed. four-terminal MOS in layout. The MOS capacitors are captured as twoterminal devices in schematics. 10.0 These mosfets are netlisted as their predefined device names for simulation purposes. Emitter sizes of 2. 10. Units: Length and width are in meters. Design variables are allowed for Length and Width entries. Simulation: These diodes are netlisted as their predefined device names for simulation purposes.3 Bipolar Transistors All BJT’s in the PRD library are 3 terminal. 5. CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 16 .GPDK045 Reference Manual REVISION 2. Calculation: The capacitance is calculated from the width and length entered. CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 17 . It has symmetric and asymmetric inductors. Calculation: The inductance value is computed using radius. space (not a variable) and number of turns. width. Units: Radius and width are in meters.0 10. Simulation: These inductors are netlisted as their predefined device names for simulation purposes.6 Inductor The inductor is three-terminal.GPDK045 Reference Manual REVISION 2. 1 volt native Vt NMOS transistor with inherited BULK • nmos2v – 1.N+ diffused resistor w/i salicide • ressndiff_2 .8 volt native Vt NMOS transistor with inherited BULK • pmos1v – 1.1 Mosfets • nmos1v .1 volt high Vt NMOS transistor with inherited BULK • nmos1v_lvt – 1.2 Resistors • resnsndiff .N+ diffused resistor w/i salicide with inherited BULK CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 18 .8 volt native Vt NMOS transistor • nmos2v_nat_3 – 1.8 volt nominal Vt PMOS transistor • pmos2v_3 .1 volt high Vt NMOS transistor • nmos1v_hvt-3 .1.GPDK045 Reference Manual REVISION 2.1 volt low Vt NMOS transistor • nmos1v_lvt_3 – 1.1 volt native Vt NMOS transistor • nmos1v_nat_3 – 1.N+ diffused resistor w/o salicide • resnsndiff_2 .P+ diffused resistor w/o salicide with inherited BULK • ressndiff .1 volt low Vt NMOS transistor with inherited BULK • nmos1v_nat – 1.0 11 Supported Devices 11.1 volt nominal Vt NMOS transistor • nmos1v_3 .1 volt nominal Vt NMOS transistor with inherited BULK • nmos1v_hvt .1 volt high Vt PMOS transistor • pmos1v_hvt_3 – 1.8 volt nominal Vt NMOS transistor • nmos2v_3 – 1.1.1.1 volt high Vt PMOS transistor with inherited BULK • pmos1v_lvt – 1.N+ diffused resistor w/o salicide with inherited BULK • resnspdiff .1 volt nominal Vt PMOS transistor • pmos1v_3 – 1.8 volt nominal Vt PMOS transistor with inherited BULK 11.1 volt low Vt PMOS transistor with inherited BULK • pmos2v .1.1 volt nominal Vt PMOS transistor with inherited BULK • pmos1v_hvt – 1.8 volt nominal Vt NMOS transistor with inherited BULK • nmos2v_nat – 1.1 volt low Vt PMOS transistor • pmos1v_lvt_3 – 1.P+ diffused resistor w/o salicide • resnspdiff_2 .1.1. P+ diffused resistor w/i salicide • resspdiff_2 .8 volt Nmos cap • pmoscap2v – 1.Vertical substrate NPN 10x10 Emitter CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 19 .Metal <k> resistor (k=1.1 volt Pmos cap • nmoscap2v – 1.N-Well resistor under STI • resnwsti_2 .Vertical substrate NPN 5x5 Emitter • npn10 .N-Well resistor under STI with inherited BULK • resnwoxide .P+ Poly resistor w/o salicide • ressppoly_2 .N+ Poly resistor w/o salicide with inherited BULK • ressppoly .Vertical substrate PNP 2x2 Emitter • vpnp5 ..N+ Poly resistor w/salicide • resnsnpoly_2 .N+ Poly resistor w/o salicide • ressnpoly_2 .P+ Poly resistor w/salicide with inherited BULK • ressnpoly .0 • resspdiff .1 volt Nmos cap • pmoscap1v – 1.P+ Poly resistor w/o salicide with inherited BULK • resm<k> .N-Well resistor under OD with inherited BULK • resnsnpoly .P+ diffused resistor w/i salicide with inherited BULK • resnwsti .GPDK045 Reference Manual REVISION 2.N-Well resistor under OD • resnwoxide_2 .N+ Poly resistor w/salicide with inherited BULK • resnsppoly .P+ Poly resistor w/salicide • resnsppoly_2 .4 Bipolars • vpnp2 .3 Capacitor • mimcap – CapMetal (Intermediate Metal 11) to Metal 10 cap • nmoscap1v – 1.Vertical substrate PNP 10x10 Emitter • npn2 .8 volt Pmos cap 11.Vertical substrate NPN 2x2 Emitter • npn5 .Vertical substrate PNP 5x5 Emitter • vpnp10 .11) 11. 1 volt high Vt P+/nwell diode • pdio_lvt – 1.GPDK045 Reference Manual REVISION 2.1 volt P+/nwell diode • pdio_hvt – 1.1 volt low Vt P+/nwell diode • pdio_2v – 1.1 volt N+/psub diode • ndio_hvt – 1.1 volt low Vt N+/psub diode • ndio_nvt – 1.5 Diodes • pdio – 1.8 volt native Vt N+/psub diode 11.8 volt P+/nwell diode • ndio – 1.6 Inductors • ind_a – Asymmetric Inductor • ind_s – Symmetric Inductor CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 20 .8 volt N+/psub diode • ndio_2v_nvt – 1.1 volt native Vt N+/psub diode • ndio_2v – 1.1 volt high Vt N+/psub diode • ndio_lvt – 1.0 11. 0 12 Views provided The following table explains the use of the cellviews provided as part of this PRD: symbol spectre hspiceD schematic auLvs auCdl ivpcell layout Used in Composer schematics Simulation / netlisting view for the Spectre & UltraSim simulator Simulation / netlisting view for the hspiceD simulator Simulation / netlisting view for all simulators. auLvs.1 Mosfets • Four terminals (D.2 Resistors • Three terminals (PLUS. auCdl. hspiceD. B) for metal mimcap capacitor • symbol. ivpcell. G.S/D/B overlapped) (G. spectre. auLvs. Device recognition symbol used in the extracted layout for netlisting purposes with DIVA and Assura Fixed cell or pcell used in Virtuoso Layout Editor.3 Capacitor • Two terminals ( really four -. hspiceD. ivpcell.GPDK045 Reference Manual REVISION 2. layout (Pcells) 12. auCdl. MINUS. ivpcell. S. It is used to implement series and parallel features in those resistors. MINUS) for metal resistors • symbol. layout (Pcells) CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 21 . auCdl. spectre. D/S/B) for mos caps • Three terminals (PLUS. auCdl. 12. Mixed-mode and logic resistors use schematic to call other simulator resistor views. Netlisting view for DIVA and Assura Circuit Descriptive Language netlisting view typically used to generate a netlist for Dracula or third party simulators. schematic. auLvs. ivpcell 12. layout (Pcells) • Resistors called in schematic views include views for all simulators. B) for diffused and poly resistors • Two terminals (PLUS. MINUS. spectre. hspiceD. B) • symbol. auLvs. symbol. spectre. B. auLvs. layout (Pcells) 12.6 CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 22 . spectre. hspiceD. auLvs. layout (Pcells) Inductors • Three terminals (PLUS. layout (Pcells) 12.0 12. spectre.5 Bipolars • Three terminals (C. MINUS) • symbol. auCdl.GPDK045 Reference Manual REVISION 2.4 Diodes • Two terminals (PLUS. E) • symbol. auCdl. ivpcell. auLvs. ivpcell. ivpcell. auCdl. MINUS. hspiceD. B) • symbol. width of each gate finger/stripe Fingers . The user may select Left and Right for an even fingered device Edit Area & Perim – allow Drain/Soure area and periphery be entered manually for simulation Drain diffusion area. Selection of all four creates a guardring • For Detached. 5.0 13 CDF parameters 13. The area and perimeter parameters are calculated and netlisted in accordance with the layouts or can be entered manually if “Edit Area & Perim” is checked CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 23 . etc.spectre model name (non-editable) Multiplier . – several simulation parameters are presented.GPDK045 Reference Manual REVISION 2. the user may specify Tap Extension (in microns) which sets the distance from the bodytie to the device. Right.gate length in meters Total Width (M) . Maximum distance is 100 microns • For Integrated. Pins are not automatically permuted and can be switched using this parameter Bodytie Type – None. or Integrated (butting source) • For Detached. 3.gate width in meters (sum of all fingers) Finger Width .number of poly gate fingers/stripes used in layout Threshold – finger width at which to apply device folding of the layout Apply Threshold – button to apply threshold or not Gate Connection – allow shorting of multi-fingered devices and addition of contact heads to gate ends S/D Connection – allow shorting of sources and/or drains on multi-finger devices S/D Metal Width – width of metal used to short sources/drains Switch S/D – source is defined as left-most diffusion region and alternating regions to the right. user may select Left. and/or Bottom to specify the located of bodyties. …).1 Mosfets Model Name .number of Parallel MOS devices Length (M) . Detached. Top. the user may select Left or Right for a device with an odd number of fingers (1. The input format should be “left 1.3 right 1. If neither pair is not present. top. right. and bottom taps would be to its original placements. a zero is assumed CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 24 .0 13. This parameter is related to the stretch handle on the taps.GPDK045 Reference Manual REVISION 2.0 bottom 2.0” without the quotes. contact resistance. and grain resistance Segment Width – resistor segment width in meters Segment Length – resistor segment length in meters Effective Width – effective resistor segment width in meters Effective Length – effective resistor segment length in meters Left Dummy – boolean value used to place a dummy resistor strip on the left side of the main resistor Right Dummy – boolean value used to place a dummy resistor strip on the right side of the main resistor Contact Rows – integer number of contact rows Contact Columns – integer number of contact columns Show Tap Params – boolean value allowing the user to set the visibility of the resistor tap properties Left Tap – boolean value used to place a resistor tap on the left side of a device Right Tap – boolean value used to place a resistor tap on the right side of a device Top Tap – boolean value used to place a resistor tap on the top side of a device Bottom Tap – boolean value used to place a resistor tap on the bottom side of a device Tap Extension – float values to set where the left. end resistance.0 top 0.2 Resistors Model Name – Spectre model name (non-editable) Segments – number of series or parallel segments for a resistor Segment Connection – cyclic field used for series or parallel segments Calculated Parameter – radio button that determines whether resistance or Length is the calculated value when instantiating a new resistor device Resistance – total resistance value equal to the sum of body resistance. Capacitance – total capacitance Length (M) . Pins are not automatically permuted and can be switched using this parameter Bodytie Type – None.width of each gate finger/stripe Fingers .gate width in meters (sum of all fingers) Finger Width .Calculated parameter cyclic (capacitance.number of poly gate fingers/stripes used in layout Gate Connection – allow shorting of multi-fingered devices and addition of contact heads to gate ends S/D Connection – allow shorting of sources and/or drains on multi-finger devices S/D Metal Width – width of metal used to short sources/drains Switch S/D – source is defined as left-most diffusion region and alternating regions to the right.3 MOScaps Model Name .0 Sheet Resistivity – sheet rho value for body of resistor (non-editable) End Resistance – resistance value for any salicided area near the contact heads in a non-salicided resistor (non-editable) Contact Resistance – resistance value for the contact heads of a particular resistor (non-editable) Grain Resistance – constant resistance value for any salicided area near the contact heads in a non-salicided resistor (non-editable) Delta Width – resistor width process variation value in meters (noneditable) Delta Length – resistor length process variation value in meters (noneditable) Temperature Coefficient 1 – temperature coefficient #1 for resistor (non-editable) Temperature Coefficient 2 – temperature coefficient #2 for resistor (non-editable) 13.number of Parallel MOS devices Calculated Parameter length. width) . or Integrated (butting source) CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 25 .GPDK045 Reference Manual REVISION 2.gate length in meters Total Width (M) .spectre model name (non-editable) Multiplier . Detached. the user may select Left or Right for a device with an odd number of fingers (1. The user may select Left and Right for an even fingered device Area capacitance – Capacitance per unit area used in parameter calculations (non-editable) Fringe capacitance – Fringe Capacitance of perimeter used in parameter calculations (non-editable) Temp rise from ambient. user may select Left. 13. 5. the user may specify Tap Extension (in microns) which sets the distance from the bodytie to the device. Maximum distance is 100 microns • For Integrated. …). – several simulation parameters are presented. etc. Selection of all four creates a guardring • For Detached. 'width' or 'length' Device Area Calculated junction area in meters squared (non-editable) Length (M) Diode length in meters Width (M) Diode width in meters Multiplier Number of Parallel Diode devices Periphery of junction Calculated junction periphery in meters (non-editable) Diodes CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 26 .4 Bipolars Model name Model name used in simulation Device Area Emitter area in microns squared (noneditable Emitter width Emitter width microns (non-editable) Multiplier Number of Parallel Bipolar devices Estimated operating region Simulation operating region Model name Model used for simulation name Calculate Parameter Choices are 'area' .GPDK045 Reference Manual REVISION 2. and/or Bottom to specify the located of bodyties. Top. 3. Right.0 • For Detached. Inductor Space Space between each metal turns in meters (non-editable) Multiplier Number of Parallel Inductor devices Number of Turns Number of metal turns of Inductor in cyclic field. CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 27 .0 13.GPDK045 Reference Manual REVISION 2.5 Inductors Model Model used for simulation name Inductance (H) Inductance value in Henry Inner Radius Inner Radius of Inductor in meters Inductor Width Width of each metal turns in meters. The following model sections are defined in the <PRD_install_directory>/models/spectre/gpdk045.scs file. Ultrasim. and AMS circuit simulators.0 14 Model Setup This PRD supports the Cadence Spectre. Section tt ff ss fs sf mc tt – Typical N and P model parameters ff – Fast N and P model parameters ss – Slow N and P model parameters fs – Fast N and slow P model parameters sf – Slow N and Fast P model parameters mc – Monte Carlo model parameters CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 28 .GPDK045 Reference Manual REVISION 2. The customer is free to modify the display.GPDK045 Reference Manual REVISION 2.drf file used on-site to achieve any desired display. and will not support desired changes to the display.0 15 Techfile Layers Cadence will provide a standard display setup. CDS # GDS # 2 4 6 10 11 12 13 14 15 16 18 20 26 27 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 30 1 24 2 3 18 4 23 5 52 72 19 6 26 27 7 8 9 10 11 30 31 32 33 34 35 37 38 39 40 41 42 151 152 161 162 7 GDS CDS name type 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 CADENCE CONFIDENTIAL Oxide Oxide_thk Nwell Poly Nhvt Nimp Phvt Pimp Nzvt SiProt Nburied Cont Nlvt Plvt Metal1 Via1 Metal2 Via2 Metal3 Via3 Metal4 Via4 Metal5 Via5 Metal6 Via6 Metal7 Via7 Metal8 Via8 Metal9 Via9 Metal10 Via10 Metal11 Metal1 CDS purpose Description drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing pin Oxide Thick Oxide Nwell Poly N+ high Vt implant N+ implant P+ high Vt implant P+ implant Native Nmos Salicide Blocking N buried Contact N+ low Vt implant P+ low Vt implant Metal1 Via1 Metal2 Via2 Metal3 Via3 Metal4 Via4 Metal5 Via5 Metal6 Via6 Metal7 Via7 Metal8 Via8 Metal9 Via9 Metal10 Via10 Metal11 Pin purpose DOCUMENT DATE :15/05/2009 PAGE 29 . 0 Metal2 Metal3 Metal4 Metal5 Metal6 Metal7 Metal8 Metal9 Metal10 Metal11 Metal1 Metal2 Metal3 Metal4 Metal5 Metal6 Metal7 Metal8 Metal9 Metal10 Metal11 Metal1 Metal2 Metal3 Metal4 Metal5 Metal6 Metal7 Metal8 Metal9 Metal10 Metal11 Metal1 Metal2 Metal3 Metal4 Metal5 Metal6 Metal7 Metal8 Metal9 Metal10 Metal11 Psub DIOdummy PNPdummy pin pin pin pin pin pin pin pin pin pin label label label label label label label label label label label fill fill fill fill fill fill fill fill fill fill fill slot slot slot slot slot slot slot slot slot slot slot drawing drawing drawing Pin purpose Pin purpose Pin purpose Pin purpose Pin purpose Pin purpose Pin purpose Pin purpose Pin purpose Pin purpose Label purpose Label purpose Label purpose Label purpose Label purpose Label purpose Label purpose Label purpose Label purpose Label purpose Label purpose Fill purpose Fill purpose Fill purpose Fill purpose Fill purpose Fill purpose Fill purpose Fill purpose Fill purpose Fill purpose Fill purpose Slot purpose Slot purpose Slot purpose Slot purpose Slot purpose Slot purpose Slot purpose Slot purpose Slot purpose Slot purpose Slot purpose P substrate Recognition layer for diodes Recognition layer for pnp DOCUMENT DATE :15/05/2009 PAGE 30 .GPDK045 Reference Manual 34 38 42 46 50 54 58 62 66 70 30 34 38 42 46 50 54 58 62 66 70 30 34 38 42 46 50 54 58 62 66 70 71 72 73 74 75 76 77 78 79 66 70 80 82 84 9 11 31 33 35 38 40 42 152 162 7 9 11 31 33 35 38 40 42 152 162 7 9 11 31 33 35 38 40 42 152 162 7 9 11 31 33 35 38 40 42 152 162 25 22 21 1 1 1 1 1 1 1 1 1 1 3 3 3 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 5 5 5 2 2 2 2 2 2 2 2 2 2 2 0 0 0 CADENCE CONFIDENTIAL REVISION 2. 0 PWdummy NPNdummy VPNP2dum IND2dummy VPNP5dum INDdummy VPNP10dum BJTdum Cap3dum Resdum Bondpad Capdum CapMetal ResWdum M1Resdum M2Resdum M3Resdum M4Resdum M5Resdum M6Resdum M7Resdum M8Resdum M9Resdum M10Resdum M11Resdum IND3dummy ESDdummy drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing drawing Recognition Recognition Recognition Recognition Recognition Recognition Recognition Recognition Recognition Recognition Recognition Recognition Recognition Recognition Recognition Recognition Recognition Recognition Recognition Recognition Recognition Recognition Recognition Recognition Recognition Recognition Recognition DOCUMENT DATE :15/05/2009 layer for substrate layer for npn layer for vpnp2x2 layer for inductor layer for vpnp5x5 layer for inductor layer for vpnp10x10 layer for vpnp’s layer for moscap layer for resistor layer for bondpad layer for moscap layer for moscap layer for resistor layer for metal res1 layer for metal res2 layer for metal res3 layer for metal res4 layer for metal res5 layer for metal res6 layer for metal res7 layer for metal res8 layer for metal res9 layer for metal res10 layer for metal res11 layer for inductor layer for esd PAGE 31 .GPDK045 Reference Manual 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 114 115 85 20 60 17 61 16 62 15 84 13 36 12 14 71 75 76 77 78 79 80 81 82 83 93 103 70 74 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CADENCE CONFIDENTIAL REVISION 2. Pin permuting of MOSFET and Resistor device is also supported.GXL The standard Cadence Virtuoso Layout design flow will be implemented. Schematic Driven Layout is recommended over Netlist Driven Layout.0 16 Virtuoso L. wells. The skill pcell layouts are compiled into the PRD. The users should follow the guidelines listed below for layout design: The Virtuoso Layout tool requires a separate license for operation. Abutment is currently supported only for MOS transistors. The Router rules file for the target process is provided with the PRD. and substrate. Names will be displayed on the layout views to aid in schematic-layout instance correlation. Auto-abutment of MOSFET devices is supported. This includes basic connectivity of connection layers. The Virtuoso Custom Router (VCR) and Virtuoso Shape Based Router (VSR) can be used to finish the unconnected interconnect in the layout. Users obtain maximum leverage from the PRD by doing schematic driven layout in the Virtuoso Layout environment. abutment will work only on schematic driven layouts.GPDK045 Reference Manual REVISION 2. The M factor will be used for device instance multiplier there will be no conflict with the parameter used in cell operation. and symbolic contacts. This flow will produce a correct by design layout. NOTE: Skill pcell source code is not included in the PRD kit.XL. Note. CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 32 . rul 17. 17. The files are: • divaDRC.rul 17.0 17 Diva Decks These decks can be found in the extracted PRD directory tree located under the ‘gpdk045’ directory.1 Diva DRC Those files are based on the design rules outlined in the design rule manual. The file is: • divaEXT.GPDK045 Reference Manual REVISION 2. The file is: • divaLVS.3 Diva LVS Diva LVS ruldeck is for compare and parameter check.rul CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 33 .2 Diva Extract Diva Extract file is for extraction of all devices in PDK. rul • compare. and LVS rule files from the documentation provided.1 Assura DRC The Assura DRC file includes DRC check as well as antenna and density checks • assuraDRC. These decks can be found in the extracted PRD directory tree in the directory: • assura 18.3 Assura QRC The Assura QRC files are also located inside assura directory. EXT.GPDK045 Reference Manual REVISION 2. • assura/rcx – directory where assura QRC files are provided CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 34 .2 Assura LVS The Assura LVS files provided are named • extract.0 18 Assura Decks Cadence has developed the Assura DRC.rul 18.rul 18. • Dog bone gate • Configurable source-drain connection for multi fingered devices.0 19 GPDK045 Pcell Layouts 19. Tab can be configured. • Optional tap placement for four terminal device. alternate) • Variable source/drain contact coverage with stretch handles on each contact strap.both) • Configurable gate straps for multi fingered devices (top.bottom. Pins access direction needs to allow routing with CCAR.source. both. • VXL ready connectivity.GPDK045 Reference Manual REVISION 2.left.1 Mos Pcell • Multi-fingered gates. (top. ‘Dog bone’ Gate CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 35 .(gate.right) Spacing between device and tab can be controlled by stretch handle. • Auto abutment enabled. • Permute properties on all pins. bottom. Both) Stretchable tap to device spacing CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 36 .Right.Top.Top. (Left.Bottom) Number of contacts is configurable Stretchable Source/Drain Contact straps Drain/Source strapping (Source.Both) Configurable Gate straping (None.Drain.GPDK045 Reference Manual REVISION 2.0 Configurable Taps. Bottom. • Dog bone • VXL ready connectivity • Optional etch guard resistors • Permute properties on all pins Series or parallel configuration Optional Etch Guard Dummies CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 Configurable number of contacts PAGE 37 .GPDK045 Reference Manual REVISION 2.0 19.2 Resistor Pcell • Parallel/Series configuration with metal straps. 0 19.GPDK045 Reference Manual REVISION 2.3 Capacitor Pcell • Configurable width. length or capacitance CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 38 . GPDK045 Reference Manual REVISION 2.0 19.4 Diode Pcell • Configurable width. length or area CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 39 . 0 19.5 Bipolar Pcell • BJT is a fixed layout CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 40 .GPDK045 Reference Manual REVISION 2. 6 Inductor Pcell • Configurable width.0 19. turns and radius CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 41 .GPDK045 Reference Manual REVISION 2. 0n nf=1 as=5.0n M=1.16e-9 DIVA LVS Netlist DIVA Device Name = “nmos1v” .GPDK045 Reference Manual REVISION 2.6e-12 \ ps=8.0 l 180e-9 w 4e-6 " CDL Netlist CDL Device Name = “nmos1v” MNM1 D G S B nmos1v W=4u L=180.6e-12 ad=5. DOCUMENT DATE :15/05/2009 PAGE 42 ..28u m=1 nrs=35m nrd=35m sa=0.1 nmos1v datasheet nmos1v Spectre Netlist Spectre Model Name = “gpdk045_nmos1v” NM1 (D G S B) gpdk045_nmos1v w=4u l=180. m 1 CADENCE CONFIDENTIAL l 1.8e-07 w 4e-06 .14e-9 sb=0.14e-9 sd=0.0 20 GPDK045 Device Datasheets 20.28u pd=8. i NM1 nmos1v D G S B . * 4 pins * 4 nets S (p D S). nmos1v Instance /NM1 = auLvs device M1 d nmos1v D G S B (p D S) i 1 nmos1v D G S B " m 1.0 Assura Netlist Assura auLvs Device Name = “nmos1v” c nmos1v MOS D B GB SB B B . 0 Width Length nmos1v – 1.GPDK045 Reference Manual REVISION 2.2 volt nominal VT NMOS transistor Device Layers Layer Color and Fill Oxide Nimp Poly Cont Metal1 Device Derivation Device Layer Derivation Recognition OXIDE AND NIMP CONTAINS POLY G Poly D Oxide AND Nimp NOT Poly S Oxide AND Nimp NOT Poly B Substrate LVS Comparison Parameter Calculation Length POLY INTERSECTING OXIDE (ILLUSTRATED ABOVE) Width Poly inside Oxide (illustrated above) • S and D are PERMUTABLE CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 43 . 2 nmos1v_hvt datasheet nmos1v_hvt Spectre Netlist Spectre Model Name = “gpdk045_nmos1v_hvt” NM1 (D G S B) gpdk045_nmos1v_hvt w=4u l=180.0n nf=1 as=5.14e-9 sb=0.28u pd=8.0 Assura Netlist Assura auLvs Device Name = “nmos1v_hvt” c nmos1v_hvt MOS D B GB SB B B .6e-12 \ ps=8.14e-9 sd=0.16e-9 DIVA LVS Netlist DIVA Device Name = “nmos1v_hvt” . * 4 pins * 4 nets S (p D S).0 20.8e-07 w 4e-06 .0n M=1. nmos1v_hvt Instance /NM1 = auLvs device M1 d nmos1v_hvt D G S B (p D S) i 1 nmos1v_hvt D G S B " m 1.6e-12 ad=5.0 l 180e-9 w 4e-6 " CDL Netlist CDL Device Name = “nmos1v_hvt” MNM1 D G S B nmos1v_hvt W=4u L=180. DOCUMENT DATE :15/05/2009 PAGE 44 .28u m=1 nrs=35m nrd=35m sa=0.. i NM1 nmos1v_hvt D G S B . m 1 CADENCE CONFIDENTIAL l 1.GPDK045 Reference Manual REVISION 2. 2 volt high VT NMOS transistor Device Layers Layer Color and Fill Oxide Nimp & Nhvt Poly Cont Metal1 Device Derivation Device Layer Derivation Recognition OXIDE AND NIMP AND NHVT CONTAINS POLY G Poly D Oxide AND Nimp AND Nhvt NOT Poly S Oxide AND Nimp AND Nhvt NOT Poly B Substrate LVS Comparison Parameter Calculation Length POLY INTERSECTING OXIDE (ILLUSTRATED ABOVE) Width Poly inside Oxide (illustrated above) * S and D are PERMUTABLE CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 45 .GPDK045 Reference Manual REVISION 2.0 Width Length nmos1v_hvt – 1. 0n nf=1 as=5.3 nmos1v_lvt datasheet Spectre Netlist Spectre Model Name = “gpdk045_nmos1v_lvt” NM1 (D G S B) gpdk045_nmos1v_lvt w=4u l=180.. i NM1 nmos1v_lvt D G S B . * 4 pins * 4 nets S (p D S).0 l 180e-9 w 4e-6 " CDL Netlist CDL Device Name = “nmos1v_lvt” MNM1 D G S B nmos1v_lvt W=4u L=180.28u m=1 nrs=35m nrd=35m sa=0.GPDK045 Reference Manual REVISION 2. DOCUMENT DATE :15/05/2009 PAGE 46 .16e-9 DIVA LVS Netlist DIVA Device Name = “nmos1v_lvt” .14e-9 sb=0.0 20.6e-12 ad=5. m 1 CADENCE CONFIDENTIAL l 1.8e-07 w 4e-06 .6e-12 \ ps=8.28u pd=8. nmos1v_lvt Instance /NM1 = auLvs device M1 d nmos1v_lvt D G S B (p D S) i 1 nmos1v_lvt D G S B " m 1.14e-9 sd=0.0n M=1.0 Assura Netlist Assura auLvs Device Name = “nmos1v_lvt” c nmos1v_lvt MOS D B GB SB B B . GPDK045 Reference Manual REVISION 2.0 Width Length nmos1v_lvt – 1.2 volt low VT NMOS transistor Device Layers Layer Color and Fill Oxide Nimp & Nlvt Poly Cont Metal1 Device Derivation Device Layer Derivation Recognition OXIDE AND NIMP AND NHVT CONTAINS POLY G Poly D Oxide AND Nimp AND Nlvt NOT Poly S Oxide AND Nimp AND Nlvt NOT Poly B Substrate LVS Comparison Parameter Calculation Length POLY INTERSECTING OXIDE (ILLUSTRATED ABOVE) Width Poly inside Oxide (illustrated above) * S and D are PERMUTABLE CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 47 . 28u m=1 nrs=35m nrd=35m sa=0.0n nf=1 as=5..0 l 900e-9 w 4e-6 " CDL Netlist CDL Device Name = “nmos1v_nat” MNM1 D G S B nmos1v_nat W=4u L=900.0 20. * 4 pins * 4 nets S (p D S). m 1 CADENCE CONFIDENTIAL l 9.28u pd=8.6e-12 ad=5.16e-9 DIVA LVS Netlist DIVA Device Name = “nmos1v_nat” .4 nmos1v_nat datasheet nmos1v_nat l:900n w:4u Spectre Netlist Spectre Model Name = “gpdk045_nmos1v_nat” NM1 (D G S B) gpdk045_nmos1v_nat w=4u l=180. DOCUMENT DATE :15/05/2009 PAGE 48 .6e-12 \ ps=8. nmos1v_nat Instance /NM1 = auLvs device M1 d nmos1v_nat D G S B (p D S) i 1 nmos1v_nat D G S B " m 1.14e-9 sd=0.0 Assura Netlist Assura auLvs Device Name = “nmos1v_nat” c nmos1v_nat MOS D B GB SB B B .GPDK045 Reference Manual REVISION 2. i NM1 nmos1v_nat D G S B .14e-9 sb=0.0e-07 w 4e-06 .0n M=1. GPDK045 Reference Manual REVISION 2.0 Width Length nmos1v_nat – 1.2 volt native VT MOS transistor Device Layers Layer Color and Fill Oxide Nimp & Nzvt Poly Cont Metal1 Device Derivation Device Layer Derivation Recognition OXIDE AND NIMP AND NZVT CONTAINS POLY G Poly D Oxide AND Nimp AND Nzvt NOT Poly S Oxide AND Nimp AND NzvtT Poly B Substrate LVS Comparison Parameter Calculation Length POLY INTERSECTING OXIDE (ILLUSTRATED ABOVE) Width Poly inside Oxide (illustrated above) * S and D are PERMUTABLE CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 49 . GPDK045 Reference Manual REVISION 2. nmos2v Instance /NM1 = auLvs device M1 d nmos2v D G S B (p D S) i 1 nmos2v D G S B " m 1. i NM1 nmos2v D G S B .14e-9 sb=0.0n nf=1 as=5.0n M=1.0 Assura Netlist Assura auLvs Device Name = “nmos2v” c nmos2v MOS D B GB SB B B .8e-07 w 4e-06 .6e-12 ad=5. * 4 pins * 4 nets S (p D S). DOCUMENT DATE :15/05/2009 PAGE 50 ..16e-9 DIVA LVS Netlist DIVA Device Name = “nmos2v” .0 l 280e-9 w 4e-6 " CDL Netlist CDL Device Name = “nmos2v” MNM1 D G S B nmos2v W=4u L=280.0 20.28u pd=8. m 1 CADENCE CONFIDENTIAL l 2.14e-9 sd=0.6e-12 \ ps=8.28u m=1 nrs=35m nrd=35m sa=0.5 nmos2v datasheet nmos2v l:280n Spectre Netlist Spectre Model Name = “gpdk045_nmos2v” NM1 (D G S B) gpdk045_nmos2v w=4u l=280. GPDK045 Reference Manual REVISION 2.8 volt nominal VT NMOS transistor Device Layers Layer Color and Fill Oxide_thk Oxide Nimp Poly Cont Metal1 Device Derivation Device Layer Derivation Recognition OXIDE_THK AND OXIDE AND NIMP CONTAINS POLY G Poly D Oxide_thk AND Oxide AND Nimp NOT Poly S Oxide_thk AND Oxide AND Nimp NOT Poly B Substrate LVS Comparison Parameter Calculation Length POLY INTERSECTING OXIDE (ILLUSTRATED ABOVE) Width Poly inside Oxide (illustrated above) • S and D are PERMUTABLE CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 51 .0 Length nmos2v – 1. 15e-9 sb=0.5m sa=0. DOCUMENT DATE :15/05/2009 PAGE 52 .18e-9 DIVA LVS Netlist DIVA Device Name = “nmos2v_nat” . nmos2v_nat Instance /NM1 = auLvs device M1 d nmos2v_nat D G S B (p D S) i 1 nmos2v_nat D G S B " m 1. * 4 pins * 4 nets S (p D S).0e-07 w 4e-06 . m 1 CADENCE CONFIDENTIAL l 9.0n M=1..15e-9 sd=0.0 l 900e-9 w 4e-6 " CDL Netlist CDL Device Name = “nmos2v_nat” MNM1 D G S B nmos2v_nat W=4u L=900.6 nmos2v_nat datasheet nmos2v_nat l:900n Spectre Netlist Spectre Model Name = “gpdk045_nmos2v_nat” NM1 (D G S B) gpdk045_nmos2v_nat w=4u l=900.3u pd=8.0 Assura Netlist Assura auLvs Device Name = “nmos2v_nat” c nmos2v_nat MOS D B GB SB B B .GPDK045 Reference Manual REVISION 2.3u m=1 nrs=37. i NM1 nmos2v_nat D G S B .5m nrd=37.0 20.0n nf=1 as=6e-12 ad=6e-12 \ ps=8. 8 volt Native VT NMOS transistor Device Layers Layer Color and Fill Oxide_thk Oxide Nimp & Nzvt Poly Cont Metal1 Device Derivation Device Layer Derivation Recognition OXIDE_THK AND OXIDE AND NIMP AND NZVT CONTAINS POLY G Poly D Oxide_thk AND Oxide AND Nimp AND Nzvt NOT Poly S Oxide_thk AND Oxide AND Nimp AND Nzvt NOT Poly B Substrate LVS Comparison Parameter Calculation Length POLY INTERSECTING OXIDE (ILLUSTRATED ABOVE) Width Poly inside Oxide (illustrated above) • S and D are PERMUTABLE CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 53 .0 Length nmos2v_nat – 1.GPDK045 Reference Manual REVISION 2. 28u m=1 nrs=35m nrd=35m sa=0. * 4 pins * 4 nets S (p D S).0 20.14e-9 sd=0.0n nf=1 as=5.0n M=1.0e-07 w 4e-06 . i MP1 pmos1v D G S B . m 1 CADENCE CONFIDENTIAL l 1.6e-12 \ ps=8.0 l 100e-9 w 4e-6 " CDL Netlist CDL Device Name = “pmos1v” MPM1 D G S B pmos1v W=4u L=100.28u pd=8.GPDK045 Reference Manual REVISION 2.0 Assura Netlist Assura auLvs Device Name = “pmos1v” c pmos1v MOS D B GB SB B B .16e-9 DIVA LVS Netlist DIVA Device Name = “pmos1v” .7 pmos1v datasheet pmos1v Spectre Netlist Spectre Model Name = “gpdk045_pmos1v” PM1 (D G S B) gpdk045_pmos1v w=4u l=180.. pmos1v Instance /PM1 = auLvs device M1 d pmos1v D G S B (p D S) i 1 pmos1v D G S B " m 1. DOCUMENT DATE :15/05/2009 PAGE 54 .14e-9 sb=0.6e-12 ad=5. 2 volt nominal VT PMOS transistor Device Layers Layer Color and Fill Nwell Oxide Pimp Poly Cont Metal1 Device Derivation Device Layer Derivation Recognition NWELL AND OXIDE AND PIMP CONTAINS POLY G Poly D Nwell AND Oxide AND Pimp NOT Poly S Nwell AND Oxide AND Pimp NOT Poly B Nwell LVS Comparison Parameter Calculation Length POLY INTERSECTING OXIDE (ILLUSTRATED ABOVE) Width Poly inside Oxide (illustrated above) * S and D are PERMUTABLE CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 55 .0 Width Length pmos1v – 1.GPDK045 Reference Manual REVISION 2. 8 pmos1v_hvt datasheet pmos1v_hvt Spectre Netlist Spectre Model Name = “gpdk045_pmos1v_hvt” PM1 (D G S B) gpdk045_pmos1v_hvt w=4u l=180.6e-12 \ ps=8.. * 4 pins * 4 nets S (p D S). m 1 CADENCE CONFIDENTIAL l 1.28u m=1 nrs=35m nrd=35m sa=0.16e-9 DIVA LVS Netlist DIVA Device Name = “pmos1v_hvt” .0 l 100e-9 w 4e-6 " CDL Netlist CDL Device Name = “pmos1v_hvt” MPM1 D G S B pmos1v_hvt W=4u L=100.14e-9 sd=0.6e-12 ad=5.0n M=1.GPDK045 Reference Manual REVISION 2.0 Assura Netlist Assura auLvs Device Name = “pmos1v_hvt” c pmos1v_hvt MOS D B GB SB B B .0n nf=1 as=5.28u pd=8.0e-07 w 4e-06 . DOCUMENT DATE :15/05/2009 PAGE 56 .0 20.14e-9 sb=0. pmos1v_hvt Instance /PM1 = auLvs device M1 d pmos1v_hvt D G S B (p D S) i 1 pmos1v_hvt D G S B " m 1. i MP1 pmos1v_hvt D G S B . GPDK045 Reference Manual REVISION 2.2 volt high VT PMOS transistor Device Layers Layer Color and Fill Nwell Oxide Pimp & Phvt Poly Cont Metal1 Device Derivation Device Layer Derivation Recognition NWELL AND OXIDE AND PIMP AND PHVT CONTAINS POLY G Poly D Nwell AND Oxide AND Pimp AND Phvt NOT Poly S Nwell AND Oxide AND Pimp AND Phvt NOT Poly B Nwell LVS Comparison Parameter Calculation Length POLY INTERSECTING OXIDE (ILLUSTRATED ABOVE) Width Poly inside Oxide (illustrated above) • S and D are PERMUTABLE CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 57 .0 Width Length pmos1v_hvt – 1. .0e-07 w 4e-06 .0n M=1.0 l 100e-9 w 4e-6 " CDL Netlist CDL Device Name = “pmos1v_lvt” MPM1 D G S B pmos1v_lvt W=4u L=100. i MP1 pmos1v_lvt D G S B .14e-9 sd=0.28u pd=8.0 20. DOCUMENT DATE :15/05/2009 PAGE 58 . pmos1v_lvt Instance /PM1 = auLvs device M1 d pmos1v_lvt D G S B (p D S) i 1 pmos1v_lvt D G S B " m 1.0 Assura Netlist Assura auLvs Device Name = “pmos1v_lvt” c pmos1v_lvt MOS D B GB SB B B .9 pmos1v_lvt datasheet pmos1v_lvt Spectre Netlist Spectre Model Name = “gpdk045_pmos1v_lvt” PM1 (D G S B) gpdk045_pmos1v_lvt w=4u l=180.16e-9 DIVA LVS Netlist DIVA Device Name = “pmos1v_lvt” .28u m=1 nrs=35m nrd=35m sa=0.GPDK045 Reference Manual REVISION 2.14e-9 sb=0.6e-12 ad=5.0n nf=1 as=5. m 1 CADENCE CONFIDENTIAL l 1. * 4 pins * 4 nets S (p D S).6e-12 \ ps=8. 0 Width Length pmos1v_lvt – 1.2 volt low VT PMOS transistor Device Layers Layer Color and Fill Nwell Oxide Pimp & Plvt Poly Cont Metal1 Device Derivation Device Layer Derivation Recognition NWELL AND OXIDE AND PIMP AND PHVT CONTAINS POLY G Poly D Nwell AND Oxide AND Pimp AND Plvt NOT Poly S Nwell AND Oxide AND Pimp AND Plvt NOT Poly B Nwell LVS Comparison Parameter Calculation Length POLY INTERSECTING OXIDE (ILLUSTRATED ABOVE) Width Poly inside Oxide (illustrated above) • S and D are PERMUTABLE CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 59 .GPDK045 Reference Manual REVISION 2. 0 20.0n M=1.0 Assura Netlist Assura auLvs Device Name = “pmos2v” c pmos2v MOS D B GB SB B B .6e-12 ad=5.0 l 150e-9 w 4e-6 " CDL Netlist CDL Device Name = “pmos2v” MPM1 D G S B pmos2v W=4u L=150. i MP1 pmos2v D G S B . * 4 pins * 4 nets S (p D S).5e-07 w 4e-06 . DOCUMENT DATE :15/05/2009 PAGE 60 ..GPDK045 Reference Manual REVISION 2. pmos2v Instance /PM1 = auLvs device M1 d pmos2v D G S B (p D S) i 1 pmos2v D G S B " m 1.28u m=1 nrs=35m nrd=35m sa=0.14e-9 sb=0.6e-12 \ ps=8. m 1 CADENCE CONFIDENTIAL l 1.28u pd=8.10 pmos2v datasheet pmos2v Spectre Netlist Spectre Model Name = “gpdk045_pmos2v” PM1 (D G S B) gpdk045_pmos2v w=4u l=180.0n nf=1 as=5.16e-9 DIVA LVS Netlist DIVA Device Name = “pmos2v” .14e-9 sd=0. GPDK045 Reference Manual REVISION 2.0 Width Length pmos2v – 1.8 volt nominal VT PMOS transistor Device Layers Layer Color and Fill Nwell Oxide & Oxide_thk Pimp Poly Cont Metal1 Device Derivation Device Layer Derivation Recognition NWELL AND OXIDE AND OXIDE_THK AND PIMP CONTAINS POLY G Poly D Nwell AND Oxide AND Oxide_thk AND Pimp NOT Poly S Nwell AND Oxide AND Oxide_thk AND Pimp NOT Poly B Nwell LVS Comparison Parameter Calculation Length POLY INTERSECTING OXIDE (ILLUSTRATED ABOVE) Width Poly inside Oxide (illustrated above) • S and D are PERMUTABLE CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 61 . 11 resm1-resm11 datasheet r:320m segW:2u segL:8u segments:1 Series resm1 Spectre Netlist Spectre Model Name = “gpdk045_resm1” R1 (MINUS PLUS) resm1_pcell1 segL=8u segW=2u Subckt resm1_pcell1 MINUS PLUS Parameters segL=8u segW=2u R0 (PLUS MINUS) gpdk045_resm1 l=segL w=segW Ends resm1_pcell1 DIVA LVS Netlist DIVA Device Name = “resm1” .. r 0. resm1 Instance /R1 = auLvs device R1 d resm1 PLUS MINUS (p PLUS MINUS) i 1 resm1 PLUS MINUS " r 320e-3 w 2e-6 l 8e-6" CDL Netlist CDL Device Name = “resm1” RR1 PLUS MINUS $[resm1] r=320m w=2u l=8u Assura Netlist Assura auLvs Device Name = “ resm1 ” c resm1 RES PLUS B MINUS B .0 20. * 2 pins * 2 nets S (p PLUS MINUS) . i R1 resm1 PLUS MINUS .32 w 2e-06 l=8e-06.GPDK045 Reference Manual REVISION 2. CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 62 . GPDK045 Reference Manual REVISION 2.0 Width Length resm1 – Metal resistor Device Layers Layer Color and Fill M1Resdum (Marker Layer) Metal1 Device Derivation Device Layer Derivation Recognition METAL1 AND M1RESDUM PLUS Metal1 TOUCHING M1Resdum MINUS Metal1 TOUCHING M1Resdum LVS Comparison Parameter Calculation Length METAL1 AND M1RESDUM LENGTH (ILLUSTRATED ABOVE) Width Metal1 AND M1Resdum Width (illustrated above) Resistance sheet resistance * Length / Width * PLUS and MINUS are PERMUTABLE * The same format is used for resm2-resm11 as is used with resm1 * Only the metal sheet rho and device name changes * Only the metal layer and recognition layer changes CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 63 . GPDK045 Reference Manual REVISION 2.0 20.12 resnsndiff datasheet r:537.333 segW:1.5u resnsndiff segL:8u segments:1 Series Spectre Netlist Spectre Model Name = “gpdk045_resnsndiff” R1 (B MINUS PLUS) resnsndiff_pcell1 segL=8u segW=1.5u Subckt resnsndiff_pcell1 B MINUS PLUS Parameters segL=8u segW=1.5u R0 (PLUS MINUS B) gpdk045_resnsndiff l=segL w=segW Ends resnsndiff_pcell1 DIVA LVS Netlist DIVA Device Name = “resnsndiff” ; resnsndiff Instance /R1 = auLvs device R1 d resnsndiff PLUS MINUS B (p PLUS MINUS) i 1 resnsndiff PLUS MINUS B " r 537.333 w 1.5e-6 l 8e-6" CDL Netlist CDL Device Name = “resnsndiff” RR1 PLUS MINUS B $[resnsndiff] r=537.333 w=1.5u l=8u Assura Netlist Assura auLvs Device Name = “ resnsndiff ” c resnsndiff RES PLUS B MINUS B B I ;; * 3 pins * 3 nets S (p PLUS MINUS) ; i R1 resnsndiff PLUS MINUS B ; r 537.333 w 1.5e-06 l=8e-06; CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 64 GPDK045 Reference Manual REVISION 2.0 Width Length resnsndiff – N+ diffused resistor without salicide Device Layers Layer Color and Fill Oxide Nimp SiProt & Resdum (Marker Layer) Cont Metal1 Device Derivation Device Layer Derivation Recognition OXIDE AND NIMP AND SIPROT AND RESDUM PLUS Oxide AND Nimp NOT Resdum MINUS Oxide AND Nimp NOT Resdum B Substrate LVS Comparison Parameter Calculation Length SIPROT LENGTH (ILLUSTRATED ABOVE) Width Oxide Width (illustrated above) Resistance sheet resistance * Length / Width * PLUS and MINUS are PERMUTABLE CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 65 GPDK045 Reference Manual REVISION 2.0 20.13 resnsnpoly datasheet r:537.333 segW:1.5u resnsnpoly segL:8u segments:1 Series Spectre Netlist Spectre Model Name = “gpdk045_resnsnpoly” R1 (B MINUS PLUS) resnsnpoly_pcell1 segL=8u segW=1.5u Subckt resnsnpoly_pcell1 B MINUS PLUS Parameters segL=8u segW=1.5u R0 (PLUS MINUS B) gpdk045_resnsnpoly l=segL w=segW Ends resnsnpoly_pcell1 DIVA LVS Netlist DIVA Device Name = “resnsnpoly” ; resnsnpoly Instance /R1 = auLvs device R1 d resnsnpoly PLUS MINUS B (p PLUS MINUS) i 1 resnsnpoly PLUS MINUS B " r 537.333 w 1.5e-6 l 8e-6" CDL Netlist CDL Device Name = “resnsnpoly” RR1 PLUS MINUS B $[resnsnpoly] r=537.333 w=1.5u l=8u Assura Netlist Assura auLvs Device Name = “ resnsnpoly ” c resnsnpoly RES PLUS B MINUS B B I ;; * 3 pins * 3 nets S (p PLUS MINUS) ; i R1 resnsnpoly PLUS MINUS B ; r 537.333 w 1.5e-06 l=8e-06; CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 66 0 Width Length resnsnpoly – N+ poly resistor without salicide Device Layers Layer Color and Fill Poly Nimp SiProt & Resdum (Marker Layer) Cont Metal1 Device Derivation Device Layer Derivation Recognition POLY AND NIMP AND SIPROT AND RESDUM PLUS Poly AND Nimp NOT Resdum MINUS Poly AND Nimp NOT Resdum LVS Comparison Parameter Calculation Length SIPROT LENGTH (ILLUSTRATED ABOVE) Width Poly Width (illustrated above) Resistance sheet resistance * Length / Width * PLUS and MINUS are PERMUTABLE CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 67 .GPDK045 Reference Manual REVISION 2. 5e-6 l 8e-6" CDL Netlist CDL Device Name = “resnspdiff” RR1 PLUS MINUS B $[resnspdiff] r=804 w=1.5e-06 l=8e-06.5u l=8u Assura Netlist Assura auLvs Device Name = “ resnspdiff ” c resnspdiff RES PLUS B MINUS B B I .14 resnspdiff datasheet r:804 segW:1.0 20. r 804 w 1.5u resnspdiff segL:8u segments:1 Series Spectre Netlist Spectre Model Name = “gpdk045_resnspdiff” R1 (B MINUS PLUS) resnspdiff_pcell1 segL=8u segW=1. resnspdiff Instance /R1 = auLvs device R1 d resnspdiff PLUS MINUS B (p PLUS MINUS) i 1 resnspdiff PLUS MINUS B " r 804 w 1.5u R0 (PLUS MINUS B) gpdk045_resnspdiff l=segL w=segW Ends resnspdiff_pcell1 DIVA LVS Netlist DIVA Device Name = “resnspdiff” . CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 68 .GPDK045 Reference Manual REVISION 2.. i R1 resnspdiff PLUS MINUS B .5u Subckt resnspdiff_pcell1 B MINUS PLUS Parameters segL=8u segW=1. * 3 pins * 3 nets S (p PLUS MINUS) . 0 Width Length resnspdiff – P+ diffused resistor without salicide Device Layers Layer Color and Fill Oxide Pimp SiProt & Resdum (Marker Layer) Cont Metal1 Device Derivation Device Layer Derivation Recognition OXIDE AND PIMP AND SIPROT AND RESDUM PLUS Oxide AND Pimp NOT Resdum MINUS Oxide AND Pimp NOT Resdum B Substrate LVS Comparison Parameter Calculation Length SIPROT LENGTH (ILLUSTRATED ABOVE) Width Oxide Width (illustrated above) Resistance sheet resistance * Length / Width • PLUS and MINUS are PERMUTABLE CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 69 .GPDK045 Reference Manual REVISION 2. resnsppoly Instance /R1 = auLvs device R1 d resnsppoly PLUS MINUS B (p PLUS MINUS) i 1 resnsppoly PLUS MINUS B " r 2137.33 w 1.5e-06 l=8e-06.0 20. r 2137.5u R0 (PLUS MINUS B) gpdk045_resnsppoly l=segL w=segW Ends resnsppoly_pcell1 DIVA LVS Netlist DIVA Device Name = “resnsppoly” .33 w=1.33 w 1.5u Subckt resnsppoly_pcell1 B MINUS PLUS Parameters segL=8u segW=1.15 resnsppoly datasheet r:2.5u resnsppoly resnsnpoly segL:8u segments:1 Series Spectre Netlist Spectre Model Name = “gpdk045_resnsppoly” R1 (B MINUS PLUS) resnsppoly_pcell1 segL=8u segW=1..GPDK045 Reference Manual REVISION 2.5e-6 l 8e-6" CDL Netlist CDL Device Name = “resnsppoly” RR1 PLUS MINUS B $[resnsppoly] r=2137.5u l=8u Assura Netlist Assura auLvs Device Name = “ resnsppoly ” c resnsppoly RES PLUS B MINUS B B I .13733K segW:1. * 3 pins * 3 nets S (p PLUS MINUS) . CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 70 . i R1 resnsppoly PLUS MINUS B . GPDK045 Reference Manual REVISION 2.0 Width Length resnsppoly – P+ poly resistor without salicide Device Layers Layer Color and Fill Poly Pimp SiProt & Resdum (Marker Layer) Cont Metal1 Device Derivation Device Layer Derivation Recognition POLY AND PIMP AND SIPROT AND RESDUM PLUS Poly AND Pimp NOT Resdum MINUS Poly AND Pimp NOT Resdum LVS Comparison Parameter Calculation Length SIPROT LENGTH (ILLUSTRATED ABOVE) Width Poly Width (illustrated above) Resistance sheet resistance * Length / Width * PLUS and MINUS are PERMUTABLE CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 71 . .3333 w 1.5u R0 (PLUS MINUS B) gpdk045_ressndiff l=segL w=segW Ends ressndiff_pcell1 DIVA LVS Netlist DIVA Device Name = “ressndiff” .5u l=8u Assura Netlist Assura auLvs Device Name = “ ressndiff ” c ressndiff RES PLUS B MINUS B B I .5e-6 l 8e-6" CDL Netlist CDL Device Name = “ressndiff” RR1 PLUS MINUS B $[ressndiff] r=57. r 57.5u ressndiff segL:8u segments:1 Series Spectre Netlist Spectre Model Name = “gpdk045_ressndiff” R1 (B MINUS PLUS) ressndiff_pcell1 segL=8u segW=1.16 ressndiff datasheet r:57.3333 w 1.GPDK045 Reference Manual REVISION 2. CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 72 .3333 segW:1. i R1 ressndiff PLUS MINUS B .5e-06 l=8e-06. ressndiff Instance /R1 = auLvs device R1 d ressndiff PLUS MINUS B (p PLUS MINUS) i 1 ressndiff PLUS MINUS B " r 57.5u Subckt ressndiff_pcell1 B MINUS PLUS Parameters segL=8u segW=1.0 20. * 3 pins * 3 nets S (p PLUS MINUS) .3333 w=1. GPDK045 Reference Manual REVISION 2.0 Width Length ressndiff – N+ diffused resistor with salicide Device Layers Layer Color and Fill Oxide Nimp Resdum (Marker Layer) Cont Metal1 Device Derivation Device Layer Derivation Recognition OXIDE AND NIMP AND RESDUM NOT SIPROT PLUS Oxide AND Nimp NOT Resdum MINUS Oxide AND Nimp NOT Resdum B Substrate LVS Comparison Parameter Calculation Length RESDUM LENGTH (ILLUSTRATED ABOVE) Width Oxide Width (illustrated above) Resistance sheet resistance * Length / Width • PLUS and MINUS are PERMUTABLE CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 73 . r 57.5u l=8u Assura Netlist Assura auLvs Device Name = “ ressnpoly ” c ressnpoly RES PLUS B MINUS B B I . i R1 ressnpoly PLUS MINUS B .3333 w 1.5u Subckt ressnpoly_pcell1 B MINUS PLUS Parameters segL=8u segW=1.GPDK045 Reference Manual REVISION 2.5u R0 (PLUS MINUS B) gpdk045_ressnpoly l=segL w=segW Ends ressnpoly_pcell1 DIVA LVS Netlist DIVA Device Name = “ressnpoly” .0 20. CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 74 . ressnpoly Instance /R1 = auLvs device R1 d ressnpoly PLUS MINUS B (p PLUS MINUS) i 1 ressnpoly PLUS MINUS B " r 57..5e-06 l=8e-06. * 3 pins * 3 nets S (p PLUS MINUS) .17 ressnpoly datasheet r:57.3333 w=1.3333 w 1.5u ressnpoly resnsnpoly segL:8u segments:1 Series Spectre Netlist Spectre Model Name = “gpdk045_ressnpoly” R1 (B MINUS PLUS) ressnpoly_pcell1 segL=8u segW=1.5e-6 l 8e-6" CDL Netlist CDL Device Name = “ressnpoly” RR1 PLUS MINUS B $[ressnpoly] r=57.3333 segW:1. 0 Width Length ressnpoly – N+ poly resistor with salicide Device Layers Layer Color and Fill Poly Nimp Resdum (Marker Layer) Cont Metal1 Device Derivation Device Layer Derivation Recognition POLY AND NIMP AND RESDUM NOT SIPROT PLUS Poly AND Nimp NOT Resdum MINUS Poly AND Nimp NOT Resdum LVS Comparison Parameter Calculation Length RESDUM LENGTH (ILLUSTRATED ABOVE) Width Poly Width (illustrated above) Resistance sheet resistance * Length / Width • PLUS and MINUS are PERMUTABLE CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 75 .GPDK045 Reference Manual REVISION 2. . resspdiff Instance /R1 = auLvs device R1 d resspdiff PLUS MINUS B (p PLUS MINUS) i 1 resspdiff PLUS MINUS B " r 57. i R1 resspdiff PLUS MINUS B .3333 segW:1.5e-6 l 8e-6" CDL Netlist CDL Device Name = “resspdiff” RR1 PLUS MINUS B $[resspdiff] r=57.5u l=8u Assura Netlist Assura auLvs Device Name = “ resspdiff ” c resspdiff RES PLUS B MINUS B B I .GPDK045 Reference Manual REVISION 2. r 57.18 resspdiff datasheet r:57.5u resspdiff segL:8u segments:1 Series Spectre Netlist Spectre Model Name = “gpdk045_resspdiff” R1 (B MINUS PLUS) resspdiff_pcell1 segL=8u segW=1. CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 76 .5e-06 l=8e-06.5u R0 (PLUS MINUS B) gpdk045_resspdiff l=segL w=segW Ends resspdiff_pcell1 DIVA LVS Netlist DIVA Device Name = “resspdiff” .3333 w=1.3333 w 1.3333 w 1.5u Subckt resspdiff_pcell1 B MINUS PLUS Parameters segL=8u segW=1. * 3 pins * 3 nets S (p PLUS MINUS) .0 20. GPDK045 Reference Manual REVISION 2.0 Width Length resspdiff – P+ diffused resistor with salicide Device Layers Layer Color and Fill Oxide Pimp Resdum (Marker Layer) Cont Metal1 Device Derivation Device Layer Derivation Recognition OXIDE AND PIMP AND RESDUM NOT SIPROT PLUS Oxide AND Pimp NOT Resdum MINUS Oxide AND Pimp NOT Resdum B Substrate LVS Comparison Parameter Calculation Length RESDUM LENGTH (ILLUSTRATED ABOVE) Width Oxide Width (illustrated above) Resistance sheet resistance * Length / Width • PLUS and MINUS are PERMUTABLE CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 77 GPDK045 Reference Manual REVISION 2.0 20.19 ressppoly datasheet r: 57.3333 segW:1.5u ressppoly resnsnpoly segL:8u segments:1 Series Spectre Netlist Spectre Model Name = “gpdk045_ressppoly” R1 (B MINUS PLUS) ressppoly_pcell1 segL=8u segW=1.5u Subckt ressppoly_pcell1 B MINUS PLUS Parameters segL=8u segW=1.5u R0 (PLUS MINUS B) gpdk045_ressppoly l=segL w=segW Ends ressppoly_pcell1 DIVA LVS Netlist DIVA Device Name = “ressppoly” ; ressppoly Instance /R1 = auLvs device R1 d ressppoly PLUS MINUS B (p PLUS MINUS) i 1 ressppoly PLUS MINUS B " r 57.3333 w 1.5e-6 l 8e-6" CDL Netlist CDL Device Name = “ressppoly” RR1 PLUS MINUS B $[ressppoly] r=57.3333 w=1.5u l=8u Assura Netlist Assura auLvs Device Name = “ ressppoly ” c ressppoly RES PLUS B MINUS B B I ;; * 3 pins * 3 nets S (p PLUS MINUS) ; i R1 ressppoly PLUS MINUS B ; r 57.3333 w 1.5e-06 l=8e-06; CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 78 GPDK045 Reference Manual REVISION 2.0 Width Length ressppoly – P+ poly resistor with salicide Device Layers Layer Color and Fill Poly Pimp Resdum (Marker Layer) Cont Metal1 Device Derivation Device Layer Derivation Recognition POLY AND PIMP AND RESDUM NOT SIPROT PLUS Poly AND Pimp NOT Resdum MINUS Poly AND Pimp NOT Resdum LVS Comparison Parameter Calculation Length RESDUM LENGTH (ILLUSTRATED ABOVE) Width Poly Width (illustrated above) Resistance sheet resistance * Length / Width • PLUS and MINUS are PERMUTABLE CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 79 5u l=8u Assura Netlist Assura auLvs Device Name = “ resnwoxide ” c resnwoxide RES PLUS B MINUS B B I .. CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 80 .GPDK045 Reference Manual REVISION 2.20 resnwoxide datasheet r:2.5u R0 (PLUS MINUS B) gpdk045_resnwoxide l=segL w=segW Ends resnwoxide_pcell1 DIVA LVS Netlist DIVA Device Name = “resnwoxide” .5e-06 l=8e-06.14K segW:1.5u Subckt resnwoxide_pcell1 B MINUS PLUS Parameters segL=8u segW=1. i R1 resnwoxide PLUS MINUS B . resnwoxide Instance /R1 = auLvs device R1 d resnwoxide PLUS MINUS B (p PLUS MINUS) i 1 resnwoxide PLUS MINUS B " r 2140 w 1. * 3 pins * 3 nets S (p PLUS MINUS) .5e-6 l 8e-6" CDL Netlist CDL Device Name = “resnwoxide” RR1 PLUS MINUS B $[resnwoxide] r=2140 w=1.0 20.5u resnwoxide segL:8u segments:1 Series Spectre Netlist Spectre Model Name = “gpdk045_resnwoxide” R1 (B MINUS PLUS) resnwoxide_pcell1 segL=8u segW=1. r 2140 w 1. GPDK045 Reference Manual REVISION 2.0 Width Length resnwoxide – Nwell Resistor within diffusion Device Layers Layer Color and Fill Oxide Nwell Nimp ResWdum (Marker Layer) Cont Metal1 Device Derivation Device Layer Derivation Recognition OXIDE AND NWELL AND SIPROT AND RESWDUM PLUS Oxide AND Nwell NOT ResWdum MINUS Oxide AND Nwell NOT ResWdum B Substrate LVS Comparison Parameter Calculation Length RESWDUM LENGTH (ILLUSTRATED ABOVE) Width Nwell Width (illustrated above) Resistance sheet resistance * Length / Width * PLUS and MINUS are PERMUTABLE CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 81 . 5e-6 l 8e-6" CDL Netlist CDL Device Name = “resnwsti” RR1 PLUS MINUS B $[resnwsti] r=2140 w=1. i R1 resnwsti PLUS MINUS B .0 20.5e-06 l=8e-06.5u R0 (PLUS MINUS B) gpdk045_resnwsti l=segL w=segW Ends resnwsti_pcell1 DIVA LVS Netlist DIVA Device Name = “resnwsti” .. * 3 pins * 3 nets S (p PLUS MINUS) .5u segL:8u segments:1 Series resnwsti Spectre Netlist Spectre Model Name = “gpdk045_resnwsti” R1 (B MINUS PLUS) resnwsti_pcell1 segL=8u segW=1.5u Subckt resnwsti_pcell1 B MINUS PLUS Parameters segL=8u segW=1. CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 82 .14K segW:1.5u l=8u Assura Netlist Assura auLvs Device Name = “ resnwsti ” c resnwsti RES PLUS B MINUS B B I . r 2140 w 1. resnwsti Instance /R1 = auLvs device R1 d resnwsti PLUS MINUS B (p PLUS MINUS) i 1 resnwsti PLUS MINUS B " r 2140 w 1.21 resnwsti datasheet r:2.GPDK045 Reference Manual REVISION 2. 0 Width Length resnwsti – Nwell Resistor Under STI Device Layers Layer Color and Fill Oxide Nwell Nimp ResWdum (Marker Layer) Cont Metal1 Device Derivation Device Layer Derivation Recognition NWELL AND RESWDUM PLUS Nwell NOT ResWdum MINUS Nwell NOT ResWdum B Substrate LVS Comparison Parameter Calculation Length RESWDUM LENGTH (ILLUSTRATED ABOVE) Width Nwell Width (illustrated above) Resistance sheet resistance * Length / Width • PLUS and MINUS are PERMUTABLE CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 83 .GPDK045 Reference Manual REVISION 2. .0 " CDL Netlist CDL Device Name = “mimcap” CC1 PLUS MINUS 16e-12 $[mimcap] m=1 Assura Netlist Assura auLvs Device Name = “mimcap” c mimcap CAP PLUS B MINUS B .0 20.GPDK045 Reference Manual REVISION 2. mimcap Instance /C1 = auLvs device C1 d mimcap PLUS MINUS (p PLUS MINUS) i 1 mimcap PLUS MINUS " area 16e-12 m 1.22 mimcap datasheet mimcap Spectre Netlist Spectre Model Name = “gpdk045_mimcap” C1 (PLUS MINUS) gpdk045_mimcap area=16e-12 perim=16e-6 m=1 DIVA LVS Netlist DIVA Device Name = “mimcap” . * 2 pins * 2 nets S (p PLUS MINUS) i C1 mimcap PLUS MINUS . CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 84 . area 16e-12 m 1 . 0 Area mimcap – Metal / Metal capacitor Device Layers Layer Color and Fill Metal 2 CapMetal Via2 Metal3 Device Derivation Device Layer Derivation Recognition CAPMETAL AND METAL2 PLUS CapMetal MINUS Metal2 UNDER CapMetal LVS Comparison Parameter Calculation Area AREA OF CAPMETAL (ILLUSTRATED ABOVE) Perimeter Perimeter of CapMetal CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 85 .GPDK045 Reference Manual REVISION 2. 0 20.23 nmoscap1v datasheet G nmoscap1v D/S/B Spectre Netlist Spectre Model Name = “gpdk045_nmoscap1v” M1 (D G S B) gpdk045_nmoscap1v w=10u l=10u m=(1)*(1) DIVA LVS Netlist DIVA Device Name = “nmoscap1v” . m 1 CADENCE CONFIDENTIAL l 1e-05 w 1e-05 .GPDK045 Reference Manual REVISION 2.0 l 10e-6 w 10e-6 " CDL Netlist CDL Device Name = “nmoscap1v” MM1 D G S B nmoscap1v W=10u L=10u M=1 Assura Netlist Assura auLvs Device Name = “nmoscap1v” c nmoscap1v MOS D B GB SB B B . nmoscap1v Instance /M1 = auLvs device M1 d nmoscap1v D G S B (p D S) i 1 nmoscap1v D G S B " m 1. * 4 pins * 4 nets S (p D S). DOCUMENT DATE :15/05/2009 PAGE 86 .. i M1 nmoscap1v D G S B . 0 Width Length nmoscap1v – 1.GPDK045 Reference Manual REVISION 2.2 volt NMOS capacitor Device Layers Layer Color and Fill Capdum Oxide Nimp Poly Cont Metal1 Device Derivation Device Layer Derivation Recognition CAPDUM AND OXIDE AND NIMP CONTAINS POLY TOP Poly BOT Capdum AND Oxide AND Nimp NOT Poly B Substrate LVS Comparison Parameter Calculation Length POLY INTERSECTING OXIDE (ILLUSTRATED ABOVE) Width Poly inside Oxide (illustrated above) * Nmos Source. and Body are Shorted Together CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 87 . Drain. 24 nmoscap2v datasheet G nmoscap2v D/S/B Spectre Netlist Spectre Model Name = “gpdk045_nmoscap2v” M1 (D G S B) gpdk045_nmoscap2v w=10u l=10u m=(1)*(1) DIVA LVS Netlist DIVA Device Name = “nmoscap2v” . nmoscap2v Instance /M1 = auLvs device M1 d nmoscap2v D G S B (p D S) i 1 nmoscap2v D G S B " m 1. m 1 CADENCE CONFIDENTIAL l 1e-05 w 1e-05 . * 4 pins * 4 nets S (p D S).GPDK045 Reference Manual REVISION 2. DOCUMENT DATE :15/05/2009 PAGE 88 .0 l 10e-6 w 10e-6 " CDL Netlist CDL Device Name = “nmoscap2v” MM1 D G S B nmoscap2v W=10u L=10u M=1 Assura Netlist Assura auLvs Device Name = “nmoscap2v” c nmoscap2v MOS D B GB SB B B .0 20. i M1 nmoscap2v D G S B .. Drain.GPDK045 Reference Manual REVISION 2.0 Width Length nmoscap2v – 1.8 volt NMOS capacitor Device Layers Layer Color and Fill Capdum Oxide & Oxide_thk Nimp Poly Cont Metal1 Device Derivation Device Layer Derivation Recognition CAPDUM AND OXIDE AND OXIDE_THK AND NIMP CONTAINS POLY TOP Poly BOT Capdum AND Oxide AND Oxide_thk AND Nimp NOT Poly B Substrate LVS Comparison Parameter Calculation Length POLY INTERSECTING OXIDE (ILLUSTRATED ABOVE) Width Poly inside Oxide (illustrated above) * Nmos Source. and Body are Shorted Together CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 89 . m 1 CADENCE CONFIDENTIAL l 1e-05 w 1e-05 . * 4 pins * 4 nets S (p D S).25 pmoscap1v datasheet G pmoscap1v D/S/B Spectre Netlist Spectre Model Name = “gpdk045_pmoscap1v” M1 (D G S B) gpdk045_pmoscap1v w=10u l=10u m=(1)*(1) DIVA LVS Netlist DIVA Device Name = “pmoscap1v” .0 l 10e-6 w 10e-6 " CDL Netlist CDL Device Name = “pmoscap1v” MM1 D G S B pmoscap1v W=10u L=10u M=1 Assura Netlist Assura auLvs Device Name = “pmoscap1v” c pmoscap1v MOS D B GB SB B B . i M1 pmoscap1v D G S B .GPDK045 Reference Manual REVISION 2.0 20. DOCUMENT DATE :15/05/2009 PAGE 90 .. pmoscap1v Instance /M1 = auLvs device M1 d pmoscap1v D G S B (p D S) i 1 pmoscap1v D G S B " m 1. 0 Width Length pmoscap1v – 1.GPDK045 Reference Manual REVISION 2.2 volt PMOS capacitor Device Layers Layer Color and Fill Nwell Capdum Oxide Pimp Poly Cont Metal1 Device Derivation Device Layer Derivation Recognition CAPDUM AND OXIDE AND PIMP AND NWELL CONTAINS POLY TOP Poly BOT Capdum AND Oxide AND Pimp AND Nwell NOT Poly B Substrate LVS Comparison Parameter Calculation Length POLY INTERSECTING OXIDE (ILLUSTRATED ABOVE) Width Poly inside Oxide (illustrated above) * Pmos Source. Drain. and Body are Shorted Together CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 91 . 0 l 10e-6 w 10e-6 " CDL Netlist CDL Device Name = “pmoscap2v” MM1 D G S B pmoscap2v W=10u L=10u M=1 Assura Netlist Assura auLvs Device Name = “pmoscap2v” c pmoscap2v MOS D B GB SB B B .GPDK045 Reference Manual REVISION 2.0 20.. i M1 pmoscap2v D G S B . * 4 pins * 4 nets S (p D S).26 pmoscap2v datasheet G pmoscap2v D/S/B Spectre Netlist Spectre Model Name = “gpdk045_pmoscap2v” M1 (D G S B) gpdk045_pmoscap2v w=10u l=10u m=(1)*(1) DIVA LVS Netlist DIVA Device Name = “pmoscap2v” . m 1 CADENCE CONFIDENTIAL l 1e-05 w 1e-05 . pmoscap2v Instance /M1 = auLvs device M1 d pmoscap2v D G S B (p D S) i 1 pmoscap2v D G S B " m 1. DOCUMENT DATE :15/05/2009 PAGE 92 . Drain.GPDK045 Reference Manual REVISION 2. and Body are Shorted Together CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 93 .0 Width Length pmoscap2v – 1.8 volt PMOS capacitor Device Layers Layer Color and Fill Nwell Capdum Oxide Pimp Poly Cont Metal1 Device Derivation Device Layer Derivation Recognition CAPDUM AND OXIDE AND PIMP AND NWELL CONTAINS POLY TOP Poly BOT Capdum AND Oxide AND Pimp AND Nwell NOT Poly B Substrate LVS Comparison Parameter Calculation Length POLY INTERSECTING OXIDE (ILLUSTRATED ABOVE) Width Poly inside Oxide (illustrated above) * Pmos Source. GPDK045 Reference Manual REVISION 2. DOCUMENT DATE :15/05/2009 PAGE 94 . area 4 m 1 CADENCE CONFIDENTIAL .. vpnp2 Instance /Q0 = auLvs device Q0 d vpnp C B E i 0 vpnp2 C B E " area 4.27 vpnp2 datasheet Vpnp2 Spectre Netlist Spectre Model Name = “gpdk045_vpnp2” Q0 ( C B E ) gpdk045_vpnp2 area=4 m=1 DIVA LVS Netlist DIVA Device Name = “vpnp2” .0 Assura Netlist Assura auLvs Device Name = “vpnp2” c vpnp2 BJT C B BB EB .0 20.0 " CDL Netlist CDL Device Name = “vpnp2” QQ0 C B E vpnp2 M=1 area=4. * 3 pins * 3 nets i Q0 vpnp2 C B E.0 m 1. 2 volt vertical substrate PNP with 2x2 fixed emitter Device Layers Layer Color and Fill BJTdummy Nwell Nimp / Oxide Pimp / Oxide Cont Metal3 Device Derivation Device Layer Derivation Recognition BJTDUMMY CONTAINS NIMP AND PIMP E BJTDummy AND Pimp And Oxide AND Nwell B BJTDummy AND Nimp And Oxide AND Nwell C BJTDummy AND Pimp And Oxide ANDNOT Nwell LVS Comparison Parameter Calculation Area AREA OF EMITTER (ILLUSTRATED ABOVE) CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 95 .GPDK045 Reference Manual REVISION 2.0 C B E Area C vpnp2 – 1. GPDK045 Reference Manual REVISION 2.0 Assura Netlist Assura auLvs Device Name = “vpnp5” c vpnp BJT C B BB EB . DOCUMENT DATE :15/05/2009 PAGE 96 .0 m 1.0 " CDL Netlist CDL Device Name = “vpnp5” QQ0 C B E vpnp5 M=1 area=25.0 20.28 vpnp5 datasheet Vpnp5 Spectre Netlist Spectre Model Name = “gpdk045_vpnp5” Q0 ( C B E ) gpdk045_vpnp5 area=25 m=1 DIVA LVS Netlist DIVA Device Name = “vpnp5” . * 3 pins * 3 nets i Q0 vpnp5 C B E. area 25 m 1 CADENCE CONFIDENTIAL . vpnp5 Instance /Q0 = auLvs device Q0 d vpnp C B E i 0 vpnp5 C B E " area 25.. GPDK045 Reference Manual REVISION 2.2 volt vertical substrate PNP with 5x5 fixed emitter Device Layers Layer Color and Fill BJTdummy Nwell Nimp / Oxide Pimp / Oxide Cont Metal3 Device Derivation Device Layer Derivation Recognition BJTDUMMY CONTAINS NIMP AND PIMP E BJTDummy AND Pimp And Oxide AND Nwell B BJTDummy AND Nimp And Oxide AND Nwell C BJTDummy AND Pimp And Oxide ANDNOT Nwell LVS Comparison Parameter Calculation Area AREA OF EMITTER (ILLUSTRATED ABOVE) CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 97 .0 C C B E Area vpnp5 – 1. 29 vpnp10 datasheet Vpnp10 Spectre Netlist Spectre Model Name = “gpdk045_vpnp10” Q0 ( C B E ) gpdk045_vpnp10 area=100 m=1 DIVA LVS Netlist DIVA Device Name = “vpnp10” . * 3 pins * 3 nets i Q0 vpnp10 C B E.0 Assura Netlist Assura auLvs Device Name = “vpnp10” c vpnp BJT C B BB EB . DOCUMENT DATE :15/05/2009 PAGE 98 .0 m 1. vpnp10 Instance /Q0 = auLvs device Q0 d vpnp C B E i 0 vpnp10 C B E " area 100.0 20. area 100 m 1 CADENCE CONFIDENTIAL .GPDK045 Reference Manual REVISION 2.0 " CDL Netlist CDL Device Name = “vpnp10” QQ0 C B E vpnp10 M=1 area=100.. 0 C B E Area C vpnp10 – 1.2 volt vertical substrate PNP with 10x10 fixed emitter Device Layers Layer Color and Fill BJTdummy Nwell Nimp / Oxide Pimp / Oxide Cont Metal3 Device Derivation Device Layer Derivation Recognition BJTDUMMY CONTAINS NIMP AND PIMP E BJTDummy AND Pimp And Oxide AND Nwell B BJTDummy AND Nimp And Oxide AND Nwell C BJTDummy AND Pimp And Oxide ANDNOT Nwell LVS Comparison Parameter Calculation Area AREA OF EMITTER (ILLUSTRATED ABOVE) CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 99 .GPDK045 Reference Manual REVISION 2. 0 m 1. area 4.30 npn2 datasheet Spectre Netlist Spectre Model Name = “gpdk045_npn2” Q1 ( C B E ) gpdk045_npn2 area=4.0 20.. i Q1 npn2 C B E .0 " CDL Netlist CDL Device Name = “npn2” QQ1 C B E npn2 area=4. * 3 pins * 3 nets * 0 instances CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 100 .0 m=1 Assura Netlist Assura auLvs Device Name = “npn2” c npn2 BJT C B BB EB .GPDK045 Reference Manual REVISION 2.0 m 1 . npn2 Instance /Q1 = auLvs device Q1 d npn2 C B E i 1 npn2 C B E " area 4.0 m=1 DIVA LVS Netlist DIVA Device Name = “npn2” . GPDK045 Reference Manual REVISION 2.2 volt vertical substrate NPN with 2x2 fixed emitter Device Layers Layer Color and Fill BJTdummy Nwell Nimp / Oxide Pimp / Oxide Cont Metal3 Device Derivation Device Layer Derivation Recognition BJTDUMMY CONTAINS NIMP AND PIMP E BJTDummy AND Pimp And Oxide AND Nwell B BJTDummy AND Nimp And Oxide AND Nwell C BJTDummy AND Pimp And Oxide ANDNOT Nwell LVS Comparison Parameter Calculation Area AREA OF EMITTER (ILLUSTRATED ABOVE) CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 101 .0 C B E Area C npn2 – 1. GPDK045 Reference Manual REVISION 2.0 20.31 npn5 datasheet Spectre Netlist Spectre Model Name = “gpdk045_npn5” Q1 ( C B E ) gpdk045_npn5 area=25.0 m=1 DIVA LVS Netlist DIVA Device Name = “npn5” ; npn5 Instance /Q1 = auLvs device Q1 d npn5 C B E i 1 npn5 C B E " area 25.0 m 1.0 " CDL Netlist CDL Device Name = “npn5” QQ1 C B E npn5 area=25.0 m=1 Assura Netlist Assura auLvs Device Name = “npn5” c npn5 BJT C B BB EB ;; * 3 pins * 3 nets * 0 instances i Q1 npn5 C B E ; area 25.0 m 1 CADENCE CONFIDENTIAL ; DOCUMENT DATE :15/05/2009 PAGE 102 GPDK045 Reference Manual REVISION 2.0 C B E Area C npn5 – 1.2 volt vertical substrate NPN with 5x5 fixed emitter Device Layers Layer Color and Fill BJTdummy Nwell Nimp / Oxide Pimp / Oxide Cont Metal3 Device Derivation Device Layer Derivation Recognition BJTDUMMY CONTAINS NIMP AND PIMP E BJTDummy AND Pimp And Oxide AND Nwell B BJTDummy AND Nimp And Oxide AND Nwell C BJTDummy AND Pimp And Oxide ANDNOT Nwell LVS Comparison Parameter Calculation Area AREA OF EMITTER (ILLUSTRATED ABOVE) CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 103 GPDK045 Reference Manual REVISION 2.0 20.32 npn10 datasheet Spectre Netlist Spectre Model Name = “gpdk045_npn10” Q1 ( C B E ) gpdk045_npn10 area=100.0 m=1 DIVA LVS Netlist DIVA Device Name = “npn10” ; npn10 Instance /Q1 = auLvs device Q1 d npn10 C B E i 1 npn10 C B E " area 100.0 m 1.0 " CDL Netlist CDL Device Name = “npn10” QQ1 C B E npn10 area=100.0 m=1 Assura Netlist Assura auLvs Device Name = “npn10” c npn10 BJT C B BB EB ;; * 3 pins * 3 nets * 0 instances i Q1 npn10 C B E ; area 100.0 m 1 CADENCE CONFIDENTIAL ; DOCUMENT DATE :15/05/2009 PAGE 104 0 C B E Area C npn10 – 1.2 volt vertical substrate NPN with 10x10 fixed emitter Device Layers Layer Color and Fill BJTdummy Nwell Nimp / Oxide Pimp / Oxide Cont Metal3 Device Derivation Device Layer Derivation Recognition BJTDUMMY CONTAINS NIMP AND PIMP E BJTDummy AND Pimp And Oxide AND Nwell B BJTDummy AND Nimp And Oxide AND Nwell C BJTDummy AND Pimp And Oxide ANDNOT Nwell LVS Comparison Parameter Calculation Area AREA OF EMITTER (ILLUSTRATED ABOVE) CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 105 .GPDK045 Reference Manual REVISION 2. ndio Instance /D0 = auLvs device D0 d ndio PLUS MINUS i 0 ndio PLUS MINUS " area 1e-12 pj 1.6e-6 m 1. DOCUMENT DATE :15/05/2009 PAGE 106 .GPDK045 Reference Manual REVISION 2.33 ndio datasheet Spectre Netlist Spectre Model Name = “gpdk045_ndio” D0 ( PLUS MINUS ) gpdk045_ndio area=160f pj=1.6e-6 m 1 CADENCE CONFIDENTIAL .0 20.6u m=1 DIVA LVS Netlist DIVA Device Name = “ndio” ..0 " CDL Netlist CDL Device Name = “ndio” DD0 PLUS MINUS ndio 160f 1. area 1e-12 pj 1. * 2 pins * 2 nets i D0 ndio PLUS MINUS .6u m=1 Assura Netlist Assura auLvs Device Name = “ndio” c ndio DIO PLUS B MINUS B . 2 volt N+/Psub diode Device Layers Layer Color and Fill DIOdummy Nimp / Oxide Pimp / Oxide Cont Metal1 Device Derivation Device Layer Derivation Recognition DIODUMMY AND NIMP PLUS DIOdummy AND Pimp MINUS DIOdummy AND Nimp LVS Comparison Parameter Calculation area Area of MINUS (illustrated above) CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 107 .0 PLUS MINUS Area ndio – 1.GPDK045 Reference Manual REVISION 2. 6e-6 m 1 CADENCE CONFIDENTIAL . DOCUMENT DATE :15/05/2009 PAGE 108 .6u m=1 Assura Netlist Assura auLvs Device Name = “pdio” c pdio DIO PLUS B MINUS B . * 2 pins * 2 nets i D0 pdio PLUS MINUS . area 1.6u m=1 DIVA LVS Netlist DIVA Device Name = “pdio” .0 " CDL Netlist CDL Device Name = “pdio” DD0 PLUS MINUS pdio 160f 1. pdio Instance /D0 = auLvs device D0 d pdio PLUS MINUS i 0 pdio PLUS MINUS " area 160e-15 pj 1.0 20.6e-6 m 1.GPDK045 Reference Manual REVISION 2.34 pdio datasheet Spectre Netlist Spectre Model Name = “gpdk045_pdio” D0 ( PLUS MINUS ) gpdk045_pdio area=160f pj=1..6e-13 pj 1. GPDK045 Reference Manual REVISION 2.2 volt P+/Nwell diode Device Layers Layer Color and Fill DIOdummy Nwell Nimp / Oxide Pimp / Oxide Cont Metal1 Device Derivation Device Layer Derivation Recognition DIODUMMY AND PIMP AND NWELL PLUS DIOdummy AND Pimp AND Nwell MINUS DIOdummy AND Nimp AND Nwell LVS Comparison Parameter area CADENCE CONFIDENTIAL Calculation Area of PLUS (illustrated above) DOCUMENT DATE :15/05/2009 PAGE 109 .0 PLUS MINUS Area pdio – 1. ndio_lvt Instance /D0 = auLvs device D0 d ndio_lvt PLUS MINUS i 0 ndio_lvt PLUS MINUS " area 1e-12 pj 1.6u m=1 Assura Netlist Assura auLvs Device Name = “ndio_lvt” c ndio_lvt DIO PLUS B MINUS B .6e-6 m 1 CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 . * 2 pins * 2 nets i D0 ndio_lvt PLUS MINUS .GPDK045 Reference Manual REVISION 2.0 20.6u m=1 DIVA LVS Netlist DIVA Device Name = “ndio_lvt” . PAGE 110 . area 1e-12 pj 1..6e-6 m 1.0 " CDL Netlist CDL Device Name = “ndio_lvt” DD0 PLUS MINUS ndio_lvt 160f 1.35 ndio_lvt datasheet ndio_lvt Spectre Netlist Spectre Model Name = “gpdk045_ndio_lvt” D0 ( PLUS MINUS ) gpdk045_ndio_lvt area=160f pj=1. GPDK045 Reference Manual REVISION 2.2 volt low VT N+/Psub diode Device Layers Layer Color and Fill DIOdummy Nimp / Oxide Pimp / Oxide Cont Metal1 Nlvt Device Derivation Device Layer Derivation Recognition DIODUMMY AND NIMP PLUS DIOdummy AND Pimp MINUS DIOdummy AND Nimp LVS Comparison Parameter Calculation area Area of MINUS (illustrated above) CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 111 .0 PLUS MINUS Area ndio_lvt – 1. 6e-6 m 1.6u m=1 Assura Netlist Assura auLvs Device Name = “ndio_lvt” c ndio_hvt DIO PLUS B MINUS B .6u m=1 DIVA LVS Netlist DIVA Device Name = “ndio_hvt” .0 " CDL Netlist CDL Device Name = “ndio_hvt” DD0 PLUS MINUS ndio_hvt 160f 1. ndio_hvt Instance /D0 = auLvs device D0 d ndio_hvt PLUS MINUS i 0 ndio_hvt PLUS MINUS " area 1e-12 pj 1. area 1e-12 pj 1.GPDK045 Reference Manual REVISION 2. PAGE 112 . * 2 pins * 2 nets i D0 ndio_hvt PLUS MINUS .6e-6 m 1 CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 .0 20.36 ndio_hvt datasheet ndio_hvt Spectre Netlist Spectre Model Name = “gpdk045_ndio_hvt” D0 ( PLUS MINUS ) gpdk045_ndio_hvt area=160f pj=1.. 0 PLUS MINUS Area ndio_hvt – 1.2 volt high VT N+/Psub diode Device Layers Layer Color and Fill DIOdummy Nimp / Oxide Pimp / Oxide Cont Metal1 Nhvt Device Derivation Device Layer Derivation Recognition DIODUMMY AND NIMP PLUS DIOdummy AND Pimp MINUS DIOdummy AND Nimp LVS Comparison Parameter Calculation area Area of MINUS (illustrated above) CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 113 .GPDK045 Reference Manual REVISION 2. 6e-6 m 1 CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 ..6u m=1 Assura Netlist Assura auLvs Device Name = “ndio_nvt” c ndio_nvt DIO PLUS B MINUS B .0 " CDL Netlist CDL Device Name = “ndio_nvt” DD0 PLUS MINUS ndio_nvt 160f 1. area 1e-12 pj 1.6e-6 m 1. * 2 pins * 2 nets i D0 ndio_nvt PLUS MINUS .6u m=1 DIVA LVS Netlist DIVA Device Name = “ndio_nvt” . PAGE 114 .GPDK045 Reference Manual REVISION 2.37 ndio_nvt datasheet ndio_nvt Spectre Netlist Spectre Model Name = “gpdk045_ndio_nvt” D0 ( PLUS MINUS ) gpdk045_ndio_nvt area=160f pj=1.0 20. ndio_nvt Instance /D0 = auLvs device D0 d ndio_nvt PLUS MINUS i 0 ndio_nvt PLUS MINUS " area 1e-12 pj 1. 0 PLUS MINUS Area ndio_nvt – 1.GPDK045 Reference Manual REVISION 2.2 volt native VT N+/Psub diode Device Layers Layer Color and Fill DIOdummy Nimp / Oxide Pimp / Oxide Cont Metal1 Nhvt Device Derivation Device Layer Derivation Recognition DIODUMMY AND NIMP PLUS DIOdummy AND Pimp MINUS DIOdummy AND Nimp LVS Comparison Parameter Calculation area Area of MINUS (illustrated above) CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 115 . 0 20.6u m=1 Assura Netlist Assura auLvs Device Name = “ndio_2v” c ndio_2v DIO PLUS B MINUS B .. ndio_2v Instance /D0 = auLvs device D0 d ndio_2v PLUS MINUS i 0 ndio_2v PLUS MINUS " area 1e-12 pj 1. PAGE 116 .38 ndio_2v datasheet ndio_2v Spectre Netlist Spectre Model Name = “gpdk045_ndio_2v” D0 ( PLUS MINUS ) gpdk045_ndio_2v area=160f pj=1.GPDK045 Reference Manual REVISION 2. area 1e-12 pj 1.6u m=1 DIVA LVS Netlist DIVA Device Name = “ndio_2v” .0 " CDL Netlist CDL Device Name = “ndio_2v” DD0 PLUS MINUS ndio_2v 160f 1. * 2 pins * 2 nets i D0 ndio_2v PLUS MINUS .6e-6 m 1.6e-6 m 1 CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 . 8 volt N+/Psub diode Device Layers Layer Color and Fill DIOdummy Nimp / Oxide Pimp / Oxide Cont Metal1 Oxide_thk Device Derivation Device Layer Derivation Recognition DIODUMMY AND NIMP PLUS DIOdummy AND Pimp MINUS DIOdummy AND Nimp LVS Comparison Parameter Calculation area Area of MINUS (illustrated above) CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 117 .GPDK045 Reference Manual REVISION 2.0 PLUS MINUS Area ndio_2v – 1. GPDK045 Reference Manual REVISION 2. PAGE 118 .0 " CDL Netlist CDL Device Name = “pdio_lvt” DD0 PLUS MINUS pdio_lvt 160f 1.6u m=1 DIVA LVS Netlist DIVA Device Name = “pdio_lvt” .39 pdio_lvt datasheet pdio_lvt Spectre Netlist Spectre Model Name = “gpdk045_pdio_lvt” D0 ( PLUS MINUS ) gpdk045_pdio_lvt area=160f pj=1.6e-6 m 1 CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 . * 2 pins * 2 nets i D0 pdio_lvt PLUS MINUS .0 20.6e-6 m 1.6u m=1 Assura Netlist Assura auLvs Device Name = “pdio_lvt” c pdio_lvt DIO PLUS B MINUS B . pdio_lvt Instance /D0 = auLvs device D0 d pdio_lvt PLUS MINUS i 0 pdio_lvt PLUS MINUS " area 1e-12 pj 1.. area 1e-12 pj 1. 2 volt low VT P+/Nwell diode Device Layers Layer Color and Fill DIOdummy Nwell Nimp / Oxide Pimp / Oxide Cont Metal1 Nlvt Device Derivation Device Layer Derivation Recognition DIODUMMY AND NIMP PLUS DIOdummy AND Pimp MINUS DIOdummy AND Nimp LVS Comparison Parameter Calculation area Area of PLUS (illustrated above) CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 119 .GPDK045 Reference Manual REVISION 2.0 PLUS MINUS Area pdio_lvt – 1. area 1e-12 pj 1.0 20. * 2 pins * 2 nets i D0 pdio_hvt PLUS MINUS .40 pdio_hvt datasheet pdio_hvt Spectre Netlist Spectre Model Name = “gpdk045_pdio_hvt” D0 ( PLUS MINUS ) gpdk045_pdio_hvt area=160f pj=1.GPDK045 Reference Manual REVISION 2..6u m=1 DIVA LVS Netlist DIVA Device Name = “pdio_hvt” . pdio_hvt Instance /D0 = auLvs device D0 d pdio_hvt PLUS MINUS i 0 pdio_hvt PLUS MINUS " area 1e-12 pj 1.6e-6 m 1 CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 .0 " CDL Netlist CDL Device Name = “pdio_hvt” DD0 PLUS MINUS pdio_hvt 160f 1. PAGE 120 .6u m=1 Assura Netlist Assura auLvs Device Name = “pdio_hvt” c pdio_hvt DIO PLUS B MINUS B .6e-6 m 1. 2 volt high VT P+/Nwell diode Device Layers Layer Color and Fill DIOdummy Nwell Nimp / Oxide Pimp / Oxide Cont Metal1 Nhvt Device Derivation Device Layer Derivation Recognition DIODUMMY AND NIMP PLUS DIOdummy AND Pimp MINUS DIOdummy AND Nimp LVS Comparison Parameter Calculation area Area of PLUS (illustrated above) CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 121 .0 PLUS MINUS Area pdio_hvt – 1.GPDK045 Reference Manual REVISION 2. area 1e-12 pj 1.41 pdio_2v datasheet pdio_2v Spectre Netlist Spectre Model Name = “gpdk045_pdio_2v” D0 ( PLUS MINUS ) gpdk045_pdio_2v area=160f pj=1.GPDK045 Reference Manual REVISION 2.6u m=1 Assura Netlist Assura auLvs Device Name = “pdio_2v” c pdio_2v DIO PLUS B MINUS B .6e-6 m 1 CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 .0 20.6e-6 m 1.. pdio_2v Instance /D0 = auLvs device D0 d pdio_2v PLUS MINUS i 0 pdio_2v PLUS MINUS " area 1e-12 pj 1.6u m=1 DIVA LVS Netlist DIVA Device Name = “pdio_2v” . PAGE 122 . * 2 pins * 2 nets i D0 pdio_2v PLUS MINUS .0 " CDL Netlist CDL Device Name = “pdio_2v” DD0 PLUS MINUS pdio_2v 160f 1. 8 volt P+/Nwell diode Device Layers Layer Color and Fill DIOdummy Nwell Nimp / Oxide Pimp / Oxide Cont Metal1 Oxide_thk Device Derivation Device Layer Derivation Recognition DIODUMMY AND NIMP PLUS DIOdummy AND Pimp MINUS DIOdummy AND Nimp LVS Comparison Parameter Calculation area Area of PLUS (illustrated above) CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 123 .GPDK045 Reference Manual REVISION 2.0 PLUS MINUS Area pdio_2v – 1. 5e-06 rad 10e-06 .42 ind_a datasheet Spectre Netlist Spectre Model Name = “gpdk045_ind_a” L0 ( PLUS MINUS B ) gpdk045_ind_a w=3u s=1.5 m 1 Assura Netlist Assura auLvs Device Name = “ind_a” c ind_a IND PLUS B MINUS B B B .GPDK045 Reference Manual REVISION 2. ind_a Instance /L1 = auLvs device L0 d ind_a PLUS MINUS B i 0 ind_a PLUS MINUS B "width 3u space 1.5 width 3e-06 space 1.5e-6 rad 10e-6 nr 8.5 m 1. * 3 pins * 3 nets i L0 ind_a PLUS MINUS B m 1 nr 8.5e-6 rad 10e-6 nr 8..5 m=1 DIVA LVS Netlist DIVA Device Name = “ind_a” .0 " CDL Netlist CDL Device Name = “ind_a” L0 PLUS MINUS B ind_a width 3u space 1.5u r=10u nr=8. CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 124 .0 20. 0 radius ind_a – Asymmetric Inductor Device Layers Layer Color and Fill INDdummy Metal11 Metal10 IND2dummy Cont Device Derivation Device Layer Derivation Recognition INDDUMMY AND METAL11 PLUS INDdummy AND Metal11 MINUS INDdummy AND Metal10 LVS Comparison Parameter Calculation radius Inner radius of Metal11 turn (illustrated above) width Width of Metal11 CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 125 .GPDK045 Reference Manual REVISION 2. 5u r=10u nr=6 m=1 DIVA LVS Netlist DIVA Device Name = “ind_s” . ind_s Instance /L2 = auLvs device L1 d ind_s PLUS MINUS B i 1 ind_s PLUS MINUS B "width 3u space 1.5e-06 rad 10e-06 . * 3 pins * 3 nets i L1 ind_s PLUS MINUS B m 1 nr 6 width 3e-06 space 1. CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 126 .5e-6 rad 10e-6 nr 6 m 1 Assura Netlist Assura auLvs Device Name = “ind_s” c ind_s IND PLUS B MINUS B B B .GPDK045 Reference Manual REVISION 2.0 " CDL Netlist CDL Device Name = “ind_s” L1 PLUS MINUS B ind_s width 3u space 1.43 ind_s datasheet Spectre Netlist Spectre Model Name = “gpdk045_ind_s” L1 ( PLUS MINUS B ) gpdk045_ind_s w=3u s=1.5e-6 rad 10e-6 nr 6 m 1..0 20. 0 radius ind_s – Symmetric Inductor Device Layers Layer Color and Fill INDdummy Metal11 Metal10 IND2dummy Cont Device Derivation Device Layer Derivation Recognition INDDUMMY AND METAL11 PLUS IND2dummy AND Metal11 MINUS IND3dummy AND Metal11 LVS Comparison Parameter Calculation radius Inner radius of Metal11 turn (illustrated above) width Width of Metal11 CADENCE CONFIDENTIAL DOCUMENT DATE :15/05/2009 PAGE 127 .GPDK045 Reference Manual REVISION 2.
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