7/10/2017 GATE 2018 - Previous Solutions & Video Lectures for FREE: GATE Questions on MOSFET, CMOS & Introduction to VLSI(1987 to Till Date) Home GATE GATE 2014 Keys Yearwise GATE Questions Topicwise GATE Questions Practice Problems GATE Exam Notes *T&C Apply Replay Wednesday, October 29, 2014 GATE Questions on MOSFET, CMOS & Introduction to VLSI (1987 to Till Date) 1988 1. In MOSFET devices, the N-channel type is better than the P-channel type in the following respects a. It has better noise immunity b. It is faster c. It is TTL compatible d. It has better drive capability Answer: B & D Solution : https://www.youtube.com/watch?v=i0tBM4SR3ug 1989 1. In a MOSFET, the polarity of the inversion layer is the same as that of the a. Charge on the gate electrode b. Minority carriers in the drain c. Majority carriers in the substrate d. Majority carriers in the source Answer: D Solution : https://www.youtube.com/watch?v=EoJQBXa0NT0 1990 1. Which of the following effects can be caused by a rise in the temperature ? a. Increase in MOSFET current b. Increase in BJT current c. Decrease in MOSFET current d. Decrease in BJT current Answer: B & C Solution : https://www.youtube.com/watch?v=BoRoLQ2eN6o Facebook 1991 1. In the figure shown, the n-channel MOSFETs are identical and their current voltage GATEpaper.in characteristics are given by the following expressions. Like Page 3.7k likes Find the current IDC as shown Be the first of your friends to like this Adsense Answer: 1 mA Solution : https://www.youtube.com/watch?v=VPgDjeUybI4 1992 http://www.gatepaper.in/2014/10/gate-questions-on-mosfet-cmos.html 1/18 com/watch?v=1C8CrsGguu0 2.com/watch?v=vQJjmHNsn3I ► 2015 (34) ▼ 2014 (143) 3. of 0. CMOS & shown in the figure.. GATE 1990 ECE Analog Circuits (Analog Answer: 2. GATE 1994 ECE Analog Circuits (Analog Answer: 80 Volts Electronics). Solution : https://www. which is Introduction to V.. Channel current is reduced on application of a more positive voltage to the gate of a ► December (14) depletion mode n-channel MOSFET. Reducing the gate oxide thickness d. GATE 1992 ECE Analog Circuits (Analog 1. under strong accumulation. GATE 1987 ECE Analog Circuits (Analog Electronics).5 Volts Electronics). Evaluate the value of the inverter threshold VINV. The threshold voltage of an n-channel MOSFET can be increased by a.com/watch?v=tAtC_pW9Bcw GATE 1995 ECE Analog Circuits (Analog Electronics).. GATE Questions on Junction Field Effect Transistor.. Increasing the channel dopant concentration b... Answer: 138 nSec Solution : https://www.com/watch?v=W34kWifl15o ▼ October (20) GATE Practice Problems on JFET (Junction Field Eff. Calculate the capacitance of a circular MOS capacitor... of the capacitor if the dielectric strength of SiO2 film is 107 V/cm.. Ԑr = 4 and Ԑo = 8.. GATEpaper's Treasure Answer: Switching ► 2016 (19) Solution : https://www. CMOS & Introduction to VLSI (1987 to Till Date) 1.. CDS =0 and CDG = 0... The device constant of the MOSFET.youtube. GATE Questions on "Bipolar Junction Transistors (B.. GATE 1989 ECE Analog Circuits (Analog Electronics). calculate the breakdown voltage Electronics). Assume the relative dielectric GATE 1993 ECE Analog Circuits (Analog constant of SiO2.... Reducing the channel length Answer: A Solution : https://www.youtube.com/watch?v=ccRFcF5_sQQ 1994 1.. a step voltage of magnitude of 4 volts is applied to the input so that the MOSFET turns ON instantaneously...com/watch?v=7om91pj90XE GATE 1991 ECE Analog Circuits (Analog 1995 Electronics). At time t = 0.. http://www..youtube.7/10/2017 GATE 2018 . 4...html 2/18 .. GATE Questions on "Special Purpose Diodes (Tunnel .Previous Solutions & Video Lectures for FREE: GATE Questions on MOSFET.in/2014/10/gate-questions-on-mosfet-cmos.. A typical CMOS inverter has the voltage transfer characteristic (VTC) curve as GATE Questions on MOSFET. Solution : https://www.youtube. Reducing the channel dopant concentration c.. K = 5 mA/ V2.youtube. (TRUE / FALSE) ► November (12) Answer: False Solution : https://www. layer of 80 mm thickness..gatepaper.5 mm dia and having a SiO2 Electronics). The transit time of the current carriers through the channel of an FET decides its ……………....854 X 10-14 F/cm. An n-channel MOSFET having a threshold voltage of 2 volts is used in the circuit shown in figure. the value of the input at which Vo falls by ΔVo = VTn + VTp.youtube. GATE Questions on "Semiconductors (Intrinsic & Ext. GATE 1988 ECE Analog Circuits (Analog Electronics). characteristics. Draw the equivalent circuit and calculate the time taken to the output Vo to fall to 5 volts.. GATE Questions on "Zener Diode" (1987 to Till Date. GATE Questions on "PN Junction (Diode)" (1987 to T... Initially the transistor is OFF and is in steady state. 0. P –type b... The load transistor has a smaller W/L ratio compared to the driver transistor d. The specifications of the circuit are : VDD = 10 volts. The driver transistor has larger leakage currents compared to the load transistor c..youtube.com/watch?v=351K-p6NM-k 2. -0.08 x 1012/cm3. Set .4 x 1011/cm3. The doping and type of the implant (assumed to be a sheet charge at the interface) required to shift the threshold voltage to -1 volt are… a. 5. N -type Answer: Solution : 3.com/watch?v=JWuLWh-pz1c 1997 1. For a MOS capacitor fabricated on a P-type semiconductor. 5.1" 1. KN(W/L) = 40 µA/V2 ► July (5) ► June (6) ► May (20) ► April (27) ► March (24) Answer: 25 kΩ (without CLM). MOSFET Data : Threshold voltage. 2.volts.com/watch?v=D2kfxsy-ypk 3.9. VT = 1 volt and IDS = 0. The region under the gate is ion implanted for threshold voltage tailoring.youtube.. None of the above Answer: C Solution : https://www.3 V-1 ► August (8) Transconductance parameter. P -type d. Determine the expression for the resistance and compute its value for Vi. The n-channel MOSFET shown in figure is used as a voltage variable resistor. Neglect body effect. VT = 1 volt ► September (7) Channel Length Modulation parameter.08 x 1012/cm3. other things remaining the same. A Silicon N-channel MOSFET has a threshold voltage of 1 volts and oxide thickness of 400 Ao. strong inversion occurs when a.Previous Solutions & Video Lectures for FREE: GATE Questions on MOSFET.in/2014/10/gate-questions-on-mosfet-cmos. Surface potential is positive and equal to twice the Fermi potential Answer: D Solution : https://www. q = 1. Given NMOS circuit as shown.com/watch?v=f5B96mqdE7I 2. Ɛo = 8. Surface potential is zero c. http://www. An N-channel silicon (EG = 1.1 eV) MOSFET was fabricated using N+ poly silicon gate and the threshold voltage was found to be 1 volt. 1.5 mA. Surface potential is equal to Fermi level b. The gate delay of an NMOS inverter is dominated by charge time rather than discharge time because a. a.6 x 10-19].youtube. N -type c.0 d. The driver transistor has larger threshold voltage than the load transistor b. 0 c. β = µnCox(W/L) = 10-4 Amp/V2. GATE Pratice Questions on "Digital Circuits .1 b.7/10/2017 GATE 2018 .4 x 1011/cm3. 1. λ = .youtube.html 3/18 .. Neglect body GATE practice Problems on PN junction (Diode) effect.gatepaper.5 kΩ (with CLM) Solution : https://www. [Ɛr (SiO2) = 3.854 x 10-14 F/cm. the new threshold voltage should be………. CMOS & Introduction to VLSI (1987 to Till Date) GATE 1996 ECE Analog Circuits (Analog 1996 Electronics).1 Answer: D Solution : https://www. Now if the gate is changed to P+ poly silicon. 1. Evaluate VDS and RD. 7. Surface potential is negative is negative and equal to Fermi potential in magnitude d. For this circuit to work as an inverter.7/10/2017 GATE 2018 .156 µSec Solution : https://www. Gate voltage b. -5 volts and 5 volts c.68 kΩ Solution : https://www.youtube. CMOS & Introduction to VLSI (1987 to Till Date) Answer: 4. Determine the High to Low propagation delay time (tpHL) when it is driving a capacitive load (CL) of 20 pF.html 4/18 .youtube. In the CMOS inverter circuit shown in figure. The threshold voltage for each transistor in figure is 2 volts.Previous Solutions & Video Lectures for FREE: GATE Questions on MOSFET. Device data : Answer: 0. the input Vi makes a transition from VOL (= 0 volts) to VOH (= 5 volts).com/watch?v=pHfKL4yw4Ko 1999 1.youtube.in/2014/10/gate-questions-on-mosfet-cmos.youtube. 11.com/watch?v=DYvtwvbyh8Q 2.com/watch?v=Uc3EuOto9Pk 1998 1. MOSFET can be used as a a. Current controlled capacitor b. The effective channel length of a MOSFET in saturation decreases with increase in a. Voltage controlled capacitor c.gatepaper. -5 volts and 0 volts b. Drain voltage http://www.15 Volts. Current controlled inductor d. 0 volts and 3 volts d. 3 volts and 5 volts Answer: A Solution : https://www. Vi must take the values a.com/watch?v=0t8YIeh7E_0 2001 1. Voltage controlled inductor Answer: B Solution : https://www. com/watch?v=jvXncirhK9c 3. 4.youtube. If P is passivation. R-P-S-Q d. Only S2 is TRUE c. S-R-Q-P Answer: B Solutoin : https://www.Previous Solutions & Video Lectures for FREE: GATE Questions on MOSFET. Source voltage d.0 mA Answer: D Solutoin : https://www. P-Q-R-S b. and assuming that the MOSFET is operating at saturation. Remain unchanged b. Both are FALSE Answer: A Solution : https://www.com/watch?v=lm9CG4kv7NU 2003 1. S1: T1 conducts when VI ≥ 2 volts. R is metallization and S is source/drain diffusion.gatepaper. then the order in which they are carried out in a standard n-well CMOS fabrication process is a.0 mA c. Q is n-well implant. Both are TRUE d. if the source is connected at a higher potential than that of the bulk (i.com/watch?v=dS__KGppUig 2004 1. the drain current for an applied VGS of 1400 mV is a.youtube.e. The drain current observed is 1 mA. VSB > 0 volts). Decrease c. 3. The given figure is the voltage transfer characteristic of http://www. Which of the following is correct. S2: T1 is always in saturation when Vo = 0 volts.youtube. Q-S-R-P c. Only S1 is TRUE b. the threshold voltage VT of the MOSFET will a. Consider the following statements in connection with the CMOS inverter in figure. where both the MOSFETs are of enhancement type and both have a threshold voltage of 2 volts.7/10/2017 GATE 2018 .in/2014/10/gate-questions-on-mosfet-cmos.youtube.com/watch?v=yySAOIv7hiw 2002 1. For an N channel type MOSFET. 0. Body voltage Answer: B Solution : https://www.youtube. Increase Answer: D Solutoin : https://www. a.5 mA d. CMOS & Introduction to VLSI (1987 to Till Date) c. Neglecting the channel length modulation effect.com/watch?v=NkWeND6-BxI 2. When the gate to source voltage (VGS) of a MOSFET with threshold voltage of 400 mV.html 5/18 . 2. Change polarity d.5 mA b. The device parameters K1 and K2 of T1 and T2 are 36 µA/v2 and 9 µA/v2 respectively. Which of the following is correct? a. ID is a. 3 mA c.Previous Solutions & Video Lectures for FREE: GATE Questions on MOSFET. then the threshold voltage is Answer: C Solution : https://www.html 6/18 .youtube.7/10/2017 GATE 2018 .com/watch?v=lPY4XzAWeSg 2. The output voltage Vo is http://www. The threshold voltage (VT) of MOSFET is 1 volt. Consider the following statements S1 and S2. S1: the threshold voltage (VT) of a MOS capacitor decreases with increase in gate oxide thickness S2: the threshold voltage (VT) of a MOS capacitor decreases with increase in substrate doping concentration. An N-channel MOSFET and its transfer curve is shown in figure. CMOS & Introduction to VLSI (1987 to Till Date) Answer: C Solution : https://www.youtube. then for VGS = 3 volts.youtube.in/2014/10/gate-questions-on-mosfet-cmos. 4 mA Answer: D Solution : https://www. S1 is FALSE and S2 is TRUE b.youtube. Both S1 and S2 are TRUE c. 9 mA d.com/watch?v=UYrsnu-QIlU 2. If the drain current (ID) is 1 mA for VGS = 2 volts. S1 is TRUE and S2 is FALSE d.com/watch?v=F1cZOGLgZIA 2005 1. The drain of an N channel MOSFET is shorted to the gate so that VGS = VDS.com/watch?v=jmKFRCr0xa0 3. 2 mA b. Both S1 and S2 are FALSE Answer: D Solution : https://www. Both transistors T1 and T2 in figure have a threshold voltage of 1 volt.gatepaper. VGS = -3 volts c.gatepaper. In the CMOS inverter circuit shown. CMOS & Introduction to VLSI (1987 to Till Date) Answer: C Solution : https://www. Match each device in Group I with its characteristic property in Group II. if the Transconductance parameters of the NMOS and PMOS transistors are Kn = Kp = µnCox(Wn/Ln) = µpCox(Wp/Lp) = 40 µA/V2 and their threshold voltages are VTn = |VTp| = 1 volt. Electrons c.7/10/2017 GATE 2018 . The dominant charge is due to the presence of a. A MOS capacitor made using P type substrate is in the accumulation mode. VGS = 3 volts Answer: D Solution : https://www. VGS = -6 volts b.in/2014/10/gate-questions-on-mosfet-cmos. Group I lists four different semiconductor devices.html 7/18 . Negatively charged ions Answer: A Solution : https://www.com/watch?v=Kxd4IZqv1vU 2007 1.com/watch?v=iwERJKn2hUU 2.Previous Solutions & Video Lectures for FREE: GATE Questions on MOSFET. VGS = 0 volts d.youtube. Holes b.com/watch?v=6fIMwxzffIo 3. the current I is http://www.youtube. Positively charged ions d.youtube. Answer: C Solution : https://www. An N-channel depletion MOSFET has the following two points on its ID verses VGS curve are (i) VGS = 0 at ID = 12 mA and (ii) VGS = -6 volts at ID = 0 mA Which of the following Q-points will give the highest Transconductance gain for small signals? a.com/watch?v=jlQ_ny0L4C0 2006 1.youtube. youtube. Then which one of the following is TRUE .com/watch?v=6yl7336P2kA 2. The gate oxide thickness in the MOS capacitor is a. 1. Assume that the permittivity of silicon and SiO2 are 1x10-12 and 3. i. 1 µm d. CMOS & Introduction to VLSI (1987 to Till Date) a.html 8/18 . Slows down as the oxide grows d. 350 nm d. where K is a constant. Is zero as the existing oxide prevents further oxidation Answer: A Solution : https://www.7/10/2017 GATE 2018 . The maximum depletion layer width in silicon is a.com/watch?v=wtboLpHXLOA 3.com/watch?v=IKyIj6hVTL8 2008 1. a. S1 is FALSE and S2 is TRUE d. 143 nm c.143 µm b. The figure shows the high frequency capacitance – voltage (C – V) characteristics of MOS capacitor having an area of 1x10-4 cm2. Both S1 and S2 are FASLE Answer: C Solution : https://www. A silicon wafer has 100nm of oxide on it and is inserted in a furnace at a temperature above 1000oC for further oxidation in dry oxygen. S1 is TRUE and S2 is FALSE c. Is independent of current oxide thickness and temperature b. Is independent of current oxide thickness but depends on temperature c. 25 µA c.Previous Solutions & Video Lectures for FREE: GATE Questions on MOSFET. the C – V plot will shift to the left. 45 µA d. The oxidation rate a.youtube. The drain current of a MOSFET in saturation is given by ID = K(VGS-VT)2.youtube.in/2014/10/gate-questions-on-mosfet-cmos.857 µm c. 90 µA Answer: D Solution : https://www. The magnitude of the Transconductance gm is http://www. 1 µm Answer: A ii.5x10-13 F/cm respectively. 0. 50 nm b.gatepaper.143 µm Answer: B iii. 0 Amp b. Both S1 and S2 are TRUE b. Consider the following statements about the C – V characteristics plot : S1: The MOS capacitor has an N type substrate S2: If the positive charges are introduced in the oxide. 0. youtube. Vbias is chosen so that both transistors are in saturation. The measured Transconductance gm of an NMOS transistor operating in the linear region is plotted against the gate voltage VG at constant drain voltage VD. The equivalent gm of the pair is defined to be dIout / dVi at constant Vout.html 9/18 . transistors M1 and M2 are identical NMOS transistors.youtube.com/watch?v=oySwKD3Vtjg 2009 http://www.com/watch?v=KE_MLvt-M-4 5.com/watch?v=CBXqcvlx97A 4.gatepaper.com/watch?v=pYDNlQanv2g 3. Nearly equal to gm1/gm2 of M2 Answer: C Solution : https://www.youtube.in/2014/10/gate-questions-on-mosfet-cmos. The product of individual gm’s of the transistors c. CMOS & Introduction to VLSI (1987 to Till Date) Answer: B Solution : https://www. Which of the following figures represents the expected dependence of gm on VG? Answer: A Solution : https://www.Previous Solutions & Video Lectures for FREE: GATE Questions on MOSFET. Assume that M2 is in saturation and the output is unloaded. Nearly equal to the gm of M1 d. For the circuit shown in the following figure.7/10/2017 GATE 2018 .youtube. The IX is related to Ibias as Answer: B Solution : https://www. The sum of individual gm’s of the transistors b. is a. Two identical NMOS transistors M1 and M2 are connected as shown below. the quantity µcox(W/L) is 1 mA/V2. Both are in triode region c. NMOS is in triode region and PMOS is in saturation region d. but S2 is not a reason for S1 d. for both transistors. Estimate the output voltage. 1800 d. 3600 Answer: B Solution: https://www.Previous Solutions & Video Lectures for FREE: GATE Questions on MOSFET. The gate oxide in a CMOS process is preferably grown using a. Linked Questions: Consider the CMOS circuit shown.youtube.com/watch?v=v-0BYB0NkMI 2.com/watch?v=7bi7sXWZYEc 2011 1. For small increase in VG beyond 1 volt. Both are in saturation region b. NMOS is in saturation region and PMOS is in triode region Answer: D ii. 1350 c.7/10/2017 GATE 2018 . and S2 is a reason for S1.in/2014/10/gate-questions-on-mosfet-cmos. Both are TRUE.com/watch?v=_BU3wB8FoBA 2010 1.e. Epitaxial deposition d. µncox = 100 µA/V2 and the threshold voltage VT = 1 volt. Ion implantation Answer: B Solution : https://www. Vo for VG = 1. Consider the following two statements about the internal conditions in an N channel MOSFET operating in the active region.com/watch?v=bXxmszDCh1U 2.html 10/18 .youtube. The voltage VX at the source of the upper transistor is http://www. i. Tristate Transistor Logic and Chip Metal Oxide semiconductor c. At room temperature. 450 b.youtube. for the MOS transistors. while the gate voltage of the P channel MOSFET is kept constant at 3 volts. Both are TRUE b. CMOS & Introduction to VLSI (1987 to Till Date) 1. Assume that. S1: the inversion charge decreases from source to drain S2: the channel potential increases from source to drain Which of the following is correct? a. Triple Transistor Logic and Chip Metal Oxide semiconductor b. which of the following gives the correct description of the region of operation of each MOSFET? a. In the circuit shown below.5 volts. based on the answer to above question) Answer: C Solution : https://www. The full forms of the abbreviations TTL and CMOS in reference to logic families are a. a possible value for the mobility of electrons in the inversion layer of a silicon N channel MOSFET is (in cm2/volt-sec) a. (Hint: use the appropriate current voltage equation for each MOSFET. where the gate voltage VG of the N channel MOSFET is increased from zero. Both are TRUE. Transistor Transistor Logic and Complementary Metal Oxide semiconductor d.com/watch?v=qbq2JXNCe_Q 3. Answer: D Solution : https://www. Wet oxidation b.gatepaper.youtube. Dry oxidation c. Tristate Transistor Logic and Complementary Metal Oxide semiconductor Answer: C Solution : https://www. Both are FALSE c.youtube. the magnitude of the threshold voltage is 1 volts and the product of the transconductance parameter and the (W/L) ratio i. The transistor is of width 1 µm. In the CMOS circuit shown. electron and hole motilities are equal. The depletion width formed at every PN junction is 10 nm. the output expression ‘Y’ is Answer: A Solution : https://www.in/2014/10/gate-questions-on-mosfet-cmos. The relative permittivity’s of Si and SiO2 are 11. CMOS & Introduction to VLSI (1987 to Till Date) a.com/watch?v=4J00rSwlU6U 2012 1.youtube.7/10/2017 GATE 2018 .9 X 10-12 F/m.youtube. In the circuit shown below. and M1 and M2 transistors are equally sized. 1 volt b.com/watch?v=Geh8HiqWIoU 3.Previous Solutions & Video Lectures for FREE: GATE Questions on MOSFET. In the three dimensional view of a silicon N channel MOS transistor shown below. δ = 20 nm.html 11/18 .com/watch?v=AOa8cOFX7WA 2.7 and 3. http://www.367 volts Answer: C Solution : https://www.youtube. 2 volts c.gatepaper.9 respectively and Ɛ0 = 8. The device M1 is in the linear region if Answer: A Solution : https://www. 0. 3 volts d. Cox = 10-8 F/cm2 and µn = 800 cm2/volt-sec. 0.gatepaper. Superior quality oxide with a higher growth rate b. shallow P – well or N – well regions can be formed using a.com/watch?v=9QAOSh8OjSY 2014 Set – 1 (15th February 2014 (Forenoon)) 1. In CMOS technology. 7 fF c. the threshold voltage VTH is 0.html 12/18 . low temperature dry oxidation d. The source – body capacitance approximately a. An increase in gate source capacitance b. When the drain voltage VD = 1.com/watch?v=em0VvbA7po4 2. The gate – source overlap capacitance is approximately a. VDS = 5 volts.35 fF d.. In MOSFET operating in saturation region.com/watch?v=xzUDuBbZUXM SET – 2 (15th February 2014 (Afternoon)) 1. Inferior quality oxide with a higher growth rate c. 2 pF d. W/L = 100.youtube. A decrease in Transconductance c. Neglect channel length modulation effects. low energy ion – implantation Answer: D Solution : https://www. 0.youtube.com/watch?v=EEcf8aHius8 2. Superior quality oxide with a lower growth rate Answer: D Solution : https://www.youtube.7 fF b. A depletion type N channel MOSFET is biased in its linear region for use as a voltage controlled resistor.youtube. The value of the voltage controlled resistor (in Ω) is ….com/watch?v=NA-HnsA124g 2.24 fF Answer: A ii. it will lead to a. low energy sputtering c.youtube.com/watch?v=60X82BxUfd8 2013 1. Inferior quality oxide with a lower growth rate d. 7 pF Answer: B Solution : https://www. A decrease in output resistance Answer: D Solution : https://www. A decrease in unity gain bandwidth product d. Dry oxidation(using dry oxygen) as compared to Wet oxidation (using stream or water vapor) produces………. channel length modulation c.Previous Solutions & Video Lectures for FREE: GATE Questions on MOSFET.0 volts. a. 0. the channel length modulation effect causes a.. low pressure chemical vapor deposition b.7 pF c. 0. CMOS & Introduction to VLSI (1987 to Till Date) i. a decrease in the threshold voltage b. 2 fF b.youtube.7/10/2017 GATE 2018 . Answer: 500 Solution : https://www. VGS = 2.8 volts. an increase in substrate leakage current d.5 volts. Assume threshold voltage VTH = -0. an increase in accumulation capacitance Answer: A Solution : https://www. If the fixed positive charges are present in the gate oxide of an N channel enhancement type MOSFET.6 http://www. In IC technology.in/2014/10/gate-questions-on-mosfet-cmos. For the N channel MOS transistor shown in the figure. youtube. the drain current ID was found to be 0.625 b.5µcox(W/L) = 0.in/2014/10/gate-questions-on-mosfet-cmos.5 Answer: C Solution : https://www.com/watch?v=rDjsCvkSUtk 3.com/watch?v=QPQ5hOdbGjE 2.75 c. VGS curve of an N channel MOSFET in linear region is 10-3 Ω-1 at V = 0. the threshold voltage |Vt| = 2 volts and K = 0. the new value of ID (in mA) is a. The transistor M1 switches from saturation region to linear region when Vin (in volts) is ………….. In MOSFET fabrication.0 volts. The value of ID (in mA) is ………… Answer: 0.7/10/2017 GATE 2018 . Channel stop implantation c. The peak electric field (in V/µm) in the oxide region is ……………. For the MOSFETs shown in the figure.com/watch?v=wsv90UUqYVY 3. For the MOSFET M1 shown in the figure.com/watch?v=abv9XXV0jks SET – 3 (16th February 2014 (Forenoon)) 1. An ideal MOS capacitor has boron doping concentration of 1015 cm-3 in the substrate. µncox = 100 µA/V2 and VTH = 0.1 mA/V2. the DS slope of the √ID vs. neglecting channel length modulation. If VD is adjusted to be 2 volts by changing the values of R and VDD.9 Solution : https://www.125 d..1 volts. The slope of the ID vs. Isolation oxide growth b. the channel length is defined during the process of a. When a gate voltage is applied.5 mA.854 x 10-14 F/cm and the relative permittivity’s of silicon and silicon dioxide are 12 and 4 respectively. a depletion region of width 0.5 µm is formed with a surface (channel) potential of 0. Lithography step leading to the contact pads Answer: C Solution : https://www.07 Solution : https://www. VGS curve (in √A/V) under saturation regime is approximately……………. http://www.youtube. 1.gatepaper. For the same device.com/watch?v=K4aRAJxegSI 4. Given that Ԑo = 8. 1. Poly-silicon gate patterning d. Answer: 0.youtube. VDD = 2. 0. Answer: 2. 0.youtube.html 13/18 .5 volts.youtube.2 volts. CMOS & Introduction to VLSI (1987 to Till Date) volts.4 Solution : https://www.Previous Solutions & Video Lectures for FREE: GATE Questions on MOSFET. assume W/L = 2. Wet Oxidation d. Sputtering b. The source voltage VSS is varied from 0 to VDD.02 Solution : https://www.com/watch?v=aT-PUfpeyOY 2.5 Solution : https://www. Neglecting the channel http://www. Molecular Beam Epitaxy c.youtube. In the circuit shown.in/2014/10/gate-questions-on-mosfet-cmos. The channel length modulation parameter λ (in V-1) is __________ Answer: 0.Cox(W/L) = 1 mA/V2. Assume that the channel length modulation parameter λ is zero and body is shorted to source. the threshold voltage is Vth greater than zero. while keeping gate-source voltage same.com/watch?v=AWdemWJenw4 2015 1. Which one of the following processes is preferred to form the gate dielectric (SiO2) of MOSFET? a.02 mA.gatepaper.com/watch?v=nAvaaApnnao 3. CMOS & Introduction to VLSI (1987 to Till Date) Answer: 1.Previous Solutions & Video Lectures for FREE: GATE Questions on MOSFET. When the drain – source voltage was increased to 6 volts.com/watch?v=4AebD_Jv5C8 4. The minimum supply voltage VDD (in volts) needed to ensure that transistor M1 operates in saturation mode of operation is ___________________ Answer: 3 Solution : https://www. The current in an enhancement mode NMOS transistor biased in saturation mode was measured to be 1 mA at a drain to source voltage of 5 volts.7/10/2017 GATE 2018 . VTN = 1 volt. the both the enhancement mode NMOS transistors have the following characteristics: Kn = µn. the drain current increased to 1. Dry Oxidation Answer: D Solution : https://www. For the NMOSFET in the circuit shown.html 14/18 .youtube. Assume that drain to source saturation voltages is much smaller than the applied drain source voltage.youtube.youtube. The maximum depletion layer thickness is 100 nm.html 15/18 . MOSFET. A MOSFET in saturation has a drain current of 1 mA for VDS = 0.com/watch?v=qipvNgPQNDM 5. If the channel length modulation coefficient is 0.gatepaper.33 Solution : https://www. the drain current ID as a function of VSS is represented by Answer: A Solution : https://www..5 volts.7/10/2017 GATE 2018 .com/watch?v=uFmH59NNz6s 6.in/2014/10/gate-questions-on-mosfet-cmos.com/watch?v=eIk6sCXiKbY Posted by GATE paper at 10:54 +25 Recommend this on Google Labels: GATE Questions. the ratio of the maximum capacitance to the minimum capacitance of this MOS capacitor is ____________ Answer: 4.05 V-1.Loved your solution +1 1 · Reply 2 Deepak Chauhan 7 months ago - Shared publicly Tq very much sir :) 1 shrikant Charthal 8 months ago - Shared publicly sir pls add communication subject 1 · Reply http://www..youtube.youtube. CMOS & Introduction to VLSI (1987 to Till Date) length modulation.youtube. the output resistance (in kΩ) of the MOSFET is ________ Answer: 20 Solution : https://www. VLSI 22 comments Add a comment Top comments Dipali Acharya 1 year ago - Shared publicly Thank you sir.Previous Solutions & Video Lectures for FREE: GATE Questions on MOSFET. In MOS capacitor with an oxide layer thickness of 10 nm. Assuming εs/εox = 3. The permittivity’s of the semiconductor and the oxide layer are εs and εox respectively. in pmos there is rule we always consider magnitude of Mr vt..gatepaper.. 1 · Reply shanmuk sandeep 1 year ago - Shared publicly so blessed with ur crystal clear solutions :) +2 1 · Reply 3 http://www. very good solution 1 · Reply Saif khan 10 months ago - Shared publicly Very important necessary things u explain.in/2014/10/gate-questions-on-mosfet-cmos.I cleared GATE xam with the help of ur solutions.html 16/18 .U r doing a gr8 job. CMOS & Introduction to VLSI (1987 to Till Date) gurpreet singh 1 year ago - Shared publicly vinay .Previous Solutions & Video Lectures for FREE: GATE Questions on MOSFET...7/10/2017 GATE 2018 . thanks a lot 1 · Reply Sri Kanth 11 months ago - Shared publicly very good explanation 1 · Reply sachin koparkar 1 year ago - Shared publicly EXCELLENT SIR 1 · Reply Veena S 1 year ago - Shared publicly Thank u sir.Thank you sir 1 mayank sharma 6 months ago - Shared publicly Shandaar 1 Govind Raju 7 months ago - Shared publicly Tq so much sir 1 · Reply Bikash kumar 7 months ago - Shared publicly sir please give solution of electromagnetics subjects 1 · Reply Sivaramakrishna Gorla 8 months ago - Shared publicly than q sir 1 · Reply rohit kumar 10 months ago - Shared publicly thank you sir ..the eq is vsd<vsg-|vt| if this eqn satis ed then pmos will be in triode or linear region +1 1 · Reply 2 gurmeet singh 1 year ago - Shared publicly Really So helpful. .... answer will be option (a) any body have other clues 1 · Reply Pramod S 5 months ago its 4th option vivek singh 1 year ago - Shared publicly Thank u very much sir :-) 1 · Reply aashik ali 1 year ago - Shared publicly thax..7/10/2017 GATE 2018 .Previous Solutions & Video Lectures for FREE: GATE Questions on MOSFET..gatepaper. CMOS & Introduction to VLSI (1987 to Till Date) Dilip Kumar 1 year ago - Shared publicly I think in1996 question 2 .999 ₹ 529 ₹ 3.099 ₹ 8....... Name Email * Message * Send http://www.749 ₹ 449 Amazon India Newer Post Home Older Post Subscribe to: Post Comments (Atom) Post Your Feedback (or) Doubts here.999 ₹ 1.in/2014/10/gate-questions-on-mosfet-cmos.html 17/18 .. 1 · Reply Sindhu Gaddam 1 year ago - Shared publicly tq very much sir :) +1 1 · Reply 2 sanjay kumar 1 year ago - Shared publicly Thank u 1 · Reply Show more ₹ 5. in/2014/10/gate-questions-on-mosfet-cmos. CMOS & Introduction to VLSI (1987 to Till Date) Simple theme.gatepaper.Previous Solutions & Video Lectures for FREE: GATE Questions on MOSFET.html 18/18 .7/10/2017 GATE 2018 . Powered by Blogger. http://www.
Report "GATE Questions on MOSFET, CMOS & Introduction to VLSI (1987 to Till Date)"