40V Precision Low Power Operational AmplifiersISL28117, ISL28217 The ISL28117 and ISL28217 are a family of very high precision amplifiers featuring low noise vs power consumption, low offset voltage, low IBIAS current and low temperature drift making them the ideal choice for applications requiring both high DC accuracy and AC performance. The combination of precision, low noise, and small footprint provides the user with outstanding value and flexibility relative to similar competitive parts. Applications for these amplifiers include precision active filters, medical and analytical instrumentation, precision power supply controls, and industrial controls. The ISL28117 single and ISL28217 dual are offered in an 8 Ld SOIC package. Both devices are offered in standard pin configurations and operate over the extended temperature range to -40°C to +125°C. ISL28117, ISL28217 Features • Low Input Offset . . . . . . . . . . . . . . ±50µV, Max. • Superb Offset TC . . . . . . . . . . . . 0.6µV/°C, Max. • Input Bias Current . . . . . . . . . . . . . . ±1nA, Max. • Input Bias Current TC . . . . . . . . . . ±5pA/°C, Max. • Low Current Consumption . . . . . . . . . . . . . 440µA • Voltage Noise. . . . . . . . . . . . . . . . . . . . . 8nV/Hz • Wide Supply Range. . . . . . . . . . . . . . 4.5V to 40V • Operating Temperature Range . . -40°C to +125°C • Small Package Offerings in Single and Dual • Pb-Free (RoHS Compliant) Related Literature*(see page 23) • See AN1508 “ISL281X7SOICEVAL1Z Evaluation Board User’s Guide” • See AN1509 “ISL282X7SOICEVAL2Z Evaluation Board User’s Guide” Applications*(see page 23) • Precision Instruments • Medical Instrumentation • Spectral Analysis Equipment • Active Filter Blocks • Thermocouples and RTD Reference Buffers • Data Acquisition • Power Supply Control Typical Application C1 8.2nF VOS Temperature Coefficient (VOSTC) 18 16 NUMBER OF AMPLIFIERS VS = ± 15V V+ 14 12 10 8 6 4 2 VIN R1 1.84k R2 4.93k 3.3nF OUTPUT + C2 V- Sallen-Key Low Pass Filter (10kHz) 0 -0.45 -0.30 -0.15 0 0.15 0.30 0.45 VOSTC (µV/°C) April 13, 2010 FN6632.4 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL28117, ISL28217 Ordering Information PART NUMBER (Notes2, 3) ISL28117FBBZ ISL28117FBBZ-T7 (Note 1) ISL28117FBBZ-T13 (Note 1) ISL28117FBZ ISL28117FBZ-T7 (Note 1) ISL28117FBZ-T13 (Note 1) ISL28117FUBZ Coming Soon ISL28117FUBZ-T13 (Note 1) Coming Soon ISL28117FUZ ISL28117FUZ-T13 (Note 1) ISL28217FBBZ ISL28217FBBZ-T7 (Note 1) ISL28217FBBZ-T13 (Note 1) ISL28217FBZ ISL28217FBZ-T7 (Note 1) ISL28217FBZ-T13 (Note 1) ISL28117SOICEVAL1Z ISL28217SOICEVAL2Z PART MARKING 28117 FBZ 28117 FBZ 28117 FBZ 28117 FBZ -C 28117 FBZ -C 28117 FBZ -C 8117Z 8117Z 8117Z -C 8117Z -C 28217 FBZ 28217 FBZ 28217 FBZ 28217 FBZ -C 28217 FBZ -C 28217 FBZ -C Evaluation Board Evaluation Board VOS (MAX) (µV) 50 (B Grade) 50 (B Grade) 50 (B Grade) 100 (C Grade) 100 (C Grade) 100 (C Grade) TBD (B Grade) TBD (B Grade) 150 (C Grade) 150 (C Grade) 50 (B Grade) 50 (B Grade) 50 (B Grade) 100 (C Grade) 100 (C Grade) 100 (C Grade) PACKAGE (Pb-Free) 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld MSOP 8 Ld MSOP 8 Ld MSOP 8 Ld MSOP 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC 8 Ld SOIC PKG. DWG. # M8.15E M8.15E M8.15E M8.15E M8.15E M8.15E M8.118 M8.118 M8.118 M8.118 M8.15E M8.15E M8.15E M8.15E M8.15E M8.15E NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL28117, ISL28217. For more information on MSL please see techbrief TB363. Pin Configurations ISL28117 (8 LD SOIC, MSOP) TOP VIEW NC -IN +IN V1 2 3 4 -+ 8 7 6 5 NC V+ VOUT NC VOUT_A 1 -IN_A 2 +IN_A 3 V- 4 - + + - ISL28217 (8 LD SOIC) TOP VIEW 8 V+ 7 VOUT_B 6 -IN_B 5 +IN_B 2 April 13, 2010 FN6632.4 8 V+ IN500Ω 500Ω IN+ V+ OUT VCIRCUIT 2 VCIRCUIT 3 ISL28217 (8 LD SOIC) PIN NAME +IN +IN_A V+IN_B -IN_B VOUT_B V+ VOUT VOUT_A -IN -IN_A NC EQUIVALENT CIRCUIT Circuit 1 Circuit 3 Circuit 1 Circuit 1 Circuit 2 Circuit 3 Circuit 2 Circuit 1 - DESCRIPTION Amplifier A non-inverting input Negative power supply Amplifier B non-inverting input Amplifier B inverting input Amplifier B output Positive power supply Amplifier A output Amplifier A inverting input No internal connection V+ CAPACITIVELY COUPLED ESD CLAMP 8 V- CIRCUIT 1 3 April 13. ISL28217 Pin Descriptions ISL28117 (8 LD SOIC) 3 3 4 4 5 6 7 7 6 1 2 2 1. 2010 FN6632.ISL28117.4 . 5. 120 60 8 Ld SOIC ISL28217 . . . . . . . . . . .4 . . . .08 0. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. MSOP Package TCVOS Input Offset Voltage Temperature Coefficient.08 4 4 TYP 8 MAX (Note 6) 50 110 100 190 150 250 0. . . . . . . . VCM = 0. . . . . . SOIC Package Input Offset Voltage Temperature Coefficient.85 TCIOS VCM CMRR Input Offset Current Temperature Coefficient Input Voltage Range Common-Mode Rejection Ratio Guaranteed by CMRR test VCM = -13V to +13V -3 -13 120 120 PSRR Power Supply Rejection Ratio VS = ±2. . . . . 155 50 Maximum Storage Temperature Range . . . . 20mA Maximum Differential Input Voltage .42V Maximum Differential Input Current . .5 TCIB IOS Input Bias Current Temperature Coefficient Input Offset Current -5 -1. . See Tech Brief TB379 for details. .000 145 145 0. 5) θJA (°C/W) θJC (°C/W) 8 Ld SOIC ISL28117 . Boldface limits apply over the operating temperature range. . . . Indefinite ESD Rating Human Body Model . +150°C Pb-Free Reflow Profile . 1. . .42 1 0. . . . . . . . . . . . CONDITIONS MIN (Note 6) -50 -110 ISL28x17 C Grade -100 -190 Input Offset Voltage. . . . 42V Min/Max Input Voltage . . . . Electrical Specifications VS ± 15V.000 18. MSOP Package IB ISL28117 C Grade -150 -250 ISL28x17 B Grade ISL28x17 C Grade ISL28117 C Grade -0.14 0. . . . . 500V Charged Device Model . . . . . . -40°C to +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time.5kV Thermal Information Thermal Resistance (Typical. . . . unless otherwise noted. . . . .6 -0. . .5V to V+ + 0. . . . . .intersil. . . . . . . . . ISL28217 Absolute Maximum Ratings Maximum Supply Voltage .14 0.. .5kV Machine Model . . .85 3 13 PARAMETER VOS DESCRIPTION UNIT µV µV µV µV µV µV µV/C µV/C µV/C nA nA pA/C nA nA pA/C V dB dB dB dB V/mV Input Offset Voltage. . 105 50 8 Ld MSOP ISL28117 . . . . . . . .9 1 1 1. . . . .5 1.ISL28117. . . 2010 FN6632. . . 5. . . . . . . . . . NOTES: 4. . the “case temp” location is taken at the package top center. . . . . . . .14 0. . . . VO = 0V. . . . . .. . . . . .see link below http://www. . . . . . .5 -1. .9 -1 -1 -1. . -40°C to +125°C. . . . . .6 0. . .V. . . .com/pbfree/Pb-FreeReflow. . . . Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. For θJC. . . . TA= +25°C.. . . 4. . . .5 5 1. .5V Max/Min Input current for Input Voltage >V+ or <V-. . . . . ..25V to ±20V 120 120 AVOL Open-Loop Gain VO = -13V to +13V. . . Temperature data established by characterization. .±20mA Output Short-Circuit Duration (1 output at a time). . . Notes 4. . SOIC Package ISL28x17 B Grade Input Bias Current 4 April 13. . .0. . . . . . . -65°C to +150°C Maximum Junction Temperature (TJMAX) . . .asp Recommended Operating Conditions Ambient Temperature Range (TA) . . . RL = 10kΩ to ground 3. VCM = 0. RL = 5kΩ to VCM AV = -1. 2010 FN6632. VOUT = 10VP-P.7 -13. ISL28217 Electrical Specifications VS ± 15V. RL = 2kΩ 0.ISL28117. unless otherwise noted.55 -13.6 10. VOUT 20% to 80% Rise Time 10% to 90% of VOUT Fall Time 90% to 10% of VOUT ts Settling Time to 0. VO = 0V. tf. -40°C to +125°C. RL = 2kΩ. G = 1.68 ISC VSUPPLY Short-Circuit Supply Voltage Range Guaranteed by PSRR ± 2. 10% to VOUT Settling Time to 0.01% 4V Step.1% 10V Step.1Hz to 10Hz f = 10Hz f = 100Hz f = 1kHz f = 10kHz f = 1kHz 1kHz. RL = 10kΩ to VCM AV = -1. 10% to VOUT tOL Output Positive Overload Recovery Time Output Negative Overload Recovery Time AV = 11.4 . RL = 5kΩ to VCM AV = -1. G = 1. Temperature data established by characterization. RL = 10kΩ to VCM AV = 1.0009 0.44 0.5 13. VOUT = 10VP-P. RL = 2kΩ 1kHz. VOUT = 50mVP-P. VOUT = 4VP-P. RL = 2kΩ to VCM 0.7 MAX (Note 6) PARAMETER VOH DESCRIPTION Output Voltage High UNIT V V V V V V V V mA mA mA V AC SPECIFICATIONS GBWP enVp-p en en en en in THD + N Gain Bandwidth Product Voltage Noise VP-P Voltage Noise Density Voltage Noise Density Voltage Noise Density Voltage Noise Density Current Noise Density Total Harmonic Distortion AV = 1k.3 -13.1% 4V Step.25 10 8.2 RL = 2kΩ to ground -13. RL = 5kΩ to VCM AV = -100. (Continued) CONDITIONS RL = 10kΩ to ground MIN (Note 6) 13. VO = 3.3 13.6 V/µs ns ns µs µs µs µs µs µs 1.5 100 120 21 24 13 18 5. 10% to VOUT Settling Time to 0. VOUT = 4VP-P. VO = 4VP-P AV = 1.2 8 8 0.01% 10V Step. 10% to VOUT Settling Time to 0. Small Signal Slew Rate. RL = 10kΩ TRANSIENT RESPONSE SR tr.5VRMS.55 TYP 13.5 -13.25 43 ± 20 13. VIN = 0.1 0.1 VOL Output Voltage Low RL = 10kΩ to ground -13.53 0. Boldface limits apply over the operating temperature range. VOUT = 50mVP-P. RL = 2kΩ to VCM AV = -100.1 IS Supply Current/Amplifier 0.2 RL = 2kΩ to ground 13.2VP-P. TA= +25°C. VIN = 0.0005 MHz µVP-P nV/√Hz nV/√Hz nV/√Hz nV/√Hz pA/√Hz % % 5 April 13.5VRMS. RL = 5kΩ to VCM AV = -1.2VP-P.5 0. VO = 3. unless otherwise noted. SOIC Package Input Offset Voltage Temperature Coefficient.7 -3.4 .44 0. ISL28217 Electrical Specifications VS ± 5V.3 3.6 0. SOIC Package Input Bias Current VOH Output Voltage High RL = 10kΩ to ground 3.7 V V RL = 2kΩ to ground 3.000 18. MSOP Package ISL28117 C Grade -150 -250 TCVOS Input Offset Voltage Temperature Coefficient.5 3.14 0. Temperature data established by characterization.5 5 1.9 -1 -1 -1. TA = +25°C. VCM = 0.ISL28117.5 1. -40°C to +125°C.25V to ±5V 120 120 AVOL Open-Loop Gain VO = -3.5 MHz 6 April 13.68 ISC Short-Circuit 43 AC SPECIFICATIONS GBWP Gain Bandwidth Product AV = 1k.18 8 8 MAX (Note 6) 50 110 100 190 150 250 0. MSOP Package IB ISL28x17 B Grade ISL28x17 C Grade ISL28117 C Grade -0.14 0.1 3.0V RL = 10kΩ to ground 3.55 -3.6 -0.14 0.1 IS Supply Current/Amplifier 0.000 145 145 0.3 0.5 -1.5 TCIB IOS Input Bias Current Temperature Coefficient Input Offset Current -5 -1.85 TCIOS VCM CMRR Input Offset Current Temperature Coefficient Input Voltage Range Common-Mode Rejection Ratio VCM = -3V to +3V -3 -3 120 120 PSRR Power Supply Rejection Ratio VS = ±2. 2010 FN6632.42 1 0.2 V V V V mA mA mA RL = 2kΩ to ground -3.3 -3.2 3.0V to +3. VO = 0V.55 V V VOL Output Voltage Low RL = 10kΩ to ground -3. Boldface limits apply over MIN (Note 6) -50 -110 ISL28x17 C Grade -100 -190 Input Offset Voltage.85 3 3 the operating temperature range.9 1 1 1. CONDITIONS ISL28x17 B Grade TYP 4 UNIT µV µV µV µV µV µV µV/C µV/C µV/C nA nA pA/C nA nA pA/C V dB dB dB dB V/mV PARAMETER VOS DESCRIPTION Input Offset Voltage.53 0. RL = 2kΩ 1.5 -3. ISL28217 Electrical Specifications VS ± 5V. Parameters with MIN and/or MAX limits are 100% tested at +25°C. unless otherwise specified.1Hz to 10Hz f = 10Hz f = 100Hz f = 1kHz f = 10kHz f = 1kHz TYP 0.25 12 8.1% 4V Step. Small Signal Slew Rate. unless otherwise noted. VOUT = 50mVP-P. VOS DISTRIBUTION FOR GRADE B 7 April 13. -40°C to +125°C.4 .ISL28117. VCM = 0.1 UNIT µVP-P nV/√Hz nV/√Hz nV/√Hz nV/√Hz pA/√Hz PARAMETER enp-p en en en en in DESCRIPTION Voltage Noise Voltage Noise Density Voltage Noise Density Voltage Noise Density Voltage Noise Density Current Noise Density TRANSIENT RESPONSE SR tr. VIN = 0. 10% to VOUT tOL AV=11.5 100 120 12 19 7 5. RL = 2kΩ. 2010 FN6632. VOS DISTRIBUTION for GRADE B FIGURE 2. VCM = 0V. Typical Performance Curves 140 VS = ±5V NUMBER OF AMPLIFIERS 120 100 80 60 40 20 0 -50 VS = ±15V. VIN = 0. RL = Open. Temperature limits established by characterization and are not production tested. Boldface limits apply over MIN (Note 6) MAX (Note 6) the operating temperature range. tf.2VP-P RL = 2kΩ to VCM Output Negative Overload Recovery Time AV = -100.8 V/µs ns ns µs µs µs µs Output Positive Overload Recovery Time AV = -100. VOUT = 50mVP-P. (Continued) CONDITIONS 0. 140 VS = ±15V 120 NUMBER OF AMPLIFIERS 100 80 60 40 20 0 -50 -30 -10 10 VOS (µV) 30 50 -30 -10 10 VOS (µV) 30 50 FIGURE 1.6 8 8 0. 10% to VOUT Settling Time to 0. VO = 4VP-P AV = 1. RL = 10kΩ to VCM AV = 1. VOUT = 4VP-P. unless otherwise specified. Temperature data established by characterization. VOUT = 4VP-P. RL = 5kΩ to VCM AV = -1. TA = +25°C.2VP-P RL = 2kΩ to VCM NOTE: 6. RL = 5kΩ to VCM 0. VOUT 20% to 80% Rise Time 10% to 90% of VOUT Fall Time 90% to 10% of VOUT ts Settling Time to 0. VO = 0V.01% 4V Step. RL = 10kΩ to VCM AV = -1. 30 -0. RL = Open. VCM = 0V.15 VOSTC (µV/°C) 0. VOS DISTRIBUTION FOR GRADE C 100 VS = ± 15V NUMBER OF AMPLIFIERS 18 16 14 12 10 8 6 4 2 VS = ± 15V 50 VOS (µV) 0 -50 -100 -50 0 50 TEMPERATURE (°C) 100 150 0 -0. ISL28217 Typical Performance Curves 300 250 200 150 100 50 0 -100 VS = ± 15V VS = ±15V. VOS RANGE vs TEMPERATURE FIGURE 6.ISL28117. unless otherwise specified. VOS RANGE vs TEMPERATURE FIGURE 8. TCVOS vs NUMBER OF AMPLIFIERS 100 VS = ± 5V NUMBER OF AMPLIFIERS 16 14 12 10 8 6 4 2 VS = ±5V 50 VOS (µV) 0 -50 -100 -50 0 50 TEMPERATURE (°C) 100 150 0 -0.30 0.15 0 0.30 0. TCVOS vs NUMBER OF AMPLIFIERS 8 April 13.4 .45 -0.45 FIGURE 7.15 0 0. (Continued) 300 250 200 150 100 50 0 -100 VS = ± 5V NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS -60 -20 20 VOS (µV) 60 100 -60 -20 20 VOS (µV) 60 100 FIGURE 3.15 0.45 VOSTC (µV/°C) FIGURE 5. VOS DISTRIBUTION FOR GRADE C FIGURE 4.30 -0. 2010 FN6632.45 -0. 5 MORE VS = ± 15V FIGURE 9. IBTC+ vs NUMBER OF AMPLIFIERS 9 April 13.5 VS = ±5V 100 150 FIGURE 13.4 . IB.5 1.5 1.5 -1.5 IB+TC (pA/°C) 2. IB+ RANGE vs TEMPERATURE FIGURE 14.5 3.5 3. 2010 FN6632.5 -1.5 IB-TC (pA/°C) 2.RANGE vs TEMPERATURE FIGURE 12. IB+ RANGE vs TEMPERATURE FIGURE 10.5 1.ISL28117.5 -1.5 -0.5 -2.5 -0.5 3. TCIB.5 -2. (Continued) 70 VS = ±15V NUMBER OF AMPLIFIERS 150 60 50 40 30 20 10 0 -3. RL = Open. TCIB+ vs NUMBER OF AMPLIFIERS 500 400 300 200 IB.5 FIGURE 11. ISL28217 Typical Performance Curves 500 400 300 200 IB+ (pA) 100 0 -100 -200 -300 -400 -500 -50 0 50 TEMPERATURE (°C) 100 VS = ±15V.5 0.5 -0.5 -2.5 0. unless otherwise specified.(pA) 100 0 -100 -200 -300 -400 -500 -50 0 50 TEMPERATURE (°C) VS = ± 15V NUMBER OF AMPLIFIERS 70 60 50 40 30 20 10 0 VS = ±15V 100 150 -3.5 0.vs NUMBER OF AMPLIFIERS 500 400 300 200 IB+ (pA) 100 0 -100 -200 -300 -400 -500 -50 0 50 TEMPERATURE (°C) VS = ± 5V NUMBER OF AMPLIFIERS 80 70 60 50 40 30 20 10 0 -3. VCM = 0V.5 IB+TC(pA/°C) 2. 5 IOSTC (pA/°C) 2. IB.5 -1.5 -2.5 3. (Continued) 90 80 NUMBER OF AMPLIFIERS 70 60 50 40 30 20 10 150 0 -3.RANGE vs TEMPERATURE FIGURE 16. RL = Open.ISL28117.vs NUMBER OF AMPLIFIERS 500 400 300 200 IOS (pA) VS = ± 15V NUMBER OF AMPLIFIERS 90 80 70 60 50 40 30 20 10 VS = ±15V 100 0 -100 -200 -300 -400 -500 -50 0 50 TEMPERATURE (°C) 100 150 0 -3.5 0. IOS RANGE vs TEMPERATURE FIGURE 20. ISL28217 Typical Performance Curves 500 400 300 200 IB.5 3.5 0.5 FIGURE 19.(pA) 100 0 -100 -200 -300 -400 -500 -50 0 50 TEMPERATURE (°C) 100 VS = ±15V. VCM = 0V.5 -1. IOSTC vs NUMBER OF AMPLIFIERS 500 400 300 200 IOS (pA) 100 0 -100 -200 -300 -400 -500 -50 0 50 TEMPERATURE (°C) VS = ± 5V NUMBER OF AMPLIFIERS 100 90 80 70 60 50 40 30 20 10 VS = ±5V 100 150 0 -3.5 -0. 2010 FN6632.5 3.5 0.5 1.5 IOSTC (pA/°C) FIGURE 17.5 VS = ±5V VS = ± 5V FIGURE 15. IBTC. IOS RANGE vs TEMPERATURE FIGURE 18.5 -0.5 1.5 -2.5 1.5 -0. unless otherwise specified.5 -1.5 2.5 IB-TC(pA/°C) 2. IOSTC vs NUMBER OF AMPLIFIERS 10 April 13.5 -2.4 . @ ±15V 0 50 100 TEMPERATURE (°C) 150 100 150 FIGURE 25.6 VS = ±15V RL = 10kΩ ±2.70 ±15V 0.4 0.4 . PSRR vs TEMPERATURE FIGURE 24.4 14. SHORT CIRCUIT CURRENT vs TEMPERATURE 11 April 13.40 13.2 14. SHORT CIRCUIT CURRENT vs TEMPERATURE FIGURE 26.ISL28117. VCM = 0V.60 Is+ (mA) VS = ±15V. 2010 FN6632.30 -50 13.50 0.8 13. CMRR vs TEMPERATURE 60 ISC+ @ ±15V 55 50 ISC+ (mA) ISC.2 -50 0 50 TEMPERATURE (°C) 100 150 0 50 TEMPERATURE (°C) 100 150 FIGURE 21. unless otherwise specified.25V 0. SUPPLY CURRENT PER AMP vs TEMPERATURE FIGURE 22.0 VOH (V) 13. (Continued) 14. +VOUT vs TEMPERATURE -140 VS = ±2.25V TO ±20V -130 -135 VCM = ±13V PSRR (dB) CMRR (dB) -145 -140 -145 -150 -155 -150 -155 -50 0 50 100 TEMPERATURE (°C) 150 -160 -50 0 50 TEMPERATURE (°C) 100 150 FIGURE 23. ISL28217 Typical Performance Curves 0.(mA) 45 40 35 30 25 -50 60 55 50 45 40 35 30 25 -50 0 50 TEMPERATURE (°C) ISC. RL = Open. 2 -14.0 -14.4 -13.8 -14. VOUT vs TEMPERATURE FIGURE 32.2 -13.2 -50 VS = +15V RL = 2kΩ -13.2 14. VOUT vs TEMPERATURE 14. VOS vs INPUT COMMON MODE VOLTAGE.2 -14.4 14. INPUT VOS vs INPUT COMMON MODE VOLTAGE.ISL28117.6 13. (Continued) 100 VO = ±13V 80 60 +125°C VS = ±15V AVOL (V/mV) VOS (µV) 40 20 0 -20 -40 -40°C +25°C 15000 10000 -50 0 50 100 TEMPERATURE (°C) 150 -60 -15 -10 -5 0 VCM (V) 5 10 15 FIGURE 27. VCM = 0V.4 -13. AVOL vs TEMPERATURE FIGURE 28. unless otherwise specified. ISL28217 Typical Performance Curves 20000 VS = ±15V.4 -50 VS = ±15V RL = 10kΩ VOS (µV) 0 50 100 TEMPERATURE (°C) 150 FIGURE 29.0 VOH (V) 13.0 -14.6 -13.8 13. 2010 FN6632.4 . VS = ±15V 100 80 60 40 20 0 -20 -40 -60 -5 -3 -1 VCM (V) 1 3 5 +25°C -40°C +125°C VOL (V) VS = +5V -13. VS = ±5V FIGURE 30.4 13. RL = Open.2 -13.8 -14. VOUT vs TEMPERATURE 12 April 13.6 VOL (V) -13.4 -50 VS = +15V RL = 2kΩ 0 50 TEMPERATURE (°C) 100 150 0 50 TEMPERATURE (°C) 100 150 FIGURE 31. 2010 FN6632. CL = 100pF FIGURE 38. unless otherwise specified. Rf = 100k -250 AV = 10. (Continued) 100 INPUT NOISE VOLTAGE (nV/√Hz) VS = ±18. INPUT NOISE VOLTAGE 0. RL = Open. ISL28217 Typical Performance Curves 250 VS = ±15V. OPEN-LOOP GAIN. ±15V 13 April 13.25. OPEN-LOOP GAIN.2V AV = 1 OPEN LOOP GAIN (dB)/PHASE (°) 0.1 1 10 100 1k 10k 100k 200 180 160 140 120 100 80 60 40 20 0 -20 R = 10k L -40 CL = 10pF -60 SIMULATION -80 -100 0. ±5V.5V VS = ±5V GAIN FREQUENCY (Hz) 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 100M FIGURE 37. PHASE vs FREQUENCY. PHASE vs FREQUENCY.000 1 2 0 3 4 5 6 7 8 9 10 10 1 1 10 100 1k 10k 100k TIME (s) FREQUENCY (Hz) FIGURE 33.4 .4V -200 Rg = 10. INPUT NOISE CURRENT SPECTRAL DENSITY FIGURE 36. VCM = 0V. VS = ±2. RL = 10kΩ. RL = 10kΩ.2V AV = 1 INPUT NOISE VOLTAGE (nV) 200 150 100 50 0 -50 -100 -150 V+ = 36.1Hz to 10Hz FIGURE 34.1m 1m 10m 100m 220 200 PHASE CMRR (dB) 180 160 140 120 100 80 60 40 20 1 10 100 1k 10k 100k 1M 10M 100M 0 1m RL = INF CL = 10pF SIMULATION 10m 100m 1 VS = ±15V OPEN LOOP GAIN (dB)/PHASE (°) VS = ±2. CL = 10pF 200 180 160 140 120 100 80 60 40 20 0 -20 R = 10k L -40 CL = 100pF -60 SIMULATION -80 -100 0.ISL28117.1m 1m 10m 100m PHASE GAIN 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 35. CMRR vs FREQUENCY. INPUT NOISE VOLTAGE SPECTRAL DENSITY 1 INPUT NOISE CURRENT (pA/√Hz) VS = ±18. Rf = 100k VS = ±20V CL = 4pF RL = 10k VOUT = 50mVP-P -10 10 100k 1M 10M FREQUENCY (Hz) FIGURE 39. ±15V FIGURE 40. Rf = 100k AV = 1 Rg = OPEN. unless otherwise specified.5V RL = 10k AV = +1 VOUT = 50mVP-P GAIN (dB) 2 1 0 -1 -2 -3 -4 -5 CL = 4pF RL = 10k -6 AV = +1 -7 V OUT = 50mVP-P -8 10 100 VS = ±2.25V VS = ±15V. VS = ±5V. Rf = 100k Rg = 1k. GAIN vs FREQUENCY vs CL FIGURE 44. 2010 FN6632. VCM = 0V.4 .01µF CL = 47pF VS = ±2. FREQUENCY RESPONSE vs FEEDBACK RESISTANCE Rf/Rg FIGURE 42.VS = ±2. GAIN vs FREQUENCY vs RL 12 10 8 6 GAIN (dB) 4 2 0 -2 -4 -6 -8 10 100 CL = 100pF CL = 270pF CL = 470pF CL = 1000pF 1k 10k 100k 1M 10M FREQUENCY (Hz) CL = 4pF CL = 0.ISL28117. ISL28217 Typical Performance Curves 120 110 100 90 80 PSRR (dB) 60 50 40 30 20 10 0 -10 10 PSRR+ AND PSRR. RL = Open. (Continued) 70 60 50 GAIN (dB) 40 30 20 10 0 10M AV = 10 Rg = 10k.99k RL = 1k RL = 10k -8 10 FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 41. Rf = 0 10k 1k 100 AV = 100 AV = 1000 Rg = 100. GAIN vs FREQUENCY vs SUPPLY VOLTAGE 14 April 13.VS = ±15V 100 1k 10k 100k FREQUENCY (Hz) 1M RL = INF CL = 4pF AV = +1 VCM = 1VP-P 70 PSRR+ AND PSRR. FREQUENCY RESPONSE vs CLOSED LOOP GAIN 4 2 NORMALIZED GAIN (dB) 0 -2 -4 -6 -8 VS = ±20V RL = 10k -10 CL = 4pF -12 AV = +2 -14 VOUT = 50mVP-P -16 10 100 1k Rf = Rg = 10k GAIN (dB) Rf = Rg = 1k Rf = Rg = 100 Rf = Rg = 100k 2 1 0 -1 -2 -3 -4 -5 -6 -7 10k 100k 1M 10M VS = ±20V CL = 4pF AV = +1 VOUT = 50mVP-P 100 1k 10k RL = 100 100k 1M 10M RL = 499 RL = 4.25V VS = ±5V VS = ±15V VS = ±20V 10k 1k 100k FREQUENCY (Hz) 1M 10M FIGURE 43. PSRR vs FREQUENCY. VS = ±15V 15 April 13.24 0.6 LARGE SIGNAL (V) 1.8 0. ISL28217 Typical Performance Curves 180 160 140 120 100 80 60 40 20 0 10 VS = ±15V RL-Driver Ch.28 0 10 20 OUTPUT @ VS = ±15V RL = 2k CL = 4pF AV = -100 Rf = 100k. VS = ±5V.4 .08 -0. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME.24 0 5 10 15 20 25 TIME (µs) 30 35 40 -0.04 0 -0.4 -0.2 -1.8 -1.4 2. RL = 2k. VS = ±5V. ±15V FIGURE 50. VS = ±5V.12 -0.0 1.08 0.0 10M -2.2 0.16 INPUT (V) 0. unless otherwise specified. Rg = 1k VIN = 200mVP-P OUTPUT @ VS= ±5V 30 40 50 60 TIME (µs) 70 80 90 INPUT 14 12 10 8 6 4 2 0 -2 100 OUTPUT (V) FIGURE 47.6 -2. RL = 2k.16 -0. 2010 FN6632.ISL28117.20 -0.08 0 10 20 OUTPUT @ VS = ±15V INPUT RL = 2k CL = 4pF AV = -100 Rf = 100k.04 0 -0. CROSSTALK. ±15V 80 70 60 OVERSHOOT (%) OUTPUT (V) 50 40 30 20 10 0 1 10 100 CAPACITANCE (pF) 1k 10k VS = ±15V RL = 10k AV = 1 VOUT = 50mVP-P O V ER SH O O T + O V ER SH O O T - 0.20 0. POSITIVE OUTPUT OVERLOAD RESPONSE TIME. ±15V FIGURE 48. Rg = 1k VIN = 200mVP-P OUTPUT @ VS = ±5V 4 2 0 -2 -4 -6 -8 -10 70 80 90 -12 100 30 40 50 60 TIME (µs) FIGURE 49.04 -0. SMALL SIGNAL TRANSIENT RESPONSE. VS = ±15V FIGURE 46. % OVERSHOOT vs LOAD CAPACITANCE. RL = Open. (Continued) 2.12 0. 10k VS = ±15V. LARGE SIGNAL TRANSIENT RESPONSE vs RL VS = ±5V. = Open RL-Receiving Ch.04 -0.4 0 10 20 30 CL = 4pF AV = +1 VOUT = 4VP-P 40 50 60 TIME (µs) 70 80 90 100 VS = ±5V. VCM = 0V. = 10k CL = 4pF AV = +1 VSOURCE = 1VP-P 100 1k 10k 100k FREQUENCY (Hz) 1M VS = ±15V. 10k CROSSTALK (dB) FIGURE 45.4 0 -0. ±15V 60 50 SMALL SIGNAL (mV) 40 30 20 10 0 -10 INPUT (V) VS = ±15V RL = 10k CL = 4pF AV = +1 VOUT = 50mVP-P 0. low input noise voltage (8nV/√Hz).4 . load conditions. Continuous operation under these conditions may degrade long term reliability.5V (±2. In applications where one or both amplifier input terminals are at risk of exposure to high voltages beyond the power supply rails. High NPN beta (>1000) reduces input bias current while maintaining good frequency response.0005% @ 3. 2010 FN6632. These amplifiers also feature high open loop gain (18kV/mV) for excellent CMRR (145dB) and THD+N performance (0. Input bias cancellation circuits provide additional bias current reduction to <1nA. low noise precision op amps. CMRR performance is typically >130dB over-temperature. or package type need to be modified to remain in the safe operating area. high impedance amplifiers. V+ . Input offset voltage temperature coefficients (VOSTC) are a maximum of ±0. even when the input voltage is 1V beyond the supplies. Figure 46 provides an example of distortion free large signal response using a 4VP-P input pulse with an input rise time of <1ns. Output Current Limiting The output current is internally limited to approximately ±45mA at +25°C and can withstand a short circuit to either rail as long as the power dissipation limits are not exceeded. ISL28217 Applications Information Functional Description The ISL28117 and ISL28217 are single and dual.5V/µs slew rate of the amplifier. Input Performance The super-beta NPN input pair provides excellent frequency response while maintaining high input precision. Figures 25 and 26 show the current limit variation with temperature. 16 April 13. Power Dissipation It is possible to exceed the +150°C maximum junction temperatures under certain load and power supply conditions. With ±15V supplies. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages. low input bias current and low noise. The minimum CMRR performance over the -40°C to +125°C temperature range is >120dB for power supply voltages from ±5V (10V) to ±15V (30V).ISL28117. The VOS temperature behavior is smooth (Figures 5 through 8) maintaining constant TC across the entire temperature range.5VRMS. The series resistors limit the high feed-through currents that can occur in pulse applications when the input dV/dT exceeds the 0. low input offset voltage (13µV typical).500Ω VIN + 500Ω VOUT RL V- FIGURE 51. series connected 500Ω current limiting resistors and an anti-parallel diode pair across the inputs (Figure 51). The worst case common mode input voltage range over temperature is 2V to each rail. Figures 9 through 16 show the high degree of bias current stability at ±5V and ±15V supplies that is maintained across the -40°C to +125°C temperature range. The Power Supply Rejection Ratio typically exceeds 140dB over the full operating voltage range and 120dB minimum over the -40°C to +125°C temperature range. 1) Input ESD Diode Protection The input terminals (IN+ and IN-) have internal ESD protection diodes to the positive and negative supply rails. These parameters are related using Equation 1: T JMAX = T MAX + θ JA xPD MAXTOTAL (EQ. The series resistors enable the input differential voltage to be equal to the maximum power supply voltage (40V) without damage. the input can forward-bias the anti-parallel diodes causing current to flow to the output resulting in severe distortion and possible diode failure. current limiting resistors may be needed at the input terminal to limit the current through the power supply ESD diodes to 20mA max.6µV/°C for the “B” and ±0. A complimentary bipolar output stage enables high capacitive load drive without external compensation. This applies to only 1 amplifier at a time for the dual op amp. and low 1/f noise corner frequency (~8Hz). 1kHz into 2kΩ). The ISL28117 and ISL28217 are immune to output phase reversal.25V) to 40V (±20V) range and are fully characterized at 10V (±5V) and 30V (±15V). Figures 1 through 4 show the typical gaussianlike distribution over the ±5V to ±15V supply range and over the full temperature range. The +25°C maximum input offset voltage (VOS) for the “B” grade is 50µV and 100µV for the “C” grade. Both devices are fabricated in a new precision 40V complementary bipolar DI process.9µV/°C for the “C” grade. Without the series resistors. Output Phase Reversal Output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. and excellent temperature stabilization. A super-beta NPN input stage with input bias current cancellation provides low input bias current (180pA typical). which reduces DC input offset errors in precision. The low bias current TC also produces very low input offset current TC. INPUT ESD DIODE CURRENT LIMITINGUNITY GAIN Operating Voltage Range The devices are designed to operate over the 4. fcm = 10Hz). rent. in part. Gain and Phase.V OUTMAX ) × --------------------------R L LICENSE STATEMENT The information in this SPICE model is protected under the United States copyright laws. the Licensee should read this license. INCLUDING BUY NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. in whole. to anyone outside the Licensee’s company. 17 April 13. incidental. loan. nontransferable licence to use this model as long as the Licensee abides by the terms of this agreement. If the Licensee does not accept these terms. Open Loop Gain Phase and Simulated CMRR vs Frequency. 2010 FN6632. The model is configured for ambient temperature of +25°C. or in modified form. AC parameters incorporated into the model are: 1/f and flatband noise. Closed Loop Gain vs RL.” In no event will Intersil be liable for special. Large Signal Step Response. Slew Rate. This macro-model is provided “AS IS. permission to use the model is not granted. The AVOL is adjusted for 155dB with the dominate pole at 0. collateral. or license the macro-model. or consequential damages in connection with or arising out of the use of this macro-model. Before using this macro-model. The CMRR is set (210dB. CMRR. The Licensee may modify the macro-model to suit his/her specific applications. The DC parameters are VOS. total supply current and output voltage swing. Closed Loop Gain vs Frequency. 2) where: • TMAX = Maximum ambient temperature • θJA = Thermal resistance of the package • PDMAX = Maximum power dissipation of 1 amplifier • VS = Total supply voltage • IqMAX = Maximum quiescent supply current of 1 amplifier • VOUTMAX = Maximum output voltage swing of the application ISL28117 and ISL28217 SPICE Model Figure 52 shows the SPICE model schematic and Figure 53 shows the net list for the ISL28117 and ISL28217 SPICE model for a Grade “B” part. AND WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED. Figures 54 through 64 show the characterization vs simulation results for the Noise Voltage.ISL28117. a nonexclusive. Intersil reserves the right to make changes to the product and the macro-model without prior notice.02Hz. WHERE IS. The Licensee may not sell. IOS. The model uses typical parameters given in the “Electrical Specifications” Table beginning on page 4. Intersil Corporation hereby grants users of this macro-model hereto referred to as “Licensee”. (EQ. The input stage models the actual device to present an accurate AC representation. ISL28217 where: • PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) • PDMAX for each amplifier can be calculated using Equation 2: V OUTMAX PD MAX = V S × I qMAX + ( V S .4 . The model is a simplified version of the actual device and simulates important AC and DC parameters. and the Licensee may make copies of this macro-model for use within their company only. 9159E 17 R11 1 Vc Vg R12 1 18 L2 15.1E3 L1 15. ISL28217 .3nA R2 5E11 IEE 200E-6 9 + VOS 13E-6 1 Mirror Q3 + 7 EOS 8 5 Q5 3 SUPERB DX C5 2pF R4 4.ISL28117.12V D7 DX V6 21 1.44mA D6 DX 20 23 D9 DX V5 + G7 V+ + - V+ + E2 Vg 1.45k CASCODE 6 D1 IEE1 96E-6 V++ 4 5 VIN- VinV5 24 D12 DN + + - Vc Vmid + + - VIN+ V-VCM Voltage Noise V++ G1 4 D2 DX + V1 . V++ R3 4. SPICE SCHEMATIC Output Stage 18 + - + + VOUT + - + - R15 90 VOUT R16 90 April 13.86V Vg Input Stage V++ G5 R7 1.1V 25 R17 290 En In+ C6 1.99e10 C2 400pF R9 2.99e10 C3 400pF R10 2.1.9159E V-- + - 10 + - 13 + - 5 Vc Vmid Vmid G2 + 12 V2 1.4 .12V G8 + - V- + V-- + E3 V- D10 DY + G9 + G10 D11 DY Supply Isolation Stage FIGURE 52.86V 11 G3 R5 1 D4 DX + V3 .1.1E3 G6 V-VCM D3 DX D5 DX VCM 1ST Gain Stage 2nd Gain Stage Mid Supply Ref Common Mode Gain Stage V++ D8 DX 22 ISY 0. 2010 FN6632.2pF IOS VCM 0.45k 4 CASCODE Q4 C4 2pF 2 SUPERB Q1 Q2 R1 5E11 0.86V R8 1.86V R6 1 G4 + 14 V4 1. VOUT 9E1 * .MODEL DY D(IS=1E-15 BV=50 Rs=1) .0 V.1 7 Mirror Q_Q4 4 6 2 Cascode Q_Q5 5 6 3 Cascode R_R3 4 V++ 4.1E3 R_R10 V-.model Mirror pnp + is=4E-15 bf=150 va=50 ik=138E-3 rb=185 + re=0.16E-12f + kf=0 af=0 .11e-2 G_G10 23 V-.ISL28117.MODEL DX D(IS=1E-12 Rs=0. ISL28217 * source ISL28117_SPICEmodel * Revision B.162277 R_R11 VC 17 1 R_R12 18 VC 1 L_L1 17 V++ 15.162277 G_G6 V-. SR = 0.02Hz AOL.11e-2 G_G9 22 V-.model Cascode npn + is=502E-18 bf=150 va=300 ik=17E-3 rb=140 + re=0.1 * *Input Stage I_IOS IN+ VIN.model SuperB npn + is=184E-15 bf=30e3 va=15 ik=70E-3 rb=50 + re=0. SPICE NET LIST 19 April 13.VOUT * source ISL28107subckt * *Voltage Noise E_En IN+ VIN+ 25 0 1 R_R17 25 0 290 D_D12 24 25 DN V_V7 24 0 0.5V/µsec *Copyright 2009 by Intersil Corporation *Refer to data sheet “LICENSE STATEMENT” Use of *this model indicates your acceptance with the *terms and provisions in the License Statement.129384e-2 G_G2 V-. * Connections: +input * | -input * | | +Vsupply * | | | -Vsupply * | | | | output * | | | | | .44E-3 E_E2 V++ 0 V+ 0 1 E_E3 V-.VG 11 VMID 2. 2010 FN6632.2E-12 cjc=0.1) .23 DY V_V5 20 VOUT 1.ends ISL28117subckt FIGURE 53.45e3 C_C4 VIN.011 rc=900 cje=0.VG 1.VG VOUT 1.22 DY D_D11 V-. 210dB f=10Hz CMRR.45e3 R_R4 5 V++ 4. 155dB f=0.11 4 5 8.99e10 C_C2 VG V++ 4e-10 C_C3 V-.11e-2 G_G8 V-.VOUT VG 1.101 rc=180 cje=1.4 .0 2e-12 C_C5 8 0 2e-12 D_D1 6 7 DX I_IEE 1 V-.2E-12 R_R1 VCM VIN.08E-9 C_C6 IN+ VIN.DC 0.5E-12 cjc=2E-12 + kf=0 af=0 .VG 4e-10 D_D4 13 V++ DX D_D5 V-.model DN D(KF=6.99e10 R_R8 V-.065 rc=35 cje=1.5e11 R_R2 IN+ VCM 5e11 Q_Q1 2 VIN.44E-12 + kf=0 af=0 .83e-3 R_R7 VG V++ 1.1E3 I_ISY V+ V.9159E-3 L_L2 18 V-.12 R_R15 VOUT V++ 9E1 R_R16 V-.129384e-2 R_R5 11 V++ 1 R_R6 V-.9159E-3 * *Output Stage with Correction Current Sources G_G7 VOUT V++ V++ VG 1.VOUT VG V-.12 DX V_V1 10 11 1.12 V_V6 VOUT 21 1. supply currents.15.69e-9 AF=1) .subckt ISL28117subckt Vin+ Vin-V+ V.86 * *Mid supply Ref R_R9 VMID V++ 2.1.86 V_V2 11 12 1.VMID 2.14 DX V_V3 13 VG 1. November 20th 2009 LaFontaine * Model for Grade B Noise.1 SuperB Q_Q2 3 8 1 SuperB Q_Q3 V-.11 1 D_D2 10 V++ DX D_D3 V-.83e-3 G_G4 V-.11e-2 D_D6 VG 20 DX D_D7 21 VG DX D_D8 V++ 22 DX D_D9 V++ 23 DX D_D10 V-.VC VCM VMID 3.DC 200e-6 I_IEE1 V++ 6 DC 96e-6 V_VOS 9 IN+ 8e-6 E_EOS 8 9 VC VMID 1 * *1st Gain Stage G_G1 V++ 11 4 5 8.86 * *2nd Gain Stage G_G3 V++ VG 11 VMID 2.0 1 * *Common Mode Gain Stage with Zero G_G5 V++ VC VCM VMID 3.34E-12 cjc=0.1.DC 0.86 V_V4 VG 14 1. Rf = 100k Rg = 1k.99k RL = 1k RL = 10k 1 RL = 10k 0 RL = 4. Rf = 100k VS = ±20V CL = 4pF RL = 10k VOUT = 50mVP-P 60 AV = 1000 Rg = 100. SIMULATED CLOSED LOOP GAIN vs FREQUENCY 2 1 0 -1 GAIN (dB) -2 -3 -4 -5 -6 -7 VS = ±20V CL = 4pF AV = +1 VOUT = 50mVP-P 100 1k 10k RL = 100 100k 1M 10M RL = 499 RL = 4.4 . SIMULATED INPUT NOISE VOLTAGE 70 60 50 GAIN (dB) 40 30 20 10 0 AV = 10 Rg = 10k. Rf = 100k 0 100k 1M 10M AV = 1 Rg = OPEN. 2010 FN6632.0 1.0M 10M -10 10 Rg = OPEN.0M 10M -8 10 FREQUENCY (Hz) 1. Rf = 100k GAIN (dB) 40 AV = 100 VS = ±15V CL = 4pF RL = 10k VOUT = 50mVP-P 20 AV = 10 Rg = 10k. CHARACTERIZED CLOSED LOOP GAIN vs RL FIGURE 59.0k 10k 100k FREQUENCY (Hz) FIGURE 54. CHARACTERIZED INPUT NOISE VOLTAGE FIGURE 55.0 10 100 1. CHARACTERIZED CLOSED LOOP GAIN vs FREQUENCY FIGURE 57.2V AV = 1 100 10 10 1 1 10 100 1k FREQUENCY (Hz) 10k 100k 1. SIMULATED CLOSED LOOP GAIN vs RL 20 April 13. ISL28217 Characterization vs Simulation Results 100 INPUT NOISE VOLTAGE (nV/√Hz) INPUT NOISE VOLTAGE (nV/√Hz) VS = ±18. Rf = 0 100 1. Rf = 100k Rg = 1k.99k RL = 1k GAIN (dB) -2 -4 VS = ±15V CL = 4pF RL = 499 -6 AV = +1 VOUT = 50mVP-P -8 10 100 RL =100 1. Rf = 0 10k 1k 100 -10 10 FREQUENCY (Hz) FIGURE 56. Rf = 100k AV = 1 AV = 100 AV = 1000 70 Rg = 100.ISL28117.0k 10k 100k FREQUENCY (Hz) FIGURE 58.0k 10k 100k FREQUENCY (Hz) 1. SIMULATED OPEN-LOOP GAIN. CHARACTERIZED LARGE SIGNAL TRANSIENT RESPONSE vs RL VS = ±15V 200 180 160 140 120 100 80 60 40 20 0 -20 R = 10k L -40 CL = 10pF -60 SIMULATION -80 -100 0.6 LARGE SIGNAL (V) LARGE SIGNAL (V) 1.0 -2. PHASE vs FREQUENCY 200 CMRR (dB) 150 100 50 1m 10m 0.2 -1.2 0.4 -0.4 0 10 20 30 CL = 4pF AV = +1 VOUT = 4VP-P 40 50 60 TIME (µs) 70 80 90 100 VS = ±15V.8 0.0 1.ISL28117. 2010 FN6632.4 2.6 -2. SIMULATED LARGE SIGNAL 10V STEP RESPONSE 200 OPEN LOOP GAIN (dB)/PHASE (°) OPEN LOOP GAIN (dB)/PHASE (°) 160 PHASE PHASE 120 80 GAIN 40 GAIN 0 1 10 100 1k 10k 100k 1M 10M 100M -40 1.0m 10m 0.4 0 -0. SIMULATED OPEN-LOOP GAIN. PHASE vs FREQUENCY 250 FIGURE 63. ISL28217 Characterization vs Simulation Results (Continued) 2.1 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FIGURE 64.1m 1m 10m 100m FIGURE 61. SIMULATED CMRR vs FREQUENCY 21 April 13.4 . RL =10k 2 1 0 -1 -2 -3 CL = 4pF AV = +1 VOUT = 4VP-P 0 20 40 60 TIME (µs) 80 100 INPUT OUTPUT 3 FIGURE 60.1 1 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 62.8 -1. which are scheduled to release Q2 2010.9159E-3” FN6632.4957” to “15. V_VOS “13e-6” to “8e-6”. 11. R12 from “6k” to “1”. please see device information page for ISL28117. Edited Spice Schematic . B) Separated TCVOS specs for SOIC and MSOP Grade C packages.9159E”. changed the following: a) corrected part marking for ISL28117FBBZ from "28117 -B FBZ" to "28117 FBZ -B".3E-9” to 0.” from Note 1. IOS from “0. Common Mode Gain Stage with Zero change in G_G5 and G_G6 “5. Mid supply Ref R_R9 and R_R10 changed “1” to “2. For more information on MSL please see techbrief TB363. R1 from “6k” to 1. Added new TCVOS specs for MSOP Grade C package. 17 and 19. added after AOL “SR = 0. 15. R_R11 and R_R12 “6. ISL28117FBZ & ISL28217FBBZ devices 3/3/10 1/21/10 12/24/09 11/25/09 11/12/09 10/16/09 22 April 13. Please go to web to make sure you have the latest Rev. In “Ordering Information” on page 2. 2010 FN6632. 2. Added Evaluation Boards to “Ordering Information” on page 2.1E3”. Replaced typical application schematic on page 1.08. Updated Theta JA for ISL28217 8 Ld SOIC from 115°C/W to 105°C/W.08E-9”. 7.4957” to “15. L_L1 and L_L2 “95. 13. Edited Spice Net List .18” to “0. Part marking in “Ordering Information” on page 2 changed as follows: ISL28117FBBZ changed from "28117 FBZ -B" to "28117 FBZ" ISL28117FBZ changed from "28117 FBZ" to "28117 FBZ -C" ISL28217FBBZ changed from "28217 FBZ -B" to "28217 FBZ" ISL28217FBZ changed from "28217 FBZ" to "28217 FBZ -C" On page 7: Changed label in Figure 1 from “VS = +5V” to “VS = ±5V” On page 7: Changed label in Figure 2 from “VS = +15V” to “VS = ±15V” Changed Typical VOS spec from “13” to “8” (B Grade). Separated each part number with it's own specific T7 and -T13 suffix and removed “Add “-T7” or “-T13” suffix for Tape and Reel. land pattern was added and dimensions were moved from table onto drawing) c) Added "Add “-T7” or “-T13” suffix for tape and reel. Added “Related Literature*(see page 23)” on page 1.4 .ISL28117.Changed Revision from “A” to “B”. L2 from “95. Added new VOS specs for MSOP Grade C package. Updated ±15 and ±5V Electrical Specification table with the following edits: A) Separated VOS specs for SOIC and MSOP Grade C packages. Corrected part marking for ISL28217FBBZ from "28217-B FBZ" to "28217 FBZ -B" B) Updated package outline drawing to most recent revision (no changes were made to package dimensions. Updated “Ordering Information” on page 2 by adding two rows for MSOP packages ISL28117FUBZ and ISL28117FUZ. Input Stage changed in I_IOS from “0. Added “Thermal Information” on page 4 for ISL28117 MSOP package. 5.4 CHANGE 1. Date change from “October 29th 2009” to “November 20th 2009”. 4. Added POD for MSOP M8. Added applicable Theta JC Note 5.") e) removed "Coming Soon" from ISL28117FBBZ.5V/µsec. but not warranted. d) added Note 3 callout to all parts (Note 3 reads: "For Moisture Sensitivity Level (MSL). IB from “0. ISL28217 Revision History The revision history provided is for informational purposes only and is believed to be accurate.2 Updated Typical Performance Curves Figure 5.4957” to “15.1E3.3 FN6632. On page 2 “Ordering Information”." to the tape and reel Note 1. R10 from “1” to “2. 9.27046e-15” to “3.9159E”. ISL28217.08”. R9 from “1” to “2.162277”.3” to “0.L1 from “95. Added Pinout accordingly.118 to the end of datasheet 3.1E3”. Added Spice Model and license statement. Added Theta JC values to “Thermal Information” on page 4. “19” to “4” (C Grade).3” to “1”. DATE 3/18/10 REVISION FN6632. 10. such as. 25. Please go to web to make sure you have the latest Rev. 17. assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www. 31.intersil. 39 & 40 with new Figures 9 thru 20 (all “conservative channels”) c. and notebooks. On temperature curves.intersil. flat panel displays. Modified typical characteristics curves to show conservative performance.1 CHANGE 1. However. 20. page 1. For information regarding Intersil Corporation and its products.0 Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. 27. Removed former Figures 1. 2010 FN6632. no responsibility is assumed by Intersil or its subsidiaries for its use. Removed “very” from “.com/product_tree Intersil products are manufactured. the reader is cautioned to verify that data sheets are current before placing orders. 30.” 1st sentence. Replaced former Figures 19. 13. page 1. software and/or specifications at any time without notice. 37 & 38 (all Channel A curves) b. Intersil Corporation reserves the right to make changes in circuit design.com/products for a complete list of Intersil product families.ISL28117. Specific channel designations removed. changed formatting to indicate range from typical value. 18. nor for any infringements of patents or other rights of third parties which may result from its use.intersil. see www. 21. 29.com 23 April 13. Added temp labels to Figures 28 & 29 Initial Release 09/03/09 FN6632.intersil. please go to www. 24. but not warranted. 7. *For a complete listing of Applications. 32. see www. ISL28217 Revision History The revision history provided is for informational purposes only and is believed to be accurate.com/design/quality Intersil products are sold by description only.php For additional products. 34.com: ISL28117.4 . 23. ISL28217 To report errors or suggestions for this datasheet. 22. 5. 3. cell phones. 3. 31.intersil. 14. 35. 9. Information furnished by Intersil is believed to be accurate and reliable. please see the respective device information page on intersil. 26.com/reports/search.low noise. Added Figures 30. Removed “Low” from 6th bullet under features.. Accordingly.. handheld products. 32 4. Changes include: a..com/askourstaff FITs are available from our website at http://rel. Related Documentation and Related Parts.intersil. 33. 2. Go to www. The Company's products address some of the industry's fastest growing markets. (Continued) DATE 10/08/09 REVISION FN6632. 28. Intersil's product families address power management and analog signal processing functions. 36. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. Updated TCVos histogram on page 1 to match TCVos histogram Figure 6 on page 7 (same graphic) 5. 75 MAX 1.5m-1994.10 C SIDE VIEW “A 0.175 ± 0. tolerance : Decimal ± 0.43 ± 0. 6.27) (0.1 ID MARK 5 (0.ISL28117.63 ±0. TYPICAL RECOMMENDED LAND PATTERN 24 April 13. 2.10 4 PIN NO.35) x 45° 1.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0.4 . (5. Dimensions are in millimeters.25 M C A B 4° ± 4° SIDE VIEW “B” TOP VIEW 1. 08/09 4 4. Reference to JEDEC MS-012.40) 3.0 ± 0. Unless otherwise specified.10 A DETAIL "A" 0.076 0.60) NOTES: (1.25mm per side.45 ± 0. 4.1 0. 2010 FN6632. The pin #1 identifier may be either a mold or mark feature.27 0.075 GAUGE PLANE C SEATING PLANE 0. 5. Dimensioning and tolerancing conform to AMSE Y14.20 3.22 ± 0.90 ± 0.90 ± 0. Interlead flash or protrusions shall not exceed 0. Dimensions in ( ) for Reference Only.03 B 6.05 Dimension does not include interlead flash or protrusions.50) 1.23 DETAIL "A" (1.25 0. ISL28217 Package Outline Drawing M8. 05 5 PIN# 1 ID 1 2 B 0.0.4 .118 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 3.15mm max per side are not included.15 H 0. Dimensions are in millimeters.0±0.10 ± 0. 3/10 5 3.10 MAX SIDE VIEW 2 4. ISL28217 Package Outline Drawing M8.80) (4.5m-1994. 5. 3.85±010 DETAIL "X" C SEATING PLANE 0.00) NOTES: 1.08 M C A-B D SIDE VIEW 1 0. 6.10 C 3°±3° (5.25 0.55 ± 0.25 .036 0. Plastic or metal protrusions of 0.0. Plastic interlead protrusions of 0.65 BSC TOP VIEW 0. Dimensions are measured at Datum Plane "H". 4.20 3. 2010 FN6632. 2.40) (3.05 A 8 D DETAIL "X" 1.ISL28117.15 0.09 .15mm max per side are not included.0±0.40) TYPICAL RECOMMENDED LAND PATTERN 25 April 13.65) (0.40) (1. Dimensions in ( ) are for reference only.9±0.05 0. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14. (0.95 REF GAUGE PLANE 0.