TABLE OF CONTENTSS. NO 1 2 Date 08.02.20 16 15.02.20 16 Title Page NO. STUDY OF MENTOR GRAPHICS 1 IMPLEMENTATION OF BASIC GATES 4 a)NAND b)NOR 3 22.02.20 16 IMPLEMENTATION OF INVERTER 11 4 29.02.20 16 IMPLEMENTATION OF CURRENTMIRROR 16 5 14.03.20 16 IMPLEMENTATION OF 21 a)COMMON SOURCE AMPLIFIER b)CASCODE AMPLIFIER 6 21.03.20 16 IMPLEMENTATION OF FLIPFLOPS a)JK- FLIPFLOP b)D-FLIPFLOP 04.04.20 16 33 SIGNATURE 7 11.04.20 16 ASSIGNMENT 41 STUDY OF MENTOR GRAPHICS: Introduction: Mentor Graphics is an Electronic Design Automation (EDA) package. The suite of tools can handle anything from Printed Circuit Board (PCB) to Hardware Definition Language (HDL). In the circuit design area, there are tools for schematic capture, digital and analog simulation, physical layout, and design verification. On the micro (chip) level, there are tools for schematic capture, simulation, physical layout, design verification, and mask generation. Many libraries contain models for popular existing design components. Mentor Graphics Designer Schematic and Designer Layout provide individual engineers with professional tools for PCB design. Easily create printed circuit boards from start to finish or leverage service bureaus to complete circuit designs. The merits are listed below: Industry-proven, professional-grade technology. More than 365,000 footprints and symbols available. Limited to 50 square inches and six signal layers Unlimited connections with Designer premium editions. Popular reference designs available. Imports commonly used schematic/layout formats. Objective of this lab is to learn the Mentor Graphics HEP2 tools as well learn the flow of the Full Custom IC design cycle. To start with, create a schematic and attach the technology library called “TSMC018”. Adding a technology library will ensure that we can do front to back design. Steps involved in the Design Procedure: Circuit Design: To open the Mentor Server from client machine, one should open the Xmanager tool from Windows Desktop. Run the commands - csh, source /home/Mentor Graphics/csh/cshrc.hep, da_ica& to open Pyxis Schematic tool for design entry. In order to create new schematic select new _ Schematic and specify the name for the design in file name tab Select Library --> Device Lib/Source Lib/Generic Lib and add circuit components to the schematic area. Give connections using wires and give input and output ports to feed the inputs and verify the outputs. Change the properties of transistors by selecting the transistor and pressing ‘Q’.or right click and select edit properties, Change the ASIM_Model from NCH to N for NMOS & PCH to P for PMOS. Go to Add _ Generate Symbol, Select Replace existing & activate symbol options Change the shape of symbol if required. Save the symbol. Test Bench Generation: Close all schematics & symbols. Create a new schematic Sample_sim by selecting new schematic from session. Add symbol of the schematic made. Add_ Instance_ Choose Symbol. Add a Pulse Source at the input to inverter and a DC Voltage source VDD port. And do the necessary connections as per the figure given below. ** (from sources library we can pick various sources) Right click on the Pulse Generator Source and select Edit Properties and Change the values of the required parameters and apply the changes. Now from the menu bar click on check and save button. This will report if any errors present. Now click on “back” tab and then select ‘Simulation’ from the palette to run the Simulation and select ok. Select a New configuration (Give a new name for simulation). Now select the Session tab _simulator/viewer from Setup on the palette and ensure that the following options are set. Simulator _ Eldo and Viewer _ EZWave and then Ok. Select Lib/Temp/In _ “include files “provide the following path by selecting the browse button. $ADK/technology/ic/models/ami05.mod. Select Analyses _and enable “DC” and”Transient”. Select Transient Setup and change the stop time to 1000N. Select the input path A and then hold CTRL key and then output path Y and click on“Probes” from the palette. Select DC in Analysis tab, Plot from Task tab. Select add. Similarly select TRAN from Analysis tab and select add and close the window. Now click on Run Eldo tab from the palette where it opens 2 windows showing Various steps running in command line. Once it finishes it will invoke the EZWave Waveform viewer. If it is not invoked Click on the View Waves Tab from the palette to invoke the EZWave Waveform Viewer. Now the EZWave displays the input and output signals. CIRCUIT DIAGRAM: NAND GATE: EXP:2 IMPLEMENTATION OF BASIC GATES AIM: To implement the universal gates NAND and NOR. TOOL USED: Mentor Graphics. DESIGN PROCEDURE: 1. In the Pyxis Schematic, use the device/source/Generic library from the Palette area and implement the circuit using transistors (2 NMOS, 2 PMOS) as shown in the circuit diagram. 2. Assume a Logic Ratio of 2 and size the transistors using the formula (W/L)n = n/1 and (W/L)p=nr/1. 3. Set the ASIM model as ‘P’ for PMOS and ‘N’ for NMOS. 4. Give VDD and GND and suitable Bulk connection. 5. Check the circuit for any errors and generate symbol for the gate/Circuit. Close the Schematic. SIMULATION: 1. Open a New Schematic and add the generated symbol. Give a source/pattern generator for the inputs A and B for all possible input combinations. 2. Give a DC source for the VDD used in the circuit design. 3. Save and check for any errors and click on the Simulation in the Palette Area. 4. Click on Select Lib/Temp/In ‘include files’ provide the following path $ADK/technology/ic/models/ami05.mod. 5. Select Analyses and enable ’Transient’ and give the start time as 0 and end time as 1000ns. 6. Run the simulation and View & Verify the generated output wave. SIMULATION: OUTPUT: CIRCUIT DIAGRAM: NOR GATE: SIMULATION: OUTPUT: RESULT: NAND and NOR has been implemented and the results have been verified. CIRCUIT DIAGRAM: EXP :3 INVERTER AIM: To implement a basic inverter. TOOL USED: Mentor Graphics DESIGN PROCEDURE: 1. In the Pyxis Schematic, use the device/source/Generic library from the Palette area and implement the circuit using transistors (2 NMOS, 2 PMOS) as shown in the circuit diagram. 2. Assume a Logic Ratio of 2 and size the transistors using the formula (W/L)n = n/1 and (W/L)p=nr/1. 3. Set the ASIM model as ‘P’ for PMOS and ‘N’ for NMOS. 4. Give VDD and GND and suitable Bulk connection. 5. Check the circuit for any errors and generate symbol for the gate/Circuit. Close the Schematic. SIMULATION: 1. Open a New Schematic and add the generated symbol. Give a source/pattern generator for the inputs A and B for all possible input combinations. 2. Give a DC source for the VDD used in the circuit design. 3. Save and check for any errors and click on the Simulation in the Palette Area. 4. Click on Select Lib/Temp/In ‘include files’ provide the following path $ADK/technology/ic/models/ami05.mod. 5.Select Analyses and enable ’Transient’ and give the start time as 0 and end time as 1000ns. 6. Run the simulation and View & Verify the generated output wave. OUTPUT: RESULT: Thus the circuit for basic inverter was designed and verified. CIRCUIT DIAGRAM: BASIC CURRENT MIRROR: EXP:4 CURRENT MIRROR AIM: To implement a current mirror. TOOL USED: Mentor Graphics DESIGN PROCEDURE: 1. In the Pyxis Schematic, use the device/source/Generic library from the Palette area and implement the circuit using transistors (2 NMOS, 2 PMOS) as shown in the circuit diagram. 2. Assume a Logic Ratio of 2 and size the transistors using the formula (W/L)n = n/1 and (W/L)p=nr/1. 3. Set the ASIM model as ‘P’ for PMOS and ‘N’ for NMOS. 4. Give VDD and GND and suitable Bulk connection. 5. Check the circuit for any errors and generate symbol for the gate/Circuit. Close the Schematic. SIMULATION: 1. Open a New Schematic and add the generated symbol. Give a source/pattern generator for the inputs A and B for all possible input combinations. 2. Give a DC source for the VDD used in the circuit design. 3. Save and check for any errors and click on the Simulation in the Palette Area. 4. Click on Select Lib/Temp/In ‘include files’ provide the following path $ADK/technology/ic/models/ami05.mod. 5.Select Analyses and enable ’Transient’ and give the start time as 0 and end time as 1000ns. 6. Run the simulation and View & Verify the generated output wave. OUTPUT: RESULT: The current mirror has been implemented and the result has been verified. CIRCUIT DIAGRAM: EXP: 5 (A)COMMON SOURCE AMPLIFIER AIM: To implement a common source amplifier. TOOL USED: Mentor Graphics DESIGN PROCEDURE: 1.In the Pyxis Schematic, use the device/source/Generic library from the Palette area and implement the circuit using transistors (2 NMOS, 2 PMOS) as shown in the circuit diagram. 2. Assume a Logic Ratio of 2 and size the transistors using the formula (W/L)n = n/1 and (W/L)p=nr/1. 3. Set the ASIM model as ‘P’ for PMOS and ‘N’ for NMOS. 4. Give VDD and GND and suitable Bulk connection. 5. Check the circuit for any errors and generate symbol for the gate/Circuit. Close the Schematic. SIMULATION: 1. Open a New Schematic and add the generated symbol. Give a source/pattern generator for the inputs A and B for all possible input combinations. 2. Give a DC source for the VDD used in the circuit design. 3. Save and check for any errors and click on the Simulation in the Palette Area. 4. Click on Select Lib/Temp/In ‘include files’ provide the following path $ADK/technology/ic/models/ami05.mod. 5.Select Analyses and enable ’Transient’ and give the start time as 0 and end time as 1000ns. 6. Run the simulation and View & Verify the generated output wave. SIMULATION: OUTPUT: RESULT: The common source amplifier has been implemented and the result has been verified. CIRCUIT DIAGRAM: (B)CASCODE AMPLIFIER AIM: To implement a cascade amplifier. TOOL USED: Mentor Graphics DESIGN PROCEDURE: 1. In the Pyxis Schematic, use the device/source/Generic library from the Palette area and implement the circuit using transistors (2 NMOS, 2 PMOS) as shown in the circuit diagram. 2. Assume a Logic Ratio of 2 and size the transistors using the formula (W/L)n = n/1 and (W/L)p=nr/1. 3. Set the ASIM model as ‘P’ for PMOS and ‘N’ for NMOS. 4. Give VDD and GND and suitable Bulk connection. 5. Check the circuit for any errors and generate symbol for the gate/Circuit. Close the Schematic. SIMULATION: 1. Open a New Schematic and add the generated symbol. Give a source/pattern generator for the inputs A and B for all possible input combinations. 2. Give a DC source for the VDD used in the circuit design. 3. Save and check for any errors and click on the Simulation in the Palette Area. 4. Click on Select Lib/Temp/In ‘include files’ provide the following path $ADK/technology/ic/models/ami05.mod. 5.Select Analyses and enable ’Transient’ and give the start time as 0 and end time as 1000ns. 6. Run the simulation and View & Verify the generated output wave. SIMULATION: OUTPUT: RESULT: Thus the circuit for cascade circuit is designed and verified. CIRCUIT DIAGRAM: EXP :6 IMPLEMENTION OF FLIPFLOP (A)JK FLIP FLOP AIM: To implement a JK Flip-flop using negative edge. TOOL USED: Mentor Graphics DESIGN PROCEDURE: 1.In the Pyxis Schematic, use the device/source/Generic library from the Palette area and implement the circuit using transistors (2 NMOS, 2 PMOS) as shown in the circuit diagram. 2. Assume a Logic Ratio of 2 and size the transistors using the formula (W/L)n = n/1 and (W/L)p=nr/1. 3. Set the ASIM model as ‘P’ for PMOS and ‘N’ for NMOS. 4. Give VDD and GND and suitable Bulk connection. 5. Check the circuit for any errors and generate symbol for the gate/Circuit. Close the Schematic. SIMULATION: 1. Open a New Schematic and add the generated symbol. Give a source/pattern generator for the inputs A and B for all possible input combinations. 2. Give a DC source for the VDD used in the circuit design. 3. Save and check for any errors and click on the Simulation in the Palette Area. 4. Click on Select Lib/Temp/In ‘include files’ provide the following path $ADK/technology/ic/models/ami05.mod. 5.Select Analyses and enable ’Transient’ and give the start time as 0 and end time as 1000ns. 6. Run the simulation and View & Verify the generated output wave. SIMULATION: OUTPUT: RESULT: The JK flipflop has been implemented and the result has been verified. CIRCUIT DIAGRAM: (B)D FLIP FLOP AIM: To implement a D Flip-flop using negative edge. TOOL USED: Mentor Graphics DESIGN PROCEDURE: 1. In the Pyxis Schematic, use the device/source/Generic library from the Palette area and implement the circuit using transistors (2 NMOS, 2 PMOS) as shown in the circuit diagram. 2. Assume a Logic Ratio of 2 and size the transistors using the formula (W/L)n = n/1 and (W/L)p=nr/1. 3. Set the ASIM model as ‘P’ for PMOS and ‘N’ for NMOS. 4. Give VDD and GND and suitable Bulk connection. 5. Check the circuit for any errors and generate symbol for the gate/Circuit. Close the Schematic. SIMULATION: 1. Open a New Schematic and add the generated symbol. Give a source/pattern generator for the inputs A and B for all possible input combinations. 2. Give a DC source for the VDD used in the circuit design. 3. Save and check for any errors and click on the Simulation in the Palette Area. 4. Click on Select Lib/Temp/In ‘include files’ provide the following path $ADK/technology/ic/models/ami05.mod. 5.Select Analyses and enable ’Transient’ and give the start time as 0 and end time as 1000ns. 6. Run the simulation and View & Verify the generated output wave. SIMULATION: OUTPUT: RESULT: The D flip-flop has been implemented and the result has been verified. AIM TO implement the given expression F=ab+cd’ using pass transistor logic. SOFTWARE REQUIRED Mentor Graphics PROCEDURE 1. 2. 3. 4. Reduce the given expression. Create a cell for transmission gate. Transmission gate is combination of NMOS and PMOS. Call the cell for each every min-terms and max-terms in the given expression; accordingly it can give the logic in the transmission gate input. 5. Connect the cell which gives the required output for the expression. 6. If for example CLK is given the input means CLK bar is given to NMOS input like vice versa Inverter Circuit with simulation and output: Circuit Diagram: Circuit Diagram: Output Waveform: Result: Thus the implementation and simulation of the expression F=ab+cd’ is done using mentor graphics tool.