Field Programmable Gate Array Implementation of 14 bit Sigma-Delta Analog to Digital Converter

I nt ernat i onal Journal of E mergi ng Trends & Technol ogy i n Comput er Sci ence (I JE TTCS) Web Site: www.ijettcs.org Email: [email protected], [email protected] Volume 1, Issue 2, July – August 2012 ISSN 2278-6856 Vol ume 1 , I ssue 2 Jul y-August 2 0 1 2 Page 2 2 9 Abstract: This paper the design and FPGA implementation of a delta sigma A/D convertor. The proposed converter has been designed using Xilinx system generator tool, which reduces the design cycle by directly generating efficient VHDL code. The VHDL code has been implemented on a Spartan 3E xc3s100e-4vq100 FPGA using ISE 12.4 tool. Keywords: Analog to Digital Convertor, Field Programmable Gate Array, Sigma–Delta, System Generator, Xilinx. 1. INTRODUCTION The most important advantages of digital processing over analog processing are a perfect storage of digitized signals, unlimited signal-to-noise ratio, the option to carry out complex calculations, and the possibility to adapt the algorithm of the calculation to changing circumstances[10]. If an application wants to use these advantages, analog signals have to be converted with high quality into a digital format in an early stage of the processing chain. And at the end of the digital processing the conversion has to be carried out in the reverse direction. The digital-to-analog translates the outcome of the signal processing into signals that can be rendered as a picture or sound. This makes analog-to-digital (A/D) conversion a crucial element in the chain between our world of physical quantities and the rapidly increasing power of digital signal processing. Fig 1 shows the (ADC) as the crucial element in a system. Figure 1: The A/D and D/A converters [10] The work on electronic ADC was started with the invention of Pulse code modulation (PCM) in 1921[1]. A significant development in ADC technology during the period was the electron beam coding tube described by R. W. Sears in [4]. The basic algorithm used in the successive approximation ADC conversion is based on the determination of an unknown weight by a minimal sequence of weighing operations [5]. Later CMOS was the ideal process for the sigma-delta (Σ-∆) architecture, which became the topology of choice for ADCs used in voice band and audio applications, as well as in higher resolution, low frequency measurement converters. The Σ-∆ architecture began to replace the parallel ADCs in audio applications. Σ-∆ offered much higher oversampling ratios, thereby relaxing output filter requirements, as well as provided higher dynamic range with lower distortion. In this paper Σ-∆ ADC has been implemented on FPGA using system generator tool by Xilinx. The performance of the Σ-∆ ADC has also evaluated by converting its digital output again into analog domain. 2. PRELIMINARIES OF A/D CONVERSION Signals, in general, can be divided into two categories an analog signal, x(t), which can be defined in a continuous- time domain and a digital signal, x(n), which can be represented as a sequence of numbers in a discrete-time domain as shown in Fig 2. The time index n of a discrete- time signal x(n) is an integer number defined by sampling interval T[8]. Thus, a discrete- time signal, x*(t), can be represented by a sampled continuous-time signal x(t) as: *( ) ( ) ( ) n x t x t t nT  · =÷· = ÷ ¿ (1) Where, ( ) 1 t  = , 0 t = 0, elsewhere Most ADCs can be classified into two groups according to the sampling rate criteria. Nyquist rate converters, such as a successive approximation register (SAR), double A practical A/D converter transforms x(t) into a discrete- time digital signal, x*(t), where each sample is expressed Field Programmable Gate Array Implementation of 14 bit Sigma-Delta Analog to Digital Converter Sukhmeet Kaur 1 , Parminder Singh Jassal 2 1 M.Tech Student , Department of Electronics and Communication Engineering, Yadavindra College of Engineering, Punjabi University Guru kashi Campus , Talwandi Sabo – 151 302 , Punjab (India) 2 Assistant Prof., Department of Electronics and Communication Engineering, Yadavindra College of Engineering, Punjabi University Guru kashi Campus , Talwandi Sabo – 151 302 , Punjab (India) I nt ernat i onal Journal of E mergi ng Trends & Technol ogy i n Comput er Sci ence (I JE TTCS) Web Site: www.ijettcs.org Email: [email protected], [email protected] Volume 1, Issue 2, July – August 2012 ISSN 2278-6856 Vol ume 1 , I ssue 2 Jul y-August 2 0 1 2 Page 2 3 0 with finite precision. Each sample is approximated by a digital code, i.e., x(t) is transformed into a sequence of finite precision or quantized samples x(n). Integration, and oversampling converters, sample analog signals which have maximum frequencies slightly less than the Nyquist frequency, f N = fs/ 2, where fs is the sampling frequency [2]. Meanwhile, oversampling converters perform the sampling process at a much higher rate, f N << Fs, where Fs denotes the input sampling rate. Figure 2: Generalized ADC process [8] Fig. 3 illustrates the conventional A/D conversion process that transforms an analog input signal x(t) into a sequence of digital codes x(n) at a sampling rate of fs = 1/T, where T denotes the sampling interval. Figure 3: Conventional ADC process [8] ( 2 )/ 1 ( ) ( ) ( ) j n t T n n x t t nT x t e T   · · =÷· =÷· ÷ = ¿ ¿ (2) also 2 ( 2 )/ 1 1 *( ) ( ) ( ) s j f nt j n t T n n x t x t e x t e T T   · · =÷· =÷· = = ¿ ¿ (3) Eqn. 2 states that the act of sampling (i.e., the sampling function): ( ) ( ) n x t t nT  · =÷· ÷ ¿ is equivalent to modulating the input signal by carrier signals having frequencies at 0, fs, 2fs,. . .. In other words, the sampled signal can be expressed in the frequency domain as the summation of the original signal component and signals frequency modulated by integer multiples of the sampling frequency Thus, input signals above the Nyquist frequency, f n , cannot be properly converted and they also create new signals in the base- band, which were not present in the original signal. This non-linear phenomenon is a signal distortion frequently referred to as aliasing [6]. The distortion can only be prevented by properly lowpass filtering called the anti- aliasing filter. In addition to an anti-aliasing filter, a sample and hold circuit is required. Although the analog signal is continuously changing, the output of the sample and hold circuitry must be constant between samples so the signal can be quantized properly. This allows the converter enough time to compare the sampled analog signal to a set of reference levels that are usually generated internally [7]. If the output of the sample-and- hold circuit varies during T, it can limit the performance of the A/D converter subsystem.Each of these reference levels is assigned a digital code. The process of converting an analog signal into a finite range number system introduces an error signal that depends on how the signal is being approximated. This quantization error is on the order of one least-significant-bit in amplitude, and it is quite small compared to full-amplitude signals. However, as the input signal gets smaller, the quantization error becomes a larger portion of the total signal. When the input signal is sampled to obtain the sequence x (n), each value is encoded using finite word lengths of B-bits including the sign bit. Assuming the sequence is scaled such that ( ) 1 x n s for fractional number representation, the pertinent dynamic range is 2. Since the encoder employs B-bits, the number of levels available for quantizing x (n) is 2 B . The interval between successive levels, q, is therefore given by: 1 1 2 B q ÷ = (4) which is called the quantization step size. Mean square value of quantization error can be calculated as [5]: / 2 2 2 2 2 2 ( )/2 1 2 12 3 q B e q q E e e de q  ÷ ÷ = = = = } (5) where E denotes statistical expectation 3. Σ-∆ A/D CONVERTER Fig. 4 shows the block diagram of a Σ-∆ A/D converter. The 1-bit digital output from the modulator is supplied to a digital decimation filter which yields a more accurate representation of the input signal at the output sampling rate of fs. In the figure is a first-order Σ-∆ modulator. It consists of an analog difference node, an integrator, a 1- bit quantizer (A/D converter), and a 1-bit D/A converter in a feed- back structure. The modulator output has only 1-bit (two levels) of information, i.e., 1 or -1. The modulator output y(n) is converted to x(t) by a 1-bit D/A converter. The input to the integrator in the modulator is the difference between the input signal x(t) and the quantized output value y(n) converted back to the I nt ernat i onal Journal of E mergi ng Trends & Technol ogy i n Comput er Sci ence (I JE TTCS) Web Site: www.ijettcs.org Email: [email protected], [email protected] Volume 1, Issue 2, July – August 2012 ISSN 2278-6856 Vol ume 1 , I ssue 2 Jul y-August 2 0 1 2 Page 2 3 1 predicted analog signal, x(t). Provided that the D/A converter is perfect, and neglecting signal delays, this difference between the input signal x(t) and the fed back signal x(t) at the integrator input is equal to the quantization error. This error is summed up in the integrator and then quantized by the 1-bit A/D converter. Figure 4: Block Diagram of Sigma delta A/D converter [8] Although the quantization error at every sampling instance is large due to the coarse nature of the two level quantizer, the action of the Σ-∆ modulator loop is to generate a ±1 output which can be averaged over several input sample periods to produce a very precise result. The averaging is performed by the decimation filter which follows the modulator. 4. FPGA IMPLEMENTATION OF Σ-∆ ADC Σ-∆ ADC has been implemented using System Generator tool of Xilinx, which reduces the design cycle. The snapshot of the ADC has been shown in Fig 5. Figure 5: Snapshot of the Set-Up Fig. 6 shows the block diagram of ADC. ADC employs a sequential binary search to arrive at the appropriate output sample. The sample rate of the ADC is computed as ( ) ( ) ( ) ( ) 1 2 1 1 clk sr MSBI mst f ADC F MSBI + = × + × + Samples/sec (6) Where is the most significant bit of the DAC input and is filter settle time constant.This approach makes the ADC unsuitable for applications requiring a high sampling rate. The 'ADC Out Register' captures the reference shifter output after a sample has been computed, then produces the ADC output sample. The 'ADC Out Register' captures the reference shifter output after a sample has been computed, then produces the ADC output sample. The 'ADC Out Register' captures the reference shifter output after a sample has been computed, then produces the ADC output sample. The 'ADC Out Register' captures the reference shifter output after a sample has been computed, then produces the ADC output sample. 4 sampl e 3 ADC_Sampl ed 2 ADCout 1 DAC_dri ver z -1 a b a = b z -1 rel1 z -1 and l 2 z -1 and l 1 z -1 [a:b] a b a = b AgtR shif t mask ref _shif ter Reference Shifter shif t mask Mask Shi fter [shi ft] [shi ft] l oad di n en -- FSTM Counter ++ DAC Sampl e Counter 0 0 d en q z -1 ADCOut Regi ster 0 'c1' 1 AgtR Figure 6: Block Diagram of ADC 1 DAC_Out d rst q z -1 r1 [a:b] a b a + b Sigma Adder d rst q z - 1 a b a + b Delta Adder 0 0 0 hi l o } hi l o } 1 DAC_In Figure 7: Block Diagram of DAC Fig. 7 shows block diagram of DAC. The Delta Adder computes the difference between the current DAC input and the current DAC output. The two concatenators create a 16-bit output with the DAC output copied in the two MSB positions. This effectively creates a difference from the Delta Adder when the DAC output is 1. The Sigma Adder accumulates the differences produced by the Delta Adder by using 'r 1 ' to storing the adder output on each successive cycle. The MSB of the 'r 1 ' output is sliced off and provides the DAC output. The pulse string is I nt ernat i onal Journal of E mergi ng Trends & Technol ogy i n Comput er Sci ence (I JE TTCS) Web Site: www.ijettcs.org Email: [email protected], [email protected] Volume 1, Issue 2, July – August 2012 ISSN 2278-6856 Vol ume 1 , I ssue 2 Jul y-August 2 0 1 2 Page 2 3 2 registered before it is driven on the DAC output port. The proposed ADC has been verified by converting its output back to analog domain by using DAC. Table 1 shows the comparison of ADC input and output of DAC. The results show that the proposed design is quite accurate in converting the analog data into digital data. The small error shown in Table 1 may be a due to inaccuracy of DAC. Figure 8: Internal View of Top Level RTL Schematic of Proposed ADC The summary of the resources utilized has been shown in table 2. Table 2: Resource Utilization for Spartan 3E xc3s100e- 4vq 100Device Device Utilization Summary (estimated values) Logic Utilization Used Available Utilization Number of Slices 38 960 3% Number of Slice Flip Flops 55 1920 2% Number of 4 input LUTs 45 1920 2% Number of bonded IOBs 3 66 4% Number of GCLKs 1 24 4% 5. CONCLUSION This paper presents the design and implementation of proposed Σ-∆ ADC. The proposed design has been implemented on Spartan 3E xc3s100e-4vq 100 FPGA Device and only consumes 38 number of slices, number of 55 Slice Flip Flops, 45 number of 4 input LUTs, 3 number of bonded IOBs and 1 number of GCLKs out of available 960, 1920, 1920, 66 and 24 respectively. The proposed design has also been verified for its accuracy. REFERENCES [1] Paul M. Rainey, "Facimile Telegraph System," U.S. Patent 1,608,527, filed July 20, 1921, issued November 30, 1926. [2] H. Nyquist, "Certain Factors Affecting Telegraph Speed," Bell System Technical Journal, Vol. 3, April 1924, pp. 324-346. [3] H. S. Black, "Pulse Code Modulation," Bell Labs Record, Vol. 25, July 1947, pp. 265-269. [4 R. W. Sears, "Electron Beam Deflection Tube for Pulse Code Modulation," Bell System Technical Journal, Vol. 27, pp. 44-57, Jan. 1948. [5] W. W. Rouse Ball and H. S. M. Coxeter, Mathematical Recreations and Essays, Thirteenth Edition, Dover Publications, 1987, pp. 50, 51. [6] H. Nyquist, “Certain topics in telegraph transmission theory,” AIEE Trans., pp. 617-644, 1928. [7] M. Armstrong, et al, “A COMS programmable self- calibrating 13b eight-channel analog interface processor,” ISSCC Dig. Tech. Paper, pp. 44-45, Feb. 1987. [8] Sangil Park, “Principles of Sigma-Delta Modulation for Analog-to- Digital Converters” Motorola Digital Signal Processors. [9] Ms.N.P.Pendharkar, Dr.K.B.Khanchandani Design, Development & Performance Investigations of Sigma-Delta ADC using CMOS Technology, International Journal of Advanced Engineering & Application, Jan 2011 Issue [10] Marcel J.M. Pelgrom “Analog-to-Digital Conversion http://www.scribd.com/doc/60454030/ Analog-to-Digital-Conversion.