1ECSE 431 - Final Project Report Vincent Arabian (260429181), Felix Le Dem (260363961), Payom Meshgin (260431193) and Anita Szilagyi (260366272) I. INTRODUCTION The goal of this project was to design a system on the Altera DE2 board that takes in a digital video signal encoded in ITU656 format, processes it and outputs the signal to a VGA-compatible display. II. DESIGN IMPLEMENTATION As seen on Figure 1, the system consists of an FPGA connected to a set of components present on the Altera DE2 board: The ADV7181 analog video decoder (ITU decoder), the ADV7123 video digital-to-analog converter (DAC) and 8 megabytes of SDRAM memory. The general operation of the systems is as follows: • The ITU decoder continuously sends out a serial stream of digital video data encoded in ITU656 format (YCbCr 4:2:2, 720*480 resolution, interlaced video). • A Grab interface extracts the ram video image and sends it out to the NIOS driver, which processes the data (adding the frame counter, convolution, etc. • The processed video is sent via the Avalon bus to the memory controller of the SDRAM, which stores the data such that the data associated to an entire frame of video is located in a contiguous address range, hence deinterlacing the video. • Meanwhile, the VGA controller makes a request for a line of video data (equivalent to one horizontal line in a frame). The DMA engine accepts the request, and in turn requests the line from memory via the Avalon bus • The line is eventually sent from memory to the DMA controller, which in turn pipelines the line to the DMA engine • The DMA engine stores the line inside the line buffer, which fills up with video data. • The VGA controller grabs onto each line and decodes it in RGB format. • The output is sent to a VGA-enabled monitor, which displays each frame at an effective rate of 30 frames per second. A. New Register File The register file version that was used for the NIOS project had to be modified to incorporate the new interrupt source (i.e. rising or falling edge of GACTIVE) and to change the registers that were used (i.e. switch from registers such as Fig. 1. Block diagram of overall design TCMP0, TCMP1, etc to registers GCTRL, GFSTART and so on). It is worth mentioning that the architecture of the register file component was split into multiple functional processes, each with its own role (i.e. “write” process, “read” process, “write interrupt” and “set interrupt”). This is a significant improvement from the previous version as it makes it a lot easier to debug and expand the component. The new source for interrupts was the start of a video field or the end of a video field. The start of the video field was signaled by the signal GACTIVE (belonging to the Grab Interface) going high. This also represented the start of valid video coming out of the grab interface and going towards the SDRAM. At the same time, the end of field was signaled by GACTIVE going low, representing the end of valid video for a field. For the purpose of the present project, the end of field source was used to service the interrupts. In order to catch the transition of GACTIVE from high to low or from low to high, an edge detection circuit was implemented in the register file component. It consisted of two extra processes: one for detecting the transition and another one for actually setting the appropriate bit in the GINT register. This was done due to the fact that a signal cannot be successfully driven by more than one process. The fields of several registers were mapped as conduit end for the Qsys system. These fields communicated directly with the other Qsys components that they served. This was done in order to bypass the Avalon bus and to speed up the communication between components. As an example, the way the register file was able to detect the rising or falling edges of GACTIVE was by receiving the current status of GACTIVE from the grab interface. 2 B. New QSYS system Other components were changed and/or added to the previously built QSYS system. Apart from the modified register file, two new components were added, namely the grab interface and the memory controller. C. Flow of data / Acquisition Overview The video data sent from the external device through the FPGA is captured by the grab interface. The grab then decodes the signals it receives into raw video data, which then it writes into the SDRAM. To accomplish that, it places the data on the Avalon bus, since both the grab interface and the memory controller are part of the QSYS system. Once in the memory, the data is ready to be picked up by the DMA engine and sent further through the line buffer and VGA controller to the screen. D. NIOS driver 1) Initialization: The NIOS controls the way in which the grab component writes to the memory. It does so by writing into the control registers located in the register file. The fields of these registers are directly connected to the grab interface through its conduit end interface. These control registers need to be initialized properly for the grab to be able to capture the first field of the first frame. Therefore: • GCTRL’s fields must be set as such: – GMODE signals the type of the field being grabbed; – GFMT signals if the capture is in color or BW – GSSHT arms the grab; • GFSTART gives the SDRAM address where the grab should start writing a field • GLPITCH represents the distance between 2 consecu- tive lines in memory, i.e. how much the value of the address “jumps”; it is normally 2 * line length, since fields are arriving interlaced • GINT controls the handling of interrupts: either at the start of frame or end of frame. 2) Interrupt Service Routine: The interrupt service routine handles the way the grab interface is programmed between two fields. It also has to take into account the end of frame event. In our implementation, a check is done at the beginning of the ISR: i f ( f i e l d numbe r == 1) { / / handl e i n t e r r u p t s e n t / / when t he grab f i n i s h e d / / wr i t i n g t he f i r s t f i e l d / / i n t o memory f i e l d numbe r = 2; } e l s e { / / handl e i n t e r r u p t s e n t / / when t he grab f i n i s h e d / / wr i t i n g t he s econd f i e l d / / i n t o memory f i e l d numbe r = 1; } The above implementation was needed in order to dis- tinguish which field’s interrupt is being serviced. The field number variable is a global variable that changes its value in both branches of the if-statement, according to which field is being serviced. Furthermore, the switch to a new frame had to be incor- porated if the second field sent the interrupt. This was done as such: f r ame number ++; i f ( f r ame number == 3) { f r ame number = 1; / / make changes t o o v e r wr i t e / / f i r s t f rame i n memory } e l s e { / / make changes t o wr i t e t he / / s econd c o n s e c u t i v e f rame / / i n t o memory } Based on which field sent the interrupt, the registers (and their fields) had to change accordingly: • GFSTART had to either – Revert to 0 after the second frame – Get set to start of frame GFSTART + length of one line for the second field of each frame – Get set to previous start of frame GFSTART + length (in bytes) of the frame that just finished being written into memory. • GMODE field of GCTRL had to be change its value to odd if previously even or to even if previously odd. E. Validation Before merging the acquisition with the DMA and VGA controller, a thorough simulation was done. We had to make sure that the grab wrote correctly to the SDRAM i.e. that the frames were de-interlaced properly and that the cycling of frames in memory was done correctly. At the same time, the interrupt service routine had to be tested to see if the switch between odd fields and even fields was done correctly. For the purpose of the simulation we used the provided video decoder. This produced 8 lines per frame, each of length 256 bytes. The full simulation can be seen in the appendix. 1) Communication between grab interface and register file: The communication between the grab and the register file can be seen in the waveform below. The boxes are color coded to show how the data is transmitted. First the data is written into the register file by the C application in Eclipse; 3 very soon after that, the data is communicated to the grab component through the register file’s conduit end interface. In the case of this test, the expected results match the actual results. Fig. 2. Simulation of the grab interface swtching between fields The following simulation snippet shows how new values are set in the interrupt service routine for the grab interface when switching between fields. (i.e. GMODE changes from 2 to 3, meaning change from grabbing next odd field to grabbing the next even field): Fig. 3. Field Switch In the next test, we show how the grab receives the correct information about the next field at the end of each field (i.e. when the eof interrupt is serviced). The 256 bytes per line in our test data leads to a GLPITCH value of 512 (since the grab needs to skip one line when writing into memory for the purpose of de-interlacing the frame). We expect the first line to be written into address 0x00, the second one into address 25610 × 0x100 (the address is 0 + 256, meaning the starting address of the first line in the second field has an offset of 256 one line from the previous field’s starting address. This is done in order to de- interlace the frame). Therefore, when done with the first field of the first frame, we expect to have 4GFSTART = 25610 = 0 × 0100. When done with a frame, the value of GFSTART needs to be updated in an appropriate manner. Therefore, we expect to see: new GFSTART = old GFSTART + (GLPITCH/2) × 8. GLPITCH is divided by 2 in order to obtain the actual length of a line in bytes and then multiplied by 8 because there are 8 lines per frame (4 in each field). This leads to: new GFSTART = old GFSTART +GLPITCH ∗ 4. So, the expected value of GFSTART at the end of the first frame is 0 + 512 × 4 = 204810 = 0 × 0800. This is the address in SDRAM where the grab will start writing the second frame. In the waveform below, it is shown that the actual results match the expected results, concluding that the switching of GFSTART is done correctly for the purpose of de-interlacing. As a side-note, it can also be seen that GFSTART switches back to being 0 after 4 fields (= 2 frames). This happens due to the choice of having 2 frames at a time in memory: one being written and one already written and ready for the DMA to read. The test was done before any kind of processing was incorporated. Fig. 4. Change of GFSTART after an interrupt Finally, it can be seen here that as data is being placed on the writedata bus of the grab interface, the same data is retrieved and placed into memory in the SDRAM: Fig. 5. Writing into SDRAM F. DMA engine The newest element in the design was a DMA (direct memory access) engine. The engine, implemented as a finite state machine, receives a request for a frame by the VGA controller in addition to line requests. Once granted, the request translates into a new request on the Avalon bus for bursts of data representing a line of a frame of video located in SDRAM. If the data is valid, the DMA engine places the contents of the line into the line buffer in address order, preparing the buffer for a read from the VGA controller. Fig. 6. Example of clock-domain crossing (for the linereq signal) The major issue regarding the DMA engine lies in its use of inputs in a different clock domain (the 27 MHz clock). In order to avoid propagating metastabilities in the logic circuit, a series of 3 pipelined flip flops were added at the inputs of the DMA that were connected to the VGA controller (the start of frame and linereq signals), hence changing the clock domain of the new signals to the 100 MHz domain. The result of this pipeline was simulated and shown on figure 6. The finite state machine of the DMA controller is shown on figure 7. The conditions in the state machine are tested at every clock cycle of the 100 MHz PLL. 4 Fig. 7. FSM diagram of the VGA controller In simulation, the FSM was shown to function correctly, as seen on figure 8 Fig. 8. Simulation of the FSM cycling through its states 1) Idle: When the frame start signal is asserted high, the burst base address is set to the register value of DMAFS- TART. When there’s a new line request, the state changes to the request state, where the controller starts requesting bursts of data. 2) Request: The DMA controller first checks if the line has been fully transferred from the memory. Otherwize it asserts the read en signal to high, sets the address to the value of the burst base address plus a burst offset, and then goes to the wait state. It also sets the burst count to the desired size of the burst. If the controller has reached the end of a line when entering the request state, the next state will be the idle state. 3) Wait: The controller will stay in this state as long as the wait request signal is held high by the Avalon interface. Once the wait request signal is lowered, the burst request has been acknowledged and can now lower the read en signal and move to the receive state. 4) Receive: It stays in this state as long as the burst of data isn’t finished. It counts the number of clock cycles where the data valid signal is held high in order to determine when the burst is complete. Once the burst is done, it changes state to the request state. G. Verification To verify the proper operation of the DMA engine, we tested that it first is able to receive all the data available on the Avalon bus when it makes a line request. Figure 9 shows an example of data being stored in to the line buffer from the DMA component. Note that the entirely of the incoming data is fully stored into the line buffer. Figure 10 shows an entire 128 by 8 pixel frame passing through the DMA controller. Fig. 9. Simulation of the FSM cycling through its states Fig. 10. Simulation of a full frame through the DMA controller H. VGA Controller The major modification made to the VGA controller was to set the VGA controller as the master component in the de- sign, meaning that it was ultimately responsible for the entire operation of the circuit. In order to implement this change, a new signal, start of frame was flagged at the beginning of every frame. This flag would then be sensed by the DMA controller, which uses the flag to synchronize to each frame read from memory. This change results in the VGA controller controlling when blanking occurs, rather than it taking the blanking signal from the source video as was the case in previous version of the DMA. Fortunately, the colour space converter, did not require any major modifications except that the 16 bit chunks of data were arriving with the Y component first instead of the Cb/Cr component. 5 III. PROCESSING In the main C function’s “while(1)” loop, two if statements were implemented to detect the presence of the 3rd and 4th switch. The 3rd switch would start the frame count, and the 4th switch would start the convolution (edge detection). A. Frame Count To be able to display a font, the first step to take was to create a bit array of 1s and 0s to represent each digit 0 through 9. Each character was to be displayed on a 12 by 12 pixel 1-bit bitmap, and thus the array was 1440 bits long. The position of a zero in the array indicated that the original pixel in the frame was not to be modified (a blank pixel). The position of a one indicates the presence of a character’s pixel. To map this array, each character was represented using ones and zeros. For example, for the digit zero, we have the scheme: 000000000000 011111111110 011111111110 011000000110 011000000110 011000000110 011000000110 011000000110 011000000110 011111111110 011111111110 000000000000 If statements were used with GACTIVE to detect the passing of each frame. At this point, the code would calculate the frame rate using the register file’s counter. The frame rate, a two digit number, could then be passed to the “getDigits” function, enabling to retrieve the digits and then display them in the function “write()” using the above mentioned array. The write() function would rewrite to the top left of a frame before displaying it. This required 3 for loops, one for each line, row, and character of the array. An excerpt of the write() function is provided in the appendix. As seen in the sample picture in the appendix, the frame counter has been successfully implemented, displayed in the upper left corner of the VGA monitor. B. Convolution Edge detection can be performed by obtaining the x and y gradient of the luminance for each pixel, and summing the values together. The resulting pixel would have high luminance if there is an edge, and low luminance otherwise. The function used for edge detection is shown in the appendix. Unfortunately, running the convolution engine resulted in frozen frames. Furthermore, the edge detection was not performed entirely. It was most likely getting stopped by an interrupt, but due to time constraints, we were unable to officially identify the source of the problem. In order to improve the functionality of the edge detection, we would need to write to the SDRAM in a faster way, preferably with some burst instead of writing each byte individually. This would have improved all processing sig- nificantly. IV. POSSIBLE IMPROVEMENTS A. Improvements on the design There are some additional features that could be imple- mented to improve our design. Features such as horizontal and vertical zoom, line reversal, and frame reversal are additions that can be made for future iterations of the VGA and DMA designs. On the NIOS driver side, features such as frame rate display and convolution can also be implemented. B. Architecture improvements Architectural improvements can be made such that the DMA and the DMA controller become a single entity. In addition, in order to exploit the efficiencies of using a monochrome format, the architecture of our VGA controller has to be modified such that it only reads one byte per pixel when displaying a frame. C. Scalability Since we have an effective frame rate of 30 frames per second, we have room to increase the output resolution of our design at the output without missing any frames. Effectively, we could double our frame resolution from 720x480 to 1440x960 by storing every pixel twice and repeating every line twice. Considering the possibility of having a video decoder running at double the operating frequency, we could potentially have an output of approximately 1024x680 at an effective rate of 30 frames per second. V. CONCLUSION We designed a system able to take an analog video signal as an input and then output it to VGA format using a NIOS driver, a Qsys system, a DMA and a display controller. After weeks of hard work, we were able to have the Grab interface write into SDRAM and successfully have the DMA read from it such that our display controller can display its contents on the screen. We were also able to implement a frame counter to showoff the processing capabilities of our developed system. We would like to thank Eric Boisvert and Franois Leduc- Primeau for taking time out of their busy schedule to assist us as we completed our project. Overall, this course was a very enriching experience, and helped refine our skills in FPGA design using CAD tools. 6 VI. APPENDIX A. Global Block diagram of the entire design 7 B. Frame shown with frame counter 8 C. ModelSim simulation of register file, grab interface and memory D. ModelSim simulation the memory storing a burst of data 9 E. Synthesis report summary F. Critical paths for the 27 MHz clock 10 G. Critical paths for the 100 MHz clock H. Reported maximum frequencies I. Processing Code 1) Snippet of the convolution code: . voi d e d g e d e t e c t i o n ( ) { f or ( i nt y = 0; y < h ; y++) { f or ( i nt x = 0; x < w; x++) { a l t u 1 6 edge x = 0 , edge y = 0 , gr adx = 0 , gr ady = 0 , y = 0; a l t u 8 r e s u l t = 0; f or ( i nt a = 0; a < Hei ght ; a ++) { f or ( i nt b = 0; b < Wi dth ; b++) { i nt c = ( x − Wi dth / 2 + b + wd) % wd ; i nt d = ( y − Hei ght / 2 + a + ht ) % ht ; edge x = ∗( s r c f r a me + 1440 ∗ imageY + 2 ∗ c ) ; / / c a l c u l a t i n g p i x e l addr e s s edge y = ∗( s r c f r a me + 1440 ∗ imageY + 2 ∗ d ) ; / / cb += i mage [ imageX ] [ i mageY ] . cb ∗ f i l t e r [ a ] [ b ] ; 11 / / cr += i mage [ imageX ] [ i mageY ] . cr ∗ f i l t e r [ a ] [ b ] ; edge x += edge x ∗ f i l t e r 1 [ a ] [ b ] ; gr ady += gr ady ∗ f i l t e r 2 [ a ] [ b ] ; y = gr adx +gr ady ; } } r e s u l t = min ( max ( f a c t o r ∗ y + bi as , 0) , 255) ; IOWR 8DIRECT(SDRAM CONTROLLER BASE, o f f s e t , r e s u l t ) ; IOWR 8DIRECT(SDRAM CONTROLLER BASE, o f f s e t +1 , 255) ; o f f s e t += 2; } IOWR 32DIRECT( REGFILE BASE, DMAFSTART, 691200) ; } ret urn n u l l ; } 2) Snippet of the write() function: . i f ( f i e l d numbe r == 1) { / / s e t t he pr oper v al ue s f o r programmi ng NIOS f o r t he s econd f i e l d wi t h i n f rame i f ( f r ame number == 1) { g f s t a r t t = g l p i t c h v a l / 2 ; } e l s e i f ( f r ame number == 2) { g f s t a r t t = ( l i ne nmbr + 1) ∗ g l p i t c h v a l / 2 ; } f i e l d numbe r = 0; IOWR 32DIRECT( REGFILE BASE, GFSTART, g f s t a r t t ) ; / / GINT: c l e a r t he i n t e r r u p t IOWR 32DIRECT( REGFILE BASE, GINT, c l r e o f i n t | e o f i n t e n ) ; IOWR 32DIRECT( REGFILE BASE, GCTRL, ( e n c ol or | gnef | en GSSHT) ) ; } e l s e { / / s e t t he pr oper v al ue s f o r programmi ng t he NIOS f o r t he s t a r t of anot he r f rame ! / / program t he DMA t o read f rom t he s t a b l e i mage t h a t has j u s t f i n i s h e d bei ng wr i t t e n i n t o memory / ∗ i f t he i nc r e me nt e d f rame number shows t h a t a t h i r d f rame woul d have t o be wr i t t e n t o memory ∗ t he n i t means t h a t we need t o go back t o 0 , i . e . s t a r t wr i t i n g at l o c a t i o n 0 i n memory agai n ∗/ i f ( f r ame number == 1) { g f s t a r t t = g l p i t c h v a l / 2 ∗ l i ne nmbr ; dma s t a r t a ddr = nul va l ; f r a me c ount ba s e a ddr = 4380 + 2 ∗ g l p i t c h v a l ; f r a me r a t e ba s e a ddr = 4380 + 10 ∗ g l p i t c h v a l ; 12 } i f ( f r ame number == 2) { g f s t a r t t = n u l v a l ; dma s t a r t a ddr = g l p i t c h v a l / 2 ∗ l i ne nmbr ; f r a me c ount ba s e a ddr = 4380 + 2 ∗ g l p i t c h v a l + g l p i t c h v a l / 2 ∗ l i ne nmbr ; f r a me r a t e ba s e a ddr = 4380 + 10 ∗ g l p i t c h v a l + g l p i t c h v a l / 2 ∗ l i ne nmbr ; } IOWR 32DIRECT( REGFILE BASE, GINT, c l r e o f i n t | e o f i n t e n ) ; IOWR 32DIRECT( REGFILE BASE, GFSTART, g f s t a r t t ) ; IOWR 32DIRECT( REGFILE BASE, GCTRL, ( e n c ol or | gnof | en GSSHT) ) ; i nt temp , temp2 ; i f ( d i s p l a y f r a me c o u n t e r == 1) { n r o f d i g i t s = g e t n u mb e r o f d i gi t s ( f r a me c ount e r ) ; f or ( i i = n r o f d i g i t s ; i i >= 1 ; i i −−) { temp = f r a me c ount ba s e a ddr + 30 ∗ ( n r o f d i g i t s − i i ) ; f or ( i = 0; i < 12; i ++) { f or ( j = 0; j < 12; j ++) { i f ( c ount da t a [ ( ( f r a me c ount e r % power ( 10 , i i ) ) / power ( 10 , i i −1) ) ∗144 + i ∗ 12 + j ] == 1) { IOWR 16DIRECT(SDRAM CONTROLLER BASE , temp+ 1440∗ i + 2∗ j , 60288) ; } } } } } IOWR 32DIRECT( REGFILE BASE, DMAFSTART, dma s t a r t a ddr ) ; f r ame number ++; f i e l d numbe r = 1; i f ( f r ame number == 3) { f r ame number = 1; } f r a me c ount e r ++; } 13 J. Constraint file: DE2 BaseProject.out.sdc ## Gener at ed SDC f i l e ” DE2 Bas ePr oj ect . out . s dc ” ## Copyr i ght ( C) 1991−2013 Al t e r a Cor por a t i on ## Your use of Al t e r a Cor por a t i on ’ s de s i gn t oo l s , l o g i c f u n c t i o n s ## and o t h e r s o f t wa r e and t o o l s , and i t s AMPP p a r t n e r l o g i c ## f u n c t i o n s , and any out put f i l e s from any of t he f o r e g o i n g ## ( i n c l u d i n g de vi c e programmi ng or s i mu l a t i o n f i l e s ) , and any ## a s s o c i a t e d document at i on or i n f o r ma t i o n a r e e x p r e s s l y s u b j e c t ## t o t he t er ms and c o n d i t i o n s of t he Al t e r a Program Li c e ns e ## Su b s c r i p t i o n Agreement , Al t e r a MegaCore Func t i on Li c e ns e ## Agreement , or o t h e r a p p l i c a b l e l i c e n s e agr eement , i nc l udi ng , ## wi t hout l i mi t a t i o n , t h a t your use i s f or t he s o l e pur pos e of ## programmi ng l o g i c d e v i c e s manuf act ur ed by Al t e r a and s ol d by ## Al t e r a or i t s a u t h o r i z e d d i s t r i b u t o r s . Pl e a s e r e f e r t o t he ## a p p l i c a b l e agr eement f or f u r t h e r d e t a i l s . ## VENDOR ” Al t e r a ” ## PROGRAM ” Quar t us I I ” ## VERSION ” Ver s i on 1 3 . 0 . 0 Bui l d 156 04/ 24/ 2013 SJ Fu l l Ver s i on ” ## DATE ” Tue Dec 03 16: 03: 52 2013 ” ## ## DEVICE ”EP2C35F672C6” ## #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ # Time I n f o r ma t i o n #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ s e t t i me f o r ma t −u n i t ns −de c i ma l pl a c e s 3 #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ # Cr e a t e Cl ock #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ c r e a t e c l o c k −name { a l t e r a r e s e r v e d t c k } −pe r i od 100. 000 −waveform { 0. 000 50. 000 } [ g e t p o r t s { a l t e r a r e s e r v e d t c k }] c r e a t e c l o c k −name { Cl ock 27 } −pe r i od 37. 037 −waveform { 0. 000 18. 518 } [ g e t p o r t s {CLOCK 27}] c r e a t e c l o c k −name {CLOCK 50} −pe r i od 20. 000 −waveform { 0. 000 10. 000 } [ g e t p o r t s {CLOCK 50}] #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ # Cr e a t e Gener at ed Cl ock #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ 14 c r e a t e g e n e r a t e d c l o c k −name { cl k100 } −s our c e [ g e t p o r t s {CLOCK 50}] −mul t i pl y by 2 −ma s t e r c l oc k {CLOCK 50} [ g e t n e t s { my p l l i n s t | a l t p l l c o mp o n e n t | cl k0 }] c r e a t e g e n e r a t e d c l o c k −name { c l k100 de l } −s our c e [ g e t p o r t s {CLOCK 50}] − mul t i pl y by 2 −o f f s e t −3.000 −ma s t e r c l oc k {CLOCK 50} [ g e t p i n s { my p l l i n s t | a l t p l l c o mp o n e n t | p l l | c l k [ 1 ] }] #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ # Set Cl ock Lat ency #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ # Set Cl ock Un c e r t a i n t y #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ # Set I nput Del ay #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ s e t i n p u t d e l a y −add del ay −max −c l oc k [ g e t c l o c k s { cl k100 }] 5. 400 [ g e t p o r t s { DRAM DQ[ 0 ] } ] s e t i n p u t d e l a y −add del ay −min −c l oc k [ g e t c l o c k s { cl k100 }] 1. 000 [ g e t p o r t s { DRAM DQ[ 0 ] } ] s e t i n p u t d e l a y −add del ay −max −c l oc k [ g e t c l o c k s { cl k100 }] 5. 400 [ g e t p o r t s { DRAM DQ[ 1 ] } ] s e t i n p u t d e l a y −add del ay −min −c l oc k [ g e t c l o c k s { cl k100 }] 1. 000 [ g e t p o r t s { DRAM DQ[ 1 ] } ] s e t i n p u t d e l a y −add del ay −max −c l oc k [ g e t c l o c k s { cl k100 }] 5. 400 [ g e t p o r t s { DRAM DQ[ 2 ] } ] s e t i n p u t d e l a y −add del ay −min −c l oc k [ g e t c l o c k s { cl k100 }] 1. 000 [ g e t p o r t s { DRAM DQ[ 2 ] } ] s e t i n p u t d e l a y −add del ay −max −c l oc k [ g e t c l o c k s { cl k100 }] 5. 400 [ g e t p o r t s { DRAM DQ[ 3 ] } ] s e t i n p u t d e l a y −add del ay −min −c l oc k [ g e t c l o c k s { cl k100 }] 1. 000 [ g e t p o r t s { DRAM DQ[ 3 ] } ] s e t i n p u t d e l a y −add del ay −max −c l oc k [ g e t c l o c k s { cl k100 }] 5. 400 [ g e t p o r t s { DRAM DQ[ 4 ] } ] s e t i n p u t d e l a y −add del ay −min −c l oc k [ g e t c l o c k s { cl k100 }] 1. 000 [ g e t p o r t s { DRAM DQ[ 4 ] } ] s e t i n p u t d e l a y −add del ay −max −c l oc k [ g e t c l o c k s { cl k100 }] 5. 400 [ g e t p o r t s { DRAM DQ[ 5 ] } ] s e t i n p u t d e l a y −add del ay −min −c l oc k [ g e t c l o c k s { cl k100 }] 1. 000 [ g e t p o r t s { DRAM DQ[ 5 ] } ] s e t i n p u t d e l a y −add del ay −max −c l oc k [ g e t c l o c k s { cl k100 }] 5. 400 [ g e t p o r t s { DRAM DQ[ 6 ] } ] s e t i n p u t d e l a y −add del ay −min −c l oc k [ g e t c l o c k s { cl k100 }] 1. 000 [ g e t p o r t s { DRAM DQ[ 6 ] } ] s e t i n p u t d e l a y −add del ay −max −c l oc k [ g e t c l o c k s { cl k100 }] 5. 400 [ g e t p o r t s { DRAM DQ[ 7 ] } ] 15 s e t i n p u t d e l a y −add del ay −min −c l oc k [ g e t c l o c k s { cl k100 }] 1. 000 [ g e t p o r t s { DRAM DQ[ 7 ] } ] s e t i n p u t d e l a y −add del ay −max −c l oc k [ g e t c l o c k s { cl k100 }] 5. 400 [ g e t p o r t s { DRAM DQ[ 8 ] } ] s e t i n p u t d e l a y −add del ay −min −c l oc k [ g e t c l o c k s { cl k100 }] 1. 000 [ g e t p o r t s { DRAM DQ[ 8 ] } ] s e t i n p u t d e l a y −add del ay −max −c l oc k [ g e t c l o c k s { cl k100 }] 5. 400 [ g e t p o r t s { DRAM DQ[ 9 ] } ] s e t i n p u t d e l a y −add del ay −min −c l oc k [ g e t c l o c k s { cl k100 }] 1. 000 [ g e t p o r t s { DRAM DQ[ 9 ] } ] s e t i n p u t d e l a y −add del ay −max −c l oc k [ g e t c l o c k s { cl k100 }] 5. 400 [ g e t p o r t s { DRAM DQ[ 1 0 ] } ] s e t i n p u t d e l a y −add del ay −min −c l oc k [ g e t c l o c k s { cl k100 }] 1. 000 [ g e t p o r t s { DRAM DQ[ 1 0 ] } ] s e t i n p u t d e l a y −add del ay −max −c l oc k [ g e t c l o c k s { cl k100 }] 5. 400 [ g e t p o r t s { DRAM DQ[ 1 1 ] } ] s e t i n p u t d e l a y −add del ay −min −c l oc k [ g e t c l o c k s { cl k100 }] 1. 000 [ g e t p o r t s { DRAM DQ[ 1 1 ] } ] s e t i n p u t d e l a y −add del ay −max −c l oc k [ g e t c l o c k s { cl k100 }] 5. 400 [ g e t p o r t s { DRAM DQ[ 1 2 ] } ] s e t i n p u t d e l a y −add del ay −min −c l oc k [ g e t c l o c k s { cl k100 }] 1. 000 [ g e t p o r t s { DRAM DQ[ 1 2 ] } ] s e t i n p u t d e l a y −add del ay −max −c l oc k [ g e t c l o c k s { cl k100 }] 5. 400 [ g e t p o r t s { DRAM DQ[ 1 3 ] } ] s e t i n p u t d e l a y −add del ay −min −c l oc k [ g e t c l o c k s { cl k100 }] 1. 000 [ g e t p o r t s { DRAM DQ[ 1 3 ] } ] s e t i n p u t d e l a y −add del ay −max −c l oc k [ g e t c l o c k s { cl k100 }] 5. 400 [ g e t p o r t s { DRAM DQ[ 1 4 ] } ] s e t i n p u t d e l a y −add del ay −min −c l oc k [ g e t c l o c k s { cl k100 }] 1. 000 [ g e t p o r t s { DRAM DQ[ 1 4 ] } ] s e t i n p u t d e l a y −add del ay −max −c l oc k [ g e t c l o c k s { cl k100 }] 5. 400 [ g e t p o r t s { DRAM DQ[ 1 5 ] } ] s e t i n p u t d e l a y −add del ay −min −c l oc k [ g e t c l o c k s { cl k100 }] 1. 000 [ g e t p o r t s { DRAM DQ[ 1 5 ] } ] #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ # Set Out put Del ay #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ # Set Cl ock Groups #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] 16 s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] s e t c l o c k g r o u p s −as ynchr onous −gr oup [ g e t c l o c k s { a l t e r a r e s e r v e d t c k }] #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ # Set Fa l s e Pat h #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ s e t f a l s e p a t h −from [ g e t c l o c k s { Cl ock 27 }] −t o [ g e t c l o c k s { cl k100 }] s e t f a l s e p a t h −from [ g e t c l o c k s { cl k100 }] −t o [ g e t c l o c k s { Cl ock 27 }] s e t f a l s e p a t h −t o [ g e t k e e p e r s {∗ a l t e r a s t d s y n c h r o n i z e r : ∗ | di n s 1 }] s e t f a l s e p a t h −from [ g e t r e g i s t e r s {myqsys : myqs ys i ns t | r e g f i l e : r e g f i l e | g f s t a r t r [ 1 ] myqsys : myqs ys i ns t | r e g f i l e : r e g f i l e | g f s t a r t r [ 2 ] myqsys : myqs ys i ns t | r e g f i l e : r e g f i l e | g f s t a r t r [ 3 ] myqsys : myqs ys i ns t | r e g f i l e : r e g f i l e | g f s t a r t r [ 4 ] myqsys : myqs ys i ns t | r e g f i l e : r e g f i l e | g f s t a r t r [ 5 ] myqsys : myqs ys i ns t | r e g f i l e : r e g f i l e | g f s t a r t r [ 6 ] myqsys : myqs ys i ns t | r e g f i l e : r e g f i l e | g f s t a r t r [ 7 ] myqsys : myqs ys i ns t | r e g f i l e : r e g f i l e | g f s t a r t r [ 8 ] myqsys : myqs ys i ns t | r e g f i l e : r e g f i l e | g f s t a r t r [ 9 ] myqsys : myqs ys i ns t | r e g f i l e : r e g f i l e | g f s t a r t r [ 10] myqsys : myqs ys i ns t | r e g f i l e : r e g f i l e | g f s t a r t r [ 11] myqsys : myqs ys i ns t | r e g f i l e : r e g f i l e | g f s t a r t r [ 12] myqsys : myqs ys i ns t | r e g f i l e : r e g f i l e | g f s t a r t r [ 13] myqsys : myqs ys i ns t | r e g f i l e : r e g f i l e | g f s t a r t r [ 14] myqsys : myqs ys i ns t | r e g f i l e : r e g f i l e | g f s t a r t r [ 15] myqsys : myqs ys i ns t | r e g f i l e : r e g f i l e | g f s t a r t r [ 16] myqsys : myqs ys i ns t | r e g f i l e : r e g f i l e | 17 g f s t a r t r [ 17] myqsys : myqs ys i ns t | r e g f i l e : r e g f i l e | g f s t a r t r [ 18] myqsys : myqs ys i ns t | r e g f i l e : r e g f i l e | g f s t a r t r [ 19] myqsys : myqs ys i ns t | r e g f i l e : r e g f i l e | g f s t a r t r [ 20] myqsys : myqs ys i ns t | r e g f i l e : r e g f i l e | g f s t a r t r [ 21] myqsys : myqs ys i ns t | r e g f i l e : r e g f i l e | g f s t a r t r [ 2 2 ] } ] s e t f a l s e p a t h −from [ g e t r e g i s t e r s {myqsys : myqs ys i ns t | r e g f i l e : r e g f i l e | gf mt r myqsys : myqs ys i ns t | r e g f i l e : r e g f i l e | gmode r [ 0 ] myqsys : myqs ys i ns t | r e g f i l e : r e g f i l e | gmode r [ 1 ] } ] s e t f a l s e p a t h −from [ g e t r e g i s t e r s {myqsys : myqs ys i ns t | g r a b i f : g r a b i f | g r a b r c o n t r o l : g r a b r c o n t r o l 1 | s t a t e . DONE myqsys : myqs ys i ns t | g r a b i f : g r a b i f | g r a b r c o n t r o l : g r a b r c o n t r o l 1 | s t a t e . WAITING myqsys : myqs ys i ns t | g r a b i f : g r a b i f | g s s h t f l a g }] s e t f a l s e p a t h −t o [ g e t p i n s −nocas e −c ompa t i bi l i t y mode {∗| a l t r s t s y n c u q 1 | a l t e r a r e s e t s y n c h r o n i z e r i n t c h a i n ∗| a c l r }] s e t f a l s e p a t h −from [ g e t k e e p e r s {∗ myqsys cpu : ∗ | myqs ys cpu ni os 2 oci : t he myqs ys cpu ni os 2 oci | myqs ys cpu ni os 2 oci br eak : t he myqs ys c pu ni os 2 oc i br e a k | br e a k r e a dr e g ∗}] −t o [ g e t k e e p e r s {∗ myqsys cpu : ∗ | myqs ys cpu ni os 2 oci : t he myqs ys cpu ni os 2 oci | myqs ys cpu j t ag debug modul e wr apper : t he myqs ys cpu j t ag debug modul e wr apper | myqs ys cpu j t ag debug modul e t ck : t he myqs ys cpu j t ag debug modul e t ck | ∗ s r ∗}] s e t f a l s e p a t h −from [ g e t k e e p e r s {∗ myqsys cpu : ∗ | myqs ys cpu ni os 2 oci : t he myqs ys cpu ni os 2 oci | myqs ys cpu ni os 2 oci debug : t he myqs ys cpu ni os 2 oci debug | ∗ r e s e t l a t c h }] −t o [ g e t k e e p e r s {∗ myqsys cpu : ∗ | myqs ys cpu ni os 2 oci : t he myqs ys cpu ni os 2 oci | myqs ys cpu j t ag debug modul e wr apper : t he myqs ys cpu j t ag debug modul e wr apper | myqs ys cpu j t ag debug modul e t ck : t he myqs ys cpu j t ag debug modul e t ck | ∗ s r [ 3 3 ] } ] s e t f a l s e p a t h −from [ g e t k e e p e r s {∗ myqsys cpu : ∗ | myqs ys cpu ni os 2 oci : t he myqs ys cpu ni os 2 oci | myqs ys cpu ni os 2 oci debug : t he myqs ys cpu ni os 2 oci debug | moni t or r e a dy }] −t o [ g e t k e e p e r s {∗ myqsys cpu : ∗ | myqs ys cpu ni os 2 oci : t he myqs ys cpu ni os 2 oci | myqs ys cpu j t ag debug modul e wr apper : t he myqs ys cpu j t ag debug modul e wr apper | myqs ys cpu j t ag debug modul e t ck : t he myqs ys cpu j t ag debug modul e t ck | ∗ s r [ 0 ] } ] s e t f a l s e p a t h −from [ g e t k e e p e r s {∗ myqsys cpu : ∗ | myqs ys cpu ni os 2 oci : t he myqs ys cpu ni os 2 oci | myqs ys cpu ni os 2 oci debug : t he myqs ys cpu ni os 2 oci debug | mo n i t o r e r r o r }] −t o [ g e t k e e p e r s {∗ myqsys cpu : ∗ | myqs ys cpu ni os 2 oci : t he myqs ys cpu ni os 2 oci | myqs ys cpu j t ag debug modul e wr apper : t he myqs ys cpu j t ag debug modul e wr apper | myqs ys cpu j t ag debug modul e t ck : t he myqs ys cpu j t ag debug modul e t ck | ∗ s r [ 3 4 ] } ] s e t f a l s e p a t h −from [ g e t k e e p e r s {∗ myqsys cpu : ∗ | myqs ys cpu ni os 2 oci : t he myqs ys cpu ni os 2 oci | myqsys cpu ni os2 oci mem : t he myqsys cpu ni os2 oci mem | ∗ MonDReg∗}] −t o [ g e t k e e p e r s {∗ myqsys cpu : ∗ | myqs ys cpu ni os 2 oci : t he myqs ys cpu ni os 2 oci | myqs ys cpu j t ag debug modul e wr apper : t he myqs ys cpu j t ag debug modul e wr apper | myqs ys cpu j t ag debug modul e t ck : t he myqs ys cpu j t ag debug modul e t ck | ∗ s r ∗}] s e t f a l s e p a t h −from [ g e t k e e p e r s {∗ myqsys cpu : ∗ | myqs ys cpu ni os 2 oci : t he myqs ys cpu ni os 2 oci | myqs ys cpu j t ag debug modul e wr apper : t he myqs ys cpu j t ag debug modul e wr apper | myqs ys cpu j t ag debug modul e t ck : t he myqs ys cpu j t ag debug modul e t ck | ∗ s r ∗}] −t o [ g e t k e e p e r s {∗ myqsys cpu : ∗ | myqs ys cpu ni os 2 oci : t he myqs ys cpu ni os 2 oci | myqs ys cpu j t ag debug modul e wr apper : t he myqs ys cpu j t ag debug modul e wr apper | myqs ys cpu j t ag debug modul e s ys cl k : t he myqs ys cpu j t ag debug modul e s ys cl k | ∗ j do ∗}] s e t f a l s e p a t h −from [ g e t k e e p e r s { s l d hub : ∗ | i r f r e g ∗}] −t o [ g e t k e e p e r s {∗ myqsys cpu : ∗ | myqs ys cpu ni os 2 oci : t he myqs ys cpu ni os 2 oci | myqs ys cpu j t ag debug modul e wr apper : t he myqs ys cpu j t ag debug modul e wr apper | 18 myqs ys cpu j t ag debug modul e s ys cl k : t he myqs ys cpu j t ag debug modul e s ys cl k | i r ∗}] s e t f a l s e p a t h −from [ g e t k e e p e r s { s l d hub : ∗ | sl d shadow j sm : shadow j sm | s t a t e [ 1 ] } ] − t o [ g e t k e e p e r s {∗ myqsys cpu : ∗ | myqs ys cpu ni os 2 oci : t he myqs ys cpu ni os 2 oci | myqs ys cpu ni os 2 oci debug : t he myqs ys cpu ni os 2 oci debug | moni t or go }] #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ # Set Mu l t i c y c l e Pat h #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ # Set Maximum Del ay #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ # Set Minimum Del ay #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ # Set I nput Tr a n s i t i o n #∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ ;