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SCHEME OF TEACHING AND EXAMINATIONB.E. ELECTRONICS & COMMUNICATION ENGINEERING (Common to EC/TC/ML) III SEMESTER Sl. No Subject Code 1 2 3 4 5 6 7 8 10MAT31 10ES32 10ES33 10ES34 10IT35 10ES36 10ESL37 10ESL38 Title Engg. Mathematics - III Analog Electronic Ckts Logic Design Network Analysis Electronic Instrumentation Field Theory Analog Electronics Lab Logic Design Lab TOTAL Teaching Dept. Teaching Hours /Week Theory Practical/ Drawing Mat @ @ @ @ @ @ @ 04 04 04 04 04 04 24 03 03 06 Examination Duration I.A. Marks 03 03 03 03 03 03 03 03 24 25 25 25 25 25 25 25 25 200 Theory/ Practical Marks 100 100 100 100 100 100 50 50 700 Total Marks Note : @ indicates concerned discipline. ES ( for theory) & ECL ( for Lab) in the subject code indicates that the subject is common to electrical and electronics stream consisting of EE/EC/IT/TC/ML/BM branches of engineering. 1 125 125 125 125 125 125 75 75 900 SCHEME OF TEACHING AND EXAMINATION B.E. ELECTRONICS & COMMUNICATION ENGINEERING (Common to EC/TC/ML) IV SEMESTER Sl. No Subject Code 1 2 3 4 5 6 7 8 10MAT 41 10ES 42 10ES43 10EC 44 10EC45 10EC46 10ESL47 10ECL48 Title Engg. Mathematics – IV Microcontrollers Control Systems Signals & Systems Fundamentals of HDL Linear ICs & Applications Microcontrollers Lab HDL Lab TOTAL Teaching Dept. Teaching Hours /Week Theory Mat @ @ @ @ @ @ @ Practical/ Drawing Duration I.A. Marks 03 03 06 03 03 03 03 03 03 03 03 24 25 25 25 25 25 25 25 25 200 04 04 04 04 04 04 24 Examination Theory/ Practical Marks 100 100 100 100 100 100 50 50 700 Total Marks Note : @ indicates concerned discipline. ES ( for theory) & ECL ( for Lab) in the subject code indicates that the subject is common to electrical and electronics stream consisting of EE/EC/IT/TC/ML/BM branches of engineering. 2 125 125 125 125 125 125 75 75 900 SCHEME OF TEACHING AND EXAMINATION B.E. ELECTRONICS & COMMUNICATION ENGINEERING (Common to EC/TC) V SEMESTER Sl. No 1 2 3 4 5 6 7 8 Subject Code 10AL51 10EC52 10EC53 10EC54 10EC55 10EC56 10ECL57 10ECL58 Title Management and Entrepreneurship Digital Signal Processing Analog Communication Microwaves and Radar Information Theory & Coding Fundamentals of CMOS VLSI DSP Lab Analog Communication Lab + LIC Lab TOTAL Teaching Dept. Teaching Hours /Week Examination Theory Practical/ Drawing Duration I.A. Marks Theory/ Practical Marks Total Marks @ 4 - 3 25 100 125 EC EC EC 4 4 4 - 3 3 3 25 25 25 100 100 100 125 125 125 EC 4 - 3 25 100 125 EC 4 - 3 25 100 125 EC - 3 3 25 50 75 EC - 3 3 25 50 75 24 06 24 200 700 900 @- Any Engineering department or department of Business study. 3 ELECTRONICS & COMMUNICATION ENGINEERING VI SEMESTER Sl. Marks - 25 25 25 25 25 25 Theory/ Practical Marks 100 100 100 100 100 100 Total Marks EC EC EC EC EC EC 4 4 4 4 4 4 - 3 3 3 3 3 3 EC - 3 3 25 50 75 EC 24 3 06 3 24 25 200 50 700 75 900 Elective – I (Group A) 10EC661 Analog and Mixed Mode VLSI Design 10EC662 Satellite Communications 10EC663 Random Process 10EC664 10EC665 10EC666 10EC667 4 Low Power VLSI Design Data Structure Using C++ Digital System Design Using Verilog Virtual Instrumentation 125 125 125 125 125 125 .A. No Subject Code 1 2 3 4 5 6 7 10EC61 10EC62 10EC63 10EC64 10EC65 10EC66x 8 10ECL68 10ECL67 Title Digital Communication Microprocessors Microelectronics Circuits Antennas and Propagation Operating Systems Elective-I (Group A) Advanced Communication Lab Microprocessor Lab TOTAL Teaching Dept.E.SCHEME OF TEACHING AND EXAMINATION B. Teaching Hours /Week Theory Examination Practical/ Drawing Duration I. Marks Theory/ Practical Marks Total Marks EC 4 - 3 25 100 125 EC EC EC EC EC EC EC 4 4 4 4 4 24 3 3 06 3 3 3 3 3 3 3 24 25 25 25 25 25 25 25 200 100 100 100 100 100 50 50 700 125 125 125 125 125 75 75 900 Elective – III (Group C) 10EC761 Programming in C++ 10EC762 Real Time Systems 10EC763 Image Processing 10EC764 Radio Frequency Integrated Circuits 10EC765 Wavelet Transforms 10EC766 Modeling and Simulation of Data Networks NOTE: * 06EC755 Applied Embedded System Design has a LAB component (syllabus is different and in the Theory Examination.SCHEME OF TEACHING AND EXAMINATION B. questions from Lab experiments will also be there.A. No 1 2 3 4 5 6 7 8 Subject Code 10EC71 10EC72 10EC73 10EC74 10EC75x 10EC76x 10ECL77 10ECL78 Title Teaching Dept. Computer Communication Networks Optical Fiber Communication Power Electronics Embedded System Design Elective-II (Group B) Elective-III (Group C) VLSI Lab Power Electronics Lab TOTAL Elective – II (Group B) 10EC751 DSP Algorithms & Architecture 10EC752 Micro and Smart Systems Technology 10EC753 Artificial Neural Network 10EC754 CAD for VLSI 10EC755 Applied Embedded System Design* 10EC756 Speech Processing Teaching Hours /Week Theory Practical/ Drawing Examination Duration I. ) 5 .E. ELECTRONICS & COMMUNICATION ENGINEERING VII SEMESTER Sl. Wireless Communication Digital Switching Systems Elective-IV (Group D) Elective-V (Group E) Project Work Seminar TOTAL Teaching Hours /Week Examination Theory Practical/ Drawing Duration I.SCHEME OF TEACHING AND EXAMINATION B.A.E. No 1 2 3 4 5 6 Subject Code 10EC81 10EC82 10EC83x 10EC84x 10ECP85 10ECS86 Title Teaching Dept. Marks 4 4 4 4 16 6 3 09 3 3 3 3 3 15 25 25 25 25 100 50 250 EC EC EC EC EC EC Elective – IV (Group D) 10EC831 Distributed Systems 10EC832 Network Security 10EC833 Optical Networks 10EC834 High Performance Computing Networks 10EC835 Internet Engineering Theory/ Practical Marks 100 100 100 100 100 500 Elective – V (Group E) 10EE841 Multimedia Communication 10EC842 Real Time Operating Systems 10EC843 GSM 10EC844 Ad-hoc Wireless Networks 10EC845 Optical Computing 6 Total Marks 125 125 125 125 200 50 750 . ELECTRONICS & COMMUNICATION ENGINEERING VIII SEMESTER Sl. 7 Hours PART-B UNIT-5 Numerical Methods . Iterative methods of solution of a system 7 . 7 Hours UNIT-2 Fourier Transforms Infinite Fourier transform.Fitting of curves of the form y = ax + b. : : : 10MAT31 04 52 IA Marks Exam Hours Exam Marks : : : 25 03 100 PART-A UNIT-1 Fourier series Convergence and divergence of infinite series of positive terms. y = a x 2 + b x + c. 6 Hours UNIT-4 Curve Fitting and Optimisation Curve fitting by the method of least squares. y = ae bx . D’Alembert’s solution of one dimensional wave equation.Raphson method.1 Numerical Solution of algebraic and transcendental equations: Regula-falsi method. Complex form of Fourier Series. half range Fourier series. Graphical method and simplex method. mathematical formulation of linear programming problem (LPP). Solution of all these equations with specified boundary conditions. Newton .III SEMESTER ENGINEERING MATHEMATICS – III Sub Code Hrs/ Week Total Hrs. properties. Fourier series of periodic functions of period and arbitrary period. definition and illustrative examples* Periodic functions. Inverse transforms 6 Hours UNIT-3 Application of PDE Various possible solutions of one dimensional wave and heat equations. Fourier Sine and Cosine transforms. Dirichlet’s conditions. two dimensional Laplace’s equation by the method of separation of variables. y = ax b Optimization: Linear programming. Practical harmonic analysis. Lagrange’s interpolation formula and inverse interpolation formula. Latest edition. three-eighth and Weddle’s rules (All formulae/rules without proof) 7 Hours UNIT-7 Numerical Methods – 3 Numerical solutions of PDE – finite difference approximation to derivatives. 6 Hours UNIT-6 Numerical Methods – 2 Finite differences: Forward and backward differences. shifting rule. Newton’s forward and backward interpolation formulae.Newton’s divided difference formula. Numerical solution of two dimensional Laplace’s equation.V. Z-transforms – definition. REFERENCE BOOKS: 1.S. Wiley Publications. Numerical integration: Simpson’s one-third. Advanced Engineering Mathematics. 2. damping rule. Tata Mc. Application of Z-transforms to solve difference equations.of equations: Gauss-seidel and Relaxation methods. B. Grewal. Divided differences . Latest edition. Engineering Mathematics. Erwin Kreyszig. questions are not to be set. 6 Hours Note: * In the case of illustrative examples. Higher Engineering Mathematics. 2. Peter V.Publishers. Graw Hill Publications. one dimensional heat and wave equations 7 Hours UNIT-8 Difference Equations and Z-Transorms Difference equations: Basic definition. Higher Engineering Mathematics. Latest edition. Largest eigen value and the corresponding eigen vector by Rayleigh’s power method. standard Ztransforms. Ramana. TEXT BOOKS: 1. CENGAGE Learning India Pvt Ltd. initial value and final value theorems. Khanna Publishers. B. O’Neil. Inverse Z-transform. 8 . Miscellaneous bias configurations. 7 Hours PART – B UNIT 5: (a) General Amplifiers: Cascade connections. Transistor switching networks. Reverse recovery time. 3 Hours (b) Feedback Amplifier: Feedback concept. analysis of CE configuration using h. Voltage divider bias. Analysis of circuits re model. Voltage divider biased. Transition and diffusion capacitance. Practical feedback circuits. CB configuration.CC and CE configuration. Bias stabilization. Relationship between hparameter model of CE. Load line analysis. 4 Hours 9 . CE Fixed bias configuration. PNP transistors. Collector feedback configuration. Emitter follower.ANALOG ELECTRONIC CIRCUITS (Common to EC/TC/EE/IT/BM/ML) Sub Code Hrs/ Week Total Hrs. : : : 10ES32 04 52 IA Marks Exam Hours Exam Marks : : : 25 03 100 PART – A UNIT 1: Diode Circuits: Diode Resistance. Cascode connections. 6 Hours UNIT 3: Transistor at Low Frequencies: BJT transistor modeling. Darlington connections. Diode equivalent circuits. Design procedures for the feedback amplifiers. Emitter stabilized biased circuits. Design operations. multistage frequency effects. Miller effect capacitance. Clippers and clampers. High frequency response. low frequency response. Feedback connections type. 6 Hours UNIT 2: Transistor Biasing: Operating point.parameter model. Rectifiers. DC bias with voltage feedback. 7 Hours UNIT 4: Transistor Frequency Response: General frequency considerations. Fixed bias circuits. PHI/Pearson Eduication. “Electronic Devices and Circuits”. 2007. Canonical forms. ‘Integrated Electronics’. 9TH Edition. FET amplifier networks.B. REFERENCE BOOKS: 1. series fed class A amplifier. Wienbridge Oscillator. : : : 10ES33 04 52 IA Marks Exam Hours Exam Marks : : : 25 03 100 PART – A UNIT 1: Principles of combinational logic-1: Definition of combinational logic. 4th Edition. Pearson/Saguine. MOSFETs. Amplifier distortions. Phase shift Oscillator. Jacob Millman & Christos C. Boylestad and Louis Nashelsky.UNIT 6: Power Amplifiers: Definitions and amplifier types. Transformer coupled Class A amplifiers. Mahadevaswamy. (BJT Version Only) Simple design methods of Oscillators. 10 . Common drain common gate configurations. 7 Hours UNIT 7: Oscillators: Oscillator operation. Biasing of FET. Tata . 2nd Edition. David A. PHI.McGraw Hill. Class B amplifier circuits. 2004 3. Tuned Oscillator circuits. Designing of Power amplifiers. Crystal Oscillator. Robert L. 6 Hours UNIT 8: FET Amplifiers: FET small signal model. “Analog Electronics Circuits: A Simplified Approach”. Bell. Generation of switching equations from truth tables. “Electronic Devices and Circuit Theory”. 2010 2. Halkias. LOGIC DESIGN (Common to EC/TC/EE/IT/BM/ML) Sub Code Hrs/ Week Total Hrs. 6 Hours TEXT BOOK: 1. Class B amplifier operations. U. 7 Hours UNIT 6: Sequential Circuits – 2: Characteristic Equations. 6 Hours UNIT 2: Principles of combinational Logic-2: Quine-McCluskey minimization technique. The Master-Slave JK FlipFlop. The gated D Latch. Counters based on Shift Registers. Mealy and Moore Models. SR Latch. The Master-Slave Flip-Flops (Pulse-Triggered Flip-Flops): The Master-Slave SR Flip-Flops. Application of SR Latch. Negative-Edge Triggered D Flip-Flop. 4 and 5 variables. Simplifying Max term equations. The gated SR Latch. 7 Hours UNIT 3: Analysis and design of combinational logic . 7 Hours PART – B UNIT 5: Sequential Circuits – 1: Basic Bistable Element. Design of a Synchronous Mod-6 Counter using clocked JK Flip-Flops Design of a Synchronous Mod-6 Counter using clocked D. Design of a Synchronous counters.I: Introduction. 6 Hours UNIT 4: Analysis and design of combinational logic . Counters Binary Ripple Counters. or SR Flip-Flops 7 Hours UNIT 7: Sequential Design . Adders and subtractorsCascading full adders. Incompletely specified functions (Don’t Care terms). 6 Hours 11 . A Switch Debouncer. Design methods of building blocks of combinational logics. Latches. Edge Triggered Flip-Flop: The Positive Edge-Triggered D Flip-Flop. Binary comparators. Synchronous Sequential Circuit Analysis and Design. Encoders.II: Digital multiplexersUsing multiplexers as Boolean function generators. Map entered variables.Quine-McCluskey using don’t care terms. State Machine Notation. Reduced Prime Implicant Tables. Registers. Synchronous Binary counters. The S R Latch. Look ahead carry. T.I: General approach.Karnaugh maps-3. Decoders-BCD decoders. Concepts of super node and super mesh. 3. Source transformations. Pearson/Saguine.II: Construction of state Diagrams. Mono and Kim. Principle of duality. 2. Network reduction using Star – Delta transformation. Charles H Roth. Second edition. 2004. “Fundamentals of logic design”. Formulation of equilibrium equations in matrix form. 2007 NETWORK ANALYSIS (Common to EC/TC/EE/IT/BM/ML) Sub Code Hrs/ Week Total Hrs. REFERENCE BOOKS: 1. Sudhakar Samuel. : : : 10ES34 04 52 IA Marks Exam Hours Exam Marks : : : 25 03 100 PART – A UNIT 1: Basic Concepts: Practical sources. Thomson Learning. John M Yarbrough. Pearson. Jr. tie-set. tie-set and cut-set schedules.UNIT 8: Sequential Design . 7 Hours UNIT 3: Network Theorems – 1: Superposition. Concept of tree and co-tree. Counter Design. 2001. Solution of resistive networks. 2. Thomson Learning. 6 Hours 12 . 7 Hours UNIT 2: Network Topology: Graph of a network. incidence matrix. “Logic Design”. “Digital Logic Applications and Design”. 2002. Loop and node analysis With linearly dependent and independent sources for DC and AC networks. 2001. 6 Hours TEXT BOOKS: 1. “Digital Principles and Design “. “Logic and computer design Fundamentals”. Donald D Givone. Reciprocity and Millman’s theorems. Tata McGraw Hill Edition. 2nd edition. Roy Choudhury. Mark Nelms. “Basic Engineering Circuit Analysis”. New Age International Publications. relationship between parameters sets. 6 Hours TEXT BOOKS: 1. 2. y. 3. 6 Hours PART – B UNIT 5: Resonant Circuits: Series and parallel resonance. 3rd Edition. REFERENCE BOOKS: 1. 2006 re-print. Hayt. 8th ed.UNIT 4: Network Theorems . J. h and transmission parameters. 6 Hours UNIT 8: Two port network parameters: Definition of z. step. Q –factor. “Networks and systems”. Kemmerly and DurbinTMH 7th Edition. Van Valkenburg. PHI / Pearson Education. 3 ed. M. waveform Synthesis. 2010 2. Maximum Power transfer theorem . frequencyresponse of series and Parallel circuits. 2006.“ Fundamentals of Electric Circuits”. David Irwin / R. 7 Hours UNIT 7: Laplace Transformation & Applications : Solution of networks.II: Thevinin’s and Norton’s theorems. ramp and impulse responses. 2009. modeling with these parameters. E. Charles K Alexander and Mathew N O Sadiku. RC and RLC circuits for AC and DC excitations. “Engineering Circuit Analysis”. evaluation of initial and final conditions in RL. Bandwidth. “Network Analysis”. John Wiley. 13 . 3. Reprint 2002. Tata McGraw-Hill. 7 Hours UNIT 6: Transient behavior and initial conditions: Behavior of circuit elements under switching condition and their Representation. 14 . AC voltmeter using Rectifiers – Half wave and full wave. Absolute and relative errors. CRT features. Digital Multi-meters. Digital frequency meters. 6 Hours PART – B UNIT – 5: Signal Generators Introduction. Multirange voltmeter. Standard signal generator. : : : 10IT35 04 52 IA Marks Exam Hours Exam Marks : : : 25 03 100 PART – A UNIT – 1: Introduction (a) Measurement Errors: Gross errors and systematic errors. Peak responding and True RMS voltmeters. Loading. General specifications. Precision. Analog storage. Typical CRT connections. Sampling and Digital storage oscilloscopes. Resolution and Significant figures. 6 Hours UNIT – 4: Special Oscilloscopes Delayed time-base oscilloscopes. Dual beam and dual trace CROs. Digital measurement of time. Block diagram and working of each block. Fixed and variable AF oscillator. Electronic switch. V – F and Successive approximation principles. (b) Voltmeters and Multimeters Introduction. 6 Hours UNIT – 3: Oscilloscopes Introduction. Basic principles. Resolution and sensitivity. DVM’s based on V – T. Accuracy. AF sine and Square wave generator. 3 + 4 Hours UNIT – 2: Digital Instruments Digital Voltmeters – Introduction. Laboratory type signal generator. Extending voltmeter ranges.ELECTRONIC INSTRUMENTATION (Common to EC/TC/IT/BM/ML) Sub Code Hrs/ Week Total Hrs. TMH. (c) Bolometer and RF power measurement using Bolometer (d) Introduction to Signal conditioning. Beately. 2. Differential output transducers and LVDT. Square and Pulse generator. Cooper D & A D Helfrick. Maxwell’s bridge. . LEDs. Selecting a transducer. Electronics & electrical measurements. Photoelectric transducer. PHI / Pearson Education. Resistive position transducer. Pearson Education.I Introduction. Wein’s bridge. Kalsi. 10 Hours TEXT BOOKS: 1. David A Bell.II –Piezoelectric transducer. inductance and capacitance Whetstone’s bridge. Thermistor. (b) Display devices: Digital display system. “Modern electronic instrumentation and measuring techniques”. Kelvin Bridge. 6 Hours UNIT – 8: Miscellaneous Topics (a) Transducers . AC bridges. “Electronic Instrumentation”. 3. 15 .Function generator. Resistive transducer. Display devices. Semiconductor photo devices. Photovoltaic transducer. Inductive transducer. REFERENCE BOOKS: 1. A K Sawhney. Frequency synthesizer. Dhanpat Rai & sons. Sweep frequency generator. PHI. Temperature transducers-RTD. Capacitance Comparison Bridge. classification of display. Electrical transducers. 3rd Edition. 3rd 2010. 9th edition. “Principles of measurement systems”. S. 6 Hours UNIT – 6: Measurement of resistance. LCD displays. Strain gauges. H. “Electronic Instrumentation and Measurements”. 2006. Resistance thermometer. 2000 2. 1998. John P. Thermocouple . (e) Introduction to LabView. Wagner’s earth connection 5 Hours UNIT – 7: Transducers . Electric field intensity. Maxwell’s First equation(Electrostatics). Examples of the solutions of Laplace’s and Poisson’s equations. Ampere’s circuital law. 6 Hours 16 . Energy density in an electrostatic field. Gauss’ law.FIELD THEORY (Common to EC/TC/ML/EE) Sub Code Hrs/ Week Total Hrs. Field due to continuous volume charge distribution. Conductors. 3 Hours UNIT 2: a. Electric flux density. Definition of potential difference and Potential. Coulomb’s Law and electric field intensity: Experimental law of Coulomb. Divergence. Continuity of current. dielectrics and capacitance: Current and current density. scalar and Vector magnetic potentials. Energy and potential : Energy expended in moving a point charge in an electric field. The line integral. : : : 10ES36 04 52 IA Marks Exam Hours Exam Marks : : : 25 03 100 PART – A UNIT 1: a. 4 Hours UNIT 3: Poisson’s and Laplace’s equations: Derivations of Poisson’s and Laplace’s Equations. magnetic flux and flux density. metallic conductors. The potential field of a point charge and system of charges. boundary conditions for perfect Dielectrics. Curl. Field of a line charge. 6 Hours UNIT 4: The steady magnetic field: Biot-Savart law. 3 Hours b. Uniqueness theorem. capacitance and examples. Conductor properties and boundary conditions. 4 Hours b. Potential gradient . Stokes’ theorem. vector operator ∇ and divergence theorem. Gauss’ law and divergence: Electric flux density. displacement current. retarded potentials. 4 Hours UNIT 6: Time varying fields and Maxwell’s equations: Faraday’s law. 17 . Force and torque on a closed circuit. McGraw-Hill. 1999. 3. Magnetic boundary conditions. John Krauss and Daniel A Fleisch. Pearson Education Asia. Maxwell’s equation in point and Integral form. 2nd edition. Prentice – Hall of India / Pearson Education. “Engineering Electromagnetics”. Indian Reprint – 2001. 5th edition. Inductance and Mutual Inductance. Tata McGraw-Hill. and John A Buck.” Edward C. Magnetic materials and inductance: Magnetization and permeability. Poynting’s theorem and wave power. 6 Hours UNIT 8: Plane waves at boundaries and in dispersive media: Reflection of uniform plane waves at normal incidence. David K Cheng.Reprint 2002. 6 Hours TEXT BOOK: 1. “Electromagnetics with Applications”. propagation in good conductors – (skin effect). 4 Hours b. SWR. Jordan and Keith G Balmain. 6 Hours UNIT 7: Uniform plane wave: Wave propagation in free space and dielectrics. REFERENCE BOOKS: 1. 2006. Potential energy and forces on magnetic materials. “Electromagnetic Waves And Radiating Systems.PART – B UNIT 5: a. 7th edition. “Field and Wave Electromagnetics”. Magnetic circuit.1989. Magnetic forces: Force on a moving charge and differential current element. 2nd edition. William H Hayt Jr. Force between differential current elements. 1968. 2. . Plane wave propagation in general directions. 1. Characteristics of Series and Parallel resonant circuits. input and output impedances. input and output impedances with and without feedback (One Experiment) 4. Wiring of a two stage BJT Voltage series feed back amplifier and determination of the gain. 10. Wiring of RC coupled Single stage FET & BJT amplifier and determination of the gain-frequency response. for 6. 9. Testing of Clamping circuits: positive clamping /negative clamping. Frequency response. Testing of Half wave. Testing for the performance of BJT – Hartley & Colpitts Oscillators RF range f0 ≥100KHz. input and output impedances (Single circuit) (One Experiment) 3. Wiring of BJT Darlington Emitter follower with and without bootstrapping and determination of the gain. LabView can be used for the verification and testing along with the above. : : : 10ESL37 03 42 IA Marks Exam Hours Exam Marks : : : 25 03 50 NOTE: Use the Discrete components to test the circuits. Wiring and Testing for the performance of BJT-RC Phase shift Oscillator for f0 ≤ 10 KHz 5. Testing for the performance of BJT -Crystal Oscillator for f0 > 100 KHz 7 Testing of Diode clipping (Single/Double ended) circuits for peak clipping. 12. 2. regulation and efficiency 11. Determination of ripple factor. Testing of a transformer less Class – B push pull power amplifier and determination of its conversion efficiency. Full wave and Bridge Rectifier circuits with and without Capacitor filter. peak detection 8. Verification of Thevinin’s Theorem and Maximum Power Transfer theorem for DC Circuits.ANALOG ELECTRONICS LAB (Common to EC/TC/EE/IT/BM/ML) Sub Code Hrs/ Week Total Hrs. 18 . 6. realization of Boolean expressions using logic gates/Universal gates. 1. 3. Shift right. Shift left. Realization of One/Two bit comparator and study of 7485 magnitude comparator. Realization of Half/Full adder and Half/Full Subtractors using logic gates. SIPO. PISO. Realization of 3 bit counters as a sequential circuit and MOD – N counter design (7476. : : : 10ESL38 03 42 IA Marks Exam Hours Exam Marks : : : 25 03 50 NOTE: Use discrete components to test and verify the logic gates. 8.LOGIC DESIGN LAB (Common to EC/TC/EE/IT/BM/ML) Sub Code Hrs/ Week Total Hrs. Simplification. PIPO operations using 74S95. 12. SISO. 2. Use of a) Decoder chip to drive LED display and b) Priority encoder. Wiring and testing Ring counter/Johnson counter. Wiring and testing of Sequence generator. 74139 for arithmetic circuits and code converter. MUX/DEMUX – use of 74153. Realization of Binary to Gray code conversion and vice versa 5. 9. 4. 74192. 74193). (i) Realization of parallel adder/Subtractors using 7483 chip (ii) BCD to Excess-3 code conversion and vice versa. 11. 10. 7490. 19 . 7. LabView can be used for designing the gates along with the above. Truth table verification of Flip-Flops: (i) JK Master slave (ii) T type and (iii) D type. Correlation and Regression. W = ez. Rodirgue’s formula. Properties of analytic functions. Cauchy’s integral formula. UNIT 2: Complex Variables Function of a complex variable. UNIT 4: Series solution of Ordinary Differential Equations and Special Functions Series solution – Frobenius method.IV SEMESTER ENGINEERING MATHEMATICS . Equations reducible to Bessel’s D. Discussion of transformations: W = z2. UNIT 3: Complex Integration Complex line integrals. z ≠ 0 Bilinear transformations. y = axb y = abx. Conformal Transformation – Definition. leading to Bessel function of fist kind. Series solution of Bessel’s D.E. Cauchy’s residue theorem (statement only). Continuity Differentiability – Definitions. Taylor’s and Laurent’s series (Statements only) Singularities.IV Sub Code Hrs/ Week Total Hrs. leading to Legendre Polynomials. Poles. Cauchy – Riemann equations in cartesian and polar forms. 20 . PART – B UNIT 5: Statistical Methods Curve fitting by the method of least squares: y = a + bx. y = aebx. Cauchy’s theorem. Residues. Limit. Runge – Kutta method of fourth order. : : : 10MAT41 04 52 IA Marks Exam Hours Exam Marks : : : 25 03 100 PART – A UNIT 1: Numerical Methods Numerical solutions of first order and first degree ordinary differential equations – Taylor’s series method. Analytic functions.E. Series solution of Legendre’s D.E. Milne’s and Adams-Bashforth predictor and corrector methods (All formulae without Proof). W = z + (I/z). Modified Euler’s method. y = a + bx + cx2.. REFERENCE BOOKS: 1. Regular stochastic matrices.d. Probability by Seymour Lipschutz (Schaum’s series). UNIT 7: Sampling. B.Probability: Addition rule.d. Binomial. UNIT 6: Random Variables (Discrete and Continuous) p. Correlation coefficient. Discrete and Independent random variables. Covariance. Sampling distribution.f. Chi-square distribution as a test of goodness of fit. Higher Engineering Mathematics by Dr. Normal and Exponential distributions. UNIT 8: Concept of joint probability – Joint probability distribution. Poisson.f. 36th Edn. Conditional probability. 21 . Ramana (Tata-Macgraw Hill). c. Stochastic matrices. Advanced Modern Engineering Mathematics by Glyn James – Pearson Education. 2. TEXT BOOK: 1. Multiplication rule.S.V. Probability vectors. Higher transition probabilities. Expectation. Confidence limits for means. Standard error. Student’s t distribution. Baye’s theorem. Grewal. Fixed points.. Testing of hypothesis for means. Kanna Publications. Markov chains. Higher Engineering Mathematics by B. Stationary distribution of regular Markov chains and absorbing states. 2. MICROCONTROLLERS (Common to EC/TC/EE/IT/BM/ML) Sub Code Hrs/ Week Total Hrs. : : : 10ES42 04 52 IA Marks Exam Hours Exam Marks : : : 25 03 100 PART – A UNIT 1: Microprocessors and microcontroller. Introduction, Microprocessors and Microcontrollers, RISC & CISC CPU Architectures, Harvard & VonNeumann CPU architecture, Computer software. The 8051 Architecture: Introduction, Architecture of 8051, Pin diagram of 8051, Memory organization, External Memory interfacing, Stacks. 6 Hours UNIT 2: Addressing Modes: Introduction, Instruction syntax, Data types, Subroutines, Addressing modes: Immediate addressing , Register addressing, Direct addressing, Indirect addressing, relative addressing, Absolute addressing, Long addressing, Indexed addressing, Bit inherent addressing, bit direct addressing. Instruction set: Instruction timings, 8051 instructions: Data transfer instructions, Arithmetic instructions, Logical instructions, Branch instructions, Subroutine instructions, Bit manipulation instruction. 6 Hours UNIT 3: 8051 programming: Assembler directives, Assembly language programs and Time delay calculations. 6 Hours UNIT 4: 8051 Interfacing and Applications: Basics of I/O concepts, I/O Port Operation, Interfacing 8051 to LCD, Keyboard, parallel and serial ADC, DAC, Stepper motor interfacing and DC motor interfacing and programming 7 Hours PART – B UNIT 5: 8051 Interrupts and Timers/counters: Basics of interrupts, 8051 interrupt structure, Timers and Counters, 8051 timers/counters, programming 8051 timers in assembly and C . 6 Hours 22 UNIT 6: 8051 Serial Communication: Data communication, Basics of Serial Data Communication, 8051 Serial Communication, connections to RS-232, Serial communication Programming in assembly and C. 8255A Programmable Peripheral Interface:, Architecture of 8255A, I/O addressing,, I/O devices interfacing with 8051 using 8255A. 6 Hours Course Aim – The MSP430 microcontroller is ideally suited for development of low-power embedded systems that must run on batteries for many years. There are also applications where MSP430 microcontroller must operate on energy harvested from the environment. This is possible due to the ultra-low power operation of MSP430 and the fact that it provides a complete system solution including a RISC CPU, flash memory, on-chip data converters and on-chip peripherals. UNIT 7: Motivation for MSP430microcontrollers – Low Power embedded systems, On-chip peripherals (analog and digital), low-power RF capabilities. Target applications (Single-chip, low cost, low power, high performance system design). 2 Hours MSP430 RISC CPU architecture, Compiler-friendly features, Instruction set, Clock system, Memory subsystem. Key differentiating factors between different MSP430 families. 2 Hours Introduction to Code Composer Studio (CCS v4). Understanding how to use CCS for Assembly, C, Assembly+C projects for MSP430 microcontrollers. Interrupt programming. 3 Hours Digital I/O – I/O ports programming using C and assembly, Understanding the muxing scheme of the MSP430 pins. 2 Hours UNIT 8: On-chip peripherals. Watchdog Timer, Comparator, Op-Amp, Basic Timer, Real Time Clock (RTC), ADC, DAC, SD16, LCD, DMA. 2 Hours Using the Low-power features of MSP430. Clock system, low-power modes, Clock request feature, Low-power programming and Interrupt. 2 Hours 23 Interfacing LED, LCD, External memory. Seven segment LED modules interfacing. Example – Real-time clock. 2 Hours Case Studies of applications of MSP430 - Data acquisition system, Wired Sensor network, Wireless sensor network with Chipcon RF interfaces. 3 Hours TEXT BOOKS: 1. “The 8051 Microcontroller and Embedded Systems – using assembly and C ”-, Muhammad Ali Mazidi and Janice Gillespie Mazidi and Rollin D. McKinlay; PHI, 2006 / Pearson, 2006 2. “MSP430 Microcontroller Basics”, John Davies, Elsevier, 2010 (Indian edition available) REFERENCE BOOKS: 1. “The 8051 Microcontroller Architecture, Programming & Applications”, 2e Kenneth J. Ayala ;, Penram International, 1996 / Thomson Learning 2005. 2. “The 8051 Microcontroller”, V.Udayashankar and MalikarjunaSwamy, TMH, 2009 3. MSP430 Teaching CD-ROM, Texas Instruments, 2008 (can be requested http://www.uniti.in ) 4. Microcontrollers: Architecture, Programming, Interfacing and System Design”,Raj Kamal, “Pearson Education, 2005 CONTROL SYSTEMS (Common to EC/TC/EE/IT/BM/ML) Sub Code Hrs/ Week Total Hrs. : : : 10ES43 04 52 IA Marks Exam Hours Exam Marks : : : 25 03 100 PART – A UNIT 1: Modeling of Systems: Introduction to Control Systems, Types of Control Systems, Effect of Feedback Systems, Differential equation of Physical Systems -Mechanical systems, Friction, Translational systems (Mechanical accelerometer, systems excluded), Rotational systems, Gear trains, Electrical systems, Analogous systems. 7 Hours UNIT 2: Block diagrams and signal flow graphs: Transfer functions, Block diagram algebra, Signal Flow graphs (State variable formulation excluded), 6 Hours 24 Nyquist Stability criterion. Experimental determination of transfer functions. Relative stability analysis. 6 Hours UNIT 6: Frequency domain analysis: Correlation between time and frequency response. 25 . Time response specifications of second order systems. REFERENCE BOOKS: 1. (Systems with transportation lag excluded).Gopal. Assessment of relative stability using Nyquist criterion.UNIT 3: Time Response of feed back control systems: Standard test signals. 2002. 7 Hours UNIT 7: Stability in the frequency domain: Introduction to Polar Plots. 7 Hours UNIT 8: Introduction to State variable analysis: Concepts of state. Introduction to lead. state variable and state models for electrical systems. The root locus concepts. “Control Systems Engineering”. Nagarath and M. Assessment of relative stability using Bode Plots. New Age International (P) Limited. K. Fourth edition – 2005. 4th Edition. “Modern Control Engineering “. steady – state errors and error constants. Pearson Education Asia/ PHI. Routh. 6 Hours PART – B UNIT 5: Root–Locus Techniques: Construction of root loci. Necessary conditions for Stability.stability criterion. Solution of state equations. Publishers. More on the Routh stability criterion. Time response specifications. Unit step response of First and second order systems. lag and lead-lag compensating networks (excluding design). J. Introduction to PID Controllers(excluding design) 7 Hours UNIT 4: Stability analysis: Concepts of stability. 6 Hours TEXT BOOK : 1. (Inverse Polar Plots excluded) Mathematical preliminaries. Introduction. Bode plots. Ogata. : : : 10EC44 04 52 IA Marks Exam Hours Exam Marks : : : 25 03 100 PART – A UNIT 1: Introduction: Definitions of a signal and a system. Differential and difference equation Representations. properties of systems. Joseph J Distefano III et al. Schaum’s Outlines. Block diagram representations. John Wiley India Pvt. 2008. Fourier 26 . 8th Edition.. classification of signals. Ltd. Frequency response of LTI systems. 7 Hours UNIT 4: Fourier representation for signals – 1: Introduction. Fourier transform representation of periodic signals. TMH. Convolution Sum and Convolution Integral. “Automatic Control Systems”. 6 Hours UNIT 3: Time-domain representations for LTI systems – 2: Properties of impulse response representation.. elementary signals. Benjamin C. basic Operations on signals. 7 Hours PART – B UNIT 5: Fourier representation for signals – 2: Discrete and continuous Fourier transforms(derivations of transforms are excluded) and their properties. 2nd Edition 2007. 3. impulse response representation. 6 Hours UNIT 2: Time-domain representations for LTI systems – 1: Convolution. Discrete time and continuous time Fourier series (derivation of series excluded) and their properties . 6 Hours UNIT 6: Applications of Fourier representations: Introduction. Systems viewed as Interconnections of operations.2. Kuo. “Feedback and Control System”. SIGNALS & SYSTEMS (Common to EC/TC/IT/BM/ML) Sub Code Hrs/ Week Total Hrs. 2005. simulation and synthesis. R. 2. properties of Z – transforms..transform representation of discrete time signals. FUNDAMENTALS OF HDL (Common to EC/TC/IT/BM/ML) Sub Code Hrs/ Week Total Hrs. “Linear Systems and Signals”. Pearson/Sanguine Technical Publishers. 2nd ed. Z – transform. TMH. 2nd edition. B. Structure of HDL Module. Operators. 2006. 4. Scham’s outlines. Willsky and A Hamid Nawab. 2. Ganesh Rao and Satish Tunga. REFERENCE BOOKS: 1. 3. Alan S. Indian Reprint 2002. Data types. H. 2004. “Signals and Systems”. properties of ROC. 1997. Oxford University Press. Simon Haykin. Tata McGraw-Hill. Sampling theorm and Nyquist rate. “Fundamentals of Signals & Systems”. 2008. P. 2nd Edn. Ranjan. 2010. “Signals and Systems”. Michael Roberts. “Signals and Systems”. “Signals and Systems” Pearson Education Asia / PHI. Types of Descriptions. Lathi. A Brief History of HDL. 6 Hours TEXT BOOK 1. 6 Hours UNIT 8: Z-transforms – 2: Transform analysis of LTI Systems. John Wiley India Pvt. P Hsu. unilateral ZTransform and its application to solve difference equations. Alan V Oppenheim. 7 Hours UNIT 7: Z-Transforms – 1: Introduction. Ltd. : : : 10EC45 04 52 IA Marks Exam Hours Exam Marks : : : 25 03 100 PART – A UNIT 1: Introduction: Why HDL? . Brief comparison of VHDL and Verilog 7 Hours 27 . inversion of Z – transforms. and Functions: Highlights of Procedures.Nazeih M. 7 Hours PART – B UNIT 5: Procedures. 2. sequential statements. Generate. Pearson/Sanguin 2010. How to invoke One language from the Other.John Weily India Pvt. Limitations of Mixed-Language Description. 6 Hours UNIT 3: Behavioral Descriptions: Behavioral Description highlights. Structure of Data-Flow Description. Generic. 3.R. Mixed-Type Description examples 6 Hours UNIT 7: Mixed –Language Descriptions: Highlights of Mixed-Language Description. REFERENCE BOOKS: 1.UNIT 2: Data –Flow Descriptions: Highlights of Data-Flow Descriptions. 7 Hours UNIT 8: Synthesis Basics: Highlights of Synthesis. The VHDL variable –Assignment Statement. and Functions. and Parameter statements. Synthesis information from Entity and Module. Advanced HDL Descriptions: File Processing.Bhaskar – BS Publications 4. Binding. Mixed-language Description Examples. tasks. 2008. Procedures and tasks. Examples of File Processing 7 Hours UNIT 6: Mixed –Type Descriptions: Why Mixed-Type Description? VHDL UserDefined Types. Data Type – Vectors.J. 6 Hours TEXT BOOKS: 1.Botros. VHDL Packages. 6 Hours UNIT 4: Structural Descriptions: Highlights of structural Description. 28 . HDL Programming (VHDL and Verilog).Pedroni-PHI. Tasks. Functions. Organization of the structural Descriptions. Circuit Design with VHDL-Volnei A. Ltd. Mapping Process and Always in the Hardware Domain. A Verilog HDL Primer. state Machines. structure of HDL behavioral Description. VHDL -Douglas perry-Tata McGraw-Hill. Fundamentals of HDL – Cyril P. CMRR and PSRR. : : : 10EC46 04 52 IA Marks Exam Hours Exam Marks : : : 25 03 100 PART – A UNIT 1: Operational Amplifier Fundamentals: Basic Op-Amp circuit. Inverting amplifiers. Capacitor coupled Non-inverting Amplifiers. Current amplifiers. High input impedance . 7 Hours UNIT 2: Op-Amps as AC Amplifiers: Capacitor coupled Voltage Follower. and circuit stability precautions. Band width. Direct coupled -Voltage Followers.Biasing Op-Amps. Frequency and phase response. Log and antilog amplifiers.Capacitor coupled Voltage Follower. Multiplier 29 . 6 Hours PART – B UNIT 5: More applications: Clamping circuits. Slew rate and Frequency limitations.LINEAR IC’s & APPLICATIONS (Common to EC/TC/IT/BM/ML) Sub Code Hrs/ Week Total Hrs. 7 Hours UNIT 3: Op-Amps frequency response and compensation: Circuit stability. instrumentation amplifier. High input impedance . Input and output impedances. Summing amplifiers. 6 Hours UNIT 4: OP-AMP Applications: Voltage sources. Op-Amp parameters – Input and output voltage. Op-Amps as DC Amplifiers. Non-inverting Amplifiers. current sources and current sinks. Zin Mod compensation. Limiting circuits. sample and hold circuits. setting the upper cut-off frequency. Capacitor coupled Inverting amplifiers. precision rectifiers.Capacitor coupled Noninverting Amplifiers. Use of a single polarity power supply. Peak detectors. V to I and I to V converters. Frequency compensating methods. offset voltages and currents. Capacitor coupled Difference amplifier. Slew rate effects. Difference amplifier. 2nd edition. “Opamps. “Design with Operational Amplifiers and Analog Integrated Circuits”. 2.F. Schmitt trigger. 30 . 5. Elsever 3. Active Filters –First and second order Low pass & High pass filters. “Operational Amplifiers”.Basic timer circuit.and divider. Bell. “Operational Amplifiers and Linear IC’s”. 3rd ed. Jain. 4. Driscoll. Triangular / rectangular wave generators. 7 Hours TEXT BOOKS: 1. New Age International. 7 Hours UNIT 6: Non-linear circuit applications: crossing detectors. 555 timer used as astable and monostable multivibrator.. 5th ed. Applications and Trouble Shooting”. 6 Hours UNIT 7: Voltage Regulators: Introduction. Elsevier. Robert. Coughlin & Fred. David A. 2008. “Operational Amplifiers and Linear Integrated Circuits”. Phase detector / comparator. 2006. Roy Choudhury and Shail B. 2005. Switching regulator. Reprint 2006. D. Wave form generator design. VCO. 3e. phase shift oscillator. 2. IC Voltage regulators. Wein bridge oscillator. George Clayton and Steve Winder. inverting Schmitt trigger circuits. PLL-operating principles. Monostable & Astable multivibrator. 2006. Sergio Franco. 2nd edition.Design. Terrell. D/A and A/ D converters – Basic DAC Techniques. AD converters. 2004. PHI/Pearson. 6 Hours UNIT 8: Other Linear IC applications: 555 timer . F. REFERENCE BOOKS: 1. Series Op-Amp regulator. PHI/Pearson. “Linear Integrated Circuits”. 723 general purpose regulator. TMH. : : : 10ESL47 03 42 IA Marks Exam Hours Exam Marks : : : 25 03 50 I. Cube – (16 bits Arithmetic operations – bit addressable). 6. Code conversion: BCD – ASCII. External ADC and Temperature control interface to 8051. Alphanumeric LCD panel and Hex keypad input interface to 8051. Elevator interface to 8051.ASCII. Finding largest element in an array. Sorting. II. Simple Calculator using 6 digit seven segment displays and Hex Keyboard interface to 8051. using DAC interface to 8051. 12. 10. PROGRAMMING 1. 8. HEX . Conditional CALL & RETURN. Generate different waveforms Sine. Counters. 5. change the frequency and amplitude. Arithmetic Instructions . 2.Block move. 7.Decimal and Decimal .Addition/subtraction. Square. 3. Triangular. Data Transfer . Programs using serial port and on-Chip timer / counter. Boolean & Logical Instructions (Bit manipulations). 11. Programs to generate delay. INTERFACING: Write C programs to interface 8051 chip to Interfacing modules to develop single chip solutions. square. Exchange.HEX . Note: Programming exercise is to be done on both 8051 & MSP430. 9. Ramp etc.MICROCONTROLLERS LAB (Common to EC/TC/EE/IT/BM/ML) Sub Code Hrs/ Week Total Hrs. 13. ASCII – Decimal. multiplication and division. Decimal . 4. Stepper and DC motor control interface to 8051. 31 . PROGRAMMING (using VHDL /Verilog) 1. 8 to 3 (encoder without priority & with priority) c. 2 to 4 decoder b. : : : 10ECL48 03 42 IA Marks Exam Hours Exam Marks : : : 25 03 50 Note: Programming can be done using any compiler. 2. 4 bit binary to gray converter e. comparator. ALU should pass the result to the out bus when enable line in high.HDL LAB (Common to EC/TC/IT/BM/ML) Sub Code Hrs/ Week Total Hrs. de-multiplexer. Download the programs on a FPGA/CPLD boards such as Apex/Acex/Max/Spartan/Sinfi/TK Base or equivalent and performance testing may be done using 32 channel pattern generator and logic analyzer apart from verification by simulation with tools such as Altera/Modelsim or equivalent. Multiplexer. 32 . ALU should decode the 4 bit op-code according to the given in example below. Write a model for 32 bit ALU using the schematic diagram shown below A (31:0) B (31:0) Opcode (3:0) Enable • • • Out ALU should use combinational logic to calculate an output based on the four bit op-code input. and tri-state the out bus when the enable line is low. 8 to 1 multiplexer d. Write HDL code to realize all the logic gates Write a HDL program for the following combinational designs a. Write a HDL code to describe the functions of a Full Adder Using three modeling styles. 2. 3. direction of DC and Stepper motor. 4. BCD counters (Synchronous reset and Asynchronous reset) and “any sequence” counters INTERFACING (at least four of the following must be covered using VHDL/Verilog) 1. Temperature sensors and display the data on LCD panel or Seven segment display. Write HDL code to control speed. 3.. JK. 7. Write HDL code to generate different waveforms (Sine. 5. D. Design 4 bit binary. Square. 2. 4. 5. Write HDL code to simulate Elevator operations Write HDL code to control external lights using relays. ALU OPERATION A+B A–B A Complement A*B A AND B A OR B A NAND B A XOR B Develop the HDL code for the following flip-flops. 2.) using DAC change the frequency and amplitude. 8. Ramp etc. Triangle. T. 6. Write HDL code to accept 8 channel Analog signal. 3. 6.OPCODE 1. 4. SR. 33 . Write HDL code to display messages on the given seven segment display and LCD and accepting Hex key pad input data. 5. Management as a Science.an emerging Class. Concept of Entrepreneurship . Meaning and steps in controlling . 6 Hours ENTREPRENEURSHIP (PART – B ) UNIT .MBO and MBE (Meaning only) Nature and importance of Staffing . Types of Entrepreneur.5 ENTREPRENEUR: Meaning of Entrepreneur.Methods of establishing control. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 MANAGEMENT (PART – A ) UNIT . Communication . Entrepreneurship in India. Evolution of the Concept.Importance of planning .4 DIRECTING & CONTROLLING: Meaning and nature of directing Leadership styles. Functions of an Entrepreneur. Stages in entrepreneurial process. Levels of Management.1 MANAGEMENT: Introduction .Meaning and importance – Coordination.V SEMESTER MANAGEMENT & ENTREPRENEURSHIP Subject Code : 10AL51 No.2 PLANNING: Nature.Types of organization . Development of Entrepreneurship.Hierarchy of plans. Scope and functional areas of Management . 7 Hours UNIT . Intrapreneur . 6 Hours UNIT . Entrepreneurship – its Barriers.Types of plans (Meaning only) .Decision making . 6 Hours 34 . Role of entrepreneurs in Economic Development.Departmentation Committees – Centralisation Vs Decentralisation of authority and responsibility . Motivation Theories. 7 Hours UNIT .steps in planning & planning premises . of Lecture Hrs.Roles of Management.Essentials of a sound control system .Meaning . meaning and importance and Techniques of Co ordination. Art or Profession Management & Administration . of Lecture Hrs/Week : 04 Total no. importance and purpose of planning process Objectives .3 ORGANISING AND STAFFING: Nature and purpose of organization Principles of organization .nature and characteristics of Management. Development of Management Thought-Early Management Approaches-Modern Management Approaches.Span of control .Process of Selection & Recruitment (in brief).Evolution of Entrepreneurship. Project Appraisal. Impact of Liberalization.I. KSIMC. Entrepreneurship Development .P.Vasant Desai Himalaya Publishing House. DIC Single Window Agency: SISI. C.S. NSIC. N. Technical Feasibility Study. Project Selection.I. Objectives.UNIT .7 INSTITUTIONAL SUPPORT: Different Schemes. Financial Feasibility Study & Social Feasibility Study. Tata McGraw Hill. 2010. 7 Hours UNIT . Guidelines by Planning Commission for Project report. TECKSOK. Skill Development Robert Lusier – Thomson. 6 Hours UNIT . P. 7 Hours TEXT BOOKS: 1. Tripathi. Functions. Dynamics of Entrepreneurial Development & Management .Pearson Education /PHI -17th Edition. Need and Significance of Report. Globalization on S. Advantages of SSI Steps to start an SSI . Different Policies of S.6 SMALL SCALE INDUSTRY: Definition. Management Fundamentals . Identification of Business Opportunities .. during 5 year plans.S S Khanka . Application. role of SSI in Economic Development. Scope. 3. Project Identification. KIADB. Reddy.. 3.Market Feasibility Study. REFERENCE BOOKS: 1. Network Analysis.S Chand & Co.S.Government policy towards SSI. KSFC. Errors of Project Report. 2.8 PREPARATION OF PROJECT: Meaning of Project.S. Effect of WTO/GATT Supporting Agencies of Government for S. Project Report. Management . Ancillary Industry and Tiny Industry (Definition only). Types of Help.Stephen Robbins . Nature of Support. 2. 4th Edition. KSSIDC.S. Need and rationale: Objectives. Privatization. Contents.Concepts. SIDBI. Principles of Management .I Meaning.Small Business Enterprises Poornima M Charantimath .Pearson Education – 2006.I. Entrepreneurship Development . 35 . formulation. Characteristics. Government Support for S. 2003. DIGITAL SIGNAL PROCESSING Subject Code : 10EC52 No. of Lecture Hrs/Week : 04 Total no. of Lecture Hrs. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT - 1 Discrete Fourier Transforms (DFT): Frequency domain sampling and reconstruction of discrete time signals. DFT as a linear transformation, its relationship with other transforms. 6 Hours UNIT - 2 Properties of DFT, multiplication of two DFTs- the circular convolution, additional DFT properties. 6 Hours UNIT - 3 Use of DFT in linear filtering, overlap-save and overlap-add method. Direct computation of DFT, need for efficient computation of the DFT (FFT algorithms). 7 Hours UNIT - 4 Radix-2 FFT algorithm for the computation of DFT and IDFT–decimationin-time and decimation-in-frequency algorithms. Goertzel algorithm, and chirp-z transform. 7 Hours PART – B UNIT - 5 IIR filter design: Characteristics of commonly used analog filters – Butterworth and Chebysheve filters, analog to analog frequency transformations. 6 Hours UNIT - 6 Implementation of discrete-time systems: Structures for IIR and FIR systemsdirect form I and direct form II systems, cascade, lattice and parallel realization. 7 Hours UNIT - 7 FIR filter design: Introduction to FIR filters, design of FIR filters using Rectangular, Hamming, Bartlet and Kaiser windows, FIR filter design using frequency sampling technique. 6 Hours 36 UNIT - 8 Design of IIR filters from analog filters (Butterworth and Chebyshev) impulse invariance method. Mapping of transfer functions: Approximation of derivative (backward difference and bilinear transformation) method, Matched z transforms, Verification for stability and linearity during mapping 7 Hours TEXT BOOK: 1. Digital signal processing – Principles Algorithms & Applications, Proakis & Monalakis, Pearson education, 4th Edition, New Delhi, 2007. REFERENCE BOOKS: 1. Discrete Time Signal Processing, Oppenheim & Schaffer, PHI, 2003. 2. Digital Signal Processing, S. K. Mitra, Tata Mc-Graw Hill, 3rd Edition, 2010. 3. Digital Signal Processing, Lee Tan: Elsivier publications, 2007 ANALOG COMMUNICATION Subject Code : 10EC53 No. of Lecture Hrs/Week : 04 Total no. of Lecture Hrs. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT - 1 RANDOM PROCESS: Random variables: Several random variables. Statistical averages: Function of Random variables, moments, Mean, Correlation and Covariance function: Principles of autocorrelation function, cross – correlation functions. Central limit theorem, Properties of Gaussian process. 7 Hours UNIT - 2 AMPLITUDE MODULATION: Introduction, AM: Time-Domain description, Frequency – Domain description. Generation of AM wave: square law modulator, switching modulator. Detection of AM waves: square law detector, envelop detector. Double side band suppressed carrier modulation (DSBSC): Time-Domain description, Frequency-Domain representation, Generation of DSBSC waves: balanced modulator, ring modulator. Coherent detection of DSBSC modulated waves. Costas loop. 7 Hours 37 UNIT - 3 SINGLE SIDE-BAND MODULATION (SSB): Quadrature carrier multiplexing, Hilbert transform, properties of Hilbert transform, Preenvelope, Canonical representation of band pass signals, Single side-band modulation, Frequency-Domain description of SSB wave, Time-Domain description. Phase discrimination method for generating an SSB modulated wave, Time-Domain description. Phase discrimination method for generating an SSB modulated wave. Demodulation of SSB waves. 6 Hours UNIT - 4 VESTIGIAL SIDE-BAND MODULATION (VSB): Frequency – Domain description, Generation of VSB modulated wave, Time - Domain description, Envelop detection of VSB wave plus carrier, Comparison of amplitude modulation techniques, Frequency translation, Frequency division multiplexing, Application: Radio broadcasting, AM radio. 6 Hours PART – B UNIT - 5 ANGLE MODULATION (FM)-I: Basic definitions, FM, narrow band FM, wide band FM, transmission bandwidth of FM waves, generation of FM waves: indirect FM and direct FM. 6 Hours UNIT - 6 ANGLE MODULATION (FM)-II: Demodulation of FM waves, FM stereo multiplexing, Phase-locked loop, Nonlinear model of the phase – locked loop, Linear model of the phase – locked loop, Nonlinear effects in FM systems. 7 Hours UNIT - 7 NOISE: Introduction, shot noise, thermal noise, white noise, Noise equivalent bandwidth, Narrow bandwidth, Noise Figure, Equivalent noise temperature, cascade connection of two-port networks. 6 Hours UNIT - 8 NOISE IN CONTINUOUS WAVE MODULATION SYSTEMS: Introduction, Receiver model, Noise in DSB-SC receivers, Noise in SSB receivers, Noise in AM receivers, Threshold effect, Noise in FM receivers, FM threshold effect, Pre-emphasis and De-emphasis in FM,. 7 Hours 38 Lathi. microwave hybrid circuits. GUNN effect diodes – GaAs diode. BARITT diode. directional couplers.1 MICROWAVE TRANSMISSION LINES: Introduction.3 MICROWAVE DIODES. standing waves and SWR. Communication Systems. Ed 2007. MICROWAVES AND RADAR Subject Code : 10EC54 No. Simon Haykins. 2. 2. 2009. 6 Hours UNIT . 2008 REFERENCE BOOKS: 1. IMPATT diode..2 MICROWAVE WAVEGUIDES AND COMPONENTS: Introduction. John Wiley India Pvt. 2010. Communication Systems. of Lecture Hrs/Week : 04 Total no. 4th ed. Avalanche transit time devices: READ diode. Stern Samy and A Mahmond. Ltd. Schottky barrier diodes.. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . 7 Hours UNIT . Ltd. India Pvt.E. Modern digital and analog Communication systems B. Microwave coaxial connectors.TEXT BOOKS: 1. An Introduction to Analog and Digital Communication. Smith chart. Transfer electron devices: Introduction. circular waveguides. rectangular waveguides. 5th Edition. Simon Haykins. John Willey. circulators and isolators. 2004. Harold P. 7 Hours 39 . transmission lines equations and solutions. Oxford University Press. line impedance and line admittance. P. Pearson Edn. of Lecture Hrs. impedance matching using single stubs. reflection and transmission coefficients. 3. Parametric amplifiers Other diodes: PIN diodes. microwave cavities. Modes of operation. RWH theory. Communication Systems: Singh and Sapre: Analog and digital TMH 2nd . Attenuators. Shielded strip Lines.8 MTI AND PULSE DOPPLER RADAR: Introduction to Doppler and MTI Radar. 40 . Microwave Engineering – David M Pozar. Radar frequencies.4 Microwave network theory and passive devices.7 AN INTRODUCTION TO RADAR: Basic Radar.6 STRIP LINES: Introduction. 3. 2008. Magic tees. 6 Hours UNIT . digital MTI processing. 2nd . Symmetrical Z and Y parameters.. 7 Hours UNIT . the origins of Radar. REFERENCE BOOK: 1. 6 Hours UNIT . pulse Doppler Radar. Coaxial connectors and adapters. 3rd Edn. Waveguide Tees. Moving target detector. Phase shifters. John Wiley India Pvt. 2. Coplanar strip lines.5 Microwave passive devices. delay line Cancellers. Microwave Engineering – Annapurna Das. The simple form of the Radar equation. S matrix representation of multi port networks. Radar block diagram. 3rd Ed. 2010.Liao / Pearson Education. Microwave Devices and circuits. Introduction to Radar systems-Merrill I Skolnik. for reciprocal Networks.UNIT . Ltd. application of Radar. 2001. Sisir K Das TMH Publication. 6 Hours PART – B UNIT . Parallèle strip lines. 7 Hours TEXT BOOKS: 1. TMH. Microstrip lines. Differential entropy and mutual information for continuous ensembles. Algebraic structures of cyclic codes. Markoff statistical model for information source. Average information content of symbols in long dependent sequences. Entropy and information rate of mark-off source. 6 Hours UNIT . Huffman coding.6 Binary Cycle Codes. Continuous channels. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . Channel capacity Theorem. Mutual information. 7 Hours UNIT . Error detection and correction.INFORMATION THEORY AND CODING Subject Code : 10EC55 No. Syndrome calculation. Shannon’s encoding algorithm. Channel Capacity. 7 Hours UNIT .4 Channel coding theorem.2 SOURCE CODING: Encoding of the source output. 7 Hours UNIT . 6 Hours PART – B UNIT . 6 Hours 41 . Discrete communication channels. Encoding using an (n-k) bit shift register. BCH codes. Communication Channels. Measure of information. Standard arrays and table look up for decoding.3 FUNDAMENTAL LIMITS ON PERFORMANCE: Source coding theorem.1 INFORMATION THEORY: Introduction.5 INTRODUCTION TO ERROR CONTROL CODING: Introduction. examples. Average information content of symbols in long independent sequences. of Lecture Hrs. Types of errors. of Lecture Hrs/Week : 04 Total no. Discrete memory less Channels. Types of codes Linear Block Codes: Matrix description. Production of E-beam masks. Pearson Ed. Ltd. of Lecture Hrs. 2007 2. ITC and Cryptography. Time domain approach. 7 Hours UNIT . II edition. 2. The Differential Inverter. Ranjan Bose. 4 Hours 42 . Transform domain approach. The Transmission Gate. Enhancement and depletion mode MOS transistors. CMOS fabrication. BiCMOS technology. Shortened cyclic codes. K. Ltd.7 RS codes. MOS Device Design Equations. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . 6 Hours TEXT BOOKS: 1. FUNDAMENTALS OF CMOS VLSI Subject Code : 10EC56 No.8 Convolution Codes. 3 Hours MOS TRANSISTOR THEORY: Introduction. Digital and analog communication systems.UNIT . Thermal aspects of processing. Static Load MOS Inverters. Digital communication. Burst and Random Error correcting codes.1 BASIC MOS TECHNOLOGY: Integrated circuit’s era. 2nd Ed 2008. John Wiley India Pvt.Glover and Grant. Sam Shanmugam. 1996. Simon Haykin. 2008. Golay codes. Burst error correcting codes. TMH. of Lecture Hrs/Week : 04 Total no. John Wiley India Pvt. Digital Communications . The Complementary CMOS Inverter – DC Characteristics. Tristate Inverter. REFERENCE BOOKS: 1. nMOS fabrication. 5 CMOS SUBSYSTEM DESIGN: Architectural issues. ALU subsystem. Other system considerations. Capacitance calculations.3 CMOS LOGIC STRUCTURES: CMOS Complementary Logic. Wiring capacitances. 3 Hours SCALING OF MOS CIRCUITS: Scaling models and factors.UNIT . Examples. 3 Hours UNIT . Limits due to current density and noise. 6 Hours UNIT . REGISTERS AND CLOCK: Timing considerations. Pass Transistor Logic. Dynamic CMOS Logic. Memory elements. Design examples – combinational logic. Switch logic. Clocked circuits. Symbolic diagrams. Tutorial exercises. Design rules and layout – lambda-based design and other rules. Adders. Driving capacitive loads. 3 Hours PART – B UNIT . Bi CMOS Logic.7 MEMORY. Propagation delays. Gate logic. Multipliers. 5 Hours Clocking Strategies 2 Hours UNIT . Layout diagrams. Limits on scaling.6 CMOS SUBSYSTEM DESIGN PROCESSES: General considerations.4 BASIC CIRCUIT CONCEPTS: Sheet resistance. 6 Hours 43 . Area capacitances. 4 Hours Basic Physical Design of Simple logic gates. The delay unit. Pseudo-nMOS Logic. Process illustration. 6 Hours UNIT . Clocked CMOS Logic. CMOS Domino Logic Cascaded Voltage Switch Logic (CVSL). Memory cell arrays.2 CIRCUIT DESIGN PROCESSES: MOS layers. Inverter delays. Stick diagrams. CMOS VLSI Design – A Circuits and Systems Perspective. Weste and David Harris. Weste.D. Real estate. Ltd. 3. Test and testability. 2008. Circular convolution of two given sequences 44 . 4. Ltd.UNIT . K. N. CMOS Digital Integrated Circuits: Analysis and Design. 2. New Delhi. Pearson Education (Asia) Pvt.A Saleh. Layout and Simulation. I/O pads. Principles of CMOS VLSI Design: A Systems Perspective.A Hodges. and ??? 3rd edition. 3rd Edition. Jacob Baker. Verification of Sampling theorem. Addison-Wesley..G Jackson and R.H. H. Tata McGraw-Hill Publishing Company Ltd. Bhat. Achuthan and K. CMOS Circuit Design. 2007. 2007. 3rd Edition. 5. 2005. Impulse response of a given system Linear convolution of two given sequences. Neil H. Layout issues. 2005. New Delhi. SungMo Kang & Yusuf Leblebici. Tata McGraw-Hill Publishing Company Limited.8 TESTABILITY: Performance parameters. 7 Hours TEXT BOOKS: 1. PHI 3rd Edition (original Edition – 1994). Fundamentals of Semiconductor Devices. 3. 3rd Edition.). Analysis and Design of Digital Integrated Circuits .com). M. 2007.Douglas A. E. Ground rules for design. R. Eshragian. (Refer to http://www. John Wiley India Pvt. 4. Basic VLSI Design . N. DIGITAL SIGNAL PROCESSING LABORATORY Subject Code : 10ECL57 No. System delays..cmosvlsi. : 42 IA Marks Exam Hours Exam Marks : 25 : 03 : 50 A LIST OF EXPERIMENTS USING MATLAB / SCILAB / OCTAVE / WAB 3. 2. Pucknell & Kamran Eshraghian. of Practical Hrs. New Delhi. REFERENCE BOOKS: 1. Tata McGraw-Hill Publishing Company Limited. 200?. (Shift to the latest edition. of Practical Hrs/Week: 03 Total no. 6. K. 11. 9. 10. Digital signal processing using MATLAB . 2.Audio applications such as to plot time and frequency (Spectrum) display of Microphone output plus a cosine using DSP. 3.Noise: Add noise above 3kHz and then remove. LIST OF EXPERIMENTS USING DSP PROCESSOR 1. of Practical Hrs/Week : 03 Total no. TMH. Second order active LPF and HPF Second order active BPF and BE Schmitt Trigger Design and test a Schmitt trigger circuit for the given values of UTP and LTP 45 .Computation of N. 8. Solving a given difference equation. 2000 3. Digital Signal Processors. MGH.Realization of an FIR filter (any type) to meet given specifications .Point DFT of a given sequence 4. B. Design and implementation of IIR filter to meet given specifications.Circular convolution of two given sequences. 2.J. 14. 5.2009 CAN BE USED FOR VERIFICATION AND TESTING. G. Cross correlation of given sequences and verification of its properties.The input can be a signal from function generator / speech signal. Venkataramani and Bhaskar. 13. 1.7. 7. 12. Autocorrelation of a given sequence and verification of its properties. Digital signal processing using MATLAB .2002 ANALOG COMMUNICATION LAB + LIC LAB Subject Code : 10ECL58 No. Interference suppression using 400 Hz tone. Linear convolution of two sequences using DFT and IDFT. 3.Sanjeet Mitra. TMH.Impulse response of first order and second order system REFERENCE BOOKS: 1. Read a wav file and match with their respective spectrograms 6. B.Linear convolution of two given sequences. : 42 IA Marks Exam Hours Exam Marks : 25 : 03 : 50 EXPERIMENTS USING DESCERTE COMPONENTS and LABVIEW . Computation of N point DFT of a given sequence and to plot magnitude and phase spectrum. Circular convolution of two given sequences using DFT and IDFT Design and implementation of FIR filter to meet given specifications. 2001 2. of Practical Hrs. Proakis & Ingale. Pulse amplitude modulation and detection 10. Design and test R-2R DAC using op-amp Design and test the following circuits using IC 555 a. Precision rectifiers – both Full Wave and Half Wave. PWM and PPM 11. 6. Frequency synthesis using PLL. Frequency modulation using 8038/2206 12. 5. Amplitude modulation using transistor/FET (Generation and detection) 9. Astable multivibrator for given frequency and duty cycle b.4. IF amplifier design 8. 46 . Monostable multivibrator for given pulse width W 7. 7 Hours UNIT . Quadrature sampling of Band pass signal.5 DIGITAL MODULATION TECHNIQUES: Digital Modulation formats. Nyquist’s criterion for distortion less base-band binary transmission. Coherent binary modulation techniques. detection of signals with unknown phase in noise. 7 Hours UNIT . eye pattern. 6 Hours UNIT .3 DPCM. matched filter receiver. response of bank of correlators to noisy input. Sampling Principles: Sampling Theorem. base-band M-ary PAM systems. Coherent quadrature modulation techniques. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . correlation receiver. 6 Hours UNIT . Discrete PAM signals.6 Detection and estimation. power spectra of discrete PAM signals.VI SEMESTER DIGITAL COMMUNICATION Subject Code : 10EC61 No.7 Detection of known signals in noise. of Lecture Hrs/Week : 04 Total no. robust quantization. 6 Hours PART – B UNIT .4 ISI.1 Basic signal processing operations in digital communication. Practical aspects of sampling and signal recovery. TDM.2 PAM. adaptive equalization for data transmission. applications. Gram-Schmidt Orthogonalization procedure. Base-Band Shaping for Data Transmission. correlative coding. Quantization noise and SNR. 7 Hours 47 . Waveform Coding Techniques. DM. 6 Hours UNIT . Non-coherent binary modulation techniques. geometric interpretation of signals. Model of DCS. PCM. of Lecture Hrs. 3 BYTE AND STRING MANIPULATION: String instructions. 6 Hours UNIT . The microprocessor-based personal computer system. Digital communications . Machine language instructions. direct sequence spread spectrum.4 8086 INTERRUPTS: 8086 Interrupts and interrupt responses.2 INSTRUCTION SET OF 8086: Assembler instruction format.Bernard Sklar: Pearson education 2007 MICROPROCESSOR Subject Code : 10EC62 No. John Wiley India Pvt. Simon Haykin. Instruction execution timing. Software interrupt applications. Programming using keyboard and video display. Procedures. Ltd. loop. K. Illustration of these instructions with example programs. logical and shift and rotate instructions. Number format conversions. Interrupt examples. Digital communications. notion of spread spectrum. frequency hop spread spectrum. 6 Hours UNIT . 7 Hours 48 . of Lecture Hrs/Week : 04 Total no. Directives and operators. flag manipulation. REP Prefix. Simon Haykin. coherent binary PSK. 7 Hours UNIT . 2008 2. Digital and Analog communication systems.UNIT . Macros. John Wildy India Lts. branch type. Hardware interrupt applications. of Lecture Hrs. 8086 CPU Architecture. applications.8 Spread Spectrum Modulation: Pseudo noise sequences. data transfer and arithmetic.1 8086 PROCESSORS: Historical background. 2008. John Wiley India Pvt. 7 Hours TEXT BOOK: 1. 3. 2008. NOP & HALT. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . REFERENCE BOOKS: 1. An introduction to Analog and Digital Communication. Ltd. Sam Shanmugam. Table translation. 2006.Programming & Hardware. Bhurchandi. TMH. Hardware & Applications . 4e. 2006. 80486 AND PENTIUM PROCESSORS: Introduction to the 80386 microprocessor.Programming. 2003 REFERENCE BOOKS: 1. Gibson. Pearson Education. Interfacing to alphanumeric displays (interfacing LED displays to microcomputer).7 SYSTEM BUS STRUCTURE: Basic 8086 configurations: minimum mode. The 8087 numeric data processor: data types. Advanced Microprocessors and Peripherals .6 8086 BASED MULTIPROCESSING SYSTEMS: Coprocessor configurations. Introduction to the Pentium microprocessor. 2.A.Triebel and Avtar Singh. Douglas hall.PART – B UNIT . Interfacing a microcomputer to a stepper motor. 7 Hours TEXT BOOKS: 1.5 8086 INTERFACING: Interfacing microprocessor to keyboard (keyboard types. processor architecture. Bus Interface: peripheral component interconnect (PCI) bus. 6 Hours UNIT . 2E PHI -2003 2. 2003 49 . 6e. The Intel Microprocessor. 8088 and 8086 Microprocessors . Ray and K. Microprocessor and Interfacing. Programming and Interfacing-Barry B. Introduction to the 80486 microprocessor. Liu and G. instruction set and examples. Brey. 7 Hours UNIT . Architecture.K. Software. maximum mode. 3. software keyboard interfacing.8 80386. A.M. Microcomputer systems-The 8086 / 8088 Family – Y. 2nd . keyboard interfacing with hardware). the parallel printer interface (LPT). Interfacing. Pearson Education / PHI. Special 80386 registers. TMH. the universal serial bus (USB) 6 Hours UNIT . keyboard circuit connections and interfacing.C. 2nd . small signal operation modes. CoUmparison of MOSFET and BJT. Small Signal Operation and Models. single stage MOS amplifiers. detection type MOSFET. the BJT differences pair. 6 Hours UNIT – 3 Single Stage IC amplifiers (continued): CS and CF amplifiers with loads. of Lecture Hrs/Week : 04 Total no. MOSFET as an amplifier and as a switch.MICROELECTRONICS CIRCUITS Subject Code : 10EC63 No. Differential amplifier with active loads. Current sources. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT – 1 MOSFETS: Device Structure and Physical Operation. SPICE examples. Determining the loop gain. biasing in MOS amplifier circuits. Multistage amplifier. Properties of negative feedback. MOSFET Circuits at DC. of Lecture Hrs. high frequency response of CS and CF amplifiers. 6 Hours UNIT – 4 Differences and Multistage Amplifiers: The MOS differential pair. CS and CE amplifiers with source ( emitter) degeneration source and emitter followers. MOSFET internal capacitances and high frequency modes. current mirrors with improved performance. high frequency response of CG and CB amplifiers. V-I Characteristics. CG and CB amplifiers with active loads. 7 Hours UNIT -2 Single Stage IC Amplifier: IC Design philiosophy. frequency response and differential amplifiers. some useful transfer parings. SPICE examples. 7 Hours PART – B UNIT – 5 Feedback. Frequency response of CS amplifiers. Series-Shunt feedback. Current mirrors and Current steering circuits. 50 . other non-ideal characteristics and differential pair. small signal operation of MOS differential pair. Biasing in MOS amplifier Circuits. Cascade amplifiers. CMOS digital logic inverter. high frequency response. Four basic feedback topologies. General Feedback structure. A-D and D-A converters. 2. antenna apertures. efficiency. diversity and gain.Stability problem. 6 Hours UNIT – 7 & 8 Digital CMOS circuits. SPICE examples. effective height. Tata McGraw-Hill. Effect of feedback an amplifier poles. Frequency compensation. Dynamic Logic Circuits. Logic Gate Circuits. Overview. SPICE examples. beam area. gain. 2007 ANTENNAS AND PROPAGATION Subject Code : 10EC64 No. 7 Hours UNIT . “Fundamentals of Microelectronics” . Oxford University Press. REFERENCE BOOK: 1.1 ANTENNA BASICS: Introduction. Data Converters. 2009.C. 5th Edition. patterns. DC analysis of the 741. 3. Design and performance analysis of CMOS inverter. Smith.6 Operational Amplifiers: The two stage CMOS Op-amp. radiation intensity. John Wiley India Pvt. Adel Sedra and K. frequency response and slew rate of 741. Sundaram Natarajan. 12 Hours TEXT BOOK: 1. beam efficiency. folded cascade CMOS op-amp. of Lecture Hrs/Week : 04 Total no. Stability study using Bode plots. Interantional Version. basic Antenna parameters. Pass-transistor logic. Ltd. of Lecture Hrs. small signal analysis of 741. “Microelectronic Circuits”. antenna temperature and antenna filed zones. 7 Hours 51 . Behzad Razavi. 741 op-amp circuit. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . bandwidth. 2008. “Microelectronics – Analysis and Design”. radiation. TROPOSPHERE WAVE PROPAGATION: Troposcopic scatter. embedded antennas. directivity. PATCH AND HORN ANTENNA: Introduction.UNIT . 8 Hours PART – B UNIT – 5 & 6 ANTENNA TYPES: Horn antennas. power patterns. patch antennas. parabolic reflectors.3 ELECTRIC DIPOLES AND THIN LINEAR ANTENNAS: Introduction. plasma antenna. Helical Antenna. free space propagation. Yagi-Uda array. 6 Hours UNIT . thin linear antenna. ultra wide band antennas. radiation resistance of short dipole.4 LOOP. lens antenna. surface wave. turnstile antenna. diffraction. 7 Hours UNIT . micro strip arrays. slot antenna. Array of two isotropic point sources. power theorem. filed patterns. electrical properties of the ionosphere. rectangular horn antennas. loop antenna general case. long wire antenna. corner reflectors.7 & 8 RADIO WAVE PROPAGATION: Introduction. antenna for remote sensing. omni directional antennas. 10 Hours 52 . effects of earth’s magnetic field. Babinet’s principle and complementary antennas. small loop. far field patterns of circular loop. low side lobe arrays. high-resolution data. radiation intensity. antennas for satellite antennas for ground penetrating radars. short electric dipole.2 POINT SOURCES AND ARRAYS: Introduction. SLOT. folded dipole antennas. intelligent antennas. 12 Hours UNIT . Ionosphere propagation. impedance of complementary and slot antennas. Ground wave propagation. comparison of far fields of small loop and short dipole. antenna for special applications – sleeve antenna. ground reflection. radiation resistance. phase patterns. point sources. log periodic antenna. Endfire array and Broadside array. fields of a short dipole(no derivation of field components). radiation resistances of lambda/2 Antenna. Time sharing systems. Krauss. layered design. Antennas and Wave Propagation. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . 2. Virtual machine operating systems. John Wiley. John Wiley India Pvt. 2003. 3rd Edn. of Lecture Hrs.S.TEXT BOOKS: 1. distributed operating systems. 7 Hours 53 . Ltd. OPERATING SYSTEMS Subject Code : 10EC65 No. Antennas and Wave Propagation . 4th Edn. Kernel based operating systems. Antennas and wave propagation . Multi programming systems. and Microkernel based operating systems. 6 Hours UNIT . Real time operating systems.1 INTRODUCTION AND OVERVIEW OF OPERATING SYSTEMS: Operating system. 2.S and the computer system. Structure of the supervisor.Harish and Sachidananda: Oxford Press 2007. Antennas and Propagation for Wireless Communication Systems . Goals of an O. 2010.S. John D. 3. of Lecture Hrs/Week : 04 Total no. O.McGraw-Hill International edition. Resource allocation and related functions. REFERENCE BOOKS: 1. 2008. Operation of an O.S. Configuring and installing of the supervisor. Antenna Theory Analysis and Design . Classes of operating systems.C A Balanis. Operating system with monolithic structure.Sineon R Saunders. Batch processing system.2 STRUCTURE OF THE OPERATING SYSTEMS: Operation of an O. User interface related functions.G S N Raju: Pearson Education 2005. 2001. Process scheduling in UNIX. OS view of processes. Contiguous and noncontiguous allocation to programs. 2001. REFERENCE BOOK: 1. Interface between file system and IOCS. TMH. kernel memory allocation. 5th Edition. 3.UNIT . Tennambhaum.5 VIRTUAL MEMORY: Virtual memory basics. Operating System – Internals and Design Systems. “Operating Systems . Threads in Solaris. Inter process communication in UNIX. 7 Hours PART – B UNIT . M. 2010. 2. D. Page replacement policies.A Concept based Approach”. 2006. Silberschatz and Galvin. Overview of I/O organization. Demand paging. Memory allocation preliminaries. Processes in UNIX. Memory allocation for program controlled data. Real time scheduling. UNIX virtual memory. Design of Operating Systems.3 PROCESS MANAGEMENT: Process concept. TMH. Willaim Stalling. Threads. Medium and short term scheduling. Allocation of disk space.4 MEMORY MANAGEMENT: Memory allocation to programs. Operating Systems Concepts.8 MESSAGE PASSING: Implementing message passing. 6 Hours UNIT . Files and directories. 54 . Implementing file access. 3rd Ed. Page sharing. Page replacement. Fundamental file organizations. UNIX file system. Interacting processes.7 SCHEDULING: Fundamentals of scheduling. 7 Hours UNIT . 7 Hours TEXT BOOK: 1. 4th Ed. Memory allocation to programs. Virtual memory using paging. Long-term scheduling. Ltd.6 FILE SYSTEMS: File system and IOCS. Pearson Education. Dhamdhare. Programmer view of processes. Mailboxes. John Wiley India Pvt. 6 Hours UNIT . 6 Hours UNIT . 2. power. (b) Measurement of power division and isolation characteristics of a microstrip 3 dB power divider. VSWR and attenuation in a microwave test bench 10. guide wavelength. 9. 4. 5. of Practical Hrs. 6. of Practical Hrs/Week: 03 Total no. Determination of coupling and isolation characteristics of a stripline (or microstrip) directional coupler 12. ASK and FSK generation and detection PSK generation and detection DPSK generation and detection QPSK generation and detection PCM generation and detection using a CODEC Chip Measurement of losses in a given optical fiber ( propagation loss. Measurement of frequency. 7. : 42 I) IA Marks Exam Hours Exam Marks : 25 : 03 : 50 Programs involving 1) Data transfer instructions like: i] Byte and word data transfer in different addressing modes. microstrip patch antenna and Yagi antenna (printed). MICROPROCESSOR LAB Subject Code : 10ECL68 No. 55 . (a) Measurement of resonance characteristics of a microstrip ring resonator and determination of dielectric constant of the substrate. 1. 11. Measurement of directivity and gain of antennas: Standard dipole (or printed dipole). of Practical Hrs. bending loss) and numerical aperture 8. : 42 IA Marks Exam Hours Exam Marks : 25 : 03 : 50 LIST OF EXPERIMENTS USING DESCERTE COMPONENTS and LABVIEW – 2009 can be used for verification and testing.ADVANCED COMMUNICATION LAB Subject Code : 10ECL67 No. TDM of two band limited signals. 3. Analog and Digital (with TDM) communication link using optical fiber. of Practical Hrs/Week: 03 Total no. LCM. factorial 3) Bit manipulation instructions like checking: i] Whether given data is positive or negative ii] Whether given data is odd or even iii] Logical 1’s and 0’s in a given data iv] 2 out 5 code v] Bit wise and nibble wise palindrome 4) Branch/Loop instructions like: i] Arrays: addition/subtraction of N nos. searching for a string.ii] Block move (with and without overlap) iii] Block interchange 2) Arithmetic & logical operations like: i] Addition and Subtraction of multi precision nos. Ascending and descending order ii] Near and Far Conditional and Unconditional jumps. GCD. ii] Multiplication and Division of signed and unsigned Hexadecimal nos. Buffered Keyboard input. iii] ASCII adjustment instructions iv] Code conversions v] Arithmetic programs to find square cube. Finding largest and smallest nos. Display of character/ String on console II) Experiments on interfacing 8086 with the following interfacing modules through DIO (Digital Input/Output-PCI bus compatible) card a) Matrix keyboard interfacing b) Seven segment display interface c) Logical controller interface d) Stepper motor interface III) Other Interfacing Programs a) Interfacing a printer to an X86 microcomputer b) PC to PC Communication 56 . 6) Programs involving Software interrupts Programs to use DOS interrupt INT 21h Function calls for Reading a Character from keyboard. string reversing. Calls and Returns 5) Programs on String manipulation like string transfer. etc. Decimating Filters for ADCs (Excluding Decimating without Averaging onwards). ADC Architectures. Digital Input Code. Integrating ADC. Pipeline DAC. Capacitors and Resistors. Multiplying Quad (Excluding Stimulation). Converting Analog Signals to Data Signals. Flash. DAC Specifications. Analog Circuits MOSFET Biasing (upto MOSFET Transition Frequency). 7 Hours (Text Book 2) UNIT 4: Data Converter SNR: Improving SNR Using Averaging (Excluding Jitter & Averaging onwards). Charge Scaling DACs. Band pass and High pass Sync filters. Cyclic DAC. Analog Multipliers. Sample and Hold Characteristics. R-2R Ladder Networks. Interpolating Filters for DAC. of Lecture Hrs. Successive Approximation ADC.ELECTIVE – I (GROUP A) ANALOG AND MIXED MODE VLSI DESIGN Subject Code : 10EC661 No. of Lecture Hrs/Week : 04 Total no. 2-Step Flash ADC. MOSFET Switch (upto Bidirectional Switches). Current Steering. Resistors String. 10 Hours UNIT 6 OPAmp Design (Excluding Circuits Noise onwards) 8 Hours TEXT BOOK: 57 . Level Shifting (Excluding Input Level Shifting For Multiplier). ADC Specifications. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 (Text Book 1) UNIT 1 Data converter fundamentals: Analog versus Digital Discrete Time Signals. Pipeline ADC. Delay and adder Elements. 7 Hours UNIT 2 Data Converters Architectures: DAC Architectures. Mixed-Signal Layout Issues. 12 Hours UNIT 3 Non-Linear Analog Circuits: Basic CMOS Comparator Design (Excluding Characterization). 8 Hours UNIT 5 Su-Microns CMOS circuit design: Process Flow. 2001.3 PROPAGATION IMPAIRMENTS AND SPACE LINK: Introduction. (Vol II of CMOS: Circuit Design. Ltd. earth eclipse of satellite. CMOS Analog Circuit Design. sun transit outage. polar mix antenna.First Edition. antenna. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . orbital plane.1. limits of visibility. CMOS Circuit. frequency allocation. Kepler laws. universal time. antenna subsystem. leandiag orbits. of Lecture Hrs. TT&C. Jacob Baker. Layout and Stimulation). local mean time and sun synchronous orbits. altitude control. atmospheric loss. 2008. uplink. Design of Analog CMOS Integrated Circuits.4 SPACE SEGMENT: Introduction. REFERENCE BOOKS: 1. McGraw Hill. sidereal time.1 OVER VIEW OF SATELLITE SYSTEMS: Introduction. B Razavi. P e Allen and D R Holberg. Edition. John Wiley India Pvt. 7 Hours UNIT .Mixed Signal Circuit Design . down link. PHI Education. Design. orbital element. 2005.R. Jacob Baker. power supply units. transponders. of Lecture Hrs/Week : 04 Total no. CMOS. effects of rain. rain attenuation. apogee and perigee heights. link power budget. ionospheric effects. Harry W Li. 6 Hours 58 . CNR. inclined orbits. SPACE LINK: Introduction. combined CNR. orbit perturbations. other impairments. system noise. transmission losses. 6 Hours UNIT . EIRP. station keeping. definitions. Geostationary orbit: Introduction. thermal control. Stimulation . look angles. 7 Hours UNIT . calendars. 2.2 ORBITS: Introduction. Layout.R. David E Boyce. 2nd 3.2002. Oxford University Press. 2. SATELLITE COMMUNICATION Subject Code : 10EC662 No. INTEL Sat. comparison of uplink power requirements for TDMA & FDMA. MATV. 4th Edition. interference between satellite circuits. SCPC (spade system). McGrawHill International edition. Assigning probabilities.1 INTRODUCTION TO PROBABILITY THEORY: Experiments. L. RadarSat. Satellite Communication Systems Engineering. Events. Pitchand. 2008. orb communication and Indian Satellite systems. R. REFERENCES BOOKS: 1. 2006. H. indoor unit. out door unit. receive only home TV system. Joint and conditional 59 . frequency and polarization. John Wiley Pvt. Satellite Communications. L. GPS. RANDOM PROCESSES Subject Code : 10EC663 No. 2007.7 & 8 DBS. Nelson. CATV. Timothy Pratt. on board signal processing satellite switched TDMA. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . pre-assigned TDMA. of Lecture Hrs. demand assigned TDMA. of Lecture Hrs/Week : 04 Total no. W.. Tx – Rx earth station. USAT. Axioms. power ratio. SATELLITE MOBILE AND SPECIALIZED SERVICES: Introduction.. 5 Hours INTERFERENCE AND SATELLITE ACCESS: Introduction. 9 Hours UNIT . bit rates for digital TV. Suyderhoud. transponder capacity. Ltd & Sons. Charles Bostian and Jeremy Allnutt. 2. satellite mobile services. Dennis Roddy. sample space.5 & 6 EARTH SEGEMENT: Introduction. 2nd Ed. down link analysis.PART – B UNIT . TDMA. Satellite Communications. orbital spacing. single access. Pearson Education. preassigned FDMA. 12 Hours TEXT BOOK: 1. A. 2nd Edition. satellite access. Baye’s Theorem. Moment generating functions. Chi-Square. PDF.EV involving multiple Random variables.4 Characteristic functions. 6 Hours UNIT . PDF. Raleigh. Independence. Engg application. Gaussian Random variable in multiple dimension. 6 Hours UNIT .3 OPERATIONS ON A SINGLE R V: Expected value. Joint CDF.8 EXAMPLE PROCESSES: Markov processes. Engg application. 6 Hours PART – B UNIT .probabilities. Laplace. EV of Random variables. Engg applications. CDF. Discrete Random Variables. Stationary and Ergodic Random processes. Distributions. entropy and source coding. Properties of ACF. Uniform Exponential. Scalar quantization. Engg Example. Gamma. Probability generating functions. Independent Random variables. joint PDF. 6 Hours UNIT . 7 Hours UNIT . Gaussian Processes. 7 Hours 60 . density and mass functions. linear prediction. Poisson Processes. 7 Hours UNIT . Central Moments.6 MULTIPLE RANDOM VARIABLES: Joint and conditional PMF. Conditional Distribution. Complex Random variables. Engg Application.7 RANDOM PROCESS: Definition and characterization. Telephone networks. Conditional expected values. EV involving pairs of Random variables. Joint probability mass functions.. EV of functions of Random variables. Gaussian random variable. Rician and Cauchy types of random variables.2 Random Variables. Erlang. Density Functions: CDF.5 Pairs of Random variables. Mathematical tools for studying Random Processes. 7 Hours UNIT . Computer networks. fundamental limits.2 Power dissipation in CMOS – Short circuit dissipation. Physics of power dissipation in MOSFET devices – MIS Structure.A. of Lecture Hrs/Week : 04 Total no. Circuit activity driven architectural transformations. 12 Hours 61 . Probability and random processes: application to Signal processing and communication . Probability. Long channel and sub-micron MOSFET. LOW POWER VLSI DESIGN Subject Code : 10EC664 No. pre. Sources of power dissipation. Papoullis and S U Pillai: McGraw Hill 2002. 6 Hours UNIT . voltage scaling. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT – 1 Introduction. FSM and Combinational logic.H Stark and Woods: PHI 2001. Hierarchy of limits. Algorithm level transforms. Low power design limits . of Lecture Hrs. circuit and system limits. operation reduction and substitution. Random variables and Random signal principles Peyton Z Peebles: TMH 4th Edition 2007. Probability. 8 Hours UNIT – 3&4 SYNTHESIS FOR LOW POWER: Behavioral.Principles of low power design. Power-constrained Least squares optimization for adaptive and non-adaptive filters. random processes and applications . Load capacitance. Transistor sizing. Probability. 2. 3. Random variables and stochastic processes . device. Material. dynamic dissipation. designing for low power. Gate induced Drain leakage.computation.TEXT BOOK: 1.S L Miller and D C Childers: Academic Press / Elsivier 2004 REFERENCE BOOKS: 1. Logic and Circuit level approaches. Design of peripheral circuits – address decoder. 7 Hours 62 . device design issues. Low voltage design techniques using reverse Vgs. Leakage current in Deep sub-micron transistors. level shifter and I/O Buffer. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . of Lecture Hrs/Week : 04 Total no. Low-Power CMOS VLSI Circuit Design. Introduction. Linear lists. minimizing short channel effect. steep sub threshold swing and multiple threshold voltages. Kaushik Roy and Sharat C Prasad.PART – B UNIT – 5&6 DESIGN AND TEST OF LOW-VOLTAGE CMOS CIRCUITS: Introduction. 7 Hours TEXT BOOK: 1. of Lecture Hrs. DATA STRUCTURE USING C++ Subject Code : 10EC665 No. Energy recovery circuit design. supply clock generation. multiple supply voltages. 2008. power estimation and optimization.8 SOFTWARE DESIGN FOR LOW POWER: Introduction.1 INTRODUCTION: Functions and parameters.7 LOW ENERGY COMPUTING: Energy dissipation in transistor channel. energy recovery in adiabatic logic and SRAM core. designs with reversible and partially reversible logic. Testing and debugging. Testing with elevated intrinsic leakage. Dynamic memory allocation classis. 12 Hours UNIT . Data Representation. Ltd. 7 Hours UNIT . sources of power dissipation. Design style. John Wiley Pvt. Formula-based representation linked representation. Indirect addressing simulating pointers. 6 BINARY AND OTHER TREES: Trees.7 PRIRITY QUEUES: Linear lists.5 SKIP LISTS AND HASHING: Dictionaries.UNIT . 6 Hours UNIT . Matrices. 4th. 6 Hours TEXT BOOK: 1. ADT and class extensions. and applications in C++ . 6 Hours PART – B UNIT . B-trees. Formulabased representation. Linear representation. Applications.3 STACKS: The abstract data types. Properties and representation of binary trees.2000. Algorithms.Balaguruswamy. 2010 . Binary tree traversal the ADT binary tree. Programming in C++ . Applications. Skip list presentation. 63 . McGraw Hill. Data structures. Hash table representation. 6 Hours UNIT-8 Search Trees: Binary search trees. Special matrices spare matrices. Formula-based representation.2 ARRAYS AND MATRICS: Arrays. 1995. 8 Hours UNIT . REFERENCE BOOKS: 1. TMH. TMH.4 Queues: The abstract data types. Linked representation. Linked Linked representation. 2. 2.Balaguruswamy. Leftist trees. 6 Hours UNIT . Binary trees. Derived classes and inheritance. Object Oriented Programming in C++ . Applications. 7 Hours UNIT . Common binary tree operations.Sartaj Sahni. Derived classed and inheritance. Heaps. Binary Coding. Binary representation and Circuit Elements. 6 Hours 64 . 7 Hours UNIT 3 Number Basics: Unsigned and Signed Integers. Fixed and Floating-point Numbers. Interfacing with memory. I/O software. Counters. Models. Interconnection and Signal Integrity. Real-World Circuits. Sequential Datapaths and Control. Instruction and Data. Verification of Combinational Circuits. 6 Hours PART – B UNIT 5 Memories: Concepts. 6 Hours UNIT 7 I/O interfacing: I/O devices. Serial Transmission. of Lecture Hours /week Total no. 6 Hours UNIT 4 Sequential Basics: Storage elements. I/O controllers. of Lecture Hours : 10EC666 : 04 : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT 1 Introduction and Methodology: Digital Systems and Embedded Systems. Memory Types. Packaging and Circuit Boards. Clocked Synchronous Timing Methodology. Combinational Components and Circuits.DIGITAL SYSTEMS DESIGN USING VERILOG Subject Code No. Error Detection and Correction. Parallel Buses. Implementation Fabrics: ICs. Design Methodology. PLDs. 7 Hours UNIT 2 Combinational Basics: Boolean Functions and Boolean Algebra. 7 Hours UNIT 6 Processor Basics: Embedded Computer Organization. RS 485 and USB standards – IEEE 488 standard – ISO –OSI model for series bus – introduction to bus protocols of MOD bus and CAN bus. Peter J. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT 1 Review of Digital Instrumentation: Representation of analog signals in the digital domain – Review of quantization in amplifier and time areas. 12 Hours UNIT 4 Cluster of Instruments in System: Interfacing of external instruments to a PC – RS 232C. sample and hold. Design Methodology: Design flow. sampling theorem. of Lecture Hrs/Week : 04 Total no. RS – 422. Concept of universal DAQ card – Use of timercounter and analog outputs on the universal DAQ card. VIRTUAL INSTRUMENTATION Subject Code : 10EC667 No. “Digital Design: An Embedded Ssytems Approach Using VERILOG”. ADC and DAC. 7 Hours TEXT BOOK: 1. Design optimization. Verification of accelerators. Ashenden. of Lecture Hrs. Elesvier. case study. 8 Hours UNIT 2 & 3 Fundamentals of Virtual Instrumentation: Concept of Virtual Instrumentation – PC based data acquisition – Typical on board DAQ card – Resolution and sampling frequency – Multiplexing of analog inputs – Singleended and differential inputs – Different strategies for sampling of multi channel analog inputs. 8 Hours 65 . 2010.UNIT 8 Accelerators: Concepts. Design for test. REFERENCE BOOKS: 1. Robert H. TMH. Bishop. “ Measrement Systems – Application and Design”. 5th Edn. 2. LABVIEW”. 2000. 1994. Ernest O. “Learning with Lab-View” Preticee Hall. Gupta and J P Gupta.PART – B UNIT 5 & 6 Graphical Programming Environment in VI: Concepts of graphical programming – Lab-view software – Concept of VIs and sub VIs – Display types – Digital – Analog – Chart – Oscilloscope types – Loops – Case and sequence structures – Types of data – Arrays – Formulate nodes – Local and Global variables – String and file I/O. Sanjay Gupta. “Virtual Instrumentation. 12 Hours UNIT 7 & 8 Analysis Tools and Simple Application in VI: Fourier transform – Power spectrum – Correlation – Windowing and filtering tools – Simple temperature indicator – ON/OFF controller – PID controller – CRO emulation – Simulation of a simple second order system – Generation of HTML page. 66 .”PC Interfacing for Data Acquisition and Process Control”. Peter W Gofton . 2009. TMH. 2. Sybes International. “Understanding Serial Communication”. New Delhi. 2007. 3. 12 Hours TEXT BOOKS: 1. Doeblin and Dhanesh N Manik. 2003. S. Instrument Society of America. Gigabit Ethernet. Connecting devices. OSI Model.11 7 Hours PART – B UNIT . DSL. Dial up modem. Multicast Routing protocols. Backbone and Virtual LANs. Standard Ethernet. 6 Hours UNIT . Noiseless channels and noisy channels.6 Network Layer.2 DATA LINK CONTROL: Framing. Virtual LANs 7 Hours UNIT . of Lecture Hrs. Flow and error control. Ipv4 addresses. Layers in OSI model.VII SEMESTER COMPUTER COMMUNICATION NETWORKS Subject Code : 10EC71 No. TCP?IP Suite. Back bone Networks. IEEE standards. HDLC. Logical addressing.5 Connecting LANs. Ipv6 addresses. Ethernet.3 MULTIPLE ACCESSES: Channelisation. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . Telephone and cable networks for data transmission. Cable TV for data transmission.4 Wired LAN. 6 Hours UNIT . Ipv4 and Ipv6 Transition from Ipv4 to Ipv6. 6 Hours 67 . Fast Ethernet. Changes in the standards. Wireless LAN IEEE 802.1 Layered tasks. 7 Hours UNIT . 6 Hours UNIT . Random access. Forwarding. Addressing.7 Delivery. Protocols. Unicast Routing Protocols. Controlled access. of Lecture Hrs/Week : 04 Total no. Telephone networks. James F. comparison of photo detectors. single mode fiber. Inter model dispersion. UDP. cutoff wave length. cylindrical fiber (no derivations in article 2. Computer Networks. 6 Hours UNIT . TCP. Response time. REFERENCE BOOKS: 1. 2nd Edition. Intra model dispersion. Photo detectors. 4th Ed. Historical development. Wayne Tomasi: Pearson education 2007. and applications of optical fiber communication. photonic crystal. 7 Hours TEXT BOOK: 1. advantages. general system. Ross: Pearson education.UNIT .3 OPTICAL SOURCES AND DETECTORS: Introduction. bending loss.8 Transport layer Process to process Delivery. Introduction to Data communication and Networking. mode filed diameter. dispersion. double hetero junction structure. Resolution. 7 Hours UNIT . : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . optical fiber waveguides. absorption. LED’s. 6 Hours 68 . Data Communication and Networking. of Lecture Hrs/Week : 04 Total no.1 OVERVIEW OF OPTICAL FIBER COMMUNICATION: Introduction. fiber optic cables specialty fibers. of Lecture Hrs. Domain name system. Photo detector noise. TMH 2006. Attenuation. LASER diodes. OPTICAL FIBER COMMUNICATION Subject Code : 10EC72 No. 2. Kurose. scattering losses.2 TRANSMISSION CHARACTERISTICS OF OPTICAL FIBERS: Introduction. Ray theory. Photo diodes. 2003. disadvantages.4. Optical Fibers: fiber materials. Keith W.4). B Forouzan. link power budget. operation. Senior.6 ANALOG AND DIGITAL LINKS: Analog links – Introduction. variable optical attenuators. single mode fiber joints. RF over fiber. 7 Hours UNIT . Optical Interfaces. active optical components. fiber splices. 6 Hours UNIT . tunable optical fibers.4 FIBER COUPLERS AND CONNECTORS: Introduction. burst mode receiver. dynamic gain equalizers. Fiber Optic Communication . quantum limit. WDM standards. fiber connectors and fiber couplers. resistive budget. Optical Receiver Operation. multiplexer. microwave photonics. Isolators and circulators. fiber alignment and joint loss. High – speed light – waveguides. coherent detection. semiconductor optical amplifiers. System considerations. direct thin film filters. Mach-Zehender interferometer. Gerd Keiser. 69 . optical drop multiplexers. MGH. Pearson Education. 6 Hours PART – B UNIT . multichannel transmission techniques. CNR. 2007.Joseph C Palais: 4th Edition. 8 Hours UNIT . SONET/SDH rings. nodal noise and chirping. basic applications and types. Digital links – Introduction. REFERENCE BOOK: 1. 2. 4th Ed. OPTICAL NETWORKS: Introduction. receiver sensitivity. overview of analog links. Pearson Education. EDFA.8 Optical Amplifiers and Networks – optical amplifiers. eye diagrams. 3rd Impression. MEMS technology. overview of WDM operation principles. Power penalties. Analog receivers. chromatic dispersion compensators. SONET / SDH. Radio over fiber links.. key link parameters. "Optical Fiber Communications". point–to–point links.7 WDM CONCEPTS AND COMPONENTS: WDM concepts.UNIT . tunable light sources.5 OPTICAL RECEIVER: Introduction. "Optical Fiber Communication”. 6 Hours TEXT BOOKS: 1. short wave length band. 2008. John M. polarization controllers. transmission distance for single mode fibers. of Lecture Hrs. 6 Hours UNIT . : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . IGBT’s. Gate characteristics. 6 Hours UNIT . Single phase controllers with restive loads and Inductive loads. 6 Hours 70 .3 INTRODUCTION TO THYRISTORS: Principle of operation states anode-cathode characteristics. 7 Hours UNIT . Turn-on Methods. Control characteristics. Thyristor firing circuits.6 AC VOLTAGE CONTROLLERS: Introduction. class A and class B types.1 Introduction. 1 φ semi converters (all converters with R & RL load). numerical problems. Principles of phase control. di / dt and dv / dt protection. self commutation. 1φ fully controlled converters. Types of power electronics circuits. Switching characteristics. Applications of power electronics. numerical problems. external pulse commutation. of Lecture Hrs/Week : 04 Total no.2 POWER TRANSISTOR: Power BJT’s. AC line commutation. natural and forced commutation. Two transistor model. auxiliary commutation. 7 Hours PART – B UNIT . Gate trigger circuits. Duel converters. Principles of on and off control. Principles of phase controlled converter operation. Complementary commutation.POWER ELECTRONICS Subject Code : 10EC73 No. Switching characteristics. Peripheral effects. Power MOSFET’s. 7 Hours UNIT .5 Thyristor turn off methods. Power semiconductor devices. Switching limits.4 CONTROLLED RECTIFIERS: Introduction. Base derive control. Isolation of gate and base drives. Dynamic Turn-on and turn-off characteristics. Gate drive. of Lecture Hrs. “Power Electronics” . The Core Level. D. 1φ bridge inverter. 2006. Anandamurhty. Singh and Kanchandani K. current source invertors. Variable DC link inverter. Rashid 3rd edition. Pearson/Sanguine Pub. Addresses. REFERENCE BOOKS: 1. Switch mode regulators – buck. voltage control of 1φ invertors. Representing Information. 7 Hours TEXT BOOKS: 1.7 DC CHOPPERS: Introduction. 3. 2010. Step down chopper with RL loads. Chopper classification. Hart.8 INVERTORS: Introduction. L Umanand. Principles of operation. 2. Embedded Design and Development Process. H. 5 Hours UNIT 2: The Hardware Side: An Introduction. 2007. Philosophy. Daniel W.B. “Power Electronics. “Power Electronics” .M. “Power Electronics”. 2.S. Essentials and Applications”. 6 Hours UNIT . TMH publisher. McGraw Hill. Understanding Numbers. EMBEDED SYSTEM DESIGN Subject Code : 10EC74 No. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT 1: Introduction to Embedded System: Introducing Embedded Systems. John Wiley India Pvt. Ltd. Principles of step down and step up choppers. V Nattarasu and R. PHI / Pearson publisher 2004. Embedded Systems.M. “Power Electronics” . Performance parameters. boost and buck – boost regulators. 2009. Registers-A 71 . of Lecture Hrs/Week : 04 Total no. 2nd Ed. Instructions.UNIT . Response Time. The CPU is a resource. Time. Dynamic Memory Allocation. Tricks of the Trade. Partitioning and Decomposing a System. SRAM Design. Basic Concepts of Caching. etc. The real time operating system (RTOS). Functional Design. Identifying the Requirements. A General Memory Interface. Thoughts on Performance Optimization. Instructions in Detail. Formulating the Requirements Specification. OS architecture. A Memory Interface in Detail. Embedded Systems-An Instruction Set View. Finite State MachinesA Theoretical Model. Designing a Cache System. Chip Organization. 12 Hours UNIT 7 & 8: Performance Analysis and Optimization: Performance or Efficiency Measures. ROM Overview. Caches and Performance. 8 Hours UNIT 3: Memories and the Memory Subsystem: Classifying Memory. memory management revisited. Time Loading. System Specifications versus System Requirements. The operating System. Hardware Accelerators. Evaluating Performance. Prototyping. Analyzing code. Other Considerations. 7 Hours UNIT 4: Embedded Systems Design and Development : System Design and Development. Problem Solving-Five Steps to Design. The Memory Map. Terminology. The methodology. The Design Process. Sharing Resources. Dynamic RAM Overview. Programs and Processes. Archiving the Project. The State Diagram. Functional Model versus Architectural Model. DRAM Memory Interface. The System Design Specification. Complexity Analysis. Tasks and Task control blocks. 12 Hours 72 . Memory Subsystem Architecture. Embedded Systems-A Register View. Life-cycle Models. DRAM Design. – A more detailed look. Performance Optimization. 6 Hours PART – B UNIT 5 & 6: Real-Time Kernels and Operating Systems: Tasks and Things. Register View of a Microprocessor The Hardware Side: Storage Elements and Finite-State Machines (2 hour) The concepts of State and Time. Threads – Lightweight and heavyweight.First Look. Architectural Design. Static RAM Overview. Memory Loading. Foreground/Background Systems. 4. REFERENCE BOOKS: 1. Dreamtech Software Team. 2008. Embedded Systems: Architecture and Programming. 8. John Wiley India Pvt. 1. Ltd. VLSI LAB Subject Code : 10ECL77 No. 7. 5. 2005. James K. 3. Embedded Systems – A contemporary Design Tool. Raj Kamal. Tammy Noergaard. MS. Programming for Embedded Systems. Embedded Systems Architecture – A Comprehensive Guide for Engineers and Programmers. T Serial & Parallel adder 4-bit counter [Synchronous and Asynchronous counter] Successive approximation register [SAR] * An appropriate constraint should be given 73 . 2008. of Practical Hrs/Week : 03 Total no. Elsevier Publication. 3. Peckol. An inverter A Buffer Transmission Gate Basic/universal gates Flip flop -RS. observe the waveform and synthesize the code with technological library with given Constraints*.TEXT BOOK: 1. Do the initial timing verification with gate level simulation. JK. TMH. 6. Ltd. 2008. D. John Weily India Pvt. 2. Write Verilog Code for the following circuits and their Test Bench for verification. 2. : 42 IA Marks Exam Hours Exam Marks : 25 : 03 : 50 (Wherever necessary Cadence/Synopsis/Menta Graphics tools must be used) PART .A DIGITAL DESIGN ASIC-DIGITAL DESIGN FLOW 1. of Practical Hrs. completing the design flow mentioned below: a. ERC c. Draw the Layout and verify the DRC. Design a 4 bit R-2R based DAC for the given specification and completing the design flow mentioned using given op-amp in the library**. Check for LVS d. Draw the Layout and verify the DRC. 4. a. Check for LVS d.B ANALOG DESIGN Analog Design Flow 1. Extract RC and back annotate the same and verify the Design e. Draw the schematic and verify the following 74 . Draw the schematic and verify the following i) DC Analysis ii) AC Analysis iii) Transient Analysis b. Design the following circuits with given specifications*. Design an Inverter with given specifications*. ERC c. ERC c. Draw the schematic and verify the following i) DC Analysis ii) Transient Analysis b. Extract RC and back annotate the same and verify the Design. Draw the Layout and verify the DRC.PART . i) A Single Stage differential amplifier ii) Common source and Common Drain amplifier 3. completing the design flow mentioned below: a. Check for LVS d. Power and Area to the given constraint*** 2. Draw the schematic and verify the following i) DC Analysis ii). Design an op-amp with given specification* using given differential amplifier Common source and Common Drain amplifier in library** and completing the design flow mentioned below: a. AC Analysis iii) Transient Analysis b. Verify & Optimize for Time. Extract RC and back annotate the same and verify the Design. Draw the Layout and verify the DRC. • • Static characteristics of SCR and DIAC. *** An appropriate constraint should be given POWER ELECTRONICS LAB Subject Code : 10ECL78 No. 75 . For the SAR based ADC mentioned in the figure below draw the mixed signal schematic and verify the functionality by completing ASIC Design FLOW. ** Applicable Library should be added & information should be given to the Designer. of Practical Hrs/Week: 03 Total no. of Practical Hrs. 5. [Specifications to GDS-II] * Appropriate specification should be given. Static characteristics of MOSFET and IGBT. : 42 IA Marks Exam Hours Exam Marks : 25 : 03 : 50 Any five converter circuits experiment from the below list must be simulated using the spice-simulator. Extract RC and back annotate the same and verify the Design.i) DC Analysis ii) AC Analysis iii) Transient Analysis b. Check for LVS d. ERC c. • • • • Controlled HWR and FWR using RC triggering circuit SCR turn off using i) LC circuit ii) Auxiliary Commutation UJT firing circuit for HWR and FWR circuits. Bus Architecture and Memory. Generation of firing signals for thyristors/ trials using digital circuits / microprocessor. Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT). • AC voltage controller using triac – diac combination. Note: Experiments to be conducted with isolation transformer and low voltage. of Lecture Hrs/Week : 04 Total no. Programmability and Program Execution. Commercial Digital Signal-processing Devices. • Single phase Fully Controlled Bridge Converter with R and R-L loads. • Voltage (Impulse) commutated chopper both constant frequency and variable frequency operations.1 INTRODUCTION TO DIGITAL SIGNAL PROCESSING: Introduction. A Digital Signal-Processing System. • Speed control of a separately exited DC motor. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . Address Generation Unit.2 ARCHITECTURES FOR PROGRAMMABLE DIGITAL SIGNALPROCESSORS: Introduction. 6 Hours UNIT .3 PROGRAMMABLE DIGITAL SIGNAL PROCESSORS: Introduction. Decimation and Interpolation. DSP ALGORITHMS AND ARCHITECTURE Subject Code : 10EC751 No. • Speed control of stepper motor. • Speed control of universal motor. DSP Computational Building Blocks. The Sampling Process. of Lecture Hrs. Data Addressing Capabilities. Linear Time-Invariant Systems. Digital Filters. 7 Hours UNIT . • Parallel / series inverter. Features for External Interfacing. Discrete Time Sequences. Data Addressing Modes of 76 . Basic Architectural Features. DSP Based Bio-telemetry Receiver. An Image Processing System. PHI/ 2002 2. Memory Interface. OnChip peripherals. Jervis B.TMS32OC54xx. REFERENCE BOOKS: 1.8 INTERFACING AND APPLICATIONS OF DSP PROCESSOR: Introduction. 2nd. External Bus Interfacing Signals.7 INTERFACING MEMORY AND PARALLEL I/O PERIPHERALS TO DSP DEVICES: Introduction. Interpolation and Decimation Filters (one example in each case).4 Detail Study of TMS320C54X & 54xx Instructions and Programming. “Digital Signal Processing”. Parallel I/O Interface. “Digital Signal Processors”.. A CODEC Interface Circuit. Programmed I/O. Pipeline Operation of TMS32OC54xx Processor. Overflow and Scaling. 7 Hours TEXT BOOK: 1. Program Control. 6 Hours UNIT . Bit-Reversed Index Generation & Implementation on the TMS32OC54xx. W Pearson-Education. Memory Space of TMS32OC54xx Processors. An FFT Algorithm for DFT Computation. 7 Hours UNIT . C. 2010 3. 7 Hours PART – B UNIT . FIR Filters.. Interrupts and I / O Direct Memory Access (DMA).6 IMPLEMENTATION OF FFT ALGORITHMS: Introduction. Interrupts of TMS32OC54XX Processors. Srinivasan. Digital Signal Processing: A practical approach. Ifeachor E. Memory Space Organization. B Venkataramani and M Bhaskar TMH. 2004. Peter Pirsch John Weily. The Q-notation. IIR Filters. Synchronous Serial Interface. 2008 77 . Thomson Learning. Avatar Singh and S.5 IMPLEMENTATION OF BASIC DSP ALGORITHMS: Introduction. “Architectures for Digital Signal Processing”. A Speech Processing System. 6 Hours UNIT . 6 Hours UNIT . electrostatic comb-drive and micromotor. of Lecture Hrs. Application areas. Processing of other materials: ceramics. : 10MS752 : 04 : 52 IA Marks Exam Hours Exam Marks : : : 25 03 100 PART – A UNIT . wafer-bonding. and systems. piezo-electric based inkjet printhead. active noise control in a helicopter cabin.2 MICRO AND SMART DEVICES AND SYSTEMS: PRINCIPLES AND MATERIALS: a) Definitions and salient features of sensors. Applications areas. Multi-disciplinary aspects. d) Systems: micro gas turbine. b) Sensors: silicon capacitive accelerometer. of Lecture Hrs. Emerging trends. 6 Hours UNIT . lithography. thin-film deposition. Commercial products. Micromachined transducers. etching (wet and dry). bonding based process flows. 7 Hours 78 . polymers and metals f. bulk. and metallization. magnetic micro relay. Evolution of micro-manufacturing. fiber-optic gyroscope and surface-acoustic-wave based wireless strain sensor. shapememory-alloy based actuator. b) What are microsystems? Feynman’s vision. piezo-resistive pressure sensor. Smart material processing: e. electro-thermal actuator. structures and systems.1 INTRODUCTION TO MICRO AND SMART SYSTEMS: a) What are smart-material systems? Evolution of smart materials. actuators. blood analyzer. portable clinical analyzer. b. Silicon wafer processing. Components of a smart system.3 MICROMANUFACTURING AND MATERIAL PROCESSING: a. Silicon micromachining: surface. c.MICRO AND SMART SYSTEMS TECHNOLOGY Subject Code No. Thick-film processing: d./ Week Total No. 7 Hours UNIT . conductometric gas sensor. moulding. c) Actuators: silicon micro-mirror arrays. Commercial products. thermal cycler for DNA amplification. flip-chip. Coupled electromechanics. Examples from smart systems and micromachined accelerometer or a thermal cycler. Capillary electro-phoresis. 7 Hours UNIT . c. 6 Hours UNIT . Electrostatics. operational amplifiers.6 ELECTRONICS. Residual stresses and stress gradients. stability. 6 Hours PART – B UNIT . PID controllers. transistors. MOSFET amplifiers. Electromagnetic actuation. Charge-measuring circuits. Transfer function.7 INTEGRATION AND PACKAGING OF MICROELECTRO MECHANICAL SYSTEMS: Integration of microelectronics and micro devices at wafer and chip levels. Coupled-domain simulations using Matlab.UNIT .4 MODELING: a. Elastic deformation and stress analysis of beams and plates. Basic fluids issues. Piezoelectric modeling. Commercial software. semiconductor diodes. Lowtemperature-cofired-ceramic (LTCC) multi-chip-module technology. Basic Op-Amp circuits. and model order reduction. Microelectronic packaging: wire and ball bonding.5 COMPUTER-AIDED SIMULATION AND DESIGN: Background to the finite element element method. Magnetostrictive actuators. Examples from microsystems. state-space modeling. 6 Hours UNIT .9 Mini-projects and class-demonstrations (not for Examination) 79 .8 CASE STUDIES: BEL pressure sensor. Heat transfer issues. Piezoresistive modeling. b. Thermal loading. 7 Hours UNIT . and active vibration control of a beam. CIRCUITS AND CONTROL: Carrier concentrations. Scaling issues. Microsystem packaging examples. Ananth Suresh. use of neural networks. Design and Development Methodologies.John Wiley Publications. of Lecture Hrs. J. Gopalakrishnan. Prof. ISBN 0-444-51616-6.Bhat. 5. Analysis and Design Principles of MEMS Devices. 2. Tata Mc-Graw-Hill. 6 Hours 80 .1 Introduction. photographs and movie clips of processing machinery and working devices. neural net architectures. A CD-supplement with Matlab codes. Animations of working principles. A. Gopalakrishna. Prof. K. Smart Material Systems and MEMS: V. history. Boston.K. 2.Vinoy. TMH 2007 ARTIFICIAL NEURAL NETWORKS Subject Code : 10EC753 No. Minhang Bao. Wiley.. USA. (ii) thermal-cycler and (iii) active control of a cantilever beam. S. Tai-Ran Tsu. MEMS. neural learning. MEMS & Microsystems: Design and Manufacture. K.a) CAD lab (coupled field simulation of electrostatic-elastic actuation with fluid effect) b) BEL pressure sensor c) Thermal-cycler for PCR d) Active control of a cantilever beam TEXT BOOKS AND A CD-SUPPLEMENT: 1. Laboratory hardware kits for (i) BEL pressure sensor. Vinoy. ISBN 0-7923-7246-8. S. Kluwer Academic Publishers. 4. Prof.J. S.Aatre. 2001. 6. “Micro and Smart Systems” by Dr. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . of Lecture Hrs/Week : 04 Total no.N. Senturia. Microsystems Design.K. structure and function of single neuron. D. Amsterdam. Varadan. REFERENCE BOOKS: 1. 3. Prof. The Netherlands. Elsevier..Nitaigour Premchand Mahalik. process flows and processing techniques. K. distance based learning.7 Associative models. toplogically organized networks. perceptions training algorithm. Penram. adaptive multilayer networks. 2. brain state networks. 81 . MGH. multilevel discrimination. polynomial regularization. 2003. application. 7 Hours UNIT . Zurada. R. adaptive resonance theorem.2 Supervised learning. mandaline. 7 Hours UNIT .3 Multiclass networks-I. setting parameter values.6 Learning vector quantizing. 6 Hours UNIT .. Mohan. Kishan Mehrotra. hop field networks. J. Schalkoff. neo-cognition. 1999. simulated annealing. Introduction to Artificial Neural Systems. linear separability. single layer networks. Artificial Neural Networks. winner take all networks. evolutionary computation. 1997. random search. Haykins.UNIT .4 Accelerating learning process. unsupervised learning. 6 Hours UNIT . counter propagation networks. guarantees of success. back propagation. theoretical results.5 Prediction networks. networks.8 Optimization using hop filed networks. 7 Hours UNIT . hetero associations. 7 Hours TEXT BOOK: 1. C. Neural Networks. 6 Hours PART – B UNIT . radial basis functions. Boltzmann machines. Elements of Artificial Neural Networks. modifications. Pearson Edu. 1997. preliminaries. Sanjay Ranka. REFERENCE BOOKS: 1. perceptions. 3. Jaico. 12 Hours UNIT – 3&4 A QUICK TOUR OF VLSI DESIGN AUTOMATION TOOLS: Data structures and Basic Algorithms. Pearson Edition 1999. 14 Hours UNIT – 7&8 SIMULATION-LOGIC SYNTHESIS: Verification-High level synthesis Compaction. 2. 82 . “Algorithms for VLSI Design Automation”. An embedded Software Primer by David E Simon. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT – 1&2 INTRODUCTION TO VLSI METHODOLOGIES: VLSI Physical Design Automation . Embedded Systems : Architecture. Shervani. and Design. H. Physical Design Automation of FPGAs. Algorithmic Graph theory and computational complexity. floor planning and pin assignment. 12 Hours REFERENCE BOOKS: 1. N. MCMS-VHDLVerilog-Implementation of Simple circuits using VHDL and Verilog. placement. 2008. of Lecture Hrs. “Algorithms for VLSI Physical Design Automation”. 1999.Fabrication process and its impact on Physical Design. John Wikey & Sons. Tractable and Intractable problems. Programming. 1998. 2002. S.Design and Fabrication of VLSI Devices . Frank Vahid. Gerez. of Lecture Hrs/Week : 04 Total no. 2. REFERENCE BOOKS: 1. 3. 14 Hours PART – B UNIT – 5&6 GENERAL PURPOSE METHODS FOR COMBINATIONAL OPTIMIZATION: partitioning. A.CAD FOR VLSI Subject Code : 10EC754 No. 2nd Edn. routing. Raj Kamal. Embedded System Design – A certified Hardware / Software Introduction. TMH. Embedded Hardware Units and devices in a system. thread and device driver concept. PCI-X and advanced buses. of Lecture Hrs.2 8051 AND ADVANCED PROCESSOR ARCHITECTURE: 8051 Architecture.. Skills required for an embedded system designer. Instruction level parallelism. Introduction to advanced architecture Processor and memory architecture. Examples of embedded systems. Formalism of system design. Sophisticated interfacing features in device ports. Embedded system-on-chip (SoC) and use of VLSI circuits design technology (A). Memory selection. Wireless communication devices. PCI. Design process in embedded system. Timer and counting devices. Processor embedded into a system (A). Wireless and mobile system protocols. of Lecture Hrs/Week : 04 Total no.1 INTRODUCTION TO THE EMBEDDED SYSTEMS: An embedded System. 6 Hours UNIT . Design process and design examples. Complex systems design and processors. Classification of embedded systems.APPLIED EMBEDDED SYSTEM DESIGN Subject Code : 10EC755 No. Interrupt servicing (handling) mechanism Multiple interrupts. Processor selection. 5 Hours UNIT . Interrupt service routine.4 DEVICE DRIVERS AND INTERRUPTS SERVICING MECHANISM: Port or device access without interrupt servicing mechanism. Embedded software in a system. 5 Hours UNIT . Performance metrics Memory types and addresses. Real time clocks Parallel bus device protocols – parallel communication network using the ISA.3 DEVICES AND COMMUNICATION BUSES FOR DEVICES NETWORK: Devices and Communication buses for Networks. Interrupt sources. Context and the periods 83 . : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . Watchdog timers. Real world interfacing. Serial communication devices Parallel port devices. Deadline 84 . Clear cut distinction between Functions.8 REAL TIME OPERATING SYSTEMS: Operating system service. Multiple threads in an applications. Mailboxes. modifiers. C++ AND JAVA: Software programming in assembly language (ALP) and in high level language ‘C’. Data flow graph models.6 PROGRAM MODELING CONCEPTS IN SINGLE AND MULTIPROCESSOR SYSTEMS SOFTWARE – DEVELOPMENT PROCESS: Program models. Timer functions. Embedded programming in Java. Event functions. statements. State machine programming models for event controlled programs. 5 Hours UNIT .. data structures. UML modeling. Process management. Device driver programming.for context-switching. Memory management. Response Times. Modeling of multiprocessor systems. Latency. ‘C’ programming elements: header and source files and preprocessor directives. Optimisation of Memory needs. RTOS Task Scheduling Models. ISRs and Tasks by their Characteristics. Inter process communications Signals. Semaphores. Sockets. file and IO subsystems management Interrupt routines in RTOS environment and handling of interrupt source calls by RTOS Introduction to Real time Operating System. 8 Hours PART – B UNIT . Task Tasks and states. 8 Hours UNIT . Shared data. Objected oriented programming. Tasks and data. Device. Remote procedure calls (RPCs). 5 Hours UNIT . program elements : macros and functions.7 REAL TIME OPERATING SYSTEMS – 1: INTER PROCESS COMMUNICATION AND SYNCHRONISATION OF PROCESSES. Concept of semaphores. Parallel port device drivers in a system Serial port device drivers in a system. Message queues. interrupt latency and Deadline Classification of processors interrupt service mechanism from context saving angle Direct memory access. Timer devices and devices interrupts. Pipes.5 PROGRAMMING CONCEPTS AND EMBEDDED PROGRAMMING IN C. Basic design using a Real Time Operating System. loops and pointers. Program elements : data types. TASK AND THREADS: Multiple processes in an application. C. Stepper Motor c. SPICE examples. OS security issues. Fundamentals of Microelectronics.. International Veersion. Lab Work: (Part of the theory class) 1. Dynamic Logic Circuits. Pearson Edition 1999. TMH. John Wiley India Pvt. Oxford University Press. Logic Gate Circuits. Write C prog to initialize the I/O ports and interface the following: a. Tata McGraw-Hill. Sundaram Natarajan. An embedded Software Primer by David E Simon. Microelectronics – Analysis and Design. Types of Real Time Operating Systems RTOSµC/OS-II. IEEE Standard POSIX 1003. John Wikey & Sons.1 b Functions for Standardisation of RTOS an Inter Process Communication Functions. LED / LCD Display b. 5th Edition. 10 Hours TEXT BOOK: 1. 2. Elevator DIGITAL CMOS CIRCUITS: Overview. 2007. Ltd. Introduction to Embedded System Design – A certified Hardware / Software by Bank Vahid. Design and performance analysis of CMSO inverter. An embedded Software Primer by David E Simon. 2008. 2. Pearson Edition 1999. 2009. Behzad Razavi. Smith. TEXT BOOK: 1. 2002. REFERENCE BOOKS: 1. Microelectronic Circuits. RTOS Vx Works. Adel Sedra and K.as Performance Metric. REFERENCE BOOKS: 1. 2008 (latest edition). 85 . Pass-transistor logic. Embedded System Architecture & Programming by Raj Kamal. 2. of Lecture Hrs. 7 Hours UNIT .2 TIME-DOMAIN METHODS FOR SPEECH PROCESSING: time dependent processing of speech. silence detection. short-time energy and average magnitude. short-time autocorrelation function.3 Speech vs.4 Brief Applications of temporal processing of speech signals in synthesis. pitch period estimation using parallel processing approach. enhancement. stops and affricates. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT .1 PRODUCTION AND CLASSIFICATION OF SPEECH SOUNDS: Introduction. sampling rates in time and frequency. 6 Hours 86 .SPEECH PROCESSING Subject Code : 10EC756 No. 7 Hours PART – B UNIT . definitions and properties: Fourier transforms interpretation and linear filter interpretation. 6 Hours UNIT . 7 Hours UNIT . nasals. of Lecture Hrs/Week : 04 Total no.5 FREQUENCY DOMAIN METHODS FOR SPEECH PROCESSING: Introduction.6 Filter bank summation and overlap add methods for short-time synthesis of speech. short-time average zero crossing rate. 6 Hours UNIT . Acoustic phonetics: vowels. semivowels. fricatives. mechanism of speech production. diphthongs. sinusoidal and harmonic plus noise method of analysis/synthesis. hearing applications and clear speech. const Qualifier. Digital Processing of Speech Signals. Variables. Pearson Education Asia. the bool type. Pointer Type. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . Quatieri. the complex cepstrum of speech. AN OVERVIEW: Getting started. String Types. 6 Hours UNIT . Reference Types.2 THE BASIC LANGUAGE: Literal Constant. Morgan. The Built-In Array Data Type. F. of Lecture Hrs. An array. Discrete Time Speech Signal Processing. REFERENCE BOOKS: 1. homomorphic vocoder. L. of Lecture Hrs/Week : 04 Total no. R. Speech and Audio Signal Processing: Processing and Perception of Speech and Music. Rabiner and R. 2004. Gold and N.8 APPLICATIONS OF SPEECH PROCESSING: Brief applications of speech processing in voice response systems hearing aid design and recognition systems. Schafer. 2004. 7 Hours UNIT .7 HOMOMORPHIC SPEECH PROCESSING: Introduction. John Wiley India Pvt. W. Preprocessor Directives.1 C++. 7 Hours TEXT BOOK: 1. 6 Hours 87 . Ltd. ELECTIVE-III (GROUP-C) PROGRAMMING IN C++ Subject Code : 10EC761 No. B. An Exception – based Design. An Object – based Design. Dynamic Memory Allocation and Pointers.UNIT . Enumeration types. 2004. Pearson Education Asia. The vector container type. Array types. the C++ program. An Object-Oriented Design. 2. T. homomorphic system for convolution. C++ Program Design: An Introduction to Programming and Object. switch. Operators ++ and --. Statements: if.6 CLASSES: Definition. C++ Primer.8 Multiple Inheritances. 2004. 6 Hours TEXT BOOK: 1. Assignment operators. Galgotia Publications. TMH publication. Class Initailization. Exception Specification and Exceptions and Design Issues. 2004. while. 2000. Class Object Arrays and Vectors.7 Overload Operators. goto. break. Argument passing.5 EXCEPTION HANDLING: Throwing an Exception. R.UNIT .3 OPERATORS: Arithmetic Operators.4 FUNCTIONS: Prototype. Bitwise operator. The class destructor. B. for Loop. 2. Lippman & J. Lajoie. Lafore. 3rd Edn. 88 . Increment and Decrement operator. REFERENCE BOOKS: 1. Class Objects. Addison Wesley. Recursion and linear function. Cohoon and Davidson. S. private & protected inheritance. 6 Hours PART – B UNIT . 7 Hours UNIT . Class scope under Inheritance. 7 Hours UNIT . Class constructior. bitset operations. 3rd Edition. public. 6 Hours UNIT . Object Oriented Programming using C++. Operators new and delete. Equality. 7 Hours UNIT . The conditional Operator. continue statements. Relational and Logical operators. Catching an exception.Oriented Design. 4 LANGUAGES FOR REAL-TIME APPLICATIONS: Introduction. Examples.5 & 6 OPERATING SYSTEMS: Introduction. Data transfer techniques.2 CONCEPTS OF COMPUTER CONTROL: Introduction. Classification of Programs. Loop control. Communications. General purpose computer. Interrupts and Device handling. Co routines. RTS Definition. Overview of real-time languages.1 INTRODUCTION TO REAL-TIME SYSTEMS: Historical background.3 COMPUTER HARDWARE REQUIREMENTS FOR RTS: Introduction. Resource control. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . 7 Hours UNIT . Concurrency. Time constraints. Minimum OS kernel. Compilation. 6 Hours UNIT . 6 Hours UNIT . Distributed system. 7 Hours PART – B UNIT . Declaration and Initialization of Variables and Constants. Syntax layout and readability. Low-level facilities. Real-time support. Task management. Mutual exclusion. 14 Hours 89 . Process-related Interfaces. Real-time multi-tasking OS. Benefits of computer control systems. Exception Handling. Classification of Real-time Systems. Scheduler and real-time clock interrupt handles. Data transfer. Centralised computer control. Modularity and Variables. Code sharing. Data types. Priority Structures. Human-computer interface. Task co-operation and communication. Memory Management. Control Structure. Sequence Control. Supervisory control. Standard Interface. Specialized processors. Scheduling strategies. of Lecture Hrs/Week : 04 Total no. of Lecture Hrs. Liveness.REAL-TIME SYSTEMS Subject Code : 10EC762 No. Single chip microcontroller. Real-Time Systems Design and Analysis. Pearson Education. Foreground/background. 2006. Preliminary design.Time Computer Control. Multi-tasking approach. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT .2 Image Sensing and Acquisition. Real-Time Systems Development. Linear and Nonlinear Operations.UNIT . Specification documentation. Monitors. 2005. Yourdon Methodology. Raj Kamal. Mutual exclusion. 2. Requirement definition for Drying Oven. REFERENCE BOOKS: 1. 2nd Edn. Real . Some Basic Relationships between Pixels. 6 Hours UNIT . Image Sampling and Quantization. Single-program approach.8 RTS DEVELOPMENT METHODOLOGIES: Introduction. elements of Visual Perception.7 DESIGN OF RTSS – GENERAL INTRODUCTION: Introduction. 6 Hours UNIT . A. Tata Mc Graw Hill. Rob Williams. second edition. 6 Hours 90 .An Introduction. 2005. India. Elsevier. 3. IMAGE PROCESSING Subject Code : 10EC763 No. Ward and Mellor Method. 6 Hours TEXT BOOKS: 1. Hately and Pirbhai Method. of Lecture Hrs/Week : 04 Total no. Embedded Systems. Stuart Bennet. of Lecture Hrs. Phillip. fundamental Steps in Digital Image Processing. Components of an Image processing system. 2005. Laplante.1 DIGITAL IMAGE FUNDAMENTALS: What is Digital Image Processing. PHI. .8 Color Fundamentals. Only-Spatial Filtering Periodic Noise Reduction by Frequency Domain Filtering. KL transform. PHI. “Fundamentals of Digital Image Processing”.6 Basics of Spatial Filtering Image enhancement in the Frequency Domain filters. Chanda and D. noise models.5 IMAGE ENHANCEMENT: Image Enhancement in Spatial domain. Woods. 7 Hours UNIT . Dutta Majumdar. B. etl . properties of unitary transforms. Some Basic Gray Level Trans -formations. Linear Position-Invariant Degradations. Jain. Hadamard transform. homomorphic filtering. 6 Hours UNIT . sine transform. minimum mean square error (Weiner) Filtering. TMH . 7 Hours UNIT . Pseudo color Image Processing. Sharpening Frequency Domain filters. 2003.4 Discrete cosine transform. Haar transform. Slant transform. Richard E. inverse filtering. Rafael C.3 IMAGE TRANSFORMS: Two-dimensional orthogonal & unitary transforms. REFERENCE BOOKS: 1. 2nd Edition 2010. two dimensional discrete Fourier transform. processing basics of full color image processing 6 Hours TEXT BOOK: 1. “Digital Image Processing”.UNIT . Restoration in the Presence of Noise. 2001. Color Models.7 Model of image degradation/restoration process. Smoothing Frequency Domain filters. “Digital Image Processing and Analysis”. Pearson Education. Enhancement Using Arithmetic/Logic Operations. 7 Hours PART – B UNIT . 2. 91 . Histogram Processing.Gonzalez. 7 Hours UNIT . Anil K. Introduction. of Lecture Hrs/Week : 04 Total no. 6 Hours UNIT . 6 Hours 92 . Modulations & Alphabet Soup. Transmission lines in more detail. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . Band Width Estimation Techniques. Risetime.3 A REVIEW OF MOS DEVICE PHYSICS: Introduction.1 OVERVIEW OF WIRELESS PRINCIPLES: A brief history of wireless systems. 4 Hours UNIT .RADIO FREQUENCY INTEGRATED CIRCUITS Subject Code : 10EC764 No. Transformers. Inductors. Interconnect options at high frequency. The method of short circuit time constant. artificial lines. Interconnect at radio frequencies: Skin effect.4 THE SMITH CHART AND S-PARAMETERS: Introduction. Propagation. FETs. Behavior of Finite – length transmission lines. operation in weak inversion (sub threshold). Other RLC networks. The method of open – circuit time constant. Noncellular wireless applications. S-parameters. Capacitors. summary of transmission line equations. MOSFET physics. 3 Hours DISTRIBUTED SYSTEMS: Introduction. Link between lumped and distributed regimes driving-point impedance of iterated structures. Delay and bandwidth. The long – channels approximation. 4 Hours UNIT . RLC Networks as impedance Transformers. The smith chart. MOS device physics in the short – channel regime. Series RLC Networks. Other effects. A little history. of Lecture Hrs. Parallel RLC Tank.2 CHARACTERISTICS OF PASSIVE IC COMPONENTS: Introduction. Shannon. resisters. 3 Hours PASSIVE RLC NETWORKS: Introduction. Design summery. Derivation of intrinsic MOSFET two-port noise parameters. Class D amplifiers. RF power amplifiers.5 HIGH FREQUENCY AMPLIFIER DESIGN: Introduction. 2nd edition Cambridge. Shot noise. Thermal noise. Typical noise performance. AB.port noise theory.6 VOLTAGE REFERENCES AND BIASING: Introduction. Cascaded amplifiers. Spurious – free Dynamic range. The design of CMOS radio-frequency integrated circuit. Diodes and bipolar transistors in CMOS technology. Class A. general considerations. 2004. Power-constrained noise optimization. 7 Hours UNIT . Diode ring mixers. Flicker noise.7 LOW NOISE AMPLIFIER DESIGN: Introduction. Thomas H. linearity and large signal performance. Design of Analog CMOS integrated circuit. Introduction. Bandgap voltage reference. Modulation of power amplifiers. Noise: Introduction. additional design considerations. Bandwidth Enhancement with fT Doublers. B and C power amplifier. Design examples. Nonlinear systems as linear mixers. Zeros as bandwidth Enhancers. Lee. 7 Hours UNIT . Mixers: Introduction. Behzad Razavi. Examples of noise calculations. Neutralization and unilateralization. 93 . REFERENCE BOOK: 1. 2005. RF PA design examples. AM – PM conversion.8 Multiplier – based mixers.PART – B UNIT . 7 Hours TEXT BOOK: 1. A handy rule of thumb. 6 Hours UNIT . Sub sampling mixers. Constant gm bias. The shunt –series amplifier. Class E amplifiers Class F amplifiers. Tuned amplifiers. Popcorn noise. Supply –independent bias circuits. Classical two. Review of diode behavior. LNA topologies: Power match versus noise match. summary of PA characteristics. Tata Mc Graw Hill. Mixer fundamental. 1 CONTINUOUS WAVELET TRANSFORM: Introduction. Digital filtering interpolation (i) Decomposition filters. (i) Bases for the approximations subspaces and Harr scaling function. the CWT as an operator. of Lecture Hrs. (i) Daubechies D4 scaling function and wavelet. (ii) Basis for the detail subspace (iii) Direct sum decomposition. 7 Hours UNIT . a wavelet basis for MRA. C-T wavelets. (ii) Example of approximating vectors in nested subspaces of an infinite dimensional linear vector space. (ii) Bases for detail subspaces and Haar wavelet. (i) Two scale relations for (t). Formal definition of an MRA.3 MRA. (i) example of approximating vectors in nested subspaces of a finite dimensional liner vector space. (iii) Basis functions for DTWT. 6 Hours 94 . (ii) reconstruction.4 EXAMPLES OF WAVELETS: Examples of orthogonal basis generating wavelets. Approximation of vectors in nested linear vector spaces. Example MRA. Constant Q-Factor Filtering Interpolation and time frequency resolution. (ii) band limited wavelets. 7 Hours UNIT . of Lecture Hrs/Week : 04 Total no. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . Definition of CWT.WEVELET TRANSFORMS Subject Code : 10EC765 No. Interpreting orthonormal MRAs for Discrete time MRA. (ii) Implication of dilation equation and orthogonality. ORTHO NORMAL WAVELETS AND THEIR RELATIONSHIP TO FILTER BANKS: Introduction.2 INTRODUCTION TO DISCRETE WAVELET TRANSFORM AND ORTHOGONAL WAVELET DECOMPOSITION: Introduction. 6 Hours UNIT . The CWT as a correlation. (i) scaling function and subspaces. Construction of a general orthonormal MRA. inverse CWT. the signal. 95 . Ramchandran.6 Non . 7 Hours UNIT . DTWT for image compression (i) Image compression using DTWT and run-length encoding. 2. speckle removal. 3.Introduction to theory and applications. Soman and K. Other Applications of Wavelet Transforms: Introduction.PART – B UNIT .7 (i) Embedded tree image coding (ii) compression with JPEG audio compression (iii) Audio masking.separable multidimensional wavelets. 2008. Filtering relationship for bi-orthogonal filters.8 CONSTRUCTION OF SIMPLE WAVELETS: Construction of simple wavelets like Harr and DB1. 2007. Image fusions. Person Education. edge detection and object isolation. 6 Hours UNIT . Ltd. Gilbert Strang and Nguyen Wellesley Cambridge press. Insight into WAVELETS from theory to practice. Wavelet transforms. wavelet packets. K. 2-D wavelets. Wave-let and filter banks.L. Wavelet transforms. Raghuveer M. Prasad and Iyengar. 7 Hours TEXT BOOK: 1. 6 Hours UNIT . transform coding. Wavelets Transform and Data Compression: Introduction. Bapardikar.5 ALTERNATIVE WAVELET REPRESENTATIONS: Introduction.P. Examples of bi-orthogonal scaling functions and wavelets. John Wiley India Pvt. Biorthogonal wavelet bases. (iv) Wavelet based audio coding.Rao and Ajit S. Eastern Economy Edition. REFERENCE BOOKS: 1. wavelet de-noising. Object detection by wavelet transforms of projections. 1996. 2000. Characterization of Optimal Routing. M/M/m. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT – 1&2 DELAY MODELS IN DATA NETWORKS: Queuing Models. Window Flow Control. Rate Adjustment Algorithms. 12 Hours UNIT – 3&4 MULTI-ACCESS COMMUNICATION: Slotted Multi-access and the Aloha System. Routing in the Codex Network. & Morgan Kaufman. 12 Hours PART – B UNIT – 5&6 ROUTING IN DATA NETWORKS: Introduction. M/M/ . Pearson Education (Asia) Pte. 2004. “High-Speed Networks and Internets” William Stallings. Varaya. 14 Hours UNIT – 7&8 FLOW CONTROL: Introduction. 2000. Walrand and P. Ltd. M/G/1 System. Carrier Sensing. Flow models. and Topological Design. Projection Methods for Optimum Routing. 14 Hours REFERENCE BOOKS: 1. Optimal Routing. of Lecture Hrs/Week : 04 Total no. 2nd edition.MODELING AND SIMULATION OF DATA NETWORKS Subject Code : 10EC766 No. Feasible Direction Methods for Optimal Routing. “High Performance Communication Networks” J. Packet Radio Networks. M/M/m/m and other Markov System. 3. M/M/1. Networks of Transmission Lines. Ltd. Rate Control Schemes. “Data Networks" Dimitri Bertsekas and Robert Gallager. 2nd edition. Harcourt India Pvt. Broadcasting Routing Information: Coping with Link Failures. 96 . 2. Time Reversibility. Splitting Algorithms. of Lecture Hrs. Networks of Queues. Prentice Hall of India. 2003. Multi-access Reservations. Network Algorithms and Shortest Path Routing. Overview of Flow Control in Practice. Cal handoff. History and Evolution Different generations of wireless cellular networks 1G. of Lecture Hrs. Traffic cases. CDMA channel concept CDMA operations. Cellular concept Cell fundamentals. GSM channel concepts. Roaming. Digital modulation 97 . views of cellular networks. Radio resources and power management Wireless network security. 7 Hours UNIT . Cellular backbone networks. 2g. of Lecture Hrs/Week : 04 Total no. Path loss models. GSM protocol architecture. CDMA overview. wireless coding techniques. GSM identifiers 6 Hours PART – B UNIT . GSM Network and system Architecture. Common cellular network components. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT .1 Introduction to wireless telecommunication systems and Networks. GSM system overview.5 GSM system operation. 6 Hours UNIT .7 Wireless Modulation techniques and Hardware. Mobility management. Hardware and software. 3G cellular systems components.3 Wireless network architecture and operation. 6 Hours UNIT .4 GSM and TDMA techniques. Capacity expansion techniques. 6 Hours UNIT . 7 Hours UNIT .6 CDMA technology.3G and 4G networks. Cellular component identification Call establishment.2 Common Cellular System components. Characteristics of air interface.VIII SEMESTER WIRELESS COMMUNICATION Subject Code : 10EC81 No. TDMA systems. REFERENCE BOOKS: 1. 2nd. Typical GSM Hardware. Kakkasageri. “Wireless Communication – Principles & Practice” . “Wireles and Mobile Network concepts and protocols”. 7 Hours TEXT BOOK: 1. 7 Hours 98 . Network services.11X technologies.S. Digital transmission.techniques.Y. Regulation. 2009. Network structure. Manvi. PHI 2001. John Wiley India Pvt. 5. FDM. Ltd. Transmission performance. UWB radio techniques.C. S. TDM.1 Developments of telecommunications.16X technologies. 4. Mobile Cellular Telecommunication. Introduction to telecommunications transmission. Fundamentals of Wireless Communication. of Lecture Hrs. M. of Lecture Hrs/Week : 04 Total no. T.8 Introduction to wireless LAN 802. Lee W.15X technologies in PAN Application and architecture Bluetooth Introduction to Broadband wireless MAN. Power levels. MGH. Evolution of Wireless LAN Introduction to 802. 802. Pramod Viswanath. 3. Diversity techniques.D P Agrawal: 2nd Edition Thomson learning 2007. 7 Hours UNIT . PDH and SDH. 2. S. 1st edition. DIGITAL SWITCHING SYSTEMS Subject Code : 10EC82 No. Wireless Telecom Systems and networks. David Tse. 2010. Rappaport. Wireless communication . Mullet: Thomson Learning 2006. Cambridge 2005. Standards. S. terminology. Four wire circuits. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . OFDM. Feature flow diagram. Circuit switching. Basics of crossbar systems. System outage and its impact on digital switching system reliability.5 TIME DIVISION SWITCHING: Introduction. 6 Hours DIGITAL SWITCHING SYSTEMS: Fundamentals : Purpose of analysis. Stored program control switching systems. Message switching. Interface of a typical digital switching system central office. Single stage networks.4 SWITCHING SYSTEMS: Introduction. Mathematical model. 7 Hours UNIT . Time switching networks. Digital switching system fundamentals. Building blocks of a digital switching system. Call features. Digital switching systems. Software architecture for level 2 control. Synchronisation. Functions of switching systems. Connect sequence. Unit of traffic. Traffic measurement. Outside plant versus inside plant. Electronic switching. Software maintenance. Impact of software patches on digital switching system 99 . Concept of generic program. lost call systems. Call models. Software architecture for level 1 control.6 SWITCHING SYSTEM SOFTWARE: Introduction. Scope. 7 Hours UNIT . Operating systems. Software linkages during call. 6 Hours PART – B UNIT . 6 Hours UNIT . Basic call processing. Digital switching system software classification. GOS of Linked systems. Gradings. Feature interaction.7 MAINTENANCE OF DIGITAL SWITCHING SYSTEM: Introduction.3 TELECOMMUNICATIONS TRAFFIC: Introduction. Distribution systems. Basic central office linkages.UNIT . Congestion. 6 Hours UNIT . Link Systems. Software architecture for level 3 control. Switching system hierarchy. Database Management. Basic software architecture. Scope. space and time switching. Evolution of digital switching systems.2 EVOLUTION OF SWITCHING SYSTEMS: Introduction. Queuing systems. 2002. Analysis report. A strategy improving software quality. REFERENCE BOOK: 1.8 A GENERIC DIGITAL SWITCHING SYSTEM MODEL: Introduction. Hardware architecture. 6 Hours 100 . Fundamental mode. Metrics. 7 Hours UNIT . Generic program upgrade. Digital Switching Systems. 2. Program for software process improvement. Traffic and Networks .maintainability. Software processes. of Lecture Hrs/Week : 04 Total no. Effect of firmware deployment on digital switching system. TMH Ed 2002. Common characteristics of digital switching systems. 2008. Embedded patcher concept. Telecommunication and Switching. Software architecture. Simple call through a digital system. A methodology for proper maintenance of digital switching system.John C Bellamy: Wiley India India Pvt. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . Number of patches applied per year. Challenges. Switching system maintainability metrics. Syed R.J E Flood: Pearson Education. Digital Telephony . Ali. Diagnostic resolution rate. Scope.1 CHARACTERIZATION OF DISTRIBUTED SYSTEMS: Introduction. Architectural models. Ltd. Firmware-software coupling. 7 Hours UNIT . Growth of digital switching system central office.2 SYSTEM MODELS: Introduction. Software processes improvement. 6 Hours TEXT BOOKS: 1. of Lecture Hrs. Defect analysis. Defect analysis. Recovery strategy. ELECTIVE –IV (GROUP D) DISTRIBUTED SYSTEM Subject Code : 10EC831 No. Upgrade process success rate. Resource sharing and the web. Examples of distributed systems. Reliability analysis. 3rd Ed. Reported critical and major faults corrected. Global states. Tim Kindberg. Clocks. 7 Hours UNIT . Cryptography progrmatics. Synchronizing physical clocks. fourth edition. Pearson education. a Middleware Approach” Arno puder. Communication between distributed objects.4 DISTRIBUTED OBJECTS AND REMOTE INVOCATION: Introduction.7 COORDINATION AND AGREEMENT: Distributed mutual exclusion. The API for the internet protocols. George Coulouris. Morgan Kaufmann publishers.3 INTERPROCESS COMMUNICATION: Introduction. Digital signature. Jeam Dollimore. Frank Pilhofer. Overview of security technique cryptographic algorithms. Group communication. Clint-server communication. External data representation and marshalling. Remote procedure call. 6 Hours PART – B UNIT . 6 Hours UNIT . “Distributed System Architecture. CORBA Services. 7 Hours UNIT . 6 Hours TEXT BOOK: 1. 2006.6 TIME & GLOBAL STATES: Introduction. Process states. REFERENCE BOOK: 1. Events and notifications. 101 . Elections. Multicast communication. Concepts & Design”.5 SECURITY: Introduction. Kay Romer. Events. 7 Hours UNIT .8 CORBA CASE STUDY: Introduction. CORBA RMI. “Distributed Systems. Distributed debugging.UNIT . The RSA algorithm. of Lecture Hrs. Viruses and UNIT . Hash Functions. Authentication functions. 6 Hours UNIT . The OSI security architecture. 6 Hours UNIT . Data encryption standard (DES). A model for network security. Simplified DES. Key Management.4 Digital signatures.7 MALICIOUS SOFTWARE: Countermeasures. 7 Hours UNIT .2 SYMMETRIC CIPHERS: Symmetric Cipher Model.NETWORK SECURITY Subject Code : 10EC832 No. Digital Signature Standard. 6 Hours UNIT . Virus 7 Hours 6 Hours . Security socket layer (SSL) and Transport layer security. Substitution Techniques. Transposition Techniques. Differential and Linear Cryptanalysis. of Lecture Hrs/Week : 04 Total no.Hellman Key Exchange. Evaluation Criteria for Advanced Encryption Standard. Secure Electronic Transaction.1 Services.8 Firewalls Design Principles. UNIT . Block Cipher Design Principles and Modes of Operation. Trusted Systems.5 Web Security Consideration.3 Principles of Public-Key Cryptasystems. Password Management. Diffie . 102 Related 6 Hours Threats. The AES Cipher.6 Intruders. mechanisms and attacks. Authentication Protocols. Intrusion Detection. 7 Hours PART – B UNIT . Elliptic Curve Arithmetic. The strength of DES. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . 7 Hours PART – B UNIT . Power penalty. Pearson Education. 6 Hours UNIT . Atul Kahate. Transmitter. OPTICAL NETWORKS Subject Code : 10EC833 No. of Lecture Hrs/Week : 04 Total no. Non linear effects SPM. System and network evolution. 6 Hours UNIT . Behrouz A. TMH. 2. Cryptography and Network Security. receiver. Multiplexing techniques.5 FIRST GENERATION NETWORKS: SONET/SDH. Crosstalk. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . 2003. Computer interconnects. 2003. of Lecture Hrs. First generation optical networks.3 Transmitters. detectors. Cryptography and Network Security.1 INTRODUCTION TO OPTICAL NETWORKS: Telecommunication networks. Wavelength converters. Layered architecture for SONET and second generation networks. 6 Hours 103 . Switches. Mans. Overall design Consideration. Forouzan. Multiplexes and filters Optical amplifiers. 2007. CPM. Solitons. Cryptography and Network Security.4 TRANSMISSION SYSTEM ENGINEERING: System model. optical amplifiers.TEXT BOOK: 1. isolators and Circulators. 7 Hours UNIT . REFERENCE BOOKS: 1. four wave mixing. Second generation optical networks.2 COMPONENTS: Couplers. TMH. Dispersion. William Stalling. Photonic packet switching. 6 Hours UNIT . an ILP formulation.UNIT . Multiplexing and demultiplexing Synchronisation. fault management. Pure TAM Network.2 NETWORK SERVICES AND LAYERED ARCHITECTURE: Applications. present and future access networks. 7 Hours TEXT BOOK: 1. HIGH PERFORMANCE COMPUTER NETWORKS Subject Code : 10EC834 No. 6 Hours UNIT . FTTC. Network management configuration management.8 ACCESS NETWORKS: Network architecture overview. Optical access networks Deployment considerations. Future networks Internet. Regular virtual topologies. Control and management.7 VIRTUAL TOPOLOGY DESIGN: Virtual topology design problem. REFERENCE BOOKS: 1.6 WAVELENGTH ROUTING NETWORKS: Optical layer. Optical Networks. 2. Cable Network. Network 104 . Node design. OTDM. HFC. of Lecture Hrs/Week : 04 Total no. Performance management. Networking principles. Network design and operation. Optical networks: A practical perspective Kumar Sivarajan and Rajiv Ramaswamy: Morgan Kauffman 1998. Combines SONET/WDM network design. 7 Hours UNIT . of Lecture Hrs. Wireless. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . Ulysees Black: Pearson education 2007.1 History of Communication Networks. routing and wavelength assignment architectural variations. Traffic characterization and quality of services. Optical Communication Networks: Biswajit Mukherjee: TMG 1998. 3 INTERNET AND TCP/IP NETWORKS: Multicast IP. Applications. Internetworking with ATM.. ad hoc networks. ISPs. SMTP. TCP and UDP. Empirical model. Network Elements. Wireless networks today. FTH. Datagram Networks Network economics. William Stallings. Intelligent networks CATV. Warland and Varaiya: Morgan Kauffman/ Elsivier 2nd Edition 2000. FTP. Mobile IP. Performance of circuit switched networks. Future networks. Channel Access. Addressing. 7 Hours UNIT . DWDM. 6 Hours PART – B UNIT . Circuit switched networks. Network architectures. Internet success and limitations. 7 Hours UNIT . 7 Hours UNIT . 105 . 2. Home RF and Bluetooth. High performance networks. Derived demand for network services. 2001.. High speed Digital cellular.6 WIRELESS NETWORKS: Link level design. REFFRENCE BOOKS: 1.8 OPTICAL NETWORKS: WDM systems. Tere Parnell. 6 Hours UNIT . 7 Hours UNIT . Open data network model. 6 Hours TEXT BOOK: 1.4 SONET.services. ATM AAL. Objectives and methods of control. High Performance Communication Networks. DSL. Pearson Edu. signaling and Routing. ATM header structure. Optical paths and networks. TMGH. Network bottlenecks. Network design. subscriber demand model. Optical LANs. Optical cross connects. Performance of TCP/IP Networks. High-Speed Networks and Internet: Performance and Quality of service. Building High-Speed Networks. 2000. Layered applications.7 Control of networks.5 ATM: Main features of ATM. Protocol engineering process. of Lecture Hrs/Week : 04 Total no. Conformance testing with TTCN. Multimedia protocol specifications.INTERNET ENGINEERING Subject Code : 10EC835 No. Verification of a protocol using finite state machines. Development methods. Application protocols. and communication protocol: Representation. OSI model. and protocol validation approaches. Network services and interfaces. SDL based tools for conformance testing. Conformance test architectures.3 SPECIFICATION AND DESCRIPTION LANGUAGE (SDL): A protocol specification language: SDL. Internet protocol specifications. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . 7 Hours PART – B UNIT .1 INTRODUCTION: Communication model. Other protocol specification languages. 7 Hours UNIT . Test sequence generation methods. Distribute architecture by local methods. Interface specifications. Communication software. NETWORK REFERENCE MODEL: Layered architecture. SDL based protocol verification. 6 Hours UNIT . Protocol Verification And Validation.2 PROTOCOL SPECIFICATION: Communication service specification. 7 Hours 106 . Interactions. TCP/IP protocol suite. of Lecture Hrs. SDL based protocol validation.4 Examples of SDL based protocol specifications. Protocol entity specification. Conformance testing of RIP. 6 Hours UNIT .5 Protocol validation. Multimedia applications testing. Protocol verification. protocol functions. Protocol design errors. 6 Hours UNIT .6 PROTOCOL CONFORMANCE TESTING: Conformance testing methodology and framework. digital principles. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . 7 Hours UNIT . 2. 2006. interactive synthesis algorithms. media types. automatic synthesis of SDL from MSC protocol re synthesis. network types. The Internet and its Protocols. text compression. images. multipoint conferencing.2 MULTIMEDIA INFORMATION REPRESENTATION: Introduction. PHI. of Lecture Hrs. video. S. 7 Hours UNIT . B A Forouzan. Adrian Farrel. Venkatarm and S. Scalability testing. multimedia applications. Communication Protocol Engineering. REFERENCES BOOKS: 1.3 TEXT AND IMAGE COMPRESSION: Introduction. text. communication modes. 2006. compression principles. of Lecture Hrs/Week : 04 Total no. 6 Hours TEXT BOOK: 1. image compression. audio. 2004. TCP/IP Protocol Stack. TMH. Manvi. 6 Hours UNIT .UNIT . ELECTIVE –V (GROUP E) MULTIMEDIA COMMUNICATIONS Subject Code : 10EC841 No. OSPF.1 MULTIMEDIA COMMUNICATIONS: Introduction. Elsevier.8 PROTOCOL SYNTHESIS: Synthesis methods. 6 Hours 107 . P. Interoperability testing. SDL based interoperability testing of CSMA/CD and CSMA/CA protocol using bridge.7 PROTOCOL PERFORMANCE TESTING: SDL based performance testing of TCP. multimedia networks. automatic synthesis algorithm. multimedia information representation. network QoS application QoS. Fred Halsall. Klara Narstedt. H. Bridges. TCP. Networks. IP Datagrams. “Multimedia Systems Design”. 6 Hours UNIT . MPEG-2. PHI. 7 Hours TEXT BOOK: 1. 7 Hours UNIT . Ralf Steinmetz. H.7 BROADBAND ATM NETWORKS: Introduction. UDP. 3. LAN protocol. IPv8.263. video compression principles.Media Coding and Content Processing”.261. RTP and RTCP. Switfh and Protocol Architecture ATM LANs. Multimedia Information Networking. Pearson Education. Fragmentation. Nalin K. QoS Support. “Multimedia Fundamentals: Vol 1 . 108 . Prabhat K. FDDI High-speed LANs. IP Address. and MPEG-4. REFERENCE BOOKS: 1. Sharda. LANs.4 AUDIO AND VIDEO COMPRESSION: Introduction. 7 Hours PART – B UNIT .8 TRANSPORT PROTOCOL: Introduction. Token ring. MPEG. 6 Hours UNIT .6 THE INTERNET: Introduction. 2003. Asia. Pearson Education. video compression. Protocols and Standards.UNIT . Kiran Thakrar. APC. Multimedia Communications: Applications.5 MULTIMEDIA INFORMATION NETWORKS: Introduction. Andleigh. 2. Cell format. audio compression. Ethernet. DPCM. MPEG-1. 2004. Second Indian reprint 2002. ADPCM. LPC. ARP and RARP. TCP/IP. 2004. PHI. Feasibility. Soft Real-Time Services: Missed Deadlines. I/O Architecture. Rate Montonic least upper bound. priority inversion. The Cyclic Esecutive. ECC Memory. 6 Hours UNIT 4 I/O Resources: Worst-case Execution time. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT 1 Introduction to Real-Time Embedded Systems: Brief history of Real Time Systems. Memory: Physical hierarchy. of Lecture Hrs. Capacity and allocation. Scheduler Concepts. Deadline – Monotonic Policy. Shared Memory. Preemptive Fixed Priority Scheduling Policies. 7 Hours PART – B UNIT 5 Multiresource Services: Blocking. Scheduling Classes. Real-Time Service Utility. 6 Hours UNIT 2 System Resources: Resource Analysis.REALTIME OPERATING SYSTEMS Subject Code : 10EC842 No. Dynamic priority policies. Real-Time OS. Thread Safe Reentrant Functions. Mixed hard and soft real-time services. Execution efficiency. Critical sections to protect shared resources. Necessary and Sufficient feasibility. Flash filesystems. Deadlock and livestock. of Lecture Hrs/Week : 04 Total no. Intermediate I/O. QoS. 7 Hours UNIT 3 Processing: Preemptive Fixed-Priority Policy. 7 Hours 109 . Alternatives to rate monotonic policy. A brief history of Embedded Systems. GSM Subsystems. Trace ports. Hierarchical applications for Fail-safe design. Efficiency. 7 Hours UNIT 7 Performance Tuning: Basic concepts of drill-down tuning. Application-level debugging. 2008 GSM Subject Code : 10EC843 No. Power-On self test and diagnostics. GSM frequency bands. Objectives of a GSM PLMN. 2007. Fundamental optimizations. “ Programming and Customizing the PIC microcontroller” .1 GSM ARCHITECTURE AND INTERFACES: Introduction. of Lecture Hrs/Week : 04 Total no. kernel scheduler traces. Single-step debugging. Available software. Design of RTOS – PIC microcontroller. Similarities and differences. 2. Path length. of Lecture Hrs. Design trade offs. and Call frequency. GSM Subsystems entities. Checking return codes. TMH. Myke Predko. Debugging Components: Execptions assert. hardware – supported profiling and tracing. External test equipment. A interface (BSC 110 . GSM PLMN. Reliability. Reliable software. Software application components. RTOS system software mechanisms. Test access ports. 6 Hours UNIT 8 High availability and Reliability Design: Reliability and Availability. (Chap 13 of book Myke Predko) 7 Hours REFERENCE BOOKS: 1. 3rd Ed. Building performance monitoring into software. GSM PLMN Services. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . GSM interfaces. The radio interface (MS to BSC). Abits interface (BTS to BSC).UNIT 6 Embedded System Components: Firmware components. Cengage Learning India Edition. “Real-Time Embedded Systems and Components” Sam Siewert. Time domain waveform coding. GSM call setup by an MS. MSC to VLR and HLR.6 PRIVACY AND SECURITY IN GSM: Introduction. Token-based authentication. GSM frame structure. Interfaces between other GSM entities. Smart antenna. Packet data on the signaling channel. Transmission bit rate. Frequency correction channel burst. Delay. GSM logical channels. 6 Hours UNIT . Half-rate vocoder. SIM cards. TCH multi frame for TCH/H. 7 Hours UNIT . Privacy of communications. 6 Hours UNIT .5 GSM messages. Dynamic power control. Group 3 fax. Mobile identification. Bit rate. MS-BS interface. GSM bursts. Synchronization burst. Radio link features of GSM. Quality. SMS. CCH multi frame. Call model. Full-rate vocoder. Radio link measurements. Data encryption in GSM. GSM PLMN services. Allowed logical channel combinations. Vocoders. Channel borrowing.2 RADIO LINK FEATURES IN GSM SYSTEMS: Introduction. Security algorithms for GSM. Interconnection for switched data. GSM data services. Data interworking. SFH.3 GSM LOGICAL CHANNELS AND FRAME STRUCTURE: Introduction. GSM GPRS. MESSAGES. Speech coding methods. SERVICES. Authentication requirements. Waveform coding. Complexity. System lifetime requirements. AND CALL FLOWS IN GSM: Introduction.4 SPEECH CODING IN GSM: Introduction. Speech code attributes. Access burst.to MSC). Mobile-Terminated call. User-to-user signaling. Wireless security requirements. ITU-T standards. Data services. 7 Hours UNIT . BS to MSC messages on the A interface. Mobility management. LPAS. Introduction. 7 Hours PART – B UNIT . 6 Hours UNIT . Topology model. Discontinuous transmission (DTX). Tele traffic models. Future techniques to reduce interface in GSM. Call release. Normal burst. Handover. Token-based registration. Location registration.7 PLANNING AND DESIGN OF A GSM WIRELESS NETWORK: Introduction. Frequency domain waveform coding. Token-based challenge. Mobility in 111 . Physical requirements. Mapping of GSM layers onto OSI layers. GSM: Evolution towards 3rd Generation Systems. OSI systems management. 1st edition 1998 2. 2001. GSM information model. OMC functionality. Coverage planning. TMN management services. Future work items. NM interface and functionality. Relationship between delay spread and symbol rate.8 MANAGEMENT OF GSM NETWORKS: Introduction. Selection of modulation scheme. Personal mobility management. Propagation path loss. “Principles of Applications of GSM”. Radio design for a cellular / PCS network.1 AD HOC NETWORKS: Introduction. ADHOC WIRELESS NETWORKS Subject Code : 10EC844 No. 6 Hours 112 . TMN interface. Radio link design. Issues in Ad hoc wireless networks. Friedhelm Hillebrand. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . Karl Kammerlander Springer. Design of a wireless system. Z. GSM & UMTS: The Creation of Global Mobile Communication. Traditional approaches to NM. Wilkes. Vijay K. 7 Hours UNIT . John Wiley & Sons. 1999. of Lecture Hrs/Week : 04 Total no. Garg & Joseph E. Management of radio resources. 7 Hours TEXT BOOK: 1. Ad hoc wireless internet. Constraints for hardware implementation. Design example for a GSM system. Management requirements for wireless networks. TMN.cellular / PCS networks. SNMP. TMN applications. of Lecture Hrs. Spectral efficiency of a wireless system. (Editor). TMN nodes. System requirements. Application of a fluid flow model. Receiver sensitivity and link budget. Management of GSM network. TMN layers. NMS functionality. Zvonar Peter Jung. REFERENCE BOOKS: 1. Design of TDMA frame. Pearson education/ PHI. Planning of a wireless network. Terminal mobility. Service requirements. Service mobility management. Platform-centered management. GSM containment tree. UNIT . C. 7 Hours TEXT BOOK: 1. Manoj. Classification of MAC protocols. 6 Hours UNIT .based MAC protocols with scheduling mechanism.4 ROUTING PROTOCOLS FOR AD HOC WIRELESS NETWORKS: Introduction. Power aware routing protocols. Issues & challenges in security provisioning.7 SECURITY: Security in wireless Ad hoc wireless Networks. 113 . MAC protocols that use directional antennas. Issues in designing a MAC protocol for Ad hoc wireless Networks.2 MAC PROTOCOLS FOR AD HOC WIRELESS NETWORKS: Introduction. 6 Hours UNIT .5 Hybrid routing protocol. Issues and challenges in providing QoS in Ad hoc wireless Networks.8 QUALITY OF SERVICE IN AD HOC WIRELESS NETWORKS: Introduction.6 TRANSPORT LAYER PROTOCOLS FOR AD HOC WIRELESS NETWORKS: Introduction. Classification of routing protocols. Pearson Education. Design goals of a transport layer protocol for Ad hoc wireless Networks. Routing protocols with effective flooding mechanisms. Siva Ram Murthy & B. On-demand routing protocol. Table drive routing protocol. 2nd Edition. reprint 2005. “Ad hoc wireless Networks”. Issues in designing a routing protocol for Ad hoc wireless Networks. 7 Hours PART – B UNIT . 7 Hours UNIT . 6 Hours UNIT . Network security requirements. Other MAC protocols. 7 Hours UNIT . Design goals of a MAC protocol for Ad hoc wireless Networks. Hierarchical routing protocols. S. Classification of QoS solutions. Issues in designing a transport layer protocol for Ad hoc wireless Networks.3 Contention . 1 MATHEMATICAL AND DIGITAL IMAGE FUNDAMENTALS: Introduction. nonlinear optical processing. Fourier Transform. Matched filter. Kluwer Academic publishers. Spatial high modulators. of Lecture Hrs/Week : 04 Total no. Theta modulation devices. “Ad hoc wireless Networks”. sampling and quantization. “Ad hoc wireless Networking”. holography. Wiley 2. Halftone processing. image enhancement. DingZhu Du. 6 Hours UNIT . Amplitude modulated recognition filters. Xiuzhen Cheng. Fourier transform property of lens . photographic film. Tonguz and Gianguigi Ferrari. 7 Hours UNIT . Joint transform correlation.3 ANALOG OPTICAL ARITHMETIC: Introduction. inverse filtering. OPTICAL COMPUTING Subject Code : 10EC845 No.4 RECOGNITION USING ANALOG OPTICAL SYSTEMS: Introduction. 6 Hours UNIT .2 LINER OPTICAL PROCESSING: Introduction. Arithmetic operations. Threshold devices. Deblurring. image restoration. 7 Hours PART – B UNIT . Xiao Hung.REFERENCE BOOKS: 1.5 DIGITAL OPTICAL COMPUTING DEVICES: Introduction. Generalized correlation filter. Melllin transform based correlation. spatial filtering using binary filters. : 52 IA Marks Exam Hours Exam Marks : 25 : 03 : 100 PART – A UNIT . Nonlinear devices. 6 Hours 114 . Ozan K. Integrated optics. discrete Fourier transform. Phase-only filter. of Lecture Hrs. basic diffraction theory. Optical implementation of symbolic substitution. Sequential ALU using POSC. ********** 115 . Parallel ALU using POSC. “Optical Computing An Introduction”.8 ARTIFICIAL INTELLIGENT COMPUTATIONS: Introduction. 7 Hours UNIT .6 SHADOW-CASTING AND SYMBOLIC SUBSTITUTION: Introduction. POSC logic operations. REFERENCE BOOKS: 1. Limitations and challenges. Symbolic substitutions.UNIT . Optical implementations. Artificial Intelligence. 2. 6 Hours UNIT . Multiplication. POSC image processing. Cellular logic architecture. Neural networks. Shadow casting system and design algorithm. Associative memory. Mohammed A. Programmable logic array. Karim.7 OPTICAL MATRIX PROCESSING: Introduction. Optical Signal Processing by Vanderlugnt John willy & sons NY 1992. 7 Hours TEXT BOOK: 1. 1992. POSC multiprocessor. Matrix operations. Signal Processing in Optics .Bradly G Boore Oxford University Press 1998. John Wiley & Sons. Interconnections. Multiplication using convolution.