Lab 11: A Simple DigitalCombinational Lock Kevin Bradshaw ECEN 248: Introduction to Digital Design, Section 302 TA: Daniel Mcbride Due date: August 11th, 2014 1 Objectives: The purpose of this lab is to learn more about Finite State Machines (FSM) and state diagrams in order to emphasize concepts over synchronous circuits learned in lecture. The type of FSM that will be built in this lab is a Moore type FSM. A Rotary Combination-Lock is to be built using behavioral Verilog. It will also be tested on the Spartan 3E board following procedures described in the lab manual. Design Using the information given in the Pre-Lab and background section of the manual, the following source codes were written in Verilog in ISE Design Suite. The source code for experiments one and two are attached to this document. The first source code implements the Combinational Lock FSM in Verilog to introduce states in higher level abstract code. This code is for a synchronous circuit that has five states and each state have up to three different paths each. The second source code implements an Up-Down Counter in Verilog to drive the combination lock. The following diagram are the pieces that were all combined in order to build the combinational lock. Results Experiment 1 The Combinational-Lock FSM code compiled and ran successfully. Figure 1 shows the waveforms observed, also including the console output verifying that all tests passed the simulation. The tests written in the test bench code is exhaustive but necessary to ensure that exact combination without any tricks will it. The simulation of the Up-Down Counter also ran successfully. The waveforms and console output are displayed in Figure 2. The test bench code for this wasn't necessarily exhaustive because it only needed to count up and down repeatedly. 2 Figure 1: Combinational-Lock FSM Waveform Figure 2: Up-Down Counter Waveform 3 Experiment 2 Experiment 2 was synthesizing and implementing the source codes written in experiment 1 onto the Spartan 3E Starter Board. Post-Lab Questions All source codes are written are included with this lab report. 1. A possible attack on your combination-lock is a brute-force attack in which every possible input combination is tried. Given the original design with a combination of three numbers between 0 and 19, how many possible input combinations exist? How about for the modified design with a combination of four numbers? For the first design, there are 20 * 19 * 19 = 7220 possible input combinations. The reason why it's not 20 * 20 * 20 is because the intermediate numbers can't be reused since it has to move to the right or left. Using the same logic as before, for the second design, there are 20 * 19 * 19 * 19 = 137180 possible input combinations. Conclusion In this lab, the source codes worked properly showing how higher level abstraction to manipulate modules designed by the student can be used to create a Finite State Machine. By testing the code on the FPGA board, I was able to learn how FSM really work with combinational circuits to describe a given problem or purpose. By following the lab procedure, I was able implement and test the designs that I created and was given. Student Feedback 1. What did you like most about the lab assignment and why? What did you like least about it and why? I liked this lab because it felt like a full-scale project. I didn't like this lab because the lab manual didn't help very much when writing the code. 2. Were there any sections of the lab manual that were unclear? Yes, the Verilog code for the combinational lock was very vague. 3. What suggestions do you have to improve the overall lab assignment? Have a tested and working code for major labs like these so that the TA can offer help to all the students in the lab.