DSD LAB MANUAL entity gate_or is .std_logic_1164. 2) VHDL Code for OR gate: library ieee. use ieee. z) begin if a=’0’ and b=’0’then z <=’0’ . z : out std_logic). end process.:1 Aim: To design all gates using VHDL.Experiment No.std_logic_1164.all. end if. else a=’1’ and b=’1’then z <=’1’ . use ieee. b. architecture archi of gate_and is begin process (a. elsif a=’0’ and b=’1’then z <=’0’ . b: in std_logic. elsif (a=’1’ and b=’0’then z <=’0’ .all. entity gate_and is port (a. end gate_and. end archi. Software Required: Active HDL VHDL Code:1) VHDL code for AND gate library ieee. end gate_nand. b: in std_logic.all. architecture archi of gate_or is begin process (a. elsif a=’0’ and b=’1’then z <=’1’ . else a=’1’ and b=’1’then z <=’1’ . architecture archi of gate_nand is begin process (a. end process. z) begin if a=’0’ and b=’0’then z <=’1’ .std_logic_1164. end gate_or. 3) VHDL code for NAND gate: library ieee. elsif a=’0’ and b=’1’then z <=’1’ . b: in std_logic.port (a. b. elsif (a=’1’ and b=’0’then z <=’1’ . b. z) begin if a=’0’ and b=’0’then z <=’0’ . end if. entity gate_nand is port (a. z : out std_logic). z : out std_logic). end archi. use ieee. . std_logic_1164. NAND and NOR gates has been done. end process. end if. end if. end gate_nor. b: in std_logic. end archi.elsif (a=’1’ and b=’0’then z <=’1’ . else a=’1’ and b=’1’then z <=’0’ . entity gate_nor is port (a. . OR. elsif (a=’1’ and b=’0’then z <=’0’ .all. end process. z : out std_logic). Result: Designing of AND. z) begin if a=’0’ and b=’0’then z <=’1’ . architecture archi of gate_nor is begin process (a. b. 4)VHDL code for NOR gate: library ieee. use ieee. else a=’1’ and b=’1’then z <=’0’ . elsif a=’0’ and b=’1’then z <=’0’ . end archi. use IEEE.ALL. use IEEE.ALL. carry <= a and b. use IEEE. b : in std_logic.Experiment No. a) Half Adder b) Full Adder Software Required: Active HDL VHDL CODE for HALF ADDER: library IEEE.STD_LOGIC_1164.STD_LOGIC_UNSIGNED.STD_LOGIC_1164.ALL. end half_adder. entity half_adder is Port ( a : in std_logic.ALL.STD_LOGIC_ARITH.ALL.STD_LOGIC_ARITH.ALL. carry : out std_logic). end Behavioral.:2 Aim: To design the following circuit and check the waveforms using VHDL.STD_LOGIC_UNSIGNED. use IEEE. use IEEE. 2) VHDL CODE for Full ADDER: library IEEE. sum : out std_logic. architecture Behavioral of half_adder is begin sum <= a xor b . entity half_adder is . use IEEE. . carry : out std_logic). end half_adder. b : in std_logic. architecture Behavioral of half_adder is begin sum <= a xor b xor c. c : in std_logic. sum : out std_logic.Port ( a : in std_logic. end Behavioral. carry <= (a and b) or (b and c) or (c and a). STD_LOGIC_UNSIGNED. s:out bit_vector(1 downto 0)).all. entity half_sub is Port ( a : in std_logic. end Behavioral.Experiment No. use IEEE.:3 Aim: To design the following circuit and check the waveforms using VHDL.STD_LOGIC_ARITH.std_logic_1164. use ieee.ALL. a) Half Subtractor b) Full Subtractor Software Required: Active HDL VHDL CODE for HALF subtractor: library IEEE. 2) VHDL CODE for Full subtractor: library ieee.STD_LOGIC_1164. architecture Behavioral of half_sub is begin diff <= a xor b . borrow : out std_logic). borrow <= a and (not b).ALL. b : in std_logic. diff : out std_logic. use IEEE. . entity flsub_select is port(a:in bit_vector(2 downto 0).ALL. use IEEE. end half_sub. ("11") when "111". ("11") when "001". ("11") when "010".end flsub_select. ("00") when "101". architecture beh of flsub_select is begin with a select s<=("00") when "000". ("10") when "100". end beh. ("01") when "011". . ("00") when "110". end archi.std_logic_1164. d. . else o <= d. s) begin if (s = "00") then o <= a. c.Experiment No. end process. end mux. use ieee. elsif (s = "01") then o <= b. o : out std_logic). end if. Software required: Active HDL VHDL code for 4x1 mux: library ieee. d : in std_logic. entity mux is port (a. c.:4 Aim: Write VHDL code for multiplexer and check the waveforms. architecture archi of mux is begin process (a. b. s : in std_logic_vector (1 downto 0).all. b. elsif (s = "10") then o <= c. use ieee. end demux.Experiment No.all. end archi.s) begin if(s=’00’)then y<=’1000’. elseif(s=’01’)then y<=’0100’. y: out std_logic_vector(0 to 3)). end if. entity demux is port (I : in std_logic. end process. Software required: Active HDL VHDL code for 1x4 demux: library ieee.:5 Aim: Write VHDL code for Demultiplexer and check the waveforms. elseif(s=’01’)then y<=’0001’.std_logic_1164. s : in std_logic_vector (1 downto 0). . architecture archi of demux is begin process (I. elseif(s=’10’)then y<=’0010’. end priority.:6 Aim: Write VHDL code for priority encoder and check the waveforms. Software required: Active HDL VHDL code for 8:3 priority encoder library ieee. architecture archi of priority is begin code <= "000" when sel(0) = '1' else "001" when sel(1) = '1' else "010" when sel(2) = '1' else "011" when sel(3) = '1' else "100" when sel(4) = '1' else "101" when sel(5) = '1' else "110" when sel(6) = '1' else "111" when sel(7) = '1' else "---".std_logic_1164.all. . entity priority is port ( sel : in std_logic_vector (7 downto 0). code :out std_logic_vector (2 downto 0)). use ieee.Experiment No. end archi. end archi. use ieee. end dec.:7 Aim: Write VHDL code for decoder and check the waveforms.: Data flow model: library ieee. . Software required: Active HDL VHDL code for a 1-of-8 decoder. res: out std_logic_vector (7 downto 0)). architecture archi of dec is begin res <= "00000001" when sel = "000" else "00000010" when sel = "001" else "00000100" when sel = "010" else "00001000" when sel = "011" else "00010000" when sel = "100" else "00100000" when sel = "101" else "01000000" when sel = "110" else "10000000".Experiment No.all. entity dec is port (sel: in std_logic_vector (2 downto 0).std_logic_1164. end comp. altb<=’0’. else if(A<B)then agtb<=’0’.std_logic_1164.aeqb. entity comp is port (A. .aitb: out std_logic_).all.:8 Aim: Write VHDL code for comparator and check the waveforms.B: in std_logic_vector (0 to 3). use ieee. agtb. architecture archi of comp is begin process(A.B) begin if(A>B)then agtb<=’1’.Experiment No. aeqb<=’0’. aeqb<=’0’. altb<=’1’. Software required: Active HDL VHDL code for comparator Behavioral model: library ieee. aeqb<=’1’. altb<=’0’. end archi. end if.else if(A=B)then agtb<=’0’. . end process. shifter : process ( clk. outp : out std_ulogic ). inp : in std_logic_vector ( width downto 0 ).Experiment No.all. architecture rtl of test_shift is signal shift_reg : unsigned ( width downto 0 ).std_logic_1164. port ( clk : in std_ulogic.numeric_std. end test_shift.all. begin outp <= shift_reg (shift_reg'high). Software required: Active HDL VHDL code for Shift Register library ieee. en : in std_ulogic. reset : in std_ulogic. use ieee. load : in std_ulogic.:9 Aim: Write VHDL code for shift register and check the waveforms. reset ) begin . entity test_shift is generic ( width : integer := 17 ). use ieee. 1 ). elsif rising_edge ( clk ) then if (load = '1' ) then shift_reg <= unsigned (inp). elsif ( en = '1' ) then shift_reg <= rotate_left ( shift_reg.if ( reset = '0' ) then shift_reg <= (others => '0'). end process shifter. end if. . end if. end rtl.