Frequency DivisionIn the Sequential Logic tutorials we saw how D-type Flip-Flop´s work and how they can be connected together to form a Data Latch. Another useful feature of the D-type Flip-Flop is as a binary divider, for Frequency Division or as a "divide-by-2" counter. Here the inverted output terminal Q (NOT-Q) is connected directly back to the Data input terminal D giving the device "feedback" as shown below. Divide-by-2 Counter It can be seen from the frequency waveforms above, that by "feeding back" the output from Q to the input terminal D, the output pulses at Q have a frequency that are exactly one half ( f÷2 ) that of the input clock frequency. In other words the circuit produces Frequency Division as it now divides the input frequency by a factor of two (an octave). This then produces a type of counter called a "ripple counter" and in ripple counters, the clock pulse triggers the first flip-flop whose output triggers the second flip-flop, which inturn triggers the third flip-flop and so on through the chain. Toggle Flip-Flop Another type of device that can be used for frequency division is the T-type or Toggle flip-flop. With a slight modification to a standard JK flip-flop, we can construct a new type of flip-flop called a Toggle flip-flop were the two inputs J and k of a JK flip-flop are connected together resulting in a device with only two inputs, the "Toggle" input itself and the controlling "Clock" input. The name "Toggle flip-flop" indicates the fact that the flip-flop has the ability to toggle between its two states, the "toggle state" and the "memory state". Since there are only two states, a T-type flip-flop is ideal for use in frequency division and counter design. Binary ripple counters can be built using "Toggle" or "T-type flip-flops" by connecting the output of one to the clock input of the next. Toggle flip-flops are ideal for building ripple counters as it toggles from one state to the next, (HIGH to LOW or LOW to HIGH) at every clock cycle so simple frequency divider and ripple counter circuits can easily be constructed using standard T-type flip-flop circuits. If we connect together in series, two T-type flip-flops the initial input frequency will be "divided-by-two" by the first flip-flop ( f÷2 ) and then "divided-by-two" again by the second flip-flop ( f÷2 )÷2, giving an output frequency which has effectively been divided four times, then its output frequency becomes one quarter value (25%) of the original clock frequency, ( f÷4 ). Each time we add another toggle or "T-type" flip-flop the output clock frequency is halved or divided-by-2 again and so on, giving an output frequency n of 2 where "n" is the number of flip-flops used in the sequence. Then the Toggle or T-type flip-flop is an edge triggered divide-by-2 device based upon the standard JK-type flip flop and which is triggered on the rising edge of the clock signal. The result is that each bit moves right by one flip-flop. All the flip-flops can be asynchronously reset and can be triggered to switch on either the leading or trailing edge of the input clock signal making it ideal for Frequency Division. Frequency Division using Toggle Flip-flops This type of counter circuit used for frequency division is commonly known as an Asynchronous 3-bit Binary Counter as the output on QA to QC, which is 3 bits wide, is a binary count from 0 to 7 for each clock pulse. In an asynchronous counter, the clock is applied only to the first stage with the output of one flip-flop stage providing the clocking signal for the next flip-flop stage and subsequent stages derive the clock from the previous stage with the clock pulse being halved by each stage. This arrangement is commonly known as Asynchronous as each clocking event occurs independently as all the bits in the counter do not all change at the same time. As the counter counts sequentially in an upwards direction from 0 to 7. This type of counter is also known as an "up" or "forward" counter (CTU) or a "3-bit Asynchronous Up Counter". The three-bit asynchronous counter shown is typical and uses flip-flops in the toggle mode. Asynchronous "Down" counters (CTD) are also available. Truth Table for a 3-bit Asynchronous Up Counter Clock Cycle 0 1 2 3 4 5 6 7 Output bit Pattern QC 0 0 0 0 1 1 1 1 QB 0 0 1 1 0 0 1 1 QA 0 1 0 1 0 1 0 1 Then by cascading together D-type or Toggle Flip-Flops we can produce divide-by-2, 4, 8 etc, asynchronous counter circuits which divide the clock frequency 2, 4 or 8 times. Counters Then a counter is a specialised register or pattern generator that produces a specified output pattern or sequence of binary values (or states) upon the application of an input pulse called the "Clock". The clock is actually used for data in these applications. Typically, counters are logic circuits than can increment or decrement a count by one but when used as asynchronous divide-by-n counters they are able to divide these input pulses producing a clock division signal. Counters are formed by connecting flip-flops together and any number of flip-flops can be connected or "cascaded" together to form a "divide-by-n" binary counter where "n" is the number of counter stages used and which is called the Modulus. The modulus or simply "MOD" of a counter is the number of output states the counter goes through before returning itself back to zero, ie, one n complete cycle. A counter with three flip-flops like the circuit above will count from 0 to 7 ie, 2 -1. It has eight different output states representing the decimal numbers 0 to 7 and is called a Modulo-8 or MOD-8 counter. A counter with four flip-flops will count from 0 to 15 and is therefore called a Modulo-16 counter and so on. An example of this is given as. 3-bit Binary Counter = 2 = 8 (modulo-8 or MOD-8) 4 4-bit Binary Counter = 2 = 16 (modulo-16 or MOD-16) 8 8-bit Binary Counter = 2 = 256 (modulo-256 or MOD-256) The Modulo number can be increased by adding more flip-flops to the counter and cascading is a method of achieving higher n modulus counters. Then the modulo or MOD number can simply be written as: MOD number = 2 3 4-bit Modulo-16 Counter Multi-bit asynchronous counters connected in this manner are also called "Ripple Counters" or ripple dividers because the change of state at each stage appears to "ripple" itself through the counter from the LSB output to its MSB output connection. Ripple counters are available in standard IC form, from the 74LS393 Dual 4-bit counter to the 74HC4060, which is a 14-bit ripple counter with its own built in clock oscillator and produce excellent frequency division of the fundamental frequency. Frequency Division Summary For frequency division, toggle mode flip-flops are used in a chain as a divide by two counter. One flip-flop will divide the clock, ƒin by 2, two flip-flops will divide ƒin by 4 (and so on). One benefit of using toggle flip-flops for frequency division is that the output at any point has an exact 50% duty cycle. In the next tutorial we will look at Asynchronous counters. or some other modulus that is equal to the power of two. InAsynchronous counters. This causes all of the Qoutputs to be reset back to binary "0000" on the count of 10. A decade counter requires resetting to zero when the output count reaches the decimal value of 10. Then an n-bit counter that counts up to its maximum modulus (2n) is called a full sequence counter and a n-bit counter whose modulus is less than the maximum possible is called a truncated counter. the clock input is connected to all of the flip-flop so that they are clocked simultaneously. Such counters are generally referred to as Decade Counters. Once QB and QD are both equal to logic "0" the output of the NAND gate returns back to a logic level "1" and the counter restarts again from "0000". A counter with a count sequence from binary "0000" (BCD = "0") through to "1001" (BCD = "9") is generally referred to as a BCD binary-coded-decimal counter because its ten state sequence is that of a BCD code but binary decade counters are more common. But it is also possible to use the basic asynchronous counter to construct special counters with counting states less than their maximum output number by forcing the counter to reset itself to zero at a pre-determined value producing a type of asynchronous counter that has truncated sequences. Asynchronous Counter In the previous tutorial we saw that an Asynchronous counter can have 2n-1 possible counting states e. . Such circuits are known as "divide-by-n" counters. Both outputs QB and QD are now equal to logic "1" and the output from the NAND gate changes state from logic "1" to a logic "0" level and whose output is also connected to the CLEAR (CLR) inputs of all the J-K Flipflops. MOD-8. MOD-16 for a 4-bit counter. We now have a decade or Modulo-10 counter. The answer is that we can by using combinational logic to take advantage of the asynchronous inputs on the flip-flop. In Synchronous counters.g. ie.The final output clock signal will have a frequency value equal to the input clock frequency divided by the MOD number of the counter. Counters can be formed by connecting individual flip-flops together and are classified according to the way they are clocked. and see that the main characteristic of an asynchronous counter is that each flip-flop in the chain derives its own clock from the previous flip-flop and is therefore independent of the input clock. when DCBA = 1010 and to do this we need to feed this condition back to the reset input. But why would we want to create an asynchronous truncated counter that is not a MOD-4. (0-15) making it ideal for use in Frequency Division. (ripple counter) the first flip-flop is clocked by the external clock pulse and then each successive flip-flop is clocked by the output of the preceding flip-flop. Asynchronous Decade Counter This type of asynchronous counter counts upwards on each leading edge of the input clock signal starting from "0000" until it reaches an output "1010" (decimal 10). If we take the modulo-16 asynchronous counter and modified it with additional logic gates it can be made to give a decade (divide-by-10) counter output for use in standard decimal counting and arithmetic circuits. Then suppose we wanted to build a "divide-by-128" counter for frequency division 7 we would need to cascade seven flip-flops since 128 = 2 . Since the maximum modulus that can be implemented with n flip-flops is 2n. Using dual flip-flops such as the 74LS74 we would still need four IC's to complete the circuit. lets say you wish to count from 0 to 39. For example. or mod-40. the above circuit could easily be adapted to other counting cycles be simply changing the connections to the AND gate. noting that the binary equivalent of 12 is "1100" and that output "QA" is the least significant bit (LSB). . Then the highest number of flip-flops required would be six. a scale-of-twelve (modulo-12) can easily be made by simply taking the inputs to the AND gate from the outputs at "QC" and "QD". One easy alternative method would be to use two TTL 7493's as 4-bit ripple counter/dividers. this means that when you are designing truncated counters you should determine the lowest power of two that is greater than or equal to your desired modulus. For example. n = 6 giving a maximum MOD of 64 as five flip-flops would only equal MOD-32.Decade Counter Truth Table Clock Count 1 2 3 4 5 6 7 8 9 10 11 Decade Counter Timing Diagram Output bit Pattern Decimal Value 0 1 2 3 4 5 6 7 8 9 QD QC QB QA 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 Counter Resets its Outputs back to Zero Using the same idea of truncating counter output sequences. Since 128 = 16 x 8. Also. Then. We could quite easily produce a 1Hz square wave signal from a standard 555 timer chip but the manufacturers data sheet tells us that it has a typical 1-2% timing error depending upon the manufacturer. The 74LS390 is a very flexible dual decade driver IC with a large number of "divide-by" combinations available ranging form divide-by-2. For example. and 100. but by using high frequency crystal oscillators and multi-bit frequency dividers. Each output in the chain depends on a change in state from the previous flip-flops output. Simple 1Hz timing signal using an 18-bit ripple counter/divider. can be used as frequency dividers to reduce a high clock frequency down to a more usable value for use in digital clocks and timing applications. Frequency Dividers This ability of the ripple counter to truncate sequences to produce a "divide-by-n" output means that counters and especially ripple counters. and at low frequencies a 2% error at 1Hz is not good. the outputs from the counter do not have a fixed time relationship with each other and do not occur at the same time due to their clocking sequence. assume we require an accurate 1Hz timing signal to operate a digital clock. They are called asynchronous counters because the clock input of the flip-flops are not all driven by the same clock signal. The main disadvantages with asynchronous counters are that there is a small delay between the arrival of the clock pulse and its output due to the internal circuitry of the gate. This is of course a very simple example of how to produce accurate frequencies. precision frequency generators can be produced for for a range of applications ranging from clocks or watches to event timing and even electronic piano/synthesizer music applications. The two IC's would be cascaded together to form a "divide-by-128" frequency divider as shown. 50. Then to summarise: Asynchronous Counters can be made from Toggle or D-type flip-flops.144kHz and an 18-bit ripple (Modulo-18) counter we can make a precision 1Hz timing signal as shown below. They can be implemented using "divide-by-n" circuits. 4. So by choosing a higher timing frequency of say 262. Of course standard IC asynchronous counters are available such as the TTL 74LS90 programmable ripple counter/divider which can be configured as a divide-by-2. Asynchronous counters are sometimes called ripple counters because the data appears to "ripple" from the output of one flip-flop to the input of the next. 20. one 7493 could be configured as a "divide-by-16" counter and the other as a "divide-by-8" counter. In asynchronous circuits this delay is called the Propagation Delay (giving the asynchronous ripple counter the nickname of propagation counter) and in some cases can produce false output counts. 10. 5. In large bit ripple counter circuits the delay of all the separate stages are added together to give a summed delay at the end of the chain which is why asynchronous counters are generally not used for in high frequency counting circuits were large numbers of bits are involved. 25. However the data sheet also tells us that the maximum operating frequency of the 555 timer is about 300kHz and a 2% error at this high frequency would be acceptable. divide-by-5 or any combination of both. . the more flip-flops that are added to an asynchronous counter chain the lower the maximum operating frequency becomes. To overcome the problem of propagation delay Synchronous Counters were developed. Truncated counters can produce any modulus number count. This results in all the individual output bits changing state at exactly the same time in response to the common clock signal with no ripple effect and therefore. propagation delay by successive stages may become undesirably large. flip-flop A (LSB) are they connected HIGH. Binary 4-bit Synchronous Counter It can be seen that the external clock pulses (pulses to be counted) are fed directly to each J-K flip-flopin the counter chain and that both the J and K inputs are all tied together in toggle mode. but only in the first flip-flop. no propagation delay. changes in the output occur in "synchronization" with the clock signal. Binary Synchronous Counter In the previous Asynchronous binary counter tutorial. advancing one state for each pulse. . but the J and K inputs of flip-flops C and D are driven from AND gates which are also supplied with signals from the input and output of the previous stage. In the next tutorial about Counters. Synchronous Counters are faster using the same clock signal for all flip-flops. since each flip-flop in this circuit will be clocked at exactly the same time. and as a result the asynchronous counter suffers from what is known as "Propagation Delay". with theSynchronous Counter. Counting errors at high clocking frequencies. the external clock signal is connected to the clock input of EVERY individual flip-flop within the counter so that all of the flip-flops are clocked together simultaneously (in parallel) at the same time giving a fixed time relationship. If we enable each J-K flip-flop to toggle based on whether or not all preceding flip-flop outputs (Q) are "HIGH" we can obtain the same counting sequence as with the asynchronous circuit but without the ripple effect. we saw that the output of one counter stage is connected directly to the clock input of the next counter stage and so on along the chain. Counting a large number of bits. extra feedback logic is required.Disadvantages of Asynchronous Counters: An extra "re-synchronizing" output flip-flop may be required. we will look at the Synchronous Counter and see that the main characteristic of an synchronous counter is that the clock input of each flip-flop in the chain is connected to all of the flip-flops so that they are clocked simultaneously. To count a truncated sequence not equal to 2n. However. Then the synchronous counter follows a predetermined sequence of states in response to the common clock signal. The J and K inputs of flip-flop B are connected to the output "Q" of flip-flop A. This delay gives them the nickname of "Propagation Counters". logic "1" allowing the flip-flop to toggle on every clock pulse. In other words. As there is no propagation delay in synchronous counters because all the counter stages are triggered in parallel the maximum operating frequency of this type of counter is much higher than that of a similar asynchronous counter. Decade 4-bit Synchronous Counter . Because this 4-bit synchronous counter counts sequentially on every clock pulse the resulting outputs count upwards from 0 ( "0000" ) to 15 ( "1111" ). Therefore. the modulo's or "MOD" number still applies as it does for asynchronous counters so n a Decade counter or BCD counter with counts from 0 to 2 -1 can be built along with truncated sequences. Decade 4-bit Synchronous Counter A 4-bit decade synchronous counter can also be built using synchronous binary counters to produce a count sequence from 0 to 9. We now have a decade or Modulo-10 counter. After reaching the count of "1001". this type of counter is also known as a 4-bit Synchronous Up Counter.4-bit Synchronous Counter Waveform Timing Diagram. As synchronous counters are formed by connecting flip-flops together and any number of flip-flops can be connected or "cascaded" together to form a "divide-by-n" binary counter. the counter recycles back to "0000". A standard binary counter can be converted to a decade (decimal 10) counter with the aid of some additional logic to implement the desired state sequence. or increment to some value. it is sometimes necessary to count "down" from a predetermined value to zero and to produce an output that activates when the zero count or other pre-set value is reached. They are called synchronous counters because the clock input of the flip-flops are clocked with the same clock signal. Synchronous binary counters use both sequential and combinational logic elements. Thus. .The additional AND gates detect when the sequence reaches "1001". the count starts over at "0000" producing a synchronous decade counter. This works because the next bit must change state when the previous bit changes from high to low . The memory section keeps track of the present state. Overall faster operation may be achieved compared to Asynchronous counters.c's such as the TTL 74LS193 or CMOS CD4510 are 4-bit binary Up or Down counters which have an additional input pin to select either the up or down count mode. The sequence of the count is controlled by combinational logic. Count Down Counter As well as counting "up" from zero and increase. (CTD). Flip-flop FF0 toggles on every clock pulse.the point at which a carry must occur to the next bit. It may seem unusual that ripple counters use the falling-edge of the clock cycle to change state. (Binary 10) and causes flip-flopFF3 to toggle on the next clock pulse. the count decreases by one for each external clock pulse from some preset value. synchronous counters count on the rising-edge which is the low to high transition of the clock signal and asynchronous ripple counters count on the falling-edge which is the high to low transition of the clock signal. We could quite easily re-arrange the additionalAND gates to produce other counters such as a Mod-12 Up counter which counts 12 states from"0000" to "1011" (0 to 11) and then repeats making them suitable for clocks. Then to summarise: Synchronous Counters can be made from Toggle or D-type flip-flops. but this makes it easier to link counters together because the most significant bit (MSB) of one counter can drive the clock input of the next. With all clock inputs wired together there is no inherent propagation delay. Synchronous counters are also called parallel counters as the clock is fed in parallel to all flip-flops. Due to the same clock pulse all outputs change simultaneously. Generally. In a binary or BCD down counter. Special dual purpose i. Synchronous Counters use edge-triggered flip-flops that change states on either the "positive-edge" (rising edge) or the "negative-edge" (falling edge) of the clock pulse on the control input resulting in one single count when the clock input changes state. This type of counter is normally referred to as a Down Counter. Advantages of Synchronous Counters: Synchronous counters are easier to design. Synchronous counters usually have a carry-out and a carry-in pin for linking counters together without introducing any propagation delays. Synchronous 3-bit Up/Down Counter . each flip-flop will change state when the previous one changes from 0 to 1 at its output. are capable of counting in either direction through any given count sequence and they can be reversed at any point within their count sequence by using an additional control input as shown below. rather than by the Q output as in the up counter configuration. As a result. Bidirectional counters. also known as Up/Down counters.4-bit Count Down Counter In the 4-bit counter above the output of each flip-flop changes state on the falling edge (1-to-0 transition) of the CLK input which is triggered by the Q output of the previous flip-flop. Bidirectional Counter Both Synchronous and Asynchronous counters are capable of counting "Up" or counting "Down". instead of changing from 1 to 0. but their is another more "Universal" type of counter that can count in both directions either Up or Down depending on the state of their input control pin and these are known as Bidirectional Counters. Sequential Logic circuits have some form of inherent "Memory" built in to them as they are able to take into account their previous input state as well as those actually present.6. either Up or Down and the timing diagram gives an example of the counters operation as this Up/Down input changes state.4. shift registers. Pulse Driven .3. Sequential logic circuits are generally termed as two state or Bistable devices which can have their output or outputs set in one of two basic states. Common chips available are the 74HC190 4-bit BCD decade Up/Down counter. Event Driven . 3. Sequential Logic Representation The word "Sequential" means that things happen in a "sequence". memory devices or counters.0) but generally. the actual clock signal determines when things will happen next.The circuit above is of a simple 3-bit Up/Down synchronous counter using JK flip-flops configured to operate as toggle or T-type flipflops giving a maximum count of zero (000) to seven (111) and back to zero again. Classification of Sequential Logic As standard logic gates are the building blocks of combinational circuits. bidirectional counters can be made to change their count direction at any point in the counting sequence. Either way sequential logic circuits can be divided into the following three main categories: 1.4. Simple sequential logic circuits can be constructed from standard Bistable circuits such as Flip-flops. . Latches and Countersand which themselves can be made by simply connecting together universal NAND Gates and/or NOR Gates in a particular combinational way to produce the required sequential circuit.1.2. the output state of a sequential logic circuit is a function of the present input.6.synchronous circuits that are synchronised to a specific clock signal. a logic level "1" or a logic level "0" and will remain "latched" (hence the name latch) indefinitely in this current state or condition until some other input trigger pulse or signal is applied which will cause the bistable to change its state once again.1. Sequential Logic Basics Unlike Combinational Logic circuits that change state depending upon the actual signals being applied to their inputs at that time.asynchronous circuits that change state immediately when enabled.7) or downwards in reverse sequence (7. 2. a sort of "before" and "after" is involved. both up and down counters are incorporated into single IC that is fully programmable to count in both an "Up" and a "Down" direction from any preset value producing a complete Bidirectional Counter chip. Clock Driven . In other words. Then the 3-Bit counter advances upward in sequence (0. one after another and in Sequential Logic circuits. bistable latches and flip-flops are the building blocks of Sequential Logic Circuits.5. the past input and/or the past output and it remembers these conditions until the next clock signal changes its state. the 74F569 is a fully synchronous Up/Down binary counter and the CMOS 4029 4bit Synchronous Up/Down counter. An additional input determines the direction of the count.5.2. Nowadays.which is a combination of the two that responds to triggering pulses. Sequential logic circuits can be constructed to produce either simple edge-triggered flip-flops or more complex sequential circuits such as storage registers.3. To retain their current state.Reset and its current output Q relating to it's current state or history. otherwise the circuit is asynchronous and depends upon an external input. it is permanently set.e. We now know that in sequential circuits changes occur only on the application of a clock signal making it synchronous. so that there is feedback from each . i. The flip-flop is basically a one-bit memory bistable device that has two inputs. called the SR flip-flop. Then the SR flip-flop actually has three inputs. namelyTIME. SR Flip-Flop The SR flip-flop can be considered as one of the most basic sequential logic circuit possible. However. and is labelled S and another which will "RESET" the device (meaning the output = "0"). The NAND Gate SR Flip-Flop The simplest way to make any basic one-bit set/reset SR flip-flop is to connect together a pair of cross-coupled 2input NAND gates to form a set-reset bistable or an active LOW SR NAND Gate Latch. one which will "SET" the device (meaning the output = "1"). we can see how feedback works by examining the most basic sequential logic components. circuits with loops or feedback paths are said to be "cyclic" in nature.As well as the two logic states mentioned above logic level "1" and logic level "0". The reset input resets the flip-flop back to its original state with an output Q that will be either at a logic level "1" or logic "0" depending upon this set/reset condition. either a "1" or a "0". labelled R. A basic NAND gate SR flip-flop circuit provides feedback from both of its outputs back to its inputs and is commonly used in memory circuits to store data bits. Unfortunately. as it can be "flipped" into one logic state or "flopped" back into another. Sequential logic circuits that return back to their original state once reset. this configuration never changes state because the output will always be the same. sequential circuits rely on feedback and this occurs when a fraction of the output is fed back to the input and this is demonstrated as: Sequential Feedback Loop The two inverters or NOT gates are connected in series with the output at Q fed back to the input. The term "Flip-flop" relates to the actual operation of the device. a third element is introduced that separates sequential logic circuits from their combinational logic counterparts. Then the SR description stands for set/reset. Set. However. the flip-flop circuit is said to be "Latched" or "Set" with Q = "1" and Q = "0". Output Q is also fed back to input "A" and so both inputs to NANDgate X are at logic level "1". R with two corresponding outputs Q and its inverse or complement Q as shown below. Output Q is fed back to input "B". Since one of its inputs is still at logic level "0" the output at Q still remains HIGH at logic level "1" and there is no change of state. Therefore. and therefore its output Q must be at logic level "0". the flip-flop circuits "Reset" state has been latched.output to one of the other NAND gate inputs. S and the other called the reset. The Basic SR Flip-flop The Set State Consider the circuit shown above. one called the set. We can define this "set/reset" action in the following truth table. therefore. This unbalance can cause one of the outputs to switch faster than the other resulting in the flip-flop switching to one state or the other which may not be the required state and data corruption will exist. Q = "0". As gate X has one of its inputs at logic "0" its output Q must equal logic level "1" (again NAND gate principles). NAND gate Y inputs are now R = "1" and B = "0". . This unstable condition is known as its Metastable state. Again NAND gate principals. Q is at logic level "0". depending upon the state of inputs S or R BEFORE this input condition existed. if the two inputs are now switched HIGH again after this condition to logic "1". not Q = "0" its inverse output Q is at logic level "1". If the reset input R changes state. its output Q must be at a logic level "1" (NAND Gate principles). If the input R is at logic level "0" (R = 0) and input S is at logic level "1" (S = 1). Therefore. S now changes state to logic "1" with input R remaining at logic "1". and goes HIGH to logic "1" with S remaining HIGH also at logic level "1". the NAND gate Y has at least one of its inputs at logic "0" therefore. This device consists of two inputs. input state R = "0" and S = "0" is an undesirable or invalid condition and must be avoided because this will give both outputs Q and Q to be at logic level "1" at the same time and we would normally want Q to be the inverse of Q. Q = "1". Reset State In this second stable state. both the outputs will go LOW resulting in the flip-flop becoming unstable and switch to an unknown data state based upon the unbalance. Truth Table for this Set-Reset Function State Set Reset Invalid S 1 1 0 1 0 0 R 0 1 1 1 0 0 Q 1 1 0 0 0 1 Q Description Set Q » 1 no change Reset Q » 0 no change memory with Q = 0 memory with Q = 1 0 0 1 1 1 0 It can be seen that when both inputs S = "1" and R = "1" the outputs Q and Q can be at either logic level "1" or "0". output Q still remains LOW at logic level "0" and there is no change of state. If the set input. so both inputs to NAND gate Y are at logic "1". However. and is given by R = "1" and S = "0". and this is shown below. Then set-reset SR Flip-flops or Bistable Latch circuits can be used to eliminate this kind of problem and this is demonstrated below. For example. switch bounce occurs when the contacts of any mechanically operated switch. This gives rise to a series of individual pulses which can be as long as tens of milliseconds that an electronic system or circuit such as a digital counter may see as a series of logic pulses instead of one long single pulse and behave incorrectly. SR Bistable Switch Debounce Circuit . a bistable SR flip-flop or SR latch is activated or set by a logic "1" applied to its S input and deactivated or reset by a logic "1" applied to its R. The SR flip-flop is said to be in an "invalid" condition (Meta-stable) if both the set and reset inputs are activated simultaneously. and one practical use of this type of set-reset circuit is as a latch used to help eliminate mechanical switch "bounce". except that the inputs are active HIGH and the invalid condition exists when both its inputs are at logic level "1". The NOR Gate SR Flip-flop Switch Debounce Circuits Edge-triggered flip-flops require a nice clean signal transition. but bounce together first before closing (or opening) when the switch is pressed. As well as using NAND gates. during this bounce period the output voltage can fluctuate wildly and may register multiple input counts instead of one single count. it is also possible to construct simple one-bit SR Flip-flops using two cross-coupled NOR gates connected in the same configuration.Then. push-button or keypad are operated and the internal switch contacts do not fully close cleanly. As its name implies. The circuit will work in a similar way to the NAND gate circuit above. Gated SR Flip-flop . the very first contact will cause the latch to change state. for example 0. The 74LS279 is a Quad SR Bistable Latch IC. When the other button is pressed.5 seconds. MAX6817. The SR flip-flop can then be RESET automatically after a short period of time. if the set or reset buttons are depressed the output will change over in the manner described above and any additional unwanted inputs (bounces) from the mechanical action of the switch will have no effect on the output at Q. either high or low. Quad SR Bistable Latch 74LS279 Gated or Clocked SR Flip-Flop It is sometimes desirable in sequential logic circuits to have a bistable SR flip-flop that only changes state when certain conditions are met regardless of the condition of either the Set or the Reset inputs. of some specified width or time period for timing or control purposes. so as to register any additional and intentional repeat inputs from the same switch contacts. This extra conditional input is called an "Enable" input and is given the prefix of "EN". Commonly available IC's specifically made to overcome the problem of switch bounce are the MAX6816. which contains four individual NAND type bistable's within a single chip enabling switch debounce or monostable/astable clock circuits to be easily constructed. for example multiple inputs from a keyboards "RETURN" key. The addition of this input means that the output at Q only changes state when it is HIGH and can therefore be used as a clock (CLK) input making it level-sensitive as shown below. Set-Reset bistable latches can also be used as Monostable (one-shot) pulse generators to generate a single output pulse. dual input and the MAX6818 octal input switch debouncer IC's.Depending upon the current state of the output. single input. By connecting a 2-input AND gate in series with each input terminal of the SR Flip-flop a Gated SR Flip-flop can be created. but any additional mechanical switch bounces will also have no effect. These chips contain the necessary flip-flop circuitry to provide clean interfacing of mechanical switches to digital systems. This enable input can also be connected to a clock timing signal adding clock synchronisation to the flip-flop creating what is sometimes called a " Clocked SR Flip-flop". The JK flip-Flop is the most widely used of all the flip-flop designs and is considered to be a universal flip-flop circuit. .When the Enable input "EN" is at logic level "0". The sequential operation of the JK flip-flop is exactly the same as for the previous SR flip-flop with the same "set" and "reset" inputs. If the circuit is "RESET" the K input is inhibited by the "0" status of Q through the upper NAND gate. "logic 0". This cross coupling of the SR flip-flop allows the previously invalid condition of S = "1" and R = "1" state to be used to produce a "toggle action" as the two inputs are now interlocked. If the circuit is "SET" the J input is inhibited by the "0" status of Q through the lower NAND gate. a JK flip-flop has four possible input combinations. and number two. Due to this additional clocked input. the JK flip-Flop was developed. Jack Kilby. the S = 0 and R = 0 condition or S = R = 0 must always be avoided. The difference this time is that the JK flip-flop has no invalid or forbidden input states of the SR Latch (when S and R are both 1). The JK flip-flop is basically a gated SR flip-flop with the addition of a clock input circuitry that prevents the illegal or invalid output condition that can occur when both inputs S and R are equal to logic level "1". if S or R change state while the enable input is high the correct latching action may not occur. So a Gated Bistable SR Flipflop operates as a standard bistable latch but the outputs are only activated when a logic "1" is applied to its EN input and deactivated by a logic "0". we will look at another type of edge-triggered flip-flop which is very similar to the RS flip-flop called a JK Flip-flop named after its inventor. latching the two outputsQ and Q into their last known state. As Q and Q are always different we can use them to control the input. respectively after its inventor Jack Kilby. The JK flip-flop is the most widely used of all the flipflop designs as it is considered to be a universal device. The Basic JK Flip-flop Both the S and the R inputs of the previous SR bistable have now been replaced by two inputs called the J and K inputs. Then this equates to: J = S and K = R. the outputs of the two AND gates are also at logic level "0". The JK flip-flop From the previous tutorial we now know that the basic gated SR NAND flip-flop suffers from two basic problems: number one. The two 2-input AND gates of the gated SR bistable have now been replaced by two 3-input NANDgates with the third input of each gate connected to the outputs at Q and Q. In the next tutorial about Sequential Logic Circuits. Then to overcome these two fundamental design problems with the SR flip-flop. the JK flip-flop toggles as shown in the following truth table. (AND Gate principles) regardless of the condition of the two inputs S and R. "no change" and "toggle". When both inputs J and K are equal to logic "1". When the enable input "EN" changes to logic level "1" the circuit responds as a normal SR bistable flip-flop with the two AND gates becoming transparent to the Set and Reset signals. The symbol for a JK flip-flop is similar to that of an SR Bistable Latch as seen in the previous tutorial except for the addition of a clock input. "logic 1". Dual JK Flip-flop 74LS73 . This eliminates all the timing problems by using two SR flip-flops connected together in series. the 74LS109 Dual positive-edge triggered JK flip-flop and the 74LS112 Dual negative-edge triggered flip-flop with both preset and clear inputs. which contains two individual JK type bistable's within a single chip enabling single or masterslave toggle flip-flops to be made. or visa-versa. Also when both the J and the K inputs are at logic level "1" at the same time. which triggers on the leading edge of the clock pulse and the other. This results in the two sections. The 74LS73 is a Dual JK flip-flop IC. the "Slave" circuit. and the clock input is pulsed either "HIGH".The Truth Table for the JK Function J 0 same as 0 for the 0 SR Latch 0 1 1 toggle action 1 1 K 0 0 1 1 0 0 1 1 Q 0 0 1 0 0 1 0 1 Q Description Memory no change Reset Q » 0 Set Q » 1 Toggle 0 1 0 1 1 0 1 0 Then the JK flip-flop is basically an SR flip-flop with feedback which enables only one of its two input terminals. This results in the JK flip-flop acting more like a T-type toggle flip-flop when both terminals are HIGH. the master section and the slave section being enabled during opposite half-cycles of the clock signal. To avoid this the timing pulse period ( T) must be kept as short as possible (high frequency). which triggers on the falling edge of the clock pulse. one for the "Master" circuit. Although this circuit is an improvement on the clocked SR flip-flop it still suffers from timing problems called "race" if the output Q changes state before the timing pulse of the clock input has time to go "OFF". Other JK flip-flop IC's include the 74LS107 Dual JK flip-flop with clear. either SET or RESET to be active at any one time thereby eliminating the invalid condition seen previously in the SR flip-flop circuit. the circuit will "toggle" from its SET state to a RESET state. As this is sometimes not possible with modern TTL IC's the much improved Master-Slave JK Flip-flop was developed. This multivibrator circuit oscillates between a "HIGH" state and a "LOW" state producing a continuous output. In the next tutorial about Sequential Logic Circuits. In other words. Astable multivibrators generally have an even 50% duty cycle.The Master-Slave JK Flip-flop The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a series configuration with the slave having an inverted clock pulse. or both of the actual clock signal as we have seen previously with the basic flip-flop circuits. . The following list are terms associated with a timing pulse or waveform. we will look at Multivibrators that are used as waveform generators to produce the clock signals to switch sequential circuits. The outputs from the "master" flip-flop are only "seen" by the gated "slave" flip-flop when the clock input goes "LOW" to logic level "0". but for these types of circuits to operate in a "sequential" way. The Master-Slave JK Flip-Flop The input signals J and K are connected to the gated "master" SR flip-flop which "locks" the input condition while the clock ( Clk) input is "HIGH" at logic level "1". the circuit accepts input data when the clock signal is "HIGH". The outputs from Q and Q from the "Slave" flip-flop are fed back to the inputs of the "Master" with the outputs of the "Master" flip-flop being connected to the two inputs of the "Slave" flip-flop. This feedback configuration from the slave's output to the master's input gives the characteristic toggle of the JK flip-flop as shown below. Then on the "Low-to-High" transition of the clock pulse the inputs of the "master" flip-flop are fed through to the gated inputs of the "slave" flip-flop and on the "High-to-Low" transition the same inputs are reflected on the output of the "slave" making this type of flip-flop edge or pulse-triggered. When the clock is "LOW". Sequential logic circuits that use the clock signal for synchronization are dependant upon the frequency and and clock pulse width to activate there switching action. the "slave" SR flip-flop does not toggle. the outputs from the "master" flip-flop are latched and any additional changes to its inputs are ignored. Multivibrators Individual Sequential Logic circuits can be used to build more complex circuits such as Multivibrators. Latches and Memories etc. Clock pulses are generally continuous square or rectangular shaped waveform that is produced by a single pulse generator circuit such as a Multivibrator. As the clock input of the "slave" flip-flop is the inverse (complement) of the "master" clock input. Sequential circuits may also change their state on either the rising or falling edge. The gated "slave" flip-flop now responds to the state of its inputs passed over by the "master" section. Counters. Shift Registers. and passes the data to the output on the falling-edge of the clock signal. the Master-Slave JK Flip-flop is a "Synchronous" device as it only passes data with the timing of the clock signal. that is that 50% of the cycle time the output is "HIGH" and the remaining 50% of the cycle time the output is "OFF". In other words. the duty cycle for an astable timing pulse is 1:1. they require the addition of a clock pulse or timing signal to cause them to change their state. Then. this is the time during which the value of the clock signal is equal to one. Active LOW . Clock Signal Waveform Clock Width .if the state changes occur at the clock's rising edge or during the clock width. Combining two or more of multivibrators provides generation of a desired pattern of pulses (including pulse width.A free-running multivibrator that has NO stable states but switches continuously between two states this action produces a train of square wave pulses at a fixed frequency. Duty Cycle . CT and the resistor. C and Resistor. This trigger pulse signal initiates a timing cycle which causes the output of the monostable to change state at the start of the timing cycle. Monostable Circuits.if the state changes occur at the clock's falling edge. Consider the circuit below. time between pulses and frequency of pulses).the clock frequency is the reciprocal of the clock period.A one-shot multivibrator that has only ONE stable state and is triggered externally with it returning back to its first stable state. ( t1) which is determined by the time constant of the timing capacitor. Monostable Multivibrators or "one-shot" pulse generators are used to convert short sharp pulses into wider ones for timing applications. i. There are basically three types of clock pulse generation circuits: Astable . Monostable multivibrators generate a single output pulse.A flip-flop that has TWO stable states that produces a single pulse either positive or negative in value.e. they can also be used to provide a clock signal or timing pulse with the aid of a single Capacitor. As NAND gates contains amplification. Clock Frequency . Then. either "high" or "low". Simple NAND Gate Monostable Circuit .Active HIGH .. Bistable . This simple type of RC Oscillator network is sometimes called a "Relaxation Oscillator". The monostable multivibrator now stays in this second timing state until the end of the RC time constant and automatically resets or returns itself back to its original (stable) state. A more common name for this type of circuit is simply a "Flip-Flop" as it can be made from two cross-coupled NAND gates (or NOR gates) as we have seen previously. between two rising or two falling edges. These timing circuits are often used because of there simplicity and are also useful if a logic circuit is designed that has un-used gates which can be utilised to create the monostable or astable oscillator. Clock Period . frequency = 1/clock period Clock pulse generation circuits can be a combination of analogue and digital circuits that produce a continuous series of pulses (these are called astable multivibrators) or a pulse of a specific duration (these are called monostable multivibrators). Monostable .this is the time between successive transitions in the same direction. (t1) and remain in this second state until the end of the timing period. R which provide the feedback and timing function.is the ratio of clock width and clock period. One way of producing a very simple clock signal is by the interconnection of logic gates. a monostable circuit has only one stable state. when a suitable external trigger signal or pulse T is applied. RT. This inturn outputs a logic "0" at Q and the circuit stays in this Meta-stable state as long as the trigger input T applied to the circuit remains LOW. (NAND gate principals). NAND gates and NOR gates connected as inverters as shown below. This is known as the Meta-stable state. Since the input impedance of the NAND gates is very high. CT increases rapidly to this new voltage level. If a negative pulse is now applied either externally or by the action of the push-button to the trigger input of the NAND gate U1. large timing periods can be achieved. the output of U2 switches HIGH again.69RC of the circuit in seconds. it is also possible to build simple monostable timing circuits that start their timing sequence from the rising-edge of the trigger pulse using NOTgates. This charging process continues until the charging current is unable to hold the input of U2 and therefore junction V1 HIGH. RT is connected to a voltage level equal to logic level "0". logic "1". The voltage across the capacitor will now increase as the capacitor CT starts to charge up from the output of U1 at a time constant determined by the resistor/capacitor combination. This results in the circuit being Stable and it will remain in this state until the trigger input Tchanges. When this happens. CT to be discharged. Since the voltage across the capacitor cannot change instantaneously (capacitor charging principals) this will cause the junction at V1 and also the input to U2 to also go HIGH. The timing resistor. As well as the NAND gate monostable type circuit above. the output of U1 will go HIGH to logic "1" (NAND gate principles). (U2) is fed back to one input of U1 to provide the necessary positive feedback. which will cause the capacitor. . The circuit has now switched back to its original stable state. NOR Gate Monostable Circuit As with the NAND gate circuit above. which inturn causes the output ofU1 to go LOW and the capacitor discharges into the output of U1 under the influence of resistor RT. As the input to U2 is LOW at logic "0" its output at Q is HIGH at logic "1". The voltage across the capacitor. The diode D1 passes this logic "1" voltage level to the RC timing network. The output from the second NAND gate. which is connected as an inverting NOT gate will therefore be HIGH. The timing resistor. The length of the output time period is determined by the capacitor/resistor combination ( RC Network) and is given as the Time Constant T = 0. which is also connected to the input of the second NOT gate. which inturn will make the output of the NANDgate U2 change LOW to logic "0" The circuit will now remain in this second state even if the trigger input pulse T is removed. The output of U1 is LOW. timing capacitor CT is completely discharged therefore junctionV1 is also equal to "0" resulting in the output from the second NAND gate U2. Since the junction V1 and the output of U1 are both at logic "0" no current flows in the capacitor CT. CTare connected together in parallel and also to the input of the second NOT gate U2. When a logic level "0" pulse is applied to the trigger input T of the first NOT gate it changes state and produces a logic level "1" output.Suppose that initially the trigger input T is held HIGH at logic level "1" by the resistor R1 so that the output from the first NAND gate U1 is LOW at logic level "0". the monostable multivibrator circuit produces a LOW going output pulse. RT and the capacitor. initially the trigger input T is HIGH at a logic level "1" so that the output from the first NOT gate U1 is LOW at logic level "0". Thus for each negative going trigger pulse. Then. RT connected across it. Astable Circuits. CT starts to discharge itself through the parallel resistor. As the capacitor. the timing cycle is determined by the time constant of the resistor-capacitor. As with the monostable multivibrator circuit above. R2 decreases until the lower threshold value of U1 is reached at which point U1 changes state and the output of U1 now becomes HIGH. This causes U1 to change state and the cycle repeats itself over again. its output switches back again producing a logic level "1" at Q. RC Network.When the trigger signal returns HIGH. then the input must therefore be LOW at logic level "0" (NAND gate principles) as will be the output from the first NAND gateU1. Capacitor. or as in our simple circuit below a pair of CMOS NAND such as the CD4011 or the 74LS132 and an RC timing network. the time constant for a NAND gate Astable Multivibrator is given as T = 2.8RC + Trigger in seconds. logic level "0". When the voltage across the capacitor drops below the lower threshold value of the input to the second NOT gate. Then. C is connected between the output of the second NAND gate U2 and its input via the timing resistor. The capacitor now charges up at a rate determined by the time constant of R2 and C. C charges up. This continual switching action from "HIGH" to "LOW" and "LOW" to "HIGH" produces a continuous and stable square wave output that switches abruptly between the two logic levels making it ideal for timing and clock pulse applications. then the oscillation frequency will be given as: . the output from the first NOT gate goes LOW to logic "0" (NOT gate principals) and the fully charged capacitor. Capacitor. One main disadvantage of Monostable Multivibrators is that the time between the application of the next trigger pulse T has to be greater than the RC time constant of the circuit. Capacitor C is now reverse biased and discharges itself through the input of NAND gate U1. C. the Time Constant for a NOT gate Monostable Multivibrator is given as T = 0. The two NAND gates are connected as inverting NOT gates.C charges up again in the opposite direction determined by the time constant of both R2 and C as before until it reaches the upper threshold value of NAND gate U1. the junction between the resistor R2 and the capacitor. NAND Gate Astable Multivibrators The astable multivibrator circuit uses two CMOS NOT gates such as the CD4069 or the 74HC04 hex inverter ICs. This causes NAND gate U2 to also change state as its input has now changed from logic "0" to logic "1" resulting in the output of NAND gate U2 becoming LOW. which is also connected to the input of the NAND gate U1 via the stabilizing resistor.2RC in seconds with the output frequency given as f = 1/T. R2. Astable Multivibrators are a type of free running oscillator that have no permanent "meta" or "steady" state but are continually changing there output from one state ("LOW") to the other state ("HIGH") and then back again. Suppose that initially the output from the NAND gate U2 is HIGH at logic level "1". The diode D1 prevents the timing capacitor from discharging itself back through the first NOT gates output. Then the output frequency can be varied by changing the value(s) of the resistors and capacitor in the circuit. For example: if resistor R2 = 10kΩ and the capacitor C = 45nF. When the input pulse goes "LOW" the bistable latches into its "SET" state. This type of multivibrator circuit passes from one state to the other "only" when a suitable external trigger pulse T is applied and to go through a full "SET-RESET" cycle two triggering pulses are required. The two NAND gates.then the output frequency is calculated as being 1kHz. both states of a bistable multivibrator are stable. As with flip-flops. "Toggle Latch" or simply "T-latch". The Bistable Multivibrators circuit is basically a SR flip-flop that we look at in the previous tutorials with the addition of an inverter or NOT gate to provide the necessary switching function. U1. counters or as a storage device in computer memories but they are best used in circuits such as Latches and Counters. NAND Gate Bistable Multivibrator The simplest way to make a Bistable Latch is to connect together a pair of Schmitt NAND gates to form a SR latch as shown above. . Then a Bistable Latch or "Toggle Latch" is a two-state device in which both states either positive or negative. The output of a bistable multivibrator will stay in this "RESET" state until another input pulse is applied and the whole sequence will start again. with its output at logic level "1". This type of circuit is also known as a "Bistable Latch". and the circuit will remain in either state indefinitely. until the input goes "HIGH" causing the bistable to latch into its "RESET" state. which equates to a time constant of 1mS so the output waveform would look like: Bistable Circuits. This U1 NAND gate can be omitted and replaced by a single toggle switch to make a switch debounce circuit as seen previously in the SR Flipflop tutorial. (logic "1" or logic "0") are stable. with its output at logic level "0". U2 and U3 form the bistable which is triggered by the input NAND gate. Bistable Multivibrators have many applications such as frequency dividers. The D-type flip-flop One of the main disadvantages of the basic SR NAND Gate bistable circuit is that the indeterminate input condition of "SET" = logic "0" and "RESET" = logic "0" is forbidden.693 (R2) C1 T = t1 + t2 The voltage across the capacitor. The 555 connected as an Astable oscillator is given below. C1 charges up through resistor. DUAL NE556 etc. Delay flip-flop. so are only included here for reference purposes as a clock pulse generator. NE555 Astable Multivibrator. Pins 2 and 6 are connected together so that it will re-trigger itself on each timing cycle. CMOS LM1455. In the next tutorial about Sequential Logic Circuits. Then the timing period of t1 and t2is given as: t1 = 0. D-type Bistable or simply a D-type flip-flop as it is more generally called. ICM7555. R2as the other side of R2 is connected to the discharge terminal. Capacitor. over-riding the feedback latching action and whichever input goes to logic level "1" first will lose control. are covered in the 555 Oscillator tutorial and other good electronics based websites. frequency dividers and latches. This type of circuit is very stable as it operates from a single supply rail resulting in an oscillation frequency which is independent of the supply voltage Vcc. This state will force both outputs to be at logic "1". .5 and 16 volts. R2 but discharges only through resistor. The 555 Timer is a very versatile low cost timing IC that can produce a very accurate timing periods with good stability of around 1% and which has a variable timing period from between a few micro-seconds to many hours with the timing period being controlled by a single RC network connected to a single positive supply of between 4. Simple Monostable or Astable timing circuits can now be easily made using standard waveform generator IC's in the form of relaxation oscillators by connecting a few passive components to their inputs with the most commonly used waveform generator type IC being the classic 555 timer. Here the 555 timer is connected as a basic Astable Multivibrator circuit. we will look another type of clock controlled flop-flop called a Data Latch. C1 ranges from between 1/3 Vcc to approximately 2/3 Vcc depending upon the RC timing period. The NE555 timer and its successors. R1 and resistor. In order to prevent this from happening an inverter can be connected between the "SET" and the "RESET" inputs to produce another type of flip-flop circuit called a Data Latch. thereby functioning as an Astable oscillator. while the other input still at logic "0" controls the resulting state of the latch. pin 7.693 (R1 + R2) C1 t2 = 0.555 Timer Circuit. Data latches are very useful sequential circuits which can be made from any standard gated SR flip-flop and used for frequency division to produce various ripple counters. The D flip-flop is by far the most important of the clocked flip-flops as it ensures that ensures that inputs S and R are never equal to one at the same time. and the inverter is used to generate the complementary "reset" input thereby making a level-sensitive D-type flip-flop from a level-sensitive RS-latch as now S = D and R = not D as shown. D flip-flop Circuit We remember that a simple SR flip-flop requires two inputs. However. If this data input is HIGH the flip-flop would be "SET" and when it is LOW the flipflop would be "RESET". By connecting an inverter (NOT gate) to the SR flip-flop we can "SET" and "RESET" the flip-flop using just one input as now the two input signals are complements of each other. The D-Type flip-flop will store and output whatever logic level is applied to its data terminal so long as the clock input is HIGH. the "master" latches the input condition at D. On the trailing edge of the clock signal (HIGH-to-LOW) the second "slave" stage is now activated. Thus the single input is called the "DATA" input. latching on to the output from the first master circuit. This then forms the basis of a D-type flip-flop. Once the clock input goes LOW the "set" and "reset" inputs of the flip-flop are both held at logic level "1" so it will not change state and store whatever data was present on its output before the clock transition occurred. In other words the output is "latched" at either logic "0" or logic "1". one to "SET" the output and one to "RESET" the output. Truth Table for the D-type Flip-flop Clk ↓»0 ↑»1 ↑»1 D X 0 1 Q Q 0 1 Q Q Description Memory no change Reset Q » 0 Set Q » 1 1 0 Note: ↓ and ↑ indicates direction of clock pulse as it is assumed D flip-flops are edge triggered The Master-Slave JK Flip-flop The basic D-type flip-flop can be improved further by adding a second SR flip-flop to its output that is activated on the complementary clock signal to produce a "Master-Slave D flip-flop". To avoid this an additional input called the "CLOCK" or "ENABLE" input is used to isolate the data input from the flip-flop after the desired data has been stored. this would be rather pointless since the flip-flop's output would always change on every data input. On the leading edge of the clock signal (LOW-to-HIGH) the first stage. This complement avoids the ambiguity inherent in the SR latch when both inputs are LOW. Then the output . since that state is no longer possible. This single data input D is used in place of the "set" signal. The effect is that D is only copied to the output Q when the clock is active. D-type flip-flops are constructed from a gated SR flip-flop with an inverter added between the S and the R inputs to allow for a single D (data) input. while the output stage is deactivated. which contains two individual D type bistable's within a single chip enabling single or master-slave toggle flip-flops to be made.e. By placing a feedback loop around the D flip-flop another type of flip-flop circuit can be constructed called a T-type flip-flop or more commonly a T-type bistable. the output has half the frequency of the clock pulses. Therefore. the slave is "ON". i. Master-Slave D flip-flop Circuit We can see from above that on the leading edge of the clock pulse the master flip-flop will be loading data from the data D input. that is. "Master-Slave D flip-flops" can be constructed by the cascading together of two latches with opposite clock phases as shown.e.stage appears to be triggered on the negative edge of the clock pulse. therefore the master is "ON". In the counters tutorials we saw how the Data Latch can be used as a "Binary Divider". Then there will always be one flip-flop "ON" and the other "OFF" but never both the master and slave "ON" at the same time. Dual D flip-flop 74LS74 Frequency Division One main use of a D flip-flop is as a Frequency Divider. successive clock pulses will make the bistable "toggle" once every two clock cycles. only when one complete pulse. that can be used as a divide-by-two circuit in binary counters as shown below. Other D flip-flop IC's include the 74LS174 HEX D flip-flop with direct clear input. the output Q acquires the value of D. If the Q output on a D-type flip-flop is connected directly to the D input giving the device closed loop "feedback". 0-1-0 is applied to the clock input. the 74LS175 Quad D flip-flop with complementary outputs and the 74LS273 Octal D flip-flop containing eight D flip-flops with a clear input in one single package. There are many different D-type flip-flop IC's available in both TTL and CMOS packages with the more common being the 74LS74 which is a Dual D flip-flop IC. or a "Frequency Divider" to produce a "divide-by-2" counter circuit. i. With the trailing edge of the clock pulse the slave flip-flop is loading data. . 1-bit data latches so that all their clock terminals are connected at the same time a simple "4-bit" Data latch can be made as shown below. By connecting together four. Data Latches Another useful application of the Data Latch is to hold or remember the data present on its data input. the output pulses at Q have a frequency that are exactly one half (f/2) that of the input clock frequency. thereby acting as a single bit memory device and IC's such as the TTL 74LS74 or the CMOS 4042 are available in Quad format for this purpose.Divide-by-2 Counter It can be seen from the frequency waveforms above. In other words the circuit produces frequency division as it now divides the input frequency by a factor of two (an octave) as Q = 1 once every two clock cycles. 4-bit Data Latch . that by "feeding back" the output from Q to the input terminal D. (Fin). one after the other from either the left or the right direction. 16 or even 32 individual data latches into one single IC package. hence the name shift register. When the clock signal is LOW at logic level "0". 8-bit Data Latch Functional diagram of the 74LS373 Octal Transparent Latch D flip-flop Summary The data or D flip-flop can be built from a pair of back-to-back latches by connecting an inverter between the S and the R inputs to allow for a single D (data) input. bi-directional bus driver or even a display driver.Transparent Data Latch The Data Latch is a very useful device in electronic and computer circuits. (but can also be active low) the outputs at Qfollows the data D inputs. hence the name transparent latch. Data Latches are Level sensitive devices such as the data latch and the transparent latch.e. whereas a flip-flop always does. eight individual data latches.e. I/O port. i. i. The difference between a D-type latch and a D-type flip-flop is that a latch does not have a clock signal. . But a single "1-bit" data latch is not very practical to use on its own and instead commercially available IC's incorporate 4. The basic D-type flip-flop circuit can be improved further by adding a second SR flip-flop to its output that is activated on the complementary clock signal to produce a "Master-Slave D flip-flop". and one such IC device is the 74LS373 Octal D-type transparent latch.e. They can be designed to have very high output impedance at both outputs Q and its inverse or complement output Q to reduce the impedance effect on the connecting circuit when used as a buffer. i. In this configuration the latch is said to be "open" and the path from D input toQ output appears to be "transparent" as the data flows through it unimpeded. The D flip-flop is an edge triggered device which transfers input data to Q on clock rising or falling edge. It basically consists of several single bit "D-Type Data Latches". The data bits may be fed in or out of the register serially. or in parallel. meaning that when the clock (CLK) input is HIGH at logic level "1". In the next tutorial about Sequential Logic Circuits. the latch "closes" and the output at Qis latched at the last value of the data that was present before the clock signal changed and no longer changes in response to D. one for each bit (0 or 1) connected together in a serial or daisy-chain arrangement so that the output from one data latch becomes the input of the next latch and so on. The Shift Register The Shift Register is another type of sequential logic circuit that is used for the storage or transfer of data in the form of binary numbers and then "shifts" the data out once every clock cycle. all together. we will look at connecting together data latches to produce another type of sequential logic circuit called a Shift Register that are used to convert parallel data into serial data and vice versa. 10. The eight individual data latches or bistables of the 74LS373 are "transparent" D-type flip-flops. The number of individual data latches required to make up a single Shift Register is determined by the number of bits to be stored with the most common being 8-bits wide. 8. The individual data latches that make up a single shift register are all driven by a common clock ( Clk) signal making them synchronous devices. The effect of data movement from left to right through a shift register can be presented graphically as: Also. (right shifting) left-in but right-out. In this tutorial it is assumed that all the data shifts to the right.the register is loaded with serial data. (right shifting). Parallel-in to Parallel-out (PIPO) . Shift register IC's are generally provided with a clear or reset connection so that they can be "SET" or "RESET" as required. shift registers operate in one of four different modes with the basic movement of data through a shift register being: Serial-in to Parallel-out (SIPO) . one bit at a time. or to convert the data from either a serial to parallel or parallel to serial format. the directional movement of the data through a shift register can be either to the left.the data is shifted serially "IN" and "OUT" of the register. Parallel-in to Serial-out (PISO) . Serial-in to Parallel-out (SIPO) 4-bit Serial-in to Parallel-out Shift Register . Serial-in to Serial-out (SISO) .the parallel data is loaded simultaneously into the register. and transferred together to their respective outputs by the same clock pulse. with the stored data being available in parallel form. (left shifting) to the right. one bit at a time in either a left or right direction under clock control.Shift Registers are used for data storage or data movement and are used in calculators or computers to store data such as two binary numbers before they are added together. (rotation) or both left and right shifting within the same register thereby making it bidirectional. Generally.the parallel data is loaded into the register simultaneously and is shifted out of the register serially one bit at a time under clock control. The logic "1" has now moved or been "shifted" one place along the register to the right as it is now at QA. . The truth table and following waveforms show the propagation of the logic "1" through the register from left to right as follows. Commonly available SIPO IC's include the standard 8-bit 74LS164 or the 74LS594.The operation is as follows. The second clock pulse will change the output of FFA to logic "0" and the output of FFB and QB HIGH to logic "1" as its input D has the logic "1" level on it from QA. If a logic "1" is connected to the DATA input pin of FFA then on the first clock pulse the output of FFA and therefore the resulting QA will be set HIGH to logic "1" with all the other outputs still remaining LOW at logic "0". Lets assume that all the flip-flops (FFA to FFD) have just been RESET (CLEAR input) and that all the outputs QA to QD are at logic level "0" i. Basic Movement of Data through a Shift Register Clock Pulse No 0 1 2 3 4 5 QA 0 1 0 0 0 0 QB 0 0 1 0 0 0 QC 0 0 0 1 0 0 QD 0 0 0 0 1 0 Note that after the fourth clock pulse has ended the 4-bits of data (0-0-0-1) are stored in the register and will remain there provided clocking of the register has stopped. Then the data has been converted from a serial data input signal to a parallel data output. In practice the input data to the register may consist of various combinations of logic "1" and "0". no parallel data output. When the third clock pulse arrives this logic "1" value moves to the output of FFC (QC) and so on until the arrival of the fifth clock pulse which sets all the outputs QA to QD back again to logic level "0" because the input to FFA has remained constant at logic level "0". and this is shown in the following table until the complete data value of 0-0-0-1 is stored in the register.e. Assume now that the DATA input pin of FFA has returned LOW again to logic "0" giving us one data pulse or 0-1-0. The effect of each clock pulse is to shift the data contents of each stage one place to the right. This data value can now be read directly from the outputs of QA to QD. it can be used to multiplex many different input lines into a single serial DATA stream which can be sent directly to a computer or transmitted over a communications line. Since there is only one output. 8. 4. this time the data is allowed to flow straight through the register and out of the other end. The logic circuit diagram below shows a generalized serial-in serial-out shift register. Well this type of Shift Register also acts as a temporary storage device or as a time delay device for the data. The data is then read out sequentially in the normal shift-right mode from the register at Q representing the data present at PA to PD. 4-bit Serial-in to Serial-out Shift Register You may think what's the point of a SISO shift register if the output data is exactly the same as the input data. hence the name Serial-in to Serial-Out Shift Register or SISO. the serial output (SO) which is taken from the output of the right hand flip-flop and the sequencing clock signal (Clk). except were before the data was read directly in a parallel form from the outputs QA to QD. Parallel-in to Serial-out (PISO) The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to parallel-out one above. the serial input (SI) which determines what enters the left hand flip-flop. all the data bits enter their inputs simultaneously. but four clock pulses are required to unload the data. This data is outputted one bit at a time on each clock cycle in a serial format. with the amount of time delay being controlled by the number of stages in the register. 16 etc or by varying the application of the clock pulses. 4-bit Parallel-in to Serial-out Shift Register As this type of shift register converts parallel data. such as an 8-bit data word into serial format. . It is important to note that with this system a clock pulse is not required to parallel load the register as it is already present. The data is loaded into the register in a parallel format i. Commonly available IC's include the 74HC166 8-bit Parallel-in/Serial-out Shift Registers.Serial-in to Serial-out (SISO) This shift register is very similar to the SIPO above. the DATA leaves the shift register one bit at a time in a serial pattern. The SISO shift register is one of the simplest of the four configurations as it has only three connections. to the parallel input pins PA to PD of the register.e. Commonly available IC's include the 74HC595 8-bit Serial-in/Serial-out Shift Register all with 3-state outputs. These devices can perform any combination of parallel and serial input to output operations but require additional inputs to specify desired function and to preload and reset the device.Parallel-in to Parallel-out (PIPO) The final mode of operation is the Parallel-in to Parallel-out Shift Register. Then one clock pulse loads and unloads the register. 74LS195 or the CMOS 4035 are available as a 4-bit multi-function devices that can be used in either serial-to-serial. parallel-to-serial. This arrangement for parallel loading and unloading is shown below. Similar to the Serial-in to Serial-out shift register. high speed bi-directional "universal" type Shift Registers such as the TTL 74LS194. in this type of register there are no interconnections between the individual flip-flops since no serial shifting of the data is required. serial-to-parallel. Also. The data is presented in a parallel format to the p arallel input pins PA to PD and then transferred together directly to their respective output pins QA to QA by the same clock pulse. with the amount of time delay being varied by the frequency of the clock pulses. the parallel output (PO) and the sequencing clock signal (Clk). 4-bit Parallel-in to Parallel-out Shift Register The PIPO shift register is the simplest of the four configurations as it has only three connections. the parallel input (PI) which determines what enters the flip-flop. right shifting. Universal Shift Register Today. this type of register also acts as a temporary storage device or as a time delay device. hence the name "Universal". This type of register also acts as a temporary storage device or as a time delay device similar to the SISO configuration above. 4-bit Universal Shift Register 74LS194 . left shifting. and as a parallel-to-parallel multifunction data register. PIPO. But what if we were to connect the output of this shift register back to its input so that the output from the last flip-flop. This then produces another type of sequential logic circuit called a Ring Counter that are used as decade counters and dividers. Then by looping the output back to the input. Shift registers are identified as SIPO. is preset so that exactly one data bit in the register is set to logic "1" with all the other bits reset to "0". The Ring Counter In the previous Shift Register tutorial we saw that if we apply a serial data signal to the input of a serial-in to serial-out shift register. QD becomes the input of the first flip-flop. we will look at what happens when the output of the last flip-flop in a shift register is connected directly back to the input of the first flip-flop producing a closed loop circuit that constantly recirculates the data around the loop.Universal shift registers are very useful digital devices. PISO. SISO. In the next tutorial about Sequential Logic Circuits. Universal shift registers are frequently used in arithmetic operations to shift data to the left or right for multiplication or division. we can convert a standard shift register into a ring counter. DA. 4-bit Ring Counter The synchronous Ring Counter example above. Summary of Shift Registers Then to summarise. The data bits can be loaded one bit at a time in a series input (SI) configuration or be loaded simultaneously in a parallel configuration (PI). the same sequence of data will exit from the last flip-flip in the register chain after a preset number of clock cycles thereby acting as a sort of time delay circuit to the original signal. The output from each flip-Flop is connected to the D input of the flip-flop at its right. Each clock pulse shifts the contents of the register one bit position to either the left or the right. Shift registers hold the data in their memory which is moved or "shifted" to their required positions on each clock pulse. and this is the principal operation of a Ring Counter. a "CLEAR" signal is firstly applied to all the flip-flops together in order to "RESET" their . delay information such as the SISO or PIPO configuration modes or transfer data from one point to another in either a serial or parallel format. A simple Shift Register can be made using only D-type flip-Flops. To achieve this. Consider the circuit below. They can be configured to respond to operations that require some form of temporary memory. Data may be removed from the register one bit at a time for a series output (SO) or removed all at the same time from a parallel output (PO). One application of shift registers is converting between serial and parallel data. and universal shift registers. We would then have a closed loop circuit that "recirculates" the DATA around a continuous loop for every state of its sequence. one flip-Flop for each data bit. is another shift register with feedback exactly the same as the standard Ring Counter above. only four of the possible sixteen states are used. But in order to cycle the data correctly around the counter we must first "load" the counter with a suitable data pattern as all logic "0"'s or all logic "1"'s outputted at each clock cycle would make the ring counter invalid. as in our example above. except that this time the inverted output Q of the last flip-flop is now connected back to the input D of the first flip-flop as shown below. Johnson Ring Counter The Johnson Ring Counter or "Twisted Ring Counters". a mod-8 ring counter requires eight flip-flops and a mod-16 ring counter would require sixteen flip-flops. However. the effect of the movement of the data bit from left to right through a ring counter can be presented graphically as follows along with its timing diagram: Rotational Movement of a Ring Counter Since the ring counter example shown above has four distinct states. making ring counters very inefficient in terms of their output state usage. A "mod-n" ring counter will require "n" number of flip-flops connected together to circulate a single data bit providing "n" different output states. This then places a single logic "1" value into the circuit of the ring counter . it is also known as a "modulo-4" or "mod-4" counter with each flip-flop output having a frequency value equal to one-fourth or a quarter (1/4) that of the main clock frequency. For example. The main advantage of this type of ring counter is that it only needs half the number of flip-flops . On each successive clock pulse. This type of data movement is called "rotation".outputs to a logic "0" level and then a "PRESET" pulse is applied to the input of the first flip-flop (FFA) before the clock pulses are applied. the counter circulates the same data bit between the four flip-flops over and over again around the "ring" every fourth clock cycle. The "MODULO" or "MODULUS" of a counter is the number of states the counter counts or sequences through before repeating itself and a ring counter can be made to output any modulo number. and like the previous shift register. "0001". 120 degree phase shift square wave generator by connecting to the data outputs at A. "0010"(2). B and NOT-B. ring counters can also be used to detect or recognise various patterns or number values within a set of data. and this is shown below.compared to the standard ring counter then its modulo number is halved. "1000"(8) and repeat. For example. The standard 5-stage Johnson counter such as the commonly available CD4017 is generally used as a synchronous decade counter/divider circuit. A 4-bit Johnson ring counter passes blocks of four logic "0" and then four logic "1" thereby producing an 8-bit pattern. "1111". . A 3-stage Johnson Ring Counter can also be used as a 3-phase. The smaller 2-stage circuit is also called a "Quadrature" (sine/cosine) Oscillator/Generator and is used to produce four individual outputs that are each "phase shifted" by 90 degrees with respect to each other. Instead of counting through a fixed set of patterns like the normal ring counter such as for a 4-bit counter. "1100". "0111". 3 or 4-stage Johnson ring counters can also be used to divide the frequency of the clock signal by varying their feedback connections and divide-by-3 or divide-by-5 outputs are also available. So a "n-stage" Johnson counter will circulate a single data bit giving sequence of 2n different states and can therefore be considered as a "mod-2n counter". Truth Table for a 4-bit Johnson Ring Counter Clock Pulse No 0 1 2 3 4 5 6 7 FFA 0 1 1 1 1 0 0 0 FFB 0 0 1 1 1 1 0 0 FFC 0 0 0 1 1 1 1 0 FFD 0 0 0 0 1 1 1 1 As well as counting or rotating data around a continuous loop. "0000" and this is demonstrated in the following table below. "1000". the Johnson counter counts up and then down as the initial logic "1" passes through it to the right replacing the preceding logic "0". Standard 2. By connecting simple logic gates such as the AND or the OR gates to the outputs of the flip-flops the circuit can be made to detect a set number or value. 4-bit Johnson Ring Counter This inversion of Q before it is fed back to input D causes the counter to "count" in a different way. "0100"(4). "1110". "0011". "0001"(1). As the inverted output Q is connected to the input D this 8-bit pattern continually repeats. Stepper Motor Control . A to D are phase shifted by 90 degrees with regards to each other. they can be used with additional circuitry. to drive a 2-phase full-step stepper motor for position control or the ability to rotate a motor to a particular location as shown below. Count Sequence As the four outputs.2-bit Quadrature Generator Output QA+QB QA+QB QA+QB Q A+Q B A 1 0 0 0 B 0 1 0 0 C 0 0 1 0 D 0 0 0 1 2-bit Quadrature Oscillator. . As this section is only intended to give the reader a basic understanding of Johnson Ring Counters and its applications. other good websites explain in more detail the types and drive requirements of stepper motors. Johnson Ring Counters are available in standard TTL or CMOS IC form. divide-by-8 Johnson counter with 8 active HIGH decoded outputs.2-phase (unipolar) Full-Step Stepper Motor Circuit The speed of rotation of the Stepper Motor will depend mainly upon the clock frequency and additional circuitry would be require to drive the "power" requirements of the motor. decade Johnson ring counter with 10 active HIGH decoded outputs or the CD4022 4-stage. such as the CD4017 5-Stage.